diff --git a/CleanSpec.mk b/CleanSpec.mk new file mode 100644 index 00000000000..039f955d2ba --- /dev/null +++ b/CleanSpec.mk @@ -0,0 +1,51 @@ +# Copyright (C) 2018 The Android Open Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +# If you don't need to do a full clean build but would like to touch +# a file or delete some intermediate files, add a clean step to the end +# of the list. These steps will only be run once, if they haven't been +# run before. +# +# E.g.: +# $(call add-clean-step, touch -c external/sqlite/sqlite3.h) +# $(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/STATIC_LIBRARIES/libz_intermediates) +# +# Always use "touch -c" and "rm -f" or "rm -rf" to gracefully deal with +# files that are missing or have been moved. +# +# Use $(PRODUCT_OUT) to get to the "out/target/product/blah/" directory. +# Use $(OUT_DIR) to refer to the "out" directory. +# +# If you need to re-do something that's already mentioned, just copy +# the command and add it to the bottom of the list. E.g., if a change +# that you made last week required touching a file and a change you +# made today requires touching the same file, just copy the old +# touch step and add it to the end of the list. +# +# ************************************************ +# NEWER CLEAN STEPS MUST BE AT THE END OF THE LIST +# ************************************************ + +# For example: +#$(call add-clean-step, rm -rf $(OUT_DIR)/target/common/obj/APPS/AndroidTests_intermediates) +#$(call add-clean-step, rm -rf $(OUT_DIR)/target/common/obj/JAVA_LIBRARIES/core_intermediates) +#$(call add-clean-step, find $(OUT_DIR) -type f -name "IGTalkSession*" -print0 | xargs -0 rm -f) +#$(call add-clean-step, rm -rf $(PRODUCT_OUT)/data/*) + +$(call add-clean-step, rm -rf $(TARGET_OUT_INTERMEDIATES)/UBOOT_OBJ) + +# ************************************************ +# NEWER CLEAN STEPS MUST BE AT THE END OF THE LIST +# ************************************************ diff --git a/Kconfig b/Kconfig index 43540614ce6..a9343aca487 100644 --- a/Kconfig +++ b/Kconfig @@ -59,6 +59,13 @@ config CC_OPTIMIZE_FOR_SIZE This option is enabled by default for U-Boot. +config XEN + bool "Select U-Boot be run as a bootloader for XEN Virtual Machine" + default n + help + Enabling this option will make U-Boot be run as a bootloader + for XEN Virtual Machine. + config DISTRO_DEFAULTS bool "Select defaults suitable for booting general purpose Linux distributions" default y if ARCH_SUNXI || TEGRA diff --git a/Makefile b/Makefile index 6b2aac6713c..225fa6828cb 100644 --- a/Makefile +++ b/Makefile @@ -678,6 +678,7 @@ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/ libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/ libs-y += drivers/serial/ +libs-y += drivers/usb/cdns3/ libs-y += drivers/usb/dwc3/ libs-y += drivers/usb/common/ libs-y += drivers/usb/emul/ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c52ff025a2..d7c3eefba67 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -602,11 +602,21 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. -config ARCH_MX8M +config ARCH_IMX8 + bool "Support NXP i.MX8 platform" + select ARM64 + select DM + select OF_CONTROL + +config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 + select SYS_FSL_HAS_SEC if SECURE_BOOT + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE select DM select SUPPORT_SPL + select IMX_SEC_INIT if HAS_CAAM config ARCH_MX23 bool "NXP i.MX23 family" @@ -626,10 +636,14 @@ config ARCH_MX28 select SUPPORT_SPL config ARCH_MX7ULP - bool "NXP MX7ULP" - select CPU_V7 + bool "NXP MX7ULP" + select CPU_V7 + select SYS_FSL_HAS_SEC if SECURE_BOOT + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE select ROM_UNIFIED_SECTIONS imply MXC_GPIO + select IMX_SEC_INIT if HAS_CAAM config ARCH_MX7 bool "Freescale MX7" @@ -639,6 +653,7 @@ config ARCH_MX7 select SYS_FSL_SEC_LE select BOARD_EARLY_INIT_F select ARCH_MISC_INIT + select IMX_SEC_INIT if HAS_CAAM imply MXC_GPIO config ARCH_MX6 @@ -647,6 +662,7 @@ config ARCH_MX6 select SYS_FSL_HAS_SEC if SECURE_BOOT select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE + select IMX_SEC_INIT if HAS_CAAM select SYS_THUMB_BUILD if SPL imply MXC_GPIO @@ -1232,7 +1248,9 @@ source "arch/arm/mach-imx/mx7/Kconfig" source "arch/arm/mach-imx/mx7ulp/Kconfig" -source "arch/arm/mach-imx/mx8m/Kconfig" +source "arch/arm/mach-imx/imx8/Kconfig" + +source "arch/arm/mach-imx/imx8m/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5881fdc8e28..56a0623ef44 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -18,7 +18,7 @@ arch-$(CONFIG_CPU_ARM1136) =-march=armv5 arch-$(CONFIG_CPU_ARM1176) =-march=armv5t arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7, -march=armv5)) -arch-$(CONFIG_ARM64) =-march=armv8-a +arch-$(CONFIG_ARM64) =-march=armv8-a -mgeneral-regs-only # On Tegra systems we must build SPL for the armv4 core on the device # but otherwise we can use the value in CONFIG_SYS_ARM_ARCH @@ -95,11 +95,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8)) libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8 imx8m vf610)) libs-y += arch/arm/mach-imx/ endif endif diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 9c213b897cd..2887a40ab64 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -68,8 +68,7 @@ endif checkgcc6: @if test "$(call cc-name)" = "gcc" -a \ "$(call cc-version)" -lt "0600"; then \ - echo '*** Your GCC is older than 6.0 and is not supported'; \ - false; \ + echo '*** Your GCC is older than 6.0 and will not be supported'; \ fi @@ -154,6 +153,10 @@ ifdef CONFIG_EFI_LOADER OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel endif +ifdef CONFIG_IMX_M4_BIND +OBJCOPYFLAGS += -j .firmware_image +endif + ifneq ($(CONFIG_IMX_CONFIG),) ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index b552e4382cd..8a244a1820f 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -5,7 +5,7 @@ * on behalf of DENX Software Engineering GmbH * * Based on code from LTIB: - * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 3a0e129d2e6..ae218a585b5 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -94,7 +94,8 @@ config PSCI_RESET !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ !TARGET_LS2081ARDB && \ - !ARCH_UNIPHIER && !TARGET_S32V234EVB + !ARCH_UNIPHIER && !TARGET_S32V234EVB && \ + !ARCH_IMX8M help Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 12495474360..0bde2c22aee 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o +obj-$(CONFIG_XEN) += xen/ diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index 0d1b0c49930..7095a322ea3 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -39,6 +39,14 @@ SECTIONS *(.data*) } >.sram +#ifdef CONFIG_RECOVER_SPL_DATA_SECTION + .data_save : { + *(.__data_save_start) + . = SIZEOF(.data); + *(.__data_save_end) + } >.sram +#endif + .u_boot_list : { . = ALIGN(8); KEEP(*(SORT(.u_boot_list*))); diff --git a/arch/arm/cpu/armv8/xen/Makefile b/arch/arm/cpu/armv8/xen/Makefile new file mode 100644 index 00000000000..c5018095596 --- /dev/null +++ b/arch/arm/cpu/armv8/xen/Makefile @@ -0,0 +1 @@ +obj-y += hypercall.o print.o diff --git a/arch/arm/cpu/armv8/xen/hypercall.S b/arch/arm/cpu/armv8/xen/hypercall.S new file mode 100644 index 00000000000..4d800d2aa00 --- /dev/null +++ b/arch/arm/cpu/armv8/xen/hypercall.S @@ -0,0 +1,33 @@ +/* + * Copyright 2018 NXP + + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +.globl HYPERVISOR_console_io; +.globl HYPERVISOR_event_channel_op; +.globl HYPERVISOR_hvm_op; +.globl HYPERVISOR_sched_op; + +.align 4; +HYPERVISOR_console_io: + mov x16, __HYPERVISOR_console_io; + hvc 0xEA1; + ret; + +HYPERVISOR_event_channel_op: + mov x16, __HYPERVISOR_event_channel_op; + hvc 0xEA1; + ret; + +HYPERVISOR_hvm_op: + mov x16, __HYPERVISOR_hvm_op; + hvc 0xEA1; + ret; + +HYPERVISOR_sched_op: + mov x16, __HYPERVISOR_sched_op; + hvc 0xEA1; + ret; diff --git a/arch/arm/cpu/armv8/xen/print.c b/arch/arm/cpu/armv8/xen/print.c new file mode 100644 index 00000000000..5194d3661af --- /dev/null +++ b/arch/arm/cpu/armv8/xen/print.c @@ -0,0 +1,29 @@ +/* + * Copyright 2018 NXP + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * To non privileged domain, need CONFIG_VERBOSE_DEBUG in XEN to + * get output. + */ +void xenprintf(const char *buf) +{ + (void)HYPERVISOR_console_io(CONSOLEIO_write, strlen(buf), buf); + return; +} + +void xenprintc(const char c) +{ + (void)HYPERVISOR_console_io(CONSOLEIO_write, 1, &c); + return; +} diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 37d4c605aca..38defaedbff 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -172,6 +172,22 @@ SECTIONS *(.__image_copy_end) } +#ifdef CONFIG_IMX_M4_BIND + .firmware_image_start : { + *(.__firmware_image_start) + } + + .firmware_image : { + KEEP(*(.firmware_image)) + } + + .firmware_image_end : { + *(.__firmware_image_end) + } + + . = ALIGN(4); +#endif + .rel_dyn_start : { *(.__rel_dyn_start) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 20a4c37d48a..c841df051da 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -382,17 +382,58 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb -dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ +dtb-$(CONFIG_MX6) += imx6ul-14x14-ddr3-arm2.dtb \ + imx6ul-14x14-ddr3-arm2-emmc.dtb \ + imx6ul-14x14-ddr3-arm2-gpmi-weim.dtb \ + imx6ul-14x14-lpddr2-arm2.dtb \ + imx6ul-14x14-evk.dtb \ + imx6ul-14x14-evk-emmc.dtb \ + imx6ul-14x14-evk-gpmi-weim.dtb \ + imx6ul-9x9-evk.dtb \ + imx6ull-14x14-ddr3-arm2.dtb \ + imx6ull-14x14-ddr3-arm2-epdc.dtb \ + imx6ull-14x14-ddr3-arm2-emmc.dtb \ + imx6ull-14x14-ddr3-arm2-gpmi-weim.dtb \ + imx6ull-14x14-ddr3-arm2-tsc.dtb \ + imx6ull-9x9-evk.dtb \ + imx6ull-14x14-evk.dtb \ + imx6ull-14x14-evk-emmc.dtb \ + imx6ull-14x14-evk-gpmi-weim.dtb \ + imx6ulz-14x14-evk.dtb \ + imx6ulz-14x14-evk-emmc.dtb \ + imx6ulz-14x14-evk-gpmi-weim.dtb \ imx6sl-evk.dtb \ imx6sll-evk.dtb \ + imx6sll-lpddr2-arm2.dtb \ + imx6sll-lpddr3-arm2.dtb \ + imx6sll-lpddr3-arm2-ecspi.dtb \ + imx6dl-arm2.dtb \ imx6dl-icore.dtb \ imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ + imx6dl-sabreauto.dtb \ + imx6dl-sabreauto-ecspi.dtb \ + imx6dl-sabreauto-gpmi-weim.dtb \ + imx6dl-sabresd.dtb \ + imx6q-arm2.dtb \ + imx6q-pop-arm2.dtb \ imx6q-cm-fx6.dtb \ imx6q-icore.dtb \ imx6q-icore-mipi.dtb \ imx6q-icore-rqs.dtb \ imx6q-logicpd.dtb \ + imx6q-sabreauto.dtb \ + imx6q-sabreauto-ecspi.dtb \ + imx6q-sabreauto-gpmi-weim.dtb \ + imx6qp-sabreauto.dtb \ + imx6qp-sabreauto-ecspi.dtb \ + imx6qp-sabreauto-gpmi-weim.dtb \ + imx6sx-14x14-arm2.dtb \ + imx6sx-17x17-arm2.dtb \ + imx6sx-17x17-arm2-ecspi.dtb \ + imx6sx-17x17-arm2-gpmi-weim.dtb \ + imx6sx-19x19-arm2.dtb \ + imx6sx-19x19-arm2-gpmi-weim.dtb \ imx6sx-sabreauto.dtb \ imx6sx-sdb.dtb \ imx6ul-geam-kit.dtb \ @@ -401,9 +442,42 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6ul-opos6uldev.dtb dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ - imx7d-sdb.dtb - -dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb + imx7d-sdb.dtb \ + imx7d-sdb-epdc.dtb \ + imx7d-sdb-gpmi-weim.dtb \ + imx7d-sdb-qspi.dtb \ + imx7d-sdb-reva.dtb \ + imx7d-12x12-lpddr3-arm2.dtb \ + imx7d-12x12-lpddr3-arm2-ecspi.dtb \ + imx7d-12x12-lpddr3-arm2-qspi.dtb \ + imx7d-12x12-ddr3-arm2.dtb \ + imx7d-19x19-ddr3-arm2.dtb \ + imx7d-19x19-lpddr2-arm2.dtb \ + imx7d-19x19-lpddr3-arm2.dtb + +dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \ + imx7ulp-evk-emmc.dtb \ + imx7ulp-evk-qspi.dtb \ + imx7ulp-10x10-arm2.dtb \ + imx7ulp-14x14-arm2.dtb + +dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \ + fsl-imx8mq-ddr3l-arm2.dtb \ + fsl-imx8mq-ddr4-arm2.dtb \ + fsl-imx8mq-phanbell.dtb \ + fsl-imx8mm-ddr3l-val.dtb \ + fsl-imx8mm-ddr4-evk.dtb \ + fsl-imx8mm-ddr4-val.dtb \ + fsl-imx8mm-evk.dtb + +dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8dx-17x17-val.dtb \ + fsl-imx8qm-ddr4-arm2.dtb \ + fsl-imx8qm-lpddr4-arm2.dtb \ + fsl-imx8qm-mek.dtb \ + fsl-imx8qm-mek-xen.dtb \ + fsl-imx8qxp-17x17-val.dtb \ + fsl-imx8qxp-lpddr4-arm2.dtb \ + fsl-imx8qxp-mek.dtb dtb-$(CONFIG_RCAR_GEN3) += \ r8a7795-h3ulcb.dtb \ diff --git a/arch/arm/dts/fsl-imx8-ca35.dtsi b/arch/arm/dts/fsl-imx8-ca35.dtsi new file mode 100644 index 00000000000..4ebc159da73 --- /dev/null +++ b/arch/arm/dts/fsl-imx8-ca35.dtsi @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/{ + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 1 clusters having 4 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + operating-points = < + /* kHz uV */ + 1000000 1150000 + >; + clocks = <&clk IMX8QXP_A35_DIV>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0xc4000002>; + cpu_on = <0xc4000003>; + }; +}; diff --git a/arch/arm/dts/fsl-imx8-ca72.dtsi b/arch/arm/dts/fsl-imx8-ca72.dtsi new file mode 100644 index 00000000000..025db05f6c4 --- /dev/null +++ b/arch/arm/dts/fsl-imx8-ca72.dtsi @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0000000>; + entry-latency-us = <700>; + exit-latency-us = <250>; + min-residency-us = <1000>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1000000>; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + /* We have 2nd clusters having 2 Cortex-A72 cores */ + A72_0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72","arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A72_1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72","arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A72_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&A72_0>, <&A72_1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0xc4000002>; + cpu_on = <0xc4000003>; + }; +}; diff --git a/arch/arm/dts/fsl-imx8dx-17x17-val.dts b/arch/arm/dts/fsl-imx8dx-17x17-val.dts new file mode 100644 index 00000000000..ae9410ef3ea --- /dev/null +++ b/arch/arm/dts/fsl-imx8dx-17x17-val.dts @@ -0,0 +1,19 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-17x17-val.dts" + +/ { + model = "Freescale i.MX8DX 17x17 Validation board"; +}; diff --git a/arch/arm/dts/fsl-imx8mm-ddr3l-val.dts b/arch/arm/dts/fsl-imx8mm-ddr3l-val.dts new file mode 100644 index 00000000000..906ba19f346 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mm-ddr3l-val.dts @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018 NXP + */ + +/dts-v1/; + +#include "fsl-imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM DDR3L Validation board"; + compatible = "fsl,imx8mm-val", "fsl,imx8mm"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mm-val { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; diff --git a/arch/arm/dts/fsl-imx8mm-ddr4-evk.dts b/arch/arm/dts/fsl-imx8mm-ddr4-evk.dts new file mode 100644 index 00000000000..1b2e9f92b27 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mm-ddr4-evk.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018 NXP + */ + +#include "fsl-imx8mm-evk.dts" + +/ { + model = "FSL i.MX8MM DDR4 EVK board"; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi0{ + status = "disabled"; +}; diff --git a/arch/arm/dts/fsl-imx8mm-ddr4-val.dts b/arch/arm/dts/fsl-imx8mm-ddr4-val.dts new file mode 100644 index 00000000000..ffe5d28b138 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mm-ddr4-val.dts @@ -0,0 +1,517 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM DDR4 Validation board"; + compatible = "fsl,imx8mm-val", "fsl,imx8mm"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-patch = &uart2; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mm-val { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart2: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + typec_ptn5110_1: ptn5110@50 { + compatible = "usb,tcpci"; + reg = <0x50>; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8 0x3802d0c8>; + max-snk-mv = <9000>; + max-snk-ma = <2000>; + op-snk-mw = <9000>; + max-snk-mw = <18000>; + port-type = "drp"; + default-role = "sink"; + }; + + typec_ptn5110_2: ptn5110@52 { + compatible = "usb,tcpci"; + reg = <0x52>; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8 0x3802d0c8>; + max-snk-mv = <9000>; + max-snk-ma = <2000>; + op-snk-mw = <9000>; + max-snk-mw = <18000>; + port-type = "drp"; + default-role = "sink"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-okay; + at803x,vddio-1p8v; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&typec_ptn5110_1>; +}; + +&usbotg2 { + status = "okay"; + extcon = <&typec_ptn5110_2>; +}; diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts b/arch/arm/dts/fsl-imx8mm-evk.dts new file mode 100644 index 00000000000..8c9cec0c5d1 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mm-evk.dts @@ -0,0 +1,524 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM EVK board"; + compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-patch = &uart2; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8mm-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart2: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + typec_ptn5110_1: ptn5110@50 { + compatible = "usb,tcpci"; + reg = <0x50>; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8 0x3802d0c8>; + max-snk-mv = <9000>; + max-snk-ma = <2000>; + op-snk-mw = <9000>; + max-snk-mw = <18000>; + port-type = "drp"; + default-role = "sink"; + }; + + typec_ptn5110_2: ptn5110@52 { + compatible = "usb,tcpci"; + reg = <0x52>; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8 0x3802d0c8>; + max-snk-mv = <9000>; + max-snk-ma = <2000>; + op-snk-mw = <9000>; + max-snk-mw = <18000>; + port-type = "drp"; + default-role = "sink"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-okay; + at803x,vddio-1p8v; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&typec_ptn5110_1>; +}; + +&usbotg2 { + status = "okay"; + extcon = <&typec_ptn5110_2>; +}; diff --git a/arch/arm/dts/fsl-imx8mm.dtsi b/arch/arm/dts/fsl-imx8mm.dtsi new file mode 100644 index 00000000000..41c8df1b2f4 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mm.dtsi @@ -0,0 +1,947 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8-ca53.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + compatible = "fsl,imx8mm"; + interrupt-parent = <&gpc>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + spi0 = &flexspi0; + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + cpus { + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x80000000>; + linux,cma-default; + }; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8000000>; + interrupt-parent = <&gic>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc_32k: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock@2 { + compatible = "fixed-clock"; + reg = <3>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock@3 { + compatible = "fixed-clock"; + reg = <4>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock@4 { + compatible = "fixed-clock"; + reg = <5>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock@5 { + compatible = "fixed-clock"; + reg = <6>; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + }; + + mipi_pd: gpc_power_domain@0 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <0>; + domain-name = "MIPI_PD"; + }; + + pcie0_pd: gpc_power_domain@1 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <1>; + domain-name = "PCIE0_PD"; + }; + + usb_otg1_pd: gpc_power_domain@2 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <2>; + domain-name = "USB_OTG1_PD"; + }; + + usb_otg2_pd: gpc_power_domain@3 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <3>; + domain-name = "USB_OTG2_PD"; + }; + + gpu_2d_pd: gpc_power_domain@4 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <4>; + domain-name = "GPU_2D_PD"; + }; + + gpu_mix_pd: gpc_power_domain@5 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <5>; + domain-name = "GPU_MIX_PD"; + }; + + vpu_mix_pd: gpc_power_domain@6 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <6>; + domain-name = "VPU_MIX_PD"; + }; + + disp_mix_pd: gpc_power_domain@7 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <7>; + domain-name = "DISP_MIX_PD"; + }; + + vpu_g1_pd: gpc_power_domain@8 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <8>; + domain-name = "VPU_G1_PD"; + }; + + vpu_g2_pd: gpc_power_domain@9 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <9>; + domain-name = "VPU_G2_PD"; + }; + + vpu_h1_pd: gpc_power_domain@10 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <10>; + domain-name = "VPU_H1_PD"; + }; + + gpio1: gpio@30200000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30200000 0x0 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30210000 0x0 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30220000 0x0 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30230000 0x0 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30240000 0x0 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x0 0x30260000 0x0 0x10000>; + interrupt = ; + little-endian; + u-boot,dm-pre-reloc; + #thermal-sensor-cells = <0>; + }; + + thermal-zones { + /* cpu thermal */ + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mm-iomuxc"; + reg = <0x0 0x30330000 0x0 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon"; + reg = <0x0 0x30340000 0x0 0x10000>; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus"; + reg = <0x0 0x30360000 0x0 0x10000>; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x0 0x30370000 0x0 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = , + ; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + }; + }; + + clk: clock-controller@30380000 { + compatible = "fsl,imx8mm-ccm"; + reg = <0x0 0x30380000 0x0 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + + src: src@30390000 { + compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; + reg = <0x0 0x30390000 0x0 0x10000>; + interrupts = ; + #reset-cells = <1>; + }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mm-gpc", "fsl,imx8mq-gpc", "syscon"; + reg = <0x0 0x303a0000 0x0 0x10000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + system_counter: timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x0 0x306a0000 0x0 0x10000>, /* system-counter-rd base */ + <0x0 0x306b0000 0x0 0x10000>, /* system-counter-cmp base */ + <0x0 0x306c0000 0x0 0x10000>; /* system-counter-ctrl base */ + clock-frequency = <8000000>; + interrupts = , + ; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx8mm-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30860000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gpc>; + clocks = <&clk IMX8MM_CLK_UART1_ROOT>, + <&clk IMX8MM_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx8mm-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30880000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gpc>; + clocks = <&clk IMX8MM_CLK_UART3_ROOT>, + <&clk IMX8MM_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mm-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30890000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gpc>; + clocks = <&clk IMX8MM_CLK_UART2_ROOT>, + <&clk IMX8MM_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a20000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a30000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a40000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a50000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; + status = "disabled"; + }; + + usbotg1: usb@32e40000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x32e40000 0x0 0x200>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS_SRC>, + <&clk IMX8MM_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>; + assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + usbmisc1: usbmisc@32e40200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x32e40200 0x0 0x200>; + }; + + usbotg2: usb@32e50000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x32e50000 0x0 0x200>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS_SRC>, + <&clk IMX8MM_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>; + assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + usbmisc2: usbmisc@32e50200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x32e50200 0x0 0x200>; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b40000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MM_CLK_USDHC1_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MM_CLK_USDHC1_DIV>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@30b50000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b50000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MM_CLK_USDHC2_ROOT>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b60000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MM_CLK_USDHC3_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + sai1: sai@30010000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30010000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI1_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0xff 0xff>; + status = "disabled"; + }; + + sai2: sai@30020000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30020000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI2_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@30030000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x0 0x30030000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI3_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai5: sai@30050000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x0 0x30050000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 24 0>, <&sdma2 9 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0xf 0xf>; + status = "disabled"; + }; + + sai6: sai@30060000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30060000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SAI6_IPG>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI6_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 24 0>, <&sdma2 11 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + status = "disabled"; + }; + + micfil: micfil@30080000 { + compatible = "fsl,imx9mq-micfil"; + reg = <0x0 0x30080000 0x0 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8MM_CLK_PDM_IPG>, + <&clk IMX8MM_CLK_PDM_ROOT>; + clock-names = "ipg_clk", "ipg_clk_app"; + dmas = <&sdma2 24 24 0>; + dma-names = "rx"; + status = "disabled"; + }; + + spdif1: spdif@30090000 { + compatible = "fsl,imx8mm-spdif", "fsl,imx8mq-spdif", "fsl,imx35-spdif"; + reg = <0x0 0x30090000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, /* core */ + <&clk IMX8MM_CLK_24M>, /* rxtx0 */ + <&clk IMX8MM_CLK_SPDIF1_DIV>, /* rxtx1 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, /* rxtx5 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MM_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sdma1: dma-controller@30bd0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x30bd0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, + <&clk IMX8MM_CLK_SDMA1_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + status = "okay"; + }; + + sdma2: dma-controller@302c0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x302c0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, + <&clk IMX8MM_CLK_SDMA2_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + status = "okay"; + }; + + sdma3: dma-controller@302b0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x302b0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, + <&clk IMX8MM_CLK_SDMA3_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + status = "okay"; + }; + + wdog1: wdog@30280000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x30280000 0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + wdog2: wdog@30290000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x30290000 0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; + status = "disabled"; + }; + + wdog3: wdog@302a0000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x302a0000 0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; + status = "disabled"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x0 0x30be0000 0x0 0x10000>; + interrupts = , + , + ; + clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET_TIMER_DIV>, + <&clk IMX8MM_CLK_ENET_REF_DIV>, + <&clk IMX8MM_CLK_ENET_PHY_REF_DIV>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI_SRC>, + <&clk IMX8MM_CLK_ENET_TIMER_SRC>, + <&clk IMX8MM_CLK_ENET_REF_SRC>, + <&clk IMX8MM_CLK_ENET_TIMER_DIV>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + stop-mode = <&gpr 0x10 3>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + flexspi0: flexspi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-flexspi"; + reg = <0x0 0x30bb0000 0x0 0x10000>, + <0x0 0x08000000 0x0 0x19ffffff>; + reg-names = "FlexSPI", "FlexSPI-memory"; + interrupts = ; + clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, + <&clk IMX8MM_CLK_QSPI_ROOT>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + lcdif: lcdif@32E00000 { + compatible = "fsl,imx8mm-lcdif", "fsl,imx28-lcdif"; + reg = <0x0 0x32e00000 0x0 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_DIV>; + clock-names = "pix"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_SRC>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rate = <594000000>; + interrupts = ; + max-res = <1920>, <1080>; + status = "disabled"; + + port@0 { + lcdif_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; + }; + + mipi_dsi_phy: dsi_phy@32e10300 { + compatible = "mixel,imx8mm-mipi-dsi-phy", + "mixel,imx8mq-mipi-dsi-phy"; + reg = <0x0 0x32e10300 0x0 0x100>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi_bridge: mipi_dsi_bridge@32E10000 { + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x32e10000 0x0 0x400>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_DSI_PHY_REF_DIV>, + <&clk IMX8MM_CLK_DSI_ESC_RX_DIV>, + <&clk IMX8MM_CLK_IPG_DSI_ESC_RX_ROOT>; + clock-names = "phy_ref", "rx_esc", "tx_esc"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_ESC_RX_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + assigned-clock-rates = <80000000>; + phys = <&mipi_dsi_phy>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + mipi_dsi: mipi_dsi@32E10000 { + compatible = "fsl,imx8mm-mipi-dsi_drm", "fsl,imx8mq-mipi-dsi_drm"; + clocks = <&clk IMX8MM_CLK_DSI_CORE_DIV>, + <&clk IMX8MM_CLK_DSI_PHY_REF_DIV>; + clock-names = "core", "phy_ref"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE_SRC>, + <&clk IMX8MM_CLK_DSI_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>; + src = <&src>; + mux-sel = <&gpr>; + phys = <&mipi_dsi_phy>; + phys-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge_in>; + }; + }; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + }; + + vpu_h1: vpu_h1@38320000 { + compatible = "nxp,imx8mq-hantro-h1"; + reg = <0x0 0x38320000 0x0 0x10000>; + reg-names = "regs_hantro_h1"; + interrupts = ; + interrupt-names = "irq_hantro_h1"; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>; + clock-names = "clk_hantro_h1"; + power-domains = <&vpu_h1_pd>; + assigned-clocks = <&clk IMX8MM_CLK_VPU_H1_SRC>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>; + status = "disabled"; + }; + + vpu_g1: vpu_g1@38300000 { + compatible = "nxp,imx8mq-hantro"; + reg = <0x0 0x38300000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1_SRC>, <&clk IMX8MM_CLK_VPU_BUS_SRC>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_g1_pd>; + status = "disabled"; + }; + + vpu_g2: vpu_g2@38310000 { + compatible = "nxp,imx8mq-hantro"; + reg = <0x0 0x38310000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G2_SRC>, <&clk IMX8MM_CLK_VPU_BUS_SRC>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_g2_pd>; + status = "disabled"; + }; +}; + +&A53_0 { + operating-points = < + /* kHz uV */ + 1800000 1000000 + 1600000 900000 + 1200000 800000 + >; + clocks = <&clk IMX8MM_CLK_A53_DIV>, <&clk IMX8MM_CLK_A53_SRC>, + <&clk IMX8MM_ARM_PLL>, <&clk IMX8MM_ARM_PLL_OUT>, + <&clk IMX8MM_SYS_PLL1_800M>; + clock-names = "a53", "arm_a53_src", "arm_pll", + "arm_pll_out", "sys1_pll_800m"; + clock-latency = <61036>; + #cooling-cells = <2>; +}; diff --git a/arch/arm/dts/fsl-imx8mq-aiy.dts b/arch/arm/dts/fsl-imx8mq-aiy.dts new file mode 100644 index 00000000000..7453e302c7c --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-aiy.dts @@ -0,0 +1,758 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x40000000 0x00020000; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ AIY"; + compatible = "fsl,imx8mq-aiy", "fsl,imx8mq"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + wm8524: wm8524 { + compatible = "wlf,wm8524"; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + clock-names = "mclk"; + wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai2>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; + regulator-virtuals { + compatible = "simple-bus"; + + virt-buck1 { + compatible = "regulator-virtual"; + virtual-supply = "buck1"; + }; + virt-buck2 { + compatible = "regulator-virtual"; + virtual-supply = "buck2"; + }; + virt-buck3 { + compatible = "regulator-virtual"; + virtual-supply = "buck3"; + }; + virt-buck4 { + compatible = "regulator-virtual"; + virtual-supply = "buck4"; + }; + virt-buck5 { + compatible = "regulator-virtual"; + virtual-supply = "buck5"; + }; + virt-buck6 { + compatible = "regulator-virtual"; + virtual-supply = "buck6"; + }; + virt-buck7 { + compatible = "regulator-virtual"; + virtual-supply = "buck7"; + }; + virt-buck8 { + compatible = "regulator-virtual"; + virtual-supply = "buck8"; + }; + virt-ldo1 { + compatible = "regulator-virtual"; + virtual-supply = "ldo1"; + }; + virt-ldo2 { + compatible = "regulator-virtual"; + virtual-supply = "ldo2"; + }; + virt-ldo3 { + compatible = "regulator-virtual"; + virtual-supply = "ldo3"; + }; + virt-ldo4 { + compatible = "regulator-virtual"; + virtual-supply = "ldo4"; + }; + virt-ldo5 { + compatible = "regulator-virtual"; + virtual-supply = "ldo5"; + }; + virt-ldo6 { + compatible = "regulator-virtual"; + virtual-supply = "ldo6"; + }; + virt-ldo7 { + compatible = "regulator-virtual"; + virtual-supply = "ldo7"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-evk { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16 + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16 + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x79 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x79 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 /*0x17059*/ + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + /* PMIC BD71837 PMIC_nINT GPIO1_IO12 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + bd71837,pmic-buck1-uses-i2c-dvs; + bd71837,pmic-buck1-dvs-voltage = <900000>, <850000>, <800000>; /* VDD_SOC: Run-Idle-Suspend */ + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + bd71837,pmic-buck3-uses-i2c-dvs; + bd71837,pmic-buck3-dvs-voltage = <1000000>, <0>, <0>; /* VDD_GPU: Run */ + bd71837,pmic-buck4-uses-i2c-dvs; + bd71837,pmic-buck4-dvs-voltage = <1000000>, <0>, <0>; /* VDD_VPU: Run */ + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + adv7535: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; /* PD pin is low */ + /* TODO: pin config & irq */ + video-mode = <34>; /* 1920x1080@30HZ */ + dsi-traffic-mode = <0>; + bpp = <24>; + status = "okay"; + port { + dsi_to_hdmi: endpoint { + remote-endpoint = <&mipi_dsi_ep>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&mipi_dsi { + reset = <&src>; + mux-sel = <&gpr>; /* lcdif or dcss */ + status = "okay"; + port { + mipi_dsi_ep: endpoint { + remote-endpoint = <&dsi_to_hdmi>; + }; + }; +}; + +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>, + <&clk IMX8MQ_AUDIO_PLL1>, + <&clk IMX8MQ_CLK_SAI2_PRE_DIV>, + <&clk IMX8MQ_CLK_SAI2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8mq-ddr3l-arm2-u-boot.dtsi b/arch/arm/dts/fsl-imx8mq-ddr3l-arm2-u-boot.dtsi new file mode 100644 index 00000000000..2af3ebbde62 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-ddr3l-arm2-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018 NXP + */ + +#include "fsl-imx8mq-u-boot.dtsi" \ No newline at end of file diff --git a/arch/arm/dts/fsl-imx8mq-ddr3l-arm2.dts b/arch/arm/dts/fsl-imx8mq-ddr3l-arm2.dts new file mode 100644 index 00000000000..857494fdf8d --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-ddr3l-arm2.dts @@ -0,0 +1,561 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ DDR3L ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + wm8524: wm8524 { + compatible = "wlf,wm8524"; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + clock-names = "mclk"; + wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai2>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-arm2 { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x7f + MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x7f + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x7f + MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x7f + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16 + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16 + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x79 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x79 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8mq-ddr4-arm2-u-boot.dtsi b/arch/arm/dts/fsl-imx8mq-ddr4-arm2-u-boot.dtsi new file mode 100644 index 00000000000..2af3ebbde62 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-ddr4-arm2-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018 NXP + */ + +#include "fsl-imx8mq-u-boot.dtsi" \ No newline at end of file diff --git a/arch/arm/dts/fsl-imx8mq-ddr4-arm2.dts b/arch/arm/dts/fsl-imx8mq-ddr4-arm2.dts new file mode 100644 index 00000000000..1fb63091c30 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-ddr4-arm2.dts @@ -0,0 +1,511 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ DDR4 ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + wm8524: wm8524 { + compatible = "wlf,wm8524"; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + clock-names = "mclk"; + wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai2>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-arm2 { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x7f + MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x7f + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x7f + MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x7f + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16 + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16 + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8mq-evk-u-boot.dtsi b/arch/arm/dts/fsl-imx8mq-evk-u-boot.dtsi new file mode 100644 index 00000000000..2af3ebbde62 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-evk-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018 NXP + */ + +#include "fsl-imx8mq-u-boot.dtsi" \ No newline at end of file diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts new file mode 100644 index 00000000000..6b713f98c09 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-evk.dts @@ -0,0 +1,617 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x40000000 0x00020000; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ EVK"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + wm8524: wm8524 { + compatible = "wlf,wm8524"; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + clock-names = "mclk"; + wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai2>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-evk { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x7f + MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x7f + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x7f + MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x7f + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16 + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16 + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x79 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x79 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + adv7535: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; /* PD pin is low */ + /* TODO: pin config & irq */ + video-mode = <34>; /* 1920x1080@30HZ */ + dsi-traffic-mode = <0>; + bpp = <24>; + status = "okay"; + port { + dsi_to_hdmi: endpoint { + remote-endpoint = <&mipi_dsi_ep>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&mipi_dsi { + reset = <&src>; + mux-sel = <&gpr>; /* lcdif or dcss */ + status = "okay"; + port { + mipi_dsi_ep: endpoint { + remote-endpoint = <&dsi_to_hdmi>; + }; + }; +}; + +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>, + <&clk IMX8MQ_AUDIO_PLL1>, + <&clk IMX8MQ_CLK_SAI2_PRE_DIV>, + <&clk IMX8MQ_CLK_SAI2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/fsl-imx8mq-phanbell-u-boot.dtsi new file mode 100644 index 00000000000..2af3ebbde62 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-phanbell-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018 NXP + */ + +#include "fsl-imx8mq-u-boot.dtsi" \ No newline at end of file diff --git a/arch/arm/dts/fsl-imx8mq-phanbell.dts b/arch/arm/dts/fsl-imx8mq-phanbell.dts new file mode 100644 index 00000000000..c40931f7bd7 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-phanbell.dts @@ -0,0 +1,746 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x40000000 0x00020000; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ Phanbell"; + compatible = "fsl,imx8mq-phanbell", "fsl,imx8mq"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + wm8524: wm8524 { + compatible = "wlf,wm8524"; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + clock-names = "mclk"; + wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai2>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; + regulator-virtuals { + compatible = "simple-bus"; + + virt-buck1 { + compatible = "regulator-virtual"; + virtual-supply = "buck1"; + }; + virt-buck2 { + compatible = "regulator-virtual"; + virtual-supply = "buck2"; + }; + virt-buck3 { + compatible = "regulator-virtual"; + virtual-supply = "buck3"; + }; + virt-buck4 { + compatible = "regulator-virtual"; + virtual-supply = "buck4"; + }; + virt-buck5 { + compatible = "regulator-virtual"; + virtual-supply = "buck5"; + }; + virt-buck6 { + compatible = "regulator-virtual"; + virtual-supply = "buck6"; + }; + virt-buck7 { + compatible = "regulator-virtual"; + virtual-supply = "buck7"; + }; + virt-buck8 { + compatible = "regulator-virtual"; + virtual-supply = "buck8"; + }; + virt-ldo1 { + compatible = "regulator-virtual"; + virtual-supply = "ldo1"; + }; + virt-ldo2 { + compatible = "regulator-virtual"; + virtual-supply = "ldo2"; + }; + virt-ldo3 { + compatible = "regulator-virtual"; + virtual-supply = "ldo3"; + }; + virt-ldo4 { + compatible = "regulator-virtual"; + virtual-supply = "ldo4"; + }; + virt-ldo5 { + compatible = "regulator-virtual"; + virtual-supply = "ldo5"; + }; + virt-ldo6 { + compatible = "regulator-virtual"; + virtual-supply = "ldo6"; + }; + virt-ldo7 { + compatible = "regulator-virtual"; + virtual-supply = "ldo7"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-evk { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16 + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16 + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x79 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x79 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 /*0x17059*/ + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + /* PMIC BD71837 PMIC_nINT GPIO1_IO12 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + bd71837,pmic-buck1-uses-i2c-dvs; + bd71837,pmic-buck1-dvs-voltage = <900000>, <850000>, <800000>; /* VDD_SOC: Run-Idle-Suspend */ + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + bd71837,pmic-buck3-uses-i2c-dvs; + bd71837,pmic-buck3-dvs-voltage = <1000000>, <0>, <0>; /* VDD_GPU: Run */ + bd71837,pmic-buck4-uses-i2c-dvs; + bd71837,pmic-buck4-dvs-voltage = <1000000>, <0>, <0>; /* VDD_VPU: Run */ + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + adv7535: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; /* PD pin is low */ + /* TODO: pin config & irq */ + video-mode = <34>; /* 1920x1080@30HZ */ + dsi-traffic-mode = <0>; + bpp = <24>; + status = "okay"; + port { + dsi_to_hdmi: endpoint { + remote-endpoint = <&mipi_dsi_ep>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "disabled"; +}; + +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&mipi_dsi { + reset = <&src>; + mux-sel = <&gpr>; /* lcdif or dcss */ + status = "okay"; + port { + mipi_dsi_ep: endpoint { + remote-endpoint = <&dsi_to_hdmi>; + }; + }; +}; + +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>, + <&clk IMX8MQ_AUDIO_PLL1>, + <&clk IMX8MQ_CLK_SAI2_PRE_DIV>, + <&clk IMX8MQ_CLK_SAI2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8mq-u-boot.dtsi b/arch/arm/dts/fsl-imx8mq-u-boot.dtsi new file mode 100644 index 00000000000..bf08a0f847b --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018 NXP + */ + +&usb3_0 { + compatible = "simple-bus"; +}; + +&usb_dwc3_0 { + compatible = "fsl, imx8mq-dwc3"; +}; + +&usb3_1 { + compatible = "simple-bus"; +}; + +&usb_dwc3_1 { + compatible = "fsl, imx8mq-dwc3"; +}; diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi index 814a1b7df4c..bf32df63eea 100644 --- a/arch/arm/dts/fsl-imx8mq.dtsi +++ b/arch/arm/dts/fsl-imx8mq.dtsi @@ -29,8 +29,10 @@ aliases { ethernet0 = &fec1; - mmc0 = &usdhc1; - mmc1 = &usdhc2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -40,6 +42,8 @@ i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; + usb0 = &usb3_0; + usb1 = &usb3_1; }; memory@40000000 { @@ -47,6 +51,21 @@ reg = <0x00000000 0x40000000 0 0xc0000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x80000000>; + linux,cma-default; + }; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ @@ -59,18 +78,75 @@ timer { compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ clock-frequency = <8333333>; interrupt-parent = <&gic>; }; + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc_25m: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc_25m"; + }; + + osc_27m: clock@2 { + compatible = "fixed-clock"; + reg = <2>; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "osc_27m"; + }; + + clk_ext1: clock@3 { + compatible = "fixed-clock"; + reg = <3>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock@4 { + compatible = "fixed-clock"; + reg = <4>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock@5 { + compatible = "fixed-clock"; + reg = <5>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock@6 { + compatible = "fixed-clock"; + reg = <6>; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + }; + power: power-controller { compatible = "fsl,imx8mq-pm-domain"; num-domains = <11>; @@ -149,50 +225,50 @@ interrupt = ; little-endian; u-boot,dm-pre-reloc; - fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>; - fsl,tmu-calibration = <0x00000000 0x00000020 - 0x00000001 0x00000028 - 0x00000002 0x00000030 - 0x00000003 0x00000038 - 0x00000004 0x00000040 - 0x00000005 0x00000048 - 0x00000006 0x00000050 - 0x00000007 0x00000058 - 0x00000008 0x00000060 - 0x00000009 0x00000068 - 0x0000000a 0x00000070 - 0x0000000b 0x00000077 - - 0x00010000 0x00000057 - 0x00010001 0x0000005b - 0x00010002 0x0000005f - 0x00010003 0x00000063 - 0x00010004 0x00000067 - 0x00010005 0x0000006b - 0x00010006 0x0000006f - 0x00010007 0x00000073 - 0x00010008 0x00000077 - 0x00010009 0x0000007b - 0x0001000a 0x0000007f - - 0x00020000 0x00000002 - 0x00020001 0x0000000e - 0x00020002 0x0000001a - 0x00020003 0x00000026 - 0x00020004 0x00000032 - 0x00020005 0x0000003e - 0x00020006 0x0000004a - 0x00020007 0x00000056 - 0x00020008 0x00000062 - - 0x00030000 0x00000000 - 0x00030001 0x00000008 - 0x00030002 0x00000010 - 0x00030003 0x00000018 - 0x00030004 0x00000020 - 0x00030005 0x00000028 - 0x00030006 0x00000030 - 0x00030007 0x00000038>; + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; + fsl,tmu-calibration = <0x00000000 0x00000023 + 0x00000001 0x00000029 + 0x00000002 0x0000002f + 0x00000003 0x00000035 + 0x00000004 0x0000003d + 0x00000005 0x00000043 + 0x00000006 0x0000004b + 0x00000007 0x00000051 + 0x00000008 0x00000057 + 0x00000009 0x0000005f + 0x0000000a 0x00000067 + 0x0000000b 0x0000006f + + 0x00010000 0x0000001b + 0x00010001 0x00000023 + 0x00010002 0x0000002b + 0x00010003 0x00000033 + 0x00010004 0x0000003b + 0x00010005 0x00000043 + 0x00010006 0x0000004b + 0x00010007 0x00000055 + 0x00010008 0x0000005d + 0x00010009 0x00000067 + 0x0001000a 0x00000070 + + 0x00020000 0x00000017 + 0x00020001 0x00000023 + 0x00020002 0x0000002d + 0x00020003 0x00000037 + 0x00020004 0x00000041 + 0x00020005 0x0000004b + 0x00020006 0x00000057 + 0x00020007 0x00000063 + 0x00020008 0x0000006f + + 0x00030000 0x00000015 + 0x00030001 0x00000021 + 0x00030002 0x0000002d + 0x00030003 0x00000039 + 0x00030004 0x00000045 + 0x00030005 0x00000053 + 0x00030006 0x0000005f + 0x00030007 0x00000071>; #thermal-sensor-cells = <0>; }; @@ -209,7 +285,7 @@ type = "passive"; }; cpu_crit0: trip1 { - temperature = <125000>; + temperature = <95000>; hysteresis = <2000>; type = "critical"; }; @@ -225,6 +301,16 @@ }; }; + gpt1: gpt@302d0000 { + compatible = "fsl,imx8mq-gpt"; + reg = <0x0 0x302d0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_GPT1_ROOT>, + <&clk IMX8MQ_CLK_GPT1_ROOT>, + <&clk IMX8MQ_GPT_3M_CLK>; + clock-names = "ipg", "per", "osc_per"; + }; + lcdif: lcdif@30320000 { compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; reg = <0x0 0x30320000 0x0 0x10000>; @@ -239,6 +325,30 @@ status = "disabled"; }; + mipi_dsi: mipi_dsi@30A00000 { + compatible = "fsl,imx8mq-mipi-dsi"; + reg = <0x0 0x30a00000 0x0 0x10000>; /* DSI registers */ + interrupts = ; + clocks = <&clk IMX8MQ_CLK_DSI_CORE_DIV>, + <&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>, + <&clk IMX8MQ_CLK_DSI_DBI_DIV>, + <&clk IMX8MQ_CLK_DSI_AHB_DIV>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>; + clock-names = "core", "phy_ref", "dbi", "rxesc", "txesc"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>, + <&clk IMX8MQ_CLK_DSI_CORE_SRC>, + <&clk IMX8MQ_CLK_DSI_AHB_SRC>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rate = <594000000>, <266000000>, <80000000>; + phy-ref-clkfreq = <27000000>; + data-lanes-num = <4>; + max-data-rate = <800000000>; + power-domains = <&power 0>; + status = "disabled"; + }; + iomuxc: iomuxc@30330000 { compatible = "fsl,imx8mq-iomuxc"; reg = <0x0 0x30330000 0x0 0x10000>; @@ -261,12 +371,44 @@ interrupts = ; }; + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x0 0x30370000 0x0 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = , + ; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + }; + }; + clk: ccm@30380000 { compatible = "fsl,imx8mq-ccm"; reg = <0x0 0x30380000 0x0 0x10000>; interrupts = , ; #clock-cells = <1>; + clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + + src: src@30390000 { + compatible = "fsl,imx8mq-src", "fsl,imx51-src", "syscon"; + reg = <0x0 0x30390000 0x0 0x10000>; + interrupts = ; + #reset-cells = <1>; }; gpc: gpc@303a0000 { @@ -278,6 +420,180 @@ interrupt-parent = <&gic>; }; + system_counter_rd: system-counter-rd@306a0000 { + compatible = "fsl,imx8mq-system-counter-rd"; + reg = <0x0 0x306a0000 0x0 0x10000>; + status = "disabled"; + }; + + system_counter_cmp: system-counter-cmp@306b0000 { + compatible = "fsl,imx8mq-system-counter-cmp"; + reg = <0x0 0x306b0000 0x0 0x10000>; + status = "disabled"; + }; + + system_counter_ctrl: system-counter-ctrl@306c0000 { + compatible = "fsl,imx8mq-system-counter-ctrl"; + reg = <0x0 0x306c0000 0x0 0x10000>; + interrupts = , + ; + status = "disabled"; + }; + + spdif1: spdif@30810000 { + compatible = "fsl,imx8mq-spdif"; + reg = <0x0 0x30810000 0x0 0x10000>; + interrupts = ; + status = "disabled"; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30860000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, + <&clk IMX8MQ_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + interrupt-parent = <&gpc>; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30880000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, + <&clk IMX8MQ_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30890000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, + <&clk IMX8MQ_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdif2: spdif@308a0000 { + compatible = "fsl,imx8mq-spdif"; + reg = <0x0 0x308a0000 0x0 0x10000>; + interrupts = ; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30a60000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, + <&clk IMX8MQ_CLK_UART4_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mu: mu@30aa0000 { + compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; + reg = <0x0 0x30aa0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "mu"; + status = "disabled"; + }; + + usb3_phy0: phy@381f0040 { + compatible = "fsl,imx8mq-usb-phy"; + #phy-cells = <1>; + reg = <0x0 0x381f0040 0x0 0x40>; + clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; + clock-names = "usb_phy_root_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + usb3_0: usb@38100000 { + compatible = "fsl, imx8mq-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>, + <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + status = "disabled"; + + usb_dwc3_0: dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0x38100000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gpc>; + phys = <&usb3_phy0 0>, <&usb3_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + power-domains = <&power 2>; + snps,power-down-scale = <2>; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + }; + + usb3_phy1: phy@382f0040 { + compatible = "fsl,imx8mq-usb-phy"; + #phy-cells = <1>; + reg = <0x0 0x382f0040 0x0 0x40>; + clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; + clock-names = "usb_phy_root_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + usb3_1: usb@38200000 { + compatible = "fsl, imx8mq-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>; + clock-names = "usb2_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>, + <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + status = "disabled"; + + usb_dwc3_1: dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0x38200000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gpc>; + phys = <&usb3_phy1 0>, <&usb3_phy1 1>; + phy-names = "usb2-phy", "usb3-phy"; + power-domains = <&power 3>; + snps,power-down-scale = <2>; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + }; + usdhc1: usdhc@30b40000 { compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; reg = <0x0 0x30b40000 0x0 0x10000>; @@ -308,6 +624,125 @@ status = "disabled"; }; + sai1: sai@30010000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30010000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI1_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 24 0>, <&sdma2 9 24 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0xff 0xff>; + status = "disabled"; + }; + + sai6: sai@30030000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30030000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI6_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + status = "disabled"; + }; + + sai5: sai@30040000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30040000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI5_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0xf 0xf>; + status = "disabled"; + }; + + sai4: sai@30050000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30050000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI4_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0x0 0xf>; + status = "disabled"; + }; + + sai2: sai@308b0000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x308b0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI2_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@308c0000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x308c0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI3_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sdma1: sdma@30bd0000 { + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x30bd0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, + <&clk IMX8MQ_CLK_SDMA1_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + status = "okay"; + }; + + sdma2: sdma@302c0000 { + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x302c0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, + <&clk IMX8MQ_CLK_SDMA2_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + status = "okay"; + }; + fec1: ethernet@30be0000 { compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x0 0x30be0000 0x0 0x10000>; @@ -336,6 +771,21 @@ status = "disabled"; }; + gpu: gpu@38000000 { + compatible = "fsl,imx8mq-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0 0x40000>, <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = ; + interrupt-names = "irq_3d"; + clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, <&clk IMX8MQ_CLK_GPU_AXI_DIV>, <&clk IMX8MQ_CLK_GPU_AHB_DIV>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, <&clk IMX8MQ_CLK_GPU_AXI_SRC>, <&clk IMX8MQ_CLK_GPU_AHB_SRC>; + assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>; + power-domains = <&power 4>; + status = "disabled"; + }; + imx_ion { compatible = "fsl,mxc-ion"; fsl,heap-id = <0>; @@ -381,6 +831,21 @@ status = "disabled"; }; + vpu: vpu@38300000 { + compatible = "nxp,imx8mq-hantro"; + reg = <0x0 0x38300000 0x0 0x200000>; + reg-names = "regs_hantro"; + interrupts = , ; + interrupt-names = "irq_hantro_g1", "irq_hantro_g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro_g1", "clk_hantro_g2", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1_SRC>, <&clk IMX8MQ_CLK_VPU_G2_SRC>, <&clk IMX8MQ_CLK_VPU_BUS_SRC>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <600000000>, <800000000>; + power-domains = <&power 5>; + status = "disabled"; + }; + wdog1: wdog@30280000 { compatible = "fsl,imx21-wdt"; reg = <0 0x30280000 0 0x10000>; @@ -422,8 +887,75 @@ clock-names = "qspi_en", "qspi"; status = "disabled"; }; + + pcie0: pcie@0x33800000 { + compatible = "fsl,imx8mq-pcie", "snps,dw-pcie"; + reg = <0x0 0x33800000 0x0 0x400000>, <0x0 0x1ff00000 0x0 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX_CG>, + <&clk IMX8MQ_CLK_PCIE1_PHY_CG>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; + ctrl-id = <0>; + power-domains = <&power 1>; + status = "disabled"; + }; + + pcie1: pcie@0x33c00000 { + compatible = "fsl,imx8mq-pcie", "snps,dw-pcie"; + reg = <0x0 0x33c00000 0x0 0x400000>, <0x0 0x27f00000 0x0 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x20000000 0x0 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX_CG>, + <&clk IMX8MQ_CLK_PCIE2_PHY_CG>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; + ctrl-id = <1>; + power-domains = <&power 10>; + status = "disabled"; + }; }; &A53_0 { + operating-points = < + /* kHz uV */ + 1200000 900000 + 800000 900000 + >; + clocks = <&clk IMX8MQ_CLK_A53_DIV>, <&clk IMX8MQ_CLK_A53_SRC>, + <&clk IMX8MQ_ARM_PLL>, <&clk IMX8MQ_ARM_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>; + clock-names = "a53", "arm_a53_src", "arm_pll", + "arm_pll_out", "sys1_pll_800m"; + clock-latency = <61036>; #cooling-cells = <2>; }; diff --git a/arch/arm/dts/fsl-imx8qm-ddr4-arm2.dts b/arch/arm/dts/fsl-imx8qm-ddr4-arm2.dts new file mode 100644 index 00000000000..2f5b453de5b --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-ddr4-arm2.dts @@ -0,0 +1,420 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x80000000 0x00020000; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM ARM2"; + compatible = "fsl,imx8qm-arm2", "fsl,imx8qm"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8qm-arm2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000048 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000048 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000048 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000048 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000048 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000048 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000048 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000048 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000048 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000048 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0x06000020 + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x06000020 + /* + * Change the default alt function from SCL/SDA to others, + * to avoid select input conflict with GPT0 + */ + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0700004c + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0700004c + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0700004c + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0700004c + >; + }; + + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c + SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c + SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c + SC_P_SPI0_CS0_DMA_SPI0_CS0 0x0600004c + SC_P_SPI0_CS1_DMA_SPI0_CS1 0x0600004c + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>,<&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>,<&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; + +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + it6263-0@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + it6263-1@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <4000000>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + status = "okay"; +}; + diff --git a/arch/arm/dts/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm/dts/fsl-imx8qm-lpddr4-arm2.dts new file mode 100644 index 00000000000..2c06ff04d30 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-lpddr4-arm2.dts @@ -0,0 +1,501 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x80000000 0x00020000; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM ARM2"; + compatible = "fsl,imx8qm-arm2", "fsl,imx8qm"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8qm-arm2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0x06000020 + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x06000020 + /* + * Change the default alt function from SCL/SDA to others, + * to avoid select input conflict with GPT0 + */ + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0700004c + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0700004c + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0700004c + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0700004c + >; + }; + + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c + SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c + SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c + SC_P_SPI0_CS0_DMA_SPI0_CS0 0x0600004c + SC_P_SPI0_CS1_DMA_SPI0_CS1 0x0600004c + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + it6263-0@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + it6263-1@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <4000000>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + status = "okay"; +}; + diff --git a/arch/arm/dts/fsl-imx8qm-mek-auto.dts b/arch/arm/dts/fsl-imx8qm-mek-auto.dts new file mode 100644 index 00000000000..011dd49bec4 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek-auto.dts @@ -0,0 +1,76 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qm-mek.dts" + +/ { + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200 androidboot.console=ttyLP0 androidboot.xen_boot=default"; + stdout-path = &lpuart0; + }; + + config { + load-environment = <0>; + }; +}; + +&gpio2 { + status = "disabled"; +}; + +&gpio4 { + status = "disabled"; +}; + +&gpio5 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&usbotg1 { + status = "disabled"; +}; + +&usb2 { + status = "disabled"; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&i2c1_lvds1 { + status = "disabled"; +}; + +&lpspi0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/fsl-imx8qm-mek-xen.dts b/arch/arm/dts/fsl-imx8qm-mek-xen.dts new file mode 100644 index 00000000000..17c333dfd4d --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek-xen.dts @@ -0,0 +1,76 @@ +/* + * Copyright 2018-2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +/ { + chosen { + bootargs = "console=hvc0 earlycon=hvc0 androidboot.console=hvc0 androidboot.xen_boot=xen androidboot.android_dt_dir=/proc/device-tree/passthrough/firmware/android/"; + stdout-path = &lpuart0; + }; +}; + +&usdhc2 { + status = "disabled"; +}; + +&gpio2 { + status = "disabled"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "disabled"; +}; + +&usb2 { + status = "disabled"; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&i2c0 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&i2c1_lvds1 { + status = "disabled"; +}; + +&lpspi0 { + status = "disabled"; +}; + +&lpuart0 { + compatible = "xen,xen"; + /delete-property/ power-domains; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts b/arch/arm/dts/fsl-imx8qm-mek.dts new file mode 100644 index 00000000000..8d391b178dc --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek.dts @@ -0,0 +1,425 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8qm-mek { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x06000021 + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x06000021 + SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x06000021 + SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x06000021 + SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x06000021 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000020 + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000020 + >; + }; + + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c + SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c + SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c + SC_P_SPI0_CS0_DMA_SPI0_CS0 0x0600004c + SC_P_SPI0_CS1_DMA_SPI0_CS1 0x0600004c + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_txc_dly; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + status = "okay"; + +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + it6263-0@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + it6263-1@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <4000000>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi new file mode 100644 index 00000000000..626985a1b9e --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm.dtsi @@ -0,0 +1,2729 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "fsl-imx8-ca53.dtsi" +#include "fsl-imx8-ca72.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + compatible = "fsl,imx8qm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + dpu0 = &dpu1; + dpu1 = &dpu2; + ethernet0 = &fec1; + ethernet1 = &fec2; + ldb0 = &ldb1; + ldb1 = &ldb2; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c6 = &i2c1_lvds0; + i2c8 = &i2c1_lvds1; + usb0 = &usbotg1; + usbphy0 = &usbphy1; + usb1 = &usb2; + usbphy1 = &usb2_phy; + spi0 = &flexspi0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + /* DRAM space - 1, size : 1 GB DRAM */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x80000000 0 0x80000000>; + linux,cma-default; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + mu8: mu@5d230000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d230000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu8a>; + status = "okay"; + }; + + mu9: mu@5d240000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d240000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu9a>; + status = "okay"; + }; + + mu: mu@5d1b0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1b0000 0x0 0x10000>; + interrupts = ; + fsl,scu_ap_mu_id = <0>; + #mbox-cells = <4>; + status = "okay"; + }; + + clk: clk { + compatible = "fsl,imx8qm-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qm-iomuxc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8000000>; + }; + + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; + }; + + imx8qm-pm { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0: PD_DC_0 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll0: PD_DC_0_PLL_0{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll1: PD_DC_0_PLL_1{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0_pll0>; + }; + }; + + pd_mipi0: PD_MIPI_0_DSI { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi0_i2c0: PD_MIPI_0_DSI_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + + pd_mipi0_i2c1: PD_MIPI_0_DSI_I2C1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + + pd_mipi0_pwm: PD_MIPI_0_DSI_PWM0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + }; + + pd_lvds0: PD_LVDS0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lvds0_i2c0: PD_LVDS0_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_lvds0>; + }; + + pd_lvds0_pwm: PD_LVDS0_PWM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_lvds0>; + }; + }; + + pd_hdmi: PD_HDMI { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_pll0: PD_HDMI_PLL_0{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_pll1: PD_HDMI_PLL_1{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_pll0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_i2c0: PD_HDMI_I2C_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_pll1>; + }; + + pd_hdmi_i2s: PD_HDMI_I2S { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_pll1>; + }; + }; + }; + }; + + }; + + pd_dc1: PD_DC_1 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc1_pll0: PD_DC_1_PLL_0{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc1_pll1: PD_DC_1_PLL_1{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc1_pll0>; + }; + }; + + pd_mipi1: PD_MIPI_1_DSI { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi1_i2c0: PD_MIPI_1_DSI_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + + pd_mipi1_i2c1: PD_MIPI_1_DSI_I2C1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + + pd_mipi1_pwm: PD_MIPI_1_DSI_PWM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + }; + + pd_lvds1: PD_LVDS1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lvds1_i2c0: PD_LVDS1_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_lvds1>; + }; + + pd_lvds1_pwm: PD_LVDS1_PWM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_lvds1>; + }; + }; + }; + + pd_lsio: PD_LSIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio_pwm0: PD_LSIO_PWM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm1: PD_LSIO_PWM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm2: PD_LSIO_PWM_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm3: PD_LSIO_PWM_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm4: PD_LSIO_PWM_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm5: PD_LSIO_PWM_5 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm6: PD_LSIO_PWM_6 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm7: PD_LSIO_PWM_7 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_kpp: PD_LSIO_KPP { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio0: PD_LSIO_GPIO_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio1: PD_LSIO_GPIO_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio2: PD_LSIO_GPIO_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio3: PD_LSIO_GPIO_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio4: PD_LSIO_GPIO_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio5: PD_LSIO_GPIO_5{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio6:PD_LSIO_GPIO_6 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio7: PD_LSIO_GPIO_7 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt0: PD_LSIO_GPT_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt1: PD_LSIO_GPT_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt2: PD_LSIO_GPT_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt3: PD_LSIO_GPT_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt4: PD_LSIO_GPT_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi0: PD_LSIO_FSPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi1: PD_LSIO_FSPI_1{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu8a: PD_LSIO_MU8A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu9a: PD_LSIO_MU9A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + }; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_usbotg0: PD_CONN_USB_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + + pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + + pd_conn_usbotg1: PD_CONN_USB_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usb2: PD_CONN_USB_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usb2_phy: PD_CONN_USB_2_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch1: PD_CONN_SDHC_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch2: PD_CONN_SDHC_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet0: PD_CONN_ENET_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet1: PD_CONN_ENET_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_nand: PD_CONN_NAND { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_mlb0: PD_CONN_MLB_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + }; + + pd_hsio: PD_HSIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_serdes0: PD_HSIO_SERDES_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie0: PD_HSIO_PCIE_A { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_serdes0>; + }; + pd_pcie1: PD_HSIO_PCIE_B { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_serdes0>; + }; + }; + pd_serdes1: PD_HSIO_SERDES_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sata0: PD_HSIO_SATA_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_serdes1>; + }; + }; + pd_gpio: PD_HSIO_GPIO { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + }; + }; + + pd_audio: PD_AUDIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_asrc0:PD_AUD_ASRC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_asrc1: PD_AUD_ASRC_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_esai0: PD_AUD_ESAI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_esai1: PD_AUD_ESAI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_spdif0: PD_AUD_SPDIF_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_spdif1: PD_AUD_SPDIF_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai0:PD_AUD_SAI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai1: PD_AUD_SAI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai2: PD_AUD_SAI_2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai3: PD_AUD_SAI_3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai4: PD_AUD_SAI_4 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai5: PD_AUD_SAI_5 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai6: PD_AUD_SAI_6 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai7: PD_AUD_SAI_7 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt5: PD_AUD_GPT_5 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt6: PD_AUD_GPT_6 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt7: PD_AUD_GPT_7 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt8: PD_AUD_GPT_8 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt9: PD_AUD_GPT_9 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt10: PD_AUD_GPT_10 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_amix: PD_AUD_AMIX { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_mqs0: PD_AUD_MQS_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_mclk_out0: PD_AUD_MCLK_OUT_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_mclk_out1: PD_AUD_MCLK_OUT_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_flexcan0: PD_DMA_CAN_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_flexcan1: PD_DMA_CAN_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_flexcan2: PD_DMA_CAN_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_ftm0: PD_DMA_FTM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_ftm1: PD_DMA_FTM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_adc0: PD_DMA_ADC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_adc1: PD_DMA_ADC_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c0: PD_DMA_I2C_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c1: PD_DMA_I2C_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c2:PD_DMA_I2C_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c3: PD_DMA_I2C_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c4: PD_DMA_I2C_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart0: PD_DMA_UART0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart4: PD_DMA_UART4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi0: PD_DMA_SPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi1: PD_DMA_SPI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi2: PD_DMA_SPI_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi3: PD_DMA_SPI_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_emvsim0: PD_DMA_EMVSIM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_emvsim1: PD_DMA_EMVSIM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + }; + pd_gpu: PD_GPU { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_gpu0: PD_GPU0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_gpu>; + }; + pd_gpu1: PD_GPU1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_gpu>; + }; + }; + + pd_vpu: PD_VPU { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_core: VPU_CORE { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_vpu>; + }; + + pd_vpu_enc: VPU_ENC { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_vpu_core>; + }; + + pd_vpu_dec: VPU_DEC { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_vpu_core>; + }; + }; + + pd_isi_ch0: PD_IMAGING { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_csi0: PD_MIPI_CSI0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_csi0_i2c0: PD_MIPI_CSI0_I2C { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_csi0>; + }; + + pd_csi0_pwm: PD_MIPI_CSI0_PWM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_csi0>; + }; + }; + + pd_csi1: PD_MIPI_CSI1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_csi1_i2c0: PD_MIPI_CSI1_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_csi1>; + }; + + pd_csi1_pwm: PD_MIPI_CSI1_PWM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_csi1>; + }; + }; + + pd_hdmi_rx: PD_HDMI_RX { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_rx_i2c0: PD_HDMI_RX_I2C { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_rx>; + }; + }; + + pd_isi_ch1: PD_IMAGING_PDMA1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch2: PD_IMAGING_PDMA2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch3: PD_IMAGING_PDMA3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch4: PD_IMAGING_PDMA4 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch5: PD_IMAGING_PDMA5 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch6: PD_IMAGING_PDMA6 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch7: PD_IMAGING_PDMA7 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + }; + }; + + tsens: thermal-sensor { + compatible = "nxp,imx8qm-sc-tsens"; + u-boot,dm-pre-reloc; + /* number of the temp sensor on the chip */ + tsens-num = <5>; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + /* cpu thermal */ + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + /*the slope and offset of the temp sensor */ + thermal-sensors = <&tsens 0>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 1>; + trips { + cpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 2>; + trips { + gpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 3>; + trips { + gpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 4>; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + rtc: rtc { + compatible = "fsl,imx-sc-rtc"; + }; + + dpu1_intsteer: dpu_intsteer@56000000 { + compatible = "fsl,imx8qm-dpu-intsteer", "syscon"; + reg = <0x0 0x56000000 0x0 0x10000>; + }; + + dpu1: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-dpu"; + reg = <0x0 0x56180000 0x0 0x40000>; + intsteer = <&dpu1_intsteer>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "irq_common", + "irq_stream0a", + "irq_stream0b", /* to M4? */ + "irq_stream1a", + "irq_stream1b", /* to M4? */ + "irq_reserved0", + "irq_reserved1", + "irq_blit"; + clocks = <&clk IMX8QM_DC0_PLL0_CLK>, + <&clk IMX8QM_DC0_PLL1_CLK>, + <&clk IMX8QM_DC0_DISP0_CLK>, + <&clk IMX8QM_DC0_DISP1_CLK>; + clock-names = "pll0", "pll1", "disp0", "disp1"; + power-domains = <&pd_dc0_pll1>; + status = "disabled"; + + dpu1_disp0: port@0 { + reg = <0>; + + dpu1_disp0_mipi_dsi: mipi-dsi-endpoint { + }; + }; + + dpu1_disp1: port@1 { + reg = <1>; + + dpu1_disp1_lvds0: lvds0-endpoint { + remote-endpoint = <&ldb1_lvds0>; + }; + + dpu1_disp1_lvds1: lvds1-endpoint { + remote-endpoint = <&ldb1_lvds1>; + }; + }; + }; + + lvds_region1: lvds_region@56240000 { + compatible = "fsl,imx8qm-lvds-region", "syscon"; + reg = <0x0 0x56240000 0x0 0x10000>; + }; + + ldb1_phy: ldb_phy@56241000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,lvds-phy"; + reg = <0x0 0x56241000 0x0 0x100>; + clocks = <&clk IMX8QM_LVDS0_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd_lvds0>; + status = "disabled"; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb1: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX8QM_LVDS0_PIXEL_CLK>, + <&clk IMX8QM_LVDS0_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_lvds0>; + gpr = <&lvds_region1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_lvds0: endpoint { + remote-endpoint = <&dpu1_disp1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_lvds1: endpoint { + remote-endpoint = <&dpu1_disp1_lvds1>; + }; + }; + }; + }; + + dpu2_intsteer: dpu_intsteer@57000000 { + compatible = "fsl,imx8qm-dpu-intsteer", "syscon"; + reg = <0x0 0x57000000 0x0 0x10000>; + }; + + dpu2: dpu@57180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-dpu"; + reg = <0x0 0x57180000 0x0 0x40000>; + intsteer = <&dpu2_intsteer>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "irq_common", + "irq_stream0a", + "irq_stream0b", /* to M4? */ + "irq_stream1a", + "irq_stream1b", /* to M4? */ + "irq_reserved0", + "irq_reserved1", + "irq_blit"; + clocks = <&clk IMX8QM_DC1_PLL0_CLK>, + <&clk IMX8QM_DC1_PLL1_CLK>, + <&clk IMX8QM_DC1_DISP0_CLK>, + <&clk IMX8QM_DC1_DISP1_CLK>; + clock-names = "pll0", "pll1", "disp0", "disp1"; + power-domains = <&pd_dc1_pll1>; + status = "disabled"; + + dpu2_disp0: port@0 { + reg = <0>; + + dpu2_disp0_mipi_dsi: mipi-dsi-endpoint { + }; + }; + + dpu2_disp1: port@1 { + reg = <1>; + + dpu2_disp1_lvds0: lvds0-endpoint { + remote-endpoint = <&ldb2_lvds0>; + }; + + dpu2_disp1_lvds1: lvds1-endpoint { + remote-endpoint = <&ldb2_lvds1>; + }; + }; + }; + + lvds_region2: lvds_region@57240000 { + compatible = "fsl,imx8qm-lvds-region", "syscon"; + reg = <0x0 0x57240000 0x0 0x10000>; + }; + + ldb2_phy: ldb_phy@57241000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,lvds-phy"; + reg = <0x0 0x57241000 0x0 0x100>; + clocks = <&clk IMX8QM_LVDS1_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd_lvds1>; + status = "disabled"; + + ldb2_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb2_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb2: ldb@572410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX8QM_LVDS1_PIXEL_CLK>, + <&clk IMX8QM_LVDS1_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_lvds1>; + gpr = <&lvds_region2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_lvds0: endpoint { + remote-endpoint = <&dpu2_disp1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_lvds1: endpoint { + remote-endpoint = <&dpu2_disp1_lvds1>; + }; + }; + }; + }; + + camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58100000 0x0 0x10000>; + interrupts = <0 297 0>; + interface = <2 0 2>; /* + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch0>; + status = "disabled"; + }; + + isi_1: isi@58110000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58110000 0x0 0x10000>; + interrupts = <0 298 0>; + interface = <2 1 2>; + clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch1>; + status = "disabled"; + }; + + isi_2: isi@58120000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58120000 0x0 0x10000>; + interrupts = <0 299 0>; + interface = <2 2 2>; + clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch2>; + status = "disabled"; + }; + + isi_3: isi@58130000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58130000 0x0 0x10000>; + interrupts = <0 300 0>; + interface = <2 3 2>; + clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch3>; + status = "disabled"; + }; + + isi_4: isi@58140000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58140000 0x0 0x10000>; + interrupts = <0 301 0>; + interface = <3 0 2>; + clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch4>; + status = "disabled"; + }; + + isi_5: isi@58150000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58150000 0x0 0x10000>; + interrupts = <0 302 0>; + interface = <3 1 2>; + clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch5>; + status = "disabled"; + }; + + isi_6: isi@58160000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58160000 0x0 0x10000>; + interrupts = <0 303 0>; + interface = <3 2 2>; + clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch6>; + status = "disabled"; + }; + + isi_7: isi@58170000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58170000 0x0 0x10000>; + interrupts = <0 304 0>; + interface = <3 3 2>; + clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch7>; + status = "disabled"; + }; + + mipi_csi_0: csi@58227000 { + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */ + <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */ + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi0>; + clocks = <&clk IMX8QM_CSI0_APB_CLK>, + <&clk IMX8QM_CSI0_CORE_CLK>, + <&clk IMX8QM_CSI0_ESC_CLK>, + <&clk IMX8QM_IMG_PXL_LINK_CSI0_CLK>; + clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8QM_CSI0_CORE_CLK>, + <&clk IMX8QM_CSI0_ESC_CLK>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd_csi0>; + status = "disabled"; + }; + + mipi_csi_1: csi@58247000 { + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x0 0x58247000 0x0 0x1000>, /* CSI1 Controler base addr */ + <0x0 0x58241000 0x0 0x1000>; /* CSI1 Subsystem CSR base addr */ + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi1>; + clocks = <&clk IMX8QM_CSI1_APB_CLK>, + <&clk IMX8QM_CSI1_CORE_CLK>, + <&clk IMX8QM_CSI1_ESC_CLK>, + <&clk IMX8QM_IMG_PXL_LINK_CSI1_CLK>; + clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8QM_CSI1_CORE_CLK>, + <&clk IMX8QM_CSI1_ESC_CLK>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd_csi1>; + status = "disabled"; + }; + }; + + gpio0: gpio@5d080000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d080000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio0>; + }; + + gpio1: gpio@5d090000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d090000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio1>; + }; + + gpio2: gpio@5d0a0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0a0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio2>; + }; + + gpio3: gpio@5d0b0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0b0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio3>; + }; + + gpio4: gpio@5d0c0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0c0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio4>; + }; + + gpio5: gpio@5d0d0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0d0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio5>; + }; + + gpio6: gpio@5d0e0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0e0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio6>; + }; + + gpio7: gpio@5d0f0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0f0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio7>; + }; + + i2c0: i2c@5a800000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a800000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C0_CLK>, + <&clk IMX8QM_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a810000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C1_CLK>, + <&clk IMX8QM_I2C1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c1>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a820000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C2_CLK>, + <&clk IMX8QM_I2C2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c2>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a830000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C3_CLK>, + <&clk IMX8QM_I2C3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c3>; + status = "disabled"; + }; + + i2c4: i2c@5a840000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a840000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C4_CLK>, + <&clk IMX8QM_I2C4_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C4_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c4>; + status = "disabled"; + }; + + irqsteer_hdmi: irqsteer@56260000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56260000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>, + <&clk IMX8QM_HDMI_LIS_IPG_CLK>; + clock-names = "pll", "ipg"; + assigned-clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>, + <&clk IMX8QM_HDMI_LIS_IPG_CLK>; + assigned-clock-rates = <675000000>, <84000000>; + power-domains = <&pd_hdmi>; + }; + + i2c0_hdmi: i2c@56266000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56266000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + clocks = <&clk IMX8QM_HDMI_I2C0_CLK>, + <&clk IMX8QM_HDMI_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_HDMI_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_hdmi_i2c0>; + status = "disabled"; + }; + + irqsteer_lvds0: irqsteer@562400000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56240000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_LVDS0_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lvds0>; + }; + + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan"; + reg = <0x0 0x5a8d0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QM_CAN0_IPG_CLK>, + <&clk IMX8QM_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan"; + reg = <0x0 0x5a8e0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QM_CAN1_IPG_CLK>, + <&clk IMX8QM_CAN1_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_CAN1_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan1>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan"; + reg = <0x0 0x5a8f0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QM_CAN2_IPG_CLK>, + <&clk IMX8QM_CAN2_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_CAN2_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan2>; + status = "disabled"; + }; + + i2c1_lvds0: i2c@56247000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56247000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_lvds0>; + clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>, + <&clk IMX8QM_LVDS0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_lvds0_i2c0>; + status = "disabled"; + }; + + irqsteer_lvds1: irqsteer@572400000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x57240000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_LVDS1_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lvds1>; + }; + + i2c1_lvds1: i2c@57247000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x57247000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>, + <&clk IMX8QM_LVDS1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_lvds1_i2c0>; + status = "disabled"; + }; + + irqsteer_csi0: irqsteer@582200000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x58220000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_CSI0_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_csi0>; + }; + + i2c0_mipi_csi0: i2c@58226000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x58226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi0>; + clocks = <&clk IMX8QM_CSI0_I2C0_CLK>, + <&clk IMX8QM_CSI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_CSI0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_csi0_i2c0>; + status = "disabled"; + }; + + irqsteer_csi1: irqsteer@582400000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x58240000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_CSI1_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_csi1>; + }; + + i2c0_mipi_csi1: i2c@58246000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x58246000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi1>; + clocks = <&clk IMX8QM_CSI1_I2C0_CLK>, + <&clk IMX8QM_CSI1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_CSI1_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_csi1_i2c0>; + status = "disabled"; + }; + + irqsteer_dsi0: irqsteer@56220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56220000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_DSI0_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi0>; + }; + + i2c0_mipi_dsi0: i2c@56226000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_dsi0>; + clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>, + <&clk IMX8QM_MIPI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi0_i2c0>; + status = "disabled"; + }; + + mipi0: mipi@56220000 { + compatible = "fsl,imx8qm-mipi_dsi"; + reg = <0x0 0x56220000 0x0 0x10000>; + interrupts = <0 59 4>; + fsl,irq-steer = <0x56220000>; + fsl,irq-num = <0x10000>; + clocks = + <&clk IMX8QM_MIPI0_PXL_CLK>, + <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>, + <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>; + clock-names = + "clk_pixel","clk_tx_esc", "clk_rx_esc"; + power-domains = <&pd_mipi0>; + instance = <0>; + data_lanes = <4>; + virtual_ch = <0>; + dpi_fmt = <5>; + status = "disabled"; + }; + + mipi1: mipi@57220000 { + compatible = "fsl,imx8qm-mipi_dsi"; + reg = <0x0 0x57220000 0x0 0x10000>; + interrupts = <0 60 4>; + fsl,irq-steer = <0x57220000>; + fsl,irq-num = <0x10000>; + clocks = + <&clk IMX8QM_MIPI1_PXL_CLK>, + <&clk IMX8QM_MIPI1_DSI_TX_ESC_CLK>, + <&clk IMX8QM_MIPI1_DSI_RX_ESC_CLK>; + clock-names = + "clk_pixel", "clk_tx_esc", "clk_rx_esc"; + power-domains = <&pd_mipi1>; + instance = <1>; + data_lanes = <4>; + virtual_ch = <0>; + dpi_fmt = <5>; + status = "disabled"; + }; + + lpspi0: lpspi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a000000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_SPI0_CLK>; + clock-names = "ipg"; + assigned-clocks = <&clk IMX8QM_SPI0_CLK>; + assigned-clock-rates = <32000000>; + power-domains = <&pd_dma_lpspi0>; + status = "disabled"; + }; + + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART0_CLK>, + <&clk IMX8QM_UART0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART0_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart0>; + status = "disabled"; + }; + + lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART1_CLK>, + <&clk IMX8QM_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart1>; + dma-names = "tx","rx"; + dmas = <&edma0 15 0 0>, + <&edma0 14 0 1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART2_CLK>, + <&clk IMX8QM_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart2>; + dma-names = "tx","rx"; + dmas = <&edma0 17 0 0>, + <&edma0 16 0 1>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART3_CLK>, + <&clk IMX8QM_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart3>; + dma-names = "tx","rx"; + dmas = <&edma0 19 0 0>, + <&edma0 18 0 1>; + status = "disabled"; + }; + + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a0a0000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART4_CLK>, + <&clk IMX8QM_UART4_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART4_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart4>; + dma-names = "tx","rx"; + dmas = <&edma0 21 0 0>, + <&edma0 20 0 1>; + status = "disabled"; + }; + + edma0: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>, /* channel15 UART1 tx */ + <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */ + <0x0 0x5a310000 0x0 0x10000>, /* channel17 UART2 tx */ + <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */ + <0x0 0x5a330000 0x0 0x10000>, /* channel19 UART3 tx */ + <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ + <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <10>; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma-chan12-tx", "edma-chan13-tx", + "edma-chan14-tx", "edma-chan15-tx", + "edma-chan16-tx", "edma-chan17-tx", + "edma-chan18-tx", "edma-chan19-tx", + "edma-chan20-tx", "edma-chan21-tx"; + status = "okay"; + }; + + edma2: dma-controller@591F0000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ + <0x0 0x59210000 0x0 0x10000>, + <0x0 0x59220000 0x0 0x10000>, + <0x0 0x59230000 0x0 0x10000>, + <0x0 0x59240000 0x0 0x10000>, + <0x0 0x59250000 0x0 0x10000>, + <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ + <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ + <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>; /* sai1 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <14>; + interrupts = , /* asrc0 */ + , + , + , + , + , + , /* esai0 */ + , + , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + ; + interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc0 */ + "edma-chan2-tx", "edma-chan3-tx", + "edma-chan4-tx", "edma-chan5-tx", + "edma-chan6-tx", "edma-chan7-tx", /* esai0 */ + "edma-chan8-tx", "edma-chan9-tx", /* spdif0 */ + "edma-chan12-tx", "edma-chan13-tx", /* sai0 */ + "edma-chan14-tx", "edma-chan15-tx"; /* sai1 */ + status = "okay"; + }; + + edma3: dma-controller@599F0000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ + <0x0 0x59A10000 0x0 0x10000>, + <0x0 0x59A20000 0x0 0x10000>, + <0x0 0x59A30000 0x0 0x10000>, + <0x0 0x59A40000 0x0 0x10000>, + <0x0 0x59A50000 0x0 0x10000>, + <0x0 0x59A80000 0x0 0x10000>, /* sai6 rx */ + <0x0 0x59A90000 0x0 0x10000>, /* sai6 tx */ + <0x0 0x59AA0000 0x0 0x10000>; /* sai7 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <9>; + interrupts = , /* asrc1 */ + , + , + , + , + , + , /* sai6 */ + , + ; /* sai7 */ + interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc1 */ + "edma-chan2-tx", "edma-chan3-tx", + "edma-chan4-tx", "edma-chan5-tx", + "edma-chan8-tx", "edma-chan9-tx", /* sai6 */ + "edma-chan10-tx"; /* sai7 */ + status = "okay"; + }; + + gpt0: gpt0@5d140000 { + compatible = "fsl,imx8qm-gpt"; + reg = <0x0 0x5d140000 0x0 0x4000>; + interrupts = ; + clocks = <&clk IMX8QM_GPT0_CLK>, <&clk IMX8QM_GPT_3M>; + clock-names = "ipg", "per"; + power-domains = <&pd_lsio_gpt0>; + }; + + gpu_3d0: gpu@53100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x53100000 0 0x40000>; + interrupts = ; + clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>; + assigned-clock-rates = <800000000>, <1000000000>; + fsl,sc_gpu_pid = ; + power-domains = <&pd_gpu0>; + status = "disabled"; + }; + + gpu_3d1: gpu@54100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x54100000 0x0 0x40000>; + interrupts = ; + clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>; + assigned-clock-rates = <800000000>, <1000000000>; + fsl,sc_gpu_pid = ; + power-domains = <&pd_gpu1>; + status = "disabled"; + }; + + imx8_gpu_ss: imx8_gpu_ss { + compatible = "fsl,imx8qm-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>, <&gpu_3d1>; + reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; + + mlb: mlb@5B060000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0 0x5B060000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, + <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_MLB_CLK>, + <&clk IMX8QM_MLB_HCLK>, + <&clk IMX8QM_MLB_IPG_CLK>; + clock-names = "mlb", "hclk", "ipg"; + assigned-clocks = <&clk IMX8QM_MLB_CLK>, + <&clk IMX8QM_MLB_HCLK>, + <&clk IMX8QM_MLB_IPG_CLK>; + assigned-clock-rates = <333333333>, <333333333>, <83333333>; + power-domains = <&pd_conn_mlb0>; + status = "disabled"; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QM_SDHC0_IPG_CLK>, + <&clk IMX8QM_SDHC0_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QM_SDHC0_DIV>; + assigned-clock-rates = <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: usdhc@5b020000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b020000 0x0 0x10000>; + clocks = <&clk IMX8QM_SDHC1_IPG_CLK>, + <&clk IMX8QM_SDHC1_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QM_SDHC1_DIV>; + assigned-clock-rates = <200000000>; + power-domains = <&pd_conn_sdch1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: usdhc@5b030000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b030000 0x0 0x10000>; + clocks = <&clk IMX8QM_SDHC2_IPG_CLK>, + <&clk IMX8QM_SDHC2_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QM_SDHC2_DIV>; + assigned-clock-rates = <200000000>; + power-domains = <&pd_conn_sdch2>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; + reg = <0x0 0x5b040000 0x0 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8QM_ENET0_IPG_CLK>, <&clk IMX8QM_ENET0_AHB_CLK>, <&clk IMX8QM_ENET0_RGMII_TX_CLK>, + <&clk IMX8QM_ENET0_PTP_CLK>, <&clk IMX8QM_ENET0_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>, + <&clk IMX8QM_ENET0_REF_DIV>, + <&clk IMX8QM_ENET0_PTP_CLK>; + assigned-clock-rates = <250000000>, <125000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd_conn_enet0>; + iommus = <&smmu 0x12 0x7f80>; + status = "disabled"; + }; + + fec2: ethernet@5b050000 { + compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; + reg = <0x0 0x5b050000 0x0 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8QM_ENET1_IPG_CLK>, <&clk IMX8QM_ENET1_AHB_CLK>, <&clk IMX8QM_ENET1_RGMII_TX_CLK>, + <&clk IMX8QM_ENET1_PTP_CLK>, <&clk IMX8QM_ENET1_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>, + <&clk IMX8QM_ENET1_REF_DIV>, + <&clk IMX8QM_ENET1_PTP_CLK>; + assigned-clock-rates = <250000000>, <125000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd_conn_enet1>; + iommus = <&smmu 0x12 0x7f80>; + status = "disabled"; + }; + + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x5b0d0200 0x0 0x200>; + }; + + usbphy1: usbphy@0x5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x0 0x5b100000 0x0 0x200>; + clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>; + power-domains = <&pd_conn_usbotg0_phy>; + + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0d0000 0x0 0x200>; + interrupts = ; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbotg0>; + }; + + usb2_phy: phy@0x5b160000 { + compatible = "fsl,imx8-usb-phy"; + reg = <0x0 0x5b160000 0x0 0x10000>; + power-domains = <&pd_conn_usb2_phy>; + }; + + usb2: usb@0x5b110000 { + compatible = "fsl,imx8-usb3"; + reg = <0x0 0x5b110000 0x0 0x38000>; + fsl,usbphy = <&usb2_phy>; + status = "disabled"; + power-domains = <&pd_conn_usb2>; + }; + + ddr_pmu0: ddr_pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x5c020000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + ddr_pmu1: ddr_pmu@5c120000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x5c120000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + vpu: vpu@2c000000 { + compatible = "nxp,imx8qm-vpu", "nxp,imx8x-vpu"; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "iobase_vpu"; + interrupts = <0 464 0x4>; + interrupt-names = "irq_vpu"; + clocks = <&clk IMX8QM_VPU_DDR_CLK>, + <&clk IMX8QM_VPU_SYS_CLK>, + <&clk IMX8QM_VPU_XUVI_CLK>, + <&clk IMX8QM_VPU_UART_CLK>; + clock-names = "clk_vpu_ddr", "clk_vpu_sys", + "clk_vpu_xuvi", "clk_vpu_uart"; + assigned-clocks = <&clk IMX8QM_VPU_DDR_CLK>, + <&clk IMX8QM_VPU_SYS_CLK>, + <&clk IMX8QM_VPU_XUVI_CLK>, + <&clk IMX8QM_VPU_UART_CLK>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <80000000>; + power-domains = <&pd_vpu_dec>; + status = "disabled"; + }; + + acm: acm@59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x0 0x59e00000 0x0 0x1D0000>; + status = "disabled"; + }; + + esai0: esai@59010000 { + compatible = "fsl,imx8qm-esai"; + reg = <0x0 0x59010000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QM_AUD_ESAI_0_IPG>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma2 6 0 1>, <&edma2 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd_esai0>; + status = "disabled"; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x0 0x59020000 0x0 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&clk IMX8QM_AUD_SPDIF_0_GCLKW>, /* core */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx0 */ + <&clk IMX8QM_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8QM_IPG_AUD_CLK_ROOT>, /* rxtx5 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8QM_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma2 8 0 5>, <&edma2 9 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd_spdif0>; + status = "disabled"; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59050000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QM_AUD_SAI_1_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_1_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma2 14 0 1>, <&edma2 15 0 0>; + status = "disabled"; + power-domains = <&pd_sai1>; + }; + + + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59040000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QM_AUD_SAI_0_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_0_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma2 12 0 1>, <&edma2 13 0 0>; + status = "disabled"; + power-domains = <&pd_sai0>; + }; + + sai6: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59820000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QM_AUD_SAI_6_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_6_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma3 8 0 1>, <&edma3 9 0 0>; + status = "disabled"; + power-domains = <&pd_sai6>; + }; + + sai7: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59830000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QM_AUD_SAI_7_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_7_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma3 10 0 0>; + status = "disabled"; + power-domains = <&pd_sai7>; + }; + + amix: amix@59840000 { + compatible = "fsl,imx8qm-amix"; + reg = <0x0 0x59840000 0x0 0x10000>; + clocks = <&clk IMX8QM_AUD_AMIX_IPG>; + clock-names = "ipg"; + power-domains = <&pd_amix>; + status = "disabled"; + }; + + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc0"; + reg = <0x0 0x59000000 0x0 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8QM_AUD_ASRC_0_IPG>, + <&clk IMX8QM_AUD_ASRC_0_MEM>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>, + <&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc0>; + status = "disabled"; + }; + + asrc1: asrc@59800000 { + compatible = "fsl,imx8qm-asrc1"; + reg = <0x0 0x59800000 0x0 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8QM_AUD_ASRC_1_IPG>, + <&clk IMX8QM_AUD_ASRC_1_MEM>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>, + <&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc1>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x0 0x59850000 0x0 0x10000>; + clocks = <&clk IMX8QM_AUD_MQS_IPG>, + <&clk IMX8QM_AUD_MQS_HMCLK>; + clock-names = "core", "mclk"; + power-domains = <&pd_mqs0>; + status = "disabled"; + }; + + flexspi0: flexspi@05d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-flexspi"; + reg = <0x0 0x5d120000 0x0 0x10000>, + <0x0 0x08000000 0x0 0x19ffffff>; + reg-names = "FlexSPI", "FlexSPI-memory"; + interrupts = ; + clocks = <&clk IMX8QM_FSPI0_CLK>, + <&clk IMX8QM_FSPI0_CLK>; + assigned-clock-rates = <29000000>,<29000000>; + clock-names = "qspi_en", "qspi"; + power-domains = <&pd_lsio_flexspi0>; + status = "disabled"; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>, + <&dpu2_disp0>, <&dpu2_disp1>; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + hsio: hsio@5f080000 { + compatible = "fsl,imx8qm-hsio", "syscon"; + reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ + }; + + pciea: pcie@0x5f000000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x0 0x5f000000 0x0 0x10000>, /* Controller reg */ + <0x0 0x6ff00000 0x0 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 73 4>, + <0 0 0 2 &gic 0 74 4>, + <0 0 0 3 &gic 0 75 4>, + <0 0 0 4 &gic 0 76 4>; + power-domains = <&pd_pcie0>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + hsio = <&hsio>; + ctrl-id = <0>; /* pciea */ + cpu-base-addr = <0x40000000>; + status = "disabled"; + }; + + pcieb: pcie@0x5f010000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg */ + <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + power-domains = <&pd_pcie1>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + hsio = <&hsio>; + ctrl-id = <1>; /* pciea */ + cpu-base-addr = <0x80000000>; + status = "disabled"; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; +}; + +&A53_0 { + operating-points = < + /* kHz uV */ + 1200000 1150000 + >; + clocks = <&clk IMX8QM_A53_DIV>; +}; + +&A72_0 { + operating-points = < + /* kHz uV */ + 1596000 1150000 + >; + clocks = <&clk IMX8QM_A72_DIV>; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-17x17-val.dts b/arch/arm/dts/fsl-imx8qxp-17x17-val.dts new file mode 100644 index 00000000000..370000d461e --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-17x17-val.dts @@ -0,0 +1,54 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +/ { + model = "Freescale i.MX8QXP 17x17 Validation board"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_1_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_1_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c3 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&usb2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts new file mode 100644 index 00000000000..5518abe1118 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts @@ -0,0 +1,428 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/* Last 3M is for M4/RPMSG */ +/memreserve/ 0x80000000 0x00400000; + +#include "fsl-imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP LPDDR4 ARM2"; + compatible = "fsl,imx8qxp-lpddr4-arm2", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <300>; + off-on-delay-us = <5000>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8qxp-arm2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpi2c1: lpi1cgrp { + fsl,pins = < + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000020 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000020 + >; + }; + + pinctrl_lpi2c3: lpi2cgrp { + fsl,pins = < + SC_P_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 + SC_P_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x06000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x06000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "disabled"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + it6263-0@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + it6263-1@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-mek-auto.dts b/arch/arm/dts/fsl-imx8qxp-mek-auto.dts new file mode 100644 index 00000000000..e105f684ec7 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-mek-auto.dts @@ -0,0 +1,76 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qxp-mek.dts" + +/ { + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200 androidboot.console=ttyLP0 androidboot.xen_boot=default"; + stdout-path = &lpuart0; + }; + + config { + load-environment = <0>; + }; +}; + +&gpio0 { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; + +&gpio3 { + status = "disabled"; +}; + +&gpio4 { + status = "disabled"; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&i2c0_mipi_lvds0 { + status = "disabled"; +}; + +&i2c0_mipi_lvds1 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&usbotg1 { + status = "disabled"; +}; + +&usb2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts new file mode 100644 index 00000000000..b37569ea48c --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-mek.dts @@ -0,0 +1,441 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/* Last 127M is for M4/RPMSG */ +/memreserve/ 0x80000000 0x08000000; + +#include "fsl-imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP MEK"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + + aliases { + i2c4 = &bb_i2c1; + i2c5 = &mfi_i2c1; + i2c6 = &i2cexp1_i2c1; + i2c7 = &i2cexp2_i2c1; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qxp-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpi2c1: lpi1cgrp { + fsl,pins = < + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000020 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x06000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x06000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx-virt-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9646_switch: mux@71 { + compatible = "nxp,pca9646", "fsl,imx-virt-i2c-mux"; + reg = <0x71>; + u-boot,i2c-offset-len = <0>; + virtual-bus-seq = <12>; + #address-cells = <1>; + #size-cells = <0>; + + bb_i2c1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + mfi_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2cexp1_i2c1: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2cexp2_i2c1: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp.dtsi b/arch/arm/dts/fsl-imx8qxp.dtsi new file mode 100644 index 00000000000..e155e8f59a3 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp.dtsi @@ -0,0 +1,2196 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "fsl-imx8-ca35.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + compatible = "fsl,imx8qxp"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + csi0 = &mipi_csi_0; + dpu0 = &dpu1; + ethernet0 = &fec1; + ethernet1 = &fec2; + ldb0 = &ldb1; + ldb1 = &ldb2; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c13 = &i2c0_mipi_lvds0; + i2c15 = &i2c0_mipi_lvds1; + spi0 = &flexspi0; + usb0 = &usbotg1; + usbphy0 = &usbphy1; + usb1 = &usb2; + usbphy1 = &usb2_phy; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + /* DRAM space - 1, size : 1 GB DRAM */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x80000000 0 0x80000000>; + linux,cma-default; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + mu8: mu@5d230000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d230000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu8a>; + status = "okay"; + }; + + mu: mu@5d1b0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1b0000 0x0 0x10000>; + interrupts = ; + fsl,scu_ap_mu_id = <0>; + #mbox-cells = <4>; + status = "okay"; + }; + + mu13: mu13@5d280000 { + compatible = "fsl,imx8-mu-hifi"; + reg = <0x0 0x5d280000 0x0 0x10000>; + interrupts = ; + fsl,hifi_ap_mu_id = <13>; + status = "okay"; + }; + + clk: clk { + compatible = "fsl,imx8qxp-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qxp-iomuxc"; + }; + + rtc: rtc { + compatible = "fsl,imx-sc-rtc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8000000>; + }; + + imx8qx-pm { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio: PD_LSIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio_pwm0: PD_LSIO_PWM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm1: PD_LSIO_PWM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm2: PD_LSIO_PWM_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm3: PD_LSIO_PWM_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm4: PD_LSIO_PWM_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm5: PD_LSIO_PWM_5 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm6: PD_LSIO_PWM_6 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm7: PD_LSIO_PWM_7 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_kpp: PD_LSIO_KPP { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio0: PD_LSIO_GPIO_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio1: PD_LSIO_GPIO_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio2: PD_LSIO_GPIO_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio3: PD_LSIO_GPIO_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio4: PD_LSIO_GPIO_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio5: PD_LSIO_GPIO_5{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio6:PD_LSIO_GPIO_6 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio7: PD_LSIO_GPIO_7 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt0: PD_LSIO_GPT_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt1: PD_LSIO_GPT_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt2: PD_LSIO_GPT_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt3: PD_LSIO_GPT_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt4: PD_LSIO_GPT_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi0: PD_LSIO_FSPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi1: PD_LSIO_FSPI_1{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu8a: PD_LSIO_MU8A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + }; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_usbotg0: PD_CONN_USB_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usbotg1: PD_CONN_USB_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usb2: PD_CONN_USB_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usb2_phy: PD_CONN_USB_2_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch1: PD_CONN_SDHC_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch2: PD_CONN_SDHC_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet0: PD_CONN_ENET_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet1: PD_CONN_ENET_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_nand: PD_CONN_NAND { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_mlb0: PD_CONN_MLB_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + }; + + pd_audio: PD_AUDIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_asrc0:PD_AUD_ASRC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_asrc1: PD_AUD_ASRC_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_esai0: PD_AUD_ESAI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_spdif0: PD_AUD_SPDIF_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai0:PD_AUD_SAI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai1: PD_AUD_SAI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai2: PD_AUD_SAI_2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai3: PD_AUD_SAI_3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai4: PD_AUD_SAI_4 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai5: PD_AUD_SAI_5 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt5: PD_AUD_GPT_5 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt6: PD_AUD_GPT_6 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt7: PD_AUD_GPT_7 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt8: PD_AUD_GPT_8 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt9: PD_AUD_GPT_9 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt10: PD_AUD_GPT_10 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_amix: PD_AUD_AMIX { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_mqs0: PD_AUD_MQS_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_hifi: PD_AUD_HIFI { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_hifi_ram: PD_AUD_OCRAM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_mclk_out0: PD_AUD_MCLK_OUT_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_mclk_out1: PD_AUD_MCLK_OUT_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_flexcan0: PD_DMA_CAN_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_flexcan1: PD_DMA_CAN_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_flexcan2: PD_DMA_CAN_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_ftm0: PD_DMA_FTM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_ftm1: PD_DMA_FTM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_adc0: PD_DMA_ADC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c0: PD_DMA_I2C_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c1: PD_DMA_I2C_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c2:PD_DMA_I2C_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c3: PD_DMA_I2C_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart0: PD_DMA_UART0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi0: PD_DMA_SPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi1: PD_DMA_SPI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi2: PD_DMA_SPI_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi3: PD_DMA_SPI_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_pwm0: PD_DMA_PWM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lcd0: PD_DMA_LCD_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + }; + + pd_gpu: gpu-power-domain { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_gpu0: gpu0 { + name = "gpu0"; + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_gpu>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pd_vpu: vpu-power-domain { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_core: vpu_core { + name = "vpu_core"; + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_vpu>; + }; + }; + + pd_hsio: hsio-power-domain { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_serdes1: PD_HSIO_SERDES_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: PD_HSIO_PCIE_B { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_serdes1>; + }; + }; + pd_gpio: PD_HSIO_GPIO { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + }; + }; + + pd_cm40: PD_CM40 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_cm40_i2c: PD_CM40_I2C { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + + pd_cm40_intmux: PD_CM40_INTMUX { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + }; + + + pd_dc0: PD_DC_0 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll0: PD_DC_0_PLL_0{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll1: PD_DC_0_PLL_1{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0_pll0>; + }; + }; + pd_mipi_dsi0: PD_MIPI_0_DSI { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_0_lvds: PD_LVDS0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + + pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + }; + + pd_mipi_dsi1: PD_MIPI_1_DSI { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_1_lvds: PD_LVDS1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + + pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + }; + }; + + pd_isi_ch0: PD_IMAGING { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_csi: PD_MIPI_CSI0 { + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + power-domains =<&pd_isi_ch0>; + + pd_mipi_csi_i2c0: PD_MIPI_CSI0_I2C { + name = "mipi_csi0_i2c"; + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_csi>; + }; + + pd_mipi_csi_pwm0: PD_MIPI_CSI0_PWM { + name = "mipi_csi0_pwm"; + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_csi>; + }; + }; + + pd_isi_ch1: PD_IMAGING_PDMA1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch2: PD_IMAGING_PDMA2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch3: PD_IMAGING_PDMA3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch4: PD_IMAGING_PDMA4 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch5: PD_IMAGING_PDMA5 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch6: PD_IMAGING_PDMA6 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch7: PD_IMAGING_PDMA7 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + }; + }; + + tsens: thermal-sensor { + compatible = "nxp,imx8qxp-sc-tsens"; + u-boot,dm-pre-reloc; + /* number of the temp sensor on the chip */ + tsens-num = <1>; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + /* cpu thermal */ + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + /*the slope and offset of the temp sensor */ + thermal-sensors = <&tsens 0>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + gpio0: gpio@5d080000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d080000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio0>; + }; + + gpio1: gpio@5d090000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d090000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio1>; + }; + + gpio2: gpio@5d0a0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0a0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio2>; + }; + + gpio3: gpio@5d0b0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0b0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio3>; + }; + + gpio4: gpio@5d0c0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0c0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio4>; + }; + + gpio5: gpio@5d0d0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0d0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio5>; + }; + + gpio6: gpio@5d0e0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0e0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio6>; + }; + + gpio7: gpio@5d0f0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0f0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio7>; + }; + + irqsteer_csi: irqsteer@58220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x58220000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_CSI0_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi_csi>; + }; + + i2c0_csi0: i2c@58226000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x58226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi>; + clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>, + <&clk IMX8QXP_CSI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_csi_i2c0>; + status = "disabled"; + }; + + intmux_cm40: intmux@37400000 { + compatible = "nxp,imx-intmux"; + reg = <0x0 0x37400000 0x0 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_CM40_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_cm40_intmux>; + status = "disabled"; + }; + + i2c0_cm40: i2c@37230000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x37230000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intmux_cm40>; + clocks = <&clk IMX8QXP_CM40_I2C_CLK>, + <&clk IMX8QXP_CM40_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_cm40_i2c>; + status = "disabled"; + }; + + dpu_intsteer: dpu_intsteer@56000000 { + compatible = "fsl,imx8qxp-dpu-intsteer", "syscon"; + reg = <0x0 0x56000000 0x0 0x10000>; + }; + + dpu1: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-dpu", "fsl,imx8qm-dpu"; + reg = <0x0 0x56180000 0x0 0x40000>; + intsteer = <&dpu_intsteer>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "irq_common", + "irq_stream0a", + "irq_stream0b", /* to M4? */ + "irq_stream1a", + "irq_stream1b", /* to M4? */ + "irq_reserved0", + "irq_reserved1", + "irq_blit"; + clocks = <&clk IMX8QXP_DC0_PLL0_CLK>, + <&clk IMX8QXP_DC0_PLL1_CLK>, + <&clk IMX8QXP_DC0_DISP0_CLK>, + <&clk IMX8QXP_DC0_DISP1_CLK>; + clock-names = "pll0", "pll1", "disp0", "disp1"; + power-domains = <&pd_dc0_pll1>; + status = "disabled"; + + dpu_disp0: port@0 { + reg = <0>; + + dpu_disp0_lvds0_ch0: lvds0-endpoint { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu_disp0_lvds0_ch1: lvds1-endpoint { + remote-endpoint = <&ldb1_ch1>; + }; + + dpu_disp0_mipi_dsi: mipi-dsi-endpoint { + }; + }; + + dpu_disp1: port@1 { + reg = <1>; + + dpu_disp1_lvds1_ch0: lvds0-endpoint { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu_disp1_lvds1_ch1: lvds1-endpoint { + remote-endpoint = <&ldb2_ch1>; + }; + + dpu_disp1_mipi_dsi: mipi-dsi-endpoint { + }; + }; + }; + + irqsteer_mipi_lvds0: irqsteer@56220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56220000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_MIPI0_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi_dsi0>; + }; + + lvds_region1: lvds_region@56220000 { + compatible = "fsl,imx8qxp-lvds-region", "syscon"; + reg = <0x0 0x56220000 0x0 0x10000>; + }; + + ldb1_phy: ldb_phy@56221000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd_mipi_dsi_0_lvds>; + status = "disabled"; + }; + + ldb1: ldb@562210e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_mipi_dsi_0_lvds>; + gpr = <&lvds_region1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu_disp0_lvds0_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu_disp0_lvds0_ch1>; + }; + }; + }; + }; + + i2c0_mipi_lvds0: i2c@56226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + clocks = <&clk IMX8QXP_MIPI0_I2C0_CLK>, + <&clk IMX8QXP_MIPI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_MIPI0_I2C0_DIV>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_dsi_0_i2c0>; + status = "disabled"; + }; + + irqsteer_mipi_lvds1: irqsteer@56240000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56240000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_MIPI1_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi_dsi1>; + }; + + lvds_region2: lvds_region@56240000 { + compatible = "fsl,imx8qxp-lvds-region", "syscon"; + reg = <0x0 0x56240000 0x0 0x10000>; + }; + + ldb2_phy: ldb_phy@56241000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x0 0x56241000 0x0 0x100>, <0x0 0x56248000 0x0 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX8QXP_MIPI1_LVDS_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd_mipi_dsi_1_lvds>; + status = "disabled"; + }; + + ldb2: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_mipi_dsi_1_lvds>; + gpr = <&lvds_region2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu_disp1_lvds1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu_disp1_lvds1_ch1>; + }; + }; + }; + }; + + camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58100000 0x0 0x10000>; + interrupts = <0 297 0>; + interface = <2 0 2>; /* + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch0>; + status = "disabled"; + }; + + isi_1: isi@58110000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58110000 0x0 0x10000>; + interrupts = <0 298 0>; + interface = <2 1 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch1>; + status = "disabled"; + }; + + isi_2: isi@58120000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58120000 0x0 0x10000>; + interrupts = <0 299 0>; + interface = <2 2 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch2>; + status = "disabled"; + }; + + isi_3: isi@58130000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58130000 0x0 0x10000>; + interrupts = <0 300 0>; + interface = <2 3 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch3>; + status = "disabled"; + }; + + isi_4: isi@58140000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58140000 0x0 0x10000>; + interrupts = <0 301 0>; + interface = <3 0 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch4>; + status = "disabled"; + }; + + isi_5: isi@58150000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58150000 0x0 0x10000>; + interrupts = <0 302 0>; + interface = <3 1 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch5>; + status = "disabled"; + }; + + isi_6: isi@58160000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58160000 0x0 0x10000>; + interrupts = <0 303 0>; + interface = <3 2 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch6>; + status = "disabled"; + }; + + isi_7: isi@58170000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58170000 0x0 0x10000>; + interrupts = <0 304 0>; + interface = <3 3 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch7>; + status = "disabled"; + }; + + mipi_csi_0: csi@58227000 { + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */ + <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */ + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi>; + clocks = <&clk IMX8QXP_CSI0_APB_CLK>, + <&clk IMX8QXP_CSI0_CORE_CLK>, + <&clk IMX8QXP_CSI0_ESC_CLK>, + <&clk IMX8QXP_IMG_PXL_LINK_CSI0_CLK>; + clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8QXP_CSI0_CORE_CLK>, + <&clk IMX8QXP_CSI0_ESC_CLK>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd_mipi_csi>; + status = "disabled"; + }; + }; + + i2c0_mipi_lvds1: i2c@56246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56246000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + clocks = <&clk IMX8QXP_MIPI1_I2C0_CLK>, + <&clk IMX8QXP_MIPI1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_MIPI1_I2C0_DIV>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_dsi_1_i2c0>; + status = "disabled"; + }; + + i2c0: i2c@5a800000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a800000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a810000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C1_CLK>, + <&clk IMX8QXP_I2C1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c1>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a820000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c2>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a830000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C3_CLK>, + <&clk IMX8QXP_I2C3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c3>; + status = "disabled"; + }; + + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x5b0d0200 0x0 0x200>; + }; + + usbphy1: usbphy@0x5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x0 0x5b100000 0x0 0x200>; + clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>; + power-domains = <&pd_conn_usbotg0_phy>; + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0d0000 0x0 0x200>; + interrupts = ; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbotg0>; + }; + + usb2_phy: phy@0x5b160000 { + compatible = "fsl,imx8-usb-phy"; + reg = <0x0 0x5b160000 0x0 0x10000>; + power-domains = <&pd_conn_usb2_phy>; + }; + + usb2: usb@0x5b110000 { + compatible = "fsl,imx8-usb3"; + reg = <0x0 0x5b110000 0x0 0x38000>; + fsl,usbphy = <&usb2_phy>; + status = "disabled"; + power-domains = <&pd_conn_usb2>; + }; + + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8d0000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8e0000 0x0 0x10000>; + interrupts = ; + /* CAN0 clock and PD is shared among all CAN instances */ + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan0>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8f0000 0x0 0x10000>; + interrupts = ; + /* CAN0 clock and PD is shared among all CAN instances */ + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan0>; + status = "disabled"; + }; + + dma_apbh: dma-apbh@5b810000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x0 0x5b810000 0x0 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8QXP_APBHDMA_CLK>; + power-domains = <&pd_conn_nand>; + }; + + gpmi: gpmi-nand@5b812000{ + compatible = "fsl,imx8qxp-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>, + <&clk IMX8QXP_GPMI_APB_CLK>, + <&clk IMX8QXP_GPMI_BCH_CLK>, + <&clk IMX8QXP_GPMI_APB_BCH_CLK>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + power-domains = <&pd_conn_nand>; + status = "disabled"; + }; + + gpu_3d0: gpu@53100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x53100000 0 0x40000>; + interrupts = ; + clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; + assigned-clock-rates = <600000000>, <850000000>; + power-domains = <&pd_gpu0>; + status = "disabled"; + }; + + imx8_gpu_ss: imx8_gpu_ss { + compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>; + reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; + + ddr_pmu0: ddr_pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x5c020000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_UART0_CLK>, + <&clk IMX8QXP_UART0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART0_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart0>; + status = "disabled"; + }; + + lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_UART1_CLK>, + <&clk IMX8QXP_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart1>; + dma-names = "tx","rx"; + dmas = <&edma0 11 0 0>, + <&edma0 10 0 1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_UART2_CLK>, + <&clk IMX8QXP_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart2>; + dma-names = "tx","rx"; + dmas = <&edma0 13 0 0>, + <&edma0 12 0 1>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_UART3_CLK>, + <&clk IMX8QXP_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart3>; + dma-names = "tx","rx"; + dmas = <&edma0 15 0 0>, + <&edma0 14 0 1>; + status = "disabled"; + }; + + edma0: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */ + <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */ + <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */ + <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */ + <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */ + #dma-cells = <3>; + dma-channels = <8>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "edma-chan8-tx", "edma-chan9-tx", + "edma-chan10-tx", "edma-chan11-tx", + "edma-chan12-tx", "edma-chan13-tx", + "edma-chan14-tx", "edma-chan15-tx"; + status = "okay"; + }; + + edma2: dma-controller@591F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ + <0x0 0x59210000 0x0 0x10000>, + <0x0 0x59220000 0x0 0x10000>, + <0x0 0x59230000 0x0 0x10000>, + <0x0 0x59240000 0x0 0x10000>, + <0x0 0x59250000 0x0 0x10000>, + <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ + <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ + <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59350000 0x0 0x10000>, + <0x0 0x59370000 0x0 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <16>; + interrupts = , /* asrc 0 */ + , + , + , + , + , + , /* esai0 */ + , + , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc0 */ + "edma-chan2-tx", "edma-chan3-tx", + "edma-chan4-tx", "edma-chan5-tx", + "edma-chan6-tx", "edma-chan7-tx", /* esai0 */ + "edma-chan8-tx", "edma-chan9-tx", /* spdif0 */ + "edma-chan12-tx", "edma-chan13-tx", /* sai0 */ + "edma-chan14-tx", "edma-chan15-tx", /* sai1 */ + "edma-chan21-tx", /* gpt5 */ + "edma-chan23-tx"; /* gpt7 */ + status = "okay"; + }; + + edma3: dma-controller@599F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ + <0x0 0x59A10000 0x0 0x10000>, + <0x0 0x59A20000 0x0 0x10000>, + <0x0 0x59A30000 0x0 0x10000>, + <0x0 0x59A40000 0x0 0x10000>, + <0x0 0x59A50000 0x0 0x10000>, + <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */ + <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */ + <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <9>; + interrupts = , /* asrc 1 */ + , + , + , + , + , + , /* sai4 */ + , + ; /* sai5 */ + interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc1 */ + "edma-chan2-tx", "edma-chan3-tx", + "edma-chan4-tx", "edma-chan5-tx", + "edma-chan8-tx", "edma-chan9-tx", /* sai4 */ + "edma-chan10-tx"; /* sai5 */ + status = "okay"; + }; + + acm: acm@59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x0 0x59e00000 0x0 0x1D0000>; + status = "disabled"; + }; + + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59040000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_0_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma2 12 0 1>, <&edma2 13 0 0>; + status = "disabled"; + power-domains = <&pd_sai0>; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59050000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_1_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma2 14 0 1>, <&edma2 15 0 0>; + status = "disabled"; + power-domains = <&pd_sai1>; + }; + + sai4: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59820000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_4_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_4_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + dmas = <&edma3 8 0 1>, <&edma3 9 0 0>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + status = "disabled"; + power-domains = <&pd_sai4>; + }; + + sai5: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59830000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_5_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_5_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma3 10 0 0>; + status = "disabled"; + power-domains = <&pd_sai5>; + }; + + amix: amix@59840000 { + compatible = "fsl,imx8qm-amix"; + reg = <0x0 0x59840000 0x0 0x10000>; + clocks = <&clk IMX8QXP_AUD_AMIX_IPG>; + clock-names = "ipg"; + power-domains = <&pd_amix>; + status = "disabled"; + }; + + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc0"; + reg = <0x0 0x59000000 0x0 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>, + <&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc0>; + status = "disabled"; + }; + + asrc1: asrc@59800000 { + compatible = "fsl,imx8qm-asrc1"; + reg = <0x0 0x59800000 0x0 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>, + <&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc1>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x0 0x59850000 0x0 0x10000>; + clocks = <&clk IMX8QXP_AUD_MQS_IPG>, + <&clk IMX8QXP_AUD_MQS_HMCLK>; + clock-names = "core", "mclk"; + power-domains = <&pd_mqs0>; + status = "disabled"; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, + <&clk IMX8QXP_SDHC0_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC0_DIV>; + assigned-clock-rates = <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: usdhc@5b020000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b020000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, + <&clk IMX8QXP_SDHC1_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC1_DIV>; + assigned-clock-rates = <200000000>; + power-domains = <&pd_conn_sdch1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: usdhc@5b030000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b030000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, + <&clk IMX8QXP_SDHC2_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC2_DIV>; + assigned-clock-rates = <200000000>; + power-domains = <&pd_conn_sdch2>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; + reg = <0x0 0x5b040000 0x0 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, + <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>, + <&clk IMX8QXP_ENET0_REF_DIV>, + <&clk IMX8QXP_ENET0_PTP_CLK>; + assigned-clock-rates = <250000000>, <125000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd_conn_enet0>; + status = "disabled"; + }; + + fec2: ethernet@5b050000 { + compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; + reg = <0x0 0x5b050000 0x0 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, + <&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>, + <&clk IMX8QXP_ENET1_REF_DIV>, + <&clk IMX8QXP_ENET1_PTP_CLK>; + assigned-clock-rates = <250000000>, <125000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd_conn_enet1>; + status = "disabled"; + }; + + mlb: mlb@5B060000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0 0x5B060000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, + <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_MLB_CLK>, + <&clk IMX8QXP_MLB_HCLK>, + <&clk IMX8QXP_MLB_IPG_CLK>; + clock-names = "mlb", "hclk", "ipg"; + assigned-clocks = <&clk IMX8QXP_MLB_CLK>, + <&clk IMX8QXP_MLB_HCLK>, + <&clk IMX8QXP_MLB_IPG_CLK>; + assigned-clock-rates = <333333333>, <333333333>, <83333333>; + power-domains = <&pd_conn_mlb0>; + status = "disabled"; + }; + + hifi4: hifi4@586e8000 { + compatible = "fsl,imx8qxp-hifi4"; + reg = <0x0 0x596e8000 0x0 0x88000>; + clocks = <&clk IMX8QXP_AUD_HIFI_IPG>, + <&clk IMX8QXP_AUD_OCRAM_IPG>, + <&clk IMX8QXP_AUD_HIFI_CORE_CLK>; + clock-names = "ipg", "ocram", "core"; + fsl,hifi4-firmware = "imx/hifi/hifi4.bin"; + power-domains = <&pd_hifi>; + }; + + esai0: esai@59010000 { + compatible = "fsl,imx6ull-esai"; + reg = <0x0 0x59010000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>, + <&clk IMX8QXP_AUD_ESAI_0_IPG>; + clock-names = "core", "extal", "fsys"; + dmas = <&edma2 6 0 1>, <&edma2 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd_esai0>; + status = "disabled"; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x0 0x59020000 0x0 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */ + <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8QXP_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma2 8 0 5>, <&edma2 9 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd_spdif0>; + status = "disabled"; + }; + + flexspi0: flexspi@05d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-flexspi"; + reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x19ffffff>; + reg-names = "FlexSPI", "FlexSPI-memory"; + interrupts = ; + clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>, + <&clk IMX8QXP_LSIO_FSPI0_CLK>; + assigned-clock-rates = <29000000>,<29000000>; + clock-names = "qspi_en", "qspi"; + power-domains = <&pd_lsio_flexspi0>; + status = "disabled"; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu_disp0>, <&dpu_disp1>; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + hsio: hsio@5f080000 { + compatible = "fsl,imx8qm-hsio", "syscon"; + reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ + }; + + pcieb: pcie@0x5f010000 { + /* + * pcieb phyx1 lane1 in default, adjust it refer to the + * exact hw design. + */ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/ + <0x0 0x7ff00000 0x0 0x10000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>, + <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>, + <&clk IMX8QXP_HSIO_PHY_X1_PCLK>, + <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + power-domains = <&pd_pcie>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + hsio = <&hsio>; + ctrl-id = <1>; /* pcieb */ + cpu-base-addr = <0x80000000>; + status = "disabled"; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; +}; + +&A35_0 { + operating-points = < + /* kHz uV */ + 1200000 1150000 + >; + clocks = <&clk IMX8QXP_A35_DIV>; +}; diff --git a/arch/arm/dts/imx6dl-arm2.dts b/arch/arm/dts/imx6dl-arm2.dts new file mode 100644 index 00000000000..04300dee553 --- /dev/null +++ b/arch/arm/dts/imx6dl-arm2.dts @@ -0,0 +1,259 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include +#include "imx6dl.dtsi" + +/ { + model = "Freescale i.MX6 DualLite Armadillo2 Board"; + compatible = "fsl,imx6q-arm2", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + leds { + compatible = "gpio-leds"; + + debug-led { + label = "Heartbeat"; + gpios = <&gpio3 25 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "disabled"; /* gpmi nand conflicts with SD */ + nand-on-flash-bbt; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbh2_1: usbh2grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 + >; + }; + + pinctrl_usbh2_2: usbh2grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 + >; + }; + + pinctrl_usbh3_1: usbh3grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 + >; + }; + + pinctrl_usbh3_2: usbh3grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc3 { + cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + status = "okay"; +}; + +&usdhc4 { + non-removable; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,dte-mode; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl-sabreauto-ecspi.dts b/arch/arm/dts/imx6dl-sabreauto-ecspi.dts new file mode 100644 index 00000000000..45ae1628362 --- /dev/null +++ b/arch/arm/dts/imx6dl-sabreauto-ecspi.dts @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl-sabreauto-gpmi-weim.dts b/arch/arm/dts/imx6dl-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000..ad2e937d4ff --- /dev/null +++ b/arch/arm/dts/imx6dl-sabreauto-gpmi-weim.dts @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl-sabreauto.dts b/arch/arm/dts/imx6dl-sabreauto.dts new file mode 100644 index 00000000000..bd13b359209 --- /dev/null +++ b/arch/arm/dts/imx6dl-sabreauto.dts @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sabreauto.dtsi" + +/ { + model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; + compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; +}; +&ldb { + lvds-channel@0 { + crtc = "ipu1-di0"; + }; + lvds-channel@1 { + crtc = "ipu1-di1"; + }; +}; +&mxcfb1 { + status = "okay"; +}; +&mxcfb2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl-sabresd.dts b/arch/arm/dts/imx6dl-sabresd.dts new file mode 100644 index 00000000000..52ebc682516 --- /dev/null +++ b/arch/arm/dts/imx6dl-sabresd.dts @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sabresd.dtsi" + +/ { + model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; + compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; +}; + +&battery { + offset-charger = <1485>; + offset-discharger = <1464>; + offset-usb-charger = <1285>; +}; + +&iomuxc { + epdc { + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000 + MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000 + MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000 + MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000 + MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000 + MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000 + MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000 + MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000 + MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000 + MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000 + MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000 + MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000 + MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000 + MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000 + MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000 + MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000 + MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000 + MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000 + MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000 + MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000 + >; + }; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&i2c3 { + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <1>; + vpos_pwrup = <2>; + gvdd_pwrup = <1>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <1>; + vneg_pwrdn = <1>; + SENSOR-supply = <®_sensor>; + gpio_pmic_pwrgood = <&gpio2 21 0>; + gpio_pmic_vcom_ctrl = <&gpio3 17 0>; + gpio_pmic_wakeup = <&gpio3 20 0>; + gpio_pmic_v3p3 = <&gpio2 20 0>; + gpio_pmic_intr = <&gpio2 25 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* 2's-compliment, -4325000 */ + regulator-min-microvolt = <0xffbe0178>; + /* 2's-compliment, -500000 */ + regulator-max-microvolt = <0xfff85ee0>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu1-di0"; + }; + + lvds-channel@1 { + crtc = "ipu1-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&pxp { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi index 9a4c22c2dad..a004478265a 100644 --- a/arch/arm/dts/imx6dl.dtsi +++ b/arch/arm/dts/imx6dl.dtsi @@ -1,6 +1,6 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -21,7 +21,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; @@ -43,9 +43,13 @@ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; + <&clks IMX6QDL_CLK_PLL1_SYS>, + <&clks IMX6QDL_CLK_PLL1>, + <&clks IMX6QDL_PLL1_BYPASS>, + <&clks IMX6QDL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; @@ -59,10 +63,60 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + soc { - ocram: sram@00900000 { + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>, + <&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>, + <&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> , + <&clks IMX6QDL_CLK_PLL3_PFD1_540M>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m"; + interrupts = <0 107 0x04>, <0 112 0x4>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + fsl,max_ddr_freq = <400000000>; + }; + + gpu@00130000 { + compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x0 0x0>, <0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_DUMMY>; + clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk", + "gpu2d_clk", "gpu3d_clk", + "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>; + reset-names = "gpu3d", "gpu2d"; + power-domains = <&gpc 1>; + }; + + ocram: sram@00905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x00905000 0x1B000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; @@ -71,14 +125,27 @@ compatible = "fsl,imx6dl-iomuxc"; }; + dcic2: dcic@020e8000 { + clocks = <&clks IMX6QDL_CLK_DCIC1 >, + <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/ + clock-names = "dcic", "disp-axi"; + }; + pxp: pxp@020f0000 { + compatible = "fsl,imx6dl-pxp-dma"; reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; epdc: epdc@020f4000 { + compatible = "fsl,imx6dl-epdc"; reg = <0x020f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>; + clock-names = "epdc_axi", "epdc_pix"; }; lcdif: lcdif@020f8000 { @@ -88,6 +155,16 @@ }; aips2: aips-bus@02100000 { + mipi_dsi: mipi@021e0000 { + compatible = "fsl,imx6dl-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 0x04>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; + }; + i2c4: i2c@021f8000 { #address-cells = <1>; #size-cells = <0>; @@ -99,35 +176,28 @@ }; }; }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu1_di0>, <&ipu1_di1>; - }; - - gpu-subsystem { - compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu_2d>, <&gpu_3d>; - }; -}; - -&gpt { - compatible = "fsl,imx6dl-gpt"; -}; - -&hdmi { - compatible = "fsl,imx6dl-hdmi"; }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb"; + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; + clock-names = "ldb_di0", "ldb_di1", "di0_sel", "di1_sel", - "di0", "di1"; + "di2_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel"; }; &vpu { compatible = "fsl,imx6dl-vpu", "cnm,coda960"; }; + +&vpu_fsl { + iramsize = <0>; +}; diff --git a/arch/arm/dts/imx6q-arm2.dts b/arch/arm/dts/imx6q-arm2.dts new file mode 100644 index 00000000000..e92fffc6847 --- /dev/null +++ b/arch/arm/dts/imx6q-arm2.dts @@ -0,0 +1,259 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include +#include "imx6q.dtsi" + +/ { + model = "Freescale i.MX6 Quad Armadillo2 Board"; + compatible = "fsl,imx6q-arm2", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + leds { + compatible = "gpio-leds"; + + debug-led { + label = "Heartbeat"; + gpios = <&gpio3 25 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "disabled"; /* gpmi nand conflicts with SD */ + nand-on-flash-bbt; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbh2_1: usbh2grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 + >; + }; + + pinctrl_usbh2_2: usbh2grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 + >; + }; + + pinctrl_usbh3_1: usbh3grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 + >; + }; + + pinctrl_usbh3_2: usbh3grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc3 { + cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + status = "okay"; +}; + +&usdhc4 { + non-removable; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,dte-mode; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-pop-arm2.dts b/arch/arm/dts/imx6q-pop-arm2.dts new file mode 100644 index 00000000000..dce61a444d9 --- /dev/null +++ b/arch/arm/dts/imx6q-pop-arm2.dts @@ -0,0 +1,439 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include +#include "imx6q.dtsi" + +/ { + model = "Freescale i.MX6 Quad Armadillo2 Board"; + compatible = "fsl,imx6q-pop-arm2", "fsl,imx6q"; + + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + }; + + pwm-backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; + power-supply = <®_lvds_3p3v>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <94>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio3 30 1>; + linux,code = <116>; + gpio-key,wakeup; + }; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + lvds_share { + gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + linux,usable-memory = <0x10000000 0x20000000>, + <0x80000000 0x20000000>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str = "1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + reg_lvds_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "LVDS-3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + }; +}; + +&cpu0 { + fsl,arm-soc-shared = <1>; +}; + +&busfreq { + fsl,max_ddr_freq = <400000000>; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds0"; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio3>; + interrupts = <31 2>; + wakeup-gpios = <&gpio3 31 0>; + }; + + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + max7310_a: gpio@1b { + compatible = "maxim,max7310"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_b: gpio@1f { + compatible = "maxim,max7310"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 + MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_hdmi_hdcp: hdmihdcpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "ipu2-di0"; + primary; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,dte-mode; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc3 { + cd-gpios = <&gpio6 11 0>; + wp-gpios = <&gpio6 14 0>; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + status = "okay"; +}; + +&usdhc4 { + non-removable; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-sabreauto-ecspi.dts b/arch/arm/dts/imx6q-sabreauto-ecspi.dts new file mode 100644 index 00000000000..3cf99ed9be6 --- /dev/null +++ b/arch/arm/dts/imx6q-sabreauto-ecspi.dts @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; diff --git a/arch/arm/dts/imx6q-sabreauto-gpmi-weim.dts b/arch/arm/dts/imx6q-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000..579aeb26e05 --- /dev/null +++ b/arch/arm/dts/imx6q-sabreauto-gpmi-weim.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-sabreauto.dts b/arch/arm/dts/imx6q-sabreauto.dts new file mode 100644 index 00000000000..a321a20832d --- /dev/null +++ b/arch/arm/dts/imx6q-sabreauto.dts @@ -0,0 +1,45 @@ +/* + * Copyright 2012-2015 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sabreauto.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Automotive Board"; + compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; +&mxcfb1 { + status = "okay"; +}; +&mxcfb2 { + status = "okay"; +}; +&mxcfb3 { + status = "okay"; +}; +&mxcfb4 { + status = "okay"; +}; +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-sabresd.dts b/arch/arm/dts/imx6q-sabresd.dts new file mode 100644 index 00000000000..a63e1b66a6b --- /dev/null +++ b/arch/arm/dts/imx6q-sabresd.dts @@ -0,0 +1,57 @@ +/* + * Copyright 2012=2015 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sabresd.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Smart Device Board"; + compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; +}; + +&battery { + offset-charger = <1900>; + offset-discharger = <1694>; + offset-usb-charger = <1685>; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi index c30c8368cae..49fb0028ccb 100644 --- a/arch/arm/dts/imx6q.dtsi +++ b/arch/arm/dts/imx6q.dtsi @@ -1,6 +1,6 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -48,9 +48,15 @@ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; + <&clks IMX6QDL_CLK_PLL1_SYS>, + <&clks IMX6QDL_CLK_PLL1>, + <&clks IMX6QDL_PLL1_BYPASS>, + <&clks IMX6QDL_PLL1_BYPASS_SRC>, + <&clks IMX6QDL_CLK_VPU_AXI_PODF>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src", + "vpu_axi_podf"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; @@ -78,10 +84,58 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + soc { - ocram: sram@00900000 { + busfreq: busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, + <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc"; + interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + fsl,max_ddr_freq = <528000000>; + }; + + gpu@00130000 { + compatible = "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x02204000 0x4000>, <0x10000000 0x0>, + <0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "iobase_vg", "phys_baseaddr", + "contiguous_mem"; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d", "irq_vg"; + clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>; + clock-names = "gpu2d_axi_clk", "openvg_axi_clk", + "gpu3d_axi_clk", "gpu2d_clk", + "gpu3d_clk", "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>, <&src 3>; + reset-names = "gpu3d", "gpu2d", "gpuvg"; + power-domains = <&gpc 1>; + }; + + ocram: sram@00905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x40000>; + reg = <0x00905000 0x3B000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; @@ -104,6 +158,54 @@ iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6q-iomuxc"; + + ipu2 { + pinctrl_ipu2_1: ipu2grp-1 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000 + MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10 + >; + }; + }; + }; + }; + + aips-bus@02100000 { /* AIPS2 */ + mipi_dsi: mipi@021e0000 { + compatible = "fsl,imx6q-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 0x04>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; }; }; @@ -118,16 +220,6 @@ status = "disabled"; }; - gpu_vg: gpu@02204000 { - compatible = "vivante,gc"; - reg = <0x02204000 0x4000>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_GPU2D_CORE>; - clock-names = "bus", "core"; - power-domains = <&gpc 1>; - }; - ipu2: ipu@02800000 { #address-cells = <1>; #size-cells = <0>; @@ -136,163 +228,38 @@ interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU2>, - <&clks IMX6QDL_CLK_IPU2_DI0>, - <&clks IMX6QDL_CLK_IPU2_DI1>; - clock-names = "bus", "di0", "di1"; - resets = <&src 4>; - - ipu2_csi0: port@0 { - reg = <0>; - }; - - ipu2_csi1: port@1 { - reg = <1>; - }; - - ipu2_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; + <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; - ipu2_di0_disp0: disp0-endpoint { - }; - - ipu2_di0_hdmi: hdmi-endpoint { - remote-endpoint = <&hdmi_mux_2>; - }; - - ipu2_di0_mipi: mipi-endpoint { - remote-endpoint = <&mipi_mux_2>; - }; - - ipu2_di0_lvds0: lvds0-endpoint { - remote-endpoint = <&lvds0_mux_2>; - }; - - ipu2_di0_lvds1: lvds1-endpoint { - remote-endpoint = <&lvds1_mux_2>; - }; - }; - - ipu2_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu2_di1_hdmi: hdmi-endpoint { - remote-endpoint = <&hdmi_mux_3>; - }; - - ipu2_di1_mipi: mipi-endpoint { - remote-endpoint = <&mipi_mux_3>; - }; - - ipu2_di1_lvds0: lvds0-endpoint { - remote-endpoint = <&lvds0_mux_3>; - }; + resets = <&src 4>; + bypass_reset = <0>; - ipu2_di1_lvds1: lvds1-endpoint { - remote-endpoint = <&lvds1_mux_3>; - }; }; }; }; - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; - }; - - gpu-subsystem { - compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>; - }; -}; - -&hdmi { - compatible = "fsl,imx6q-hdmi"; - - port@2 { - reg = <2>; - - hdmi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_hdmi>; - }; - }; - - port@3 { - reg = <3>; - - hdmi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_hdmi>; - }; - }; -}; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; + + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; - - lvds-channel@0 { - port@2 { - reg = <2>; - - lvds0_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_lvds0>; - }; - }; - - port@3 { - reg = <3>; - - lvds0_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_lvds0>; - }; - }; - }; + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; + clock-names = "ldb_di0", "ldb_di1", + "di0_sel", "di1_sel", + "di2_sel", "di3_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel"; - lvds-channel@1 { - port@2 { - reg = <2>; - - lvds1_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_lvds1>; - }; - }; - - port@3 { - reg = <3>; - - lvds1_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_lvds1>; - }; - }; - }; -}; - -&mipi_dsi { - ports { - port@2 { - reg = <2>; - - mipi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_mipi>; - }; - }; - - port@3 { - reg = <3>; - - mipi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_mipi>; - }; - }; - }; }; &vpu { diff --git a/arch/arm/dts/imx6qdl-sabreauto.dtsi b/arch/arm/dts/imx6qdl-sabreauto.dtsi new file mode 100644 index 00000000000..992ee81c628 --- /dev/null +++ b/arch/arm/dts/imx6qdl-sabreauto.dtsi @@ -0,0 +1,1167 @@ +/* + * Copyright 2012-2015 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +/ { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + gpio-keys { + compatible = "gpio-keys1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + home { + label = "Home"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + + back { + label = "Back"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + + program { + label = "Program"; + gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + }; + + memory: memory { + reg = <0x10000000 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + user { + label = "debug"; + gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_h1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_vio1: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vio1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_vio2: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vio2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_vd: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_va: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "va"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_sd3_vmmc: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "P3V3_SDa_SWITCHED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* remove below line to enable this regulator */ + status = "disabled"; + }; + + reg_can_en: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds_share { + gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + clocks { + codec_osc: anaclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai>; + asrc-controller = <&asrc>; + audio-codec = <&codec>; + }; + + sound-fm { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si4763"; + ssi-controller = <&ssi2>; + fm-controller = <&si476x_codec>; + mux-int-port = <2>; + mux-ext-port = <5>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx-sabreauto-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + status = "okay"; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, + <&clks IMX6QDL_PLL4_BYPASS>, + <&clks IMX6QDL_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, + <&clks IMX6QDL_PLL4_BYPASS_SRC>; + assigned-clock-rates = <0>, <0>, <24576000>; + fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; + fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds0"; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + status = "disabled"; /* pin conflict with WEIM NOR */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai>; + assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>, + <&clks IMX6QDL_CLK_ESAI_EXTAL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + fsl,magic-packet; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */ + xceiver-supply = <®_can_stby>; + status = "disabled"; /* pin conflict with fec */ +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "disabled"; /* pin conflict with uart3 */ + nand-on-flash-bbt; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio2>; + interrupts = <28 2>; + wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + }; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&codec_osc>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + }; + + si4763: si4763@63 { + compatible = "si4761"; + reg = <0x63>; + va-supply = <®_si4763_va>; + vd-supply = <®_si4763_vd>; + vio1-supply = <®_si4763_vio1>; + vio2-supply = <®_si4763_vio2>; + revision-a10; /* set to default A10 compatible command set */ + + si476x_codec: si476x-codec { + compatible = "si476x-codec"; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + status = "okay"; + + adv7180: adv7180@21 { + compatible = "adv,adv7180"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_1>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + pwn-gpios = <&max7310_b 2 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + cvbs = <1>; + }; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio5>; + interrupts = <17 2>; + }; + + max7310_a: gpio@30 { + compatible = "maxim,max7310"; + reg = <0x30>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_b: gpio@32 { + compatible = "maxim,max7310"; + reg = <0x32>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_c: gpio@34 { + compatible = "maxim,max7310"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + interrupt-parent = <&gpio2>; + interrupts = <29 1>; + }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <7>; + interrupt-parent = <&gpio6>; + interrupts = <31 8>; + interrupt-route = <1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-sabreauto { + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1f059 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 + MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x17059 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x17059 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi1_cs: ecspi1cs { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_esai: esaigrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 + MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 + MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 + MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 + MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 + MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 + MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 + MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 + MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b8b1 + >; + }; + + pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b8b1 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b8b1 + >; + }; + + pinctrl_mlb: mlb { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000 + MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000 + MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000 + >; + }; + + pinctrl_pwm3: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + >; + }; + + pinctrl_weim_cs0: weimcs0grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor: weimnorgrp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6QDL_CLK_SPDIF_SEL>, + <&clks IMX6QDL_CLK_SPDIF_PODF>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_PFD3_454M>; + assigned-clock-rates = <0>, <227368421>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi2 { + assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>; + fsl,mode = "i2s-master"; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */ + <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */ + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + /* + * Due to board issue, we can not use external regulator for card slot + * by default since the card power is shared with card detect pullup. + * Disabling the vmmc regulator will cause unexpected card detect + * interrupts. + * HW rework is needed to fix this isssue. Remove R695 first, then you + * can open below line to enable the using of external regulator. + * Then you will be able to power off the card during suspend. This is + * especially needed for a SD3.0 card re-enumeration working on UHS mode + * Note: reg_sd3_vmmc is also need to be enabled + */ + /* vmmc-supply = <®_sd3_vmmc>; */ + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x08000000>; + status = "disabled"; /* pin conflict with SPI NOR */ + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +}; diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi new file mode 100644 index 00000000000..93c154bb688 --- /dev/null +++ b/arch/arm/dts/imx6qdl-sabresd.dtsi @@ -0,0 +1,1096 @@ +/* + * Copyright 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +/ { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio2 24 1>; + uok_input = <&gpio1 27 1>; + chg_input = <&gpio3 23 1>; + flt_input = <&gpio5 2 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,usb_valid; + status = "okay"; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + lvds0 { + gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + }; + lvds1 { + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + }; + + chosen { + stdout-path = &uart1; + }; + + leds { + compatible = "gpio-leds"; + + charger-led { + gpios = <&gpio1 2 0>; + linux,default-trigger = "max8903-charger-charging"; + retain-state-suspended; + }; + }; + + memory: memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_usb_h1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 29 0>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_audio: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "wm8962-supply"; + gpio = <&gpio4 10 0>; + enable-active-high; + }; + + reg_pcie: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 19 0>; + regulator-always-on; + enable-active-high; + }; + + reg_sensor: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "sensor-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 0>; + startup-delay-us = <500>; + enable-active-high; + }; + + reg_hdmi: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "hdmi-5v-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + hdmi-5v-supply = <&swbst_reg>; + }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio6 14 0>; + enable-active-high; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; + }; + + sound { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&ssi2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + mux-int-port = <2>; + mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio7 8 1>; + mic-det-gpios = <&gpio1 9 1>; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "okay"; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + status = "okay"; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + reset-delay-us = <50>; + #reset-cells = <0>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&clks { + fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; + fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 9 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 0>; + fsl,magic-packet; + status = "okay"; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds1"; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + HDMI-supply = <®_hdmi>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + amic-mono; + }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <0>; + vdd-supply = <®_sensor>; + vddio-supply = <®_sensor>; + interrupt-parent = <&gpio1>; + interrupts = <18 8>; + interrupt-route = <1>; + }; + + ov564x: ov564x@3c { + compatible = "ovti,ov564x"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_2>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3, + on rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */ + rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <8 2>; + wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + }; + + max11801@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <26 2>; + work-mode = <1>;/*DCM mode*/ + }; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */ + compatible = "ovti,ov564x_mipi"; + reg = <0x3c>; + clocks = <&clks 201>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 + rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */ + rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */ + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <7 2>; + wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + }; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + vdd-supply = <®_sensor>; + interrupt-parent = <&gpio3>; + interrupts = <9 2>; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + vdd-supply = <®_sensor>; + vddio-supply = <®_sensor>; + interrupt-parent = <&gpio3>; + interrupts = <16 1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-sabresd { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c2_egalax_int: egalax_i2c2_intgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 + >; + }; + + pinctrl_i2c3_egalax_int: egalax_i2c3_intgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_hdmi_hdcp: hdmihdcpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b8b1 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b8b1 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000 + >; + }; + }; + + gpio_leds { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&mipi_csi { + status = "okay"; + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; +}; + +&mipi_dsi { + dev_id = <0>; + disp_id = <1>; + lcd_panel = "TRULY-WVGA"; + disp-power-on-supply = <®_mipi_dsi_pwr_on>; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 0>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi index e04b57089a6..6221d659a32 100644 --- a/arch/arm/dts/imx6qdl.dtsi +++ b/arch/arm/dts/imx6qdl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -31,10 +31,6 @@ i2c1 = &i2c2; i2c2 = &i2c3; ipu0 = &ipu1; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mmc3 = &usdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -46,6 +42,17 @@ spi3 = &ecspi4; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + usb0 = &usbotg; + usb1 = &usbh1; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; }; clocks { @@ -77,7 +84,11 @@ compatible = "simple-bus"; interrupt-parent = <&gpc>; ranges; - u-boot,dm-spl; + + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x00100000 0x3fff>; + }; dma_apbh: dma-apbh@00110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; @@ -92,6 +103,16 @@ clocks = <&clks IMX6QDL_CLK_APBH_DMA>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <0 20 0x04>; + secvio_src = <0x8000001d>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + gpmi: gpmi-nand@00112000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; @@ -112,53 +133,16 @@ status = "disabled"; }; - hdmi: hdmi@0120000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00120000 0x9000>; - interrupts = <0 115 0x04>; - gpr = <&gpr>; - clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, - <&clks IMX6QDL_CLK_HDMI_ISFR>; - clock-names = "iahb", "isfr"; - status = "disabled"; - - port@0 { - reg = <0>; - - hdmi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_hdmi>; - }; - }; - - port@1 { - reg = <1>; - - hdmi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_hdmi>; - }; - }; - }; - - gpu_3d: gpu@00130000 { - compatible = "vivante,gc"; - reg = <0x00130000 0x4000>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, - <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>; - clock-names = "bus", "core", "shader"; - power-domains = <&gpc 1>; + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - gpu_2d: gpu@00134000 { - compatible = "vivante,gc"; - reg = <0x00134000 0x4000>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_GPU2D_CORE>; - clock-names = "bus", "core"; - power-domains = <&gpc 1>; + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; }; timer@00a00600 { @@ -169,15 +153,6 @@ clocks = <&clks IMX6QDL_CLK_TWD>; }; - intc: interrupt-controller@00a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - L2: l2-cache@00a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; @@ -186,7 +161,6 @@ cache-level = <2>; arm,tag-latency = <4 2 3>; arm,data-latency = <4 2 3>; - arm,shared-override; }; pcie: pcie@0x01000000 { @@ -197,7 +171,8 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ + ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ + 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; interrupts = ; @@ -220,13 +195,51 @@ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; + hdmi_core: hdmi_core@00120000 { + compatible = "fsl,imx6q-hdmi-core"; + reg = <0x00120000 0x9000>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_video: hdmi_video@020e0000 { + compatible = "fsl,imx6q-hdmi-video"; + reg = <0x020e0000 0x1000>; + reg-names = "hdmi_gpr"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_audio: hdmi_audio@00120000 { + compatible = "fsl,imx6q-hdmi-audio"; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + dmas = <&sdma 2 25 0>; + dma-names = "tx"; + status = "disabled"; + }; + + hdmi_cec: hdmi_cec@00120000 { + compatible = "fsl,imx6q-hdmi-cec"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + aips-bus@02000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - u-boot,dm-spl; spba-bus@02000000 { compatible = "fsl,spba-bus", "simple-bus"; @@ -245,13 +258,13 @@ clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, - <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, + <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", "rxtx5", "rxtx6", - "rxtx7", "spba"; + "rxtx7", "dma"; status = "disabled"; }; @@ -264,7 +277,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI1>, <&clks IMX6QDL_CLK_ECSPI1>; clock-names = "ipg", "per"; - dmas = <&sdma 3 8 1>, <&sdma 4 8 2>; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -278,7 +291,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI2>, <&clks IMX6QDL_CLK_ECSPI2>; clock-names = "ipg", "per"; - dmas = <&sdma 5 8 1>, <&sdma 6 8 2>; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -292,7 +305,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI3>, <&clks IMX6QDL_CLK_ECSPI3>; clock-names = "ipg", "per"; - dmas = <&sdma 7 8 1>, <&sdma 8 8 2>; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -306,7 +319,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI4>, <&clks IMX6QDL_CLK_ECSPI4>; clock-names = "ipg", "per"; - dmas = <&sdma 9 8 1>, <&sdma 10 8 2>; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -333,7 +346,7 @@ <&clks IMX6QDL_CLK_ESAI_EXTAL>, <&clks IMX6QDL_CLK_ESAI_IPG>, <&clks IMX6QDL_CLK_SPBA>; - clock-names = "core", "mem", "extal", "fsys", "spba"; + clock-names = "core", "mem", "extal", "fsys", "dma"; dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -348,8 +361,8 @@ clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, <&clks IMX6QDL_CLK_SSI1>; clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; + dmas = <&sdma 37 22 0>, + <&sdma 38 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -364,8 +377,8 @@ clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, <&clks IMX6QDL_CLK_SSI2>; clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; + dmas = <&sdma 41 22 0>, + <&sdma 42 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -380,8 +393,8 @@ clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, <&clks IMX6QDL_CLK_SSI3>; clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; + dmas = <&sdma 45 22 0>, + <&sdma 46 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -402,7 +415,7 @@ "asrck_1", "asrck_2", "asrck_3", "asrck_4", "asrck_5", "asrck_6", "asrck_7", "asrck_8", "asrck_9", "asrck_a", "asrck_b", "asrck_c", - "asrck_d", "asrck_e", "asrck_f", "spba"; + "asrck_d", "asrck_e", "asrck_f", "dma"; dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; dma-names = "rxa", "rxb", "rxc", @@ -426,9 +439,26 @@ clocks = <&clks IMX6QDL_CLK_VPU_AXI>, <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; clock-names = "per", "ahb"; - power-domains = <&gpc 1>; resets = <&src 1>; iram = <&ocram>; + status = "disabled"; + }; + + vpu_fsl: vpu_fsl@02040000 { + compatible = "fsl,imx6-vpu"; + reg = <0x02040000 0x3c000>; + reg-names = "vpu_regs"; + interrupts = <0 3 IRQ_TYPE_EDGE_RISING>, + <0 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq"; + clocks = <&clks IMX6QDL_CLK_VPU_AXI>, + <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, + <&clks IMX6QDL_CLK_OCRAM>; + clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram"; + iramsize = <0x21000>; + iram = <&ocram>; + resets = <&src 1>; + power-domains = <&gpc 1>; }; aipstz@0207c000 { /* AIPSTZ1 */ @@ -486,6 +516,7 @@ clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, <&clks IMX6QDL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x34 28 0x10 17>; status = "disabled"; }; @@ -496,6 +527,7 @@ clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, <&clks IMX6QDL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x34 29 0x10 18>; status = "disabled"; }; @@ -518,7 +550,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - u-boot,dm-spl; }; gpio2: gpio@020a0000 { @@ -625,7 +656,7 @@ <0 54 IRQ_TYPE_LEVEL_HIGH>, <0 127 IRQ_TYPE_LEVEL_HIGH>; - regulator-1p1 { + regulator-1p1@110 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <800000>; @@ -637,23 +668,24 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; - regulator-3p0 { + reg_3p0: regulator-3p0@120 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; anatop-vol-bit-width = <5>; anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; - regulator-2p5 { + regulator-2p5@130 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2000000>; @@ -665,9 +697,10 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2000000>; anatop-max-voltage = <2750000>; + anatop-enable-bit = <0>; }; - reg_arm: regulator-vddcore { + reg_arm: regulator-vddcore@140 { compatible = "fsl,anatop-regulator"; regulator-name = "vddarm"; regulator-min-microvolt = <725000>; @@ -682,9 +715,10 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; - reg_pu: regulator-vddpu { + reg_pu: regulator-vddpu@140 { compatible = "fsl,anatop-regulator"; regulator-name = "vddpu"; regulator-min-microvolt = <725000>; @@ -699,9 +733,10 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; - reg_soc: regulator-vddsoc { + reg_soc: regulator-vddsoc@140 { compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; @@ -716,6 +751,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; }; @@ -732,6 +768,7 @@ reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; @@ -740,9 +777,27 @@ reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; + usbphy_nop1: usbphy_nop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6QDL_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + + usbphy_nop2: usbphy_nop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6QDL_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + + caam_snvs: caam-snvs@020cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x020cc000 0x4000>; + }; + snvs: snvs@020cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -759,7 +814,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; status = "disabled"; }; }; @@ -796,7 +851,8 @@ <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_VPU_AXI>; + <&clks IMX6QDL_CLK_VPU_AXI>, + <&clks IMX6QDL_CLK_IPG>; #power-domain-cells = <1>; }; @@ -808,13 +864,11 @@ iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; reg = <0x020e0000 0x4000>; - u-boot,dm-spl; }; ldb: ldb@020e0008 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; gpr = <&gpr>; status = "disabled"; @@ -823,22 +877,6 @@ #size-cells = <0>; reg = <0>; status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@1 { - reg = <1>; - - lvds0_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds0>; - }; - }; }; lvds-channel@1 { @@ -846,33 +884,27 @@ #size-cells = <0>; reg = <1>; status = "disabled"; - - port@0 { - reg = <0>; - - lvds1_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds1>; - }; - }; - - port@1 { - reg = <1>; - - lvds1_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds1>; - }; - }; }; }; dcic1: dcic@020e4000 { + compatible = "fsl,imx6q-dcic"; reg = <0x020e4000 0x4000>; interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; }; dcic2: dcic@020e8000 { + compatible = "fsl,imx6q-dcic"; reg = <0x020e8000 0x4000>; interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; }; sdma: sdma@020ec000 { @@ -893,33 +925,31 @@ #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; - u-boot,dm-spl; crypto: caam@2100000 { - compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; - clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, - <&clks IMX6QDL_CLK_CAAM_ACLK>, - <&clks IMX6QDL_CLK_CAAM_IPG>, - <&clks IMX6QDL_CLK_EIM_SLOW>; - clock-names = "mem", "aclk", "ipg", "emi_slow"; - - sec_jr0: jr0@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr1@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2100000 0x40000>; + ranges = <0 0x2100000 0x40000>; + interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */ + clocks = <&clks IMX6QDL_CAAM_MEM>, <&clks IMX6QDL_CAAM_ACLK>, <&clks IMX6QDL_CAAM_IPG> ,<&clks IMX6QDL_CLK_EIM_SLOW>; + clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow"; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 105 0x4>; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 106 0x4>; + }; }; - }; aipstz@0217c000 { /* AIPSTZ2 */ reg = <0x0217c000 0x4000>; @@ -935,6 +965,7 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -962,6 +993,9 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + phy_type = "hsic"; + fsl,usbphy = <&usbphy_nop1>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -975,6 +1009,9 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + phy_type = "hsic"; + fsl,usbphy = <&usbphy_nop2>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -989,20 +1026,28 @@ compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts-extended = - <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + <&gpc 0 118 IRQ_TYPE_LEVEL_HIGH>, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp"; + stop-mode = <&gpr 0x34 27>; + fsl,wakeup_irq = <0>; status = "disabled"; }; - mlb@0218c000 { + mlb: mlb@0218c000 { + compatible = "fsl,imx6q-mlb150"; reg = <0x0218c000 0x4000>; interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, <0 117 IRQ_TYPE_LEVEL_HIGH>, <0 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_MLB>, + <&clks IMX6QDL_CLK_PLL8_MLB>; + clock-names = "mlb", "pll8_mlb"; + iram = <&ocram>; + status = "disabled"; }; usdhc1: usdhc@02190000 { @@ -1087,6 +1132,11 @@ reg = <0x021ac000 0x4000>; }; + mmdc0-1@021b0000 { /* MMDC0-1 */ + compatible = "fsl,imx6q-mmdc-combine"; + reg = <0x021b0000 0x8000>; + }; + mmdc0: mmdc@021b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; @@ -1125,41 +1175,32 @@ status = "disabled"; }; - mipi_csi: mipi@021dc000 { + mipi_csi: mipi_csi@021dc000 { /* MIPI-CSI */ + compatible = "fsl,imx6q-mipi-csi2"; reg = <0x021dc000 0x4000>; + interrupts = <0 100 0x04>, <0 101 0x04>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, + <&clks IMX6QDL_CLK_EMI_SEL>, + <&clks IMX6QDL_CLK_VIDEO_27M>; + /* Note: clks 138 is hsi_tx, however, the dphy_c + * hsi_tx and pll_refclk use the same clk gate. + * In current clk driver, open/close clk gate do + * use hsi_tx for a temporary debug purpose. + */ + clock-names = "dphy_clk", "pixel_clk", "cfg_clk"; + status = "disabled"; }; - mipi_dsi: mipi@021e0000 { - #address-cells = <1>; - #size-cells = <0>; + mipi@021e0000 { /* MIPI-DSI */ reg = <0x021e0000 0x4000>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mipi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_mipi>; - }; - }; - - port@1 { - reg = <1>; - - mipi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_mipi>; - }; - }; - }; }; vdoa@021e4000 { + compatible = "fsl,imx6q-vdoa"; reg = <0x021e4000 0x4000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_VDOA>; + iram = <&ocram>; }; uart2: serial@021e8000 { @@ -1219,68 +1260,15 @@ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, <0 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, - <&clks IMX6QDL_CLK_IPU1_DI1>; - clock-names = "bus", "di0", "di1"; + <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; resets = <&src 2>; - - ipu1_csi0: port@0 { - reg = <0>; - }; - - ipu1_csi1: port@1 { - reg = <1>; - }; - - ipu1_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu1_di0_disp0: disp0-endpoint { - }; - - ipu1_di0_hdmi: hdmi-endpoint { - remote-endpoint = <&hdmi_mux_0>; - }; - - ipu1_di0_mipi: mipi-endpoint { - remote-endpoint = <&mipi_mux_0>; - }; - - ipu1_di0_lvds0: lvds0-endpoint { - remote-endpoint = <&lvds0_mux_0>; - }; - - ipu1_di0_lvds1: lvds1-endpoint { - remote-endpoint = <&lvds1_mux_0>; - }; - }; - - ipu1_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu1_di1_disp1: disp1-endpoint { - }; - - ipu1_di1_hdmi: hdmi-endpoint { - remote-endpoint = <&hdmi_mux_1>; - }; - - ipu1_di1_mipi: mipi-endpoint { - remote-endpoint = <&mipi_mux_1>; - }; - - ipu1_di1_lvds0: lvds0-endpoint { - remote-endpoint = <&lvds0_mux_1>; - }; - - ipu1_di1_lvds1: lvds1-endpoint { - remote-endpoint = <&lvds1_mux_1>; - }; - }; + bypass_reset = <0>; }; }; }; diff --git a/arch/arm/dts/imx6qp-sabreauto-ecspi.dts b/arch/arm/dts/imx6qp-sabreauto-ecspi.dts new file mode 100644 index 00000000000..8846739a555 --- /dev/null +++ b/arch/arm/dts/imx6qp-sabreauto-ecspi.dts @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; diff --git a/arch/arm/dts/imx6qp-sabreauto-gpmi-weim.dts b/arch/arm/dts/imx6qp-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000..b91ebad6111 --- /dev/null +++ b/arch/arm/dts/imx6qp-sabreauto-gpmi-weim.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + compatible = "fsl,imx6qp-gpmi-nand"; + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qp-sabreauto.dts b/arch/arm/dts/imx6qp-sabreauto.dts new file mode 100644 index 00000000000..d06d7b13db1 --- /dev/null +++ b/arch/arm/dts/imx6qp-sabreauto.dts @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabreauto.dts" +#include "imx6qp.dtsi" + +/ { + model = "Freescale i.MX6 Quad Plus SABRE Automotive Board"; +}; + +&mxcfb1 { + prefetch; +}; + +&mxcfb2 { + prefetch; +}; + +&mxcfb3 { + prefetch; +}; + +&mxcfb4 { + prefetch; +}; + +&fec { + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; +}; + +&i2c2 { + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&pcie { + reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; + +®_sd3_vmmc { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usdhc3 { + vmmc-supply = <®_sd3_vmmc>; +}; + +&vgen3_reg { + regulator-always-on; +}; + diff --git a/arch/arm/dts/imx6qp-sabresd.dts b/arch/arm/dts/imx6qp-sabresd.dts new file mode 100644 index 00000000000..27d6353eea5 --- /dev/null +++ b/arch/arm/dts/imx6qp-sabresd.dts @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd.dts" +#include "imx6qp.dtsi" + +/ { + model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board"; +}; + +&cpu0 { + arm-supply = <&sw2_reg>; +}; + +&iomuxc { + imx6qdl-sabresd { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + }; +}; + +&mxcfb1 { + prefetch; +}; + +&mxcfb2 { + prefetch; +}; + +&mxcfb3 { + prefetch; +}; + +&mxcfb4 { + prefetch; +}; + +&ov564x { + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DOVDD-supply = <&sw4_reg>; /* 1.8v */ +}; + +&ov564x_mipi { + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DOVDD-supply = <&sw4_reg>; /* 1.8v */ +}; + +&pcie { + pcie-bus-supply = <&vgen3_reg>; /* 1.8v pwr up pcie ext osc on revb */ + reset-gpio = <&gpio7 12 0>; + status = "okay"; +}; + +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi new file mode 100644 index 00000000000..c6a22882240 --- /dev/null +++ b/arch/arm/dts/imx6qp.dtsi @@ -0,0 +1,157 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/ { + aliases { + pre0 = &pre1; + pre1 = &pre2; + pre2 = &pre3; + pre3 = &pre4; + prg0 = &prg1; + prg1 = &prg2; + }; + + soc { + ocram_2: sram@00940000 { + compatible = "mmio-sram"; + reg = <0x00940000 0x20000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + ocram_3: sram@00960000 { + compatible = "mmio-sram"; + reg = <0x00960000 0x20000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + pcie: pcie@0x01000000 { + compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; + reg = <0x01ffc000 0x4000>, <0x01f00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>, <&clks IMX6QDL_PLL6_BYPASS>, + <&clks IMX6QDL_PLL6_BYPASS_SRC>, + <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>; + clock-names = "pcie_phy", "pcie_ext", "pcie_ext_src", "pcie_bus", "pcie"; + status = "disabled"; + }; + + aips-bus@02100000 { /* AIPS2 */ + pre1: pre@021c8000 { + compatible = "fsl,imx6q-pre"; + reg = <0x021c8000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRE0>; + interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram_2>; + status = "disabled"; + }; + + pre2: pre@021c9000 { + compatible = "fsl,imx6q-pre"; + reg = <0x021c9000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRE1>; + interrupts = <0 97 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram_2>; + status = "disabled"; + }; + + pre3: pre@021ca000 { + compatible = "fsl,imx6q-pre"; + reg = <0x021ca000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRE2>; + interrupts = <0 98 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram_3>; + status = "disabled"; + }; + + pre4: pre@021cb000 { + compatible = "fsl,imx6q-pre"; + reg = <0x021cb000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRE3>; + interrupts = <0 99 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram_3>; + status = "disabled"; + }; + + prg1: prg@021cc000 { + compatible = "fsl,imx6q-prg"; + reg = <0x021cc000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRG0_AXI>, + <&clks IMX6QDL_CLK_PRG0_APB>; + clock-names = "axi", "apb"; + gpr = <&gpr>; + status = "disabled"; + }; + + prg2: prg@021cd000 { + compatible = "fsl,imx6q-prg"; + reg = <0x021cd000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRG1_AXI>, + <&clks IMX6QDL_CLK_PRG1_APB>; + clock-names = "axi", "apb"; + gpr = <&gpr>; + status = "disabled"; + }; + }; + + ipu1: ipu@02400000 { + compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + clocks = <&clks IMX6QDL_CLK_IPU1>, + <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG0_APB>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", "prg"; + }; + + ipu2: ipu@02800000 { + compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + clocks = <&clks IMX6QDL_CLK_IPU2>, + <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG1_APB>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", "prg"; + }; + + sata: sata@02200000 { + compatible = "fsl,imx6qp-ahci"; + reg = <0x02200000 0x4000>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_SATA>, + <&clks IMX6QDL_CLK_SATA_REF_100M>, + <&clks IMX6QDL_CLK_AHB>; + clock-names = "sata", "sata_ref", "ahb"; + status = "disabled"; + }; + }; +}; + +&ldb { + compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb"; +}; diff --git a/arch/arm/dts/imx6sl-evk.dts b/arch/arm/dts/imx6sl-evk.dts index 0a90eea1701..3747e32077f 100644 --- a/arch/arm/dts/imx6sl-evk.dts +++ b/arch/arm/dts/imx6sl-evk.dts @@ -16,6 +16,19 @@ model = "Freescale i.MX6 SoloLite EVK Board"; compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio4 13 1>; + uok_input = <&gpio4 13 1>; + chg_input = <&gpio4 15 1>; + flt_input = <&gpio4 14 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,adc_disable; + status = "okay"; + }; + memory { reg = <0x80000000 0x40000000>; }; @@ -39,6 +52,11 @@ }; }; + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -96,7 +114,7 @@ sound { compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + cpu-dai = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -107,6 +125,23 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio4 19 1>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sl-evk-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; + + sii902x_reset: sii902x-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 19 1>; + reset-delay-us = <100000>; + #reset-cells = <0>; }; }; @@ -116,7 +151,21 @@ status = "okay"; }; +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&csi { + port { + csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + &ecspi1 { + fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 11 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; @@ -131,6 +180,15 @@ }; }; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + &fec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec>; @@ -139,10 +197,17 @@ status = "okay"; }; +&gpc { + fsl,ldo-bypass = <1>; +}; + &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; status = "okay"; pmic: pfuze100@08 { @@ -244,12 +309,98 @@ }; }; }; + + elan@10 { + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio2>; + interrupts = <10 2>; + gpio_elan_cs = <&gpio2 9 0>; + gpio_elan_rst = <&gpio4 4 0>; + gpio_intr = <&gpio2 10 0>; + status = "okay"; + }; + + mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* 2's-compliment, -4325000 */ + regulator-min-microvolt = <0xffbe0178>; + /* 2's-compliment, -500000 */ + regulator-max-microvolt = <0xfff85ee0>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; + }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; status = "okay"; codec: wm8962@1a { @@ -264,6 +415,45 @@ PLLVDD-supply = <&vgen3_reg>; SPKVDD1-supply = <®_aud4v>; SPKVDD2-supply = <®_aud4v>; + amic-mono; + }; + + sii902x@39 { + compatible = "SiI,sii902x"; + interrupt-parent = <&gpio2>; + interrupts = <10 2>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + resets = <&sii902x_reset>; + reg = <0x39>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_0>; + clocks = <&clks IMX6SL_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 25 1>; + rst-gpios = <&gpio1 26 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi_ep>; + }; + }; }; }; @@ -282,6 +472,17 @@ MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x17000 + MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000 + MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0 + MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x1b0b0 + MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 >; }; @@ -303,6 +504,39 @@ >; }; + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x80000000 + MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x80000000 + MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x80000000 + MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x80000000 + MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x80000000 + MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x80000000 + MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x80000000 + MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x80000000 + MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x80000000 + MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x80000000 + MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000 + MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000 + MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000 + MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000 + MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000 + MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000 + MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000 + MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x80000000 + MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x80000000 + MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x80000000 + MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000 + MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x80000000 + MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x80000000 + MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000 + MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x80000000 + MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000 + MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000 + MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000 + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 @@ -337,6 +571,12 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x1b8b1 + MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x1b8b1 + >; + }; pinctrl_i2c2: i2c2grp { fsl,pins = < @@ -345,6 +585,20 @@ >; }; + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x1b8b1 + MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x1b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1 + MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_kpp: kppgrp { fsl,pins = < MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 @@ -356,7 +610,7 @@ >; }; - pinctrl_lcd: lcdgrp { + pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 @@ -382,6 +636,11 @@ MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 @@ -401,6 +660,12 @@ >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x80000000 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 @@ -408,6 +673,24 @@ >; }; + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x1b0b1 + MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4dte_1: uart4dtegrp-1 { + fsl,pins = < + MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x1b0b1 + MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x1b0b1 + >; + }; + pinctrl_usbotg1: usbotg1grp { fsl,pins = < MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 @@ -524,9 +807,34 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 >; }; + + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0 + MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0 + MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0 + MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0 + MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0 + MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0 + MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0 + MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0 + MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0 + MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0 + MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0 + MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0 + MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0 + MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0 + MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; }; }; +&pxp { + status = "okay"; +}; + &kpp { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_kpp>; @@ -545,13 +853,14 @@ &lcdif { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; lcd-supply = <®_lcd_3v3>; - display = <&display0>; + display = <&display>; status = "okay"; - display0: display0 { - bits-per-pixel = <32>; + display: display { + bits-per-pixel = <16>; bus-width = <24>; display-timings { @@ -585,7 +894,21 @@ status = "okay"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6SL_CLK_SPDIF0_SEL>, + <&clks IMX6SL_CLK_SPDIF0_PODF>; + assigned-clock-parents = <&clks IMX6SL_CLK_PLL3_PFD3>; + assigned-clock-rates = <0>, <227368421>; + status = "okay"; +}; + &ssi2 { + fsl,mode = "i2s-slave"; + assigned-clocks = <&clks IMX6SL_CLK_SSI2_SEL>, + <&clks IMX6SL_CLK_SSI2>; + assigned-clock-rates = <0>, <24000000>; status = "okay"; }; @@ -600,6 +923,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg1>; disable-over-current; + srp-disable; + hnp-disable; + adp-disable; status = "okay"; }; @@ -610,6 +936,14 @@ status = "okay"; }; +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -618,6 +952,8 @@ bus-width = <8>; cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -628,6 +964,8 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -637,5 +975,7 @@ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; diff --git a/arch/arm/dts/imx6sl.dtsi b/arch/arm/dts/imx6sl.dtsi index cc9572ea286..ceb87f9d1c2 100644 --- a/arch/arm/dts/imx6sl.dtsi +++ b/arch/arm/dts/imx6sl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -8,6 +8,8 @@ */ #include +#include +#include "skeleton.dtsi" #include "imx6sl-pinfunc.h" #include @@ -41,13 +43,15 @@ spi3 = &ecspi4; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + usb0 = &usbotg1; + usb1 = &usbotg2; }; cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0x0>; @@ -65,17 +69,37 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, - <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, - <&clks IMX6SL_CLK_PLL1_SYS>; + clocks = <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_STEP>, + <&clks IMX6SL_CLK_PLL1_SW>, + <&clks IMX6SL_CLK_PLL1_SYS>, + <&clks IMX6SL_CLK_PLL1>, + <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", + "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + intc: interrupt-controller@00a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -102,6 +126,10 @@ }; }; + reg_vbus_wakeup: usb_vbus_wakeup { + compatible = "fsl,imx6-dummy-ldo2p5"; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -109,9 +137,42 @@ interrupt-parent = <&gpc>; ranges; - ocram: sram@00900000 { + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>, + <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>, + <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>, + <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>, + <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM_PODF>, + <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>, + <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>, + <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>, + <&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", + "ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src", + "pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + + ocram: sram@00905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x00905000 0x1B000>; clocks = <&clks IMX6SL_CLK_OCRAM>; }; @@ -150,7 +211,7 @@ reg = <0x02004000 0x4000>; interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; + <&sdma 15 18 0>; dma-names = "rx", "tx"; clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, @@ -161,7 +222,7 @@ "rxtx1", "rxtx2", "rxtx3", "rxtx4", "rxtx5", "rxtx6", - "rxtx7", "spba"; + "rxtx7", "dma"; status = "disabled"; }; @@ -174,6 +235,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI1>, <&clks IMX6SL_CLK_ECSPI1>; clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -186,6 +249,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI2>, <&clks IMX6SL_CLK_ECSPI2>; clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -198,6 +263,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI3>, <&clks IMX6SL_CLK_ECSPI3>; clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -210,6 +277,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI4>, <&clks IMX6SL_CLK_ECSPI4>; clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -261,8 +330,8 @@ clocks = <&clks IMX6SL_CLK_SSI1_IPG>, <&clks IMX6SL_CLK_SSI1>; clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; + dmas = <&sdma 37 22 0>, + <&sdma 38 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -277,8 +346,8 @@ clocks = <&clks IMX6SL_CLK_SSI2_IPG>, <&clks IMX6SL_CLK_SSI2>; clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; + dmas = <&sdma 41 22 0>, + <&sdma 42 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -293,8 +362,8 @@ clocks = <&clks IMX6SL_CLK_SSI3_IPG>, <&clks IMX6SL_CLK_SSI3>; clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; + dmas = <&sdma 45 22 0>, + <&sdma 46 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -385,12 +454,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, - <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, - <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, - <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, - <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, - <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; }; gpio2: gpio@020a0000 { @@ -402,13 +465,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, - <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, - <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, - <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, - <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, - <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, - <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; }; gpio3: gpio@020a4000 { @@ -420,14 +476,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, - <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, - <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, - <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, - <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, - <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, - <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, - <&iomuxc 31 102 1>; }; gpio4: gpio@020a8000 { @@ -439,21 +487,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, - <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, - <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, - <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, - <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, - <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, - <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, - <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, - <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, - <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, - <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, - <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, - <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, - <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, - <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; }; gpio5: gpio@020ac000 { @@ -465,17 +498,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, - <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, - <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, - <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, - <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, - <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, - <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, - <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, - <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, - <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, - <&iomuxc 21 161 1>; }; kpp: kpp@020b8000 { @@ -518,7 +540,7 @@ <0 54 IRQ_TYPE_LEVEL_HIGH>, <0 127 IRQ_TYPE_LEVEL_HIGH>; - regulator-1p1 { + regulator-1p1@110 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <800000>; @@ -530,23 +552,24 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; - regulator-3p0 { + reg_3p0: regulator-3p0@120 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; anatop-vol-bit-width = <5>; anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; - regulator-2p5 { + regulator-2p5@130 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2100000>; @@ -558,9 +581,10 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2100000>; anatop-max-voltage = <2850000>; + anatop-enable-bit = <0>; }; - reg_arm: regulator-vddcore { + reg_arm: regulator-vddcore@140 { compatible = "fsl,anatop-regulator"; regulator-name = "vddarm"; regulator-min-microvolt = <725000>; @@ -575,14 +599,16 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; - reg_pu: regulator-vddpu { + reg_pu: regulator-vddpu@140 { compatible = "fsl,anatop-regulator"; regulator-name = "vddpu"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; - regulator-always-on; + regulator-enable-ramp-delay = <150>; + regulator-boot-on; anatop-reg-offset = <0x140>; anatop-vol-bit-shift = <9>; anatop-vol-bit-width = <5>; @@ -592,9 +618,10 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; - reg_soc: regulator-vddsoc { + reg_soc: regulator-vddsoc@140 { compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; @@ -609,6 +636,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; }; @@ -625,6 +653,7 @@ reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; @@ -633,9 +662,16 @@ reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; + usbphy_nop1: usbphy_nop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6SL_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + snvs: snvs@020cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -652,7 +688,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; status = "disabled"; }; }; @@ -683,8 +719,12 @@ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; pu-supply = <®_pu>; - clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; + clocks = <&clks IMX6SL_CLK_GPU2D_PODF>, <&clks IMX6SL_CLK_GPU2D_OVG>, + <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_LCDIF_AXI>, + <&clks IMX6SL_CLK_LCDIF_PIX>, <&clks IMX6SL_CLK_EPDC_AXI>, + <&clks IMX6SL_CLK_EPDC_PIX>, <&clks IMX6SL_CLK_PXP_AXI>; + clock-names = "gpu2d_podf", "gpu2d_ovg", "ipg", "lcd_axi", + "lcd_pix", "epdc_axi", "epdc_pix", "pxp_axi"; #power-domain-cells = <1>; }; @@ -700,8 +740,14 @@ }; csi: csi@020e4000 { + compatible = "fsl,imx6sl-csi"; reg = <0x020e4000 0x4000>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; }; spdc: spdc@020e8000 { @@ -717,18 +763,26 @@ <&clks IMX6SL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; + iram = <&ocram>; /* imx6sl reuses imx6q sdma firmware */ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; pxp: pxp@020f0000 { + compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; epdc: epdc@020f4000 { + compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc"; reg = <0x020f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; }; lcdif: lcdif@020f8000 { @@ -743,11 +797,15 @@ }; dcp: dcp@020fc000 { - compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; + compatible = "fsl,imx6sl-dcp"; reg = <0x020fc000 0x4000>; interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, <0 100 IRQ_TYPE_LEVEL_HIGH>, <0 101 IRQ_TYPE_LEVEL_HIGH>; + /* DCP clock always on */ + clocks = <&clks IMX6SL_CLK_DUMMY>; + clock-names = "dcp"; + status = "okay"; }; }; @@ -768,6 +826,7 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -794,6 +853,9 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + phy_type = "hsic"; + fsl,usbphy = <&usbphy_nop1>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -802,6 +864,7 @@ compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks IMX6SL_CLK_USBOH3>; + vbus-wakeup-supply = <®_vbus_wakeup>; }; fec: ethernet@02188000 { @@ -897,18 +960,16 @@ reg = <0x021b0000 0x4000>; }; - rngb: rngb@021b4000 { + rng: rng@021b4000 { + compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng"; reg = <0x021b4000 0x4000>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>; }; weim: weim@021b8000 { - #address-cells = <2>; - #size-cells = <1>; reg = <0x021b8000 0x4000>; interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - fsl,weim-cs-gpr = <&gpr>; - status = "disabled"; }; ocotp: ocotp@021bc000 { @@ -922,6 +983,24 @@ reg = <0x021d8000 0x4000>; status = "disabled"; }; + + gpu: gpu@02200000 { + compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu"; + reg = <0x02200000 0x4000>, <0x02204000 0x4000>, + <0x80000000 0x0>, <0x0 0x8000000>; + reg-names = "iobase_2d", "iobase_vg", + "phys_baseaddr", "contiguous_mem"; + interrupts = , ; + interrupt-names = "irq_2d", "irq_vg"; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "gpu2d_axi_clk", "openvg_axi_clk", + "gpu2d_clk"; + resets = <&src 3>, <&src 3>; + reset-names = "gpu2d", "gpuvg"; + power-domains = <&gpc 1>; + }; }; }; }; diff --git a/arch/arm/dts/imx6sll-evk.dts b/arch/arm/dts/imx6sll-evk.dts index b4af007c983..a254b48bbd3 100644 --- a/arch/arm/dts/imx6sll-evk.dts +++ b/arch/arm/dts/imx6sll-evk.dts @@ -162,8 +162,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; status = "okay"; pmic: pfuze100@08 { @@ -339,8 +342,11 @@ &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; status = "okay"; codec: wm8962@1a { @@ -534,34 +540,34 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17061 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13061 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17061 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17061 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17061 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17061 >; }; pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170a1 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130a1 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170a1 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170a1 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170a1 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170a1 >; }; pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170e9 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170e9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170e9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170e9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170e9 >; }; @@ -615,34 +621,34 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13059 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059 + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061 >; }; pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130b9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1 >; }; pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9 >; }; @@ -659,6 +665,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x1b8b1 + MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x1b8b1 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1 @@ -666,11 +679,24 @@ >; }; + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x41b8b1 + MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x41b8b1 + >; + }; + pinctrl_pwm1: pmw1grp { fsl,pins = < MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 >; }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6SLL_PAD_WDOG_B__WDOG1_B 0x170b0 + >; + }; }; }; @@ -753,7 +779,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>; vqmmc-supply = <®_sd2_vmmc>; bus-width = <8>; - no-removable; + non-removable; status = "okay"; }; @@ -799,3 +825,9 @@ &ssi2 { status = "okay"; }; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,wdog_b; +}; diff --git a/arch/arm/dts/imx6sll-lpddr2-arm2.dts b/arch/arm/dts/imx6sll-lpddr2-arm2.dts new file mode 100644 index 00000000000..33f230f9c97 --- /dev/null +++ b/arch/arm/dts/imx6sll-lpddr2-arm2.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sll-lpddr3-arm2.dts" + diff --git a/arch/arm/dts/imx6sll-lpddr3-arm2-ecspi.dts b/arch/arm/dts/imx6sll-lpddr3-arm2-ecspi.dts new file mode 100644 index 00000000000..d1facfc26f7 --- /dev/null +++ b/arch/arm/dts/imx6sll-lpddr3-arm2-ecspi.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sll-lpddr3-arm2.dts" + +&ecspi1 { + status = "okay"; +}; + +&lcdif { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6sll-lpddr3-arm2.dts b/arch/arm/dts/imx6sll-lpddr3-arm2.dts new file mode 100644 index 00000000000..ad2106e1561 --- /dev/null +++ b/arch/arm/dts/imx6sll-lpddr3-arm2.dts @@ -0,0 +1,852 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include +#include "imx6sll.dtsi" + +/ { + model = "Freescale i.MX6SLL LPDDR3 ARM2 Board"; + compatible = "fsl,imx6sll-lpddr3-arm2", "fsl,imx6sll"; + + memory { + reg = <0x80000000 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + users { + label = "debug"; + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_aud3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; + + reg_aud4v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; + + reg_lcd: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-pwr"; + gpio = <&gpio4 8 0>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC_VCCQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + reg_sd3_vmmc: sd3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD3_WIFI"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; + + sound { + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio4 24 1>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <393216000>; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "okay"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* 2's-compliment, -4325000 */ + regulator-min-microvolt = <0xffbe0178>; + /* 2's-compliment, -500000 */ + regulator-max-microvolt = <0xfff85ee0>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; + DCVDD-supply = <&vgen3_reg>; + DBVDD-supply = <®_aud3v>; + AVDD-supply = <&vgen3_reg>; + CPVDD-supply = <&vgen3_reg>; + MICVDD-supply = <®_aud3v>; + PLLVDD-supply = <&vgen3_reg>; + SPKVDD1-supply = <®_aud4v>; + SPKVDD2-supply = <®_aud4v>; + amic-mono; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6SLL_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 25 1>; + rst-gpios = <&gpio1 26 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog_sd2_reset>; + + imx6sll-lpddr3-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 + MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059 + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */ + MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */ + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ + >; + }; + + pinctrl_hog_sd2_reset: hoggrp-1 { + fsl,pins = < + MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059 + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 + MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 + MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 + MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 + MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088 + MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088 + MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088 + MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088 + MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088 + MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088 + MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088 + MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088 + MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088 + MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088 + MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088 + MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088 + MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059 + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1 + MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1 + MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1 + MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1 + MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1 + MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1 + MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1 + MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1 + MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1 + MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1 + MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1 + MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1 + MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1 + MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1 + MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1 + MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1 + MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1 + MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1 + MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1 + MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1 + MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1 + MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1 + MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1 + MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1 + MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 + MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 + MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 + MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 + MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 + MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 + MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 + MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 + MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 + MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 + MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 + MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 + MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */ + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */ + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */ + MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */ + MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */ + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x4130b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x17059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170b9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9 + >; + }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x17059 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x1b8b1 + MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x1b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x4041b8b1 + MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x4041b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x41b8b1 + MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x41b8b1 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 + MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 + MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 + MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x100b1 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + lcd-supply = <®_lcd>; + display = <&display>; + status = "okay"; + + display: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pxp { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vqmmc-supply = <®_sd2_vmmc>; + bus-width = <8>; + no-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd3_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 11 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + flash: m25p80@0 { + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6sll.dtsi b/arch/arm/dts/imx6sll.dtsi index 349c47a03a2..28f6210b53c 100644 --- a/arch/arm/dts/imx6sll.dtsi +++ b/arch/arm/dts/imx6sll.dtsi @@ -23,9 +23,6 @@ i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -37,6 +34,8 @@ spi4 = &ecspi4; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + usb0 = &usbotg1; + usb1 = &usbotg2; }; cpus { @@ -528,7 +527,6 @@ fsl,tempmon = <&anatop>; fsl,tempmon-data = <&ocotp>; clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; - status = "disabled"; }; usbphy1: usbphy@020c9000 { @@ -629,7 +627,7 @@ }; sdma: sdma@020ec000 { - compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma"; + compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_SDMA>, @@ -726,7 +724,7 @@ }; usdhc1: usdhc@02190000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02190000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC1>, @@ -740,7 +738,7 @@ }; usdhc2: usdhc@02194000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02194000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC2>, @@ -754,7 +752,7 @@ }; usdhc3: usdhc@02198000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02198000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC3>, diff --git a/arch/arm/dts/imx6sx-14x14-arm2.dts b/arch/arm/dts/imx6sx-14x14-arm2.dts new file mode 100644 index 00000000000..ec48b7de533 --- /dev/null +++ b/arch/arm/dts/imx6sx-14x14-arm2.dts @@ -0,0 +1,1365 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SoloX 14x14 ARM2 Board"; + compatible = "fsl,imx6sx-14x14-lpddr2-arm2", "fsl,imx6sx"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clocks { + codec_osc: codec_osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_sdb_vmmc: sdb_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: usb_otg2_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 0>; + enable-active-high; + }; + + reg_vref_3v3: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + sound { + compatible = "fsl,imx6sx-arm2-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6sx-arm2-sgtl5000"; + cpu-dai = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1a_reg>; + fsl,arm-soc-shared = <1>; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "disabled"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-id = <1>; + fsl,num_tx_queues=<3>; + fsl,num_rx_queues=<3>; + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-id = <0>; + fsl,num_tx_queues=<3>; + fsl,num_rx_queues=<3>; + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x2>; + fsl,cpu_pupscr_sw = <0x1>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; /* pin conflict with qspi*/ + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322_1: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + max7322_2: gpio@69 { + compatible = "maxim,max7322"; + reg = <0x69>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&codec_osc>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <®_3p3v>; + }; +}; + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4_1>; + pinctrl-1 = <&pinctrl_i2c4_1_gpio>; + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059 + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059 + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000 + /* CAN1_2_EN */ + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + /* CAN1_2_STBY_B */ + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + /* CAN1_ERR_B */ + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059 + /* CAN2_ERR_B */ + MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059 + /* SD2_PWROFF */ + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + >; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat_0 + &pinctrl_lcdif_ctrl_0>; + display = <&display>; + status = "okay"; + + display: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb_1>; + status = "disabled";/* pin conflict with usdhc2*/ +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_1>; + status = "disabled"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_1>; + status = "disabled"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&usbh { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh_1>; + pinctrl-1 = <&pinctrl_usbh_2>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen1_reg>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + /* + * Pin conflict with others, need to switch R580 & R579 + * to B and disable pwm3 to enable it. + */ + vbus-supply = <®_usb_otg2_vbus>; + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_1>; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 0>; + wp-gpios = <&gpio2 15 0>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sdb_vmmc>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + bus-width = <8>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 + >; + }; + + pinctrl_audmux_3: audmux-3 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0 + MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0 + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_csi_1: csigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 + >; + }; + }; + + enet1 { + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + }; + + enet2 { + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + + pinctrl_esai_2: esaigrp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + }; + + i2c4 { + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_1_gpio: i2c4grp-1-gpio { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1 + MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1 + >; + }; + + pinctrl_i2c4_2: i2c4grp-2 { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + >; + }; + }; + + lcdif1 { + pinctrl_lcdif_dat_0: lcdifdatgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 + >; + }; + + pinctrl_mlb_2: mlbgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x31 + MX6SX_PAD_ENET2_CRS__MLB_SIG 0x31 + MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x31 + >; + }; + }; + + mqs { + pinctrl_mqs_1: mqsgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_0: pwm3grp-0 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + }; + + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 + >; + }; + }; + + qspi2 { + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 + >; + }; + }; + + sai1 { + pinctrl_sai1_1: sai1grp_1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 + >; + }; + + pinctrl_sai1_2: sai1grp_2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 + >; + }; + }; + + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_spdif_3: spdifgrp-3 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + }; + + usbh { + pinctrl_usbh_1: usbhgrp-1 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 + >; + }; + + pinctrl_usbh_2: usbhgrp-2 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 + >; + }; + }; + + usbotg1 { + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4_3: usdhc4grp-3 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 + >; + }; + + }; + + wdog { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 + >; + }; + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 + /* data */ + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 + /* address */ + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx-17x17-arm2-ecspi.dts b/arch/arm/dts/imx6sx-17x17-arm2-ecspi.dts new file mode 100644 index 00000000000..873478cbeac --- /dev/null +++ b/arch/arm/dts/imx6sx-17x17-arm2-ecspi.dts @@ -0,0 +1,459 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SoloX SDB Board"; + compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif0"; + }; + + backlight2 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif1"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds0 { + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_lcd_3v3: lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-3v3"; + gpio = <&gpio3 27 0>; + enable-active-high; + status = "disabled"; + }; + + vcc_sd3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_sd3>; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; /* pin conflict with qspi*/ +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart5 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <&vcc_sd3>; + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "okay"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6x-sdb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059 + MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000 + >; + }; + + pinctrl_canfd1: canfd1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0 + >; + }; + + pinctrl_canfd2: canfd2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 + MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_vcc_sd3: vccsd3grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ + MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ + >; + }; + + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx-17x17-arm2-gpmi-weim.dts b/arch/arm/dts/imx6sx-17x17-arm2-gpmi-weim.dts new file mode 100644 index 00000000000..e1d883157ce --- /dev/null +++ b/arch/arm/dts/imx6sx-17x17-arm2-gpmi-weim.dts @@ -0,0 +1,429 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SoloX SDB Board"; + compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif0"; + }; + + backlight2 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif1"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds0 { + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_lcd_3v3: lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-3v3"; + gpio = <&gpio3 27 0>; + enable-active-high; + status = "disabled"; + }; + + vcc_sd3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_sd3>; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; /* pin conflict with qspi*/ + nand-on-flash-bbt; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart5 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <&vcc_sd3>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6x-sdb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059 + MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000 + >; + }; + + pinctrl_canfd1: canfd1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0 + >; + }; + + pinctrl_canfd2: canfd2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 + MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_vcc_sd3: vccsd3grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ + MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx-17x17-arm2.dts b/arch/arm/dts/imx6sx-17x17-arm2.dts new file mode 100644 index 00000000000..d29143bc40a --- /dev/null +++ b/arch/arm/dts/imx6sx-17x17-arm2.dts @@ -0,0 +1,1309 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SoloX 17x17 ARM2 Board"; + compatible = "fsl,imx6sx-17x17-arm2", "fsl,imx6sx"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clocks { + codec_osc: codec_osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_sdb_vmmc: sdb_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: usb_otg2_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 0>; + enable-active-high; + }; + + reg_vref_3v3: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + sound { + compatible = "fsl,imx6sx-arm2-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6sx-arm2-sgtl5000"; + cpu-dai = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "disabled"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x2>; + fsl,cpu_pupscr_sw = <0x1>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,wdog-reset = <1>; /* watchdog select of reset source */ + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322_1: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + max7322_2: gpio@69 { + compatible = "maxim,max7322"; + reg = <0x69>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&codec_osc>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <®_3p3v>; + }; +}; + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4_1>; + pinctrl-1 = <&pinctrl_i2c4_1_gpio>; + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059 + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059 + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000 + /* CAN1_2_EN */ + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + /* CAN1_2_STBY_B */ + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + /* CAN1_ERR_B */ + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059 + /* CAN2_ERR_B */ + MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059 + /* SD2_PWROFF */ + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + /* WDOG_B reset */ + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 + >; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat_0 + &pinctrl_lcdif_ctrl_0>; + display = <&display>; + status = "okay"; + + display: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb_1>; + status = "disabled";/* pin conflict with usdhc2*/ +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_1>; + status = "disabled"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_1>; + status = "disabled"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&usbh { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh_1>; + pinctrl-1 = <&pinctrl_usbh_2>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen1_reg>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + /* + * Pin conflict with others, need to switch R580 & R579 + * to B and disable pwm3 to enable it. + */ + vbus-supply = <®_usb_otg2_vbus>; + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_1>; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 0>; + wp-gpios = <&gpio2 15 0>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sdb_vmmc>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + bus-width = <8>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + canfd1 { + pinctrl_canfd1_1: canfd1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0 + >; + }; + }; + + canfd2 { + pinctrl_canfd2_1: canfd2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0 + >; + }; + }; + + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_csi_1: csigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 + >; + }; + }; + + enet1 { + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + }; + + enet2 { + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + }; + + i2c4 { + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_1_gpio: i2c4grp-1-gpio { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1 + MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1 + >; + }; + + pinctrl_i2c4_2: i2c4grp-2 { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + >; + }; + }; + + lcdif1 { + pinctrl_lcdif_dat_0: lcdifdatgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_0: pwm3grp-0 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + }; + + qspi2 { + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 + >; + }; + }; + + sai1 { + pinctrl_sai1_1: sai1grp_1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 + >; + }; + + pinctrl_sai1_2: sai1grp_2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 + >; + }; + }; + + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + }; + + usbh { + pinctrl_usbh_1: usbhgrp-1 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 + >; + }; + + pinctrl_usbh_2: usbhgrp-2 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 + >; + }; + }; + + usbotg1 { + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + >; + }; + + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 + /* data */ + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 + /* address */ + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx-19x19-arm2-gpmi-weim.dts b/arch/arm/dts/imx6sx-19x19-arm2-gpmi-weim.dts new file mode 100644 index 00000000000..a50f335adb8 --- /dev/null +++ b/arch/arm/dts/imx6sx-19x19-arm2-gpmi-weim.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-19x19-arm2.dts" + +&qspi2 { + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; /* pin conflict with qspi*/ + nand-on-flash-bbt; +}; diff --git a/arch/arm/dts/imx6sx-19x19-arm2.dts b/arch/arm/dts/imx6sx-19x19-arm2.dts new file mode 100644 index 00000000000..14eef732cab --- /dev/null +++ b/arch/arm/dts/imx6sx-19x19-arm2.dts @@ -0,0 +1,1299 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SoloX 19x19 ARM2 Board"; + compatible = "fsl,imx6sx-19x19-arm2", "fsl,imx6sx"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds0 { + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + }; + }; + + clocks { + codec_osc: codec_osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai>; + asrc-controller = <&asrc>; + audio-codec = <&cs42888>; + }; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai_1>; + status = "okay"; +}; + +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322_1: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + max7322_2: gpio@69 { + compatible = "maxim,max7322"; + reg = <0x69>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_1>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio3 26 1>; + rst-gpios = <&gpio3 25 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4_2>; + pinctrl-1 = <&pinctrl_i2c4_2_gpio>; + scl-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&codec_osc>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <®_3p3v>; + }; + + cs42888: cs42888@048 { + compatible = "cirrus,cs42888"; + reg = <0x048>; + clocks = <&clks IMX6SX_CLK_ESAI_EXTAL>; + clock-names = "mclk"; + VA-supply = <®_3p3v>; + VD-supply = <®_3p3v>; + VLS-supply = <®_3p3v>; + VLC-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x1b0b0 + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x1b0b0 + >; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat_0 + &pinctrl_lcdif_ctrl_0>; + display = <&display0>; + status = "disabled"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; + status = "okay"; + + display1: display { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_1>; + status = "disabled"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&usbh { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh_1>; + pinctrl-1 = <&pinctrl_usbh_2>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen1_reg>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_1>; + bus-width = <4>; + keep-power-in-suspend; + enable-sdio-wakeup; + no-1-8-v; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x50000000 0x08000000>; + status = "disabled"; /* pin conflict with qspi, nand and lcd1 */ + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +}; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + canfd1 { + pinctrl_canfd1_1: canfd1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0 + >; + }; + }; + + canfd2 { + pinctrl_canfd2_1: canfd2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0 + >; + }; + }; + + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_csi_1: csigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 + >; + }; + }; + + enet1 { + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + }; + + enet2 { + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + }; + + i2c4 { + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_2: i2c4grp-2 { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_2_gpio: i2c4grp-2-gpio { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x1b8b1 + MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x1b8b1 + >; + }; + }; + + lcdif1 { + pinctrl_lcdif_dat_0: lcdifdatgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 + >; + }; + }; + + mqs { + pinctrl_mqs_1: mqsgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_0: pwm3grp-0 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + }; + + qspi2 { + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 + >; + }; + }; + + sai1 { + pinctrl_sai1_1: sai1grp_1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 + >; + }; + + pinctrl_sai1_2: sai1grp_2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 + >; + }; + }; + + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + }; + + usbh { + pinctrl_usbh_1: usbhgrp-1 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 + >; + }; + + pinctrl_usbh_2: usbhgrp-2 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 + >; + }; + }; + + usbotg1 { + pinctrl_usb_otg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + >; + }; + + }; + + wdog { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 + >; + }; + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 + /* data */ + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 + /* address */ + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx-pinfunc.h b/arch/arm/dts/imx6sx-pinfunc.h index 42c4c800fee..5f21be0f7e9 100644 --- a/arch/arm/dts/imx6sx-pinfunc.h +++ b/arch/arm/dts/imx6sx-pinfunc.h @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -70,6 +70,7 @@ #define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 #define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART1_CTS_B 0x002C 0x0374 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 @@ -79,6 +80,7 @@ #define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 #define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART1_RTS_B 0x0030 0x0378 0x082C 0x4 0x1 #define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 @@ -88,6 +90,7 @@ #define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 #define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 #define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO08__UART2_CTS_B 0x0034 0x037C 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 @@ -97,6 +100,7 @@ #define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 #define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO09__UART2_RTS_B 0x0038 0x0380 0x0834 0x4 0x1 #define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 @@ -204,6 +208,7 @@ #define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 #define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 #define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0 +#define MX6SX_PAD_CSI_DATA06__UART6_CTS_B 0x0064 0x03AC 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 @@ -214,6 +219,7 @@ #define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 #define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 #define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA07__UART6_RTS_B 0x0068 0x03B0 0x0854 0x4 0x1 #define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 @@ -223,6 +229,7 @@ #define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 #define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 #define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2 +#define MX6SX_PAD_CSI_HSYNC__UART4_CTS_B 0x006C 0x03B4 0x0000 0x3 0x0 #define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 @@ -255,6 +262,7 @@ #define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 #define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 #define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_VSYNC__UART4_RTS_B 0x0078 0x03C0 0x0844 0x3 0x3 #define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 @@ -308,20 +316,6 @@ #define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 #define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 #define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 -/* - * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is - * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a - * PHY in RMII mode. This configuration is valid if: - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset - * It seems to be a silicon bug that in this configuration ENET1_TX reference - * clock isn't provided automatically. According to i.MX6SX reference manual - * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it - * should be the case. - * So this might have unwanted side effects for other hardware units that are - * also connected to that pin and using respective function as input (e.g. - * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). - */ #define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 #define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 #define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 @@ -357,6 +351,7 @@ #define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 #define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 #define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2 +#define MX6SX_PAD_ENET2_RX_CLK__UART1_CTS_B 0x009C 0x03E4 0x0000 0x3 0x0 #define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 #define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 @@ -367,6 +362,7 @@ #define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 #define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 #define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__UART1_RTS_B 0x00A0 0x03E8 0x082C 0x3 0x3 #define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 #define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 @@ -376,6 +372,7 @@ #define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 #define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2 +#define MX6SX_PAD_KEY_COL0__UART6_CTS_B 0x00A4 0x03EC 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 #define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 #define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 @@ -394,6 +391,7 @@ #define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 #define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2 +#define MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x00AC 0x03F4 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 #define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 #define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 @@ -419,6 +417,7 @@ #define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 #define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW0__UART6_RTS_B 0x00B8 0x0400 0x0854 0x2 0x3 #define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 #define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 #define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 @@ -438,6 +437,7 @@ #define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 #define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x00C0 0x0408 0x084C 0x2 0x3 #define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 #define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 #define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 @@ -820,6 +820,7 @@ #define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 #define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0 +#define MX6SX_PAD_NAND_DATA04__UART3_CTS_B 0x0160 0x04A8 0x0000 0x3 0x0 #define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 #define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 @@ -830,6 +831,7 @@ #define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 #define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA05__UART3_RTS_B 0x0164 0x04AC 0x083C 0x3 0x1 #define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 #define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 @@ -972,6 +974,7 @@ #define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 #define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__UART3_RTS_B 0x01A0 0x04E8 0x083C 0x1 0x4 #define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 @@ -980,6 +983,7 @@ #define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 #define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5 +#define MX6SX_PAD_QSPI1B_DATA1__UART3_CTS_B 0x01A4 0x04EC 0x0000 0x1 0x0 #define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 @@ -1251,6 +1255,7 @@ #define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 #define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 #define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA2__UART2_RTS_B 0x0230 0x0578 0x0834 0x4 0x2 #define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 @@ -1260,6 +1265,7 @@ #define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 #define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 #define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3 +#define MX6SX_PAD_SD1_DATA3__UART2_CTS_B 0x0234 0x057C 0x0000 0x4 0x0 #define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 @@ -1330,6 +1336,7 @@ #define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_CLK__UART4_RTS_B 0x0250 0x0598 0x0844 0x1 0x0 #define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 #define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 #define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 @@ -1369,6 +1376,7 @@ #define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1 +#define MX6SX_PAD_SD3_DATA2__UART4_CTS_B 0x0260 0x05A8 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 #define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 #define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 @@ -1414,6 +1422,7 @@ #define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 #define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2 +#define MX6SX_PAD_SD3_DATA6__UART3_CTS_B 0x0270 0x05B8 0x0000 0x3 0x0 #define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 @@ -1424,6 +1433,7 @@ #define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 #define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 #define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA7__UART3_RTS_B 0x0274 0x05BC 0x083C 0x3 0x3 #define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 @@ -1515,6 +1525,7 @@ #define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 #define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0 +#define MX6SX_PAD_SD4_DATA6__UART5_CTS_B 0x0298 0x05E0 0x0000 0x2 0x0 #define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 #define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 @@ -1525,6 +1536,7 @@ #define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 #define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA7__UART5_RTS_B 0x029C 0x05E4 0x084C 0x2 0x1 #define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 #define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 diff --git a/arch/arm/dts/imx6sx-sabreauto.dts b/arch/arm/dts/imx6sx-sabreauto.dts index a4c2627f974..39438a77332 100644 --- a/arch/arm/dts/imx6sx-sabreauto.dts +++ b/arch/arm/dts/imx6sx-sabreauto.dts @@ -14,15 +14,83 @@ model = "Freescale i.MX6 SoloX Sabre Auto Board"; compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; + backlight2 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif1"; + }; + + clocks { + codec_osc: anaclk2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + }; + + max7310_reset: max7310-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + memory { reg = <0x80000000 0x80000000>; }; + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + reg_audio: cs42888_supply { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vio1: vio1_tnr { + compatible = "regulator-fixed"; + regulator-name = "vio1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vio2: vio2_tnr { + compatible = "regulator-fixed"; + regulator-name = "vio2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vd: f3v3_tnr { + compatible = "regulator-fixed"; + regulator-name = "vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_va: f5v_tnr { + compatible = "regulator-fixed"; + regulator-name = "va"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + vcc_sd3: regulator@0 { compatible = "regulator-fixed"; reg = <0>; @@ -34,51 +102,347 @@ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: usb_otg2_vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 0>; + enable-active-high; + }; + + reg_can_wake: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "can-wake"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_en: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_wake>; + }; + + reg_can_stby: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_vref_3v3: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai>; + asrc-controller = <&asrc>; + audio-codec = <&codec>; + }; + + sound-fm { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si4763"; + + ssi-controller = <&ssi2>; + fm-controller = <&si476x_codec>; + mux-int-port = <2>; + mux-ext-port = <5>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; }; }; -&uart1 { +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&audmux { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; + pinctrl-0 = <&pinctrl_audmux_3>; status = "okay"; }; -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&vcc_sd3>; +&clks { + assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, + <&clks IMX6SX_PLL4_BYPASS>, + <&clks IMX6SX_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, + <&clks IMX6SX_PLL4_BYPASS_SRC>; + assigned-clock-rates = <0>, <0>, <24576000>; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai_2>; + assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>, + <&clks IMX6SX_CLK_ESAI_EXTAL>; + assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; status = "okay"; }; -&usdhc4 { +&fec1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; status = "okay"; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; status = "okay"; + + codec: cs42888@048 { + compatible = "cirrus,cs42888"; + reg = <0x048>; + clocks = <&codec_osc 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + }; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <22 2>; + wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; + }; + + si4763: si4763@63 { + compatible = "si4761"; + reg = <0x63>; + va-supply = <&si4763_va>; + vd-supply = <&si4763_vd>; + vio1-supply = <&si4763_vio1>; + vio2-supply = <&si4763_vio2>; + revision-a10; /* set to default A10 compatible command set */ + + si476x_codec: si476x-codec { + compatible = "si476x-codec"; + }; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3_2>; + pinctrl-1 = <&pinctrl_i2c3_2_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; status = "okay"; max7310_a: gpio@30 { @@ -86,6 +450,7 @@ reg = <0x30>; gpio-controller; #gpio-cells = <2>; + resets = <&max7310_reset>; }; max7310_b: gpio@32 { @@ -93,11 +458,293 @@ reg = <0x32>; gpio-controller; #gpio-cells = <2>; + resets = <&max7310_reset>; + }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <7>; + interrupt-parent = <&gpio3>; + interrupts = <24 8>; + interrupt-route = <1>; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + interrupt-parent = <&gpio6>; + interrupts = <6 1>; + }; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio3>; + interrupts = <23 2>; + }; + +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; + status = "okay"; + + display1: display { + bits-per-pixel = <16>; + bus-width = <18>; }; }; +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "lcdif2"; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb_2>; + status = "okay"; +}; + +&pcie { + reset-gpio = <&max7310_b 3 0>; + status = "okay"; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_3>; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-master"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&uart5 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_1>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <&vcc_sd3>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakup; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + &iomuxc { imx6x-sabreauto { + pinctrl_audmux_3: audmux-3 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0 + MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x80000000 + >; + }; + + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + + pinctrl_esai_2: esaigrp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + + pinctrl_flexcan1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + pinctrl_i2c2_1: i2c2grp-1 { fsl,pins = < MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 @@ -105,6 +752,13 @@ >; }; + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; + pinctrl_i2c3_2: i2c3grp-2 { fsl,pins = < MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 @@ -112,6 +766,50 @@ >; }; + pinctrl_i2c3_2_gpio: i2c3grp-2-gpio { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 + >; + }; + + pinctrl_mlb_2: mlbgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x31 + MX6SX_PAD_ENET2_CRS__MLB_SIG 0x31 + MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x31 + >; + }; + + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 + >; + }; + + pinctrl_spdif_3: spdifgrp-3 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 @@ -119,6 +817,49 @@ >; }; + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 @@ -168,14 +909,14 @@ pinctrl_usdhc4: usdhc4grp { fsl,pins = < - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 + MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17071 /* CD */ + MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17071 /* WP */ >; }; @@ -184,5 +925,49 @@ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 + >; + }; }; }; +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; + nand-on-flash-bbt; +}; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/arch/arm/dts/imx6sx-sdb-emmc.dts b/arch/arm/dts/imx6sx-sdb-emmc.dts new file mode 100644 index 00000000000..6a2a07b0e2b --- /dev/null +++ b/arch/arm/dts/imx6sx-sdb-emmc.dts @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb.dts" + +/* + * The eMMC chip on imx6sx sdb board is DNP by default. + * Need do hw rework to burn the eMMC4.5 chip on the eMMC socket on uSDHC4 + * and connect eMMC signals as well as disconnect BOOT SD CARD slot signals + */ +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + pinctrl-1 = <&pinctrl_usdhc4_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_1_200mhz>; + bus-width = <8>; + /* + * overwrite cd-gpios and wp-gpios since they are reused as eMMC DATA + * signals after rework + */ + cd-gpios = <>; + wp-gpios = <>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts index 6dd9bebfe02..4625415de30 100644 --- a/arch/arm/dts/imx6sx-sdb.dts +++ b/arch/arm/dts/imx6sx-sdb.dts @@ -10,112 +10,47 @@ / { model = "Freescale i.MX6 SoloX SDB RevB Board"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze200"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + regulators { + /* Transceiver EN/STBY is active low on RevB board */ + reg_can_stby: regulator@10 { + gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; }; }; }; +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1a_reg>; + fsl,arm-soc-shared = <1>; +}; + &qspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi2>; status = "okay"; +#ifndef SPANSIONFLASH + ddrsmp=<0>; + flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; + compatible = "spi-flash"; spi-max-frequency = <29000000>; reg = <0>; }; @@ -123,16 +58,17 @@ flash1: n25q256a@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; + compatible = "spi-flash"; spi-max-frequency = <29000000>; reg = <1>; }; +#endif }; -®_arm { - vin-supply = <&sw1a_reg>; +&usbphy1 { + tx-d-cal = <0x5>; }; -®_soc { - vin-supply = <&sw1a_reg>; +&usbphy2 { + tx-d-cal = <0x5>; }; diff --git a/arch/arm/dts/imx6sx-sdb.dtsi b/arch/arm/dts/imx6sx-sdb.dtsi index da815527a7f..9781adcc483 100644 --- a/arch/arm/dts/imx6sx-sdb.dtsi +++ b/arch/arm/dts/imx6sx-sdb.dtsi @@ -24,11 +24,19 @@ reg = <0x80000000 0x40000000>; }; - backlight { + backlight1 { compatible = "pwm-backlight"; pwms = <&pwm3 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; + fb-names = "mxs-lcdif0"; + }; + backlight2 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif1"; }; gpio-keys { @@ -49,6 +57,18 @@ }; }; + hannstar_cabc { + compatible = "hannstar,cabc"; + lvds0 { + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -104,6 +124,7 @@ regulator-name = "lcd-3v3"; gpio = <&gpio3 27 0>; enable-active-high; + status = "disabled"; }; reg_peri_3v3: regulator@5 { @@ -114,7 +135,7 @@ regulator-name = "peri_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; }; @@ -129,12 +150,49 @@ regulator-max-microvolt = <3300000>; gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; }; + + reg_vref_3v3: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_pcie: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 1 0>; + regulator-always-on; + enable-active-high; + }; + + reg_can_en: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_can_stby: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; sound { compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + cpu-dai = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -145,7 +203,35 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <6>; + codec-master; + hp-det-gpios = <&gpio1 17 1>; }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sx-sdb-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; + + sii902x_reset: sii902x-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 27 1>; + reset-delay-us = <100000>; + #reset-cells = <0>; + status = "disabled"; + }; +}; + +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; }; &audmux { @@ -154,6 +240,11 @@ status = "okay"; }; + +&gpc { + fsl,ldo-bypass = <1>; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -176,6 +267,37 @@ }; }; +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; +}; + &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; @@ -184,17 +306,214 @@ status = "okay"; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_0>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio3 28 1>; + rst-gpios = <&gpio3 27 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; + + sii902x@39 { + compatible = "SiI,sii902x"; + interrupt-parent = <&gpio4>; + interrupts = <21 2>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + resets = <&sii902x_reset>; + reg = <0x39>; + status = "disabled"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio4>; + interrupts = <19 2>; + wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + }; +}; + &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; status = "okay"; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio6>; + interrupts = <5 1>; + shared-interrupt; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + interrupt-parent = <&gpio6>; + interrupts = <5 1>; + shared-interrupt; + }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <1>; + interrupt-parent = <&gpio6>; + interrupts = <2 8>; + interrupt-route = <2>; + }; }; &i2c4 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; status = "okay"; codec: wm8962@1a { @@ -209,6 +528,7 @@ PLLVDD-supply = <&vgen4_reg>; SPKVDD1-supply = <®_psu_5v>; SPKVDD2-supply = <®_psu_5v>; + amic-mono; }; }; @@ -217,9 +537,9 @@ pinctrl-0 = <&pinctrl_lcd>; lcd-supply = <®_lcd_3v3>; display = <&display0>; - status = "okay"; + status = "disabled"; - display0: display0 { + display0: display { bits-per-pixel = <16>; bus-width = <24>; @@ -244,20 +564,70 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 0 0>; + status = "okay"; +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; + status = "okay"; + display1: display { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; +&ldb { + status = "okay"; + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "lcdif2"; + status = "okay"; + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + &snvs_poweroff { status = "okay"; }; -&sai1 { +&spdif { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "disabled"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; }; &ssi2 { @@ -273,14 +643,20 @@ &uart5 { /* for bluetooth */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; + fsl,uart-has-rtscts; status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ }; &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; status = "okay"; }; @@ -290,21 +666,13 @@ status = "okay"; }; -&usbphy1 { - fsl,tx-d-cal = <106>; -}; - -&usbphy2 { - fsl,tx-d-cal = <106>; -}; - &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; non-removable; no-1-8-v; keep-power-in-suspend; - wakeup-source; + enable-sdio-wakeup; status = "okay"; }; @@ -317,7 +685,7 @@ cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; keep-power-in-suspend; - wakeup-source; + enable-sdio-wakeup; vmmc-supply = <&vcc_sd3>; status = "okay"; }; @@ -333,11 +701,29 @@ &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; + fsl,wdog_b; }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>; + imx6x-sdb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059 + MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000 + MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 + >; + }; + + pinctrl_can_gpios: can-gpios { + fsl,pins = < + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + >; + }; + pinctrl_audmux: audmuxgrp { fsl,pins = < MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 @@ -348,11 +734,38 @@ >; }; + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 @@ -391,6 +804,20 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + pinctrl_gpio_keys: gpio_keysgrp { fsl,pins = < MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 @@ -405,10 +832,37 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 >; }; @@ -419,6 +873,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4grp-gpio { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1 + MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1 + >; + }; + pinctrl_lcd: lcdgrp { fsl,pins = < MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 @@ -453,6 +914,25 @@ >; }; + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 + >; + }; + pinctrl_peri_3v3: peri3v3grp { fsl,pins = < MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 @@ -465,6 +945,12 @@ >; }; + pinctrl_pwm4: pwm4grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + pinctrl_qspi2: qspi2grp { fsl,pins = < MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 @@ -482,19 +968,25 @@ >; }; - pinctrl_vcc_sd3: vccsd3grp { + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 + >; + }; + + pinctrl_spdif: spdifgrp { fsl,pins = < - MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 >; }; - pinctrl_sai1: sai1grp { + pinctrl_vcc_sd3: vccsd3grp { fsl,pins = < - MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 - MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 - MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 - MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 - MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 >; }; @@ -514,6 +1006,15 @@ >; }; + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usb_otg1: usbotg1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 @@ -545,16 +1046,16 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17069 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17069 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17069 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17069 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17069 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17069 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17069 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17069 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17069 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ >; @@ -603,6 +1104,51 @@ >; }; + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 @@ -610,3 +1156,14 @@ }; }; }; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx.dtsi b/arch/arm/dts/imx6sx.dtsi index 1a473e83efb..aeaacaf0749 100644 --- a/arch/arm/dts/imx6sx.dtsi +++ b/arch/arm/dts/imx6sx.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -30,23 +30,25 @@ i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mmc3 = &usdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - spi4 = &ecspi5; + spi0 = &qspi1; + spi1 = &qspi2; + spi2 = &ecspi1; + spi3 = &ecspi2; + spi4 = &ecspi3; + spi5 = &ecspi4; + spi6 = &ecspi5; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + lcdif0 = &lcdif1; + lcdif1 = &lcdif2; + usb0 = &usbotg1; + usb1 = &usbotg2; }; cpus { @@ -77,14 +79,32 @@ <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_PLL1_SW>, - <&clks IMX6SX_CLK_PLL1_SYS>; + <&clks IMX6SX_CLK_PLL1_SYS>, + <&clks IMX6SX_CLK_PLL1>, + <&clks IMX6SX_PLL1_BYPASS>, + <&clks IMX6SX_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; soc-supply = <®_soc>; }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + intc: interrupt-controller@00a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -138,13 +158,53 @@ interrupt-parent = <&gpc>; ranges; + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>, + <&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>, + <&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>, + <&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>, + <&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>, + <&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>, + <&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM_PODF>, + <&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>, + <&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>, + <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_PODF>, + <&clks IMX6SX_CLK_M4>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", + "pll3_usb_otg", "periph", "periph_pre", "periph_clk2", + "periph_clk2_sel", "osc", "pll1_sys", "periph2", + "ahb", "ocram", "pll1_sw", "periph2_pre", + "periph2_clk2_sel", "periph2_clk2", "step", "mmdc", + "m4"; + fsl,max_ddr_freq = <400000000>; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = ; }; - ocram: sram@00900000 { + ocrams: sram@008f8000 { + compatible = "fsl,lpm-sram"; + reg = <0x008f8000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCRAM_S>; + }; + + ocrams_ddr: sram@00900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00900000 0x1000>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + ocram: sram@00901000 { compatible = "mmio-sram"; + reg = <0x00901000 0x1F000>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + ocram_mf: sram-mf@00900000 { + compatible = "fsl,mega-fast-sram"; reg = <0x00900000 0x20000>; clocks = <&clks IMX6SX_CLK_OCRAM>; }; @@ -159,16 +219,6 @@ arm,data-latency = <4 2 3>; }; - gpu: gpu@01800000 { - compatible = "vivante,gc"; - reg = <0x01800000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_GPU>, - <&clks IMX6SX_CLK_GPU>, - <&clks IMX6SX_CLK_GPU>; - clock-names = "bus", "core", "shader"; - }; - dma_apbh: dma-apbh@01804000 { compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; @@ -182,6 +232,37 @@ clocks = <&clks IMX6SX_CLK_APBH_DMA>; }; + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x00100000 0x3fff>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <0 20 0x04>; + secvio_src = <0x8000001d>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + gpu: gpu@01800000 { + compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu"; + reg = <0x01800000 0x4000>, <0x80000000 0x0>, + <0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = ; + interrupt-names = "irq_3d"; + clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>, + <&clks 0>; + clock-names = "gpu3d_axi_clk", "gpu3d_clk", + "gpu3d_shader_clk"; + resets = <&src 0>; + reset-names = "gpu3d"; + power-domains = <&gpc 1>; + }; + gpmi: gpmi-nand@01806000{ compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; @@ -234,7 +315,7 @@ "rxtx1", "rxtx2", "rxtx3", "rxtx4", "rxtx5", "rxtx6", - "rxtx7", "spba"; + "rxtx7", "dma"; status = "disabled"; }; @@ -247,6 +328,8 @@ clocks = <&clks IMX6SX_CLK_ECSPI1>, <&clks IMX6SX_CLK_ECSPI1>; clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -259,6 +342,8 @@ clocks = <&clks IMX6SX_CLK_ECSPI2>, <&clks IMX6SX_CLK_ECSPI2>; clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -271,6 +356,8 @@ clocks = <&clks IMX6SX_CLK_ECSPI3>, <&clks IMX6SX_CLK_ECSPI3>; clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -283,11 +370,14 @@ clocks = <&clks IMX6SX_CLK_ECSPI4>, <&clks IMX6SX_CLK_ECSPI4>; clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; uart1: serial@02020000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -299,6 +389,7 @@ }; esai: esai@02024000 { + compatible = "fsl,imx35-esai"; reg = <0x02024000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_ESAI_IPG>, @@ -307,7 +398,10 @@ <&clks IMX6SX_CLK_ESAI_IPG>, <&clks IMX6SX_CLK_SPBA>; clock-names = "core", "mem", "extal", - "fsys", "spba"; + "fsys", "dma"; + dmas = <&sdma 23 21 0>, + <&sdma 24 21 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -319,7 +413,7 @@ clocks = <&clks IMX6SX_CLK_SSI1_IPG>, <&clks IMX6SX_CLK_SSI1>; clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; + dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -333,7 +427,7 @@ clocks = <&clks IMX6SX_CLK_SSI2_IPG>, <&clks IMX6SX_CLK_SSI2>; clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; + dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -347,25 +441,34 @@ clocks = <&clks IMX6SX_CLK_SSI3_IPG>, <&clks IMX6SX_CLK_SSI3>; clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; + dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; }; asrc: asrc@02034000 { + compatible = "fsl,imx53-asrc"; reg = <0x02034000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_ASRC_MEM>, - <&clks IMX6SX_CLK_ASRC_IPG>, - <&clks IMX6SX_CLK_SPDIF>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck", "spba"; - dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, - <&sdma 19 20 1>, <&sdma 20 20 1>, - <&sdma 21 20 1>, <&sdma 22 20 1>; + clocks = <&clks IMX6SX_CLK_ASRC_IPG>, + <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "dma"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; status = "okay"; }; }; @@ -417,6 +520,7 @@ clocks = <&clks IMX6SX_CLK_CAN1_IPG>, <&clks IMX6SX_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; @@ -427,6 +531,7 @@ clocks = <&clks IMX6SX_CLK_CAN2_IPG>, <&clks IMX6SX_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; @@ -448,7 +553,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 5 26>; }; gpio2: gpio@020a0000 { @@ -460,7 +564,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 31 20>; }; gpio3: gpio@020a4000 { @@ -472,7 +575,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 51 29>; }; gpio4: gpio@020a8000 { @@ -484,7 +586,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 80 32>; }; gpio5: gpio@020ac000 { @@ -496,7 +597,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 112 24>; }; gpio6: gpio@020b0000 { @@ -508,7 +608,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; }; gpio7: gpio@020b4000 { @@ -520,7 +619,12 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; + }; + + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; }; kpp: kpp@020b8000 { @@ -564,7 +668,7 @@ , ; - regulator-1p1 { + regulator-1p1@110 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <800000>; @@ -576,23 +680,24 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; - regulator-3p0 { + reg_3p0: regulator-3p0@120 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; anatop-vol-bit-width = <5>; anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; - regulator-2p5 { + regulator-2p5@130 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2100000>; @@ -604,9 +709,10 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2100000>; anatop-max-voltage = <2875000>; + anatop-enable-bit = <0>; }; - reg_arm: regulator-vddcore { + reg_arm: regulator-vddcore@140 { compatible = "fsl,anatop-regulator"; regulator-name = "vddarm"; regulator-min-microvolt = <725000>; @@ -623,9 +729,9 @@ anatop-max-voltage = <1450000>; }; - reg_pcie: regulator-vddpcie { + reg_pcie_phy: regulator-vddpcie-phy@140 { compatible = "fsl,anatop-regulator"; - regulator-name = "vddpcie"; + regulator-name = "vddpcie-phy"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; anatop-reg-offset = <0x140>; @@ -639,7 +745,7 @@ anatop-max-voltage = <1450000>; }; - reg_soc: regulator-vddsoc { + reg_soc: regulator-vddsoc@140 { compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; @@ -670,6 +776,7 @@ reg = <0x020c9000 0x1000>; interrupts = ; clocks = <&clks IMX6SX_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; @@ -678,9 +785,21 @@ reg = <0x020ca000 0x1000>; interrupts = ; clocks = <&clks IMX6SX_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; + usbphy_nop1: usbphy_nop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6SX_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + + caam_snvs: caam-snvs@020cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x020cc000 0x4000>; + }; + snvs: snvs@020cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -696,7 +815,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; status = "disabled"; }; @@ -705,7 +824,7 @@ regmap = <&snvs>; interrupts = ; linux,keycode = ; - wakeup-source; + wakeup; }; }; @@ -734,6 +853,16 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>; + clocks = <&clks IMX6SX_CLK_GPU>, <&clks IMX6SX_CLK_IPG>, + <&clks IMX6SX_CLK_PXP_AXI>, <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_LCDIF1_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_LCDIF2_PIX>, <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_VADC>; + clock-names = "gpu3d_core", "ipg", "pxp_axi", "disp_axi", "lcdif1_pix", + "lcdif_axi", "lcdif2_pix", "csi_mclk"; + pcie-phy-supply = <®_pcie_phy>; + #power-domain-cells = <1>; }; iomuxc: iomuxc@020e0000 { @@ -747,8 +876,32 @@ reg = <0x020e4000 0x4000>; }; + ldb: ldb@020e0014 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb"; + gpr = <&gpr>; + status = "disabled"; + clocks = <&clks IMX6SX_CLK_LDB_DI0>, + <&clks IMX6SX_CLK_LCDIF1_SEL>, + <&clks IMX6SX_CLK_LCDIF2_SEL>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_7>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>; + clock-names = "ldb_di0", + "di0_sel", + "di1_sel", + "ldb_di0_div_3_5", + "ldb_di0_div_7", + "ldb_di0_div_sel"; + lvds-channel@0 { + reg = <0>; + status = "disabled"; + }; + }; + sdma: sdma@020ec000 { - compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; + compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SDMA>, @@ -769,17 +922,13 @@ crypto: caam@2100000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; #address-cells = <1>; #size-cells = <1>; - reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6SX_CLK_CAAM_MEM>, - <&clks IMX6SX_CLK_CAAM_ACLK>, - <&clks IMX6SX_CLK_CAAM_IPG>, - <&clks IMX6SX_CLK_EIM_SLOW>; - clock-names = "mem", "aclk", "ipg", "emi_slow"; + reg = <0x2100000 0x40000>; + ranges = <0 0x2100000 0x40000>; + clocks = <&clks IMX6SX_CLK_CAAM_MEM>, <&clks IMX6SX_CLK_CAAM_ACLK>, + <&clks IMX6SX_CLK_CAAM_IPG> ,<&clks IMX6SX_CLK_EIM_SLOW>; + clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow"; sec_jr0: jr0@1000 { compatible = "fsl,sec-v4.0-job-ring"; @@ -828,6 +977,7 @@ clocks = <&clks IMX6SX_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; phy_type = "hsic"; + fsl,usbphy = <&usbphy_nop1>; fsl,anatop = <&anatop>; dr_mode = "host"; ahb-burst-config = <0x0>; @@ -857,15 +1007,20 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <0>; status = "disabled"; }; mlb: mlb@0218c000 { + compatible = "fsl,imx6sx-mlb50"; reg = <0x0218c000 0x4000>; interrupts = , , ; clocks = <&clks IMX6SX_CLK_MLB>; + clock-names = "mlb"; + iram = <&ocram>; status = "disabled"; }; @@ -964,6 +1119,10 @@ <&clks IMX6SX_CLK_ENET_PTP>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + stop-mode = <&gpr 0x10 4>; + fsl,wakeup_irq = <0>; status = "disabled"; }; @@ -975,21 +1134,28 @@ }; ocotp: ocotp@021bc000 { - compatible = "fsl,imx6sx-ocotp", "syscon"; + compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SX_CLK_OCOTP>; }; + romcp@021ac000 { + compatible = "fsl,imx6sx-romcp", "syscon"; + reg = <0x021ac000 0x4000>; + }; + sai1: sai@021d4000 { compatible = "fsl,imx6sx-sai"; reg = <0x021d4000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SAI1_IPG>, + <&clks IMX6SX_CLK_DUMMY>, <&clks IMX6SX_CLK_SAI1>, <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; + dma-source = <&gpr 0 15 0 16>; status = "disabled"; }; @@ -1004,11 +1170,13 @@ reg = <0x021dc000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SAI2_IPG>, + <&clks IMX6SX_CLK_DUMMY>, <&clks IMX6SX_CLK_SAI2>, <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; - dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; + dmas = <&sdma 33 23 0>, <&sdma 34 23 0>; + dma-source = <&gpr 0 17 0 18>; status = "disabled"; }; @@ -1038,8 +1206,15 @@ status = "disabled"; }; + qspi_m4: qspi-m4 { + compatible = "fsl,imx6sx-qspi-m4-restore"; + reg = <0x021e4000 0x4000>; + status = "disabled"; + }; + uart2: serial@021e8000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1051,7 +1226,8 @@ }; uart3: serial@021ec000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1063,7 +1239,8 @@ }; uart4: serial@021f0000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1075,7 +1252,8 @@ }; uart5: serial@021f4000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1095,6 +1273,11 @@ clocks = <&clks IMX6SX_CLK_I2C4>; status = "disabled"; }; + + qosc: qosc@021fc000 { + compatible = "fsl,imx6sx-qosc"; + reg = <0x021fc000 0x4000>; + }; }; aips3: aips-bus@02200000 { @@ -1112,31 +1295,59 @@ ranges; csi1: csi@02214000 { + compatible = "fsl,imx6s-csi"; reg = <0x02214000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, <&clks IMX6SX_CLK_CSI>, <&clks IMX6SX_CLK_DCIC1>; - clock-names = "disp-axi", "csi_mclk", "dcic"; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + power-domains = <&gpc 2>; + status = "disabled"; + }; + + dcic1: dcic@0220c000 { + compatible = "fsl,imx6sx-dcic"; + reg = <0x0220c000 0x4000>; + interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_DCIC1>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; + }; + + dcic2: dcic@02210000 { + compatible = "fsl,imx6sx-dcic"; + reg = <0x02210000 0x4000>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_DCIC2>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; status = "disabled"; }; pxp: pxp@02218000 { + compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; reg = <0x02218000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_PXP_AXI>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pxp-axi", "disp-axi"; + power-domains = <&gpc 2>; status = "disabled"; }; csi2: csi@0221c000 { + compatible = "fsl,imx6s-csi"; reg = <0x0221c000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, <&clks IMX6SX_CLK_CSI>, <&clks IMX6SX_CLK_DCIC2>; - clock-names = "disp-axi", "csi_mclk", "dcic"; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + power-domains = <&gpc 2>; status = "disabled"; }; @@ -1148,6 +1359,7 @@ <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&gpc 2>; status = "disabled"; }; @@ -1159,15 +1371,19 @@ <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&gpc 2>; status = "disabled"; }; vadc: vadc@02228000 { + compatible = "fsl,imx6sx-vadc"; reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; reg-names = "vadc-vafe", "vadc-vdec"; clocks = <&clks IMX6SX_CLK_VADC>, <&clks IMX6SX_CLK_CSI>; clock-names = "vadc", "csi"; + power-domains = <&gpc 2>; + gpr = <&gpr>; status = "disabled"; }; }; @@ -1177,9 +1393,8 @@ reg = <0x02280000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_IPG>; + num-channels = <4>; clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; status = "disabled"; }; @@ -1188,9 +1403,8 @@ reg = <0x02284000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_IPG>; + num-channels = <4>; clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; status = "disabled"; }; @@ -1214,8 +1428,28 @@ status = "disabled"; }; + sema4: sema4@02290000 { /* sema4 */ + compatible = "fsl,imx6sx-sema4"; + reg = <0x02290000 0x4000>; + interrupts = <0 116 0x04>; + status = "okay"; + }; + + mu: mu@02294000 { /* mu */ + compatible = "fsl,imx6sx-mu"; + reg = <0x02294000 0x4000>; + interrupts = <0 90 0x04>; + status = "okay"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx6sx-rpmsg"; + status = "disabled"; + }; + uart6: serial@022a0000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x022a0000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1269,30 +1503,30 @@ pcie: pcie@0x08000000 { compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; - reg = <0x08ffc000 0x4000>; /* DBI */ + reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>; + reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - /* configuration space */ - ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 - /* downstream I/O */ - 0x81000000 0 0 0x08f80000 0 0x00010000 - /* non-prefetchable memory */ - 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; + ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, - <&clks IMX6SX_CLK_PCIE_AXI>, + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_PCIE_AXI>, <&clks IMX6SX_CLK_LVDS1_OUT>, + <&clks IMX6SX_CLK_PCIE_REF_125M>, <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pcie_ref_125m", "pcie_axi", - "lvds_gate", "display_axi"; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + pcie-phy-supply = <®_pcie_phy>; + power-domains = <&gpc 2>; status = "disabled"; }; }; - - gpu-subsystem { - compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu>; - }; }; diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-arm2-emmc.dts b/arch/arm/dts/imx6ul-14x14-ddr3-arm2-emmc.dts new file mode 100644 index 00000000000..2e35ed6d353 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-ddr3-arm2-emmc.dts @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-arm2.dts" + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1_8bit>; + pinctrl-1 = <&pinctrl_usdhc1_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_8bit_200mhz>; + bus-width = <8>; + cd-gpios = <>; + wp-gpios = <>; + vmmc-supply = <>; + tuning-step = <2>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-arm2-gpmi-weim.dts b/arch/arm/dts/imx6ul-14x14-ddr3-arm2-gpmi-weim.dts new file mode 100644 index 00000000000..2e6b54495d0 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-ddr3-arm2-gpmi-weim.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-arm2.dts" + +/* + * solve pin conflict with NAND + * + * USDHC2_CD, SD2_RST_B, USDHC2_WP conflict with RAWNAND CE pins , also + * overwritten the conflict of SD2_RST_B with RAWNAND ALE in hog + * QSPI CLK, CE and DATA pins conflict with RAWNAND data pins and CE, CLE, RB, + * WP, DQS pin + * + */ +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; +}; + +&qspi{ + status = "disabled"; +}; + +&gpmi{ + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-arm2.dts b/arch/arm/dts/imx6ul-14x14-ddr3-arm2.dts new file mode 100644 index 00000000000..622a7d666ec --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-ddr3-arm2.dts @@ -0,0 +1,774 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite DDR3 ARM2 Board"; + compatible = "fsl,imx6ul-14x14-ddr3-arm2", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1a_reg>; + fsl,arm-soc-shared = <1>; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "okay"; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,n25q032"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "mii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + }; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog1 &pinctrl_hog_sd>; + + imx6ul-ddr3-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x17059 /* SD2 CD */ + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x17059 /* SD2 WP */ + >; + }; + + pinctrl_hog1: hoggrp1 { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESECT */ + >; + }; + + pinctrl_hog_sd: hoggrp_sd { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */ + >; + }; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_bt: btgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0b0 + MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0 + MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x1b8b1 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088 + MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0 + MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0 + MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0 + MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x1f0b8 + MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0 + MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1_8bit_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170f9 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100f9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + }; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 + &pinctrl_bt>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-evk-emmc.dts b/arch/arm/dts/imx6ul-14x14-evk-emmc.dts new file mode 100644 index 00000000000..b56d34d9f8a --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-evk-emmc.dts @@ -0,0 +1,20 @@ + +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts b/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts new file mode 100644 index 00000000000..7cff0874697 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&iomuxc { + imx6ul-evk-gpmi-rework { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-evk.dts b/arch/arm/dts/imx6ul-14x14-evk.dts new file mode 100644 index 00000000000..dea65aaba35 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-evk.dts @@ -0,0 +1,780 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; + compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + }; + + sound: sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <3 0>; + hp-det-gpios = <&gpio5 4 0>; + mic-det-gpios = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; + dc-supply = <®_gpio_dvfs>; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* used for lcd reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_pf1550: pf1550 { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x80000000 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + + pinctrl_sim2_1: sim2grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x11 + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb810 + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb810 + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb811 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_8bit: usdhc2grp_8bit { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + + status = "okay"; +}; + +&sim2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim2_1>; + assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; + assigned-clock-rates = <240000000>; + /* GPIO_ACTIVE_HIGH/LOW:sim card voltage control + * NCN8025:Vcc = ACTIVE_HIGH?5V:3V + * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V + */ + pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + port = <1>; + sven_low_active; + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/arch/arm/dts/imx6ul-14x14-lpddr2-arm2.dts b/arch/arm/dts/imx6ul-14x14-lpddr2-arm2.dts new file mode 100644 index 00000000000..c1121416c82 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-lpddr2-arm2.dts @@ -0,0 +1,780 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 14X14 LPDDR2 ARM2 Board"; + compatible = "fsl,imx6ul-14x14-lpddr2-arm2", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 22 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2_1 &pinctrl_ecspi2_cs_1>; + status = "disabled"; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,n25q032"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1a_reg>; + fsl,arm-soc-shared = <1>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x2>; + fsl,cpu_pupscr_sw = <0x1>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,wdog-reset = <1>; /* watchdog select of reset source */ + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "disabled"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + keep-power-in-suspend; + vmmc-supply = <®_sd2_vmmc>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog_nand>; + + imx6ul-14x14-lpddr2-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* SD1 CD */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* SD1 WP */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */ + >; + }; + + pinctrl_hog_nand: hoggrp_nand { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x17059 /* SD1 RESET */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */ + >; + }; + + pinctrl_ecspi2_cs_1: ecspi2_cs_grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 + >; + }; + + pinctrl_ecspi2_1: ecspi2grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x10b0 + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x10b0 + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 + MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x1b0b0 + MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x4b01b0a8 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 + MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x4b01b0a8 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x1b0b0 + MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x1b0b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x11088 + MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x11088 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x1b0b0 + MX6UL_PAD_SD1_CLK__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1_8bit_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_8bit: usdhc2_8bit_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6ul-9x9-evk.dts b/arch/arm/dts/imx6ul-9x9-evk.dts new file mode 100644 index 00000000000..34dc8d1cf57 --- /dev/null +++ b/arch/arm/dts/imx6ul-9x9-evk.dts @@ -0,0 +1,832 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 9x9 EVK Board"; + compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x6000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <3 0>; + hp-det-gpios = <&gpio5 4 0>; + mic-det-gpios = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + arm-supply = <&sw1c_reg>; + soc-supply = <&sw1c_reg>; + fsl,arm-soc-shared = <1>; +}; + +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,wdog-reset = <1>; /* watchdog select of reset source */ + fsl,ldo-bypass = <1>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* used for lcd reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + + pinctrl_sim2_1: sim2grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + + status = "okay"; +}; + +&sim2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim2_1>; + assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; + assigned-clock-rates = <240000000>; + pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + port = <1>; + sven_low_active; + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure_delay_time = <0xffff>; + pre_charge_time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/arch/arm/dts/imx6ul-pinfunc.h b/arch/arm/dts/imx6ul-pinfunc.h index 0034eeb8454..1d43f51dfcf 100644 --- a/arch/arm/dts/imx6ul-pinfunc.h +++ b/arch/arm/dts/imx6ul-pinfunc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2014 - 2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -14,925 +14,948 @@ * The pin function ID is a tuple of * */ -#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 -#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 - -#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0 - -#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0 -#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0 -#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0 -#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 -#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 -#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 -#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0 -#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 -#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 -#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x0000 2 0 -#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 -#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 -#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0 -#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 -#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 -#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 -#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0 -#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0 -#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0 -#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0 -#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0 -#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0 -#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0 -#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0 -#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0 -#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0 -#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0 -#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0 -#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0 -#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0 -#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0 -#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 -#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 -#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 -#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 -#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 -#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 -#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 -#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 -#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 -#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 -#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0 -#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0 -#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1 -#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0 -#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0 -#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0 -#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 -#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 -#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 -#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 -#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 -#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 -#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 -#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2 -#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1 -#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0 -#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0 -#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3 -#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0 -#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0 -#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0 -#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0 -#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0 -#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1 -#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1 -#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1 -#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1 -#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1 -#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0 -#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1 -#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2 -#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0 -#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2 -#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0 -#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0 -#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04c4 3 1 -#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0 -#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0 -#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0 -#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3 -#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0 -#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0 -#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0 -#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04c8 3 1 -#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0 -#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0 -#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 8 1 -#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0 -#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2 -#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0 -#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1 -#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x04d8 3 0 -#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0 -#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0 -#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x069c 8 1 -#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3 -#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0 -#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0 -#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1 -#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x04cc 3 1 -#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0 -#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0 -#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0674 8 2 -#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0 -#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0 -#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0 -#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0 -#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 -#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 -#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 -#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0 -#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 -#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 -#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 -#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0 -#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04e0 3 0 -#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0 -#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0 -#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0 -#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 8 0 -#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0 -#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0 -#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0 -#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0 -#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x04e4 3 0 -#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0 -#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0 -#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0 -#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x055c 8 0 -#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1 -#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0 -#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0 -#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0 -#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x04e8 3 0 -#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0 -#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0 -#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0 -#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0558 8 0 -#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0 -#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 -#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 -#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 -#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x0000 3 0 -#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 -#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 -#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 -#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0 -#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x04b8 8 1 -#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1 -#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 -#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 -#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 -#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x0000 3 0 -#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 -#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 -#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 -#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0 -#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0 -#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 -#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 -#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 -#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x0000 3 0 -#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 -#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 -#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 -#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1 -#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 -#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 -#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 -#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x0000 3 0 -#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 -#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 -#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 -#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0 -#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 -#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 -#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 -#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x0000 3 0 -#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 -#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 -#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 -#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1 -#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 -#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 -#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 -#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x0000 3 0 -#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 -#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 -#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0000 8 0 -#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 -#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 -#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 -#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 -#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 -#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 -#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x0000 3 0 -#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 -#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 -#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 -#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 -#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 -#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0000 3 0 -#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 -#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 -#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 -#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0000 3 0 -#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x0000 6 0 -#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 -#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 -#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0000 3 0 -#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 -#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x0000 6 0 -#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 -#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 -#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x0000 3 0 -#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x0000 6 0 -#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 -#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0000 3 0 -#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 -#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x0000 6 0 -#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 -#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0000 3 0 -#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 -#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x0000 6 0 -#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 -#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0000 3 0 -#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 -#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x0000 6 0 -#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 -#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x0000 3 0 -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 -#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 -#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0594 8 1 -#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 -#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0000 3 0 -#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 -#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0590 8 1 -#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1 -#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1 -#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1 -#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0 -#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 -#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8 0x0374 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 -#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0664 8 1 -#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0 -#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1 -#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1 -#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1 -#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 -#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0 -#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 -#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 -#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0660 8 1 -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0 -#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0 -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2 -#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x04bc 8 1 -#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 -#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0000 3 0 -#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0 -#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0 -#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 -#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 -#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 -#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0 -#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 -#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 -#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 -#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0 -#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0 -#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3 -#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0 -#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0 -#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0 -#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0 -#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0 -#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0 -#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0 -#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0 -#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2 -#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0 -#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0 -#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0 -#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0 -#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0 -#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 -#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 -#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 -#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0000 3 0 -#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 -#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 -#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 -#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0 -#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0 -#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0 -#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0 -#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0 -#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0 -#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 -#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 -#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 -#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 -#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 -#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 -#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 -#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 -#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 -#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 -#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 -#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 -#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 -#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 -#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 -#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 -#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 -#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0690 8 0 -#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 -#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0694 8 0 -#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 -#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0698 8 0 -#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0678 8 1 -#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0670 8 1 -#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x067c 8 1 -#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 -#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 -#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 -#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0680 8 1 -#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 -#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0684 8 0 -#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 -#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 8 1 -#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 -#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 -#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 -#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0 -#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 -#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 -#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 -#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 -#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 -#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 -#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x0000 3 0 -#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 -#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 -#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 -#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x0000 3 0 -#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 -#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0 -#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 -#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0 -#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 -#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x0000 3 0 -#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1 -#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1 -#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2 -#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1 -#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1 -#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3 -#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1 -#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1 -#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4 -#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 -#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0000 3 0 -#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 -#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0 -#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0 -#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0 -#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0 -#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0 -#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0 -#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0 -#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0 -#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0 -#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0 -#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0 -#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0 -#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0 -#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0 -#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0 -#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 -#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 -#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 -#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0000 3 0 -#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 -#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 -#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 -#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2 -#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0 -#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0 -#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0 -#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1 -#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0 -#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0 -#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3 -#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0 -#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0 -#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0 -#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0 -#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1 -#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0 -#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0 -#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0 -#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2 -#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0 -#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0 -#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0 -#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1 -#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0 -#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0 -#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3 -#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0 -#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0 -#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1 -#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0 -#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 -#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 -#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 -#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0000 6 0 -#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 -#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 -#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 -#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0 -#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 -#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 -#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 -#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0000 6 0 -#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 -#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 -#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 -#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x0000 2 0 -#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 -#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 -#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 -#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0664 8 2 -#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0 -#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1 -#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0 -#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x04b8 8 2 -#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1 -#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1 -#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3 -#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0 -#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1 -#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1 -#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0 -#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0 -#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0660 8 2 -#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1 -#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0 -#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3 -#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0 -#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x04bc 8 2 -#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0 -#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0 -#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0 -#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0 -#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0 -#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0 -#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0 -#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0 -#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0 -#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1 -#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2 -#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0 -#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2 -#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0 -#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0 -#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0 -#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3 -#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0 -#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0 -#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0 -#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0 -#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0 -#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0 -#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0 -#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0 -#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0 -#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0 -#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0 -#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0 -#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0 -#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0 -#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0 -#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0 -#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0 -#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0 -#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1 -#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0 -#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0 -#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0 -#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0 -#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 -#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 -#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0000 3 0 -#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 -#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 -#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2 -#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1 -#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5 -#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0 -#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0 -#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0 -#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0 -#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1 -#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2 -#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1 -#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1 -#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x066c 8 2 -#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 -#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 -#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0000 3 0 -#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 -#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0668 8 2 -#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1 -#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2 -#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 -#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 -#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 -#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1 -#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0 +#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02A0 0x0000 0x5 0x0 +#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02A4 0x0000 0x5 0x0 +#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001C 0x02A8 0x0000 0x5 0x0 +#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02AC 0x0000 0x5 0x0 +#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02B0 0x0000 0x5 0x0 +#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02B4 0x0000 0x5 0x0 +#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002C 0x02B8 0x0000 0x5 0x0 +#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02BC 0x0000 0x5 0x0 +#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02C0 0x0000 0x5 0x0 +#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02C4 0x0000 0x5 0x0 +#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003C 0x02C8 0x0000 0x5 0x0 +#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02CC 0x0000 0x5 0x0 +#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02D0 0x0000 0x0 0x0 +#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02D0 0x05A0 0x1 0x0 +#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02D0 0x0000 0x2 0x0 +#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02D0 0x0000 0x3 0x0 +#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02D0 0x04C0 0x4 0x0 +#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02D0 0x0000 0x5 0x0 +#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02D0 0x0610 0x6 0x0 +#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02D4 0x0000 0x0 0x0 +#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02D4 0x0598 0x1 0x0 +#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02D4 0x05F0 0x2 0x0 +#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02D4 0x0000 0x3 0x0 +#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02D4 0x0000 0x4 0x0 +#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02D4 0x0000 0x5 0x0 +#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02D4 0x0614 0x6 0x0 +#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02D4 0x0000 0x8 0x0 +#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004C 0x02D8 0x0000 0x0 0x0 +#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004C 0x02D8 0x059C 0x1 0x0 +#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004C 0x02D8 0x05FC 0x2 0x0 +#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004C 0x02D8 0x0000 0x3 0x0 +#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004C 0x02D8 0x0000 0x4 0x0 +#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004C 0x02D8 0x0000 0x5 0x0 +#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004C 0x02D8 0x0000 0x6 0x0 +#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004C 0x02D8 0x0000 0x8 0x0 +#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02DC 0x0000 0x0 0x0 +#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02DC 0x0000 0x1 0x0 +#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02DC 0x05F8 0x2 0x0 +#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02DC 0x0000 0x4 0x0 +#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02DC 0x0000 0x5 0x0 +#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02DC 0x0000 0x6 0x0 +#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02DC 0x0000 0x8 0x0 +#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02E0 0x0000 0x0 0x0 +#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02E0 0x0000 0x1 0x0 +#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02E0 0x05F4 0x2 0x0 +#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02E0 0x0000 0x4 0x0 +#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02E0 0x0000 0x5 0x0 +#define MX6UL_PAD_JTAG_TCK__REF_CLK_32K 0x0054 0x02E0 0x0000 0x6 0x0 +#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02E0 0x0000 0x8 0x0 +#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02E4 0x0000 0x0 0x0 +#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02E4 0x0000 0x1 0x0 +#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02E4 0x0000 0x2 0x0 +#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02E4 0x0000 0x4 0x0 +#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02E4 0x0000 0x5 0x0 +#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058 0x02E4 0x0000 0x6 0x0 +#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02E4 0x0000 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005C 0x02E8 0x05AC 0x0 0x1 +#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005C 0x02E8 0x058C 0x1 0x0 +#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005C 0x02E8 0x04B8 0x2 0x0 +#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005C 0x02E8 0x0574 0x3 0x0 +#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005C 0x02E8 0x0000 0x4 0x0 +#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005C 0x02E8 0x0000 0x5 0x0 +#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005C 0x02E8 0x0000 0x6 0x0 +#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005C 0x02E8 0x0000 0x7 0x0 +#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005C 0x02E8 0x0000 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02EC 0x05B0 0x0 0x1 +#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02EC 0x0000 0x1 0x0 +#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02EC 0x0664 0x2 0x0 +#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02EC 0x057C 0x3 0x0 +#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02EC 0x0000 0x4 0x0 +#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02EC 0x0000 0x5 0x0 +#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02EC 0x0000 0x6 0x0 +#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02EC 0x0000 0x7 0x0 +#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02EC 0x0000 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02F0 0x05A4 0x0 0x0 +#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02F0 0x0000 0x1 0x0 +#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02F0 0x0000 0x2 0x0 +#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02F0 0x0000 0x3 0x0 +#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02F0 0x066C 0x4 0x0 +#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02F0 0x0000 0x5 0x0 +#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02F0 0x0610 0x6 0x1 +#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02F0 0x0000 0x7 0x0 +#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02F0 0x0000 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02F0 0x0624 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02F4 0x05A8 0x0 0x1 +#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02F4 0x0000 0x1 0x0 +#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02F4 0x0660 0x2 0x0 +#define MX6UL_PAD_GPIO1_IO03__REF_CLK_32K 0x0068 0x02F4 0x0000 0x3 0x0 +#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02F4 0x0668 0x4 0x0 +#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02F4 0x0000 0x5 0x0 +#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02F4 0x0000 0x6 0x0 +#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02F4 0x0000 0x7 0x0 +#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02F4 0x0624 0x8 0x1 +#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02F4 0x0000 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006C 0x02F8 0x0574 0x0 0x1 +#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006C 0x02F8 0x0000 0x1 0x0 +#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006C 0x02F8 0x0000 0x2 0x0 +#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006C 0x02F8 0x0000 0x3 0x0 +#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006C 0x02F8 0x0000 0x4 0x0 +#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006C 0x02F8 0x0000 0x5 0x0 +#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006C 0x02F8 0x0000 0x6 0x0 +#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006C 0x02F8 0x0000 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006C 0x02F8 0x0644 0x8 0x2 +#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02FC 0x057C 0x0 0x1 +#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02FC 0x0000 0x1 0x0 +#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02FC 0x04BC 0x2 0x0 +#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02FC 0x0530 0x3 0x0 +#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02FC 0x0000 0x4 0x0 +#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02FC 0x0000 0x5 0x0 +#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02FC 0x0000 0x6 0x0 +#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02FC 0x0644 0x8 0x3 +#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02FC 0x0000 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0x0 0x0 +#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 0x1 0x0 +#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 0x2 0x0 +#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 0x3 0x0 +#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069C 0x4 0x0 +#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 0x5 0x0 +#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 0x6 0x0 +#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 0x7 0x0 +#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0x0 0x0 +#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 0x1 0x0 +#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 0x2 0x0 +#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 0x3 0x0 +#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 0x4 0x1 +#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 0x5 0x0 +#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 0x6 0x0 +#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 0x8 0x1 +#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007C 0x0308 0x0000 0x0 0x0 +#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007C 0x0308 0x0000 0x1 0x0 +#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007C 0x0308 0x0000 0x2 0x0 +#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007C 0x0308 0x052C 0x3 0x1 +#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007C 0x0308 0x0000 0x4 0x0 +#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007C 0x0308 0x0000 0x5 0x0 +#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007C 0x0308 0x04C0 0x6 0x1 +#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007C 0x0308 0x0640 0x8 0x1 +#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007C 0x0308 0x0000 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030C 0x0000 0x0 0x0 +#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030C 0x0000 0x1 0x0 +#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030C 0x0618 0x2 0x0 +#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030C 0x0524 0x3 0x1 +#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030C 0x0000 0x4 0x0 +#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030C 0x0000 0x5 0x0 +#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030C 0x0000 0x6 0x0 +#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030C 0x0000 0x8 0x0 +#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030C 0x0640 0x8 0x2 +#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0x0 0x0 +#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0x0 0x2 +#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 0x1 0x0 +#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05B4 0x2 0x0 +#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04C4 0x3 0x1 +#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 0x4 0x0 +#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 0x5 0x0 +#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 0x8 0x0 +#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0x0 0x3 +#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0x0 0x0 +#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 0x1 0x0 +#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05B8 0x2 0x0 +#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04C8 0x3 0x1 +#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 0x4 0x0 +#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 0x5 0x0 +#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 0x8 0x1 +#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008C 0x0318 0x0000 0x0 0x0 +#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008C 0x0318 0x0620 0x0 0x2 +#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008C 0x0318 0x0000 0x1 0x0 +#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008C 0x0318 0x066C 0x2 0x1 +#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008C 0x0318 0x04D8 0x3 0x0 +#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008C 0x0318 0x0000 0x4 0x0 +#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008C 0x0318 0x0000 0x5 0x0 +#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008C 0x0318 0x069C 0x8 0x1 +#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031C 0x0620 0x0 0x3 +#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031C 0x0000 0x0 0x0 +#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031C 0x0000 0x1 0x0 +#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031C 0x0668 0x2 0x1 +#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031C 0x04CC 0x3 0x1 +#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031C 0x0000 0x4 0x0 +#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031C 0x0000 0x5 0x0 +#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031C 0x0674 0x8 0x2 +#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0x0 0x0 +#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062C 0x0 0x0 +#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 0x1 0x0 +#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05BC 0x2 0x0 +#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04DC 0x3 0x0 +#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058C 0x4 0x1 +#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 0x5 0x0 +#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0560 0x8 0x0 +#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062C 0x0 0x1 +#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0x0 0x0 +#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 0x1 0x0 +#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05C0 0x2 0x0 +#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04E0 0x3 0x0 +#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 0x4 0x0 +#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 0x5 0x0 +#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 0x7 0x0 +#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 0x8 0x0 +#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009C 0x0328 0x0000 0x0 0x0 +#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009C 0x0328 0x0628 0x0 0x0 +#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009C 0x0328 0x0000 0x1 0x0 +#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009C 0x0328 0x0000 0x2 0x0 +#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009C 0x0328 0x04E4 0x3 0x0 +#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009C 0x0328 0x0000 0x4 0x0 +#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009C 0x0328 0x0000 0x5 0x0 +#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009C 0x0328 0x0000 0x7 0x0 +#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009C 0x0328 0x055C 0x8 0x0 +#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00A0 0x032C 0x0628 0x0 0x1 +#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00A0 0x032C 0x0000 0x0 0x0 +#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00A0 0x032C 0x0000 0x1 0x0 +#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00A0 0x032C 0x0588 0x2 0x0 +#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00A0 0x032C 0x04E8 0x3 0x0 +#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00A0 0x032C 0x0000 0x4 0x0 +#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00A0 0x032C 0x0000 0x5 0x0 +#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00A0 0x032C 0x0000 0x7 0x0 +#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00A0 0x032C 0x0558 0x8 0x0 +#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00A4 0x0330 0x0000 0x0 0x0 +#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00A4 0x0330 0x0634 0x0 0x0 +#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00A4 0x0330 0x0000 0x1 0x0 +#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00A4 0x0330 0x0000 0x2 0x0 +#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00A4 0x0330 0x04D4 0x3 0x0 +#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00A4 0x0330 0x0000 0x4 0x0 +#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00A4 0x0330 0x0628 0x4 0x2 +#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00A4 0x0330 0x0000 0x5 0x0 +#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00A4 0x0330 0x0000 0x7 0x0 +#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00A4 0x0330 0x04B8 0x8 0x1 +#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00A8 0x0334 0x0634 0x0 0x1 +#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00A8 0x0334 0x0000 0x0 0x0 +#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00A8 0x0334 0x0000 0x1 0x0 +#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00A8 0x0334 0x0000 0x2 0x0 +#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00A8 0x0334 0x04D0 0x3 0x0 +#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00A8 0x0334 0x0628 0x4 0x3 +#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00A8 0x0334 0x0000 0x4 0x0 +#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00A8 0x0334 0x0000 0x5 0x0 +#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00A8 0x0334 0x0000 0x8 0x0 +#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00AC 0x0338 0x0000 0x0 0x0 +#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00AC 0x0338 0x0630 0x0 0x0 +#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00AC 0x0338 0x0000 0x1 0x0 +#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00AC 0x0338 0x0000 0x2 0x0 +#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00AC 0x0338 0x04EC 0x3 0x0 +#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00AC 0x0338 0x0000 0x4 0x0 +#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00AC 0x0338 0x0000 0x5 0x0 +#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00AC 0x0338 0x0000 0x8 0x0 +#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00B0 0x033C 0x0630 0x0 0x1 +#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00B0 0x033C 0x0000 0x0 0x0 +#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00B0 0x033C 0x0000 0x1 0x0 +#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00B0 0x033C 0x0584 0x2 0x0 +#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00B0 0x033C 0x04F0 0x3 0x0 +#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00B0 0x033C 0x0000 0x4 0x0 +#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00B0 0x033C 0x0000 0x5 0x0 +#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00B0 0x033C 0x0000 0x8 0x0 +#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00B4 0x0340 0x0000 0x0 0x0 +#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00B4 0x0340 0x063C 0x0 0x0 +#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00B4 0x0340 0x0000 0x1 0x0 +#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00B4 0x0340 0x05A4 0x2 0x1 +#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00B4 0x0340 0x04F4 0x3 0x0 +#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00B4 0x0340 0x0000 0x4 0x0 +#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00B4 0x0340 0x0000 0x5 0x0 +#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00B4 0x0340 0x0544 0x8 0x1 +#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00B8 0x0344 0x063C 0x0 0x1 +#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00B8 0x0344 0x0000 0x0 0x0 +#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00B8 0x0344 0x0000 0x1 0x0 +#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00B8 0x0344 0x05A8 0x2 0x2 +#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00B8 0x0344 0x04F8 0x3 0x0 +#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00B8 0x0344 0x0000 0x4 0x0 +#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00B8 0x0344 0x0000 0x5 0x0 +#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00B8 0x0344 0x0550 0x8 0x1 +#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00BC 0x0348 0x0000 0x5 0x0 +#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00BC 0x0348 0x054C 0x8 0x0 +#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00BC 0x0348 0x0000 0x0 0x0 +#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x4 +#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00BC 0x0348 0x0000 0x1 0x0 +#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00BC 0x0348 0x05AC 0x2 0x2 +#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00BC 0x0348 0x04FC 0x3 0x0 +#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00BC 0x0348 0x0000 0x4 0x0 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x5 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00C0 0x034C 0x0000 0x0 0x0 +#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00C0 0x034C 0x0000 0x1 0x0 +#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00C0 0x034C 0x05B0 0x2 0x2 +#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00C0 0x034C 0x0500 0x3 0x0 +#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00C0 0x034C 0x0000 0x4 0x0 +#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00C0 0x034C 0x0000 0x5 0x0 +#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00C0 0x034C 0x0548 0x8 0x1 +#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00C4 0x0350 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00C4 0x0350 0x0638 0x1 0x0 +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00C4 0x0350 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00C4 0x0350 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00C4 0x0350 0x0504 0x3 0x0 +#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00C4 0x0350 0x0000 0x4 0x0 +#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00C4 0x0350 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00C4 0x0350 0x05D0 0x6 0x0 +#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00C4 0x0350 0x0000 0x8 0x0 +#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00C8 0x0354 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00C8 0x0354 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00C8 0x0354 0x0638 0x1 0x1 +#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00C8 0x0354 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00C8 0x0354 0x0508 0x3 0x0 +#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00C8 0x0354 0x0584 0x4 0x1 +#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00C8 0x0354 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00C8 0x0354 0x05C4 0x6 0x0 +#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00C8 0x0354 0x0000 0x8 0x0 +#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00CC 0x0358 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x3 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00CC 0x0358 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET1_RX_EN__REF_CLK_32K 0x00CC 0x0358 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00CC 0x0358 0x050C 0x3 0x0 +#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00CC 0x0358 0x0000 0x4 0x0 +#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00CC 0x0358 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00CC 0x0358 0x05D4 0x6 0x0 +#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00CC 0x0358 0x0000 0x8 0x0 +#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00D0 0x035C 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00D0 0x035C 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x4 +#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00D0 0x035C 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00D0 0x035C 0x0510 0x3 0x0 +#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00D0 0x035C 0x0588 0x4 0x1 +#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00D0 0x035C 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00D0 0x035C 0x05C8 0x6 0x0 +#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00D0 0x035C 0x0000 0x8 0x0 +#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00D4 0x0360 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00D4 0x0360 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00D4 0x0360 0x0648 0x1 0x2 +#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00D4 0x0360 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00D4 0x0360 0x0514 0x3 0x0 +#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00D4 0x0360 0x0580 0x4 0x1 +#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00D4 0x0360 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00D4 0x0360 0x05D8 0x6 0x0 +#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00D4 0x0360 0x0000 0x8 0x0 +#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00D8 0x0364 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00D8 0x0364 0x0648 0x1 0x3 +#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00D8 0x0364 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00D8 0x0364 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00D8 0x0364 0x0518 0x3 0x0 +#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00D8 0x0364 0x0000 0x4 0x0 +#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00D8 0x0364 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00D8 0x0364 0x05CC 0x6 0x0 +#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00D8 0x0364 0x0000 0x8 0x0 +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00DC 0x0368 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00DC 0x0368 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00DC 0x0368 0x0650 0x1 0x0 +#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00DC 0x0368 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00DC 0x0368 0x051C 0x3 0x0 +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00DC 0x0368 0x0574 0x4 0x2 +#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00DC 0x0368 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00DC 0x0368 0x0000 0x6 0x0 +#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00DC 0x0368 0x0594 0x8 0x1 +#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00E0 0x036C 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00E0 0x036C 0x0650 0x1 0x1 +#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00E0 0x036C 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00E0 0x036C 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00E0 0x036C 0x0520 0x3 0x0 +#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00E0 0x036C 0x0000 0x4 0x0 +#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00E0 0x036C 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00E0 0x036C 0x0000 0x6 0x0 +#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00E0 0x036C 0x0590 0x8 0x1 +#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00E4 0x0370 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00E4 0x0370 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00E4 0x0370 0x064C 0x1 0x1 +#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00E4 0x0370 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00E4 0x0370 0x05B4 0x3 0x1 +#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00E4 0x0370 0x0578 0x4 0x1 +#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00E4 0x0370 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00E4 0x0370 0x0000 0x6 0x0 +#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00E4 0x0370 0x0000 0x8 0x0 +#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00E8 0x0374 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00E8 0x0374 0x064C 0x1 0x2 +#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00E8 0x0374 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00E8 0x0374 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00E8 0x0374 0x05B8 0x3 0x1 +#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00E8 0x0374 0x0000 0x4 0x0 +#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00E8 0x0374 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00E8 0x0374 0x0000 0x6 0x0 +#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00E8 0x0374 0x0664 0x8 0x1 +#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00EC 0x0378 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00EC 0x0378 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00EC 0x0378 0x0654 0x1 0x0 +#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00EC 0x0378 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00EC 0x0378 0x05BC 0x3 0x1 +#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00EC 0x0378 0x0000 0x4 0x0 +#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00EC 0x0378 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00EC 0x0378 0x0000 0x6 0x0 +#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00EC 0x0378 0x0000 0x8 0x0 +#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00F0 0x037C 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00F0 0x037C 0x0654 0x1 0x1 +#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00F0 0x037C 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00F0 0x037C 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00F0 0x037C 0x05C0 0x3 0x1 +#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00F0 0x037C 0x0000 0x4 0x0 +#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00F0 0x037C 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00F0 0x037C 0x0000 0x6 0x0 +#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00F0 0x037C 0x0000 0x8 0x0 +#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00F4 0x0380 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00F4 0x0380 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00F4 0x0380 0x065C 0x1 0x0 +#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00F4 0x0380 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00F4 0x0380 0x0564 0x3 0x0 +#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00F4 0x0380 0x0000 0x4 0x0 +#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00F4 0x0380 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00F4 0x0380 0x0000 0x6 0x0 +#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00F4 0x0380 0x0000 0x8 0x0 +#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00F8 0x0384 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00F8 0x0384 0x065C 0x1 0x1 +#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00F8 0x0384 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00F8 0x0384 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00F8 0x0384 0x056C 0x3 0x0 +#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00F8 0x0384 0x0000 0x4 0x0 +#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00F8 0x0384 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00F8 0x0384 0x0000 0x6 0x0 +#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00F8 0x0384 0x0660 0x8 0x1 +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00FC 0x0388 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00FC 0x0388 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00FC 0x0388 0x0658 0x1 0x0 +#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00FC 0x0388 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00FC 0x0388 0x0568 0x3 0x0 +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00FC 0x0388 0x057C 0x4 0x2 +#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00FC 0x0388 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00FC 0x0388 0x0000 0x6 0x0 +#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00FC 0x0388 0x04BC 0x8 0x1 +#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038C 0x0000 0x0 0x0 +#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038C 0x0658 0x1 0x1 +#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038C 0x0000 0x1 0x0 +#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038C 0x0000 0x2 0x0 +#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038C 0x0570 0x3 0x0 +#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038C 0x0000 0x4 0x0 +#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038C 0x0000 0x5 0x0 +#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038C 0x0000 0x6 0x0 +#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038C 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063C 0x2 0x2 +#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0600 0x3 0x0 +#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063C 0x2 0x3 +#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060C 0x3 0x0 +#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010C 0x0398 0x05DC 0x0 0x0 +#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010C 0x0398 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010C 0x0398 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010C 0x0398 0x0638 0x2 0x2 +#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010C 0x0398 0x0608 0x3 0x0 +#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010C 0x0398 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010C 0x0398 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010C 0x0398 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039C 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039C 0x05DC 0x1 0x1 +#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039C 0x0638 0x2 0x3 +#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039C 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039C 0x0604 0x3 0x0 +#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039C 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039C 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039C 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03A0 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03A0 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03A0 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03A0 0x0000 0x3 0x0 +#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03A0 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03A0 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03A0 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03A4 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03A4 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118 0x03A4 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03A4 0x0000 0x3 0x0 +#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03A4 0x05B8 0x4 0x2 +#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03A4 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03A4 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03A4 0x05E0 0x8 0x1 +#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011C 0x03A8 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03A8 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011C 0x03A8 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011C 0x03A8 0x0000 0x3 0x0 +#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011C 0x03A8 0x05B4 0x4 0x2 +#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011C 0x03A8 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011C 0x03A8 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011C 0x03A8 0x05EC 0x8 0x0 +#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03AC 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03AC 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120 0x03AC 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03AC 0x0000 0x3 0x0 +#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03AC 0x05C0 0x4 0x2 +#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03AC 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03AC 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03AC 0x05E8 0x8 0x0 +#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03B0 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03B0 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124 0x03B0 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03B0 0x0000 0x3 0x0 +#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03B0 0x05BC 0x4 0x2 +#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03B0 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03B0 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03B0 0x05E4 0x8 0x0 +#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03B4 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03B4 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03B4 0x0658 0x1 0x2 +#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128 0x03B4 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03B4 0x0000 0x3 0x0 +#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03B4 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03B4 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03B4 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03B4 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012C 0x03B8 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012C 0x03B8 0x0658 0x1 0x3 +#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012C 0x03B8 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012C 0x03B8 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012C 0x03B8 0x0000 0x3 0x0 +#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012C 0x03B8 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012C 0x03B8 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012C 0x03B8 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012C 0x03B8 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03BC 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03BC 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03BC 0x0650 0x1 0x2 +#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130 0x03BC 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03BC 0x0000 0x3 0x0 +#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03BC 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03BC 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03BC 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03BC 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03C0 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03C0 0x0650 0x1 0x3 +#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03C0 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134 0x03C0 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03C0 0x0000 0x3 0x0 +#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03C0 0x061C 0x4 0x0 +#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03C0 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03C0 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03C0 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03C4 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03C4 0x0618 0x1 0x2 +#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138 0x03C4 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03C4 0x0504 0x3 0x1 +#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03C4 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03C4 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03C4 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03C4 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013C 0x03C8 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013C 0x03C8 0x0600 0x1 0x1 +#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013C 0x03C8 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013C 0x03C8 0x0508 0x3 0x1 +#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013C 0x03C8 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013C 0x03C8 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013C 0x03C8 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013C 0x03C8 0x0584 0x8 0x2 +#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03CC 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03CC 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140 0x03CC 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03CC 0x050C 0x3 0x1 +#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03CC 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03CC 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03CC 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03CC 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03D0 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03D0 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144 0x03D0 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03D0 0x0510 0x3 0x1 +#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03D0 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03D0 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03D0 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03D0 0x0588 0x8 0x2 +#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03D4 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03D4 0x060C 0x1 0x1 +#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148 0x03D4 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03D4 0x0514 0x3 0x1 +#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03D4 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03D4 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03D4 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03D4 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014C 0x03D8 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014C 0x03D8 0x0608 0x1 0x1 +#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014C 0x03D8 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014C 0x03D8 0x0518 0x3 0x1 +#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014C 0x03D8 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014C 0x03D8 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014C 0x03D8 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014C 0x03D8 0x0000 0x8 0x0 +#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03DC 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03DC 0x0604 0x1 0x1 +#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150 0x03DC 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03DC 0x051C 0x3 0x1 +#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03DC 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03DC 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03DC 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03DC 0x068C 0x8 0x0 +#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03E0 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03E0 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154 0x03E0 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03E0 0x0520 0x3 0x1 +#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03E0 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03E0 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03E0 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03E0 0x0690 0x8 0x0 +#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03E4 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03E4 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03E4 0x0654 0x1 0x2 +#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158 0x03E4 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03E4 0x04D4 0x3 0x1 +#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03E4 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03E4 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03E4 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03E4 0x0694 0x8 0x0 +#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015C 0x03E8 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015C 0x03E8 0x0654 0x1 0x3 +#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015C 0x03E8 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015C 0x03E8 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x03E8 0x04D0 0x3 0x1 +#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015C 0x03E8 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015C 0x03E8 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015C 0x03E8 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015C 0x03E8 0x0698 0x8 0x0 +#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03EC 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03EC 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03EC 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03EC 0x04EC 0x3 0x1 +#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03EC 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03EC 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03EC 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03EC 0x0678 0x8 0x1 +#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03F0 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03F0 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03F0 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03F0 0x0670 0x8 0x1 +#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03F0 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03F0 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03F0 0x0000 0x2 0x0 +#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03F0 0x04F0 0x3 0x1 +#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03F4 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03F4 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03F4 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03F4 0x067C 0x8 0x1 +#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03F4 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03F4 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03F4 0x065C 0x1 0x2 +#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03F4 0x0534 0x2 0x0 +#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03F4 0x04F4 0x3 0x1 +#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016C 0x03F8 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016C 0x03F8 0x065C 0x1 0x3 +#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016C 0x03F8 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016C 0x03F8 0x0540 0x2 0x0 +#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016C 0x03F8 0x04F8 0x3 0x1 +#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016C 0x03F8 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016C 0x03F8 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016C 0x03F8 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016C 0x03F8 0x0680 0x8 0x1 +#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03FC 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03FC 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03FC 0x053C 0x2 0x0 +#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03FC 0x04FC 0x3 0x1 +#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03FC 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03FC 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03FC 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03FC 0x0684 0x8 0x0 +#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0x0 0x0 +#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 0x1 0x0 +#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 0x2 0x0 +#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0500 0x3 0x1 +#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 0x4 0x0 +#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 0x5 0x0 +#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 0x6 0x0 +#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 0x8 0x1 +#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 0x1 0x2 +#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x05D0 0x3 0x1 +#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017C 0x0408 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017C 0x0408 0x0678 0x1 0x2 +#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017C 0x0408 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017C 0x0408 0x05C4 0x3 0x1 +#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017C 0x0408 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017C 0x0408 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017C 0x0408 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040C 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040C 0x067C 0x1 0x2 +#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040C 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040C 0x05D4 0x3 0x1 +#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040C 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040C 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040C 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 0x1 0x2 +#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x05C8 0x3 0x1 +#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 0x1 0x1 +#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x05D8 0x3 0x1 +#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018C 0x0418 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018C 0x0418 0x0688 0x1 0x2 +#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018C 0x0418 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018C 0x0418 0x05CC 0x3 0x1 +#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018C 0x0418 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018C 0x0418 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018C 0x0418 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041C 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041C 0x068C 0x1 0x1 +#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041C 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041C 0x0564 0x3 0x1 +#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041C 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041C 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041C 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041C 0x062C 0x8 0x2 +#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 0x1 0x1 +#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056C 0x3 0x1 +#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062C 0x8 0x3 +#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 0x1 0x1 +#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 0x3 0x1 +#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 0x8 0x4 +#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019C 0x0428 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019C 0x0428 0x0698 0x1 0x1 +#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019C 0x0428 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019C 0x0428 0x0570 0x3 0x1 +#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019C 0x0428 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019C 0x0428 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019C 0x0428 0x0628 0x8 0x5 +#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019C 0x0428 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01A0 0x042C 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01A0 0x042C 0x0000 0x1 0x0 +#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01A0 0x042C 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01A0 0x042C 0x0000 0x3 0x0 +#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01A0 0x042C 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01A0 0x042C 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01A0 0x042C 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01A4 0x0430 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01A4 0x0430 0x0000 0x1 0x0 +#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01A4 0x0430 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01A4 0x0430 0x0000 0x3 0x0 +#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01A4 0x0430 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01A4 0x0430 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01A4 0x0430 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01A8 0x0434 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01A8 0x0434 0x0000 0x1 0x0 +#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01A8 0x0434 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01A8 0x0434 0x0560 0x3 0x1 +#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01A8 0x0434 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01A8 0x0434 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01A8 0x0434 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01A8 0x0434 0x0634 0x8 0x2 +#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01AC 0x0438 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01AC 0x0438 0x0000 0x1 0x0 +#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01AC 0x0438 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01AC 0x0438 0x0554 0x3 0x1 +#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01AC 0x0438 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01AC 0x0438 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01AC 0x0438 0x0634 0x8 0x3 +#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01AC 0x0438 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01B0 0x043C 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01B0 0x043C 0x0000 0x1 0x0 +#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01B0 0x043C 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01B0 0x043C 0x055C 0x3 0x1 +#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01B0 0x043C 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01B0 0x043C 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01B0 0x043C 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01B0 0x043C 0x0630 0x8 0x2 +#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01B4 0x0440 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01B4 0x0440 0x0000 0x1 0x0 +#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01B4 0x0440 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01B4 0x0440 0x0558 0x3 0x1 +#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01B4 0x0440 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01B4 0x0440 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01B4 0x0440 0x0630 0x8 0x3 +#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01B4 0x0440 0x0000 0x8 0x0 +#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01B8 0x0444 0x0000 0x0 0x0 +#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01B8 0x0444 0x0530 0x1 0x1 +#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01B8 0x0444 0x0000 0x2 0x0 +#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01B8 0x0444 0x0000 0x3 0x0 +#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01B8 0x0444 0x0000 0x4 0x0 +#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01B8 0x0444 0x0000 0x5 0x0 +#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01B8 0x0444 0x0614 0x6 0x1 +#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01B8 0x0444 0x061C 0x8 0x1 +#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01BC 0x0448 0x0000 0x0 0x0 +#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01BC 0x0448 0x0000 0x1 0x0 +#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01BC 0x0448 0x0000 0x2 0x0 +#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01BC 0x0448 0x0000 0x3 0x0 +#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01BC 0x0448 0x0000 0x4 0x0 +#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01BC 0x0448 0x0000 0x5 0x0 +#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01BC 0x0448 0x0610 0x6 0x2 +#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01BC 0x0448 0x0000 0x8 0x0 +#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01C0 0x044C 0x0000 0x0 0x0 +#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01C0 0x044C 0x0000 0x1 0x0 +#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01C0 0x044C 0x05F0 0x2 0x1 +#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01C0 0x044C 0x0618 0x3 0x3 +#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01C0 0x044C 0x0000 0x4 0x0 +#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01C0 0x044C 0x0000 0x5 0x0 +#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01C0 0x044C 0x0664 0x8 0x2 +#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01C4 0x0450 0x0000 0x0 0x0 +#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01C4 0x0450 0x0000 0x1 0x0 +#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01C4 0x0450 0x05FC 0x2 0x1 +#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01C4 0x0450 0x0000 0x3 0x0 +#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01C4 0x0450 0x0000 0x4 0x0 +#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01C4 0x0450 0x0000 0x5 0x0 +#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01C4 0x0450 0x04B8 0x8 0x2 +#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01C8 0x0454 0x0000 0x0 0x0 +#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01C8 0x0454 0x05A0 0x1 0x1 +#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01C8 0x0454 0x05F8 0x2 0x1 +#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01C8 0x0454 0x0584 0x3 0x3 +#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01C8 0x0454 0x0000 0x4 0x0 +#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01C8 0x0454 0x0000 0x5 0x0 +#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01C8 0x0454 0x0000 0x8 0x0 +#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01CC 0x0458 0x0000 0x0 0x0 +#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01CC 0x0458 0x0598 0x1 0x1 +#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01CC 0x0458 0x05F4 0x2 0x1 +#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01CC 0x0458 0x0000 0x3 0x0 +#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01CC 0x0458 0x0000 0x4 0x0 +#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01CC 0x0458 0x0000 0x5 0x0 +#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01CC 0x0458 0x0000 0x6 0x0 +#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01CC 0x0458 0x0660 0x8 0x2 +#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01D0 0x045C 0x0000 0x0 0x0 +#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01D0 0x045C 0x059C 0x1 0x1 +#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01D0 0x045C 0x0000 0x2 0x0 +#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01D0 0x045C 0x0588 0x3 0x3 +#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01D0 0x045C 0x0000 0x4 0x0 +#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01D0 0x045C 0x0000 0x5 0x0 +#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01D0 0x045C 0x0000 0x6 0x0 +#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01D0 0x045C 0x04BC 0x8 0x2 +#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01D4 0x0460 0x0000 0x0 0x0 +#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01D4 0x0460 0x0674 0x1 0x0 +#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01D4 0x0460 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01D4 0x0460 0x05A8 0x3 0x0 +#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01D4 0x0460 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01D4 0x0460 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01D4 0x0460 0x0000 0x6 0x0 +#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01D4 0x0460 0x0000 0x8 0x0 +#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01D4 0x0460 0x064C 0x8 0x0 +#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01D8 0x0464 0x0528 0x0 0x1 +#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01D8 0x0464 0x069C 0x1 0x2 +#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01D8 0x0464 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01D8 0x0464 0x05A4 0x3 0x2 +#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01D8 0x0464 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01D8 0x0464 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01D8 0x0464 0x0000 0x6 0x0 +#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01D8 0x0464 0x064C 0x8 0x3 +#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01D8 0x0464 0x0000 0x8 0x0 +#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01DC 0x0468 0x052C 0x0 0x0 +#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01DC 0x0468 0x0670 0x1 0x0 +#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01DC 0x0468 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01DC 0x0468 0x05B0 0x3 0x0 +#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01DC 0x0468 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01DC 0x0468 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01DC 0x0468 0x0000 0x6 0x0 +#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01DC 0x0468 0x0648 0x8 0x0 +#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01DC 0x0468 0x0000 0x8 0x0 +#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01E0 0x046C 0x0524 0x0 0x0 +#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01E0 0x046C 0x0678 0x1 0x0 +#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01E0 0x046C 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01E0 0x046C 0x05AC 0x3 0x0 +#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01E0 0x046C 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01E0 0x046C 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01E0 0x046C 0x0000 0x6 0x0 +#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01E0 0x046C 0x0000 0x8 0x0 +#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01E0 0x046C 0x0648 0x8 0x1 +#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01E4 0x0470 0x04C4 0x0 0x0 +#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01E4 0x0470 0x067C 0x1 0x0 +#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01E4 0x0470 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01E4 0x0470 0x0544 0x3 0x0 +#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01E4 0x0470 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01E4 0x0470 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01E4 0x0470 0x0000 0x6 0x0 +#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01E4 0x0470 0x0000 0x8 0x0 +#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01E4 0x0470 0x0644 0x8 0x0 +#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01E8 0x0474 0x04C8 0x0 0x0 +#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01E8 0x0474 0x0680 0x1 0x0 +#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01E8 0x0474 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01E8 0x0474 0x0550 0x3 0x0 +#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01E8 0x0474 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01E8 0x0474 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01E8 0x0474 0x05E0 0x6 0x0 +#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01E8 0x0474 0x0644 0x8 0x1 +#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01E8 0x0474 0x0000 0x8 0x0 +#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01EC 0x0478 0x04D8 0x0 0x1 +#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01EC 0x0478 0x0684 0x1 0x2 +#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01EC 0x0478 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01EC 0x0478 0x054C 0x3 0x1 +#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01EC 0x0478 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01EC 0x0478 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01EC 0x0478 0x0000 0x6 0x0 +#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x5 +#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01EC 0x0478 0x0000 0x8 0x0 +#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01F0 0x047C 0x04CC 0x0 0x0 +#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01F0 0x047C 0x0688 0x1 0x0 +#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01F0 0x047C 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01F0 0x047C 0x0548 0x3 0x0 +#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01F0 0x047C 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01F0 0x047C 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01F0 0x047C 0x0000 0x6 0x0 +#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01F0 0x047C 0x0000 0x8 0x0 +#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01F0 0x047C 0x0640 0x8 0x0 +#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01F4 0x0480 0x04DC 0x0 0x1 +#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01F4 0x0480 0x068C 0x1 0x2 +#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01F4 0x0480 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01F4 0x0480 0x0534 0x3 0x1 +#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01F4 0x0480 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01F4 0x0480 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01F4 0x0480 0x05EC 0x6 0x1 +#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01F4 0x0480 0x066C 0x8 0x2 +#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01F8 0x0484 0x04E0 0x0 0x1 +#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01F8 0x0484 0x0690 0x1 0x2 +#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01F8 0x0484 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01F8 0x0484 0x0540 0x3 0x1 +#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01F8 0x0484 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01F8 0x0484 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01F8 0x0484 0x05E8 0x6 0x1 +#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01F8 0x0484 0x0668 0x8 0x2 +#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01FC 0x0488 0x04E4 0x0 0x1 +#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01FC 0x0488 0x0694 0x1 0x2 +#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01FC 0x0488 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01FC 0x0488 0x053C 0x3 0x1 +#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01FC 0x0488 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01FC 0x0488 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01FC 0x0488 0x05E4 0x6 0x1 +#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01FC 0x0488 0x0000 0x8 0x0 +#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048C 0x04E8 0x0 0x1 +#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048C 0x0698 0x1 0x2 +#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048C 0x0000 0x2 0x0 +#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048C 0x0538 0x3 0x1 +#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048C 0x0000 0x4 0x0 +#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048C 0x0000 0x5 0x0 +#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048C 0x0000 0x6 0x0 +#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048C 0x0000 0x8 0x0 #endif /* __DTS_IMX6UL_PINFUNC_H */ diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi index 7affab866fc..fb4d0dc76c1 100644 --- a/arch/arm/dts/imx6ul.dtsi +++ b/arch/arm/dts/imx6ul.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -26,8 +26,6 @@ i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -39,14 +37,15 @@ sai1 = &sai1; sai2 = &sai2; sai3 = &sai3; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usbotg0 = &usbotg1; - usbotg1 = &usbotg2; + spi0 = &qspi; + spi1 = &ecspi1; + spi2 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + usb0 = &usbotg1; + usb1 = &usbotg2; }; cpus { @@ -60,12 +59,14 @@ clock-latency = <61036>; /* two CLK32 periods */ operating-points = < /* kHz uV */ + 696000 1275000 528000 1175000 396000 1025000 198000 950000 >; fsl,soc-operating-points = < /* KHz uV */ + 696000 1275000 528000 1175000 396000 1175000 198000 1175000 @@ -134,7 +135,24 @@ compatible = "simple-bus"; interrupt-parent = <&gpc>; ranges; - u-boot,dm-spl; + + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>, + <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>, + <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>, + <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>, + <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>, + <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc"; + fsl,max_ddr_freq = <400000000>; + }; pmu { compatible = "arm,cortex-a7-pmu"; @@ -142,9 +160,19 @@ status = "disabled"; }; - ocram: sram@00900000 { + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + }; + + ocram: sram@00905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x00905000 0x1B000>; }; dma_apbh: dma-apbh@01804000 { @@ -160,6 +188,21 @@ clocks = <&clks IMX6UL_CLK_APBHDMA>; }; + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; + reg = <0x00100000 0x3fff>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + gpmi: gpmi-nand@01806000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; @@ -186,7 +229,6 @@ #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - u-boot,dm-spl; spba-bus@02000000 { compatible = "fsl,spba-bus", "simple-bus"; @@ -195,6 +237,28 @@ reg = <0x02000000 0x40000>; ranges; + spdif: spdif@02004000 { + compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = ; + dmas = <&sdma 41 18 0>, + <&sdma 42 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>, + <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_SPDIF>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_IPG>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + status = "disabled"; + }; + ecspi1: ecspi@02008000 { #address-cells = <1>; #size-cells = <0>; @@ -204,6 +268,8 @@ clocks = <&clks IMX6UL_CLK_ECSPI1>, <&clks IMX6UL_CLK_ECSPI1>; clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -216,6 +282,8 @@ clocks = <&clks IMX6UL_CLK_ECSPI2>, <&clks IMX6UL_CLK_ECSPI2>; clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -228,6 +296,8 @@ clocks = <&clks IMX6UL_CLK_ECSPI3>, <&clks IMX6UL_CLK_ECSPI3>; clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -240,23 +310,27 @@ clocks = <&clks IMX6UL_CLK_ECSPI4>, <&clks IMX6UL_CLK_ECSPI4>; clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; uart7: serial@02018000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02018000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART7_IPG>, <&clks IMX6UL_CLK_UART7_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 43 4 0>, <&sdma 44 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; uart1: serial@02020000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART1_IPG>, @@ -267,12 +341,14 @@ uart8: serial@02024000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02024000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART8_IPG>, <&clks IMX6UL_CLK_UART8_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 45 4 0>, <&sdma 46 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -282,9 +358,10 @@ reg = <0x02028000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_SAI1_IPG>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_SAI1>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma 35 24 0>, <&sdma 36 24 0>; dma-names = "rx", "tx"; @@ -297,9 +374,11 @@ reg = <0x0202c000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_SAI2_IPG>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_SAI2>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma 37 24 0>, <&sdma 38 24 0>; dma-names = "rx", "tx"; @@ -312,14 +391,40 @@ reg = <0x02030000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_SAI3_IPG>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_SAI3>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma 39 24 0>, <&sdma 40 24 0>; dma-names = "rx", "tx"; status = "disabled"; }; + + asrc: asrc@02034000 { + compatible = "fsl,imx53-asrc"; + reg = <0x02034000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ASRC_IPG>, + <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + status = "okay"; + }; }; tsc: tsc@02040000 { @@ -333,6 +438,13 @@ status = "disabled"; }; + bee: bee@02044000 { + compatible = "fsl,imx6ul-bee"; + reg = <0x02044000 0x4000>; + interrupts = ; + status = "disabled"; + }; + pwm1: pwm@02080000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; @@ -384,6 +496,7 @@ clocks = <&clks IMX6UL_CLK_CAN1_IPG>, <&clks IMX6UL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; @@ -394,6 +507,7 @@ clocks = <&clks IMX6UL_CLK_CAN2_IPG>, <&clks IMX6UL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; @@ -402,8 +516,8 @@ reg = <0x02098000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_GPT1_BUS>, - <&clks IMX6UL_CLK_GPT1_SERIAL>; - clock-names = "ipg", "per"; + <&clks IMX6UL_CLK_GPT_3M>; + clock-names = "ipg", "osc_per"; }; gpio1: gpio@0209c000 { @@ -417,7 +531,6 @@ #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, <&iomuxc 16 33 16>; - u-boot,dm-spl; }; gpio2: gpio@020a0000 { @@ -454,7 +567,6 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; - u-boot,dm-spl; }; gpio5: gpio@020ac000 { @@ -469,6 +581,12 @@ gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; }; + snvslp: snvs@020b0000 { + compatible = "fsl,imx6ul-snvs"; + reg = <0x020b0000 0x4000>; + interrupts = ; + }; + fec2: ethernet@020b4000 { compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x020b4000 0x4000>; @@ -481,8 +599,11 @@ <&clks IMX6UL_CLK_ENET2_REF_125M>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + stop-mode = <&gpr 0x10 4>; fsl,num-tx-queues=<1>; fsl,num-rx-queues=<1>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; status = "disabled"; }; @@ -594,6 +715,19 @@ fsl,anatop = <&anatop>; }; + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupts = ; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + }; + + caam_snvs: caam-snvs@020cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x020cc000 0x4000>; + }; + snvs: snvs@020cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -610,7 +744,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; status = "disabled"; }; @@ -648,12 +782,12 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; }; iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6ul-iomuxc"; reg = <0x020e0000 0x4000>; - u-boot,dm-spl; }; gpr: iomuxc-gpr@020e4000 { @@ -671,6 +805,13 @@ clock-names = "ipg", "per"; }; + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + + sdma: sdma@020ec000 { compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", "fsl,imx35-sdma"; @@ -680,6 +821,7 @@ <&clks IMX6UL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; + iram = <&ocram>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; @@ -734,7 +876,44 @@ #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; - u-boot,dm-spl; + + crypto: caam@2140000 { + compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2140000 0x3c000>; + ranges = <0 0x2140000 0x3c000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, + <&clks IMX6UL_CLK_CAAM_MEM>; + clock-names = "ipg", "aclk", "mem"; + + sec_ctrl: ctrl@0 { + /* CAAM Page 0 only accessible */ + /* by secure world */ + compatible = "fsl,sec-v4.0-ctrl"; + reg = <0x2140000 0x1000>; + secure-status = "okay"; + status = "disabled"; + }; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + sec_jr2: jr2@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; usbotg1: usb@02184000 { compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; @@ -781,8 +960,18 @@ <&clks IMX6UL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + stop-mode = <&gpr 0x10 3>; fsl,num-tx-queues=<1>; fsl,num-rx-queues=<1>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; + status = "disabled"; + }; + + sim1: sim@0218c000 { + compatible = "fsl,imx6ul-sim"; + reg = <0x0218c000 0x4000>; + interrupts = ; status = "disabled"; }; @@ -852,11 +1041,56 @@ status = "disabled"; }; + romcp@021ac000 { + compatible = "fsl,imx6ul-romcp", "syscon"; + reg = <0x021ac000 0x4000>; + }; + mmdc: mmdc@021b0000 { compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; + sim2: sim@021b4000 { + compatible = "fsl,imx6ul-sim"; + reg = <0x021b4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SIM2>; + clock-names = "sim"; + status = "disabled"; + }; + + weim: weim@021b8000 { + compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; + + ocotp: ocotp-ctrl@021bc000 { + compatible = "fsl,imx6ul-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6UL_CLK_OCOTP>; + }; + + csu: csu@021c0000 { + compatible = "fsl,imx6ul-csu"; + reg = <0x021c0000 0x4000>; + interrupts = ; + status = "disabled"; + }; + + csi: csi@021c4000 { + compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi"; + reg = <0x021c4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_CSI>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + lcdif: lcdif@021c8000 { compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; reg = <0x021c8000 0x4000>; @@ -881,47 +1115,65 @@ status = "disabled"; }; + pxp: pxp@021cc000 { + compatible = "fsl,imx6ul-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; + reg = <0x021cc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PXP>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; + }; + uart2: serial@021e8000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART2_IPG>, <&clks IMX6UL_CLK_UART2_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; uart3: serial@021ec000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART3_IPG>, <&clks IMX6UL_CLK_UART3_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; uart4: serial@021f0000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART4_IPG>, <&clks IMX6UL_CLK_UART4_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; uart5: serial@021f4000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART5_IPG>, <&clks IMX6UL_CLK_UART5_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -937,12 +1189,14 @@ uart6: serial@021fc000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021fc000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART6_IPG>, <&clks IMX6UL_CLK_UART6_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; }; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-arm2-emmc.dts b/arch/arm/dts/imx6ull-14x14-ddr3-arm2-emmc.dts new file mode 100644 index 00000000000..934e6f6b850 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-arm2-emmc.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <>; + wp-gpios = <>; + vmmc-supply = <>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-arm2-epdc.dts b/arch/arm/dts/imx6ull-14x14-ddr3-arm2-epdc.dts new file mode 100644 index 00000000000..c476f442efd --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-arm2-epdc.dts @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +&epdc { + status = "okay"; +}; + +&fec2 { + status = "disabled"; +}; + +&lcdif { + status = "disabled"; +}; + +&max17135 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-arm2-gpmi-weim.dts b/arch/arm/dts/imx6ull-14x14-ddr3-arm2-gpmi-weim.dts new file mode 100644 index 00000000000..327677aafa7 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-arm2-gpmi-weim.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +&gpmi { + status ="okay"; +}; + +&qspi { + status ="disabled"; +}; + +&usdhc2{ + status ="disabled"; +}; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-arm2-lcdif.dts b/arch/arm/dts/imx6ull-14x14-ddr3-arm2-lcdif.dts new file mode 100644 index 00000000000..40e86a4e08c --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-arm2-lcdif.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* DTS file for LCDIF at imx6ull ddr3 arm2 board */ + +#include "imx6ull-14x14-ddr3-arm2.dts" + +/ { + backlight { + status = "okay"; + }; +}; + +&fec1 { + status = "disabled"; +}; + +&lcdif { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-arm2-tsc.dts b/arch/arm/dts/imx6ull-14x14-ddr3-arm2-tsc.dts new file mode 100644 index 00000000000..8893e39b0ac --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-arm2-tsc.dts @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-arm2-lcdif.dts" + +&csi { + status = "disabled"; +}; + +&i2c1 { + status = "disabled"; +}; + +®_usb_otg1_vbus { + pinctrl-0 = < >; + gpio = < >; +}; + +&ov5640 { + status = "disabled"; +}; + +&usbotg1 { + status = "disabled"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + status = "okay"; + xnur-gpio = <&gpio1 3 0>; + measure_delay_time = <0xfff>; + pre_charge_time = <0xffff>; +}; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-arm2.dts b/arch/arm/dts/imx6ull-14x14-ddr3-arm2.dts new file mode 100644 index 00000000000..3194cb2cde6 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-arm2.dts @@ -0,0 +1,1040 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ull.dtsi" + +/ { + model = "Freescale i.MX6 ULL DDR3 ARM2 Board"; + compatible = "fsl,imx6ull-ddr3-arm2", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "disabled"; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&clks { + /* For bringup, comments this. + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; + */ +}; + +&cpu0 { + /* + * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1a_reg>; + fsl,arm-soc-shared = <1>; +}; + +&csi { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "disabled"; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,n25q032"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "mii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio5 8 1>; + rst-gpios = <&gpio5 7 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "disabled"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio3 16 0>; + gpio_pmic_vcom_ctrl = <&gpio3 24 0>; + gpio_pmic_wakeup = <&gpio3 14 0>; + gpio_pmic_v3p3 = <&gpio3 17 0>; + gpio_pmic_intr = <&gpio3 13 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* 2's-compliment, -4325000 */ + regulator-min-microvolt = <0xffbe0178>; + /* 2's-compliment, -500000 */ + regulator-max-microvolt = <0xfff85ee0>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&iomuxc { + imx6ul-ddr3-arm2 { + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b098 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 + MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0a0 + MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0a0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0 + MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x10b1 + MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x10b1 + MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x10b1 + MX6UL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x10b1 + MX6UL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x10b1 + MX6UL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x10b1 + MX6UL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x10b1 + MX6UL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x10b1 + MX6UL_PAD_LCD_CLK__EPDC_SDCLK 0x10b1 + MX6UL_PAD_LCD_ENABLE__EPDC_SDLE 0x10b1 + MX6UL_PAD_LCD_HSYNC__EPDC_SDOE 0x10b1 + MX6UL_PAD_LCD_VSYNC__EPDC_SDCE0 0x10b1 + MX6UL_PAD_LCD_DATA00__EPDC_SDDO00 0x10b1 + MX6UL_PAD_LCD_DATA01__EPDC_SDDO01 0x10b1 + MX6UL_PAD_LCD_DATA02__EPDC_SDDO02 0x10b1 + MX6UL_PAD_LCD_DATA03__EPDC_SDDO03 0x10b1 + MX6UL_PAD_LCD_DATA04__EPDC_SDDO04 0x10b1 + MX6UL_PAD_LCD_DATA05__EPDC_SDDO05 0x10b1 + MX6UL_PAD_LCD_DATA06__EPDC_SDDO06 0x10b1 + MX6UL_PAD_LCD_DATA07__EPDC_SDDO07 0x10b1 + MX6UL_PAD_LCD_DATA14__EPDC_SDSHR 0x10b1 + MX6UL_PAD_LCD_DATA15__EPDC_GDRL 0x10b1 + MX6UL_PAD_LCD_DATA16__EPDC_GDCLK 0x10b1 + MX6UL_PAD_LCD_DATA17__EPDC_GDSP 0x10b1 + MX6UL_PAD_LCD_RESET__EPDC_GDOE 0x10b1 + >; + }; + + pinctrl_esai: esaigrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x1b0b0 + MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x1b0b0 + MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x1b0b0 + MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x1b0b0 + MX6UL_PAD_CSI_DATA07__ESAI_T0 0x1b0b0 + MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x1b0b0 + MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x1b0b0 + MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x1b0b0 + MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x1b0b0 + MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x1b0b0 + MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x1b0b0 + MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x1b8b1 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4_gpio: i2c4grp_gpio { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x1b8b0 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x1b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x80000000 /* pwrgood */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x80000000 /* vcom_ctrl */ + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x80000000 /* wakeup */ + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x80000000 /* v3p3 */ + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x80000000 /* pwr int */ + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088 + MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 +#ifdef REWORKED_ENABLE_ALL_QSPI + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 +#endif + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0 + MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0 + MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0 + MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x110b0 + MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0 + MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1_8bit_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc1_cd_wp: usdhc1_cd_wp_grp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */ + >; + }; + + pinctrl_usdhc1_rst: usdhc1_rst_grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_usdhc1_vselect: usdhc1_vselect_grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100a9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170a9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170a9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170a9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170a9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_rst: usdhc2_rst_grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x30b0 + >; + }; + }; +}; + +&iomuxc_snvs { + imx6ul-ddr3-arm2 { + pinctrl_bt: btgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 + >; + }; + + pinctrl_sai2_hp_det_b: sai2_hp_det_grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "disabled"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; +#ifdef REWORKED_ENABLE_ALL_QSPI + fsl,qspi-has-second-chip = <1>; +#endif + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + +#ifdef REWORKED_ENABLE_ALL_QSPI + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +#endif +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 + &pinctrl_bt>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "disabled"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_rst>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_rst>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_rst>; + non-removable; + no-1-8-v; /* VSELECT not connected by default */ + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/arch/arm/dts/imx6ull-14x14-evk-emmc.dts b/arch/arm/dts/imx6ull-14x14-evk-emmc.dts new file mode 100644 index 00000000000..4ea3d91e2cb --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-evk-emmc.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-14x14-evk-gpmi-weim.dts b/arch/arm/dts/imx6ull-14x14-evk-gpmi-weim.dts new file mode 100644 index 00000000000..924696ee6d7 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-evk-gpmi-weim.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&iomuxc { + imx6ull-evk-gpmi-rework { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts index 8a1b67d6bbf..d2477b079ac 100644 --- a/arch/arm/dts/imx6ull-14x14-evk.dts +++ b/arch/arm/dts/imx6ull-14x14-evk.dts @@ -22,6 +22,19 @@ reg = <0x80000000 0x20000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; @@ -30,6 +43,11 @@ status = "okay"; }; + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -66,10 +84,48 @@ }; }; + sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <3 0>; + hp-det-gpios = <&gpio5 4 0>; + mic-det-gpios = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + spi5 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; status = "okay"; gpio-sck = <&gpio5 11 0>; gpio-mosi = <&gpio5 10 0>; @@ -81,7 +137,6 @@ gpio_spi: gpio_spi@0 { compatible = "fairchild,74hc595"; gpio-controller; - oe-gpios = <&gpio5 8 0>; #gpio-cells = <2>; reg = <0>; registers-number = <1>; @@ -102,6 +157,16 @@ assigned-clock-rates = <786432000>; }; +&csi { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -133,6 +198,20 @@ }; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + &gpc { fsl,cpu_pupscr_sw2iso = <0x1>; fsl,cpu_pupscr_sw = <0x0>; @@ -143,8 +222,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; status = "okay"; mag3110@0e { @@ -164,9 +246,40 @@ &i2c2 { clock_frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; }; &iomuxc { @@ -247,6 +360,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 @@ -254,6 +374,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 + >; + }; + pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 @@ -309,6 +436,25 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 @@ -334,6 +480,12 @@ >; }; + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 @@ -345,6 +497,28 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 @@ -356,6 +530,51 @@ >; }; + pinctrl_usdhc2_8bit: usdhc2grp_8bit { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 @@ -379,7 +598,7 @@ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 >; }; - + pinctrl_lcdif_reset: lcdifresetgrp { fsl,pins = < /* used for lcd reset */ @@ -445,6 +664,10 @@ status = "okay"; }; +&pxp { + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; @@ -454,7 +677,6 @@ flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; - /* compatible = "micron,n25q256a"; */ compatible = "spi-flash"; spi-max-frequency = <29000000>; spi-nor,ddr-quad-read-dummy = <6>; @@ -462,6 +684,28 @@ }; }; +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2 + &pinctrl_sai2_hp_det_b>; + + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -479,6 +723,8 @@ }; &usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; dr_mode = "otg"; srp-disable; hnp-disable; @@ -501,8 +747,10 @@ }; &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; keep-power-in-suspend; enable-sdio-wakeup; @@ -513,10 +761,7 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; non-removable; - keep-power-in-suspend; - enable-sdio-wakeup; status = "okay"; }; diff --git a/arch/arm/dts/imx6ull-9x9-evk.dts b/arch/arm/dts/imx6ull-9x9-evk.dts new file mode 100644 index 00000000000..10978e437f4 --- /dev/null +++ b/arch/arm/dts/imx6ull-9x9-evk.dts @@ -0,0 +1,832 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6ull.dtsi" + +/ { + model = "Freescale i.MX6 ULL 9x9 EVK Board"; + compatible = "fsl,imx6ull-9x9-evk", "fsl,imx6ull"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x6000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai2>; + audio-codec = <&codec>; + asrc-controller = <&asrc>; + codec-master; + gpr = <&gpr 4 0x100000 0x100000>; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <3 0>; + hp-det-gpios = <&gpio5 4 0>; + mic-det-gpios = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + arm-supply = <&sw1c_reg>; + soc-supply = <&sw1c_reg>; + fsl,arm-soc-shared = <1>; +}; + +&csi { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,wdog-reset = <1>; /* watchdog select of reset source */ + fsl,ldo-bypass = <1>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default_snvs"; + pinctrl-0 = <&pinctrl_hog_2>; + imx6ull-evk { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_lcdif_reset: lcdifresetgrp { + fsl,pins = < + /* used for lcd reset */ + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_sai2_hp_det_b: sai2_hp_det_grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl + &pinctrl_lcdif_reset>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2 + &pinctrl_sai2_hp_det_b>; + + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure_delay_time = <0xffff>; + pre_charge_time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 28b8422f318..d46366983ce 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -29,8 +29,6 @@ i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -46,6 +44,8 @@ spi4 = &ecspi4; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + usb0 = &usbotg1; + usb1 = &usbotg2; }; cpus { diff --git a/arch/arm/dts/imx6ulz-14x14-evk-emmc.dts b/arch/arm/dts/imx6ulz-14x14-evk-emmc.dts new file mode 100644 index 00000000000..2c6c5ccaf52 --- /dev/null +++ b/arch/arm/dts/imx6ulz-14x14-evk-emmc.dts @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2018 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ulz-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ulz-14x14-evk-gpmi-weim.dts b/arch/arm/dts/imx6ulz-14x14-evk-gpmi-weim.dts new file mode 100644 index 00000000000..35f916ae227 --- /dev/null +++ b/arch/arm/dts/imx6ulz-14x14-evk-gpmi-weim.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2018 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ulz-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&iomuxc { + imx6ulz-evk-gpmi-rework { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6ulz-14x14-evk.dts b/arch/arm/dts/imx6ulz-14x14-evk.dts new file mode 100644 index 00000000000..42bf5352c60 --- /dev/null +++ b/arch/arm/dts/imx6ulz-14x14-evk.dts @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-evk.dts" + +/ { + model = "Freescale i.MX6 ULZ 14x14 EVK Board"; + compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull"; + + backlight { + status = "disabled"; + }; + + pxp_v4l2 { + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts index f6c21052ae8..69c775971e2 100644 --- a/arch/arm/dts/imx7-colibri.dts +++ b/arch/arm/dts/imx7-colibri.dts @@ -83,15 +83,15 @@ &iomuxc_lpsr { pinctrl_i2c1: i2c1-grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f - MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f + MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f >; }; pinctrl_i2c1_gpio: i2c1-gpio-grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f >; }; }; diff --git a/arch/arm/dts/imx7d-12x12-ddr3-arm2.dts b/arch/arm/dts/imx7d-12x12-ddr3-arm2.dts new file mode 100644 index 00000000000..725dd169645 --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-ddr3-arm2.dts @@ -0,0 +1,578 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7 DDR3 12x12 ARM2 Board"; + compatible = "fsl,imx7d-12x12-ddr3-arm2", "fsl,imx7d"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd3_vmmc: sd3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio6 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_can1_3v3: can1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + }; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <4>; + cs-gpios = <&gpio5 3 0>, <&gpio5 4 0>, <&gpio5 5 0>, <&gpio5 6 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "disabled"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&epxp { + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-12x12-ddr3-arm2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + >; + }; + + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX7D_PAD_SD1_CLK__GPIO5_IO3 0x2 + MX7D_PAD_SD1_CMD__GPIO5_IO4 0x2 + MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x2 + MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x2 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x2 + MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x2 + MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x2 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x59 + MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x59 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x59 + MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x59 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x32 + MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x32 + >; + }; + + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f + MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x7f + MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x7f + >; + }; + + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x4001b0b0 + MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x4001b0b0 + MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x4001b0b0 + MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x4001b0b0 + MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x4001b0b0 + MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x4001b0b0 + MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x4001b0b0 + MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x4001b0b0 + MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x4001b0b0 + MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x4001b0b0 + MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x4001b0b0 + MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x4001b0b0 + MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x4001b0b0 + MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x4001b0b0 + MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x4001b0b0 + MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x4001b0b0 + MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x4001b0b0 + MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x4001b0b0 + MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x4001b0b0 + MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x4001b0b0 + MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x4001b0b0 + MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x4001b0b0 + MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x4001b0b0 + MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x4001b0b0 + MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x4001b0b0 + MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x4001b0b0 + MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x4001b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x59 + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x59 + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x59 + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x59 + >; + }; + + pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x5a + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x5a + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x5a + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x5a + >; + }; + + pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x5b + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x5b + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x5b + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x5b + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + >; + }; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-12x12-ddr3-arm2 { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x59 /* flexcan stby1 */ + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x59 /* flexcan stby2 */ + MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x80000000 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x7f + MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x7f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x4000007f + MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x4000007f + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&sdma { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC2_ROOT_CLK>; + assigned-clocks-rates = <400000000>; + bus-width = <8>; + tuning-step = <2>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + vmmc-supply = <®_sd3_vmmc>; + cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + no-1-8-v; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts b/arch/arm/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts new file mode 100644 index 00000000000..16dd447a141 --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +&epdc { + status = "disabled"; +}; + +&ecspi1{ + status = "okay"; +}; + +/* + * pin conflict with ecspi1 + * default hog setting conflicts with ECSPI1 MOSI and MISO + * EPDC PWRCTRL conflicts with ECSPI1 CS pin + */ +&iomuxc { + pinctrl-0 = <&pinctrl_hog_1>; + pinctrl-1 = <&pinctrl_hog_1>; +}; diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts b/arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts new file mode 100644 index 00000000000..c26556d059b --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51 + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51 + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51 + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51 + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51 + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51 + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51 + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51 + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_qspi1_1>; + pinctrl-1 = <&pinctrl_qspi1_1>; + status = "okay"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-arm2.dts b/arch/arm/dts/imx7d-12x12-lpddr3-arm2.dts new file mode 100644 index 00000000000..e74707bd57d --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-lpddr3-arm2.dts @@ -0,0 +1,1037 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7 LPDDR3 12x12 ARM2 Board"; + compatible = "fsl,imx7d-12x12-lpddr3-arm2", "fsl,imx7d"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_gpio_keys>; + pinctrl-1 = <&pinctrl_gpio_keys_sleep>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_aud_1v8: aud_1v8 { + compatible = "regulator-fixed"; + regulator-name = "AUD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_3v3: can1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + reg_coedc_5v: coedc_5v { + compatible = "regulator-fixed"; + regulator-name = "CODEC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&epdc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_epdc_0>; + pinctrl-1 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&epxp { + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 19 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + pinctrl-1 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "disabled"; + + spi_flash1: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-1 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-1 = <&pinctrl_enet2>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-1 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + pinctrl-2 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + fsl,lpsr-mode; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1>; + pinctrl-2 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 31 0>; + gpio_pmic_vcom_ctrl = <&gpio4 14 0>; + gpio_pmic_wakeup = <&gpio4 23 0>; + gpio_pmic_v3p3 = <&gpio4 20 0>; + gpio_pmic_intr = <&gpio4 18 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* 2's-compliment, -4325000 */ + regulator-min-microvolt = <0xffbe0178>; + /* 2's-compliment, -500000 */ + regulator-max-microvolt = <0xfff85ee0>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; + + codec: wm8958@1a { + compatible = "wlf,wm8958"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "mclk1", "mclk2"; + + DBVDD1-supply = <®_aud_1v8>; + DBVDD2-supply = <®_aud_1v8>; + DBVDD3-supply = <®_aud_1v8>; + AVDD2-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_coedc_5v>; + SPKVDD2-supply = <®_coedc_5v>; + wlf,ldo1ena; + wlf,ldo2ena; + }; +}; + +&iomuxc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + + imx7d-12x12-lpddr3-arm2 { + + pinctrl_bt: btgrp-1 { + fsl,pins = < + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* BT REG on */ + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x2 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x2 + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x2 + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x2 + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x80000000 /* pwr int */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59 + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59 + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x59 /* STBY */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59 + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59 + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x59 /* STBY */ + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_gpio_keys_sleep: gpio_keysgrp_sleep { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x80000000 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x80000000 + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x80000000 + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x80000000 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_hog_mipi: hoggrp_mipi { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x59 + >; + }; + + pinctrl_hog_sd2_vselect: hoggrp_sd2vselect { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x59 + >; + }; + + pinctrl_hog_headphone_det: hoggrp_headphone_det { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f + >; + }; + + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0 + MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x2 + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x2 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x1f + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + pinctrl_sim1_1: sim1grp-1 { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x77 + MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x77 + MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x77 + MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x73 + MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x73 + >; + }; + + }; +}; + +&iomuxc_lpsr { + imx7d-12x12-lpddr3-arm2 { + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + }; + + imx7d-sdb { + pinctrl_usbotg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + pinctrl-1 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ocrams { + fsl,enable-lpsr; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 21 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio6 19 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&sim1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sim1_1>; + pinctrl-1 = <&pinctrl_sim1_1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-1 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart3_1 + &pinctrl_bt>; + pinctrl-1 = <&pinctrl_uart3_1 + &pinctrl_bt>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1_1>; + pinctrl-1 = <&pinctrl_usdhc1_1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_1>; + cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_1>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/arch/arm/dts/imx7d-19x19-ddr3-arm2.dts b/arch/arm/dts/imx7d-19x19-ddr3-arm2.dts new file mode 100644 index 00000000000..58b5e3139b7 --- /dev/null +++ b/arch/arm/dts/imx7d-19x19-ddr3-arm2.dts @@ -0,0 +1,816 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7 DDR3L 19x19 ARM2 Board"; + compatible = "fsl,imx7d-19x19-ddr3-arm2", "fsl,imx7d"; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + /* gpios disconnected see resistors R601, R583 */ + status = "disabled"; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_lcd_reset: lcd-reset { + compatible = "regulator-fixed"; + regulator-name = "lcd-reset"; + gpio = <&gpio3 4 0>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd3_vmmc: sd3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio6 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_coedc_5v: coedc_5v { + compatible = "regulator-fixed"; + regulator-name = "CODEC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_aud_3v3: aud_3v3 { + compatible = "regulator-fixed"; + regulator-name = "AUD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_aud_1v8: aud_1v8 { + compatible = "regulator-fixed"; + regulator-name = "AUD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "okay"; + + flash: at45@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&epxp { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + codec: wm8958@1a { + compatible = "wlf,wm8958"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "mclk1", "mclk2"; + + DBVDD1-supply = <®_aud_1v8>; + DBVDD2-supply = <®_aud_1v8>; + DBVDD3-supply = <®_aud_3v3>; + AVDD2-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_coedc_5v>; + SPKVDD2-supply = <®_coedc_5v>; + + wlf,ldo1ena; + wlf,ldo2ena; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd3_vselect>; + + imx7d-19x19-ddr3-arm2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x59 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x59 + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59 + MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x59 + + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x7F + MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x7F + >; + }; + + pinctrl_hog_sd3_vselect: hoggrp_sd3vselect { + fsl,pins = < + MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x59 + >; + }; + + pinctrl_csi: csigrp-1 { + fsl,pins = < + MX7D_PAD_LCD_DATA04__CSI_VSYNC 0x0F + MX7D_PAD_LCD_DATA05__CSI_HSYNC 0x0F + MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x0F + MX7D_PAD_LCD_DATA07__CSI_MCLK 0x0F + MX7D_PAD_LCD_DATA08__CSI_DATA9 0x0F + MX7D_PAD_LCD_DATA09__CSI_DATA8 0x0F + MX7D_PAD_LCD_DATA10__CSI_DATA7 0x0F + MX7D_PAD_LCD_DATA11__CSI_DATA6 0x0F + MX7D_PAD_LCD_DATA12__CSI_DATA5 0x0F + MX7D_PAD_LCD_DATA13__CSI_DATA4 0x0F + MX7D_PAD_LCD_DATA14__CSI_DATA3 0x0F + MX7D_PAD_LCD_DATA15__CSI_DATA2 0x0F + MX7D_PAD_LCD_DATA02__GPIO3_IO7 0x0F + MX7D_PAD_LCD_DATA03__GPIO3_IO8 0x0F + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x2 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f + >; + }; + + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f + >; + }; + + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x1f + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x59 + MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x59 + MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x59 + MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x59 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + >; + }; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-19x19-ddr3-arm2 { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x80000000 + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x80000000 + >; + }; + + pinctrl_mipi_csi: mipicsigrp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x3 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "disabled"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + status = "disabled"; +}; + +&sdma { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + pinctrl-0 = <&pinctrl_uart3dte_1>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + tuning-step = <2>; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + tuning-step = <2>; + vmmc-supply = <®_sd3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7d-19x19-lpddr2-arm2.dts b/arch/arm/dts/imx7d-19x19-lpddr2-arm2.dts new file mode 100644 index 00000000000..8541551c312 --- /dev/null +++ b/arch/arm/dts/imx7d-19x19-lpddr2-arm2.dts @@ -0,0 +1,474 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7D LPDDR2 19x19 ARM2 Board"; + compatible = "fsl,imx7d-19x19-lpddr2-arm2", "fsl,imx7d"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_SD1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-19x19-lpddr3-arm2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f + >; + }; + + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x71 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__EIM_OE 0x71 + MX7D_PAD_EPDC_DATA09__EIM_RW 0x71 + MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x71 + MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x71 + MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x75 + /* data */ + MX7D_PAD_LCD_DATA00__EIM_DATA0 0x7d + MX7D_PAD_LCD_DATA01__EIM_DATA1 0x7d + MX7D_PAD_LCD_DATA02__EIM_DATA2 0x7d + MX7D_PAD_LCD_DATA03__EIM_DATA3 0x7d + MX7D_PAD_LCD_DATA04__EIM_DATA4 0x7d + MX7D_PAD_LCD_DATA05__EIM_DATA5 0x7d + MX7D_PAD_LCD_DATA06__EIM_DATA6 0x7d + MX7D_PAD_LCD_DATA07__EIM_DATA7 0x7d + MX7D_PAD_LCD_DATA08__EIM_DATA8 0x7d + MX7D_PAD_LCD_DATA09__EIM_DATA9 0x7d + MX7D_PAD_LCD_DATA10__EIM_DATA10 0x7d + MX7D_PAD_LCD_DATA11__EIM_DATA11 0x7d + MX7D_PAD_LCD_DATA12__EIM_DATA12 0x7d + MX7D_PAD_LCD_DATA13__EIM_DATA13 0x7d + MX7D_PAD_LCD_DATA14__EIM_DATA14 0x7d + MX7D_PAD_LCD_DATA15__EIM_DATA15 0x7d + /* address */ + MX7D_PAD_EPDC_DATA00__EIM_AD0 0x71 + MX7D_PAD_EPDC_DATA01__EIM_AD1 0x71 + MX7D_PAD_EPDC_DATA02__EIM_AD2 0x71 + MX7D_PAD_EPDC_DATA03__EIM_AD3 0x71 + MX7D_PAD_EPDC_DATA04__EIM_AD4 0x71 + MX7D_PAD_EPDC_DATA05__EIM_AD5 0x71 + MX7D_PAD_EPDC_DATA06__EIM_AD6 0x71 + MX7D_PAD_EPDC_DATA07__EIM_AD7 0x71 + MX7D_PAD_EPDC_BDR1__EIM_AD8 0x71 + MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x71 + MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x71 + MX7D_PAD_EPDC_SDLE__EIM_AD11 0x71 + MX7D_PAD_EPDC_SDOE__EIM_AD12 0x71 + MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x71 + MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x71 + MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x71 + MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x71 + MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x71 + MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x71 + MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x71 + MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x71 + MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x71 + MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x71 + MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x71 + MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x71 + MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x71 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-19x19-lpddr3-arm2 { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x14 + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + }; +}; + +&sdma { + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x28000000 0x08000000>; + status = "okay"; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x08000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + pinctrl-0 = <&pinctrl_uart3dte_1>; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7d-19x19-lpddr3-arm2.dts b/arch/arm/dts/imx7d-19x19-lpddr3-arm2.dts new file mode 100644 index 00000000000..8c000da2332 --- /dev/null +++ b/arch/arm/dts/imx7d-19x19-lpddr3-arm2.dts @@ -0,0 +1,481 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7 LPDDR3 19x19 ARM2 Board"; + compatible = "fsl,imx7d-19x19-lpddr3-arm2", "fsl,imx7d"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_SD1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-19x19-lpddr3-arm2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f + >; + }; + + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x71 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__EIM_OE 0x71 + MX7D_PAD_EPDC_DATA09__EIM_RW 0x71 + MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x71 + MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x71 + MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x75 + /* data */ + MX7D_PAD_LCD_DATA00__EIM_DATA0 0x7d + MX7D_PAD_LCD_DATA01__EIM_DATA1 0x7d + MX7D_PAD_LCD_DATA02__EIM_DATA2 0x7d + MX7D_PAD_LCD_DATA03__EIM_DATA3 0x7d + MX7D_PAD_LCD_DATA04__EIM_DATA4 0x7d + MX7D_PAD_LCD_DATA05__EIM_DATA5 0x7d + MX7D_PAD_LCD_DATA06__EIM_DATA6 0x7d + MX7D_PAD_LCD_DATA07__EIM_DATA7 0x7d + MX7D_PAD_LCD_DATA08__EIM_DATA8 0x7d + MX7D_PAD_LCD_DATA09__EIM_DATA9 0x7d + MX7D_PAD_LCD_DATA10__EIM_DATA10 0x7d + MX7D_PAD_LCD_DATA11__EIM_DATA11 0x7d + MX7D_PAD_LCD_DATA12__EIM_DATA12 0x7d + MX7D_PAD_LCD_DATA13__EIM_DATA13 0x7d + MX7D_PAD_LCD_DATA14__EIM_DATA14 0x7d + MX7D_PAD_LCD_DATA15__EIM_DATA15 0x7d + /* address */ + MX7D_PAD_EPDC_DATA00__EIM_AD0 0x71 + MX7D_PAD_EPDC_DATA01__EIM_AD1 0x71 + MX7D_PAD_EPDC_DATA02__EIM_AD2 0x71 + MX7D_PAD_EPDC_DATA03__EIM_AD3 0x71 + MX7D_PAD_EPDC_DATA04__EIM_AD4 0x71 + MX7D_PAD_EPDC_DATA05__EIM_AD5 0x71 + MX7D_PAD_EPDC_DATA06__EIM_AD6 0x71 + MX7D_PAD_EPDC_DATA07__EIM_AD7 0x71 + MX7D_PAD_EPDC_BDR1__EIM_AD8 0x71 + MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x71 + MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x71 + MX7D_PAD_EPDC_SDLE__EIM_AD11 0x71 + MX7D_PAD_EPDC_SDOE__EIM_AD12 0x71 + MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x71 + MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x71 + MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x71 + MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x71 + MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x71 + MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x71 + MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x71 + MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x71 + MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x71 + MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x71 + MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x71 + MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x71 + MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x71 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-19x19-lpddr3-arm2 { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x14 + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + }; +}; + +&sdma { + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x28000000 0x08000000>; + status = "okay"; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x08000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + pinctrl-0 = <&pinctrl_uart3dte_1>; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7d-pinfunc-lpsr.h b/arch/arm/dts/imx7d-pinfunc-lpsr.h new file mode 100644 index 00000000000..378694ee05c --- /dev/null +++ b/arch/arm/dts/imx7d-pinfunc-lpsr.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX7D_PINFUNC_LPSR_H +#define __DTS_IMX7D_PINFUNC_LPSR_H + +/* + * The pin function ID is a tuple of + * + * + * NOTE: imx7d-lpsr pin groups should be put under &iomuxc_lpsr node when used + */ + +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 +#define MX7D_PAD_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 +#define MX7D_PAD_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 +#define MX7D_PAD_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 +#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 +#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 +#define MX7D_PAD_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 +#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 +#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 + +#endif /* __DTS_IMX7D_PINFUNC_LPSR_H */ diff --git a/arch/arm/dts/imx7d-pinfunc.h b/arch/arm/dts/imx7d-pinfunc.h index f6f7e78f882..3c54694782d 100644 --- a/arch/arm/dts/imx7d-pinfunc.h +++ b/arch/arm/dts/imx7d-pinfunc.h @@ -15,61 +15,6 @@ * */ -#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 -#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 -#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 -#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 -#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 #define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0 #define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0 #define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0 @@ -592,7 +537,7 @@ #define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2 #define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0 #define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0 -#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0 +#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x06C4 0x2 0x0 #define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 #define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 #define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 @@ -1112,13 +1057,13 @@ #define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0 #define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0 #define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x06A4 0x2 0x1 #define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0 #define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0 #define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x069C 0x2 0x1 #define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0 diff --git a/arch/arm/dts/imx7d-sdb-epdc.dts b/arch/arm/dts/imx7d-sdb-epdc.dts new file mode 100644 index 00000000000..e263ad44637 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-epdc.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-epdc.dtsi" diff --git a/arch/arm/dts/imx7d-sdb-epdc.dtsi b/arch/arm/dts/imx7d-sdb-epdc.dtsi new file mode 100644 index 00000000000..a04aca79b19 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-epdc.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&epdc { + status = "okay"; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&max17135 { + status = "okay"; +}; + +&sii902x { + status = "disabled"; +}; + +&sim1 { + status = "disabled"; +}; + +&uart5 { + status = "disabled"; +}; + +&i2c3 { + elan@10 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_elan_touch>; + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio6>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + gpio_elan_cs = <&gpio6 13 0>; + gpio_elan_rst = <&gpio6 15 0>; + gpio_intr = <&gpio6 12 0>; + status = "okay"; + }; +}; diff --git a/arch/arm/dts/imx7d-sdb-gpmi-weim.dts b/arch/arm/dts/imx7d-sdb-gpmi-weim.dts new file mode 100644 index 00000000000..346e38cca60 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-gpmi-weim.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-gpmi-weim.dtsi" diff --git a/arch/arm/dts/imx7d-sdb-gpmi-weim.dtsi b/arch/arm/dts/imx7d-sdb-gpmi-weim.dtsi new file mode 100644 index 00000000000..3a1208f4424 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-gpmi-weim.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&gpmi{ + status = "okay"; +}; + +&sai1{ + status = "disabled"; +}; + +&usdhc3{ + status = "disabled"; +}; + +&uart5{ + status = "disabled"; +}; diff --git a/arch/arm/dts/imx7d-sdb-qspi.dts b/arch/arm/dts/imx7d-sdb-qspi.dts new file mode 100644 index 00000000000..a46990554d2 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-qspi.dts @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-qspi.dtsi" diff --git a/arch/arm/dts/imx7d-sdb-qspi.dtsi b/arch/arm/dts/imx7d-sdb-qspi.dtsi new file mode 100644 index 00000000000..c684b56ced0 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-qspi.dtsi @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<0>; + + flash0: mx25l51245g@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + /* take off one dummy cycle */ + spi-nor,ddr-quad-read-dummy = <5>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/imx7d-sdb-reva.dts b/arch/arm/dts/imx7d-sdb-reva.dts new file mode 100644 index 00000000000..36568bd8df5 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-reva.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-sdb.dts" + +/ { + regulators { + reg_usb_otg2_vbus: regulator@1 { + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + }; + + reg_pcie: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + }; + + sound-hdmi { + cpu-dai = <&sai1>; + }; +}; + +&ecspi3 { + status = "disabled"; +}; + +&epdc { + pinctrl-0 = <&pinctrl_epdc0>; + en-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-assert-gpios = <>; +}; + +&i2c4 { + ov5647_mipi: ov5647_mipi@36 { + pwn-gpios = <&gpio_spi 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&iomuxc { + imx7d-sdb { + pinctrl_tsc2046_pendown: tsc2046_pendown { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 + MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 + MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 + MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x79 + MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x79 + >; + }; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_usbotg2_pwr_1>; +}; + +&iomuxc_lpsr { + pinctrl-0 = <&pinctrl_hog_2>; +}; + +&uart5 { + fsl,uart-has-rtscts; +}; diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index a9458993df5..4e3c2335d0b 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -16,27 +16,11 @@ reg = <0x80000000 0x80000000>; }; - spi4 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - status = "okay"; - gpio-sck = <&gpio1 13 0>; - gpio-mosi = <&gpio1 9 0>; - cs-gpios = <&gpio1 12 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gpio_spi: gpio_spi@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <1>; - registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ - spi-max-frequency = <100000>; - }; + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; }; regulators { @@ -64,187 +48,277 @@ enable-active-high; }; - reg_sd1_vmmc: regulator@3 { + reg_can2_3v3: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; + }; + + reg_vref_1v8: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_sd1_vmmc: regulator@5 { compatible = "regulator-fixed"; regulator-name = "VDD_SD1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; startup-delay-us = <200000>; + off-on-delay = <20000>; enable-active-high; }; - }; -}; -&iomuxc { - imx7d-sdb { - pinctrl_spi1: spi1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 - >; + wlreg_on: fixedregulator@6 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; }; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + gpios = <&gpio4 20 0>; /* WL_HOST_WAKE */ + wlreg_on-supply = <&wlreg_on>; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f - MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f - >; - }; + sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&codec>; + codec-master; + /* JD2: hp detect high for headphone*/ + hp-det = <2 0>; + hp-det-gpios = <&gpio2 28 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Main MIC", + "Main MIC", "MICB"; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <12288000>; + }; - pinctrl_usdhc1_gpio: usdhc1_gpiogrp { - fsl,pins = < - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ - >; - }; + sound-hdmi { + compatible = "fsl,imx7d-sdb-sii902x", + "fsl,imx-audio-sii902x"; + model = "sii902x-audio"; + cpu-dai = <&sai3>; + hdmi-controler = <&sii902x>; + }; - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; - }; + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + status = "okay"; + gpio-sck = <&gpio1 13 0>; + gpio-mosi = <&gpio1 9 0>; + cs-gpios = <&gpio1 12 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ + spi-max-frequency = <100000>; }; + }; +}; - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; - }; +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */ - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ - >; - }; +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; - pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5a - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a - >; +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + tsc2046@0 { + compatible = "ti,tsc2046"; + reg = <0>; + spi-max-frequency = <1000000>; + pinctrl-names ="default"; + pinctrl-0 = <&pinctrl_tsc2046_pendown>; + interrupt-parent = <&gpio2>; + interrupts = <29 0>; + pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <0>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <0>; + ti,pressure-max = /bits/ 16 <0>; + ti,x-plate-ohms = /bits/ 16 <400>; + wakeup-source; + }; +}; + +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&csi1 { + csi-mux-mipi = <&gpr 0x14 4>; + fsl,mipi-mode; + status = "okay"; + + port { + csi_ep: endpoint { + remote-endpoint = <&csi_mipi_ep>; }; + }; +}; - pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5b - MX7D_PAD_SD2_CLK__SD2_CLK 0x1b - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b - >; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0 &pinctrl_enet2_epdc0_en>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + en-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&epxp { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-assert-gpios = <&gpio_spi 5 GPIO_ACTIVE_HIGH>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; }; + }; +}; - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_epdc0_en>; + pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; +}; + +&mipi_csi { + clock-frequency = <240000000>; + status = "okay"; + port { + mipi_sensor_ep: endpoint1 { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; }; - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; + csi_mipi_ep: endpoint2 { + remote-endpoint = <&csi_ep>; }; }; }; +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; status = "okay"; pmic: pfuze3000@08 { @@ -309,7 +383,6 @@ vgen2_reg: vldo2 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <1550000>; - regulator-always-on; }; vgen3_reg: vccsd { @@ -341,35 +414,335 @@ &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; status = "okay"; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; status = "okay"; -}; + sii902x: sii902x@39 { + compatible = "SiI,sii902x"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sii902x>; + interrupt-parent = <&gpio2>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + reg = <0x39>; + status = "okay"; + }; -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "disabled"; -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 31 0>; + gpio_pmic_vcom_ctrl = <&gpio4 14 0>; + gpio_pmic_wakeup = <&gpio2 23 0>; + gpio_pmic_v3p3 = <&gpio2 30 0>; + gpio_pmic_intr = <&gpio2 22 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + clocks = <&clks IMX7D_CLK_DUMMY>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; + AVDD-supply = <&vgen6_reg>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_sensor_ep>; + }; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + enable-gpio = <&gpio_spi 7 GPIO_ACTIVE_LOW>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pcie_phy{ + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + reset-gpio = <&gpio_spi 1 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio_spi 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; + assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, + <&clks IMX7D_SAI3_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sdma { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>; + + imx7d-sdb { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + + pinctrl_usbotg2_pwr_2: usbotg2-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; + + pinctrl_enet2_epdc0_en: enet2_epdc0_grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x80000000 + >; + }; + + pinctrl_sai3_mclk: sai3grp_mclk { + fsl,pins = < + MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x1f + >; + }; + }; +}; + +&sim1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim1_1>; + port = <0>; + sven_low_active; + status = "okay"; +}; + + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + wakeup-source; vmmc-supply = <®_sd1_vmmc>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + enable-sdio-wakeup; + keep-power-in-suspend; status = "okay"; }; @@ -378,10 +751,13 @@ pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + enable-sdio-wakeup; + keep-power-in-suspend; non-removable; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "okay"; + cd-post; + pm-ignore-notify; + wifi-host; + status = "disabled"; }; &usdhc3 { @@ -389,9 +765,482 @@ pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; bus-width = <8>; non-removable; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; status = "okay"; }; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-sdb { + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ + >; + }; + + pinctrl_epdc_elan_touch: epdc_elan_touch_grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x59 + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x80000000 + >; + }; + + pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b + >; + }; + + pinctrl_ecspi3_cs: ecspi3_cs_grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x80000000 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4grp_gpio { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x7f + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x7f + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX7D_PAD_LCD_RESET__LCD_RESET 0x79 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pwrgood */ + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 /* vcom_ctrl */ + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x80000000 /* wakeup */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x80000000 /* v3p3 */ + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x80000000 /* pwr int */ + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 + >; + }; + + pinctrl_tsc2046_pendown: tsc2046_pendown { + fsl,pins = < + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 + >; + }; + + pinctrl_spi1: spi1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_sii902x: hdmigrp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 + >; + }; + + pinctrl_sim1_1: sim1grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x77 + MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x77 + MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x77 + MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x73 + MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x73 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x19 /* BT_REG_ON */ + >; + }; + + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + + pinctrl_usbotg2_pwr_1: usbotg2-1 { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */ + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + }; +}; diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi index f6dee41a05d..d89a3888109 100644 --- a/arch/arm/dts/imx7d.dtsi +++ b/arch/arm/dts/imx7d.dtsi @@ -1,6 +1,7 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright 2016 Toradex AG + * Copyright 2017 NXP. * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -44,10 +45,15 @@ #include "imx7s.dtsi" / { + aliases { + usb1 = &usbotg2; + }; + cpus { cpu0: cpu@0 { operating-points = < /* KHz uV */ + 1200000 1225000 996000 1075000 792000 975000 >; @@ -62,6 +68,20 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + soc { etm@3007d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; @@ -83,6 +103,265 @@ }; }; }; + + busfreq { + compatible = "fsl,imx_busfreq"; + fsl,max_ddr_freq = <533000000>; + clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>, + <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>, + <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>, + <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>, + <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>; + clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", "dram_alt_sel", + "pll_dram", "dram_alt_root", "pfd2_270m", "pfd1_332m", "ahb", "axi"; + interrupts = <0 112 0x04>, <0 113 0x04>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + }; + + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; + reg = <0x00100000 0x3fff>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + status = "disabled"; + }; + + ocrams_ddr: sram@00900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00900000 0x1000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocram: sram@901000 { + compatible = "mmio-sram"; + reg = <0x00901000 0x1f000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocrams: sram@00180000 { + compatible = "fsl,lpm-sram"; + reg = <0x00180000 0x8000>; + clocks = <&clks IMX7D_OCRAM_S_CLK>; + status = "disabled"; + }; + + ocrams_mf: sram-mf@00900000 { + compatible = "fsl,mega-fast-sram"; + reg = <0x00900000 0x20000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + pcie: pcie@0x33800000 { + compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; + reg = <0x33800000 0x4000>, <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + pcie-phy-supply = <®_1p0d>; + fsl,max-link-speed = <2>; + status = "disabled"; + }; + }; +}; + +&aips1 { + kpp: kpp@30320000 { + compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; + reg = <0x30320000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>; + status = "disabled"; + }; + + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "fsl,imx7d-ocotp", "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clks IMX7D_OCOTP_CLK>; + status = "okay"; + }; + + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupts = ; + fsl,tempmon =<&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + iomuxc_lpsr_gpr: lpsr-gpr@30270000 { + compatible = "fsl,imx7d-lpsr-gpr"; + reg = <0x30270000 0x10000>; + }; +}; + +&aips2 { + flextimer1: flextimer@30640000 { + compatible = "fsl,imx7d-flextimer"; + reg = <0x30640000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + flextimer2: flextimer@30650000 { + compatible = "fsl,imx7d-flextimer"; + reg = <0x30650000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + system_counter_rd: system-counter-rd@306a0000 { + compatible = "fsl,imx7d-system-counter-rd"; + reg = <0x306a0000 0x10000>; + status = "disabled"; + }; + + system_counter_cmp: system-counter-cmp@306b0000 { + compatible = "fsl,imx7d-system-counter-cmp"; + reg = <0x306b0000 0x10000>; + status = "disabled"; + }; + + system_counter_ctrl: system-counter-ctrl@306c0000 { + compatible = "fsl,imx7d-system-counter-ctrl"; + reg = <0x306c0000 0x10000>; + interrupts = , + ; + status = "disabled"; + }; + + pcie_phy: pcie-phy@306d0000 { + compatible = "fsl,imx-pcie-phy"; + reg = <0x306d0000 0x10000>; + status = "disabled"; + }; + + epdc: epdc@306f0000 { + compatible = "fsl,imx7d-epdc"; + interrupts = ; + reg = <0x306f0000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>; + clock-names = "epdc_axi", "epdc_pix"; + epdc-ram = <&gpr 0x4 30>; + status = "disabled"; + }; + + epxp: epxp@30700000 { + compatible = "fsl,imx7d-pxp-dma"; + interrupts = , + ; + reg = <0x30700000 0x10000>; + clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + csi1: csi@30710000 { + compatible = "fsl,imx7d-csi", "fsl,imx6s-csi"; + reg = <0x30710000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7d-mipi-csi"; + reg = <0x30750000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_clk", "phy_clk"; + mipi-phy-supply = <®_1p0d>; + csis-phy-reset = <&src 0x28 2>; + bus-width = <4>; + status = "disabled"; + }; + + mipi_dsi: mipi-dsi@30760000 { + compatible = "fsl,imx7d-mipi-dsi"; + reg = <0x30760000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_cfg_clk", "mipi_pllref_clk"; + mipi-phy-supply = <®_1p0d>; + status = "disabled"; + }; + + ddrc: ddrc@307a0000 { + compatible = "fsl,imx7-ddrc"; + reg = <0x307a0000 0x10000>; }; }; @@ -95,6 +374,9 @@ fsl,usbphy = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; phy-clkgate-delay-us = <400>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; @@ -116,17 +398,121 @@ interrupts = , , ; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>, <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET2_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; status = "disabled"; }; + + crypto: caam@30900000 { + compatible = "fsl,imx7d-caam", "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = ; + clocks = <&clks IMX7D_CAAM_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "ipg", "aclk"; + + sec_ctrl: ctrl@0 { + /* CAAM Page 0 only accessible */ + /* by secure world */ + compatible = "fsl,sec-v4.0-ctrl"; + reg = <0x30900000 0x1000>; + secure-status = "okay"; + status = "disabled"; + }; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr2@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; + + mu: mu@30aa0000 { + compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + clock-names = "mu"; + status = "okay"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx7d-rpmsg"; + status = "disabled"; + }; + + sema4: sema4@30ac0000 { + compatible = "fsl,imx7d-sema4"; + reg = <0x30ac0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>; + clock-names = "sema4"; + status = "okay"; + }; + + sim1: sim@30b90000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30b90000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SIM1_ROOT_CLK>; + clock-names = "sim"; + status = "disabled"; + }; + + sim2: sim@30ba0000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30ba0000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + qspi1: qspi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + weim: weim@30bc0000 { + compatible = "fsl,imx7d-weim", "fsl,imx6sx-weim", "fsl,imx6q-weim"; + reg = <0x30bc0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_EIM_ROOT_CLK>; + status = "disabled"; + }; + +}; + +&usbphynop3 { + vcc-supply = <®_1p2>; }; &ca_funnel_ports { diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi index a7d48e785d3..5c5f27a2a6c 100644 --- a/arch/arm/dts/imx7s.dtsi +++ b/arch/arm/dts/imx7s.dtsi @@ -46,6 +46,8 @@ #include #include #include "imx7d-pinfunc.h" +#include "imx7d-pinfunc-lpsr.h" +#include "skeleton.dtsi" / { #address-cells = <1>; @@ -71,9 +73,6 @@ i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -81,10 +80,12 @@ serial4 = &uart5; serial5 = &uart6; serial6 = &uart7; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; + spi1 = &qspi1; + spi2 = &ecspi1; + spi3 = &ecspi2; + spi4 = &ecspi3; + spi5 = &ecspi4; + usb0 = &usbotg1; }; cpus { @@ -98,6 +99,7 @@ clock-frequency = <792000000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; + clock-names = "arm"; }; }; @@ -119,7 +121,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - interrupt-parent = <&intc>; + interrupt-parent = <&gpc>; ranges; funnel@30041000 { @@ -305,14 +307,18 @@ <0x31002000 0x2000>, <0x31004000 0x2000>, <0x31006000 0x2000>; + interrupt-parent = <&intc>; }; timer { compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; interrupts = , , , ; + interrupt-parent = <&intc>; + clock-frequency = <8000000>; }; aips1: aips-bus@30000000 { @@ -322,6 +328,23 @@ reg = <0x30000000 0x400000>; ranges; + gpc: gpc@303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x1000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>; + }; + + pgc { + compatible = "fsl,imx7d-pgc"; + mipi-phy-supply = <®_1p0d>; + pcie-phy-supply = <®_1p0d>; + vcc-supply = <®_1p2>; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; @@ -447,9 +470,10 @@ compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; reg = <0x302d0000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT1_ROOT_CLK>; - clock-names = "ipg", "per"; + clocks = <&clks IMX7D_GPT1_ROOT_CLK>, + <&clks IMX7D_GPT1_ROOT_CLK>, + <&clks IMX7D_GPT_3M_CLK>; + clock-names = "ipg", "per", "osc_per"; }; gpt2: gpt@302e0000 { @@ -516,7 +540,23 @@ anatop-min-bit-val = <8>; anatop-min-voltage = <800000>; anatop-max-voltage = <1200000>; + anatop-enable-bit = <0>; + }; + + reg_1p2: regulator-vdd1p2@220 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + anatop-reg-offset = <0x220>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0x14>; + anatop-min-voltage = <1100000>; + anatop-max-voltage = <1300000>; + anatop-enable-bit = <31>; }; + }; snvs: snvs@30370000 { @@ -535,7 +575,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + mask = <0x61>; }; snvs_pwrkey: snvs-powerkey { @@ -651,8 +691,9 @@ reg = <0x30730000 0x10000>; interrupts = ; clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, - <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; - clock-names = "pix", "axi"; + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; status = "disabled"; }; }; @@ -719,6 +760,8 @@ clocks = <&clks IMX7D_UART2_ROOT_CLK>, <&clks IMX7D_UART2_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 24 4 0>, <&sdma 25 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -730,6 +773,8 @@ clocks = <&clks IMX7D_UART3_ROOT_CLK>, <&clks IMX7D_UART3_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 26 4 0>, <&sdma 27 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -739,10 +784,11 @@ reg = <0x308a0000 0x10000>; interrupts = ; clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_SAI1_ROOT_CLK>, <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; status = "disabled"; @@ -754,10 +800,11 @@ reg = <0x308b0000 0x10000>; interrupts = ; clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_SAI2_ROOT_CLK>, <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; status = "disabled"; @@ -769,10 +816,11 @@ reg = <0x308c0000 0x10000>; interrupts = ; clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_SAI3_ROOT_CLK>, <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; status = "disabled"; @@ -785,6 +833,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN1_ROOT_CLK>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; @@ -795,6 +844,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN2_ROOT_CLK>; clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; @@ -846,6 +896,8 @@ clocks = <&clks IMX7D_UART4_ROOT_CLK>, <&clks IMX7D_UART4_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 28 4 0>, <&sdma 29 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -857,6 +909,8 @@ clocks = <&clks IMX7D_UART5_ROOT_CLK>, <&clks IMX7D_UART5_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 30 4 0>, <&sdma 31 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -868,6 +922,8 @@ clocks = <&clks IMX7D_UART6_ROOT_CLK>, <&clks IMX7D_UART6_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 32 4 0>, <&sdma 33 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -879,6 +935,8 @@ clocks = <&clks IMX7D_UART7_ROOT_CLK>, <&clks IMX7D_UART7_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 34 4 0>, <&sdma 35 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -890,6 +948,9 @@ fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; phy-clkgate-delay-us = <400>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; @@ -934,10 +995,12 @@ compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b40000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, <&clks IMX7D_USDHC1_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; bus-width = <4>; status = "disabled"; }; @@ -950,6 +1013,8 @@ <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_USDHC2_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; bus-width = <4>; status = "disabled"; }; @@ -962,6 +1027,8 @@ <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_USDHC3_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; bus-width = <4>; status = "disabled"; }; @@ -983,11 +1050,11 @@ interrupts = , , ; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,num-tx-queues=<3>; diff --git a/arch/arm/dts/imx7ulp-10x10-arm2.dts b/arch/arm/dts/imx7ulp-10x10-arm2.dts new file mode 100644 index 00000000000..d105937c0da --- /dev/null +++ b/arch/arm/dts/imx7ulp-10x10-arm2.dts @@ -0,0 +1,64 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "NXP i.MX7ULP 10x10 arm2"; + compatible = "fsl,imx7ulp-10x10-arm2", "fsl,imx7ulp", "Generic DT based system"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x40A60000,115200"; + stdout-path = &lpuart6; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; +}; + +&iomuxc1 { + pinctrl-names = "default"; + + imx7ulp-10x10-arm2 { + pinctrl_lpuart6: lpuart6grp { + fsl,pins = < + IMX7ULP_PAD_PTE11__LPUART6_RX 0x400 + IMX7ULP_PAD_PTE10__LPUART6_TX 0x400 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX7ULP_PAD_PTE3__SDHC1_CMD 0x843 + IMX7ULP_PAD_PTE2__SDHC1_CLK 0x843 + IMX7ULP_PAD_PTE4__SDHC1_D3 0x843 + IMX7ULP_PAD_PTE5__SDHC1_D2 0x843 + IMX7ULP_PAD_PTE0__SDHC1_D1 0x843 + IMX7ULP_PAD_PTE1__SDHC1_D0 0x843 + >; + }; + }; +}; + +&lpuart6 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart6>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7ulp-14x14-arm2.dts b/arch/arm/dts/imx7ulp-14x14-arm2.dts new file mode 100644 index 00000000000..8a67474e2fc --- /dev/null +++ b/arch/arm/dts/imx7ulp-14x14-arm2.dts @@ -0,0 +1,72 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "NXP i.MX7ULP 14x14 arm2"; + compatible = "fsl,imx7ulp-14x14-arm2", "fsl,imx7ulp", "Generic DT based system"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200"; + stdout-path = &lpuart4; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; +}; + +&iomuxc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7ulp-14x14-arm2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + IMX7ULP_PAD_PTC10__PTC10 0x30100 + IMX7ULP_PAD_PTC1__PTC1 0x20100 + >; + }; + + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + IMX7ULP_PAD_PTC3__LPUART4_RX 0x400 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x400 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX7ULP_PAD_PTE3__SDHC1_CMD 0x843 + IMX7ULP_PAD_PTE2__SDHC1_CLK 0x843 + IMX7ULP_PAD_PTE4__SDHC1_D3 0x843 + IMX7ULP_PAD_PTE5__SDHC1_D2 0x843 + IMX7ULP_PAD_PTE0__SDHC1_D1 0x843 + IMX7ULP_PAD_PTE1__SDHC1_D0 0x843 + >; + }; + }; +}; + +&lpuart4 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7ulp-evk-emmc.dts b/arch/arm/dts/imx7ulp-evk-emmc.dts new file mode 100644 index 00000000000..403bfb28e2b --- /dev/null +++ b/arch/arm/dts/imx7ulp-evk-emmc.dts @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +/* To support eMMC HS200/HS400, need to do the following reowrk: + * 1,remove TF sd slot, replace eMMC chip + * 2,fix eMMC I/O voltage to 1.8v, remove R183, short TP3 and TP89 + * 3,add R107, make eMMC boot work + */ +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0_8bit>; + pinctrl-1 = <&pinctrl_usdhc0_8bit>; + pinctrl-2 = <&pinctrl_usdhc0_8bit>; + pinctrl-3 = <&pinctrl_usdhc0_8bit>; + non-removable; + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7ulp-evk-qspi.dts b/arch/arm/dts/imx7ulp-evk-qspi.dts new file mode 100644 index 00000000000..aeef08a552c --- /dev/null +++ b/arch/arm/dts/imx7ulp-evk-qspi.dts @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + + flash0: mx25r6435f@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25r6435f"; + spi-max-frequency = <29000000>; + }; +}; + +&iomuxc { + status = "okay"; +}; + +&iomuxc { + imx7ulp-evk { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + IMX7ULP_PAD_PTB7__QSPIA_SS1_B 0x43 /* SS1 */ + IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x43 /* SS0 */ + IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x43 /* SCLK */ + IMX7ULP_PAD_PTB9__QSPIA_DQS 0x43 /* DQS */ + IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x43 /* D3 */ + IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x43 /* D2 */ + IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x43 /* D1 */ + IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x43 /* D0 */ + >; + }; + }; +}; + diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts index e56b7226e6f..08a682f3144 100644 --- a/arch/arm/dts/imx7ulp-evk.dts +++ b/arch/arm/dts/imx7ulp-evk.dts @@ -15,7 +15,7 @@ compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system"; chosen { - bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200"; + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200"; stdout-path = &lpuart4; }; @@ -66,7 +66,7 @@ compatible = "regulator-fixed"; reg = <0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; regulator-name = "usb_otg1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -84,22 +84,6 @@ enable-active-high; }; - reg_vsd_3v3b: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "VSD_3V3B"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_extcon_usb1>; }; pf1550-rpmsg { @@ -166,134 +150,135 @@ imx7ulp-evk { pinctrl_hog_1: hoggrp-1 { fsl,pins = < - ULP1_PAD_PTC10__PTC10 0x30100 /* USDHC0 CD */ - ULP1_PAD_PTC1__PTC1 0x20100 - ULP1_PAD_PTD0__PTD0 0x30100 /* USDHC0 RST */ - ULP1_PAD_PTE13__PTE13 0x30103 /* USDHC1 CD */ - ULP1_PAD_PTE12__PTE12 0x30103 /* USDHC1 WP */ - ULP1_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */ + IMX7ULP_PAD_PTC1__PTC1 0x20000 >; }; pinctrl_backlight: backlight_grp { fsl,pins = < - ULP1_PAD_PTF2__PTF2 0x20100 + IMX7ULP_PAD_PTF2__PTF2 0x20100 >; }; pinctrl_lpi2c5: lpi2c5grp { fsl,pins = < - ULP1_PAD_PTC4__LPI2C5_SCL 0x527 - ULP1_PAD_PTC5__LPI2C5_SDA 0x527 + IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27 + IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27 >; }; pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { fsl,pins = < - ULP1_PAD_PTC19__PTC19 0x20103 + IMX7ULP_PAD_PTC19__PTC19 0x20003 >; }; pinctrl_lpuart4: lpuart4grp { fsl,pins = < - ULP1_PAD_PTC3__LPUART4_RX 0x400 - ULP1_PAD_PTC2__LPUART4_TX 0x400 + IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 >; }; pinctrl_lpuart6: lpuart6grp { fsl,pins = < - ULP1_PAD_PTE10__LPUART6_TX 0x400 - ULP1_PAD_PTE11__LPUART6_RX 0x400 - ULP1_PAD_PTE9__LPUART6_RTS_B 0x400 - ULP1_PAD_PTE8__LPUART6_CTS_B 0x400 - ULP1_PAD_PTE7__PTE7 0x00 /* BT_REG_ON */ + IMX7ULP_PAD_PTE10__LPUART6_TX 0x3 + IMX7ULP_PAD_PTE11__LPUART6_RX 0x3 + IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3 + IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3 + IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */ >; }; pinctrl_lpuart7: lpuart7grp { fsl,pins = < - ULP1_PAD_PTF14__LPUART7_TX 0x400 - ULP1_PAD_PTF15__LPUART7_RX 0x400 - ULP1_PAD_PTF13__LPUART7_RTS_B 0x400 - ULP1_PAD_PTF12__LPUART7_CTS_B 0x400 + IMX7ULP_PAD_PTF14__LPUART7_TX 0x3 + IMX7ULP_PAD_PTF15__LPUART7_RX 0x3 + IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3 + IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3 >; }; pinctrl_usdhc0: usdhc0grp { fsl,pins = < - ULP1_PAD_PTD1__SDHC0_CMD 0x843 - ULP1_PAD_PTD2__SDHC0_CLK 0x10843 - ULP1_PAD_PTD7__SDHC0_D3 0x843 - ULP1_PAD_PTD8__SDHC0_D2 0x843 - ULP1_PAD_PTD9__SDHC0_D1 0x843 - ULP1_PAD_PTD10__SDHC0_D0 0x843 + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTC10__PTC10 0x10000 /* USDHC0 CD */ + IMX7ULP_PAD_PTD0__PTD0 0x20000 /* USDHC0 RST */ >; }; pinctrl_usdhc0_8bit: usdhc0grp_8bit { fsl,pins = < - ULP1_PAD_PTD1__SDHC0_CMD 0x843 - ULP1_PAD_PTD2__SDHC0_CLK 0x843 - ULP1_PAD_PTD3__SDHC0_D7 0x843 - ULP1_PAD_PTD4__SDHC0_D6 0x843 - ULP1_PAD_PTD5__SDHC0_D5 0x843 - ULP1_PAD_PTD6__SDHC0_D4 0x843 - ULP1_PAD_PTD7__SDHC0_D3 0x843 - ULP1_PAD_PTD8__SDHC0_D2 0x843 - ULP1_PAD_PTD9__SDHC0_D1 0x843 - ULP1_PAD_PTD10__SDHC0_D0 0x843 + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 + IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 + IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 + IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 + IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 >; }; pinctrl_lpi2c7: lpi2c7grp { fsl,pins = < - ULP1_PAD_PTF12__LPI2C7_SCL 0x527 - ULP1_PAD_PTF13__LPI2C7_SDA 0x527 + IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27 + IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27 >; }; pinctrl_lpspi3: lpspi3grp { fsl,pins = < - ULP1_PAD_PTF16__LPSPI3_SIN 0x300 - ULP1_PAD_PTF17__LPSPI3_SOUT 0x300 - ULP1_PAD_PTF18__LPSPI3_SCK 0x300 - ULP1_PAD_PTF19__LPSPI3_PCS0 0x300 + IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0 + IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0 + IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0 + IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0 >; }; - pinctrl_usb_otg1: usbotg1grp { + pinctrl_usbotg1_vbus: otg1vbusgrp { fsl,pins = < - ULP1_PAD_PTC0__PTC0 0x30100 + IMX7ULP_PAD_PTC0__PTC0 0x20000 >; }; - pinctrl_extcon_usb1: extcon1grp { + pinctrl_usbotg1_id: otg1idgrp { fsl,pins = < - ULP1_PAD_PTC8__PTC8 0x30103 + IMX7ULP_PAD_PTC13__USB0_ID 0x10003 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - ULP1_PAD_PTE3__SDHC1_CMD 0x843 - ULP1_PAD_PTE2__SDHC1_CLK 0x843 - ULP1_PAD_PTE1__SDHC1_D0 0x843 - ULP1_PAD_PTE0__SDHC1_D1 0x843 - ULP1_PAD_PTE5__SDHC1_D2 0x843 - ULP1_PAD_PTE4__SDHC1_D3 0x843 + IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43 + IMX7ULP_PAD_PTE2__SDHC1_CLK 0x10042 + IMX7ULP_PAD_PTE1__SDHC1_D0 0x43 + IMX7ULP_PAD_PTE0__SDHC1_D1 0x43 + IMX7ULP_PAD_PTE5__SDHC1_D2 0x43 + IMX7ULP_PAD_PTE4__SDHC1_D3 0x43 >; }; pinctrl_usdhc1_rst: usdhc1grp_rst { fsl,pins = < - ULP1_PAD_PTE11__PTE11 0x30100 /* USDHC1 RST */ + IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */ + IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */ + IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */ + IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */ >; }; - pinctrl_wifi: wifigrp { + pinctrl_dsi_hdmi: dsi_hdmi_grp { fsl,pins = < - ULP1_PAD_PTE6__PTE6 0x43 /* WL_REG_ON */ + IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */ >; }; }; @@ -304,7 +289,7 @@ disp-dev = "mipi_dsi_northwest"; display = <&display0>; - display0: display { + display0: display@0 { bits-per-pixel = <16>; bus-width = <24>; @@ -343,21 +328,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpi2c5>; status = "okay"; - - fxas2100x@20 { - compatible = "fsl,fxas2100x"; - reg = <0x20>; - }; - - fxos8700@1e { - compatible = "fsl,fxos8700"; - reg = <0x1e>; - }; - - mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; }; &lpspi3 { @@ -406,13 +376,18 @@ &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; - extcon = <0>, <&extcon_usb1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; srp-disable; hnp-disable; adp-disable; status = "okay"; }; +&usbphy1 { + fsl,tx-d-cal = <88>; +}; + &usdhc0 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc0>; diff --git a/arch/arm/dts/imx7ulp-pinfunc.h b/arch/arm/dts/imx7ulp-pinfunc.h index b1b6a71f2cd..777d7f09475 100644 --- a/arch/arm/dts/imx7ulp-pinfunc.h +++ b/arch/arm/dts/imx7ulp-pinfunc.h @@ -1,5 +1,6 @@ /* - * Copyright 2014 - 2015 Freescale Semiconductor, Inc. + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 - 2018 NXP * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -7,876 +8,885 @@ * */ -#ifndef __DTS_ULP1_PINFUNC_H -#define __DTS_ULP1_PINFUNC_H +#ifndef __DTS_IMX7ULP_PINFUNC_H +#define __DTS_IMX7ULP_PINFUNC_H /* * The pin function ID is a tuple of - * - * - * !!! IMPORTANT NOTE !!! - * - * There's common mux_reg & conf_reg register for each pad on ULP1 device, so the first - * two values are defined as same value. Extra non-zero mux2_reg value within the tuple - * means that there's additional mux2 control register that must be configured to - * mux2_val accordingly to fetch desired pin functionality on ULP1 device. - * + * */ +#define IMX7ULP_PAD_PTA0__CMP0_IN1_3V 0x0000 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA0__PTA0 0x0000 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA0__LPSPI0_PCS1 0x0000 0x0104 0x3 0x2 +#define IMX7ULP_PAD_PTA0__LPUART0_CTS_B 0x0000 0x01F8 0x4 0x2 +#define IMX7ULP_PAD_PTA0__LPI2C0_SCL 0x0000 0x017C 0x5 0x2 +#define IMX7ULP_PAD_PTA0__TPM0_CLKIN 0x0000 0x01A8 0x6 0x2 +#define IMX7ULP_PAD_PTA0__I2S0_RX_BCLK 0x0000 0x01B8 0x7 0x2 +#define IMX7ULP_PAD_PTA0__LLWU0_P0 0x0000 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA1__CMP0_IN2_3V 0x0004 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA1__LPSPI0_PCS2 0x0004 0x0108 0x3 0x1 +#define IMX7ULP_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA1__LPI2C0_SDA 0x0004 0x0180 0x5 0x1 +#define IMX7ULP_PAD_PTA1__TPM0_CH0 0x0004 0x0138 0x6 0x1 +#define IMX7ULP_PAD_PTA1__I2S0_RX_FS 0x0004 0x01BC 0x7 0x1 +#define IMX7ULP_PAD_PTA2__CMP1_IN2_3V 0x0008 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA2__LPSPI0_PCS3 0x0008 0x010C 0x3 0x1 +#define IMX7ULP_PAD_PTA2__LPUART0_TX 0x0008 0x0200 0x4 0x1 +#define IMX7ULP_PAD_PTA2__LPI2C0_HREQ 0x0008 0x0178 0x5 0x1 +#define IMX7ULP_PAD_PTA2__TPM0_CH1 0x0008 0x013C 0x6 0x1 +#define IMX7ULP_PAD_PTA2__I2S0_RXD0 0x0008 0x01DC 0x7 0x1 +#define IMX7ULP_PAD_PTA3__CMP1_IN4_3V 0x000C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA3__PTA3 0x000C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA3__LPSPI0_PCS0 0x000C 0x0100 0x3 0x1 +#define IMX7ULP_PAD_PTA3__LPUART0_RX 0x000C 0x01FC 0x4 0x1 +#define IMX7ULP_PAD_PTA3__TPM0_CH2 0x000C 0x0140 0x6 0x1 +#define IMX7ULP_PAD_PTA3__I2S0_RXD1 0x000C 0x01E0 0x7 0x1 +#define IMX7ULP_PAD_PTA3__CMP0_OUT 0x000C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA3__LLWU0_P1 0x000C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA4__ADC1_CH3A 0x0010 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA4__LPSPI0_SIN 0x0010 0x0114 0x3 0x1 +#define IMX7ULP_PAD_PTA4__LPUART1_CTS_B 0x0010 0x0204 0x4 0x1 +#define IMX7ULP_PAD_PTA4__LPI2C1_SCL 0x0010 0x0188 0x5 0x1 +#define IMX7ULP_PAD_PTA4__TPM0_CH3 0x0010 0x0144 0x6 0x1 +#define IMX7ULP_PAD_PTA4__I2S0_MCLK 0x0010 0x01B4 0x7 0x1 +#define IMX7ULP_PAD_PTA5__ADC1_CH3B 0x0014 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA5__LPSPI0_SOUT 0x0014 0x0118 0x3 0x1 +#define IMX7ULP_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA5__LPI2C1_SDA 0x0014 0x018C 0x5 0x1 +#define IMX7ULP_PAD_PTA5__TPM0_CH4 0x0014 0x0148 0x6 0x1 +#define IMX7ULP_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01C0 0x7 0x1 +#define IMX7ULP_PAD_PTA6__ADC1_CH4A 0x0018 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA6__LPSPI0_SCK 0x0018 0x0110 0x3 0x1 +#define IMX7ULP_PAD_PTA6__LPUART1_TX 0x0018 0x020C 0x4 0x1 +#define IMX7ULP_PAD_PTA6__LPI2C1_HREQ 0x0018 0x0184 0x5 0x1 +#define IMX7ULP_PAD_PTA6__TPM0_CH5 0x0018 0x014C 0x6 0x1 +#define IMX7ULP_PAD_PTA6__I2S0_TX_FS 0x0018 0x01C4 0x7 0x1 +#define IMX7ULP_PAD_PTA7__ADC1_CH4B 0x001C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA7__PTA7 0x001C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA7__LPUART1_RX 0x001C 0x0208 0x4 0x1 +#define IMX7ULP_PAD_PTA7__TPM1_CH1 0x001C 0x0154 0x6 0x1 +#define IMX7ULP_PAD_PTA7__I2S0_TXD0 0x001C 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA8__ADC1_CH5A 0x0020 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA8__LPSPI1_PCS1 0x0020 0x0120 0x3 0x1 +#define IMX7ULP_PAD_PTA8__LPUART2_CTS_B 0x0020 0x0210 0x4 0x1 +#define IMX7ULP_PAD_PTA8__LPI2C2_SCL 0x0020 0x0194 0x5 0x1 +#define IMX7ULP_PAD_PTA8__TPM1_CLKIN 0x0020 0x01AC 0x6 0x1 +#define IMX7ULP_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA9__ADC1_CH5B 0x0024 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA9__LPSPI1_PCS2 0x0024 0x0124 0x3 0x1 +#define IMX7ULP_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA9__LPI2C2_SDA 0x0024 0x0198 0x5 0x1 +#define IMX7ULP_PAD_PTA9__TPM1_CH0 0x0024 0x0150 0x6 0x1 +#define IMX7ULP_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA10__LPSPI1_PCS3 0x0028 0x0128 0x3 0x1 +#define IMX7ULP_PAD_PTA10__LPUART2_TX 0x0028 0x0218 0x4 0x1 +#define IMX7ULP_PAD_PTA10__LPI2C2_HREQ 0x0028 0x0190 0x5 0x1 +#define IMX7ULP_PAD_PTA10__TPM2_CLKIN 0x0028 0x01F4 0x6 0x1 +#define IMX7ULP_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01B8 0x7 0x1 +#define IMX7ULP_PAD_PTA11__ADC1_CH6B 0x002C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA11__PTA11 0x002C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA11__LPUART2_RX 0x002C 0x0214 0x4 0x1 +#define IMX7ULP_PAD_PTA11__TPM2_CH0 0x002C 0x0158 0x6 0x1 +#define IMX7ULP_PAD_PTA11__I2S0_RX_FS 0x002C 0x01BC 0x7 0x2 +#define IMX7ULP_PAD_PTA12__ADC1_CH7A 0x0030 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA12__LPSPI1_SIN 0x0030 0x0130 0x3 0x1 +#define IMX7ULP_PAD_PTA12__LPUART3_CTS_B 0x0030 0x021C 0x4 0x1 +#define IMX7ULP_PAD_PTA12__LPI2C3_SCL 0x0030 0x01A0 0x5 0x1 +#define IMX7ULP_PAD_PTA12__TPM2_CH1 0x0030 0x015C 0x6 0x1 +#define IMX7ULP_PAD_PTA12__I2S0_RXD0 0x0030 0x01DC 0x7 0x2 +#define IMX7ULP_PAD_PTA13__ADC1_CH7B 0x0034 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA13__PTA13 0x0034 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA13__LPSPI1_SOUT 0x0034 0x0134 0x3 0x2 +#define IMX7ULP_PAD_PTA13__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA13__LPI2C3_SDA 0x0034 0x01A4 0x5 0x2 +#define IMX7ULP_PAD_PTA13__TPM3_CLKIN 0x0034 0x01B0 0x6 0x1 +#define IMX7ULP_PAD_PTA13__I2S0_RXD1 0x0034 0x01E0 0x7 0x2 +#define IMX7ULP_PAD_PTA13__CMP0_OUT 0x0034 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA13__LLWU0_P2 0x0034 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA14__ADC1_CH8A 0x0038 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA14__PTA14 0x0038 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA14__LPSPI1_SCK 0x0038 0x012C 0x3 0x2 +#define IMX7ULP_PAD_PTA14__LPUART3_TX 0x0038 0x0224 0x4 0x2 +#define IMX7ULP_PAD_PTA14__LPI2C3_HREQ 0x0038 0x019C 0x5 0x2 +#define IMX7ULP_PAD_PTA14__TPM3_CH0 0x0038 0x0160 0x6 0x1 +#define IMX7ULP_PAD_PTA14__I2S0_MCLK 0x0038 0x01B4 0x7 0x2 +#define IMX7ULP_PAD_PTA14__LLWU0_P3 0x0038 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA15__ADC1_CH8B 0x003C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA15__PTA15 0x003C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA15__LPSPI1_PCS0 0x003C 0x011C 0x3 0x1 +#define IMX7ULP_PAD_PTA15__LPUART3_RX 0x003C 0x0220 0x4 0x1 +#define IMX7ULP_PAD_PTA15__TPM3_CH1 0x003C 0x0164 0x6 0x1 +#define IMX7ULP_PAD_PTA15__I2S0_TX_BCLK 0x003C 0x01C0 0x7 0x2 +#define IMX7ULP_PAD_PTA16__CMP1_IN5_3V 0x0040 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA16__LPSPI0_SOUT 0x0040 0x0118 0x3 0x2 +#define IMX7ULP_PAD_PTA16__LPUART0_CTS_B 0x0040 0x01F8 0x4 0x1 +#define IMX7ULP_PAD_PTA16__LPI2C0_SCL 0x0040 0x017C 0x5 0x1 +#define IMX7ULP_PAD_PTA16__TPM3_CH2 0x0040 0x0168 0x6 0x1 +#define IMX7ULP_PAD_PTA16__I2S0_TX_FS 0x0040 0x01C4 0x7 0x2 +#define IMX7ULP_PAD_PTA17__CMP1_IN6_3V 0x0044 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA17__LPSPI0_SCK 0x0044 0x0110 0x3 0x2 +#define IMX7ULP_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA17__LPI2C0_SDA 0x0044 0x0180 0x5 0x2 +#define IMX7ULP_PAD_PTA17__TPM3_CH3 0x0044 0x016C 0x6 0x1 +#define IMX7ULP_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA18__CMP1_IN1_3V 0x0048 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA18__PTA18 0x0048 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA18__FXIO0_D2 0x0048 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA18__LPSPI0_PCS0 0x0048 0x0100 0x3 0x2 +#define IMX7ULP_PAD_PTA18__LPUART0_TX 0x0048 0x0200 0x4 0x2 +#define IMX7ULP_PAD_PTA18__LPI2C0_HREQ 0x0048 0x0178 0x5 0x2 +#define IMX7ULP_PAD_PTA18__TPM3_CH4 0x0048 0x0170 0x6 0x1 +#define IMX7ULP_PAD_PTA18__I2S0_TXD1 0x0048 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA18__LLWU0_P4 0x0048 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA19__CMP1_IN3_3V 0x004C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA19__PTA19 0x004C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA19__FXIO0_D3 0x004C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA19__LPUART0_RX 0x004C 0x01FC 0x4 0x2 +#define IMX7ULP_PAD_PTA19__TPM3_CH5 0x004C 0x0174 0x6 0x1 +#define IMX7ULP_PAD_PTA19__I2S1_RX_BCLK 0x004C 0x01CC 0x7 0x1 +#define IMX7ULP_PAD_PTA19__LPTMR0_ALT3 0x004C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA19__LLWU0_P5 0x004C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA20__ADC0_CH10A 0x0050 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA20__LPSPI0_SIN 0x0050 0x0114 0x3 0x2 +#define IMX7ULP_PAD_PTA20__LPUART1_CTS_B 0x0050 0x0204 0x4 0x2 +#define IMX7ULP_PAD_PTA20__LPI2C1_SCL 0x0050 0x0188 0x5 0x2 +#define IMX7ULP_PAD_PTA20__TPM0_CLKIN 0x0050 0x01A8 0x6 0x1 +#define IMX7ULP_PAD_PTA20__I2S1_RX_FS 0x0050 0x01D0 0x7 0x1 +#define IMX7ULP_PAD_PTA21__ADC0_CH10B 0x0054 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA21__LPSPI0_PCS1 0x0054 0x0104 0x3 0x1 +#define IMX7ULP_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA21__LPI2C1_SDA 0x0054 0x018C 0x5 0x2 +#define IMX7ULP_PAD_PTA21__TPM0_CH0 0x0054 0x0138 0x6 0x2 +#define IMX7ULP_PAD_PTA21__I2S1_RXD0 0x0054 0x01E4 0x7 0x1 +#define IMX7ULP_PAD_PTA22__ADC0_CH9A 0x0058 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA22__LPSPI0_PCS2 0x0058 0x0108 0x3 0x2 +#define IMX7ULP_PAD_PTA22__LPUART1_TX 0x0058 0x020C 0x4 0x2 +#define IMX7ULP_PAD_PTA22__LPI2C1_HREQ 0x0058 0x0184 0x5 0x2 +#define IMX7ULP_PAD_PTA22__TPM0_CH1 0x0058 0x013C 0x6 0x2 +#define IMX7ULP_PAD_PTA22__I2S1_RXD1 0x0058 0x01E8 0x7 0x1 +#define IMX7ULP_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTA23__ADC0_CH9B 0x005C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA23__PTA23 0x005C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA23__FXIO0_D7 0x005C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA23__LPSPI0_PCS3 0x005C 0x010C 0x3 0x2 +#define IMX7ULP_PAD_PTA23__LPUART1_RX 0x005C 0x0208 0x4 0x2 +#define IMX7ULP_PAD_PTA23__TPM0_CH2 0x005C 0x0140 0x6 0x2 +#define IMX7ULP_PAD_PTA23__I2S1_MCLK 0x005C 0x01C8 0x7 0x1 +#define IMX7ULP_PAD_PTA23__LLWU0_P6 0x005C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA24__ADC0_CH8A 0x0060 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA24__LPSPI1_PCS1 0x0060 0x0120 0x3 0x2 +#define IMX7ULP_PAD_PTA24__LPUART2_CTS_B 0x0060 0x0210 0x4 0x2 +#define IMX7ULP_PAD_PTA24__LPI2C2_SCL 0x0060 0x0194 0x5 0x2 +#define IMX7ULP_PAD_PTA24__TPM0_CH3 0x0060 0x0144 0x6 0x2 +#define IMX7ULP_PAD_PTA24__I2S1_TX_BCLK 0x0060 0x01D4 0x7 0x1 +#define IMX7ULP_PAD_PTA25__ADC0_CH8B 0x0064 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA25__LPSPI1_PCS2 0x0064 0x0124 0x3 0x2 +#define IMX7ULP_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA25__LPI2C2_SDA 0x0064 0x0198 0x5 0x2 +#define IMX7ULP_PAD_PTA25__TPM0_CH4 0x0064 0x0148 0x6 0x2 +#define IMX7ULP_PAD_PTA25__I2S1_TX_FS 0x0064 0x01D8 0x7 0x1 +#define IMX7ULP_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA26__LPSPI1_PCS3 0x0068 0x0128 0x3 0x2 +#define IMX7ULP_PAD_PTA26__LPUART2_TX 0x0068 0x0218 0x4 0x2 +#define IMX7ULP_PAD_PTA26__LPI2C2_HREQ 0x0068 0x0190 0x5 0x2 +#define IMX7ULP_PAD_PTA26__TPM0_CH5 0x0068 0x014C 0x6 0x2 +#define IMX7ULP_PAD_PTA26__I2S1_RXD2 0x0068 0x01EC 0x7 0x1 +#define IMX7ULP_PAD_PTA27__PTA27 0x006C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA27__JTAG_TDO 0x006C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTA27__FXIO0_D11 0x006C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA27__LPUART2_RX 0x006C 0x0214 0x4 0x2 +#define IMX7ULP_PAD_PTA27__TPM1_CH1 0x006C 0x0154 0x6 0x2 +#define IMX7ULP_PAD_PTA27__I2S1_RXD3 0x006C 0x01F0 0x7 0x1 +#define IMX7ULP_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA28__LPSPI1_SIN 0x0070 0x0130 0x3 0x2 +#define IMX7ULP_PAD_PTA28__LPUART3_CTS_B 0x0070 0x021C 0x4 0x2 +#define IMX7ULP_PAD_PTA28__LPI2C3_SCL 0x0070 0x01A0 0x5 0x2 +#define IMX7ULP_PAD_PTA28__TPM1_CLKIN 0x0070 0x01AC 0x6 0x2 +#define IMX7ULP_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA29__LPSPI1_SOUT 0x0074 0x0134 0x3 0x1 +#define IMX7ULP_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA29__LPI2C3_SDA 0x0074 0x01A4 0x5 0x1 +#define IMX7ULP_PAD_PTA29__TPM1_CH0 0x0074 0x0150 0x6 0x2 +#define IMX7ULP_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA30__ADC0_CH1A 0x0078 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA30__LPSPI1_SCK 0x0078 0x012C 0x3 0x1 +#define IMX7ULP_PAD_PTA30__LPUART3_TX 0x0078 0x0224 0x4 0x1 +#define IMX7ULP_PAD_PTA30__LPI2C3_HREQ 0x0078 0x019C 0x5 0x1 +#define IMX7ULP_PAD_PTA30__TPM2_CLKIN 0x0078 0x01F4 0x6 0x2 +#define IMX7ULP_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTA31__ADC0_CH1B 0x007C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA31__PTA31 0x007C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA31__FXIO0_D15 0x007C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA31__LPSPI1_PCS0 0x007C 0x011C 0x3 0x2 +#define IMX7ULP_PAD_PTA31__LPUART3_RX 0x007C 0x0220 0x4 0x2 +#define IMX7ULP_PAD_PTA31__TPM2_CH0 0x007C 0x0158 0x6 0x2 +#define IMX7ULP_PAD_PTA31__I2S1_TXD1 0x007C 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA31__LPTMR0_ALT1 0x007C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA31__EWM_IN 0x007C 0x0228 0xc 0x1 +#define IMX7ULP_PAD_PTA31__LLWU0_P7 0x007C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB0__LPSPI0_SIN 0x0080 0x0114 0x3 0x3 +#define IMX7ULP_PAD_PTB0__LPUART0_TX 0x0080 0x0200 0x4 0x3 +#define IMX7ULP_PAD_PTB0__TPM2_CH1 0x0080 0x015C 0x6 0x2 +#define IMX7ULP_PAD_PTB0__CLKOUT0 0x0080 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTB1__ADC0_CH0B 0x0084 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB1__PTB1 0x0084 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB1__FXIO0_D17 0x0084 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB1__LPSPI0_SOUT 0x0084 0x0118 0x3 0x3 +#define IMX7ULP_PAD_PTB1__LPUART0_RX 0x0084 0x01FC 0x4 0x3 +#define IMX7ULP_PAD_PTB1__TPM3_CLKIN 0x0084 0x01B0 0x6 0x3 +#define IMX7ULP_PAD_PTB1__I2S1_TX_BCLK 0x0084 0x01D4 0x7 0x2 +#define IMX7ULP_PAD_PTB1__RTC_CLKOUT 0x0084 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB1__EWM_IN 0x0084 0x0228 0xc 0x2 +#define IMX7ULP_PAD_PTB1__LLWU0_P8 0x0084 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB2__ADC0_CH6A 0x0088 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB2__LPSPI0_SCK 0x0088 0x0110 0x3 0x3 +#define IMX7ULP_PAD_PTB2__LPUART1_TX 0x0088 0x020C 0x4 0x3 +#define IMX7ULP_PAD_PTB2__TPM3_CH0 0x0088 0x0160 0x6 0x2 +#define IMX7ULP_PAD_PTB2__I2S1_TX_FS 0x0088 0x01D8 0x7 0x2 +#define IMX7ULP_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB3__ADC0_CH6B 0x008C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB3__PTB3 0x008C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB3__FXIO0_D19 0x008C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB3__LPSPI0_PCS0 0x008C 0x0100 0x3 0x3 +#define IMX7ULP_PAD_PTB3__LPUART1_RX 0x008C 0x0208 0x4 0x3 +#define IMX7ULP_PAD_PTB3__TPM3_CH1 0x008C 0x0164 0x6 0x2 +#define IMX7ULP_PAD_PTB3__I2S1_TXD0 0x008C 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTB3__TRACE_D0 0x008C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB3__LPTMR1_ALT2 0x008C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB3__LLWU0_P9 0x008C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB4__LPSPI0_PCS1 0x0090 0x0104 0x3 0x3 +#define IMX7ULP_PAD_PTB4__LPUART2_TX 0x0090 0x0218 0x4 0x3 +#define IMX7ULP_PAD_PTB4__LPI2C0_HREQ 0x0090 0x0178 0x5 0x3 +#define IMX7ULP_PAD_PTB4__TPM3_CH2 0x0090 0x0168 0x6 0x2 +#define IMX7ULP_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTB4__QSPIA_DATA7 0x0090 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB4__SEC_VIO_B 0x0090 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB5__LPSPI0_PCS2 0x0094 0x0108 0x3 0x3 +#define IMX7ULP_PAD_PTB5__LPUART2_RX 0x0094 0x0214 0x4 0x3 +#define IMX7ULP_PAD_PTB5__LPI2C1_HREQ 0x0094 0x0184 0x5 0x3 +#define IMX7ULP_PAD_PTB5__TPM3_CH3 0x0094 0x016C 0x6 0x2 +#define IMX7ULP_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTB5__QSPIA_DATA6 0x0094 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB5__RTC_CLKOUT 0x0094 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB6__ADC1_CH1A 0x0098 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB6__PTB6 0x0098 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB6__FXIO0_D22 0x0098 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB6__LPSPI0_PCS3 0x0098 0x010C 0x3 0x3 +#define IMX7ULP_PAD_PTB6__LPUART3_TX 0x0098 0x0224 0x4 0x3 +#define IMX7ULP_PAD_PTB6__LPI2C0_SCL 0x0098 0x017C 0x5 0x3 +#define IMX7ULP_PAD_PTB6__TPM3_CH4 0x0098 0x0170 0x6 0x2 +#define IMX7ULP_PAD_PTB6__I2S1_TXD3 0x0098 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTB6__QSPIA_DATA5 0x0098 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB6__TRACE_D3 0x0098 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB6__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB6__LLWU0_P10 0x0098 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB7__ADC1_CH1B 0x009C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB7__PTB7 0x009C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB7__FXIO0_D23 0x009C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB7__LPSPI1_SIN 0x009C 0x0130 0x3 0x3 +#define IMX7ULP_PAD_PTB7__LPUART3_RX 0x009C 0x0220 0x4 0x3 +#define IMX7ULP_PAD_PTB7__LPI2C0_SDA 0x009C 0x0180 0x5 0x3 +#define IMX7ULP_PAD_PTB7__TPM3_CH5 0x009C 0x0174 0x6 0x2 +#define IMX7ULP_PAD_PTB7__I2S1_MCLK 0x009C 0x01C8 0x7 0x2 +#define IMX7ULP_PAD_PTB7__QSPIA_SS1_B 0x009C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB7__CMP1_OUT 0x009C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB7__LLWU0_P11 0x009C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0 0x00A0 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB8__PTB8 0x00A0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB8__FXIO0_D24 0x00A0 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB8__LPSPI1_SOUT 0x00A0 0x0134 0x3 0x3 +#define IMX7ULP_PAD_PTB8__LPI2C1_SCL 0x00A0 0x0188 0x5 0x3 +#define IMX7ULP_PAD_PTB8__TPM0_CLKIN 0x00A0 0x01A8 0x6 0x3 +#define IMX7ULP_PAD_PTB8__I2S1_RX_BCLK 0x00A0 0x01CC 0x7 0x2 +#define IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x00A0 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB8__RTC_CLKOUT 0x00A0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2 0x00A4 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB9__PTB9 0x00A4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB9__FXIO0_D25 0x00A4 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB9__LPSPI1_SCK 0x00A4 0x012C 0x3 0x3 +#define IMX7ULP_PAD_PTB9__LPI2C1_SDA 0x00A4 0x018C 0x5 0x3 +#define IMX7ULP_PAD_PTB9__TPM0_CH0 0x00A4 0x0138 0x6 0x3 +#define IMX7ULP_PAD_PTB9__I2S1_RX_FS 0x00A4 0x01D0 0x7 0x2 +#define IMX7ULP_PAD_PTB9__QSPIA_DQS 0x00A4 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB9__LLWU0_P12 0x00A4 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB10__CMP0_IN1 0x00A8 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB10__PTB10 0x00A8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB10__FXIO0_D26 0x00A8 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB10__LPSPI1_PCS0 0x00A8 0x011C 0x3 0x3 +#define IMX7ULP_PAD_PTB10__LPI2C2_SCL 0x00A8 0x0194 0x5 0x3 +#define IMX7ULP_PAD_PTB10__TPM0_CH1 0x00A8 0x013C 0x6 0x3 +#define IMX7ULP_PAD_PTB10__I2S1_RXD0 0x00A8 0x01E4 0x7 0x2 +#define IMX7ULP_PAD_PTB10__TRACE_D4 0x00A8 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB11__CMP0_IN3 0x00AC 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB11__PTB11 0x00AC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB11__FXIO0_D27 0x00AC 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB11__LPSPI1_PCS1 0x00AC 0x0120 0x3 0x3 +#define IMX7ULP_PAD_PTB11__LPI2C2_SDA 0x00AC 0x0198 0x5 0x3 +#define IMX7ULP_PAD_PTB11__TPM1_CLKIN 0x00AC 0x01AC 0x6 0x3 +#define IMX7ULP_PAD_PTB11__I2S1_RXD1 0x00AC 0x01E8 0x7 0x2 +#define IMX7ULP_PAD_PTB11__TRACE_D5 0x00AC 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0 0x00B0 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB12__PTB12 0x00B0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB12__FXIO0_D28 0x00B0 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB12__LPSPI1_PCS2 0x00B0 0x0124 0x3 0x3 +#define IMX7ULP_PAD_PTB12__LPUART2_TX 0x00B0 0x0218 0x4 0x4 +#define IMX7ULP_PAD_PTB12__LPI2C3_SCL 0x00B0 0x01A0 0x5 0x3 +#define IMX7ULP_PAD_PTB12__TPM1_CH0 0x00B0 0x0150 0x6 0x3 +#define IMX7ULP_PAD_PTB12__I2S1_RXD2 0x00B0 0x01EC 0x7 0x2 +#define IMX7ULP_PAD_PTB12__TRACE_D6 0x00B0 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1 0x00B4 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB13__PTB13 0x00B4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB13__FXIO0_D29 0x00B4 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB13__LPSPI1_PCS3 0x00B4 0x0128 0x3 0x3 +#define IMX7ULP_PAD_PTB13__LPUART2_RX 0x00B4 0x0214 0x4 0x4 +#define IMX7ULP_PAD_PTB13__LPI2C3_SDA 0x00B4 0x01A4 0x5 0x3 +#define IMX7ULP_PAD_PTB13__TPM1_CH1 0x00B4 0x0154 0x6 0x3 +#define IMX7ULP_PAD_PTB13__I2S1_RXD3 0x00B4 0x01F0 0x7 0x2 +#define IMX7ULP_PAD_PTB13__QSPIA_DATA4 0x00B4 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB13__TRACE_D7 0x00B4 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB14__ADC1_CH2A 0x00B8 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB14__PTB14 0x00B8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB14__FXIO0_D30 0x00B8 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB14__LPI2C2_HREQ 0x00B8 0x0190 0x5 0x3 +#define IMX7ULP_PAD_PTB14__TPM2_CLKIN 0x00B8 0x01F4 0x6 0x3 +#define IMX7ULP_PAD_PTB14__QSPIA_SS1_B 0x00B8 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB14__QSPIA_SCLK_B 0x00B8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTB14__RTC_CLKOUT 0x00B8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB14__LLWU0_P13 0x00B8 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB15__ADC1_CH2B 0x00BC 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB15__PTB15 0x00BC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB15__FXIO0_D31 0x00BC 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB15__LPI2C3_HREQ 0x00BC 0x019C 0x5 0x3 +#define IMX7ULP_PAD_PTB15__TPM2_CH0 0x00BC 0x0158 0x6 0x3 +#define IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x00BC 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB16__ADC0_CH4A 0x00C0 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB16__PTB16 0x00C0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB16__TPM2_CH1 0x00C0 0x015C 0x6 0x3 +#define IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x00C0 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB16__LLWU0_P14 0x00C0 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB17__ADC0_CH4B 0x00C4 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB17__PTB17 0x00C4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB17__TPM3_CLKIN 0x00C4 0x01B0 0x6 0x2 +#define IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x00C4 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB18__ADC0_CH5A 0x00C8 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB18__PTB18 0x00C8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB18__TPM3_CH0 0x00C8 0x0160 0x6 0x3 +#define IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x00C8 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB19__ADC0_CH5B 0x00CC 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB19__PTB19 0x00CC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB19__TPM3_CH1 0x00CC 0x0164 0x6 0x3 +#define IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x00CC 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB19__USB0_ID 0x00CC 0x0338 0xa 0x0 +#define IMX7ULP_PAD_PTB19__LLWU0_P15 0x00CC 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 +#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 +#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 +#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027C 0x5 0x1 +#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 +#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024C 0x4 0x1 +#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 +#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 +#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC3__PTC3 0x000C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000C 0x0248 0x4 0x1 +#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000C 0x0288 0x6 0x1 +#define IMX7ULP_PAD_PTC3__FB_AD3 0x000C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 +#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02A0 0x3 0x1 +#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 +#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02BC 0x5 0x1 +#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028C 0x6 0x1 +#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 +#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02A4 0x3 0x1 +#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02C0 0x5 0x1 +#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 +#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020C 0x2 0x1 +#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02A8 0x3 0x1 +#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 +#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02B8 0x5 0x1 +#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 +#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC7__PTC7 0x001C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001C 0x0210 0x2 0x1 +#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001C 0x0254 0x4 0x1 +#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001C 0x02C8 0x6 0x1 +#define IMX7ULP_PAD_PTC7__FB_AD7 0x001C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 +#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02B0 0x3 0x1 +#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025C 0x4 0x1 +#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02FC 0x5 0x1 +#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02CC 0x6 0x1 +#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 +#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02B4 0x3 0x1 +#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 +#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02C4 0x6 0x1 +#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021C 0x2 0x1 +#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02AC 0x3 0x1 +#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 +#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02F8 0x5 0x1 +#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02E8 0x6 0x1 +#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC11__PTC11 0x002C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002C 0x0220 0x2 0x1 +#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002C 0x029C 0x3 0x1 +#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002C 0x0260 0x4 0x1 +#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002C 0x02EC 0x6 0x1 +#define IMX7ULP_PAD_PTC11__FB_AD11 0x002C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 +#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 +#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 +#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 +#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02F0 0x6 0x1 +#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 +#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 +#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030C 0x5 0x1 +#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02F4 0x6 0x1 +#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1 +#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022C 0x2 0x1 +#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031C 0x3 0x1 +#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 +#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 +#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02DC 0x6 0x1 +#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC15__PTC15 0x003C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003C 0x0230 0x2 0x1 +#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003C 0x026C 0x4 0x1 +#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003C 0x02E0 0x6 0x1 +#define IMX7ULP_PAD_PTC15__FB_AD15 0x003C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 +#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 +#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02E4 0x6 0x1 +#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1 +#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 +#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 +#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02D8 0x6 0x1 +#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023C 0x2 0x1 +#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 +#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02D0 0x6 0x1 +#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2 +#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033C 0xc 0x1 +#define IMX7ULP_PAD_PTC19__PTC19 0x004C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004C 0x0240 0x2 0x1 +#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004C 0x0310 0x3 0x1 +#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004C 0x02D4 0x6 0x1 +#define IMX7ULP_PAD_PTC19__FB_A16 0x004C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC19__USB0_ID 0x004C 0x0338 0xa 0x3 +#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTC19__VIU_DE 0x004C 0x033C 0xc 0x3 +#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD3__PTD3 0x008C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD7__PTD7 0x009C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD8__PTD8 0x00A0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00A0 0x0298 0x6 0x2 +#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00A0 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD9__PTD9 0x00A4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00A4 0x0280 0x6 0x2 +#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00A4 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD10__PTD10 0x00A8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00A8 0x0284 0x6 0x2 +#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00A8 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD11__PTD11 0x00AC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00AC 0x0288 0x6 0x2 +#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00AC 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02A0 0x3 0x2 +#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 +#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 +#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02A4 0x3 0x2 +#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027C 0x5 0x2 +#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02A8 0x3 0x2 +#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024C 0x4 0x2 +#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 +#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE3__PTE3 0x010C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010C 0x0248 0x4 0x2 +#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010C 0x02C8 0x6 0x2 +#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02B0 0x3 0x2 +#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 +#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02BC 0x5 0x2 +#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02CC 0x6 0x2 +#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02B4 0x3 0x2 +#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02C0 0x5 0x2 +#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02C4 0x6 0x2 +#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033C 0xc 0x2 +#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02AC 0x3 0x2 +#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 +#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02B8 0x5 0x2 +#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02E8 0x6 0x2 +#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1 +#define IMX7ULP_PAD_PTE7__PTE7 0x011C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011C 0x029C 0x3 0x2 +#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011C 0x0254 0x4 0x2 +#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011C 0x02EC 0x6 0x2 +#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE7__FB_A18 0x011C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE7__VIU_FID 0x011C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 +#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025C 0x4 0x2 +#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02FC 0x5 0x2 +#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02F0 0x6 0x2 +#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 +#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 +#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 +#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02F4 0x6 0x2 +#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032C 0x7 0x1 +#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031C 0x3 0x2 +#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 +#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02F8 0x5 0x2 +#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02DC 0x6 0x2 +#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE11__PTE11 0x012C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE11__VIU_D19 0x012C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012C 0x0260 0x4 0x2 +#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012C 0x02E0 0x6 0x2 +#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE11__FB_A20 0x012C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 +#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 +#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 +#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02E4 0x6 0x2 +#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 +#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2 +#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 +#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030C 0x5 0x2 +#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02D8 0x6 0x2 +#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032C 0x8 0x2 +#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 +#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 +#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 +#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02D0 0x6 0x2 +#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2 +#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE15__PTE15 0x013C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013C 0x0310 0x3 0x2 +#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013C 0x026C 0x4 0x2 +#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013C 0x02D4 0x6 0x2 +#define IMX7ULP_PAD_PTE15__FB_A24 0x013C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE15__VIU_D23 0x013C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 +#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 +#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 +#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033C 0xc 0x0 +#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027C 0x5 0x3 +#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 +#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024C 0x4 0x3 +#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 +#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 +#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF3__PTF3 0x018C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018C 0x0248 0x4 0x3 +#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018C 0x0288 0x6 0x3 +#define IMX7ULP_PAD_PTF3__FB_AD16 0x018C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 +#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02A0 0x3 0x3 +#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 +#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02BC 0x5 0x3 +#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028C 0x6 0x2 +#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 +#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02A4 0x3 0x3 +#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02C0 0x5 0x3 +#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 +#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020C 0x2 0x2 +#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02A8 0x3 0x3 +#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 +#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02B8 0x5 0x3 +#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 +#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF7__PTF7 0x019C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019C 0x0210 0x2 0x2 +#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019C 0x0254 0x4 0x3 +#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019C 0x02C8 0x6 0x3 +#define IMX7ULP_PAD_PTF7__FB_AD20 0x019C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF7__VIU_D3 0x019C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF8__PTF8 0x01A0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01A0 0x0214 0x2 0x2 +#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01A0 0x02B0 0x3 0x3 +#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01A0 0x025C 0x4 0x3 +#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01A0 0x02FC 0x5 0x3 +#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01A0 0x02CC 0x6 0x3 +#define IMX7ULP_PAD_PTF8__FB_AD21 0x01A0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF8__USB1_CLK 0x01A0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF8__VIU_D4 0x01A0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF9__PTF9 0x01A4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01A4 0x0218 0x2 0x2 +#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01A4 0x02B4 0x3 0x3 +#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01A4 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01A4 0x0300 0x5 0x3 +#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01A4 0x02C4 0x6 0x3 +#define IMX7ULP_PAD_PTF9__FB_AD22 0x01A4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF9__USB1_NXT 0x01A4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF9__VIU_D5 0x01A4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF10__PTF10 0x01A8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01A8 0x021C 0x2 0x2 +#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01A8 0x02AC 0x3 0x3 +#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01A8 0x0264 0x4 0x3 +#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01A8 0x02F8 0x5 0x3 +#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01A8 0x02E8 0x6 0x3 +#define IMX7ULP_PAD_PTF10__FB_AD23 0x01A8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF10__USB1_STP 0x01A8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF10__VIU_D6 0x01A8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF11__PTF11 0x01AC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01AC 0x0220 0x2 0x2 +#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01AC 0x029C 0x3 0x3 +#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01AC 0x0260 0x4 0x3 +#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01AC 0x02EC 0x6 0x3 +#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01AC 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF11__USB1_DIR 0x01AC 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF11__VIU_D7 0x01AC 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF12__PTF12 0x01B0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01B0 0x0224 0x2 0x2 +#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01B0 0x0314 0x3 0x3 +#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01B0 0x0268 0x4 0x3 +#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01B0 0x0308 0x5 0x3 +#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01B0 0x02F0 0x6 0x3 +#define IMX7ULP_PAD_PTF12__FB_AD24 0x01B0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF12__USB1_DATA0 0x01B0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF12__VIU_D8 0x01B0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF13__PTF13 0x01B4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01B4 0x0228 0x2 0x2 +#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01B4 0x0318 0x3 0x3 +#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01B4 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01B4 0x030C 0x5 0x3 +#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01B4 0x02F4 0x6 0x3 +#define IMX7ULP_PAD_PTF13__FB_AD25 0x01B4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF13__USB1_DATA1 0x01B4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF13__VIU_D9 0x01B4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF14__PTF14 0x01B8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01B8 0x022C 0x2 0x2 +#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01B8 0x031C 0x3 0x3 +#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01B8 0x0270 0x4 0x3 +#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01B8 0x0304 0x5 0x3 +#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01B8 0x02DC 0x6 0x3 +#define IMX7ULP_PAD_PTF14__FB_AD26 0x01B8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF14__USB1_DATA2 0x01B8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF14__VIU_D10 0x01B8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF15__PTF15 0x01BC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01BC 0x0230 0x2 0x2 +#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01BC 0x026C 0x4 0x3 +#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01BC 0x02E0 0x6 0x3 +#define IMX7ULP_PAD_PTF15__FB_AD27 0x01BC 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF15__USB1_DATA3 0x01BC 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF15__VIU_D11 0x01BC 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF16__PTF16 0x01C0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF16__USB1_DATA4 0x01C0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF16__VIU_D12 0x01C0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01C0 0x0234 0x2 0x2 +#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01C0 0x0324 0x3 0x3 +#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01C0 0x02E4 0x6 0x3 +#define IMX7ULP_PAD_PTF16__FB_AD28 0x01C0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF17__PTF17 0x01C4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF17__USB1_DATA5 0x01C4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF17__VIU_D13 0x01C4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01C4 0x0238 0x2 0x2 +#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01C4 0x0328 0x3 0x3 +#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01C4 0x02D8 0x6 0x3 +#define IMX7ULP_PAD_PTF17__FB_AD29 0x01C4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF18__PTF18 0x01C8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF18__USB1_DATA6 0x01C8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF18__VIU_D14 0x01C8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01C8 0x023C 0x2 0x2 +#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01C8 0x0320 0x3 0x3 +#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01C8 0x02D0 0x6 0x3 +#define IMX7ULP_PAD_PTF18__FB_AD30 0x01C8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF19__PTF19 0x01CC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF19__USB1_DATA7 0x01CC 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF19__VIU_D15 0x01CC 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01CC 0x0240 0x2 0x2 +#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01CC 0x0310 0x3 0x3 +#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01CC 0x02D4 0x6 0x3 +#define IMX7ULP_PAD_PTF19__FB_AD31 0x01CC 0x0000 0x9 0x0 -#define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0 -#define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0 -#define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0 -#define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2 -#define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2 -#define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2 -#define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2 -#define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2 -#define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0 -#define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0 -#define ULP1_PAD_PTA1__LPSPI0_PCS2 0x0004 0xd108 0x3 0x1 -#define ULP1_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0 -#define ULP1_PAD_PTA1__LPI2C0_SDA 0x0004 0xd180 0x5 0x1 -#define ULP1_PAD_PTA1__TPM0_CH0 0x0004 0xd138 0x6 0x1 -#define ULP1_PAD_PTA1__I2S0_RX_FS 0x0004 0x01bc 0x7 0x1 -#define ULP1_PAD_PTA2__CMP1_IN2A 0x0008 0x0000 0x0 0x0 -#define ULP1_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0 -#define ULP1_PAD_PTA2__LPSPI0_PCS3 0x0008 0xd10c 0x3 0x1 -#define ULP1_PAD_PTA2__LPUART0_TX 0x0008 0xd200 0x4 0x1 -#define ULP1_PAD_PTA2__LPI2C0_HREQ 0x0008 0xd178 0x5 0x1 -#define ULP1_PAD_PTA2__TPM0_CH1 0x0008 0xd13c 0x6 0x1 -#define ULP1_PAD_PTA2__I2S0_RXD0 0x0008 0x01dc 0x7 0x1 -#define ULP1_PAD_PTA3_LLWU0_P1__CMP1_IN2B 0x000c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA3_LLWU0_P1__PTA3 0x000c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA3_LLWU0_P1__CMP0_OUT 0x000c 0x0000 0xb 0x0 -#define ULP1_PAD_PTA3_LLWU0_P1__LLWU0_P1 0x000c 0x0000 0xd 0x0 -#define ULP1_PAD_PTA3_LLWU0_P1__LPUART0_RX 0x000c 0xd1fc 0x4 0x1 -#define ULP1_PAD_PTA3_LLWU0_P1__TPM0_CH2 0x000c 0xd140 0x6 0x1 -#define ULP1_PAD_PTA3_LLWU0_P1__I2S0_RXD1 0x000c 0x01e0 0x7 0x1 -#define ULP1_PAD_PTA4__ADC1_CH2A 0x0010 0x0000 0x0 0x0 -#define ULP1_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0 -#define ULP1_PAD_PTA4__LPSPI0_SIN 0x0010 0xd114 0x3 0x1 -#define ULP1_PAD_PTA4__LPUART1_CTS_B 0x0010 0xd204 0x4 0x1 -#define ULP1_PAD_PTA4__LPI2C1_SCL 0x0010 0xd188 0x5 0x1 -#define ULP1_PAD_PTA4__TPM0_CH3 0x0010 0xd144 0x6 0x1 -#define ULP1_PAD_PTA4__I2S0_MCLK 0x0010 0x01b4 0x7 0x1 -#define ULP1_PAD_PTA5__ADC1_CH2B 0x0014 0x0000 0x0 0x0 -#define ULP1_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0 -#define ULP1_PAD_PTA5__LPSPI0_SOUT 0x0014 0xd118 0x3 0x1 -#define ULP1_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0 -#define ULP1_PAD_PTA5__LPI2C1_SDA 0x0014 0xd18c 0x5 0x1 -#define ULP1_PAD_PTA5__TPM0_CH4 0x0014 0xd148 0x6 0x1 -#define ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01c0 0x7 0x1 -#define ULP1_PAD_PTA6__ADC1_CH3A 0x0018 0x0000 0x0 0x0 -#define ULP1_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0 -#define ULP1_PAD_PTA6__LPSPI0_SCK 0x0018 0xd110 0x3 0x1 -#define ULP1_PAD_PTA6__LPUART1_TX 0x0018 0xd20c 0x4 0x1 -#define ULP1_PAD_PTA6__LPI2C1_HREQ 0x0018 0xd184 0x5 0x1 -#define ULP1_PAD_PTA6__TPM0_CH5 0x0018 0xd14c 0x6 0x1 -#define ULP1_PAD_PTA6__I2S0_TX_FS 0x0018 0x01c4 0x7 0x1 -#define ULP1_PAD_PTA7__ADC1_CH3B 0x001c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA7__PTA7 0x001c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA7__LPSPI0_PCS0 0x001c 0xd100 0x3 0x1 -#define ULP1_PAD_PTA7__LPUART1_RX 0x001c 0xd208 0x4 0x1 -#define ULP1_PAD_PTA7__TPM1_CH1 0x001c 0xd154 0x6 0x1 -#define ULP1_PAD_PTA7__I2S0_TXD0 0x001c 0x0000 0x7 0x0 -#define ULP1_PAD_PTA8__ADC1_CH7A 0x0020 0x0000 0x0 0x0 -#define ULP1_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0 -#define ULP1_PAD_PTA8__LPSPI1_PCS1 0x0020 0xd120 0x3 0x1 -#define ULP1_PAD_PTA8__LPUART2_CTS_B 0x0020 0xd210 0x4 0x1 -#define ULP1_PAD_PTA8__LPI2C2_SCL 0x0020 0xd194 0x5 0x1 -#define ULP1_PAD_PTA8__TPM1_CLKIN 0x0020 0xd1ac 0x6 0x1 -#define ULP1_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0 -#define ULP1_PAD_PTA9__ADC1_CH7B 0x0024 0x0000 0x0 0x0 -#define ULP1_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0 -#define ULP1_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0 -#define ULP1_PAD_PTA9__LPSPI1_PCS2 0x0024 0xd124 0x3 0x1 -#define ULP1_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0 -#define ULP1_PAD_PTA9__LPI2C2_SDA 0x0024 0xd198 0x5 0x1 -#define ULP1_PAD_PTA9__TPM1_CH0 0x0024 0xd150 0x6 0x1 -#define ULP1_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0 -#define ULP1_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0 -#define ULP1_PAD_PTA10__LPSPI1_PCS3 0x0028 0xd128 0x3 0x1 -#define ULP1_PAD_PTA10__LPUART2_TX 0x0028 0xd218 0x4 0x1 -#define ULP1_PAD_PTA10__LPI2C2_HREQ 0x0028 0xd190 0x5 0x1 -#define ULP1_PAD_PTA10__TPM2_CLKIN 0x0028 0xd1f4 0x6 0x1 -#define ULP1_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01b8 0x7 0x1 -#define ULP1_PAD_PTA11__ADC1_CH6B 0x002c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA11__PTA11 0x002c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA11__LPUART2_RX 0x002c 0xd214 0x4 0x1 -#define ULP1_PAD_PTA11__TPM2_CH0 0x002c 0xd158 0x6 0x1 -#define ULP1_PAD_PTA11__I2S0_RX_FS 0x002c 0x01bc 0x7 0x2 -#define ULP1_PAD_PTA12__ADC1_CH5A 0x0030 0x0000 0x0 0x0 -#define ULP1_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0 -#define ULP1_PAD_PTA12__LPSPI1_SIN 0x0030 0xd130 0x3 0x1 -#define ULP1_PAD_PTA12__LPUART3_CTS_B 0x0030 0xd21c 0x4 0x1 -#define ULP1_PAD_PTA12__LPI2C3_SCL 0x0030 0xd1a0 0x5 0x1 -#define ULP1_PAD_PTA12__TPM2_CH1 0x0030 0xd15c 0x6 0x1 -#define ULP1_PAD_PTA12__I2S0_RXD0 0x0030 0x01dc 0x7 0x2 -#define ULP1_PAD_PTA13_LLWU0_P2__ADC1_CH5B 0x0034 0x0000 0x0 0x0 -#define ULP1_PAD_PTA13_LLWU0_P2__PTA13 0x0034 0x0000 0x1 0x0 -#define ULP1_PAD_PTA13_LLWU0_P2__CMP0_OUT 0x0034 0x0000 0xb 0x0 -#define ULP1_PAD_PTA13_LLWU0_P2__LLWU0_P2 0x0034 0x0000 0xd 0x0 -#define ULP1_PAD_PTA13_LLWU0_P2__LPSPI1_SOUT 0x0034 0xd134 0x3 0x2 -#define ULP1_PAD_PTA13_LLWU0_P2__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0 -#define ULP1_PAD_PTA13_LLWU0_P2__LPI2C3_SDA 0x0034 0xd1a4 0x5 0x2 -#define ULP1_PAD_PTA13_LLWU0_P2__TPM3_CLKIN 0x0034 0xd1b0 0x6 0x1 -#define ULP1_PAD_PTA13_LLWU0_P2__I2S0_RXD1 0x0034 0x01e0 0x7 0x2 -#define ULP1_PAD_PTA14_LLWU0_P3__ADC1_CH4A 0x0038 0x0000 0x0 0x0 -#define ULP1_PAD_PTA14_LLWU0_P3__PTA14 0x0038 0x0000 0x1 0x0 -#define ULP1_PAD_PTA14_LLWU0_P3__LLWU0_P3 0x0038 0x0000 0xd 0x0 -#define ULP1_PAD_PTA14_LLWU0_P3__LPSPI1_SCK 0x0038 0xd12c 0x3 0x2 -#define ULP1_PAD_PTA14_LLWU0_P3__LPUART3_TX 0x0038 0xd224 0x4 0x2 -#define ULP1_PAD_PTA14_LLWU0_P3__LPI2C3_HREQ 0x0038 0xd19c 0x5 0x2 -#define ULP1_PAD_PTA14_LLWU0_P3__TPM3_CH0 0x0038 0xd160 0x6 0x1 -#define ULP1_PAD_PTA14_LLWU0_P3__I2S0_MCLK 0x0038 0x01b4 0x7 0x2 -#define ULP1_PAD_PTA15__ADC1_CH4B 0x003c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA15__PTA15 0x003c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA15__LPSPI1_PCS0 0x003c 0xd11c 0x3 0x1 -#define ULP1_PAD_PTA15__LPUART3_RX 0x003c 0xd220 0x4 0x1 -#define ULP1_PAD_PTA15__TPM3_CH1 0x003c 0xd164 0x6 0x1 -#define ULP1_PAD_PTA15__I2S0_TX_BCLK 0x003c 0x01c0 0x7 0x2 -#define ULP1_PAD_PTA16__CMP1_IN0A 0x0040 0x0000 0x0 0x0 -#define ULP1_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0 -#define ULP1_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0 -#define ULP1_PAD_PTA16__LPSPI0_PCS1 0x0040 0xd104 0x3 0x1 -#define ULP1_PAD_PTA16__LPUART0_CTS_B 0x0040 0xd1f8 0x4 0x1 -#define ULP1_PAD_PTA16__LPI2C0_SCL 0x0040 0xd17c 0x5 0x1 -#define ULP1_PAD_PTA16__TPM3_CH2 0x0040 0xd168 0x6 0x1 -#define ULP1_PAD_PTA16__I2S0_TX_FS 0x0040 0x01c4 0x7 0x2 -#define ULP1_PAD_PTA17__CMP1_IN0B 0x0044 0x0000 0x0 0x0 -#define ULP1_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0 -#define ULP1_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0 -#define ULP1_PAD_PTA17__LPSPI0_PCS2 0x0044 0xd108 0x3 0x2 -#define ULP1_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0 -#define ULP1_PAD_PTA17__LPI2C0_SDA 0x0044 0xd180 0x5 0x2 -#define ULP1_PAD_PTA17__TPM3_CH3 0x0044 0xd16c 0x6 0x1 -#define ULP1_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__CMP1_IN1A 0x0048 0x0000 0x0 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__PTA18 0x0048 0x0000 0x1 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__NMI1_B 0x0048 0x0000 0xb 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__LLWU0_P4 0x0048 0x0000 0xd 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__FXIO0_D2 0x0048 0x0000 0x2 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__LPSPI0_PCS3 0x0048 0xd10c 0x3 0x2 -#define ULP1_PAD_PTA18_LLWU0_P4__LPUART0_TX 0x0048 0xd200 0x4 0x2 -#define ULP1_PAD_PTA18_LLWU0_P4__LPI2C0_HREQ 0x0048 0xd178 0x5 0x2 -#define ULP1_PAD_PTA18_LLWU0_P4__TPM3_CH4 0x0048 0xd170 0x6 0x1 -#define ULP1_PAD_PTA18_LLWU0_P4__I2S0_TXD1 0x0048 0x0000 0x7 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__CMP1_IN1B 0x004c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__PTA19 0x004c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__LPTMR0_ALT3 0x004c 0x0000 0xb 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__LLWU0_P5 0x004c 0x0000 0xd 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__FXIO0_D3 0x004c 0x0000 0x2 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__LPUART0_RX 0x004c 0xd1fc 0x4 0x2 -#define ULP1_PAD_PTA19_LLWU0_P5__TPM3_CH5 0x004c 0xd174 0x6 0x1 -#define ULP1_PAD_PTA19_LLWU0_P5__I2S1_RX_BCLK 0x004c 0xd1cc 0x7 0x1 -#define ULP1_PAD_PTA20__ADC0_CH7A 0x0050 0x0000 0x0 0x0 -#define ULP1_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0 -#define ULP1_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0 -#define ULP1_PAD_PTA20__LPSPI0_SIN 0x0050 0xd114 0x3 0x2 -#define ULP1_PAD_PTA20__LPUART1_CTS_B 0x0050 0xd204 0x4 0x2 -#define ULP1_PAD_PTA20__LPI2C1_SCL 0x0050 0xd188 0x5 0x2 -#define ULP1_PAD_PTA20__TPM0_CLKIN 0x0050 0xd1a8 0x6 0x1 -#define ULP1_PAD_PTA20__I2S1_RX_FS 0x0050 0xd1d0 0x7 0x1 -#define ULP1_PAD_PTA21__ADC0_CH7B 0x0054 0x0000 0x0 0x0 -#define ULP1_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0 -#define ULP1_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0 -#define ULP1_PAD_PTA21__LPSPI0_SOUT 0x0054 0xd118 0x3 0x2 -#define ULP1_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0 -#define ULP1_PAD_PTA21__LPI2C1_SDA 0x0054 0xd18c 0x5 0x2 -#define ULP1_PAD_PTA21__TPM0_CH0 0x0054 0xd138 0x6 0x2 -#define ULP1_PAD_PTA21__I2S1_RXD0 0x0054 0xd1e4 0x7 0x1 -#define ULP1_PAD_PTA22__ADC0_CH6A 0x0058 0x0000 0x0 0x0 -#define ULP1_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0 -#define ULP1_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0 -#define ULP1_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0 -#define ULP1_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0 -#define ULP1_PAD_PTA22__LPSPI0_SCK 0x0058 0xd110 0x3 0x2 -#define ULP1_PAD_PTA22__LPUART1_TX 0x0058 0xd20c 0x4 0x2 -#define ULP1_PAD_PTA22__LPI2C1_HREQ 0x0058 0xd184 0x5 0x2 -#define ULP1_PAD_PTA22__TPM0_CH1 0x0058 0xd13c 0x6 0x2 -#define ULP1_PAD_PTA22__I2S1_RXD1 0x0058 0xd1e8 0x7 0x1 -#define ULP1_PAD_PTA23_LLWU0_P6__ADC0_CH6B 0x005c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA23_LLWU0_P6__PTA23 0x005c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA23_LLWU0_P6__LLWU0_P6 0x005c 0x0000 0xd 0x0 -#define ULP1_PAD_PTA23_LLWU0_P6__FXIO0_D7 0x005c 0x0000 0x2 0x0 -#define ULP1_PAD_PTA23_LLWU0_P6__LPSPI0_PCS0 0x005c 0xd100 0x3 0x2 -#define ULP1_PAD_PTA23_LLWU0_P6__LPUART1_RX 0x005c 0xd208 0x4 0x2 -#define ULP1_PAD_PTA23_LLWU0_P6__TPM0_CH2 0x005c 0xd140 0x6 0x2 -#define ULP1_PAD_PTA23_LLWU0_P6__I2S1_MCLK 0x005c 0xd1c8 0x7 0x1 -#define ULP1_PAD_PTA24__ADC0_CH5A 0x0060 0x0000 0x0 0x0 -#define ULP1_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0 -#define ULP1_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0 -#define ULP1_PAD_PTA24__LPSPI1_PCS1 0x0060 0xd120 0x3 0x2 -#define ULP1_PAD_PTA24__LPUART2_CTS_B 0x0060 0xd210 0x4 0x2 -#define ULP1_PAD_PTA24__LPI2C2_SCL 0x0060 0xd194 0x5 0x2 -#define ULP1_PAD_PTA24__TPM0_CH3 0x0060 0xd144 0x6 0x2 -#define ULP1_PAD_PTA24__I2S1_TX_BCLK 0x0060 0xd1d4 0x7 0x1 -#define ULP1_PAD_PTA25__ADC0_CH5B 0x0064 0x0000 0x0 0x0 -#define ULP1_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0 -#define ULP1_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0 -#define ULP1_PAD_PTA25__LPSPI1_PCS2 0x0064 0xd124 0x3 0x2 -#define ULP1_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0 -#define ULP1_PAD_PTA25__LPI2C2_SDA 0x0064 0xd198 0x5 0x2 -#define ULP1_PAD_PTA25__TPM0_CH4 0x0064 0xd148 0x6 0x2 -#define ULP1_PAD_PTA25__I2S1_TX_FS 0x0064 0xd1d8 0x7 0x1 -#define ULP1_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0 -#define ULP1_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0 -#define ULP1_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0 -#define ULP1_PAD_PTA26__LPSPI1_PCS3 0x0068 0xd128 0x3 0x2 -#define ULP1_PAD_PTA26__LPUART2_TX 0x0068 0xd218 0x4 0x2 -#define ULP1_PAD_PTA26__LPI2C2_HREQ 0x0068 0xd190 0x5 0x2 -#define ULP1_PAD_PTA26__TPM0_CH5 0x0068 0xd14c 0x6 0x2 -#define ULP1_PAD_PTA26__I2S1_RXD2 0x0068 0xd1ec 0x7 0x1 -#define ULP1_PAD_PTA27__PTA27 0x006c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA27__JTAG_TDO 0x006c 0x0000 0xa 0x0 -#define ULP1_PAD_PTA27__FXIO0_D11 0x006c 0x0000 0x2 0x0 -#define ULP1_PAD_PTA27__LPUART2_RX 0x006c 0xd214 0x4 0x2 -#define ULP1_PAD_PTA27__TPM1_CH1 0x006c 0xd154 0x6 0x2 -#define ULP1_PAD_PTA27__I2S1_RXD3 0x006c 0xd1f0 0x7 0x1 -#define ULP1_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0 -#define ULP1_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0 -#define ULP1_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0 -#define ULP1_PAD_PTA28__LPSPI1_SIN 0x0070 0xd130 0x3 0x2 -#define ULP1_PAD_PTA28__LPUART3_CTS_B 0x0070 0xd21c 0x4 0x2 -#define ULP1_PAD_PTA28__LPI2C3_SCL 0x0070 0xd1a0 0x5 0x2 -#define ULP1_PAD_PTA28__TPM1_CLKIN 0x0070 0xd1ac 0x6 0x2 -#define ULP1_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0 -#define ULP1_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0 -#define ULP1_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0 -#define ULP1_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0 -#define ULP1_PAD_PTA29__LPSPI1_SOUT 0x0074 0xd134 0x3 0x1 -#define ULP1_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0 -#define ULP1_PAD_PTA29__LPI2C3_SDA 0x0074 0xd1a4 0x5 0x1 -#define ULP1_PAD_PTA29__TPM1_CH0 0x0074 0xd150 0x6 0x2 -#define ULP1_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0 -#define ULP1_PAD_PTA30__ADC0_CH4A 0x0078 0x0000 0x0 0x0 -#define ULP1_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0 -#define ULP1_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0 -#define ULP1_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0 -#define ULP1_PAD_PTA30__LPSPI1_SCK 0x0078 0xd12c 0x3 0x1 -#define ULP1_PAD_PTA30__LPUART3_TX 0x0078 0xd224 0x4 0x1 -#define ULP1_PAD_PTA30__LPI2C3_HREQ 0x0078 0xd19c 0x5 0x1 -#define ULP1_PAD_PTA30__TPM2_CLKIN 0x0078 0xd1f4 0x6 0x2 -#define ULP1_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__ADC0_CH4B 0x007c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__PTA31 0x007c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__LPTMR0_ALT1 0x007c 0x0000 0xb 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__EWM_IN 0x007c 0xd228 0xc 0x1 -#define ULP1_PAD_PTA31_LLWU0_P7__LLWU0_P7 0x007c 0x0000 0xd 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__FXIO0_D15 0x007c 0x0000 0x2 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__LPSPI1_PCS0 0x007c 0xd11c 0x3 0x2 -#define ULP1_PAD_PTA31_LLWU0_P7__LPUART3_RX 0x007c 0xd220 0x4 0x2 -#define ULP1_PAD_PTA31_LLWU0_P7__TPM2_CH0 0x007c 0xd158 0x6 0x2 -#define ULP1_PAD_PTA31_LLWU0_P7__I2S1_TXD1 0x007c 0x0000 0x7 0x0 -#define ULP1_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0 -#define ULP1_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0 -#define ULP1_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0 -#define ULP1_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0 -#define ULP1_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0 -#define ULP1_PAD_PTB0__LPSPI0_SIN 0x0080 0xd114 0x3 0x3 -#define ULP1_PAD_PTB0__LPUART0_TX 0x0080 0xd200 0x4 0x3 -#define ULP1_PAD_PTB0__TPM2_CH1 0x0080 0xd15c 0x6 0x2 -#define ULP1_PAD_PTB0__CLKOUT 0x0080 0x0000 0x9 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__ADC0_CH0B 0x0084 0x0000 0x0 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__PTB1 0x0084 0x0000 0x1 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__RTC_CLKOUT 0x0084 0x0000 0xb 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__EWM_IN 0x0084 0xd228 0xc 0x2 -#define ULP1_PAD_PTB1_LLWU0_P8__LLWU0_P8 0x0084 0x0000 0xd 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__FXIO0_D17 0x0084 0x0000 0x2 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__LPSPI0_SOUT 0x0084 0xd118 0x3 0x3 -#define ULP1_PAD_PTB1_LLWU0_P8__LPUART0_RX 0x0084 0xd1fc 0x4 0x3 -#define ULP1_PAD_PTB1_LLWU0_P8__TPM3_CLKIN 0x0084 0xd1b0 0x6 0x3 -#define ULP1_PAD_PTB1_LLWU0_P8__I2S1_TX_BCLK 0x0084 0xd1d4 0x7 0x2 -#define ULP1_PAD_PTB2__ADC0_CH1A 0x0088 0x0000 0x0 0x0 -#define ULP1_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0 -#define ULP1_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0 -#define ULP1_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0 -#define ULP1_PAD_PTB2__LPSPI0_SCK 0x0088 0xd110 0x3 0x3 -#define ULP1_PAD_PTB2__LPUART1_TX 0x0088 0xd20c 0x4 0x3 -#define ULP1_PAD_PTB2__TPM3_CH0 0x0088 0xd160 0x6 0x2 -#define ULP1_PAD_PTB2__I2S1_TX_FS 0x0088 0xd1d8 0x7 0x2 -#define ULP1_PAD_PTB3_LLWU0_P9__ADC0_CH1B 0x008c 0x0000 0x0 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__PTB3 0x008c 0x0000 0x1 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__TRACE_D0 0x008c 0x0000 0xa 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__LPTMR1_ALT2 0x008c 0x0000 0xb 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__LLWU0_P9 0x008c 0x0000 0xd 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__FXIO0_D19 0x008c 0x0000 0x2 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__LPSPI0_PCS0 0x008c 0xd100 0x3 0x3 -#define ULP1_PAD_PTB3_LLWU0_P9__LPUART1_RX 0x008c 0xd208 0x4 0x3 -#define ULP1_PAD_PTB3_LLWU0_P9__TPM3_CH1 0x008c 0xd164 0x6 0x2 -#define ULP1_PAD_PTB3_LLWU0_P9__I2S1_TXD0 0x008c 0x0000 0x7 0x0 -#define ULP1_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0 -#define ULP1_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0 -#define ULP1_PAD_PTB4__BOOTCFG0 0x0090 0x0000 0xd 0x0 -#define ULP1_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0 -#define ULP1_PAD_PTB4__LPSPI0_PCS1 0x0090 0xd104 0x3 0x3 -#define ULP1_PAD_PTB4__LPUART2_TX 0x0090 0xd218 0x4 0x3 -#define ULP1_PAD_PTB4__LPI2C0_HREQ 0x0090 0xd178 0x5 0x3 -#define ULP1_PAD_PTB4__TPM3_CH2 0x0090 0xd168 0x6 0x2 -#define ULP1_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0 -#define ULP1_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0 -#define ULP1_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0 -#define ULP1_PAD_PTB5__BOOTCFG1 0x0094 0x0000 0xd 0x0 -#define ULP1_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0 -#define ULP1_PAD_PTB5__LPSPI0_PCS2 0x0094 0xd108 0x3 0x3 -#define ULP1_PAD_PTB5__LPUART2_RX 0x0094 0xd214 0x4 0x3 -#define ULP1_PAD_PTB5__LPI2C1_HREQ 0x0094 0xd184 0x5 0x3 -#define ULP1_PAD_PTB5__TPM3_CH3 0x0094 0xd16c 0x6 0x2 -#define ULP1_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__PTB6 0x0098 0x0000 0x1 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__TRACE_D3 0x0098 0x0000 0xa 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__LLWU0_P10 0x0098 0x0000 0xd 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__FXIO0_D22 0x0098 0x0000 0x2 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__LPSPI0_PCS3 0x0098 0xd10c 0x3 0x3 -#define ULP1_PAD_PTB6_LLWU0_P10__LPUART3_TX 0x0098 0xd224 0x4 0x3 -#define ULP1_PAD_PTB6_LLWU0_P10__LPI2C0_SCL 0x0098 0xd17c 0x5 0x3 -#define ULP1_PAD_PTB6_LLWU0_P10__TPM3_CH4 0x0098 0xd170 0x6 0x2 -#define ULP1_PAD_PTB6_LLWU0_P10__I2S1_TXD3 0x0098 0x0000 0x7 0x0 -#define ULP1_PAD_PTB7_LLWU0_P11__PTB7 0x009c 0x0000 0x1 0x0 -#define ULP1_PAD_PTB7_LLWU0_P11__CMP1_OUT 0x009c 0x0000 0xb 0x0 -#define ULP1_PAD_PTB7_LLWU0_P11__LLWU0_P11 0x009c 0x0000 0xd 0x0 -#define ULP1_PAD_PTB7_LLWU0_P11__FXIO0_D23 0x009c 0x0000 0x2 0x0 -#define ULP1_PAD_PTB7_LLWU0_P11__LPSPI1_SIN 0x009c 0xd130 0x3 0x3 -#define ULP1_PAD_PTB7_LLWU0_P11__LPUART3_RX 0x009c 0xd220 0x4 0x3 -#define ULP1_PAD_PTB7_LLWU0_P11__LPI2C0_SDA 0x009c 0xd180 0x5 0x3 -#define ULP1_PAD_PTB7_LLWU0_P11__TPM3_CH5 0x009c 0xd174 0x6 0x2 -#define ULP1_PAD_PTB7_LLWU0_P11__I2S1_MCLK 0x009c 0xd1c8 0x7 0x2 -#define ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x009c 0x0000 0x8 0x0 -#define ULP1_PAD_PTB8__CMP0_IN0A 0x00a0 0x0000 0x0 0x0 -#define ULP1_PAD_PTB8__PTB8 0x00a0 0x0000 0x1 0x0 -#define ULP1_PAD_PTB8__RTC_CLKOUT 0x00a0 0x0000 0xb 0x0 -#define ULP1_PAD_PTB8__FXIO0_D24 0x00a0 0x0000 0x2 0x0 -#define ULP1_PAD_PTB8__LPSPI1_SOUT 0x00a0 0xd134 0x3 0x3 -#define ULP1_PAD_PTB8__LPI2C1_SCL 0x00a0 0xd188 0x5 0x3 -#define ULP1_PAD_PTB8__TPM0_CLKIN 0x00a0 0xd1a8 0x6 0x3 -#define ULP1_PAD_PTB8__I2S1_RX_BCLK 0x00a0 0xd1cc 0x7 0x2 -#define ULP1_PAD_PTB8__QSPIA_SS0_B 0x00a0 0x0000 0x8 0x0 -#define ULP1_PAD_PTB9_LLWU0_P12__CMP0_IN0B 0x00a4 0x0000 0x0 0x0 -#define ULP1_PAD_PTB9_LLWU0_P12__PTB9 0x00a4 0x0000 0x1 0x0 -#define ULP1_PAD_PTB9_LLWU0_P12__LLWU0_P12 0x00a4 0x0000 0xd 0x0 -#define ULP1_PAD_PTB9_LLWU0_P12__FXIO0_D25 0x00a4 0x0000 0x2 0x0 -#define ULP1_PAD_PTB9_LLWU0_P12__LPSPI1_SCK 0x00a4 0xd12c 0x3 0x3 -#define ULP1_PAD_PTB9_LLWU0_P12__LPI2C1_SDA 0x00a4 0xd18c 0x5 0x3 -#define ULP1_PAD_PTB9_LLWU0_P12__TPM0_CH0 0x00a4 0xd138 0x6 0x3 -#define ULP1_PAD_PTB9_LLWU0_P12__I2S1_RX_FS 0x00a4 0xd1d0 0x7 0x2 -#define ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x00a4 0x0000 0x8 0x0 -#define ULP1_PAD_PTB10__CMP0_IN1A 0x00a8 0x0000 0x0 0x0 -#define ULP1_PAD_PTB10__PTB10 0x00a8 0x0000 0x1 0x0 -#define ULP1_PAD_PTB10__TRACE_D4 0x00a8 0x0000 0xa 0x0 -#define ULP1_PAD_PTB10__FXIO0_D26 0x00a8 0x0000 0x2 0x0 -#define ULP1_PAD_PTB10__LPSPI1_PCS0 0x00a8 0xd11c 0x3 0x3 -#define ULP1_PAD_PTB10__LPI2C2_SCL 0x00a8 0xd194 0x5 0x3 -#define ULP1_PAD_PTB10__TPM0_CH1 0x00a8 0xd13c 0x6 0x3 -#define ULP1_PAD_PTB10__I2S1_RXD0 0x00a8 0xd1e4 0x7 0x2 -#define ULP1_PAD_PTB10__QSPIA_DATA7 0x00a8 0x0000 0x8 0x0 -#define ULP1_PAD_PTB11__CMP0_IN1B 0x00ac 0x0000 0x0 0x0 -#define ULP1_PAD_PTB11__PTB11 0x00ac 0x0000 0x1 0x0 -#define ULP1_PAD_PTB11__TRACE_D5 0x00ac 0x0000 0xa 0x0 -#define ULP1_PAD_PTB11__FXIO0_D27 0x00ac 0x0000 0x2 0x0 -#define ULP1_PAD_PTB11__LPSPI1_PCS1 0x00ac 0xd120 0x3 0x3 -#define ULP1_PAD_PTB11__LPI2C2_SDA 0x00ac 0xd198 0x5 0x3 -#define ULP1_PAD_PTB11__TPM1_CLKIN 0x00ac 0xd1ac 0x6 0x3 -#define ULP1_PAD_PTB11__I2S1_RXD1 0x00ac 0xd1e8 0x7 0x2 -#define ULP1_PAD_PTB11__QSPIA_DATA6 0x00ac 0x0000 0x8 0x0 -#define ULP1_PAD_PTB12__ADC1_CH0A 0x00b0 0x0000 0x0 0x0 -#define ULP1_PAD_PTB12__PTB12 0x00b0 0x0000 0x1 0x0 -#define ULP1_PAD_PTB12__TRACE_D6 0x00b0 0x0000 0xa 0x0 -#define ULP1_PAD_PTB12__FXIO0_D28 0x00b0 0x0000 0x2 0x0 -#define ULP1_PAD_PTB12__LPSPI1_PCS2 0x00b0 0xd124 0x3 0x3 -#define ULP1_PAD_PTB12__LPI2C3_SCL 0x00b0 0xd1a0 0x5 0x3 -#define ULP1_PAD_PTB12__TPM1_CH0 0x00b0 0xd150 0x6 0x3 -#define ULP1_PAD_PTB12__I2S1_RXD2 0x00b0 0xd1ec 0x7 0x2 -#define ULP1_PAD_PTB12__QSPIA_DATA5 0x00b0 0x0000 0x8 0x0 -#define ULP1_PAD_PTB13__ADC1_CH0B 0x00b4 0x0000 0x0 0x0 -#define ULP1_PAD_PTB13__PTB13 0x00b4 0x0000 0x1 0x0 -#define ULP1_PAD_PTB13__TRACE_D7 0x00b4 0x0000 0xa 0x0 -#define ULP1_PAD_PTB13__FXIO0_D29 0x00b4 0x0000 0x2 0x0 -#define ULP1_PAD_PTB13__LPSPI1_PCS3 0x00b4 0xd128 0x3 0x3 -#define ULP1_PAD_PTB13__LPI2C3_SDA 0x00b4 0xd1a4 0x5 0x3 -#define ULP1_PAD_PTB13__TPM1_CH1 0x00b4 0xd154 0x6 0x3 -#define ULP1_PAD_PTB13__I2S1_RXD3 0x00b4 0xd1f0 0x7 0x2 -#define ULP1_PAD_PTB13__QSPIA_DATA4 0x00b4 0x0000 0x8 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__ADC1_CH1A 0x00b8 0x0000 0x0 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__PTB14 0x00b8 0x0000 0x1 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__LLWU0_P13 0x00b8 0x0000 0xd 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__FXIO0_D30 0x00b8 0x0000 0x2 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__LPI2C2_HREQ 0x00b8 0xd190 0x5 0x3 -#define ULP1_PAD_PTB14_LLWU0_P13__TPM2_CLKIN 0x00b8 0xd1f4 0x6 0x3 -#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SS0_B 0x00b8 0x0000 0x8 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SCLK_B 0x00b8 0x0000 0x9 0x0 -#define ULP1_PAD_PTB15__ADC1_CH1B 0x00bc 0x0000 0x0 0x0 -#define ULP1_PAD_PTB15__PTB15 0x00bc 0x0000 0x1 0x0 -#define ULP1_PAD_PTB15__FXIO0_D31 0x00bc 0x0000 0x2 0x0 -#define ULP1_PAD_PTB15__LPI2C3_HREQ 0x00bc 0xd19c 0x5 0x3 -#define ULP1_PAD_PTB15__TPM2_CH0 0x00bc 0xd158 0x6 0x3 -#define ULP1_PAD_PTB15__QSPIA_SCLK 0x00bc 0x0000 0x8 0x0 -#define ULP1_PAD_PTB16_LLWU0_P14__ADC0_CH2A 0x00c0 0x0000 0x0 0x0 -#define ULP1_PAD_PTB16_LLWU0_P14__PTB16 0x00c0 0x0000 0x1 0x0 -#define ULP1_PAD_PTB16_LLWU0_P14__LLWU0_P14 0x00c0 0x0000 0xd 0x0 -#define ULP1_PAD_PTB16_LLWU0_P14__TPM2_CH1 0x00c0 0xd15c 0x6 0x3 -#define ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x00c0 0x0000 0x8 0x0 -#define ULP1_PAD_PTB17__ADC0_CH2B 0x00c4 0x0000 0x0 0x0 -#define ULP1_PAD_PTB17__PTB17 0x00c4 0x0000 0x1 0x0 -#define ULP1_PAD_PTB17__TPM3_CLKIN 0x00c4 0xd1b0 0x6 0x2 -#define ULP1_PAD_PTB17__QSPIA_DATA2 0x00c4 0x0000 0x8 0x0 -#define ULP1_PAD_PTB18__ADC0_CH3A 0x00c8 0x0000 0x0 0x0 -#define ULP1_PAD_PTB18__PTB18 0x00c8 0x0000 0x1 0x0 -#define ULP1_PAD_PTB18__TPM3_CH0 0x00c8 0xd160 0x6 0x3 -#define ULP1_PAD_PTB18__QSPIA_DATA1 0x00c8 0x0000 0x8 0x0 -#define ULP1_PAD_PTB19_LLWU0_P15__ADC0_CH3B 0x00cc 0x0000 0x0 0x0 -#define ULP1_PAD_PTB19_LLWU0_P15__PTB19 0x00cc 0x0000 0x1 0x0 -#define ULP1_PAD_PTB19_LLWU0_P15__USB0_ID 0x00cc 0x0000 0xa 0x0 -#define ULP1_PAD_PTB19_LLWU0_P15__LLWU0_P15 0x00cc 0x0000 0xd 0x0 -#define ULP1_PAD_PTB19_LLWU0_P15__TPM3_CH1 0x00cc 0xd164 0x6 0x3 -#define ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x00cc 0x0000 0x8 0x0 -#define ULP1_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 -#define ULP1_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 -#define ULP1_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 -#define ULP1_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 -#define ULP1_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 -#define ULP1_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 -#define ULP1_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 -#define ULP1_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 -#define ULP1_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 -#define ULP1_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 -#define ULP1_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 -#define ULP1_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 -#define ULP1_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 -#define ULP1_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 -#define ULP1_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 -#define ULP1_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 -#define ULP1_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 -#define ULP1_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 -#define ULP1_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 -#define ULP1_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 -#define ULP1_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 -#define ULP1_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 -#define ULP1_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 -#define ULP1_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 -#define ULP1_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 -#define ULP1_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 -#define ULP1_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 -#define ULP1_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 -#define ULP1_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 -#define ULP1_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 -#define ULP1_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 -#define ULP1_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 -#define ULP1_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 -#define ULP1_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 -#define ULP1_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 -#define ULP1_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 -#define ULP1_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 -#define ULP1_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 -#define ULP1_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 -#define ULP1_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 -#define ULP1_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 -#define ULP1_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 -#define ULP1_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 -#define ULP1_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 -#define ULP1_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 -#define ULP1_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 -#define ULP1_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 -#define ULP1_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 -#define ULP1_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 -#define ULP1_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 -#define ULP1_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 -#define ULP1_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 -#define ULP1_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 -#define ULP1_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 -#define ULP1_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 -#define ULP1_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 -#define ULP1_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 -#define ULP1_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 -#define ULP1_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 -#define ULP1_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 -#define ULP1_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 -#define ULP1_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 -#define ULP1_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 -#define ULP1_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 -#define ULP1_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 -#define ULP1_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 -#define ULP1_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 -#define ULP1_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 -#define ULP1_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 -#define ULP1_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 -#define ULP1_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 -#define ULP1_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 -#define ULP1_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 -#define ULP1_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 -#define ULP1_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 -#define ULP1_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 -#define ULP1_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 -#define ULP1_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 -#define ULP1_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 -#define ULP1_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 -#define ULP1_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 -#define ULP1_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 -#define ULP1_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 -#define ULP1_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 -#define ULP1_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 -#define ULP1_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 -#define ULP1_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 -#define ULP1_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 -#define ULP1_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 -#define ULP1_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 -#define ULP1_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 -#define ULP1_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 -#define ULP1_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 -#define ULP1_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 -#define ULP1_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 -#define ULP1_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 -#define ULP1_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 -#define ULP1_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 -#define ULP1_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 -#define ULP1_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 -#define ULP1_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 -#define ULP1_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 -#define ULP1_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 -#define ULP1_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 -#define ULP1_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 -#define ULP1_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 -#define ULP1_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 -#define ULP1_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 -#define ULP1_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 -#define ULP1_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 -#define ULP1_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 -#define ULP1_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 -#define ULP1_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 -#define ULP1_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 -#define ULP1_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 -#define ULP1_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 -#define ULP1_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 -#define ULP1_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 -#define ULP1_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 -#define ULP1_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 -#define ULP1_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 -#define ULP1_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 -#define ULP1_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 -#define ULP1_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 -#define ULP1_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 -#define ULP1_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 -#define ULP1_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 -#define ULP1_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 -#define ULP1_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 -#define ULP1_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 -#define ULP1_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 -#define ULP1_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 -#define ULP1_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 -#define ULP1_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 -#define ULP1_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 -#define ULP1_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 -#define ULP1_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 -#define ULP1_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 -#define ULP1_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 -#define ULP1_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 -#define ULP1_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 -#define ULP1_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 -#define ULP1_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 -#define ULP1_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 -#define ULP1_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 -#define ULP1_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 -#define ULP1_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 -#define ULP1_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 -#define ULP1_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 -#define ULP1_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 -#define ULP1_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 -#define ULP1_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 -#define ULP1_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 -#define ULP1_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 -#define ULP1_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 -#define ULP1_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 -#define ULP1_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 -#define ULP1_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 -#define ULP1_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 -#define ULP1_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 -#define ULP1_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 -#define ULP1_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 -#define ULP1_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 -#define ULP1_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 -#define ULP1_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 -#define ULP1_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 -#define ULP1_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 -#define ULP1_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 -#define ULP1_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 -#define ULP1_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 -#define ULP1_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 -#define ULP1_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 -#define ULP1_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 -#define ULP1_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 -#define ULP1_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 -#define ULP1_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 -#define ULP1_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 -#define ULP1_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 -#define ULP1_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 -#define ULP1_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 -#define ULP1_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 -#define ULP1_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 -#define ULP1_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 -#define ULP1_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 -#define ULP1_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 -#define ULP1_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 -#define ULP1_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 -#define ULP1_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 -#define ULP1_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 -#define ULP1_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 -#define ULP1_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 -#define ULP1_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 -#define ULP1_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 -#define ULP1_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 -#define ULP1_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 -#define ULP1_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 -#define ULP1_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 -#define ULP1_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 -#define ULP1_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 -#define ULP1_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 -#define ULP1_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 -#define ULP1_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 -#define ULP1_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 -#define ULP1_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 -#define ULP1_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 -#define ULP1_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 -#define ULP1_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 -#define ULP1_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 -#define ULP1_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 -#define ULP1_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 -#define ULP1_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 -#define ULP1_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 -#define ULP1_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 -#define ULP1_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 -#define ULP1_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 -#define ULP1_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 -#define ULP1_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 -#define ULP1_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 -#define ULP1_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 -#define ULP1_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 -#define ULP1_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 -#define ULP1_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 -#define ULP1_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 -#define ULP1_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 -#define ULP1_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 -#define ULP1_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 -#define ULP1_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 -#define ULP1_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 -#define ULP1_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 -#define ULP1_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 -#define ULP1_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 -#define ULP1_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 -#define ULP1_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 -#define ULP1_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 -#define ULP1_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 -#define ULP1_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 -#define ULP1_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 -#define ULP1_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 -#define ULP1_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 -#define ULP1_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 -#define ULP1_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 -#define ULP1_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 -#define ULP1_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 -#define ULP1_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 -#define ULP1_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 -#define ULP1_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 -#define ULP1_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 -#define ULP1_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 -#define ULP1_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 -#define ULP1_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 -#define ULP1_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 -#define ULP1_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 -#define ULP1_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 -#define ULP1_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 -#define ULP1_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 -#define ULP1_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 -#define ULP1_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 -#define ULP1_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 -#define ULP1_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 -#define ULP1_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 -#define ULP1_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 -#define ULP1_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 -#define ULP1_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 -#define ULP1_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 -#define ULP1_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 -#define ULP1_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 -#define ULP1_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 -#define ULP1_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 -#define ULP1_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 -#define ULP1_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 -#define ULP1_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 -#define ULP1_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 -#define ULP1_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 -#define ULP1_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 -#define ULP1_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 -#define ULP1_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 -#define ULP1_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 -#define ULP1_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 -#define ULP1_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 -#define ULP1_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 -#define ULP1_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 -#define ULP1_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 -#define ULP1_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 -#define ULP1_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 -#define ULP1_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 -#define ULP1_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 -#define ULP1_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 -#define ULP1_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 -#define ULP1_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 -#define ULP1_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 -#define ULP1_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 -#define ULP1_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 -#define ULP1_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 -#define ULP1_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 -#define ULP1_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 -#define ULP1_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 -#define ULP1_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 -#define ULP1_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 -#define ULP1_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 -#define ULP1_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0 -#define ULP1_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 -#define ULP1_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 -#define ULP1_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 -#define ULP1_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 -#define ULP1_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 -#define ULP1_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 -#define ULP1_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 -#define ULP1_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 -#define ULP1_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 -#define ULP1_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 -#define ULP1_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 -#define ULP1_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 -#define ULP1_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 -#define ULP1_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 -#define ULP1_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 -#define ULP1_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 -#define ULP1_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 -#define ULP1_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 -#define ULP1_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 -#define ULP1_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 -#define ULP1_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 -#define ULP1_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 -#define ULP1_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 -#define ULP1_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 -#define ULP1_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 -#define ULP1_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 -#define ULP1_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 -#define ULP1_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 -#define ULP1_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 -#define ULP1_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 -#define ULP1_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 -#define ULP1_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 -#define ULP1_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 -#define ULP1_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 -#define ULP1_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 -#define ULP1_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 -#define ULP1_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 -#define ULP1_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 -#define ULP1_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 -#define ULP1_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 -#define ULP1_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 -#define ULP1_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 -#define ULP1_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 -#define ULP1_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 -#define ULP1_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 -#define ULP1_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 -#define ULP1_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 -#define ULP1_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 -#define ULP1_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 -#define ULP1_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 -#define ULP1_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 -#define ULP1_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 -#define ULP1_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 -#define ULP1_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 -#define ULP1_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 -#define ULP1_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 -#define ULP1_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 -#define ULP1_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 -#define ULP1_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 -#define ULP1_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 -#define ULP1_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 -#define ULP1_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 -#define ULP1_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 -#define ULP1_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 -#define ULP1_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 -#define ULP1_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 -#define ULP1_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 -#define ULP1_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 -#define ULP1_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 -#define ULP1_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 -#define ULP1_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 -#define ULP1_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 -#define ULP1_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 -#define ULP1_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 -#define ULP1_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 -#define ULP1_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 -#define ULP1_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 -#define ULP1_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 -#define ULP1_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 -#define ULP1_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 -#define ULP1_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 -#define ULP1_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 -#define ULP1_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 -#define ULP1_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 -#define ULP1_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 -#define ULP1_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 -#define ULP1_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 -#define ULP1_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 -#define ULP1_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 -#define ULP1_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 -#define ULP1_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 -#define ULP1_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 -#define ULP1_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 -#define ULP1_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 -#define ULP1_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 -#define ULP1_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 -#define ULP1_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 -#define ULP1_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 -#define ULP1_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 -#define ULP1_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 -#define ULP1_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 -#define ULP1_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 -#define ULP1_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 -#define ULP1_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 -#define ULP1_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 -#define ULP1_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 -#define ULP1_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 -#define ULP1_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 -#define ULP1_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 -#define ULP1_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 -#define ULP1_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 -#define ULP1_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 -#define ULP1_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 -#define ULP1_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 -#define ULP1_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 -#define ULP1_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 -#define ULP1_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 -#define ULP1_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 -#define ULP1_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 -#define ULP1_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 -#define ULP1_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 -#define ULP1_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 -#define ULP1_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 -#define ULP1_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 -#define ULP1_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 -#define ULP1_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 -#define ULP1_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 -#define ULP1_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 -#define ULP1_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 -#define ULP1_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 -#define ULP1_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 -#define ULP1_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 -#define ULP1_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 -#define ULP1_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 -#define ULP1_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 -#define ULP1_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 -#define ULP1_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 -#define ULP1_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 -#define ULP1_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 -#define ULP1_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 -#define ULP1_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 -#define ULP1_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 -#define ULP1_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 -#define ULP1_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 -#define ULP1_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 -#define ULP1_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 -#define ULP1_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 -#define ULP1_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 - -#endif /* __DTS_ULP1_PINFUNC_H */ +#endif /* __DTS_IMX7ULP_PINFUNC_H */ diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi index a8458f89d5f..7bcd2cc3469 100644 --- a/arch/arm/dts/imx7ulp.dtsi +++ b/arch/arm/dts/imx7ulp.dtsi @@ -16,10 +16,12 @@ interrupt-parent = <&intc>; aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; + gpio0 = &gpio4; + gpio1 = &gpio5; + gpio2 = &gpio0; + gpio3 = &gpio1; + gpio4 = &gpio2; + gpio5 = &gpio3; mmc0 = &usdhc0; mmc1 = &usdhc1; serial0 = &lpuart4; @@ -27,10 +29,12 @@ serial2 = &lpuart6; serial3 = &lpuart7; usbphy0 = &usbphy1; + usb0 = &usbotg1; i2c4 = &lpi2c4; i2c5 = &lpi2c5; i2c6 = &lpi2c6; i2c7 = &lpi2c7; + spi0 = &qspi1; }; cpus { @@ -503,6 +507,22 @@ fsl,mux_mask = <0xf00>; }; + gpio4: gpio@4103f000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x4103f000 0x1000 0x4100F000 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&iomuxc 0 0 32>; + }; + + gpio5: gpio@41040000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x41040000 0x1000 0x4100F040 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&iomuxc 0 32 32>; + }; + gpio0: gpio@40ae0000 { compatible = "fsl,imx7ulp-gpio"; reg = <0x40ae0000 0x1000 0x400F0000 0x40>; diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig new file mode 100644 index 00000000000..e3ee091a2f8 --- /dev/null +++ b/arch/arm/imx-common/Kconfig @@ -0,0 +1,78 @@ +config IMX_CONFIG + string + +config IMX_OPTEE + bool "Support OP-TEE" + help + Enable support for OP-TEE + +config GPT_TIMER + bool "Using i.MX GPT timer as system tick timer" + depends on ARCH_MX6 || ARCH_MX7 + help + Enable GPT timer driver for system tick timer on i.MX6 and + i.MX7. + +config ROM_UNIFIED_SECTIONS + bool + +config IMX_RDC + bool "i.MX Resource domain controller driver" + depends on ARCH_MX6 || ARCH_MX7 + help + i.MX Resource domain controller is used to assign masters + and peripherals to differet domains. This can be used to + isolate resources. + +config IMX_BOOTAUX + bool "Support boot auxiliary core" + depends on ARCH_MX7 || ARCH_MX6 || ARCH_IMX8 + help + bootaux [addr] to boot auxiliary core. + +config USE_IMXIMG_PLUGIN + bool "Use imximage plugin code" + depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX7ULP + help + i.MX6/7 supports DCD and Plugin. Enable this configuration + to use Plugin, otherwise DCD will be used. + +config SECURE_BOOT + bool "Support i.MX HAB features" + depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M + select FSL_CAAM if !MX6ULL && !MX6SLL && !MX6SL && !IMX8M + help + This option enables the support for secure boot (HAB). + See doc/README.mxc_hab for more details. + +config FSL_MFGPROT + bool "Support the 'mfgprot' command" + depends on SECURE_BOOT && ARCH_MX7 + help + This option enables the manufacturing protection command + which can be used has a protection feature for Manufacturing + process. With this tool is possible to authenticate the + chip to the OEM's server. + +config DBG_MONITOR + bool "Enable the AXI debug monitor" + depends on ARCH_MX6 || ARCH_MX7 + help + This option enables the debug monitor which prints out last + failed AXI access info when system reboot is caused by AXI + access failure. + +config IMX_M4_BIND + bool "Bind ULP M4 image to final u-boot" + depends on ARCH_MX7ULP + help + Select this to bind a ULP M4 image to final u-boot image + User needs put the M4 image ulp_m4.bin under u-boot directory + +config IMX_TRUSTY_OS + bool "Support Trusty OS related feature" + depends on ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M + select SYS_ARM_CACHE_WRITEALLOC + +config SYS_ARM_CACHE_WRITEALLOC + bool "support cache write alloc" diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 470961c6f7f..430e8dde466 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -1,5 +1,6 @@ /* * (C) Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -18,6 +19,7 @@ #define MXC_CPU_MX6Q 0x63 #define MXC_CPU_MX6UL 0x64 #define MXC_CPU_MX6ULL 0x65 +#define MXC_CPU_MX6ULZ 0x6b /* dummy ID */ #define MXC_CPU_MX6SOLO 0x66 /* dummy */ #define MXC_CPU_MX6SLL 0x67 #define MXC_CPU_MX6D 0x6A @@ -25,23 +27,40 @@ #define MXC_CPU_MX6QP 0x69 #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 -#define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8MQ 0x82 +#define MXC_CPU_IMX8MD 0x83 /* dummy ID */ +#define MXC_CPU_IMX8MQL 0x84 /* dummy ID */ +#define MXC_CPU_IMX8MM 0x85 /* dummy ID */ +#define MXC_CPU_IMX8MML 0x86 /* dummy ID */ +#define MXC_CPU_IMX8MMD 0x87 /* dummy ID */ +#define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */ +#define MXC_CPU_IMX8MMS 0x89 /* dummy ID */ +#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */ +#define MXC_CPU_IMX8QM 0x91 /* dummy ID */ +#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ +#define MXC_CPU_IMX8DX 0x93 /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 -#define MXC_SOC_MX8M 0x80 +#define MXC_SOC_IMX8M 0x80 +#define MXC_SOC_IMX8 0x90 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 #define CHIP_REV_1_2 0x12 +#define CHIP_REV_1_3 0x13 #define CHIP_REV_1_5 0x15 #define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_1 0x21 #define CHIP_REV_2_5 0x25 #define CHIP_REV_3_0 0x30 +#define CHIP_REV_A 0x0 +#define CHIP_REV_B 0x1 + #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 #define BOARD_VER_OFFSET 0x8 diff --git a/arch/arm/include/asm/arch-imx8/MX8_extension.h b/arch/arm/include/asm/arch-imx8/MX8_extension.h new file mode 100644 index 00000000000..6c888d8b00d --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/MX8_extension.h @@ -0,0 +1,485 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * @file devices/MX8/include/MX8_extension.h + * + * @brief SDK 1.3 Extension + * + * Header file containing the SDK 1.3 extension for i.MX8. + */ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __MX8_EXTENSION_H__ +#define __MX8_EXTENSION_H__ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* + * MX8 MU + * + * MU + * + * Registers defined in this header file: + * - MU_TR - Transmit Register n + * - MU_RR - Receive Register n + * - MU_SR - Status Register + * - MU_CR - Control Register + */ + +/******************************************************************************* + * MU_TR - Transmit Register n + ******************************************************************************/ + +/*! + * @brief MU_TR - Transmit Register n (RW) + * + * Reset value: 0x00000000U + * + * Use Processor A/B Transmit Register n (TRn, 32-bit, write-only) to transmit a + * message or data to the Processor B/A. You can only write to the TRn register + * when the TEn bit in SR register is set to "1". Reading the TRn register + * returns all zeros. + */ +/*! + * @name Constants and macros for entire MU_TR register + */ +/*@{*/ +#define MU_RD_TR(base, index) (MU_TR_REG(base, index)) +#define MU_WR_TR(base, index, value) (MU_TR_REG(base, index) = (value)) +#define MU_RMW_TR(base, index, mask, value) (MU_WR_TR(base, index, (MU_RD_TR(base, index) & ~(mask)) | (value))) +#define MU_SET_TR(base, index, value) (BME_OR32(&MU_TR_REG(base, index), (uint32_t)(value))) +#define MU_CLR_TR(base, index, value) (BME_AND32(&MU_TR_REG(base, index), (uint32_t)(~(value)))) +#define MU_TOG_TR(base, index, value) (BME_XOR32(&MU_TR_REG(base, index), (uint32_t)(value))) +/*@}*/ + +/******************************************************************************* + * MU_RR - Receive Register n + ******************************************************************************/ + +/*! + * @brief MU_RR - Receive Register n (RO) + * + * Reset value: 0x00000000U + * + * Use Processor A/B Receive Register n (RRn, 32-bit, read-only) to receive a + * message or data from the Processor B/A. Data written to the Processor B/A TRn + * register is immediately reflected in the Processor A/B RRn register. You can + * only read the RRn register when the RFn bit in the SR register is set to "1". + * Writing to the RRn register generates an error response to the Processor A/B. + */ +/*! + * @name Constants and macros for entire MU_RR register + */ +/*@{*/ +#define MU_RD_RR(base, index) (MU_RR_REG(base, index)) +/*@}*/ + +/******************************************************************************* + * MU_SR - Status Register + ******************************************************************************/ + +/*! + * @brief MU_SR - Status Register (RW) + * + * Reset value: 0x00F00080U + * + * Use the Processor A/B Status Register (SR, 32-bit, read-write) to show + * interrupt status from the Processor B/A, general purpose flags , and to set dual + * function control-status bits. Some dual-purpose bits are set by the MU logic, and + * cleared by the Processor A/B-side programmer Other dual-purpose bits are set + * by the Processor A/B-side programmer, and cleared by the MU logic. + */ +/*! + * @name Constants and macros for entire MU_SR register + */ +/*@{*/ +#define MU_RD_SR(base) (MU_SR_REG(base)) +#define MU_WR_SR(base, value) (MU_SR_REG(base) = (value)) +#define MU_RMW_SR(base, mask, value) (MU_WR_SR(base, (MU_RD_SR(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual MU_SR bitfields + */ + +/*! + * @name Register MU_SR, field Fn[2:0] (RW) + * + * For n = {0, 1, 2} Processor A/B Side Flag n. (Read-only) Fn bit is the + * Processor A/B side flag that reflects the values written to the Fn bit in the + * Processor B/A control register. Every time that the Processor B/A Fn bit in the CR + * register is written, the Processor B/A Fn bit in the CR register write event + * updates the Fn bit after the event update latency, which is measured in terms of + * the number of clocks of the Processor B/A and the Processor A/B. + * + * Values: + * - 0b000 - Processor B/A Fn bit in the CR register is written 0 (default). + * - 0b001 - Processor B/A Fn bit in the CR register is written 1. + */ +/*@{*/ +/*! @brief Read current value of the MU_SR_Fn field. */ +#define MU_RD_SR_Fn(base) ((MU_SR_REG(base) & MU_SR_Fn_MASK) >> MU_SR_Fn_SHIFT) + +/*! @brief Set the Fn field to a new value. */ +#define MU_WR_SR_Fn(base, value) (MU_RMW_SR(base, (MU_SR_Fn_MASK | MU_SR_NMIC_MASK), MU_SR_Fn(value))) +/*@}*/ + +/*! + * @name Register MU_SR, field EP[4] (RW) + * + * Processor A/B Side Event Pending. (Read-only) EP bit is set to "1" when the + * Processor A/B side mechanism sends an event update request to the Processor B/A + * side. EP bit is cleared when the event update acknowledge is received. An + * "event" is any hardware message that is reflected in the Processor B/A SR + * register on the Processor B/A side (for example, "transmit register 0 written"). + * During normal operations, you do not have to deal with the state of the EP bit + * because the event update mechanism works automatically. To ensure events have + * been posted to Processor B/A before entering STOP mode, you should verify that + * the EP bit is cleared. If EP bit is set to "1", you should wait and continue to + * poll it (EP bit) before entering STOP mode. Reading the Processor A/B SR + * register (to check the EP bit) should be the last access to the MU that should be + * performed before entering STOPor WAIT modes; otherwise, the EP bit may be set + * by subsequent additional actions. The EP bit is cleared when the MU resets. + * + * Values: + * - 0b0 - The Processor A-side event is not pending (default). + * - 0b1 - The Processor A-side event is pending. + */ +/*@{*/ +/*! @brief Read current value of the MU_SR_EP field. */ +#define MU_RD_SR_EP(base) ((MU_SR_REG(base) & MU_SR_EP_MASK) >> MU_SR_EP_SHIFT) + +/*! @brief Set the EP field to a new value. */ +#define MU_WR_SR_EP(base, value) (MU_RMW_SR(base, (MU_SR_EP_MASK | MU_SR_NMIC_MASK), MU_SR_EP(value))) +/*@}*/ + +/*! + * @name Register MU_SR, field PM[6:5] (RW) + * + * Processor B/A Power Mode. (Read-only) PM[1:0] bits indicate the Processor B/A + * power mode. The Processor B/A Power Mode is platform-specific. + * + * Values: + * - 0b00 - The Processor B/A is in Run Mode. + * - 0b01 - The Processor B/A is in WAIT Mode. + * - 0b10 - The Processor B/A is in STOP/VLPS Mode. + * - 0b11 - The Processor B/A is in LLS/VLLS Mode. + */ +/*@{*/ +#define MU_SR_PM_RUN (0U) /*!< Bit field value for MU_SR_PM: The Processor B/A is in Run Mode. */ +#define MU_SR_PM_WAIT (0x1U) /*!< Bit field value for MU_SR_PM: The Processor B/A is in WAIT Mode. */ +#define MU_SR_PM_STOP (0x2U) /*!< Bit field value for MU_SR_PM: The Processor B/A is in STOP/VLPS Mode. */ +#define MU_SR_PM_DSM (0x3U) /*!< Bit field value for MU_SR_PM: The Processor B/A is in LLS/VLLS Mode. */ +/*! @brief Read current value of the MU_SR_PM field. */ +#define MU_RD_SR_PM(base) ((MU_SR_REG(base) & MU_SR_PM_MASK) >> MU_SR_PM_SHIFT) + +/*! @brief Set the PM field to a new value. */ +#define MU_WR_SR_PM(base, value) (MU_RMW_SR(base, (MU_SR_PM_MASK | MU_SR_NMIC_MASK), MU_SR_PM(value))) +/*@}*/ + +/*! + * @name Register MU_SR, field FUP[8] (RW) + * + * Processor A/B Flags Update Pending. (Read-only) FUP bit is set to "1" when + * the Processor A/B side sends a Flags Update request to the Processor B/A side. A + * Flags Update request is generated when there is a change to the Fn[2:0] bits + * of the Processor A/B CR register. No flag update changes are allowed while the + * FUP bit is set to "1". Any write to the Fn[2:0] bits of the Processor A/B CR + * register, while the FUP bit is set to "1", will not generate a Flags Update + * event, and the Fn[2:0] bits will stay unchanged. FUP bit is cleared when this + * Flags Update request is internally acknowledged (that the flag is updated) from + * the MU Processor B/A side, and during MU reset. + * + * Values: + * - 0b0 - No flags updated, initiated by the Processor A, in progress (default) + * - 0b1 - Processor A/B initiated flags update, processing + */ +/*@{*/ +/*! @brief Read current value of the MU_SR_FUP field. */ +#define MU_RD_SR_FUP(base) ((MU_SR_REG(base) & MU_SR_FUP_MASK) >> MU_SR_FUP_SHIFT) + +/*! @brief Set the FUP field to a new value. */ +#define MU_WR_SR_FUP(base, value) (MU_RMW_SR(base, (MU_SR_FUP_MASK | MU_SR_NMIC_MASK), MU_SR_FUP(value))) +/*@}*/ + +/*! + * @name Register MU_SR, field TEn[23:20] (RW) + * + * For n = {0, 1, 2, 3} Processor A/B Transmit Register n Empty. (Read-only) The + * TEn bit is set to "1" after the Processor B/A RRn register is read on the + * Processor B/A side. After the TEn bit is set to "1", the TEn bit signals the + * Processor A/B side that the Processor A/B TRn register is ready to be written on + * the Processor A/B side, and a Transmit n interrupt is issued on the Processor + * A/B side (if the TEn bit in the Processor A/B CR register is set to "1"). TEn + * bit is cleared after the Processor A/B TRn register is written on the Processor + * A/B side. TEn bit is set to "1" when the MU is reset. + * + * Values: + * - 0b0000 - Processor A/B TRn register is not empty. + * - 0b0001 - Processor A/B TRn register is empty (default). + */ +/*@{*/ +/*! @brief Read current value of the MU_SR_TEn field. */ +#define MU_RD_SR_TEn(base) ((MU_SR_REG(base) & MU_SR_TEn_MASK) >> MU_SR_TEn_SHIFT) + +/*! @brief Set the TEn field to a new value. */ +#define MU_WR_SR_TEn(base, value) (MU_RMW_SR(base, (MU_SR_TEn_MASK | MU_SR_NMIC_MASK), MU_SR_TEn(value))) +/*@}*/ + +/*! + * @name Register MU_SR, field RFn[27:24] (RW) + * + * For n = {0, 1, 2, 3} Processor A/B Receive Register n Full. (Read-only) The + * RFn bit is set to "1" when the Processor B/A TRn register is written on the + * Processor B/A side. After the RFn bit is set to "1", the RFn bit signals the + * Processor A/B side that new data is ready to be read by the Processor A/B in the + * Processor A/B RRn register, and a Receive n interrupt is issued on the + * Processor A/B side (if the RIEn bit in the Processor A/B CR register has been set to + * "1"). RFn bit is cleared when the Processor A/B RRn register is read, and when + * the MU is reset. + * + * Values: + * - 0b0000 - Processor A/B RRn register is not full (default). + * - 0b0001 - Processor A/B RRn register has received data from Processor B/A + * TRn register and is ready to be read by the Processor A/B. + */ +/*@{*/ +/*! @brief Read current value of the MU_SR_RFn field. */ +#define MU_RD_SR_RFn(base) ((MU_SR_REG(base) & MU_SR_RFn_MASK) >> MU_SR_RFn_SHIFT) + +/*! @brief Set the RFn field to a new value. */ +#define MU_WR_SR_RFn(base, value) (MU_RMW_SR(base, (MU_SR_RFn_MASK | MU_SR_NMIC_MASK), MU_SR_RFn(value))) +/*@}*/ + +/*! + * @name Register MU_SR, field GIPn[31:28] (RW) + * + * For n = {0, 1, 2, 3} Processor A/B General Interrupt Request n Pending. + * (Read-Write) GIPn bit signals the Processor A/B that the GIRn bit in the BCR + * register on the Processor B-side was set from "0" to "1". If the GIEn bit in the ACR + * register is set to "1", a General Interrupt n request is issued. The GIPn bit + * is cleared by writing it back as "1". Writing "0", or writing "1" when the + * GIPn bit is cleared is ignored. Use this feature in the interrupt routine, where + * the GIPn bit is cleared in order to de-assert the interrupt request source at + * the interrupt controller. An example of a proper bit clearing sequence is: + * clear Processor A register, set the desired bit in it (Processor A register), + * and write it to the ASR register, thus clearing the GIPn bit. GIPn bit is + * cleared when the MU is reset. + * + * Values: + * - 0b0000 - Processor A/B general purpose interrupt n is not pending. (default) + * - 0b0001 - Processor A/B general purpose interrupt n is pending. + */ +/*@{*/ +/*! @brief Read current value of the MU_SR_GIPn field. */ +#define MU_RD_SR_GIPn(base) ((MU_SR_REG(base) & MU_SR_GIPn_MASK) >> MU_SR_GIPn_SHIFT) + +/*! @brief Set the GIPn field to a new value. */ +#define MU_WR_SR_GIPn(base, value) (MU_RMW_SR(base, (MU_SR_GIPn_MASK | MU_SR_NMIC_MASK), MU_SR_GIPn(value))) +/*@}*/ + +/******************************************************************************* + * MU_CR - Control Register + ******************************************************************************/ + +/*! + * @brief MU_CR - Control Register (RW) + * + * Reset value: 0x00000100U + * + * Use the Control Register (CR, 32-bit, read-write) to enable the MU interrupts + * on the Processor A/B-side, and trigger events and interrupts on the Processor + * B/A-side (general purpose interrupt, flag update). + */ +/*! + * @name Constants and macros for entire MU_CR register + */ +/*@{*/ +#define MU_RD_CR(base) (MU_CR_REG(base)) +#define MU_WR_CR(base, value) (MU_CR_REG(base) = (value)) +#define MU_RMW_CR(base, mask, value) (MU_WR_CR(base, (MU_RD_CR(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual MU_CR bitfields + */ + +/*! + * @name Register MU_CR, field Fn[2:0] (RW) + * + * For n = {0, 1, 2} Processor A/B to Processor B/A Flag n. (Read-Write) Fn bit + * is a read-write flag that is reflected in Fn bit in the Processor B/A SR + * register on the Processor B/A side. Fn bit is cleared when the MU resets. + * + * Values: + * - 0b000 - Clears the Fn bit in the SR register. + * - 0b001 - Sets the Fn bit in the SR register. + */ +/*@{*/ +/*! @brief Read current value of the MU_CR_Fn field. */ +#define MU_RD_CR_Fn(base) ((MU_CR_REG(base) & MU_CR_Fn_MASK) >> MU_CR_Fn_SHIFT) + +/*! @brief Set the Fn field to a new value. */ +#define MU_WR_CR_Fn(base, value) (MU_RMW_CR(base, MU_CR_Fn_MASK, MU_CR_Fn(value))) +/*@}*/ + +/*! + * @name Register MU_CR, field NMI[3] (RW) + * + * Processor B/A Non-maskable Interrupt. (Read-Write) When NMI bit is set to + * "1", it initiates a Non-Maskable Interrupt to the Processor B/A. NMI bit is + * cleared by the MU after the Processor B/A asserts the NMIC bit in the Processor B/A + * SR register. After the NMI bit is cleared, the Processor A/B can initiate + * another non-maskable interrupt to the Processor B/A. The NMI bit is cleared when + * the MU resets. + * + * Values: + * - 0b0 - Non-maskable interrupt is not issued to the Processor B/A by the + * Processor A/B (default). + * - 0b1 - Non-maskable interrupt is issued to the Processor B/A by the + * Processor A/B. + */ +/*@{*/ +/*! @brief Read current value of the MU_CR_NMI field. */ +#define MU_RD_CR_NMI(base) ((MU_CR_REG(base) & MU_CR_NMI_MASK) >> MU_CR_NMI_SHIFT) + +/*! @brief Set the NMI field to a new value. */ +#define MU_WR_CR_NMI(base, value) (MU_RMW_CR(base, MU_CR_NMI_MASK, MU_CR_NMI(value))) +/*@}*/ + +/*! + * @name Register MU_CR, field MUR[5] (RW) + * + * Processor A MU Reset. Setting MUR bit to "1" resets both the Processor B and + * the Processor A sides of the MU module, forcing all control and status + * registers to return to their default values and all internal states to be cleared. + * Before setting the MUR bit to "1", it is advisable to interrupt the Processor B + * , because setting the MUR bit may affect the ongoing Processor B program. MUR + * bit can only be written as "1". MUR bit is always read as "0". MUR bit is + * cleared during the MU reset sequence. This bit is only available on the Processor + * A side. + * + * Values: + * - 0b0 - N/A. Self clearing bit (default). + * - 0b1 - Asserts the Processor A MU reset. + */ +/*@{*/ +/*! @brief Read current value of the MU_CR_MUR field. */ +#define MU_RD_CR_MUR(base) ((MU_CR_REG(base) & MU_CR_MUR_MASK) >> MU_CR_MUR_SHIFT) + +/*! @brief Set the MUR field to a new value. */ +#define MU_WR_CR_MUR(base, value) (MU_RMW_CR(base, MU_CR_MUR_MASK, MU_CR_MUR(value))) +/*@}*/ + +/*! + * @name Register MU_CR, field GIRn[19:16] (RW) + * + * For n = {0, 1, 2, 3} Processor A/B General Purpose Interrupt Request n. + * (Read-Write) Writing "1" to the GIRn bit sets the GIPn bit in the Processor B/A SR + * register on the Processor B-side. If the GIEn bit in the Processor B/A CR + * register is set to "1" on the Processor B/A side, a General Purpose Interrupt n + * request is triggered. The GIRn bit is cleared if the GIPn bit (in the Processor + * B/A SR register on the Processor B/A side) is cleared by writing it (GIPn bit) + * as "1", thereby signalling the Processor A/B that the interrupt was accepted + * (cleared by the software). The GIPn bit cannot be written as "0" on the + * Processor A/B side. To ensure proper operations, you must verify that the GIRn bit + * is cleared (meaning that there is no pending interrupt) before setting it (GIRn + * bit). GIRn bit is cleared when the MU resets. + * + * Values: + * - 0b0000 - Processor A/B General Interrupt n is not requested to the + * Processor B/A (default). + * - 0b0001 - Processor A/B General Interrupt n is requested to the Processor + * B/A. + */ +/*@{*/ +/*! @brief Read current value of the MU_CR_GIRn field. */ +#define MU_RD_CR_GIRn(base) ((MU_CR_REG(base) & MU_CR_GIRn_MASK) >> MU_CR_GIRn_SHIFT) + +/*! @brief Set the GIRn field to a new value. */ +#define MU_WR_CR_GIRn(base, value) (MU_RMW_CR(base, MU_CR_GIRn_MASK, MU_CR_GIRn(value))) +/*@}*/ + +/*! + * @name Register MU_CR, field TIEn[23:20] (RW) + * + * For n = {0, 1, 2, 3} Processor A/B Transmit Interrupt Enable n. (Read-Write) + * TIEn bit enables Processor A/B Transmit Interrupt n. If TIEn bit is set to "1" + * (enabled), then an Processor A/B Transmit Interrupt n request is issued when + * the TEn bit in the Processor A/B SR register is set to "1". If TIEn bit is + * cleared (disabled), then the value of the TEn bit is ignored and no Processor A/B + * Transmit Interrupt n request will be issued. TIEn bit is cleared when the MU + * resets. + * + * Values: + * - 0b0000 - Disables Processor A/B Transmit Interrupt n. (default) + * - 0b0001 - Enables Processor A/B Transmit Interrupt n. + */ +/*@{*/ +/*! @brief Read current value of the MU_CR_TIEn field. */ +#define MU_RD_CR_TIEn(base) ((MU_CR_REG(base) & MU_CR_TIEn_MASK) >> MU_CR_TIEn_SHIFT) + +/*! @brief Set the TIEn field to a new value. */ +#define MU_WR_CR_TIEn(base, value) (MU_RMW_CR(base, MU_CR_TIEn_MASK, MU_CR_TIEn(value))) +/*@}*/ + +/*! + * @name Register MU_CR, field RIEn[27:24] (RW) + * + * For n = {0, 1, 2, 3} Processor A/B Receive Interrupt Enable n. (Read-Write) + * RIEn bit enables Processor A/B Receive Interrupt n. If RIEn bit is set to "1" + * (enabled), then an Processor A/B Receive Interrupt n request is issued when the + * RFn bit in the Processor A/B SR register is set to "1". If RIEn bit is + * cleared (disabled), then the value of the RFn bit is ignored and no Processor A/B + * Receive Interrupt n request will be issued. RIEn bit is cleared when the MU + * resets. + * + * Values: + * - 0b0000 - Disables Processor A/B Receive Interrupt n. (default) + * - 0b0001 - Enables Processor A/B Receive Interrupt n. + */ +/*@{*/ +/*! @brief Read current value of the MU_CR_RIEn field. */ +#define MU_RD_CR_RIEn(base) ((MU_CR_REG(base) & MU_CR_RIEn_MASK) >> MU_CR_RIEn_SHIFT) + +/*! @brief Set the RIEn field to a new value. */ +#define MU_WR_CR_RIEn(base, value) (MU_RMW_CR(base, MU_CR_RIEn_MASK, MU_CR_RIEn(value))) +/*@}*/ + +/*! + * @name Register MU_CR, field GIEn[31:28] (RW) + * + * For n = {0, 1, 2, 3} Processor A/B General Purpose Interrupt Enable n. + * (Read-Write) GIEn bit enables Processor A/B General Interrupt n. If GIEn bit is set + * to "1" (enabled), then a General Interrupt n request is issued when the GIPn + * bit in the Processor A/B SR register is set to "1". If GIEn is cleared + * (disabled), then the value of the GIPn bit is ignored and no General Interrupt n + * request will be issued. GIEn bit is cleared when the MU resets. + * + * Values: + * - 0b0000 - Disables Processor A/B General Interrupt n. (default) + * - 0b0001 - Enables Processor A/B General Interrupt n. + */ +/*@{*/ +/*! @brief Read current value of the MU_CR_GIEn field. */ +#define MU_RD_CR_GIEn(base) ((MU_CR_REG(base) & MU_CR_GIEn_MASK) >> MU_CR_GIEn_SHIFT) + +/*! @brief Set the GIEn field to a new value. */ +#define MU_WR_CR_GIEn(base, value) (MU_RMW_CR(base, MU_CR_GIEn_MASK, MU_CR_GIEn(value))) +/*@}*/ + + +#endif /* __MX8_EXTENSION_H__ */ +/* EOF */ diff --git a/arch/arm/include/asm/arch-imx8/MX8_mu.h b/arch/arm/include/asm/arch-imx8/MX8_mu.h new file mode 100644 index 00000000000..f1e266a278a --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/MX8_mu.h @@ -0,0 +1,219 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_MU_REGISTERS_H__ +#define __HW_MU_REGISTERS_H__ + +/* ---------------------------------------------------------------------------- + -- MU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer + * @{ + */ + +/** MU - Register Layout Typedef */ +typedef struct { + __IO uint32_t TR[4]; /**< Transmit Register n, array offset: 0x20, array step: 0x4 */ + __I uint32_t RR[4]; /**< Receive Register n, array offset: 0x40, array step: 0x4 */ + __IO uint32_t SR; /**< Status Register, offset: 0x60 */ + __IO uint32_t CR; /**< Control Register, offset: 0x64 */ +} MU_Type, *MU_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- MU - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Accessor_Macros MU - Register accessor macros + * @{ + */ + + +/* MU - Register accessors */ +#define MU_TR_REG(base,index) ((base)->TR[index]) +#define MU_TR_COUNT 4 +#define MU_RR_REG(base,index) ((base)->RR[index]) +#define MU_RR_COUNT 4 +#define MU_SR_REG(base) ((base)->SR) +#define MU_CR_REG(base) ((base)->CR) + +/*! + * @} + */ /* end of group MU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Masks MU Register Masks + * @{ + */ + +/* TR Bit Fields */ +#define MU_TR_DATA_MASK 0xFFFFFFFFu +#define MU_TR_DATA_SHIFT 0 +#define MU_TR_DATA_WIDTH 32 +#define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x))<> MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) +#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) +#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72) + +u32 cpu_mask(void); diff --git a/arch/arm/include/asm/arch-imx8/crm_regs.h b/arch/arm/include/asm/arch-imx8/crm_regs.h new file mode 100644 index 00000000000..20c867bb596 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/crm_regs.h @@ -0,0 +1,10 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_MX8_CRM_REGS_H +#define _ASM_ARCH_MX8_CRM_REGS_H +/* Dummy header, some imx-common code needs this file */ +#endif diff --git a/arch/arm/include/asm/arch-imx8/fsl_device_registers.h b/arch/arm/include/asm/arch-imx8/fsl_device_registers.h new file mode 100644 index 00000000000..f498cc9a33b --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/fsl_device_registers.h @@ -0,0 +1,20 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +#include +#include + +#define FSL_FEATURE_SOC_MU_COUNT (1) + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/arch/arm/include/asm/arch-imx8/fsl_mu_hal.h b/arch/arm/include/asm/arch-imx8/fsl_mu_hal.h new file mode 100644 index 00000000000..a93f0b6737e --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/fsl_mu_hal.h @@ -0,0 +1,645 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * @file hal/inc/fsl_mu_hal.h + * + * Header file containing HAL API for the MU. + * + * @addtogroup MU_HAL (HAL) MU Hardware Abstraction Layer + * + * Module for low-level MU hardware access. + * + * @{ + */ + +#ifndef __FSL_MU_HAL_H__ +#define __FSL_MU_HAL_H__ + +#include +#ifdef DEBUG +#include +#else +#define assert(x) ((void) 0) +#endif +#include +#if FSL_FEATURE_SOC_MU_COUNT + +/* Defines */ + +/*! + * This define is used to access MU registers. + */ +#define DSC_MU_BASE_ADDR(X, Y) ((MU_Type *) (((uint32_t) DSC_BASE_ADDR(X)) \ + + 0xC000 + (0x80 * Y))) + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*!@brief Bit mask for general purpose interrupt 0 pending. */ +#define MU_SR_GIP0_MASK (1U<<31U) +/*!@brief Bit mask for RX full interrupt 0 pending. */ +#define MU_SR_RF0_MASK (1U<<27U) +/*!@brief Bit mask for TX empty interrupt 0 pending. */ +#define MU_SR_TE0_MASK (1U<<23U) +/*!@brief Bit mask for general purpose interrupt 0 enable. */ +#define MU_CR_GIE0_MASK (1U<<31U) +/*!@brief Bit mask for RX full interrupt 0 enable. */ +#define MU_CR_RIE0_MASK (1U<<27U) +/*!@brief Bit mask for TX empty interrupt 0 enable. */ +#define MU_CR_TIE0_MASK (1U<<23U) +/*!@brief Bit mask to trigger general purpose interrupt 0. */ +#define MU_CR_GIR0_MASK (1U<<19U) + +/*!@brief Number of general purpose interrupt. */ +#define MU_GPn_COUNT (4U) + +/* Mask for MU_CR_GIRN and MU_CR_NMI. When read-modify-write to MU_CR, should + pay attention to these bits in case of trigger interrupts by mistake.*/ +#define MU_CR_GIRn_NMI_MASK (MU_CR_GIRn_MASK | MU_CR_NMI_MASK) + +/*! + * @brief MU status return codes. + */ +typedef enum _mu_status { + kStatus_MU_Success = 0U, /*!< Success. */ + kStatus_MU_TxNotEmpty = 1U, /*!< TX register is not empty. */ + kStatus_MU_RxNotFull = 2U, /*!< RX register is not full. */ + kStatus_MU_FlagPending = 3U, /*!< Previous flags update pending. */ + kStatus_MU_EventPending = 4U, /*!< MU event is pending. */ + kStatus_MU_Initialized = 5U, /*!< MU driver has initialized previously. */ + kStatus_MU_IntPending = 6U, /*!< Previous general interrupt still pending. */ + kStatus_MU_Failed = 7U /*!< Execution failed. */ +} mu_status_t; + +/*! + * @brief MU message status. + */ +typedef enum _mu_msg_status { + kMuTxEmpty0 = MU_SR_TE0_MASK, /*!< TX0 empty status. */ + kMuTxEmpty1 = MU_SR_TE0_MASK >> 1U, /*!< TX1 empty status. */ + kMuTxEmpty2 = MU_SR_TE0_MASK >> 2U, /*!< TX2 empty status. */ + kMuTxEmpty3 = MU_SR_TE0_MASK >> 3U, /*!< TX3 empty status. */ + kMuTxEmpty = kMuTxEmpty0 | + kMuTxEmpty1 | + kMuTxEmpty2 | + kMuTxEmpty3, /*!< TX empty status. */ + + kMuRxFull0 = MU_SR_RF0_MASK, /*!< RX0 full status. */ + kMuRxFull1 = MU_SR_RF0_MASK >> 1U, /*!< RX1 full status. */ + kMuRxFull2 = MU_SR_RF0_MASK >> 2U, /*!< RX2 full status. */ + kMuRxFull3 = MU_SR_RF0_MASK >> 3U, /*!< RX3 full status. */ + kMuRxFull = kMuRxFull0 | + kMuRxFull1 | + kMuRxFull2 | + kMuRxFull3, /*!< RX empty status. */ + + kMuGenInt0 = MU_SR_GIP0_MASK, /*!< General purpose interrupt 0 pending status. */ + kMuGenInt1 = MU_SR_GIP0_MASK >> 1U, /*!< General purpose interrupt 2 pending status. */ + kMuGenInt2 = MU_SR_GIP0_MASK >> 2U, /*!< General purpose interrupt 2 pending status. */ + kMuGenInt3 = MU_SR_GIP0_MASK >> 3U, /*!< General purpose interrupt 3 pending status. */ + kMuGenInt = kMuGenInt0 | + kMuGenInt1 | + kMuGenInt2 | + kMuGenInt3, /*!< General purpose interrupt pending status. */ + + kMuStatusAll = kMuTxEmpty | + kMuRxFull | + kMuGenInt, /*!< All MU status. */ + +} mu_msg_status_t; + +/*! + * @brief Core boot configuration. + */ +typedef enum _mu_core_boot_config { + kMuCoreBootFromDmem = 0x01U, /*!< Boot from DMEM base. */ + kMuCoreBootFromImem = 0x02U, /*!< Boot from IMEM base. */ + kMuCoreBootFrom0 = 0x03U, /*!< Boot from 0x00. */ +} mu_core_boot_config_t; + +/*! + * @brief Power mode definition. + */ +typedef enum _mu_power_mode { + kMuPowerModeRun = 0x00U, /*!< Run mode. */ + kMuPowerModeWait = 0x01U, /*!< WAIT mode. */ + kMuPowerModeStop = 0x02U, /*!< STOP mode. */ + kMuPowerModeDsm = 0x03U, /*!< DSM mode. */ +} mu_power_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization Functions + * @{ + */ +/*! + * @brief Initializes the MU module to reset state. + * + * This function sets the MU module control register to its default reset value. + * + * @param base Register base address for the module. + */ +static inline void MU_HAL_Init(MU_Type *base) +{ + /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ + MU_WR_CR(base, (MU_RD_CR(base) + & ~(MU_CR_GIEn_MASK | + MU_CR_RIEn_MASK | + MU_CR_TIEn_MASK | + MU_CR_GIRn_MASK | + MU_CR_Fn_MASK))); +} + +/* @} */ + +/*! + * @name Send Message Functions + * @{ + */ + +/*! + * @brief Try to send a message. + * + * This function tries to send a message, if the RX register is not empty, + * this function returns kStatus_MU_TxNotEmpty. + * + * @param base Register base address for the module. + * @param regIdex Tx register index. + * @param msg Message to send. + * @retval kStatus_MU_Success Message send successfully. + * @retval kStatus_MU_TxNotEmpty Message not send because TX is not empty. + */ +mu_status_t MU_HAL_TrySendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg); + +/*! + * @brief Block to send a message. + * + * This function waits until TX register is empty and send the message. + * + * @param base Register base address for the module. + * @param regIdex Tx register index. + * @param msg Message to send. + */ +void MU_HAL_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg); + +/*! + * @brief Check TX empty status. + * + * This function checks the specific tramsmit register empty status. + * + * @param base Register base address for the module. + * @param index TX register index to check. + * @retval true TX register is empty. + * @retval false TX register is not empty. + */ +static inline bool MU_HAL_IsTxEmpty(MU_Type *base, uint32_t index) +{ + return (bool)(MU_RD_SR(base) & (MU_SR_TE0_MASK >> index)); +} + +/*! + * @brief Enable TX empty interrupt. + * + * This function enables specific TX empty interrupt. + * + * @param base Register base address for the module. + * @param index TX interrupt index to enable. + * + * Example: + @code + // To enable TX0 empty interrupts. + MU_HAL_EnableTxEmptyInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_HAL_EnableTxEmptyInt(MU_Type *base, uint32_t index) +{ + MU_WR_CR(base, (MU_RD_CR(base) + & ~MU_CR_GIRn_NMI_MASK) /* Clear GIRn and NMI */ + | (MU_CR_TIE0_MASK>>index)); /* Set TIEn */ +} + +/*! + * @brief Disable TX empty interrupt. + * + * This function disables specific TX empty interrupt. + * + * @param base Register base address for the module. + * @param disableMask Bitmap of the interrupts to disable. + * + * Example: + @code + // To disable TX0 empty interrupts. + MU_HAL_DisableTxEmptyInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_HAL_DisableTxEmptyInt(MU_Type *base, uint32_t index) +{ + MU_WR_CR(base, (MU_RD_CR(base) + & ~MU_CR_GIRn_NMI_MASK) /* Clear GIRn and NMI */ + & ~(MU_CR_TIE0_MASK>>index)); /* Clear TIEn */ +} + +/* @} */ + +/*! + * @name Receive Message Functions + * @{ + */ + +/*! + * @brief Try to receive a message. + * + * This function tries to receive a message, if the RX register is not full, + * this function returns kStatus_MU_RxNotFull. + * + * @param base Register base address for the module. + * @param regIdex Rx register index. + * @param msg Message to receive. + * @retval kStatus_MU_Success Message receive successfully. + * @retval kStatus_MU_RxNotFull Message not received because RX is not full. + */ +mu_status_t MU_HAL_TryReceiveMsg(MU_Type *base, uint32_t regIndex, uint32_t *msg); + +/*! + * @brief Block to receive a message. + * + * This function waits until RX register is full and receive the message. + * + * @param base Register base address for the module. + * @param regIdex Rx register index. + * @param msg Message to receive. + */ +void MU_HAL_ReceiveMsg(MU_Type *base, uint32_t regIndex, uint32_t *msg); + +/*! + * @brief Check RX full status. + * + * This function checks the specific receive register full status. + * + * @param base Register base address for the module. + * @param index RX register index to check. + * @retval true RX register is full. + * @retval false RX register is not full. + */ +static inline bool MU_HAL_IsRxFull(MU_Type *base, uint32_t index) +{ + return (bool)(MU_RD_SR(base) & (MU_SR_RF0_MASK >> index)); +} + +/*! + * @brief Enable RX full interrupt. + * + * This function enables specific RX full interrupt. + * + * @param base Register base address for the module. + * @param index RX interrupt index to enable. + * + * Example: + @code + // To enable RX0 full interrupts. + MU_HAL_EnableRxFullInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_HAL_EnableRxFullInt(MU_Type *base, uint32_t index) +{ + MU_WR_CR(base, (MU_RD_CR(base) + & ~MU_CR_GIRn_NMI_MASK) /* Clear GIRn and NMI */ + | (MU_CR_RIE0_MASK>>index)); /* Set RIEn */ +} + +/*! + * @brief Disable RX full interrupt. + * + * This function disables specific RX full interrupt. + * + * @param base Register base address for the module. + * @param disableMask Bitmap of the interrupts to disable. + * + * Example: + @code + // To disable RX0 full interrupts. + MU_HAL_DisableRxFullInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_HAL_DisableRxFullInt(MU_Type *base, uint32_t index) +{ + MU_WR_CR(base, (MU_RD_CR(base) + & ~MU_CR_GIRn_NMI_MASK) /* Clear GIRn and NMI */ + & ~(MU_CR_RIE0_MASK>>index)); /* Clear RIEn */ +} + +/* @} */ + +/*! + * @name General Purpose Interrupt Functions + * @{ + */ + +/*! + * @brief Enable general purpose interrupt. + * + * This function enables specific general purpose interrupt. + * + * @param base Register base address for the module. + * @param index General purpose interrupt index to enable. + * + * Example: + @code + // To enable general purpose interrupts 0. + MU_HAL_EnableGeneralInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_HAL_EnableGeneralInt(MU_Type *base, uint32_t index) +{ + MU_WR_CR(base, (MU_RD_CR(base) + & ~MU_CR_GIRn_NMI_MASK) /* Clear GIRn and NMI */ + | (MU_CR_GIE0_MASK>>index)); /* Set GIEn */ +} + +/*! + * @brief Disable general purpose interrupt. + * + * This function disables specific general purpose interrupt. + * + * @param base Register base address for the module. + * @param index General purpose interrupt index to disable. + * + * Example: + @code + // To disable general purpose interrupts 0. + MU_HAL_DisableGeneralInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_HAL_DisableGeneralInt(MU_Type *base, uint32_t index) +{ + MU_WR_CR(base, (MU_RD_CR(base) + & ~MU_CR_GIRn_NMI_MASK) /* Clear GIRn and NMI */ + & ~(MU_CR_GIE0_MASK>>index)); /* Clear GIEn */ +} + +/*! + * @brief Check specific general purpose interrupt pending flag. + * + * This function checks the specific general purpose interrupt pending status. + * + * @param base Register base address for the module. + * @param index Index of the general purpose interrupt flag to check. + * @retval true General purpose interrupt is pending. + * @retval false General purpose interrupt is not pending. + */ +static inline bool MU_HAL_IsGeneralIntPending(MU_Type *base, uint32_t index) +{ + return (bool)(MU_RD_SR(base) & (MU_SR_GIP0_MASK >> index)); +} + +/*! + * @brief Clear specific general purpose interrupt pending flag. + * + * This function clears the specific general purpose interrupt pending status. + * + * @param base Register base address for the module. + * @param index Index of the general purpose interrupt flag to clear. + */ +static inline void MU_HAL_ClearGeneralIntPending(MU_Type *base, uint32_t index) +{ + MU_WR_SR(base, MU_SR_GIP0_MASK >> index); +} + +/*! + * @brief Trigger specific general purpose interrupt. + * + * This function triggers specific general purpose interrupt to other core. + * + * To ensure proper operations, please make sure the correspond general purpose + * interrupt triggerd previously has been accepted by the other core. The + * function MU_HAL_IsGeneralIntAccepted could be used for this check. If the + * previous general interrupt has not been accepted by the other core, this + * function does not trigger interrupt acctually and returns error. + * + * @param base Register base address for the module. + * @param index Index of general purpose interrupt to trigger. + * @retval kStatus_MU_Success Interrupt has been triggered successfully. + * @retval kStatus_MU_IntPending Previous interrupt has not been accepted. + */ +mu_status_t MU_HAL_TriggerGeneralInt(MU_Type *base, uint32_t index); + +/*! + * @brief Check specific general purpose interrupt is accepted or not. + * + * This function checks whether the specific general purpose interrupt has + * been accepted by the other core or not. + * + * @param base Register base address for the module. + * @param index Index of the general purpose interrupt to check. + * @retval true General purpose interrupt is accepted. + * @retval false General purpose interrupt is not accepted. + */ +static inline bool MU_HAL_IsGeneralIntAccepted(MU_Type *base, uint32_t index) +{ + return !(bool)(MU_RD_CR(base) & (MU_CR_GIR0_MASK >> index)); +} + +/* @} */ + +/*! + * @name Non-maskable Interrupt (NMI) Functions + * @{ + */ + +/*! + * @brief Trigger non-maskable interrupt (NMI) to the other core. + * + * This functions triggers the NMI to the other core. + * + * @param base Register base address for the module. + */ +static inline void MU_HAL_TriggerNmi(MU_Type *base) +{ + MU_WR_CR_NMI(base, 1U); +} + +/*! + * @brief Get non-maskable interrupt (NMI) trigger status. + * + * This functions get the NMI trigger status. It is used to check whether the NMI + * triggered by the function MU_HAL_TriggerNmi has been accepted by the other + * core. When the NMI has been accepted by the other core, MU_HAL_TriggerNmi + * could be used to trigger another NMI. + * + * @param base Register base address for the module. + * @retval true NMI is issued and not accepted by the other core. + * @retval false NMI is not issued or has been accepted by the other core. + */ +static inline bool MU_HAL_IsNmiIssued(MU_Type *base) +{ + return (bool)MU_RD_CR_NMI(base); +} + +/* @} */ + +/*! + * @name Flag Functions + * @{ + */ + +/*! + * @brief Try to set some bits of the 3-bit flag reflect on the other MU side. + * + * This functions tries to set some bits of the 3-bit flag. If previous flags + * update is still pending, this function returns kStatus_MU_FlagPending. + * + * @param base Register base address for the module. + * @retval kStatus_MU_Success Flag set successfully. + * @retval kStatus_MU_FlagPending Previous flag update is pending. + */ +mu_status_t MU_HAL_TrySetFlags(MU_Type *base, uint32_t flags); + +/*! + * @brief Set some bits of the 3-bit flag reflect on the other MU side. + * + * This functions set some bits of the 3-bit flag. If previous flags update is + * still pending, this function will block and poll to set the flag. + * + * @param base Register base address for the module. + */ +void MU_HAL_SetFlags(MU_Type *base, uint32_t flags); + +/*! + * @brief Checks whether the previous flag update is pending. + * + * After setting flags, the flags update request is pending untill internally + * acknowledged. During the pending period, it is not allowed to set flags again. + * This function is used to check the pending status, it could be used together + * with function MU_HAL_TrySetFlags. + * + * @param base Register base address for the module. + * @return True if pending, faulse if not. + */ +static inline bool MU_HAL_IsFlagPending(MU_Type *base) +{ + return (bool)MU_RD_SR_FUP(base); +} + +/*! + * @brief Get the current value of the 3-bit flag set by other side. + * + * This functions gets the current value of the 3-bit flag. + * + * @param base Register base address for the module. + * @return flags Current value of the 3-bit flag. + */ +static inline uint32_t MU_HAL_GetFlags(MU_Type *base) +{ + return MU_RD_SR_Fn(base); +} + +/* @} */ + +/*! + * @name Misc. Functions + * @{ + */ + +/*! + * @brief Reset MU for both A side and B side. + * + * This function resets MU for both A side and B side. Before reset, it is + * recommend to interrupt processor B, because this function may affect the + * ongoing processor B program. + * + * @param base Register base address for the module. + * @note Only MU side A could use this function. + */ +static inline void MU_HAL_Reset(MU_Type *base) +{ + MU_WR_CR_MUR(base, 1U); +} + +/*! + * @brief Get the power mode of the other core. + * + * This functions gets the power mode of the other core. + * + * @param base Register base address for the module. + * @return powermode Power mode of the other core. + */ +static inline mu_power_mode_t MU_HAL_GetOtherCorePowerMode(MU_Type *base) +{ + return (mu_power_mode_t)MU_RD_SR_PM(base); +} + +/*! + * @brief Get the event pending status. + * + * This functions gets the event pending status. To ensure events have been + * posted to the other side before entering STOP mode, please verify the + * event pending status using this function. + * + * @param base Register base address for the module. + * @retval true Event is pending. + * @retval false Event is not pending. + */ +static inline bool MU_HAL_IsEventPending(MU_Type *base) +{ + return (bool)MU_RD_SR_EP(base); +} + +/*! + * @brief Get the the MU message status. + * + * This functions gets TX/RX and general purpose interrupt pending status. The + * parameter is passed in as bitmask of the status to check. + * + * @param base Register base address for the module. + * @param statusToCheck The status to check, see mu_msg_status_t. + * @return Status checked. + * + * Example: + @code + // To check TX0 empty status. + MU_HAL_GetMsgStatus(MU0_BASE, kMuTxEmpty0); + + // To check all RX full status. + MU_HAL_GetMsgStatus(MU0_BASE, kMuRxFull); + + // To check general purpose interrupt 0 and 3 pending status. + MU_HAL_GetMsgStatus(MU0_BASE, kMuGenInt0 | kMuGenInt3); + + // To check all status. + MU_HAL_GetMsgStatus(MU0_BASE, kMuStatusAll); + + @endcode + */ +static inline uint32_t MU_HAL_GetMsgStatus(MU_Type *base, uint32_t statusToCheck) +{ + return MU_RD_SR(base) & statusToCheck; +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif +#endif /* __FSL_MU_HAL_H__ */ + +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/arch/arm/include/asm/arch-imx8/gpio.h b/arch/arm/include/asm/arch-imx8/gpio.h new file mode 100644 index 00000000000..51aa9e862f3 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/gpio.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX8_GPIO_H +#define __ASM_ARCH_IMX8_GPIO_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +/* GPIO registers */ +struct gpio_regs { + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ + u32 gpio_psr; /* pad satus */ +}; +#endif + +/* IMX8 the GPIO index is from 0 not 1 */ +#define IMX_GPIO_NR(port, index) (((port)*32)+((index)&31)) + +#endif /* __ASM_ARCH_IMX8_GPIO_H */ diff --git a/arch/arm/include/asm/arch-imx8/i2c.h b/arch/arm/include/asm/arch-imx8/i2c.h new file mode 100644 index 00000000000..4b1bd4ba278 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/i2c.h @@ -0,0 +1,47 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#ifndef __ASM_ARCH_IMX8_I2C_H__ +#define __ASM_ARCH_IMX8_I2C_H__ + +#include +#include + +struct imx_i2c_map { + unsigned index; + sc_rsrc_t rsrc; + u32 lpcg[4]; +}; + +static struct imx_i2c_map imx_i2c_desc[] = { + {0, SC_R_I2C_0, {LPI2C_0_LPCG}}, + {1, SC_R_I2C_1, {LPI2C_1_LPCG}}, + {2, SC_R_I2C_2, {LPI2C_2_LPCG}}, + {3, SC_R_I2C_3, {LPI2C_3_LPCG}}, +#ifdef CONFIG_IMX8QM + {4, SC_R_I2C_4, {LPI2C_4_LPCG}}, +#endif + {5, SC_R_LVDS_0_I2C_0, {DI_LVDS_0_LPCG + 0x10}}, /* lvds0 i2c0 */ + {6, SC_R_LVDS_0_I2C_0, {DI_LVDS_0_LPCG + 0x10}}, /* lvds0 i2c1 */ + {7, SC_R_LVDS_1_I2C_0, {DI_LVDS_1_LPCG + 0x10}}, /* lvds1 i2c0 */ + {8, SC_R_LVDS_1_I2C_0, {DI_LVDS_1_LPCG + 0x10}}, /* lvds1 i2c1 */ + {9, SC_R_CSI_0_I2C_0, {MIPI_CSI_0_LPCG + 0x14}}, + {10, SC_R_CSI_1_I2C_0, {MIPI_CSI_1_LPCG + 0x14}}, + {11, SC_R_HDMI_I2C_0, {DI_HDMI_LPCG}}, + {12, SC_R_HDMI_RX_I2C_0, {RX_HDMI_LPCG + 0x10, RX_HDMI_LPCG + 0x14, RX_HDMI_LPCG + 0x18, RX_HDMI_LPCG + 0x1C}}, +#ifdef CONFIG_IMX8QM + {13, SC_R_MIPI_0_I2C_0, {MIPI_DSI_0_LPCG + 0x14, MIPI_DSI_0_LPCG + 0x18, MIPI_DSI_0_LPCG + 0x1c}}, + {14, SC_R_MIPI_0_I2C_1, {MIPI_DSI_0_LPCG + 0x24, MIPI_DSI_0_LPCG + 0x28, MIPI_DSI_0_LPCG + 0x2c}}, + {15, SC_R_MIPI_1_I2C_0, {MIPI_DSI_1_LPCG + 0x14, MIPI_DSI_1_LPCG + 0x18, MIPI_DSI_1_LPCG + 0x1c}}, + {16, SC_R_MIPI_1_I2C_1, {MIPI_DSI_1_LPCG + 0x24, MIPI_DSI_1_LPCG + 0x28, MIPI_DSI_1_LPCG + 0x2c}}, +#else + {13, SC_R_MIPI_0_I2C_0, {DI_MIPI0_LPCG + 0x10}}, + {14, SC_R_MIPI_0_I2C_1, {DI_MIPI0_LPCG + 0x14}}, + {15, SC_R_MIPI_1_I2C_0, {DI_MIPI1_LPCG + 0x10}}, + {16, SC_R_MIPI_1_I2C_1, {DI_MIPI1_LPCG + 0x14}}, +#endif +}; +#endif /* __ASM_ARCH_IMX8_I2C_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/image.h b/arch/arm/include/asm/arch-imx8/image.h new file mode 100644 index 00000000000..2b21f8878ea --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/image.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define IV_MAX_LEN 32 +#define HASH_MAX_LEN 64 + +#define CONTAINER_HDR_ALIGNMENT 0x400 +#define CONTAINER_HDR_EMMC_OFFSET 0 +#define CONTAINER_HDR_MMCSD_OFFSET SZ_32K +#define CONTAINER_HDR_QSPI_OFFSET SZ_4K +#define CONTAINER_HDR_NAND_OFFSET SZ_128M + + struct container_hdr{ + uint8_t version; + uint8_t length_lsb; + uint8_t length_msb; + uint8_t tag; + uint32_t flags; + uint16_t sw_version; + uint8_t fuse_version; + uint8_t num_images; + uint16_t sig_blk_offset; + uint16_t reserved; + }__attribute__((packed)); + + struct boot_img_t{ + uint32_t offset; + uint32_t size; + uint64_t dst; + uint64_t entry; + uint32_t hab_flags; + uint32_t meta; + uint8_t hash[HASH_MAX_LEN]; + uint8_t iv[IV_MAX_LEN]; + }__attribute__((packed)); + + struct signature_block_hdr{ + uint8_t version; + uint8_t length_lsb; + uint8_t length_msb; + uint8_t tag; + uint16_t srk_table_offset; + uint16_t cert_offset; + uint16_t blob_offset; + uint16_t signature_offset; + uint32_t reserved; + }__attribute__((packed)); diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h new file mode 100644 index 00000000000..e3d3e2b5048 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -0,0 +1,142 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_IMX_REGS_H__ +#define __ASM_ARCH_IMX_REGS_H__ + +#define MU_BASE_ADDR(id) ((0x5D1B0000UL + (id*0x10000))) + +#define LPUART_BASE 0x5A060000 + +#define GPT1_BASE_ADDR 0x5D140000 +#define SCU_LPUART_BASE 0x33220000 +#define GPIO1_BASE_ADDR 0x5D080000 +#define GPIO2_BASE_ADDR 0x5D090000 +#define GPIO3_BASE_ADDR 0x5D0A0000 +#define GPIO4_BASE_ADDR 0x5D0B0000 +#define GPIO5_BASE_ADDR 0x5D0C0000 +#define GPIO6_BASE_ADDR 0x5D0D0000 +#define GPIO7_BASE_ADDR 0x5D0E0000 +#define GPIO8_BASE_ADDR 0x5D0F0000 +#define LPI2C1_BASE_ADDR 0x5A800000 +#define LPI2C2_BASE_ADDR 0x5A810000 +#define LPI2C3_BASE_ADDR 0x5A820000 +#define LPI2C4_BASE_ADDR 0x5A830000 +#define LPI2C5_BASE_ADDR 0x5A840000 + +#ifdef CONFIG_IMX8QXP +#define LVDS0_PHYCTRL_BASE 0x56221000 +#define LVDS1_PHYCTRL_BASE 0x56241000 +#define MIPI0_SS_BASE 0x56220000 +#define MIPI1_SS_BASE 0x56240000 +#endif + +#ifdef CONFIG_IMX8QM +#define LVDS0_PHYCTRL_BASE 0x56241000 +#define LVDS1_PHYCTRL_BASE 0x57241000 +#define MIPI0_SS_BASE 0x56220000 +#define MIPI1_SS_BASE 0x57220000 +#endif + +#ifdef CONFIG_LPUART +#define LPUART_BASE SCU_LPUART_BASE +#endif + +#define APBH_DMA_ARB_BASE_ADDR 0x5B810000 +#define APBH_DMA_ARB_END_ADDR 0x5B81FFFF +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + +#define PASS_OVER_INFO_ADDR 0x0010fe00 + +#define USB_BASE_ADDR 0x5b0d0000 +#define USB_PHY0_BASE_ADDR 0x5b100000 + +#define CAAM_ARB_BASE_ADDR (0x31800000) +#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000) + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#include + +bool is_usb_boot(void); +void disconnect_from_pc(void); +#define is_boot_from_usb is_usb_boot + +struct usbphy_regs { + u32 usbphy_pwd; /* 0x000 */ + u32 usbphy_pwd_set; /* 0x004 */ + u32 usbphy_pwd_clr; /* 0x008 */ + u32 usbphy_pwd_tog; /* 0x00c */ + u32 usbphy_tx; /* 0x010 */ + u32 usbphy_tx_set; /* 0x014 */ + u32 usbphy_tx_clr; /* 0x018 */ + u32 usbphy_tx_tog; /* 0x01c */ + u32 usbphy_rx; /* 0x020 */ + u32 usbphy_rx_set; /* 0x024 */ + u32 usbphy_rx_clr; /* 0x028 */ + u32 usbphy_rx_tog; /* 0x02c */ + u32 usbphy_ctrl; /* 0x030 */ + u32 usbphy_ctrl_set; /* 0x034 */ + u32 usbphy_ctrl_clr; /* 0x038 */ + u32 usbphy_ctrl_tog; /* 0x03c */ + u32 usbphy_status; /* 0x040 */ + u32 reserved0[3]; + u32 usbphy_debug0; /* 0x050 */ + u32 usbphy_debug0_set; /* 0x054 */ + u32 usbphy_debug0_clr; /* 0x058 */ + u32 usbphy_debug0_tog; /* 0x05c */ + u32 reserved1[4]; + u32 usbphy_debug1; /* 0x070 */ + u32 usbphy_debug1_set; /* 0x074 */ + u32 usbphy_debug1_clr; /* 0x078 */ + u32 usbphy_debug1_tog; /* 0x07c */ + u32 usbphy_version; /* 0x080 */ + u32 reserved2[7]; + u32 usb1_pll_480_ctrl; /* 0x0a0 */ + u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ + u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ + u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ + u32 reserved3[4]; + u32 usb1_vbus_detect; /* 0xc0 */ + u32 usb1_vbus_detect_set; /* 0xc4 */ + u32 usb1_vbus_detect_clr; /* 0xc8 */ + u32 usb1_vbus_detect_tog; /* 0xcc */ + u32 usb1_vbus_det_stat; /* 0xd0 */ + u32 reserved4[3]; + u32 usb1_chrg_detect; /* 0xe0 */ + u32 usb1_chrg_detect_set; /* 0xe4 */ + u32 usb1_chrg_detect_clr; /* 0xe8 */ + u32 usb1_chrg_detect_tog; /* 0xec */ + u32 usb1_chrg_det_stat; /* 0xf0 */ + u32 reserved5[3]; + u32 usbphy_anactrl; /* 0x100 */ + u32 usbphy_anactrl_set; /* 0x104 */ + u32 usbphy_anactrl_clr; /* 0x108 */ + u32 usbphy_anactrl_tog; /* 0x10c */ + u32 usb1_loopback; /* 0x110 */ + u32 usb1_loopback_set; /* 0x114 */ + u32 usb1_loopback_clr; /* 0x118 */ + u32 usb1_loopback_tog; /* 0x11c */ + u32 usb1_loopback_hsfscnt; /* 0x120 */ + u32 usb1_loopback_hsfscnt_set; /* 0x124 */ + u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ + u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ + u32 usphy_trim_override_en; /* 0x130 */ + u32 usphy_trim_override_en_set; /* 0x134 */ + u32 usphy_trim_override_en_clr; /* 0x138 */ + u32 usphy_trim_override_en_tog; /* 0x13c */ + u32 usb1_pfda_ctrl1; /* 0x140 */ + u32 usb1_pfda_ctrl1_set; /* 0x144 */ + u32 usb1_pfda_ctrl1_clr; /* 0x148 */ + u32 usb1_pfda_ctrl1_tog; /* 0x14c */ +}; +#endif + +#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/imx8-pins.h b/arch/arm/include/asm/arch-imx8/imx8-pins.h new file mode 100644 index 00000000000..2b12269deba --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8-pins.h @@ -0,0 +1,18 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX8_PINS_H__ +#define __ASM_ARCH_IMX8_PINS_H__ + +#if defined(CONFIG_IMX8QM) +#include "imx8qm_pads.h" +#elif defined(CONFIG_IMX8QXP) +#include "imx8qxp_pads.h" +#else +#error "No pin header" +#endif + +#endif /* __ASM_ARCH_IMX8_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/imx8_lvds.h b/arch/arm/include/asm/arch-imx8/imx8_lvds.h new file mode 100644 index 00000000000..68fbf6d41e6 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8_lvds.h @@ -0,0 +1,115 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMX8_LVDS_H_ +#define _IMX8_LVDS_H_ + +#define IMX_LVDS_SET_FIELD(__field__, __value__) (((__value__) << (__field__ ## _SHIFT)) & (__field__ ## _MASK)) +#define IMX_LVDS_GET_FIELD(__field__, __reg__) (((__reg__) & (__field__ ## _MASK)) >> (__field__ ## _SHIFT)) + +#define IMX_LVDS_SET(__reg__) (reg+0x4) +#define IMX_LVDS_CLEAR(__reg__) (reg+0x8) +#define IMX_LVDS_TOGGLE(__reg__)(reg+0x4) + +#define LVDS_CTRL 0x0e0 +#define LVDS_CTRL_CH0_MODE_MASK 0x03U +#define LVDS_CTRL_CH0_MODE_SHIFT 0U +#define LVDS_CTRL_CH0_MODE__DISABLED 0x00U +#define LVDS_CTRL_CH0_MODE__DI0 0x01U +#define LVDS_CTRL_CH0_MODE__RESERVED 0x02U +#define LVDS_CTRL_CH0_MODE__DI1 0x03U + +#define LVDS_CTRL_CH1_MODE_MASK 0x0cU +#define LVDS_CTRL_CH1_MODE_SHIFT 2U +#define LVDS_CTRL_CH1_MODE__DISABLED 0x00U +#define LVDS_CTRL_CH1_MODE__DI0 0x01U +#define LVDS_CTRL_CH1_MODE__RESERVED 0x02U +#define LVDS_CTRL_CH1_MODE__DI1 0x03U + +#define LVDS_CTRL_SPLIT_MODE_MASK 0x10U +#define LVDS_CTRL_SPLIT_MODE_SHIFT 4U +#define LVDS_CTRL_SPLIT_MODE__DISABLE 0x00U +#define LVDS_CTRL_SPLIT_MODE__ENABLE 0x01U + +#define LVDS_CTRL_CH0_DATA_WIDTH_MASK 0x20U +#define LVDS_CTRL_CH0_DATA_WIDTH_SHIFT 5U +#define LVDS_CTRL_CH0_DATA_WIDTH__18BIT 0x00U +#define LVDS_CTRL_CH0_DATA_WIDTH__24BIT 0x01U + +#define LVDS_CTRL_CH0_BIT_MAP_MASK 0x40U +#define LVDS_CTRL_CH0_BIT_MAP_SHIFT 6U +#define LVDS_CTRL_CH0_BIT_MAP__SWWG 0x00U +#define LVDS_CTRL_CH0_BIT_MAP__JEIDA 0x01U + +#define LVDS_CTRL_CH1_DATA_WIDTH_MASK 0x80U +#define LVDS_CTRL_CH1_DATA_WIDTH_SHIFT 7U +#define LVDS_CTRL_CH1_DATA_WIDTH__18BIT 0x00U +#define LVDS_CTRL_CH1_DATA_WIDTH__24BIT 0x01U + +#define LVDS_CTRL_CH1_BIT_MAP_MASK 0x100U +#define LVDS_CTRL_CH1_BIT_MAP_SHIFT 8U +#define LVDS_CTRL_CH1_BIT_MAP__SWWG 0x00U +#define LVDS_CTRL_CH1_BIT_MAP__JEIDA 0x01U + +#define LVDS_CTRL_DI0_VSYNC_POL_MASK 0x200U +#define LVDS_CTRL_DI0_VSYNC_POL_SHIFT 9U +#define LVDS_CTRL_DI0_VSYNC_POL__ACTIVE_LOW 0x00U +#define LVDS_CTRL_DI0_VSYNC_POL__ACTIVE_HIGH 0x01U + +#define LVDS_CTRL_DI1_VSYNC_POL_MASK 0x400U +#define LVDS_CTRL_DI1_VSYNC_POL_SHIFT 10U +#define LVDS_CTRL_DI1_VSYNC_POL__ACTIVE_LOW 0x00U +#define LVDS_CTRL_DI1_VSYNC_POL__ACTIVE_HIGH 0x01U + +#define LVDS_CTRL_CH0_10BIT_ENABLE_MASK 0x400000U +#define LVDS_CTRL_CH0_10BIT_ENABLE_SHIFT 22U +#define LVDS_CTRL_CH0_10BIT_ENABLE__USE_DATA_WIDTH 0x00U +#define LVDS_CTRL_CH0_10BIT_ENABLE__10BIT 0x01U + +#define LVDS_CTRL_CH1_10BIT_ENABLE_MASK 0x800000U +#define LVDS_CTRL_CH1_10BIT_ENABLE_SHIFT 23U +#define LVDS_CTRL_CH1_10BIT_ENABLE__USE_DATA_WIDTH 0x00U +#define LVDS_CTRL_CH1_10BIT_ENABLE__10BIT 0x01U + +#define LVDS_CTRL_DI0_DATA_WIDTH_MASK 0x03000000U +#define LVDS_CTRL_DI0_DATA_WIDTH_SHIFT 24U +#define LVDS_CTRL_DI0_DATA_WIDTH__USE_18BIT 0x00U +#define LVDS_CTRL_DI0_DATA_WIDTH__USE_24BIT 0x1U +#define LVDS_CTRL_DI0_DATA_WIDTH__USE_30BIT 0x2U + +#define LVDS_CTRL_DI1_DATA_WIDTH_MASK 0x0C000000U +#define LVDS_CTRL_DI1_DATA_WIDTH_SHIFT 26U +#define LVDS_CTRL_DI1_DATA_WIDTH__USE_18BIT 0x00U +#define LVDS_CTRL_DI1_DATA_WIDTH__USE_24BIT 0x1U +#define LVDS_CTRL_DI1_DATA_WIDTH__USE_30BIT 0x2U + +#define LVDS_PHY_CTRL (0x0) + +#define LVDS_PHY_CTRL_PD_MASK (1<<0) +#define LVDS_PHY_CTRL_PD_SHIFT (0) +#define LVDS_PHY_CTRL_RFB_MASK (1<<1) +#define LVDS_PHY_CTRL_RFB_SHIFT (1) +#define LVDS_PHY_CTRL_NB_MASK (1<<2) +#define LVDS_PHY_CTRL_NB_SHIFT (2) +#define LVDS_PHY_CTRL_CH0_EN_MASK (1<<3) +#define LVDS_PHY_CTRL_CH0_EN_SHIFT (3) +#define LVDS_PHY_CTRL_CH1_EN_MASK (1<<4) +#define LVDS_PHY_CTRL_CH1_EN_SHIFT (4) + +#define LVDS_PHY_CTRL_TST_MASK (0x3f<<5) +#define LVDS_PHY_CTRL_TST_SHIFT (5) + +#define LVDS_PHY_CTRL_CA_MASK (0x7<<11) +#define LVDS_PHY_CTRL_CA_SHIFT (11) + +#define LVDS_PHY_CTRL_CCM_MASK (0x7<<14) +#define LVDS_PHY_CTRL_CCM_SHIFT (14) + +#define LVDS_PHY_CTRL_M_MASK (0x3<<17) +#define LVDS_PHY_CTRL_M_SHIFT (17) + +#endif /* _IMX8_LVDS_H_ */ diff --git a/arch/arm/include/asm/arch-imx8/imx8_mipi_dsi.h b/arch/arm/include/asm/arch-imx8/imx8_mipi_dsi.h new file mode 100644 index 00000000000..63024f3fc5f --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8_mipi_dsi.h @@ -0,0 +1,394 @@ +/* + * Copyright 2015-2017 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMX8_MIPI_DSI_H_ +#define _IMX8_MIPI_DSI_H_ + +#define MIPI_CSR_OFFSET 0x1000 /* Subsystem Control Status Registers (CSR) */ +#define MIPI_CSR_TX_ULPS 0x0 +#define MIPIv2_CSR_TX_ULPS 0x30 +#define MIPI_CSR_TX_ULPS_VALUE 0x1F + +#define MIPI_CSR_PXL2DPI 0x4 +#define MIPIv2_CSR_PXL2DPI 0x40 + +#define MIPI_CSR_PXL2DPI_16_BIT_PACKED 0x0 +#define MIPI_CSR_PXL2DPI_16_BIT_565_ALIGNED 0x1 +#define MIPI_CSR_PXL2DPI_16_BIT_565_SHIFTED 0x2 +#define MIPI_CSR_PXL2DPI_18_BIT_PACKED 0x3 +#define MIPI_CSR_PXL2DPI_18_BIT_ALIGNED 0x4 +#define MIPI_CSR_PXL2DPI_24_BIT 0x5 + +#define DSI_CMD_BUF_MAXSIZE (128) + +#define MIPI_DSI_OFFSET 0x8000 /* MIPI DSI Controller */ + +/* DPI interface pixel color coding map */ +enum mipi_dsi_dpi_fmt { + MIPI_RGB565_PACKED = 0, + MIPI_RGB565_LOOSELY, + MIPI_RGB565_CONFIG3, + MIPI_RGB666_PACKED, + MIPI_RGB666_LOOSELY, + MIPI_RGB888, +}; + +struct mipi_dsi_context { + char *NAME; + uint32_t REGS_BASE; + uint32_t CSR_REGS_BASE; +}; + +struct dsi_cfg_csr_object { + uint32_t dsi_host_cfg_num_lanes; + uint32_t dsi_host_cfg_noncont_clk; + uint32_t dsi_host_cfg_t_pre; + uint32_t dsi_host_cfg_t_post; + uint32_t dsi_host_cfg_tx_gap; + uint32_t dsi_host_cfg_autoinsert_eotp; + uint32_t dsi_host_cfg_extrcmd_after_eotp; + uint32_t dsi_host_cfg_htx_to_cnt; + uint32_t dsi_host_cfg_lrx_h_to_cnt; + uint32_t dsi_host_cfg_bta_h_to_cnt; + uint32_t dsi_host_cfg_twakeup; +}; + +struct dsi_cfg_dpi_object { + uint32_t dsi_host_cfg_dpi_pxl_payld_size; + uint32_t dsi_host_cfg_dpi_pxl_fifo_send_lev; + uint32_t dsi_host_cfg_dpi_if_color_coding; + uint32_t dsi_host_cfg_dpi_pxl_format; + uint32_t dsi_host_cfg_dpi_vsync_pol; + uint32_t dsi_host_cfg_dpi_hsync_pol; + uint32_t dsi_host_cfg_dpi_video_mode; + uint32_t dsi_host_cfg_dpi_hfp; + uint32_t dsi_host_cfg_dpi_hbp; + uint32_t dsi_host_cfg_dpi_hsa; + uint32_t dsi_host_cfg_dpi_en_mult_pkt; + uint32_t dsi_host_cfg_dpi_vbp; + uint32_t dsi_host_cfg_dpi_vfp; + uint32_t dsi_host_cfg_dpi_bllp_mode; + uint32_t dsi_host_cfg_dpi_null_pkt_bllp; + uint32_t dsi_host_cfg_dpi_vactive; + uint32_t dsi_host_cfg_dpi_vc; +}; + +struct dsi_cfg_pkt_object { + uint32_t dsi_host_pkt_ctrl; + uint32_t dsi_host_send_pkt; + uint32_t dsi_host_irq_mask; + uint32_t dsi_host_irq_mask2; +}; + +struct dsi_cfg_dphy_object { + uint32_t dphy_pd_tx; + uint32_t dphy_m_prg_hs_prepare; + uint32_t dphy_mc_prg_hs_prepare; + uint32_t dphy_m_prg_hs_zero; + uint32_t dphy_mc_prg_hs_zero; + uint32_t dphy_m_prg_hs_trial; + uint32_t dphy_mc_prg_hs_trial; + uint32_t dphy_pd_pll; + uint32_t dphy_tst; + uint32_t dphy_cn; + uint32_t dphy_cm; + uint32_t dphy_co; + uint32_t dphy_lock; + uint32_t dphy_lock_byp; + uint32_t dphy_tx_rcal; + uint32_t dphy_auto_pd_en; + uint32_t dphy_rxlprp; + uint32_t dphy_rxcdrp; +}; + +/* dphy */ +#define DPHY_PD_TX 0x300 +#define DPHY_M_PRG_HS_PREPARE 0x304 +#define DPHY_MC_PRG_HS_PREPARE 0x308 +#define DPHY_M_PRG_HS_ZERO 0x30c +#define DPHY_MC_PRG_HS_ZERO 0x310 +#define DPHY_M_PRG_HS_TRAIL 0x314 +#define DPHY_MC_PRG_HS_TRAIL 0x318 +#define DPHY_PD_PLL 0x31c +#define DPHY_TST 0x320 +#define DPHY_CN 0x324 +#define DPHY_CM 0x328 +#define DPHY_CO 0x32c +#define DPHY_LOCK 0x330 +#define DPHY_LOCK_BYP 0x334 +#define DPHY_RTERM_SEL 0x338 +#define DPHY_AUTO_PD_EN 0x33c +#define DPHY_RXLPRP 0x340 +#define DPHY_RXCDRP 0x344 + +/* host */ +#define HOST_CFG_NUM_LANES 0x0 +#define HOST_CFG_NONCONTINUOUS_CLK 0x4 +#define HOST_CFG_T_PRE 0x8 +#define HOST_CFG_T_POST 0xc +#define HOST_CFG_TX_GAP 0x10 +#define HOST_CFG_AUTOINSERT_EOTP 0x14 +#define HOST_CFG_EXTRA_CMDS_AFTER_EOTP 0x18 +#define HOST_CFG_HTX_TO_COUNT 0x1c +#define HOST_CFG_LRX_H_TO_COUNT 0x20 +#define HOST_CFG_BTA_H_TO_COUNT 0x24 +#define HOST_CFG_TWAKEUP 0x28 +#define HOST_CFG_STATUS_OUT 0x2c +#define HOST_RX_ERROR_STATUS 0x30 + +/* dpi */ +#define DPI_PIXEL_PAYLOAD_SIZE 0x200 +#define DPI_PIXEL_FIFO_SEND_LEVEL 0x204 +#define DPI_INTERFACE_COLOR_CODING 0x208 +#define DPI_PIXEL_FORMAT 0x20c +#define DPI_VSYNC_POLARITY 0x210 +#define DPI_HSYNC_POLARITY 0x214 +#define DPI_VIDEO_MODE 0x218 +#define DPI_HFP 0x21c +#define DPI_HBP 0x220 +#define DPI_HSA 0x224 +#define DPI_ENABLE_MULT_PKTS 0x228 +#define DPI_VBP 0x22c +#define DPI_VFP 0x230 +#define DPI_BLLP_MODE 0x234 +#define DPI_USE_NULL_PKT_BLLP 0x238 +#define DPI_VACTIVE 0x23c +#define DPI_VC 0x240 + +/* apb pkt */ +#define HOST_TX_PAYLOAD 0x280 + +#define HOST_PKT_CONTROL 0x284 +#define HOST_PKT_CONTROL_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_CONTROL_VC(x) (((x) & 0x3) << 16) +#define HOST_PKT_CONTROL_DT(x) (((x) & 0x3f) << 18) +#define HOST_PKT_CONTROL_HS_SEL(x) (((x) & 0x1) << 24) +#define HOST_PKT_CONTROL_BTA_TX(x) (((x) & 0x1) << 25) +#define HOST_PKT_CONTROL_BTA_NO_TX(x) (((x) & 0x1) << 26) + +#define HOST_SEND_PACKET 0x288 +#define HOST_PKT_STATUS 0x28c +#define HOST_PKT_FIFO_WR_LEVEL 0x290 +#define HOST_PKT_FIFO_RD_LEVEL 0x294 +#define HOST_PKT_RX_PAYLOAD 0x298 + +#define HOST_PKT_RX_PKT_HEADER 0x29c +#define HOST_PKT_RX_PKT_HEADER_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_RX_PKT_HEADER_DT(x) (((x) & 0x3f) << 16) +#define HOST_PKT_RX_PKT_HEADER_VC(x) (((x) & 0x3) << 22) + +#define HOST_IRQ_STATUS 0x2a0 +#define HOST_IRQ_STATUS_SM_NOT_IDLE (1 << 0) +#define HOST_IRQ_STATUS_TX_PKT_DONE (1 << 1) +#define HOST_IRQ_STATUS_DPHY_DIRECTION (1 << 2) +#define HOST_IRQ_STATUS_TX_FIFO_OVFLW (1 << 3) +#define HOST_IRQ_STATUS_TX_FIFO_UDFLW (1 << 4) +#define HOST_IRQ_STATUS_RX_FIFO_OVFLW (1 << 5) +#define HOST_IRQ_STATUS_RX_FIFO_UDFLW (1 << 6) +#define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD (1 << 7) +#define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD (1 << 8) +#define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT (1 << 29) +#define HOST_IRQ_STATUS_LP_RX_TIMEOUT (1 << 30) +#define HOST_IRQ_STATUS_HS_TX_TIMEOUT (1 << 31) + +#define HOST_IRQ_STATUS2 0x2a4 +#define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR (1 << 0) +#define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR (1 << 1) +#define HOST_IRQ_STATUS2_CRC_ERR (1 << 2) + +#define HOST_IRQ_MASK 0x2a8 +#define HOST_IRQ_MASK_SM_NOT_IDLE_MASK (1 << 0) +#define HOST_IRQ_MASK_TX_PKT_DONE_MASK (1 << 1) +#define HOST_IRQ_MASK_DPHY_DIRECTION_MASK (1 << 2) +#define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK (1 << 3) +#define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK (1 << 4) +#define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK (1 << 5) +#define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK (1 << 6) +#define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK (1 << 7) +#define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK (1 << 8) +#define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK (1 << 29) +#define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK (1 << 30) +#define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK (1 << 31) + +#define HOST_IRQ_MASK2 0x2ac +#define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK (1 << 0) +#define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK (1 << 1) +#define HOST_IRQ_MASK2_CRC_ERR_MASK (1 << 2) + +/* ------------------------------------- end -------------------------------- */ +#define BITSLICE(x, a, b) (((x) >> (b)) & ((1 << ((a)-(b)+1)) - 1)) + +#ifdef DEBUG +#define W32(reg, val) \ +do {printf("%s():%d reg 0x%p val 0x%08x\n",\ + __func__, __LINE__, reg, val);\ + __raw_writel(val, reg); } while (0) +#else +#define W32(reg, val) __raw_writel(val, reg) +#endif + +#define R32(reg) __raw_readl(reg) + +/* helper functions */ +inline void dsi_host_ctrl_csr_setup(void __iomem *base, + struct dsi_cfg_csr_object *dsi_config, + uint16_t csr_setup_mask) +{ + if (BITSLICE(csr_setup_mask, 0, 0)) + W32(base + HOST_CFG_NUM_LANES, + dsi_config->dsi_host_cfg_num_lanes); + if (BITSLICE(csr_setup_mask, 1, 1)) + W32(base + HOST_CFG_NONCONTINUOUS_CLK, + dsi_config->dsi_host_cfg_noncont_clk); + if (BITSLICE(csr_setup_mask, 2, 2)) + W32(base + HOST_CFG_T_PRE, dsi_config->dsi_host_cfg_t_pre); + if (BITSLICE(csr_setup_mask, 3, 3)) + W32(base + HOST_CFG_T_POST, + dsi_config->dsi_host_cfg_t_post); + if (BITSLICE(csr_setup_mask, 4, 4)) + W32(base + HOST_CFG_TX_GAP, + dsi_config->dsi_host_cfg_tx_gap); + if (BITSLICE(csr_setup_mask, 5, 5)) + W32(base + HOST_CFG_AUTOINSERT_EOTP, + dsi_config->dsi_host_cfg_autoinsert_eotp); + if (BITSLICE(csr_setup_mask, 6, 6)) + W32(base + HOST_CFG_EXTRA_CMDS_AFTER_EOTP, + dsi_config->dsi_host_cfg_extrcmd_after_eotp); + if (BITSLICE(csr_setup_mask, 7, 7)) + W32(base + HOST_CFG_HTX_TO_COUNT, + dsi_config->dsi_host_cfg_htx_to_cnt); + if (BITSLICE(csr_setup_mask, 8, 8)) + W32(base + HOST_CFG_LRX_H_TO_COUNT, + dsi_config->dsi_host_cfg_lrx_h_to_cnt); + if (BITSLICE(csr_setup_mask, 9, 9)) + W32(base + HOST_CFG_BTA_H_TO_COUNT, + dsi_config->dsi_host_cfg_bta_h_to_cnt); + if (BITSLICE(csr_setup_mask, 10, 10)) + W32(base + HOST_CFG_TWAKEUP, + dsi_config->dsi_host_cfg_twakeup); +} + +inline void dsi_host_ctrl_dpi_setup(void __iomem *base, + struct dsi_cfg_dpi_object *dsi_config, + uint32_t dpi_setup_mask) +{ + if (BITSLICE(dpi_setup_mask, 0, 0)) + W32(base + DPI_PIXEL_PAYLOAD_SIZE, + dsi_config->dsi_host_cfg_dpi_pxl_payld_size); + if (BITSLICE(dpi_setup_mask, 1, 1)) + W32(base + DPI_PIXEL_FIFO_SEND_LEVEL, + dsi_config->dsi_host_cfg_dpi_pxl_fifo_send_lev); + if (BITSLICE(dpi_setup_mask, 2, 2)) + W32(base + DPI_INTERFACE_COLOR_CODING, + dsi_config->dsi_host_cfg_dpi_if_color_coding); + if (BITSLICE(dpi_setup_mask, 3, 3)) + W32(base + DPI_PIXEL_FORMAT, + dsi_config->dsi_host_cfg_dpi_pxl_format); + if (BITSLICE(dpi_setup_mask, 4, 4)) + W32(base + DPI_VSYNC_POLARITY, + dsi_config->dsi_host_cfg_dpi_vsync_pol); + if (BITSLICE(dpi_setup_mask, 5, 5)) + W32(base + DPI_HSYNC_POLARITY, + dsi_config->dsi_host_cfg_dpi_hsync_pol); + if (BITSLICE(dpi_setup_mask, 6, 6)) + W32(base + DPI_VIDEO_MODE, + dsi_config->dsi_host_cfg_dpi_video_mode); + if (BITSLICE(dpi_setup_mask, 7, 7)) + W32(base + DPI_HFP, dsi_config->dsi_host_cfg_dpi_hfp); + if (BITSLICE(dpi_setup_mask, 8, 8)) + W32(base + DPI_HBP, dsi_config->dsi_host_cfg_dpi_hbp); + if (BITSLICE(dpi_setup_mask, 9, 9)) + W32(base + DPI_HSA, dsi_config->dsi_host_cfg_dpi_hsa); + if (BITSLICE(dpi_setup_mask, 10, 10)) + W32(base + DPI_ENABLE_MULT_PKTS, + dsi_config->dsi_host_cfg_dpi_en_mult_pkt); + if (BITSLICE(dpi_setup_mask, 11, 11)) + W32(base + DPI_VBP, dsi_config->dsi_host_cfg_dpi_vbp); + if (BITSLICE(dpi_setup_mask, 12, 12)) + W32(base + DPI_VFP, dsi_config->dsi_host_cfg_dpi_vfp); + if (BITSLICE(dpi_setup_mask, 13, 13)) + W32(base + DPI_BLLP_MODE, + dsi_config->dsi_host_cfg_dpi_bllp_mode); + if (BITSLICE(dpi_setup_mask, 14, 14)) + W32(base + DPI_USE_NULL_PKT_BLLP, + dsi_config->dsi_host_cfg_dpi_null_pkt_bllp); + if (BITSLICE(dpi_setup_mask, 15, 15)) + W32(base + DPI_VACTIVE, + dsi_config->dsi_host_cfg_dpi_vactive); + if (BITSLICE(dpi_setup_mask, 16, 16)) + W32(base + DPI_VC, dsi_config->dsi_host_cfg_dpi_vc); +} + +inline void dsi_host_ctrl_pkt_setup(void __iomem *base, + struct dsi_cfg_pkt_object *dsi_config, + uint8_t pkt_setup_mask) +{ + if (BITSLICE(pkt_setup_mask, 0, 0)) + W32(base + HOST_PKT_CONTROL, + dsi_config->dsi_host_pkt_ctrl); + if (BITSLICE(pkt_setup_mask, 2, 2)) + W32(base + HOST_IRQ_MASK, dsi_config->dsi_host_irq_mask); + if (BITSLICE(pkt_setup_mask, 3, 3)) + W32(base + HOST_IRQ_MASK2, dsi_config->dsi_host_irq_mask2); + if (BITSLICE(pkt_setup_mask, 1, 1)) + W32(base + HOST_SEND_PACKET, + dsi_config->dsi_host_send_pkt); +} + +inline void dsi_host_ctrl_dphy_setup(void __iomem *base, + struct dsi_cfg_dphy_object *dsi_config, + uint32_t dphy_setup_mask) +{ + int i; + + if (BITSLICE(dphy_setup_mask, 8, 8)) + W32(base + DPHY_TST, dsi_config->dphy_tst); + if (BITSLICE(dphy_setup_mask, 9, 9)) + W32(base + DPHY_CN, dsi_config->dphy_cn); + if (BITSLICE(dphy_setup_mask, 10, 10)) + W32(base + DPHY_CM, dsi_config->dphy_cm); + if (BITSLICE(dphy_setup_mask, 11, 11)) + W32(base + DPHY_CO, dsi_config->dphy_co); + if (BITSLICE(dphy_setup_mask, 7, 7)) + W32(base + DPHY_PD_PLL, dsi_config->dphy_pd_pll); + /* todo: disable on zebu */ + /*Polling of DPHY Lock status / wait for PLL lock */ + for (i = 0; i < 100; i++) { + u32 lock; + udelay(10); + /*todo: zebu abort when reading DPHY LOCK */ + lock = R32(DPHY_LOCK); + printf("DPHY PLL Lock = 0x%08x\n", lock); + } + /*todo: Need to wait for lock here */ + + if (BITSLICE(dphy_setup_mask, 1, 1)) + W32(base + DPHY_M_PRG_HS_PREPARE, + dsi_config->dphy_m_prg_hs_prepare); + if (BITSLICE(dphy_setup_mask, 2, 2)) + W32(base + DPHY_MC_PRG_HS_PREPARE, + dsi_config->dphy_mc_prg_hs_prepare); + if (BITSLICE(dphy_setup_mask, 3, 3)) + W32(base + DPHY_M_PRG_HS_ZERO, + dsi_config->dphy_m_prg_hs_zero); + if (BITSLICE(dphy_setup_mask, 4, 4)) + W32(base + DPHY_MC_PRG_HS_ZERO, + dsi_config->dphy_mc_prg_hs_zero); + if (BITSLICE(dphy_setup_mask, 5, 5)) + W32(base + DPHY_M_PRG_HS_TRAIL, + dsi_config->dphy_m_prg_hs_trial); + if (BITSLICE(dphy_setup_mask, 6, 6)) + W32(base + DPHY_MC_PRG_HS_TRAIL, + dsi_config->dphy_mc_prg_hs_trial); + if (BITSLICE(dphy_setup_mask, 0, 0)) + W32(base + DPHY_PD_TX, dsi_config->dphy_pd_tx); + if (BITSLICE(dphy_setup_mask, 12, 12)) + W32(base + DPHY_LOCK, dsi_config->dphy_lock); + if (BITSLICE(dphy_setup_mask, 13, 13)) + W32(base + DPHY_LOCK_BYP, dsi_config->dphy_lock_byp); +} +#endif /* _IMX8_MIPI_DSI_H_ */ diff --git a/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h new file mode 100644 index 00000000000..692c27f7d30 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h @@ -0,0 +1,200 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_1_LPCG 0x5AC90000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_4_LPCG 0x5AC40000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define EMVSIM_1_LPCG 0x5A4E0000 +#define EMVSIM_0_LPCG 0x5A4D0000 +#define LPUART_4_LPCG 0x5A4A0000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* MIPI DSI SS */ +#define MIPI_DSI_0_LPCG 0x56223000 +#define MIPI_DSI_1_LPCG 0x57223000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SPDIF_1_LPCG 0x59430000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_HDMI_RX_SAI_0_LPCG 0x59480000 +#define AUD_HDMI_TX_SAI_0_LPCG 0x59490000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_ESAI_1_LPCG 0x59c10000 +#define AUD_SAI_6_LPCG 0x59c20000 +#define AUD_SAI_7_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + +/* CM41 SS */ +#define CM41_I2C_LPCG 0x3B630000 + +#endif diff --git a/arch/arm/include/asm/arch-imx8/imx8qm_pads.h b/arch/arm/include/asm/arch-imx8/imx8qm_pads.h new file mode 100644 index 00000000000..5cd2b767592 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qm_pads.h @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file used to configure SoC pad list. + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/*@{*/ +#define SC_P_SIM0_CLK 0 /*!< DMA.SIM0.CLK, LSIO.GPIO0.IO00 */ +#define SC_P_SIM0_RST 1 /*!< DMA.SIM0.RST, LSIO.GPIO0.IO01 */ +#define SC_P_SIM0_IO 2 /*!< DMA.SIM0.IO, LSIO.GPIO0.IO02 */ +#define SC_P_SIM0_PD 3 /*!< DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */ +#define SC_P_SIM0_POWER_EN 4 /*!< DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */ +#define SC_P_SIM0_GPIO0_00 5 /*!< DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /*!< */ +#define SC_P_M40_I2C0_SCL 7 /*!< M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */ +#define SC_P_M40_I2C0_SDA 8 /*!< M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */ +#define SC_P_M40_GPIO0_00 9 /*!< M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */ +#define SC_P_M40_GPIO0_01 10 /*!< M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */ +#define SC_P_M41_I2C0_SCL 11 /*!< M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */ +#define SC_P_M41_I2C0_SDA 12 /*!< M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */ +#define SC_P_M41_GPIO0_00 13 /*!< M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ +#define SC_P_M41_GPIO0_01 14 /*!< M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ +#define SC_P_GPT0_CLK 15 /*!< LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ +#define SC_P_GPT0_CAPTURE 16 /*!< LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */ +#define SC_P_GPT0_COMPARE 17 /*!< LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ +#define SC_P_GPT1_CLK 18 /*!< LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ +#define SC_P_GPT1_CAPTURE 19 /*!< LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */ +#define SC_P_GPT1_COMPARE 20 /*!< LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ +#define SC_P_UART0_RX 21 /*!< DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */ +#define SC_P_UART0_TX 22 /*!< DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */ +#define SC_P_UART0_RTS_B 23 /*!< DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */ +#define SC_P_UART0_CTS_B 24 /*!< DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */ +#define SC_P_UART1_TX 25 /*!< DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */ +#define SC_P_UART1_RX 26 /*!< DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */ +#define SC_P_UART1_RTS_B 27 /*!< DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */ +#define SC_P_UART1_CTS_B 28 /*!< DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /*!< */ +#define SC_P_SCU_PMIC_MEMC_ON 30 /*!< SCU.GPIO0.IOXX_PMIC_MEMC_ON */ +#define SC_P_SCU_WDOG_OUT 31 /*!< SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SDA 32 /*!< SCU.PMIC_I2C.SDA */ +#define SC_P_PMIC_I2C_SCL 33 /*!< SCU.PMIC_I2C.SCL */ +#define SC_P_PMIC_EARLY_WARNING 34 /*!< SCU.PMIC_EARLY_WARNING */ +#define SC_P_PMIC_INT_B 35 /*!< SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 36 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */ +#define SC_P_SCU_GPIO0_01 37 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */ +#define SC_P_SCU_GPIO0_02 38 /*!< SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */ +#define SC_P_SCU_GPIO0_03 39 /*!< SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */ +#define SC_P_SCU_GPIO0_04 40 /*!< SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */ +#define SC_P_SCU_GPIO0_05 41 /*!< SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */ +#define SC_P_SCU_GPIO0_06 42 /*!< SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */ +#define SC_P_SCU_GPIO0_07 43 /*!< SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */ +#define SC_P_SCU_BOOT_MODE0 44 /*!< SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 45 /*!< SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 46 /*!< SCU.DSC.BOOT_MODE2 */ +#define SC_P_SCU_BOOT_MODE3 47 /*!< SCU.DSC.BOOT_MODE3 */ +#define SC_P_SCU_BOOT_MODE4 48 /*!< SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */ +#define SC_P_SCU_BOOT_MODE5 49 /*!< SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */ +#define SC_P_LVDS0_GPIO00 50 /*!< LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */ +#define SC_P_LVDS0_GPIO01 51 /*!< LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ +#define SC_P_LVDS0_I2C0_SCL 52 /*!< LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ +#define SC_P_LVDS0_I2C0_SDA 53 /*!< LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ +#define SC_P_LVDS0_I2C1_SCL 54 /*!< LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */ +#define SC_P_LVDS0_I2C1_SDA 55 /*!< LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */ +#define SC_P_LVDS1_GPIO00 56 /*!< LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */ +#define SC_P_LVDS1_GPIO01 57 /*!< LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ +#define SC_P_LVDS1_I2C0_SCL 58 /*!< LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */ +#define SC_P_LVDS1_I2C0_SDA 59 /*!< LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */ +#define SC_P_LVDS1_I2C1_SCL 60 /*!< LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */ +#define SC_P_LVDS1_I2C1_SDA 61 /*!< LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /*!< */ +#define SC_P_MIPI_DSI0_I2C0_SCL 63 /*!< MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 64 /*!< MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */ +#define SC_P_MIPI_DSI0_GPIO0_00 65 /*!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */ +#define SC_P_MIPI_DSI0_GPIO0_01 66 /*!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 67 /*!< MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 68 /*!< MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */ +#define SC_P_MIPI_DSI1_GPIO0_00 69 /*!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */ +#define SC_P_MIPI_DSI1_GPIO0_01 70 /*!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /*!< */ +#define SC_P_MIPI_CSI0_MCLK_OUT 72 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 73 /*!< MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 74 /*!< MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_CSI0_GPIO0_00 75 /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_CSI0_GPIO0_01 76 /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_CSI1_MCLK_OUT 77 /*!< MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_CSI1_GPIO0_00 78 /*!< MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_CSI1_GPIO0_01 79 /*!< MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_CSI1_I2C0_SCL 80 /*!< MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */ +#define SC_P_MIPI_CSI1_I2C0_SDA 81 /*!< MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */ +#define SC_P_HDMI_TX0_TS_SCL 82 /*!< HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */ +#define SC_P_HDMI_TX0_TS_SDA 83 /*!< HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */ +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /*!< */ +#define SC_P_ESAI1_FSR 85 /*!< AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */ +#define SC_P_ESAI1_FST 86 /*!< AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */ +#define SC_P_ESAI1_SCKR 87 /*!< AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */ +#define SC_P_ESAI1_SCKT 88 /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */ +#define SC_P_ESAI1_TX0 89 /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */ +#define SC_P_ESAI1_TX1 90 /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */ +#define SC_P_ESAI1_TX2_RX3 91 /*!< AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */ +#define SC_P_ESAI1_TX3_RX2 92 /*!< AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */ +#define SC_P_ESAI1_TX4_RX1 93 /*!< AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */ +#define SC_P_ESAI1_TX5_RX0 94 /*!< AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */ +#define SC_P_SPDIF0_RX 95 /*!< AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */ +#define SC_P_SPDIF0_TX 96 /*!< AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */ +#define SC_P_SPDIF0_EXT_CLK 97 /*!< AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */ +#define SC_P_SPI3_SCK 98 /*!< DMA.SPI3.SCK, LSIO.GPIO2.IO17 */ +#define SC_P_SPI3_SDO 99 /*!< DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */ +#define SC_P_SPI3_SDI 100 /*!< DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */ +#define SC_P_SPI3_CS0 101 /*!< DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */ +#define SC_P_SPI3_CS1 102 /*!< DMA.SPI3.CS1, LSIO.GPIO2.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /*!< */ +#define SC_P_ESAI0_FSR 104 /*!< AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */ +#define SC_P_ESAI0_FST 105 /*!< AUD.ESAI0.FST, LSIO.GPIO2.IO23 */ +#define SC_P_ESAI0_SCKR 106 /*!< AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */ +#define SC_P_ESAI0_SCKT 107 /*!< AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */ +#define SC_P_ESAI0_TX0 108 /*!< AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */ +#define SC_P_ESAI0_TX1 109 /*!< AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */ +#define SC_P_ESAI0_TX2_RX3 110 /*!< AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */ +#define SC_P_ESAI0_TX3_RX2 111 /*!< AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */ +#define SC_P_ESAI0_TX4_RX1 112 /*!< AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */ +#define SC_P_ESAI0_TX5_RX0 113 /*!< AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */ +#define SC_P_MCLK_IN0 114 /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */ +#define SC_P_MCLK_OUT0 115 /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /*!< */ +#define SC_P_SPI0_SCK 117 /*!< DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */ +#define SC_P_SPI0_SDO 118 /*!< DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */ +#define SC_P_SPI0_SDI 119 /*!< DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */ +#define SC_P_SPI0_CS0 120 /*!< DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */ +#define SC_P_SPI0_CS1 121 /*!< DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */ +#define SC_P_SPI2_SCK 122 /*!< DMA.SPI2.SCK, LSIO.GPIO3.IO07 */ +#define SC_P_SPI2_SDO 123 /*!< DMA.SPI2.SDO, LSIO.GPIO3.IO08 */ +#define SC_P_SPI2_SDI 124 /*!< DMA.SPI2.SDI, LSIO.GPIO3.IO09 */ +#define SC_P_SPI2_CS0 125 /*!< DMA.SPI2.CS0, LSIO.GPIO3.IO10 */ +#define SC_P_SPI2_CS1 126 /*!< DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */ +#define SC_P_SAI1_RXC 127 /*!< AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */ +#define SC_P_SAI1_RXD 128 /*!< AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */ +#define SC_P_SAI1_RXFS 129 /*!< AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */ +#define SC_P_SAI1_TXC 130 /*!< AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */ +#define SC_P_SAI1_TXD 131 /*!< AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */ +#define SC_P_SAI1_TXFS 132 /*!< AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /*!< */ +#define SC_P_ADC_IN7 134 /*!< DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */ +#define SC_P_ADC_IN6 135 /*!< DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */ +#define SC_P_ADC_IN5 136 /*!< DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */ +#define SC_P_ADC_IN4 137 /*!< DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */ +#define SC_P_ADC_IN3 138 /*!< DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */ +#define SC_P_ADC_IN2 139 /*!< DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */ +#define SC_P_ADC_IN1 140 /*!< DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */ +#define SC_P_ADC_IN0 141 /*!< DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */ +#define SC_P_MLB_SIG 142 /*!< CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */ +#define SC_P_MLB_CLK 143 /*!< CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */ +#define SC_P_MLB_DATA 144 /*!< CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /*!< */ +#define SC_P_FLEXCAN0_RX 146 /*!< DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */ +#define SC_P_FLEXCAN0_TX 147 /*!< DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */ +#define SC_P_FLEXCAN1_RX 148 /*!< DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */ +#define SC_P_FLEXCAN1_TX 149 /*!< DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */ +#define SC_P_FLEXCAN2_RX 150 /*!< DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */ +#define SC_P_FLEXCAN2_TX 151 /*!< DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /*!< */ +#define SC_P_USB_SS3_TC0 153 /*!< DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 154 /*!< DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 155 /*!< DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 156 /*!< DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /*!< */ +#define SC_P_USDHC1_RESET_B 158 /*!< CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */ +#define SC_P_USDHC1_VSELECT 159 /*!< CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */ +#define SC_P_USDHC2_RESET_B 160 /*!< CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */ +#define SC_P_USDHC2_VSELECT 161 /*!< CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */ +#define SC_P_USDHC2_WP 162 /*!< CONN.USDHC2.WP, LSIO.GPIO4.IO11 */ +#define SC_P_USDHC2_CD_B 163 /*!< CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /*!< */ +#define SC_P_ENET0_MDIO 165 /*!< CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */ +#define SC_P_ENET0_MDC 166 /*!< CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */ +#define SC_P_ENET0_REFCLK_125M_25M 167 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */ +#define SC_P_ENET1_REFCLK_125M_25M 168 /*!< CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */ +#define SC_P_ENET1_MDIO 169 /*!< CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */ +#define SC_P_ENET1_MDC 170 /*!< CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /*!< */ +#define SC_P_QSPI1A_SS0_B 172 /*!< LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */ +#define SC_P_QSPI1A_SS1_B 173 /*!< LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */ +#define SC_P_QSPI1A_SCLK 174 /*!< LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */ +#define SC_P_QSPI1A_DQS 175 /*!< LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_QSPI1A_DATA3 176 /*!< LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */ +#define SC_P_QSPI1A_DATA2 177 /*!< LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */ +#define SC_P_QSPI1A_DATA1 178 /*!< LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */ +#define SC_P_QSPI1A_DATA0 179 /*!< LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /*!< */ +#define SC_P_QSPI0A_DATA0 181 /*!< LSIO.QSPI0A.DATA0 */ +#define SC_P_QSPI0A_DATA1 182 /*!< LSIO.QSPI0A.DATA1 */ +#define SC_P_QSPI0A_DATA2 183 /*!< LSIO.QSPI0A.DATA2 */ +#define SC_P_QSPI0A_DATA3 184 /*!< LSIO.QSPI0A.DATA3 */ +#define SC_P_QSPI0A_DQS 185 /*!< LSIO.QSPI0A.DQS */ +#define SC_P_QSPI0A_SS0_B 186 /*!< LSIO.QSPI0A.SS0_B */ +#define SC_P_QSPI0A_SS1_B 187 /*!< LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */ +#define SC_P_QSPI0A_SCLK 188 /*!< LSIO.QSPI0A.SCLK */ +#define SC_P_QSPI0B_SCLK 189 /*!< LSIO.QSPI0B.SCLK */ +#define SC_P_QSPI0B_DATA0 190 /*!< LSIO.QSPI0B.DATA0 */ +#define SC_P_QSPI0B_DATA1 191 /*!< LSIO.QSPI0B.DATA1 */ +#define SC_P_QSPI0B_DATA2 192 /*!< LSIO.QSPI0B.DATA2 */ +#define SC_P_QSPI0B_DATA3 193 /*!< LSIO.QSPI0B.DATA3 */ +#define SC_P_QSPI0B_DQS 194 /*!< LSIO.QSPI0B.DQS */ +#define SC_P_QSPI0B_SS0_B 195 /*!< LSIO.QSPI0B.SS0_B */ +#define SC_P_QSPI0B_SS1_B 196 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /*!< */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */ +#define SC_P_PCIE_CTRL0_WAKE_B 199 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */ +#define SC_P_PCIE_CTRL0_PERST_B 200 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */ +#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /*!< HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */ +#define SC_P_PCIE_CTRL1_WAKE_B 202 /*!< HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */ +#define SC_P_PCIE_CTRL1_PERST_B 203 /*!< HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /*!< */ +#define SC_P_USB_HSIC0_DATA 205 /*!< CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */ +#define SC_P_USB_HSIC0_STROBE 206 /*!< CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */ +#define SC_P_CALIBRATION_0_HSIC 207 /*!< */ +#define SC_P_CALIBRATION_1_HSIC 208 /*!< */ +#define SC_P_EMMC0_CLK 209 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B */ +#define SC_P_EMMC0_CMD 210 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */ +#define SC_P_EMMC0_DATA0 211 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */ +#define SC_P_EMMC0_DATA1 212 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */ +#define SC_P_EMMC0_DATA2 213 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */ +#define SC_P_EMMC0_DATA3 214 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */ +#define SC_P_EMMC0_DATA4 215 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */ +#define SC_P_EMMC0_DATA5 216 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */ +#define SC_P_EMMC0_DATA6 217 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */ +#define SC_P_EMMC0_DATA7 218 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */ +#define SC_P_EMMC0_STROBE 219 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */ +#define SC_P_EMMC0_RESET_B 220 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /*!< */ +#define SC_P_USDHC1_CLK 222 /*!< CONN.USDHC1.CLK, AUD.MQS.R */ +#define SC_P_USDHC1_CMD 223 /*!< CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */ +#define SC_P_USDHC1_DATA0 224 /*!< CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */ +#define SC_P_USDHC1_DATA1 225 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */ +#define SC_P_CTL_NAND_RE_P_N 226 /*!< */ +#define SC_P_USDHC1_DATA2 227 /*!< CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */ +#define SC_P_USDHC1_DATA3 228 /*!< CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */ +#define SC_P_CTL_NAND_DQS_P_N 229 /*!< */ +#define SC_P_USDHC1_DATA4 230 /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */ +#define SC_P_USDHC1_DATA5 231 /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */ +#define SC_P_USDHC1_DATA6 232 /*!< CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */ +#define SC_P_USDHC1_DATA7 233 /*!< CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */ +#define SC_P_USDHC1_STROBE 234 /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /*!< */ +#define SC_P_USDHC2_CLK 236 /*!< CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */ +#define SC_P_USDHC2_CMD 237 /*!< CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */ +#define SC_P_USDHC2_DATA0 238 /*!< CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */ +#define SC_P_USDHC2_DATA1 239 /*!< CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */ +#define SC_P_USDHC2_DATA2 240 /*!< CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */ +#define SC_P_USDHC2_DATA3 241 /*!< CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /*!< */ +#define SC_P_ENET0_RGMII_TXC 243 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */ +#define SC_P_ENET0_RGMII_TX_CTL 244 /*!< CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */ +#define SC_P_ENET0_RGMII_TXD0 245 /*!< CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */ +#define SC_P_ENET0_RGMII_TXD1 246 /*!< CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */ +#define SC_P_ENET0_RGMII_TXD2 247 /*!< CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */ +#define SC_P_ENET0_RGMII_TXD3 248 /*!< CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */ +#define SC_P_ENET0_RGMII_RXC 249 /*!< CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */ +#define SC_P_ENET0_RGMII_RX_CTL 250 /*!< CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */ +#define SC_P_ENET0_RGMII_RXD0 251 /*!< CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */ +#define SC_P_ENET0_RGMII_RXD1 252 /*!< CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */ +#define SC_P_ENET0_RGMII_RXD2 253 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */ +#define SC_P_ENET0_RGMII_RXD3 254 /*!< CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /*!< */ +#define SC_P_ENET1_RGMII_TXC 256 /*!< CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */ +#define SC_P_ENET1_RGMII_TX_CTL 257 /*!< CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */ +#define SC_P_ENET1_RGMII_TXD0 258 /*!< CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */ +#define SC_P_ENET1_RGMII_TXD1 259 /*!< CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */ +#define SC_P_ENET1_RGMII_TXD2 260 /*!< CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */ +#define SC_P_ENET1_RGMII_TXD3 261 /*!< CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */ +#define SC_P_ENET1_RGMII_RXC 262 /*!< CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */ +#define SC_P_ENET1_RGMII_RX_CTL 263 /*!< CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */ +#define SC_P_ENET1_RGMII_RXD0 264 /*!< CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */ +#define SC_P_ENET1_RGMII_RXD1 265 /*!< CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */ +#define SC_P_ENET1_RGMII_RXD2 266 /*!< CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */ +#define SC_P_ENET1_RGMII_RXD3 267 /*!< CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /*!< */ +/*@}*/ + +#endif /* SC_PADS_H */ + diff --git a/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h new file mode 100644 index 00000000000..5fed5140c1a --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h @@ -0,0 +1,195 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define ROMCP_LPCG 0x5D500000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define PWM_LPCG 0x5A590000 +#define LCD_LPCG 0x5A580000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* PARALLEL CSI SS */ +#define PARALLEL_CSI_LPCG 0x58263000 + +/* Display MIPI SS */ +#define DI_MIPI0_LPCG 0x56223000 +#define DI_MIPI1_LPCG 0x56243000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_SAI_4_LPCG 0x59c20000 +#define AUD_SAI_5_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + + +#endif diff --git a/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h b/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h new file mode 100644 index 00000000000..8db40c549a7 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file used to configure SoC pad list. + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B 0 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */ +#define SC_P_PCIE_CTRL0_WAKE_B 2 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /*!< */ +#define SC_P_USB_SS3_TC0 4 /*!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 5 /*!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 6 /*!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 7 /*!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /*!< */ +#define SC_P_EMMC0_CLK 9 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ +#define SC_P_EMMC0_CMD 10 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ +#define SC_P_EMMC0_DATA0 11 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ +#define SC_P_EMMC0_DATA1 12 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ +#define SC_P_EMMC0_DATA2 13 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ +#define SC_P_EMMC0_DATA3 14 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /*!< */ +#define SC_P_EMMC0_DATA4 16 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */ +#define SC_P_EMMC0_DATA5 17 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */ +#define SC_P_EMMC0_DATA6 18 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */ +#define SC_P_EMMC0_DATA7 19 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */ +#define SC_P_EMMC0_STROBE 20 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */ +#define SC_P_EMMC0_RESET_B 21 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /*!< */ +#define SC_P_USDHC1_RESET_B 23 /*!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */ +#define SC_P_USDHC1_VSELECT 24 /*!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */ +#define SC_P_CTL_NAND_RE_P_N 25 /*!< */ +#define SC_P_USDHC1_WP 26 /*!< CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */ +#define SC_P_USDHC1_CD_B 27 /*!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_CTL_NAND_DQS_P_N 28 /*!< */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /*!< */ +#define SC_P_USDHC1_CLK 30 /*!< CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ +#define SC_P_USDHC1_CMD 31 /*!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ +#define SC_P_USDHC1_DATA0 32 /*!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */ +#define SC_P_USDHC1_DATA1 33 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */ +#define SC_P_USDHC1_DATA2 34 /*!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */ +#define SC_P_USDHC1_DATA3 35 /*!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /*!< */ +#define SC_P_ENET0_RGMII_TXC 37 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */ +#define SC_P_ENET0_RGMII_TX_CTL 38 /*!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ +#define SC_P_ENET0_RGMII_TXD0 39 /*!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */ +#define SC_P_ENET0_RGMII_TXD1 40 /*!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */ +#define SC_P_ENET0_RGMII_TXD2 41 /*!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */ +#define SC_P_ENET0_RGMII_TXD3 42 /*!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /*!< */ +#define SC_P_ENET0_RGMII_RXC 44 /*!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */ +#define SC_P_ENET0_RGMII_RX_CTL 45 /*!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */ +#define SC_P_ENET0_RGMII_RXD0 46 /*!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ +#define SC_P_ENET0_RGMII_RXD1 47 /*!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ +#define SC_P_ENET0_RGMII_RXD2 48 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */ +#define SC_P_ENET0_RGMII_RXD3 49 /*!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /*!< */ +#define SC_P_ENET0_REFCLK_125M_25M 51 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */ +#define SC_P_ENET0_MDIO 52 /*!< CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */ +#define SC_P_ENET0_MDC 53 /*!< CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /*!< */ +#define SC_P_ESAI0_FSR 55 /*!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */ +#define SC_P_ESAI0_FST 56 /*!< ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */ +#define SC_P_ESAI0_SCKR 57 /*!< ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */ +#define SC_P_ESAI0_SCKT 58 /*!< ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */ +#define SC_P_ESAI0_TX0 59 /*!< ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */ +#define SC_P_ESAI0_TX1 60 /*!< ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */ +#define SC_P_ESAI0_TX2_RX3 61 /*!< ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */ +#define SC_P_ESAI0_TX3_RX2 62 /*!< ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */ +#define SC_P_ESAI0_TX4_RX1 63 /*!< ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */ +#define SC_P_ESAI0_TX5_RX0 64 /*!< ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */ +#define SC_P_SPDIF0_RX 65 /*!< ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */ +#define SC_P_SPDIF0_TX 66 /*!< ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */ +#define SC_P_SPDIF0_EXT_CLK 67 /*!< ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /*!< */ +#define SC_P_SPI3_SCK 69 /*!< ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */ +#define SC_P_SPI3_SDO 70 /*!< ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */ +#define SC_P_SPI3_SDI 71 /*!< ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */ +#define SC_P_SPI3_CS0 72 /*!< ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */ +#define SC_P_SPI3_CS1 73 /*!< ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */ +#define SC_P_MCLK_IN1 74 /*!< ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */ +#define SC_P_MCLK_IN0 75 /*!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */ +#define SC_P_MCLK_OUT0 76 /*!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */ +#define SC_P_UART1_TX 77 /*!< ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */ +#define SC_P_UART1_RX 78 /*!< ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */ +#define SC_P_UART1_RTS_B 79 /*!< ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */ +#define SC_P_UART1_CTS_B 80 /*!< ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /*!< */ +#define SC_P_SAI0_TXD 82 /*!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */ +#define SC_P_SAI0_TXC 83 /*!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */ +#define SC_P_SAI0_RXD 84 /*!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */ +#define SC_P_SAI0_TXFS 85 /*!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */ +#define SC_P_SAI1_RXD 86 /*!< ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */ +#define SC_P_SAI1_RXC 87 /*!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */ +#define SC_P_SAI1_RXFS 88 /*!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */ +#define SC_P_SPI2_CS0 89 /*!< ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */ +#define SC_P_SPI2_SDO 90 /*!< ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */ +#define SC_P_SPI2_SDI 91 /*!< ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */ +#define SC_P_SPI2_SCK 92 /*!< ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */ +#define SC_P_SPI0_SCK 93 /*!< ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */ +#define SC_P_SPI0_SDI 94 /*!< ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */ +#define SC_P_SPI0_SDO 95 /*!< ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */ +#define SC_P_SPI0_CS1 96 /*!< ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */ +#define SC_P_SPI0_CS0 97 /*!< ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /*!< */ +#define SC_P_ADC_IN1 99 /*!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */ +#define SC_P_ADC_IN0 100 /*!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */ +#define SC_P_ADC_IN3 101 /*!< ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */ +#define SC_P_ADC_IN2 102 /*!< ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */ +#define SC_P_ADC_IN5 103 /*!< ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */ +#define SC_P_ADC_IN4 104 /*!< ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */ +#define SC_P_FLEXCAN0_RX 105 /*!< ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */ +#define SC_P_FLEXCAN0_TX 106 /*!< ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */ +#define SC_P_FLEXCAN1_RX 107 /*!< ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */ +#define SC_P_FLEXCAN1_TX 108 /*!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */ +#define SC_P_FLEXCAN2_RX 109 /*!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */ +#define SC_P_FLEXCAN2_TX 110 /*!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */ +#define SC_P_UART0_RX 111 /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */ +#define SC_P_UART0_TX 112 /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */ +#define SC_P_UART2_TX 113 /*!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */ +#define SC_P_UART2_RX 114 /*!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /*!< */ +#define SC_P_MIPI_DSI0_I2C0_SCL 116 /*!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 117 /*!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_DSI0_GPIO0_00 118 /*!< MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_DSI0_GPIO0_01 119 /*!< MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 120 /*!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 121 /*!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_DSI1_GPIO0_00 122 /*!< MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_DSI1_GPIO0_01 123 /*!< MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /*!< */ +#define SC_P_JTAG_TRST_B 125 /*!< SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SCL 126 /*!< SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */ +#define SC_P_PMIC_I2C_SDA 127 /*!< SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */ +#define SC_P_PMIC_INT_B 128 /*!< SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 129 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */ +#define SC_P_SCU_GPIO0_01 130 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */ +#define SC_P_SCU_PMIC_STANDBY 131 /*!< SCU.DSC.PMIC_STANDBY */ +#define SC_P_SCU_BOOT_MODE0 132 /*!< SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 133 /*!< SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 134 /*!< SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */ +#define SC_P_SCU_BOOT_MODE3 135 /*!< SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */ +#define SC_P_CSI_D00 136 /*!< CI_PI.D02, ADMA.SAI0.RXC */ +#define SC_P_CSI_D01 137 /*!< CI_PI.D03, ADMA.SAI0.RXD */ +#define SC_P_CSI_D02 138 /*!< CI_PI.D04, ADMA.SAI0.RXFS */ +#define SC_P_CSI_D03 139 /*!< CI_PI.D05, ADMA.SAI2.RXC */ +#define SC_P_CSI_D04 140 /*!< CI_PI.D06, ADMA.SAI2.RXD */ +#define SC_P_CSI_D05 141 /*!< CI_PI.D07, ADMA.SAI2.RXFS */ +#define SC_P_CSI_D06 142 /*!< CI_PI.D08, ADMA.SAI3.RXC */ +#define SC_P_CSI_D07 143 /*!< CI_PI.D09, ADMA.SAI3.RXD */ +#define SC_P_CSI_HSYNC 144 /*!< CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */ +#define SC_P_CSI_VSYNC 145 /*!< CI_PI.VSYNC, CI_PI.D01 */ +#define SC_P_CSI_PCLK 146 /*!< CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */ +#define SC_P_CSI_MCLK 147 /*!< CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */ +#define SC_P_CSI_EN 148 /*!< CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */ +#define SC_P_CSI_RESET 149 /*!< CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /*!< */ +#define SC_P_MIPI_CSI0_MCLK_OUT 151 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 152 /*!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 153 /*!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */ +#define SC_P_MIPI_CSI0_GPIO0_01 154 /*!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */ +#define SC_P_MIPI_CSI0_GPIO0_00 155 /*!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */ +#define SC_P_QSPI0A_DATA0 156 /*!< LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ +#define SC_P_QSPI0A_DATA1 157 /*!< LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ +#define SC_P_QSPI0A_DATA2 158 /*!< LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ +#define SC_P_QSPI0A_DATA3 159 /*!< LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ +#define SC_P_QSPI0A_DQS 160 /*!< LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ +#define SC_P_QSPI0A_SS0_B 161 /*!< LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ +#define SC_P_QSPI0A_SS1_B 162 /*!< LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */ +#define SC_P_QSPI0A_SCLK 163 /*!< LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /*!< */ +#define SC_P_QSPI0B_SCLK 165 /*!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */ +#define SC_P_QSPI0B_DATA0 166 /*!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */ +#define SC_P_QSPI0B_DATA1 167 /*!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */ +#define SC_P_QSPI0B_DATA2 168 /*!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */ +#define SC_P_QSPI0B_DATA3 169 /*!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */ +#define SC_P_QSPI0B_DQS 170 /*!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */ +#define SC_P_QSPI0B_SS0_B 171 /*!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */ +#define SC_P_QSPI0B_SS1_B 172 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /*!< */ +/*@}*/ + +#endif /* SC_PADS_H */ + diff --git a/arch/arm/include/asm/arch-imx8/iomux.h b/arch/arm/include/asm/arch-imx8/iomux.h new file mode 100644 index 00000000000..b4e68af54b3 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/iomux.h @@ -0,0 +1,42 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX8_IOMUX_H__ +#define __ASM_ARCH_IMX8_IOMUX_H__ + +/* We use 64bits value for iomux settings. + * High 32bits are used for padring register value, + * low 16bits are used for pin index. + */ +typedef u64 iomux_cfg_t; + +#define PADRING_IFMUX_EN_SHIFT 31 +#define PADRING_IFMUX_EN_MASK (1 << 31) +#define PADRING_GP_EN_SHIFT 30 +#define PADRING_GP_EN_MASK (1 << 30) +#define PADRING_IFMUX_SHIFT 27 +#define PADRING_IFMUX_MASK (0x7 << 27) +#define PADRING_CONFIG_SHIFT 25 +#define PADRING_LPCONFIG_SHIFT 23 +#define PADRING_PULL_SHIFT 5 +#define PADRING_DSE_SHIFT 0 + + +#define MUX_PAD_CTRL_SHIFT 32 +#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0xFFFFFFFF << MUX_PAD_CTRL_SHIFT) +#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_SHIFT (PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_MASK ((iomux_cfg_t)0x7 << MUX_MODE_SHIFT) +#define PIN_ID_MASK ((iomux_cfg_t)0xFFFF) + +/* Valid mux alt0 to alt7 */ +#define MUX_MODE_ALT(x) (((iomux_cfg_t)x << MUX_MODE_SHIFT) & MUX_MODE_MASK) + + +void imx8_iomux_setup_pad(iomux_cfg_t pad); +void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, + unsigned count); +#endif /* __ASM_ARCH_IMX8_IOMUX_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/lpcg.h b/arch/arm/include/asm/arch-imx8/lpcg.h new file mode 100644 index 00000000000..7e551f0ec14 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/lpcg.h @@ -0,0 +1,25 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX8_LPCG_H__ +#define __ASM_ARCH_IMX8_LPCG_H__ + +#if defined(CONFIG_IMX8QM) +#include "imx8qm_lpcg.h" +#elif defined(CONFIG_IMX8QXP) +#include "imx8qxp_lpcg.h" +#else +#error "No lpcg header" +#endif + +void LPCG_ClockOff(u32 lpcg_addr, u8 clk); +void LPCG_ClockOn(u32 lpcg_addr, u8 clk); +void LPCG_ClockAutoGate(u32 lpcg_addr, u8 clk); +void LPCG_AllClockOff(u32 lpcg_addr); +void LPCG_AllClockOn(u32 lpcg_addr); +void LPCG_AllClockAutoGate(u32 lpcg_addr); + +#endif /* __ASM_ARCH_IMX8_LPCG_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h b/arch/arm/include/asm/arch-imx8/power-domain.h new file mode 100644 index 00000000000..e7bbe3e36d1 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/power-domain.h @@ -0,0 +1,16 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_POWER_DOMAIN_H +#define _ASM_ARCH_POWER_DOMAIN_H + +#include + +struct imx8_power_domain_platdata{ + sc_rsrc_t resource_id; +}; + +#endif diff --git a/arch/arm/include/asm/arch-imx8/sid.h b/arch/arm/include/asm/arch-imx8/sid.h new file mode 100644 index 00000000000..c705fa36865 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sid.h @@ -0,0 +1,14 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include + +struct smmu_sid { + sc_rsrc_t rsrc; + sc_rm_sid_t sid; + char dev_name[32]; +}; + +sc_err_t imx8_config_smmu_sid(struct smmu_sid *dev_sids, int size); diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h new file mode 100644 index 00000000000..24788e55e28 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct pass_over_info_t { + uint16_t barker; + uint16_t len; + uint32_t g_bt_cfg_shadow; + uint32_t card_address_mode; + uint32_t bad_block_count_met; + uint32_t g_ap_mu; +}; + +int print_bootinfo(void); +int init_otg_power(void); +void power_off_pd_devices(const char* permanent_on_devices[], int size); +extern unsigned long rom_pointer[]; +enum boot_device get_boot_device(void); +bool check_m4_parts_boot(void); diff --git a/arch/arm/include/asm/arch-imx8/video_common.h b/arch/arm/include/asm/arch-imx8/video_common.h new file mode 100644 index 00000000000..e6ac01ca0f5 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/video_common.h @@ -0,0 +1,23 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_VIDEO_COMMON_H__ +#define __ASM_ARCH_VIDEO_COMMON_H__ + +#include +#include + +#define PS2KHZ(ps) (1000000000UL / (ps)) + +int lvds2hdmi_setup(int i2c_bus); +int lvds_soc_setup(int lvds_id, sc_pm_clock_rate_t pixel_clock); +void lvds_configure(int lvds_id); +int display_controller_setup(sc_pm_clock_rate_t pixel_clock); +int imxdpuv1_fb_init(struct fb_videomode const *mode, uint8_t disp, uint32_t pixfmt); +void imxdpuv1_fb_disable(void); + +#endif /* __ASM_ARCH_VIDEO_COMMON_H__ */ diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h new file mode 100644 index 00000000000..8f540571f47 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -0,0 +1,13 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef CONFIG_IMX8MQ +#include +#elif defined(CONFIG_IMX8MM) +#include +#else +#error "Error no clock.h" +#endif diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h new file mode 100644 index 00000000000..d8b59d31b5e --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h @@ -0,0 +1,896 @@ +/* + * Copyright 2018 NXP + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_IMX8MM_CLOCK_H +#define _ASM_ARCH_IMX8MM_CLOCK_H + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_IPG_CLK, + MXC_CSPI_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_I2C_CLK, + MXC_UART_CLK, + MXC_QSPI_CLK, +}; + +enum pll_clocks { + ANATOP_ARM_PLL, + ANATOP_VPU_PLL, + ANATOP_GPU_PLL, + ANATOP_SYSTEM_PLL1, + ANATOP_SYSTEM_PLL2, + ANATOP_SYSTEM_PLL3, + ANATOP_AUDIO_PLL1, + ANATOP_AUDIO_PLL2, + ANATOP_VIDEO_PLL, + ANATOP_DRAM_PLL, +}; + +enum clk_slice_type { + CORE_CLOCK_SLICE, + BUS_CLOCK_SLICE, + IP_CLOCK_SLICE, + AHB_CLOCK_SLICE, + IPG_CLOCK_SLICE, + CORE_SEL_CLOCK_SLICE, + DRAM_SEL_CLOCK_SLICE, +}; + +enum clk_root_index { + ARM_A53_CLK_ROOT = 0, + ARM_M4_CLK_ROOT = 1, + VPU_A53_CLK_ROOT = 2, + GPU3D_CLK_ROOT = 3, + GPU2D_CLK_ROOT = 4, + MAIN_AXI_CLK_ROOT = 16, + ENET_AXI_CLK_ROOT = 17, + NAND_USDHC_BUS_CLK_ROOT = 18, + VPU_BUS_CLK_ROOT = 19, + DISPLAY_AXI_CLK_ROOT = 20, + DISPLAY_APB_CLK_ROOT = 21, + DISPLAY_RTRM_CLK_ROOT = 22, + USB_BUS_CLK_ROOT = 23, + GPU_AXI_CLK_ROOT = 24, + GPU_AHB_CLK_ROOT = 25, + NOC_CLK_ROOT = 26, + NOC_APB_CLK_ROOT = 27, + AHB_CLK_ROOT = 32, + /* TODO: IPG Not sure */ + IPG_CLK_ROOT = 33, + AUDIO_AHB_CLK_ROOT = 34, + MIPI_DSI_ESC_RX_CLK_ROOT = 36, + DRAM_SEL_CFG = 48, + CORE_SEL_CFG = 49, + DRAM_ALT_CLK_ROOT = 64, + DRAM_APB_CLK_ROOT = 65, + VPU_G1_CLK_ROOT = 66, + VPU_G2_CLK_ROOT = 67, + DISPLAY_DTRC_CLK_ROOT = 68, + DISPLAY_DC8000_CLK_ROOT = 69, + PCIE_CTRL_CLK_ROOT = 70, + PCIE_PHY_CLK_ROOT = 71, + PCIE_AUX_CLK_ROOT = 72, + DC_PIXEL_CLK_ROOT = 73, + LCDIF_PIXEL_CLK_ROOT = 74, + SAI1_CLK_ROOT = 75, + SAI2_CLK_ROOT = 76, + SAI3_CLK_ROOT = 77, + SAI4_CLK_ROOT = 78, + SAI5_CLK_ROOT = 79, + SAI6_CLK_ROOT = 80, + SPDIF1_CLK_ROOT = 81, + SPDIF2_CLK_ROOT = 82, + ENET_REF_CLK_ROOT = 83, + ENET_TIMER_CLK_ROOT = 84, + ENET_PHY_REF_CLK_ROOT = 85, + NAND_CLK_ROOT = 86, + QSPI_CLK_ROOT = 87, + USDHC1_CLK_ROOT = 88, + USDHC2_CLK_ROOT = 89, + I2C1_CLK_ROOT = 90, + I2C2_CLK_ROOT = 91, + I2C3_CLK_ROOT = 92, + I2C4_CLK_ROOT = 93, + UART1_CLK_ROOT = 94, + UART2_CLK_ROOT = 95, + UART3_CLK_ROOT = 96, + UART4_CLK_ROOT = 97, + USB_CORE_REF_CLK_ROOT = 98, + USB_PHY_REF_CLK_ROOT = 99, + GIC_CLK_ROOT = 100, + ECSPI1_CLK_ROOT = 101, + ECSPI2_CLK_ROOT = 102, + PWM1_CLK_ROOT = 103, + PWM2_CLK_ROOT = 104, + PWM3_CLK_ROOT = 105, + PWM4_CLK_ROOT = 106, + GPT1_CLK_ROOT = 107, + GPT2_CLK_ROOT = 108, + GPT3_CLK_ROOT = 109, + GPT4_CLK_ROOT = 110, + GPT5_CLK_ROOT = 111, + GPT6_CLK_ROOT = 112, + TRACE_CLK_ROOT = 113, + WDOG_CLK_ROOT = 114, + WRCLK_CLK_ROOT = 115, + IPP_DO_CLKO1 = 116, + IPP_DO_CLKO2 = 117, + MIPI_DSI_CORE_CLK_ROOT = 118, + MIPI_DSI_PHY_REF_CLK_ROOT = 119, + MIPI_DSI_DBI_CLK_ROOT = 120, + USDHC3_CLK_ROOT = 121, + MIPI_CSI1_CORE_CLK_ROOT = 122, + MIPI_CSI1_PHY_REF_CLK_ROOT = 123, + MIPI_CSI1_ESC_CLK_ROOT = 124, + MIPI_CSI2_CORE_CLK_ROOT = 125, + MIPI_CSI2_PHY_REF_CLK_ROOT = 126, + MIPI_CSI2_ESC_CLK_ROOT = 127, + PCIE2_CTRL_CLK_ROOT = 128, + PCIE2_PHY_CLK_ROOT = 129, + PCIE2_AUX_CLK_ROOT = 130, + ECSPI3_CLK_ROOT = 131, + PDM_CLK_ROOT = 132, + VPU_H1_CLK_ROOT = 133, + CLK_ROOT_MAX, +}; + +enum clk_root_src { + OSC_24M_CLK, + ARM_PLL_CLK, + DRAM_PLL1_CLK, + VIDEO_PLL2_CLK, + VPU_PLL_CLK, + GPU_PLL_CLK, + SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_266M_CLK, + SYSTEM_PLL1_200M_CLK, + SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_133M_CLK, + SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_333M_CLK, + SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_166M_CLK, + SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, + AUDIO_PLL1_CLK, + AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, + OSC_32K_CLK, + EXT_CLK_1, + EXT_CLK_2, + EXT_CLK_3, + EXT_CLK_4, + OSC_HDMI_CLK +}; + +enum clk_ccgr_index { + CCGR_DVFS = 0, + CCGR_ANAMIX = 1, + CCGR_CPU = 2, + CCGR_CSU = 3, + CCGR_DEBUG = 4, + CCGR_DDR1 = 5, + CCGR_ECSPI1 = 7, + CCGR_ECSPI2 = 8, + CCGR_ECSPI3 = 9, + CCGR_ENET1 = 10, + CCGR_GPIO1 = 11, + CCGR_GPIO2 = 12, + CCGR_GPIO3 = 13, + CCGR_GPIO4 = 14, + CCGR_GPIO5 = 15, + CCGR_GPT1 = 16, + CCGR_GPT2 = 17, + CCGR_GPT3 = 18, + CCGR_GPT4 = 19, + CCGR_GPT5 = 20, + CCGR_GPT6 = 21, + CCGR_HS = 22, + CCGR_I2C1 = 23, + CCGR_I2C2 = 24, + CCGR_I2C3 = 25, + CCGR_I2C4 = 26, + CCGR_IOMUX = 27, + CCGR_IOMUX1 = 28, + CCGR_IOMUX2 = 29, + CCGR_IOMUX3 = 30, + CCGR_IOMUX4 = 31, + CCGR_SNVSMIX_IPG_CLK = 32, + CCGR_MU = 33, + CCGR_OCOTP = 34, + CCGR_OCRAM = 35, + CCGR_OCRAM_S = 36, + CCGR_PCIE = 37, + CCGR_PERFMON1 = 38, + CCGR_PERFMON2 = 39, + CCGR_PWM1 = 40, + CCGR_PWM2 = 41, + CCGR_PWM3 = 42, + CCGR_PWM4 = 43, + CCGR_QOS = 44, + CCGR_QOS_DISPMIX = 45, + CCGR_QOS_ETHENET = 46, + CCGR_QSPI = 47, + CCGR_RAWNAND = 48, + CCGR_RDC = 49, + CCGR_ROM = 50, + CCGR_SAI1 = 51, + CCGR_SAI2 = 52, + CCGR_SAI3 = 53, + CCGR_SAI4 = 54, + CCGR_SAI5 = 55, + CCGR_SAI6 = 56, + CCGR_SCTR = 57, + CCGR_SDMA1 = 58, + CCGR_SDMA2 = 59, + CCGR_SEC_DEBUG = 60, + CCGR_SEMA1 = 61, + CCGR_SEMA2 = 62, + CCGR_SIM_DISPLAY = 63, + CCGR_SIM_ENET = 64, + CCGR_SIM_M = 65, + CCGR_SIM_MAIN = 66, + CCGR_SIM_S = 67, + CCGR_SIM_WAKEUP = 68, + CCGR_SIM_HSIO = 69, + CCGR_SIM_VPU = 70, + CCGR_SNVS = 71, + CCGR_TRACE = 72, + CCGR_UART1 = 73, + CCGR_UART2 = 74, + CCGR_UART3 = 75, + CCGR_UART4 = 76, + CCGR_USB_MSCALE_PL301 = 77, + CCGR_GPU3D = 79, + CCGR_USDHC1 = 81, + CCGR_USDHC2 = 82, + CCGR_WDOG1 = 83, + CCGR_WDOG2 = 84, + CCGR_WDOG3 = 85, + CCGR_VPUG1 = 86, + CCGR_GPU_BUS = 87, + CCGR_VPUH1 = 89, + CCGR_VPUG2 = 90, + CCGR_PDM = 91, + CCGR_GIC = 92, + CCGR_DISPMIX = 93, + CCGR_USDHC3 = 94, + CCGR_SDMA3 = 95, + CCGR_XTAL = 96, + CCGR_PLL = 97, + CCGR_TEMP_SENSOR = 98, + CCGR_VPUMIX_BUS = 99, + CCGR_GPU2D = 102, + CCGR_MAX +}; + +enum clk_src_index { + CLK_SRC_CKIL_SYNC_REQ = 0, + CLK_SRC_ARM_PLL_EN = 1, + CLK_SRC_GPU_PLL_EN = 2, + CLK_SRC_VPU_PLL_EN = 3, + CLK_SRC_DRAM_PLL_EN = 4, + CLK_SRC_SYSTEM_PLL1_EN = 5, + CLK_SRC_SYSTEM_PLL2_EN = 6, + CLK_SRC_SYSTEM_PLL3_EN = 7, + CLK_SRC_AUDIO_PLL1_EN = 8, + CLK_SRC_AUDIO_PLL2_EN = 9, + CLK_SRC_VIDEO_PLL1_EN = 10, + CLK_SRC_RESERVED = 11, + CLK_SRC_ARM_PLL = 12, + CLK_SRC_GPU_PLL = 13, + CLK_SRC_VPU_PLL = 14, + CLK_SRC_DRAM_PLL = 15, + CLK_SRC_SYSTEM_PLL1_800M = 16, + CLK_SRC_SYSTEM_PLL1_400M = 17, + CLK_SRC_SYSTEM_PLL1_266M = 18, + CLK_SRC_SYSTEM_PLL1_200M = 19, + CLK_SRC_SYSTEM_PLL1_160M = 20, + CLK_SRC_SYSTEM_PLL1_133M = 21, + CLK_SRC_SYSTEM_PLL1_100M = 22, + CLK_SRC_SYSTEM_PLL1_80M = 23, + CLK_SRC_SYSTEM_PLL1_40M = 24, + CLK_SRC_SYSTEM_PLL2_1000M = 25, + CLK_SRC_SYSTEM_PLL2_500M = 26, + CLK_SRC_SYSTEM_PLL2_333M = 27, + CLK_SRC_SYSTEM_PLL2_250M = 28, + CLK_SRC_SYSTEM_PLL2_200M = 29, + CLK_SRC_SYSTEM_PLL2_166M = 30, + CLK_SRC_SYSTEM_PLL2_125M = 31, + CLK_SRC_SYSTEM_PLL2_100M = 32, + CLK_SRC_SYSTEM_PLL2_50M = 33, + CLK_SRC_SYSTEM_PLL3 = 34, + CLK_SRC_AUDIO_PLL1 = 35, + CLK_SRC_AUDIO_PLL2 = 36, + CLK_SRC_VIDEO_PLL1 = 37, +}; + +enum root_pre_div { + CLK_ROOT_PRE_DIV1 = 0, + CLK_ROOT_PRE_DIV2, + CLK_ROOT_PRE_DIV3, + CLK_ROOT_PRE_DIV4, + CLK_ROOT_PRE_DIV5, + CLK_ROOT_PRE_DIV6, + CLK_ROOT_PRE_DIV7, + CLK_ROOT_PRE_DIV8, +}; + +enum root_post_div { + CLK_ROOT_POST_DIV1 = 0, + CLK_ROOT_POST_DIV2, + CLK_ROOT_POST_DIV3, + CLK_ROOT_POST_DIV4, + CLK_ROOT_POST_DIV5, + CLK_ROOT_POST_DIV6, + CLK_ROOT_POST_DIV7, + CLK_ROOT_POST_DIV8, + CLK_ROOT_POST_DIV9, + CLK_ROOT_POST_DIV10, + CLK_ROOT_POST_DIV11, + CLK_ROOT_POST_DIV12, + CLK_ROOT_POST_DIV13, + CLK_ROOT_POST_DIV14, + CLK_ROOT_POST_DIV15, + CLK_ROOT_POST_DIV16, + CLK_ROOT_POST_DIV17, + CLK_ROOT_POST_DIV18, + CLK_ROOT_POST_DIV19, + CLK_ROOT_POST_DIV20, + CLK_ROOT_POST_DIV21, + CLK_ROOT_POST_DIV22, + CLK_ROOT_POST_DIV23, + CLK_ROOT_POST_DIV24, + CLK_ROOT_POST_DIV25, + CLK_ROOT_POST_DIV26, + CLK_ROOT_POST_DIV27, + CLK_ROOT_POST_DIV28, + CLK_ROOT_POST_DIV29, + CLK_ROOT_POST_DIV30, + CLK_ROOT_POST_DIV31, + CLK_ROOT_POST_DIV32, + CLK_ROOT_POST_DIV33, + CLK_ROOT_POST_DIV34, + CLK_ROOT_POST_DIV35, + CLK_ROOT_POST_DIV36, + CLK_ROOT_POST_DIV37, + CLK_ROOT_POST_DIV38, + CLK_ROOT_POST_DIV39, + CLK_ROOT_POST_DIV40, + CLK_ROOT_POST_DIV41, + CLK_ROOT_POST_DIV42, + CLK_ROOT_POST_DIV43, + CLK_ROOT_POST_DIV44, + CLK_ROOT_POST_DIV45, + CLK_ROOT_POST_DIV46, + CLK_ROOT_POST_DIV47, + CLK_ROOT_POST_DIV48, + CLK_ROOT_POST_DIV49, + CLK_ROOT_POST_DIV50, + CLK_ROOT_POST_DIV51, + CLK_ROOT_POST_DIV52, + CLK_ROOT_POST_DIV53, + CLK_ROOT_POST_DIV54, + CLK_ROOT_POST_DIV55, + CLK_ROOT_POST_DIV56, + CLK_ROOT_POST_DIV57, + CLK_ROOT_POST_DIV58, + CLK_ROOT_POST_DIV59, + CLK_ROOT_POST_DIV60, + CLK_ROOT_POST_DIV61, + CLK_ROOT_POST_DIV62, + CLK_ROOT_POST_DIV63, + CLK_ROOT_POST_DIV64, +}; + +struct clk_root_map { + enum clk_root_index entry; + enum clk_slice_type slice_type; + u32 slice_index; + u8 src_mux[8]; +}; + +struct ccm_ccgr { + u32 ccgr; + u32 ccgr_set; + u32 ccgr_clr; + u32 ccgr_tog; +}; + +struct ccm_root { + u32 target_root; + u32 target_root_set; + u32 target_root_clr; + u32 target_root_tog; + u32 misc; + u32 misc_set; + u32 misc_clr; + u32 misc_tog; + u32 nm_post; + u32 nm_post_root_set; + u32 nm_post_root_clr; + u32 nm_post_root_tog; + u32 nm_pre; + u32 nm_pre_root_set; + u32 nm_pre_root_clr; + u32 nm_pre_root_tog; + u32 db_post; + u32 db_post_root_set; + u32 db_post_root_clr; + u32 db_post_root_tog; + u32 db_pre; + u32 db_pre_root_set; + u32 db_pre_root_clr; + u32 db_pre_root_tog; + u32 reserved[4]; + u32 access_ctrl; + u32 access_ctrl_root_set; + u32 access_ctrl_root_clr; + u32 access_ctrl_root_tog; +}; + +struct ccm_reg { + u32 reserved_0[4096]; + struct ccm_ccgr ccgr_array[192]; + u32 reserved_1[3328]; + struct ccm_root core_root[5]; + u32 reserved_2[352]; + struct ccm_root bus_root[12]; + u32 reserved_3[128]; + struct ccm_root ahb_ipg_root[4]; + u32 reserved_4[384]; + struct ccm_root dram_sel; + struct ccm_root core_sel; + u32 reserved_5[448]; + struct ccm_root ip_root[78]; +}; + +enum dram_pll_out_val { + DRAM_PLL_OUT_100M, + DRAM_PLL_OUT_167M, + DRAM_PLL_OUT_266M, + DRAM_PLL_OUT_667M, + DRAM_PLL_OUT_400M, + DRAM_PLL_OUT_600M, + DRAM_PLL_OUT_750M, + DRAM_PLL_OUT_800M, +}; + +enum dram_bypassclk_val { + DRAM_BYPASSCLK_100M, + DRAM_BYPASSCLK_250M, + DRAM_BYPASSCLK_400M, +}; + +#define AUDIO_PLL1_GNRL_CTL (0x30360000) +#define AUDIO_PLL1_FDIV_CTL0 (0x30360004) +#define AUDIO_PLL1_FDIV_CTL1 (0x30360008) +#define AUDIO_PLL1_SSCG_CTL (0x3036000c) +#define AUDIO_PLL1_MNIT_CTL (0x30360010) +#define AUDIO_PLL2_GNRL_CTL (0x30360014) +#define AUDIO_PLL2_FDIV_CTL0 (0x30360018) +#define AUDIO_PLL2_FDIV_CTL1 (0x3036001c) +#define AUDIO_PLL2_SSCG_CTL (0x30360020) +#define AUDIO_PLL2_MNIT_CTL (0x30360024) +#define VIDEO_PLL1_GNRL_CTL (0x30360028) +#define VIDEO_PLL1_FDIV_CTL0 (0x3036002c) +#define VIDEO_PLL1_FDIV_CTL1 (0x30360030) +#define VIDEO_PLL1_SSCG_CTL (0x30360034) +#define VIDEO_PLL1_MNIT_CTL (0x30360038) +#define DRAM_PLL_GNRL_CTL (0x30360050) +#define DRAM_PLL_FDIV_CTL0 (0x30360054) +#define DRAM_PLL_FDIV_CTL1 (0x30360058) +#define DRAM_PLL_SSCG_CTL (0x3036005c) +#define DRAM_PLL_MNIT_CTL (0x30360060) +#define GPU_PLL_GNRL_CTL (0x30360064) +#define GPU_PLL_DIV_CTL (0x30360068) +#define GPU_PLL_LOCKED_CTL (0x3036006c) +#define GPU_PLL_MNIT_CTL (0x30360070) +#define VPU_PLL_GNRL_CTL (0x30360074) +#define VPU_PLL_DIV_CTL (0x30360078) +#define VPU_PLL_LOCKED_CTL (0x3036007c) +#define VPU_PLL_MNIT_CTL (0x30360080) +#define ARM_PLL_GNRL_CTL (0x30360084) +#define ARM_PLL_DIV_CTL (0x30360088) +#define ARM_PLL_LOCKED_CTL (0x3036008c) +#define ARM_PLL_MNIT_CTL (0x30360090) +#define SYS_PLL1_GNRL_CTL (0x30360094) +#define SYS_PLL1_DIV_CTL (0x30360098) +#define SYS_PLL1_LOCKED_CTL (0x3036009c) +#define SYS_PLL1_MNIT_CTL (0x30360100) +#define SYS_PLL2_GNRL_CTL (0x30360104) +#define SYS_PLL2_DIV_CTL (0x30360108) +#define SYS_PLL2_LOCKED_CTL (0x3036010c) +#define SYS_PLL2_MNIT_CTL (0x30360110) +#define SYS_PLL3_GNRL_CTL (0x30360114) +#define SYS_PLL3_DIV_CTL (0x30360118) +#define SYS_PLL3_LOCKED_CTL (0x3036011c) +#define SYS_PLL3_MNIT_CTL (0x30360120) +#define ANAMIX_MISC_CTL (0x30360124) +#define DIGPROG (0x30360800) + +#define INTPLL_LOCK_MASK BIT(31) +#define INTPLL_LOCK_SEL_MASK BIT(29) +#define INTPLL_EXT_BYPASS_MASK BIT(28) +#define INTPLL_DIV20_CLKE_MASK BIT(27) +#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26) +#define INTPLL_DIV10_CLKE_MASK BIT(25) +#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24) +#define INTPLL_DIV8_CLKE_MASK BIT(23) +#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22) +#define INTPLL_DIV6_CLKE_MASK BIT(21) +#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20) +#define INTPLL_DIV5_CLKE_MASK BIT(19) +#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18) +#define INTPLL_DIV4_CLKE_MASK BIT(17) +#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16) +#define INTPLL_DIV3_CLKE_MASK BIT(15) +#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14) +#define INTPLL_DIV2_CLKE_MASK BIT(13) +#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12) +#define INTPLL_CLKE_MASK BIT(11) +#define INTPLL_CLKE_OVERRIDE_MASK BIT(10) +#define INTPLL_RST_MASK BIT(9) +#define INTPLL_RST_OVERRIDE_MASK BIT(8) +#define INTPLL_BYPASS_MASK BIT(4) +#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2) +#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0) + +#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12) +#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12)) +#define INTPLL_MAIN_DIV_SHIFT 12 +#define INTPLL_PRE_DIV_MASK GENMASK(9, 4) +#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4)) +#define INTPLL_PRE_DIV_SHIFT 4 +#define INTPLL_POST_DIV_MASK GENMASK(2, 0) +#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0)) +#define INTPLL_POST_DIV_SHIFT 0 + +#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4) +#define INTPLL_LOCK_CON_DLY_SHIFT 4 +#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2) +#define INTPLL_LOCK_CON_OUT_SHIFT 2 +#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0) +#define INTPLL_LOCK_CON_IN_SHIFT 0 + +#define INTPLL_LRD_EN_MASK BIT(21) +#define INTPLL_FOUT_MASK BIT(20) +#define INTPLL_AFC_SEL_MASK BIT(19) +#define INTPLL_PBIAS_CTRL_MASK BIT(18) +#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17) +#define INTPLL_AFCINIT_SEL_MASK BIT(16) +#define INTPLL_FSEL_MASK BIT(14) +#define INTPLL_FEED_EN_MASK BIT(13) +#define INTPLL_EXTAFC_MASK GENMASK(7, 3) +#define INTPLL_AFC_EN_MASK BIT(2) +#define INTPLL_ICP_MASK GENMASK(1, 0) + +/* CORE clock generation: i ranges from 0 to 4 */ +#define CCM_CORE_CLK_ROOT_GEN_TAGET(i) (0x30388000UL + 0x80 * (i) + 0x00) +#define CCM_CORE_CLK_ROOT_GEN_TAGET_SET(i) (0x30388000UL + 0x80 * (i) + 0x04) +#define CCM_CORE_CLK_ROOT_GEN_TAGET_CLR(i) (0x30388000UL + 0x80 * (i) + 0x08) +#define CCM_CORE_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x0c) +#define CCM_CORE_CLK_ROOT_GEN_MISC(i) (0x30388000UL + 0x80 * (i) + 0x10) +#define CCM_CORE_CLK_ROOT_GEN_MISC_SET(i) (0x30388000UL + 0x80 * (i) + 0x14) +#define CCM_CORE_CLK_ROOT_GEN_MISC_CLR(i) (0x30388000UL + 0x80 * (i) + 0x18) +#define CCM_CORE_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x1c) +#define CCM_CORE_CLK_ROOT_GEN_NM_POST(i) (0x30388000UL + 0x80 * (i) + 0x20) +#define CCM_CORE_CLK_ROOT_GEN_NM_POST_SET(i) (0x30388000UL + 0x80 * (i) + 0x24) +#define CCM_CORE_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30388000UL + 0x80 * (i) + 0x28) +#define CCM_CORE_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x2c) +#define CCM_CORE_CLK_ROOT_GEN_NM_PRE(i) (0x30388000UL + 0x80 * (i) + 0x30) +#define CCM_CORE_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30388000UL + 0x80 * (i) + 0x3c) +#define CCM_CORE_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30388000UL + 0x80 * (i) + 0x38) +#define CCM_CORE_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x3c) +#define CCM_CORE_CLK_ROOT_GEN_DB_POST(i) (0x30388000UL + 0x80 * (i) + 0x40) +#define CCM_CORE_CLK_ROOT_GEN_DB_POST_SET(i) (0x30388000UL + 0x80 * (i) + 0x44) +#define CCM_CORE_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30388000UL + 0x80 * (i) + 0x48) +#define CCM_CORE_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30388000UL + 0x80 * (i) + 0x4c) +#define CCM_CORE_CLK_ROOT_GEN_DB_PRE(i) (0x30388000UL + 0x80 * (i) + 0x50) +#define CCM_CORE_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30388000UL + 0x80 * (i) + 0x54) +#define CCM_CORE_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30388000UL + 0x80 * (i) + 0x58) +#define CCM_CORE_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x5c) +#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL(i) (0x30388000UL + 0x80 * (i) + 0x70) +#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30388000UL + 0x80 * (i) + 0x74) +#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30388000UL + 0x80 * (i) + 0x78) +#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30388000UL + 0x80 * (i) +0x7c) + + +/* BUS clock generation: i ranges from 0 to 11 */ +#define CCM_BUS_CLK_ROOT_GEN_TAGET(i) (0x30388800UL + 0x80 * (i) + 0x00) +#define CCM_BUS_CLK_ROOT_GEN_TAGET_SET(i) (0x30388800UL + 0x80 * (i) + 0x04) +#define CCM_BUS_CLK_ROOT_GEN_TAGET_CLR(i) (0x30388800UL + 0x80 * (i) + 0x08) +#define CCM_BUS_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x0c) +#define CCM_BUS_CLK_ROOT_GEN_MISC(i) (0x30388800UL + 0x80 * (i) + 0x10) +#define CCM_BUS_CLK_ROOT_GEN_MISC_SET(i) (0x30388800UL + 0x80 * (i) + 0x14) +#define CCM_BUS_CLK_ROOT_GEN_MISC_CLR(i) (0x30388800UL + 0x80 * (i) + 0x18) +#define CCM_BUS_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x1c) +#define CCM_BUS CLK_ROOT_GEN_NM_POST(i) (0x30388800UL + 0x80 * (i) + 0x20) +#define CCM_BUS_CLK_ROOT_GEN_NM_POST_SET(i) (0x30388800UL + 0x80 * (i) + 0x24) +#define CCM_BUS_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30388800UL + 0x80 * (i) + 0x28) +#define CCM_BUS_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x2c) +#define CCM_BUS_CLK_ROOT_GEN_NM_PRE(i) (0x30388800UL + 0x80 * (i) + 0x30) +#define CCM_BUS_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30388800UL + 0x80 * (i) + 0x3c) +#define CCM_BUS_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30388800UL + 0x80 * (i) + 0x38) +#define CCM_BUS_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x3c) +#define CCM_BUS_CLK_ROOT_GEN_DB_POST(i) (0x30388800UL + 0x80 * (i) + 0x40) +#define CCM_BUS_CLK_ROOT_GEN_DB_POST_SET(i) (0x30388800UL + 0x80 * (i) + 0x44) +#define CCM_BUS_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30388800UL + 0x80 * (i) + 0x48) +#define CCM_BUS_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30388800UL + 0x80 * (i) + 0x4c) +#define CCM_BUS_CLK_ROOT_GEN_DB_PRE(i) (0x30388800UL + 0x80 * (i) + 0x50) +#define CCM_BUS_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30388800UL + 0x80 * (i) + 0x54) +#define CCM_BUS_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30388800UL + 0x80 * (i) + 0x58) +#define CCM_BUS_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x5c) +#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL(i) (0x30388800UL + 0x80 * (i) + 0x70) +#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30388800UL + 0x80 * (i) + 0x74) +#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30388800UL + 0x80 * (i) + 0x78) +#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x7c) + +/* IP clock generation: i ranges from 0 to 77 */ +#define CCM_IP_CLK_ROOT_GEN_TAGET(i) (0x3038a000UL + 0x80 * (i) + 0x00) +#define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (0x3038a000UL + 0x80 * (i) + 0x04) +#define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x08) +#define CCM_IP_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x0c) +#define CCM_IP_CLK_ROOT_GEN_MISC(i) (0x3038a000UL + 0x80 * (i) + 0x10) +#define CCM_IP_CLK_ROOT_GEN_MISC_SET(i) (0x3038a000UL + 0x80 * (i) + 0x14) +#define CCM_IP_CLK_ROOT_GEN_MISC_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x18) +#define CCM_IP_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x1c) +#define CCM_IP_CLK_ROOT_GEN_NM_POST(i) (0x3038a000UL + 0x80 * (i) + 0x20) +#define CCM_IP_CLK_ROOT_GEN_NM_POST_SET(i) (0x3038a000UL + 0x80 * (i) + 0x24) +#define CCM_IP_CLK_ROOT_GEN_NM_POST_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x28) +#define CCM_IP_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x2c) +#define CCM_IP_CLK_ROOT_GEN_NM_PRE(i) (0x3038a000UL + 0x80 * (i) + 0x30) +#define CCM_IP_CLK_ROOT_GEN_NM_PRE_SET(i) (0x3038a000UL + 0x80 * (i) + 0x3c) +#define CCM_IP_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x38) +#define CCM_IP_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x3c) +#define CCM_IP_CLK_ROOT_GEN_DB_POST(i) (0x3038a000UL + 0x80 * (i) + 0x40) +#define CCM_IP_CLK_ROOT_GEN_DB_POST_SET(i) (0x3038a000UL + 0x80 * (i) + 0x44) +#define CCM_IP_CLK_ROOT_GEN_DB_POST_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x48) +#define CCM_IP_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x3038a000UL + 0x80 * (i) + 0x4c) +#define CCM_IP_CLK_ROOT_GEN_DB_PRE(i) (0x3038a000UL + 0x80 * (i) + 0x50) +#define CCM_IP_CLK_ROOT_GEN_DB_PRE_SET(i) (0x3038a000UL + 0x80 * (i) + 0x54) +#define CCM_IP_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x58) +#define CCM_IP_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x5c) +#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL(i) (0x3038a000UL + 0x80 * (i) + 0x70) +#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x3038a000UL + 0x80 * (i) + 0x74) +#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x78) +#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x7c) + +/* AHB clock generation: i ranges from 0 to 1*/ +#define CCM_AHB_CLK_ROOT_GEN_TAGET(i) (0x30389000UL + 0x80 * (i) + 0x00) +#define CCM_AHB_CLK_ROOT_GEN_TAGET_SET(i) (0x30389000UL + 0x80 * (i) + 0x04) +#define CCM_AHB_CLK_ROOT_GEN_TAGET_CLR(i) (0x30389000UL + 0x80 * (i) + 0x08) +#define CCM_AHB_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x0c) +#define CCM_AHB_CLK_ROOT_GEN_MISC(i) (0x30389000UL + 0x80 * (i) + 0x10) +#define CCM_AHB_CLK_ROOT_GEN_MISC_SET(i) (0x30389000UL + 0x80 * (i) + 0x14) +#define CCM_AHB_CLK_ROOT_GEN_MISC_CLR(i) (0x30389000UL + 0x80 * (i) + 0x18) +#define CCM_AHB_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x1c) +#define CCM_AHB CLK_ROOT_GEN_NM_POST(i) (0x30389000UL + 0x80 * (i) + 0x20) +#define CCM_AHB_CLK_ROOT_GEN_NM_POST_SET(i) (0x30389000UL + 0x80 * (i) + 0x24) +#define CCM_AHB_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30389000UL + 0x80 * (i) + 0x28) +#define CCM_AHB_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x2c) +#define CCM_AHB_CLK_ROOT_GEN_NM_PRE(i) (0x30389000UL + 0x80 * (i) + 0x30) +#define CCM_AHB_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30389000UL + 0x80 * (i) + 0x3c) +#define CCM_AHB_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30389000UL + 0x80 * (i) + 0x38) +#define CCM_AHB_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x3c) +#define CCM_AHB_CLK_ROOT_GEN_DB_POST(i) (0x30389000UL + 0x80 * (i) + 0x40) +#define CCM_AHB_CLK_ROOT_GEN_DB_POST_SET(i) (0x30389000UL + 0x80 * (i) + 0x44) +#define CCM_AHB_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30389000UL + 0x80 * (i) + 0x48) +#define CCM_AHB_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30389000UL + 0x80 * (i) + 0x4c) +#define CCM_AHB_CLK_ROOT_GEN_DB_PRE(i) (0x30389000UL + 0x80 * (i) + 0x50) +#define CCM_AHB_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30389000UL + 0x80 * (i) + 0x54) +#define CCM_AHB_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30389000UL + 0x80 * (i) + 0x58) +#define CCM_AHB_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x5c) +#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL(i) (0x30389000UL + 0x80 * (i) + 0x70) +#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30389000UL + 0x80 * (i) + 0x74) +#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30389000UL + 0x80 * (i) + 0x78) +#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x7c) + +/* IPG clock generation: i ranges from 0 to 1*/ +#define CCM_IPG_CLK_ROOT_GEN_TAGET(i) (0x30389080UL + 0x80 * (i) + 0x00) +#define CCM_IPG_CLK_ROOT_GEN_TAGET_SET(i) (0x30389080UL + 0x80 * (i) + 0x04) +#define CCM_IPG_CLK_ROOT_GEN_TAGET_CLR(i) (0x30389080UL + 0x80 * (i) + 0x08) +#define CCM_IPG_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x0c) +#define CCM_IPG_CLK_ROOT_GEN_MISC(i) (0x30389080UL + 0x80 * (i) + 0x10) +#define CCM_IPG_CLK_ROOT_GEN_MISC_SET(i) (0x30389080UL + 0x80 * (i) + 0x14) +#define CCM_IPG_CLK_ROOT_GEN_MISC_CLR(i) (0x30389080UL + 0x80 * (i) + 0x18) +#define CCM_IPG_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x1c) +#define CCM_IPG CLK_ROOT_GEN_NM_POST(i) (0x30389080UL + 0x80 * (i) + 0x20) +#define CCM_IPG_CLK_ROOT_GEN_NM_POST_SET(i) (0x30389080UL + 0x80 * (i) + 0x24) +#define CCM_IPG_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30389080UL + 0x80 * (i) + 0x28) +#define CCM_IPG_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x2c) +#define CCM_IPG_CLK_ROOT_GEN_NM_PRE(i) (0x30389080UL + 0x80 * (i) + 0x30) +#define CCM_IPG_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30389080UL + 0x80 * (i) + 0x3c) +#define CCM_IPG_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30389080UL + 0x80 * (i) + 0x38) +#define CCM_IPG_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x3c) +#define CCM_IPG_CLK_ROOT_GEN_DB_POST(i) (0x30389080UL + 0x80 * (i) + 0x40) +#define CCM_IPG_CLK_ROOT_GEN_DB_POST_SET(i) (0x30389080UL + 0x80 * (i) + 0x44) +#define CCM_IPG_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30389080UL + 0x80 * (i) + 0x48) +#define CCM_IPG_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30389080UL + 0x80 * (i) + 0x4c) +#define CCM_IPG_CLK_ROOT_GEN_DB_PRE(i) (0x30389080UL + 0x80 * (i) + 0x50) +#define CCM_IPG_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30389080UL + 0x80 * (i) + 0x54) +#define CCM_IPG_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30389080UL + 0x80 * (i) + 0x58) +#define CCM_IPG_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x5c) +#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL(i) (0x30389080UL + 0x80 * (i) + 0x70) +#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30389080UL + 0x80 * (i) + 0x74) +#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30389080UL + 0x80 * (i) + 0x78) +#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x7c) + +/* CORE_SEL clock generation */ +#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET (0x30389880UL + 0x00) +#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET_SET (0x30389880UL + 0x04) +#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET_CLR (0x30389880UL + 0x08) +#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET_TOGGLE (0x30389880UL + 0x0c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC (0x30389880UL + 0x10) +#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC_SET (0x30389880UL + 0x14) +#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC_CLR (0x30389880UL + 0x18) +#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC_TOGGLE (0x30389880UL + 0x1c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST (0x30389880UL + 0x20) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST_SET (0x30389880UL + 0x24) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST_CLR (0x30389880UL + 0x28) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST_TOGGLE (0x30389880UL + 0x2c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE (0x30389880UL + 0x30) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE_SET (0x30389880UL + 0x3c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE_CLR (0x30389880UL + 0x38) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE_TOGGLE (0x30389880UL + 0x3c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST (0x30389880UL + 0x40) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST_SET (0x30389880UL + 0x44) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST_CLR (0x30389880UL + 0x48) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST_TOGGL (0x30389880UL + 0x4c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE (0x30389880UL + 0x50) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE_SET (0x30389880UL + 0x54) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE_CLR (0x30389880UL + 0x58) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE_TOGGLE (0x30389880UL + 0x5c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL (0x30389880UL + 0x70) +#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL_SET (0x30389880UL + 0x74) +#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL_CLR (0x30389880UL + 0x78) +#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL_TOGGLE (0x30389880UL + 0x7c) + +/* DRAM_SEL clock generation */ +#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET (0x30389800UL + 0x00) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET_SET (0x30389800UL + 0x04) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET_CLR (0x30389800UL + 0x08) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET_TOGGLE (0x30389800UL + 0x0c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC (0x30389800UL + 0x10) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC_SET (0x30389800UL + 0x14) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC_CLR (0x30389800UL + 0x18) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC_TOGGLE (0x30389800UL + 0x1c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST (0x30389800UL + 0x20) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST_SET (0x30389800UL + 0x24) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST_CLR (0x30389800UL + 0x28) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST_TOGGLE (0x30389800UL + 0x2c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE (0x30389800UL + 0x30) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE_SET (0x30389800UL + 0x3c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE_CLR (0x30389800UL + 0x38) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE_TOGGLE (0x30389800UL + 0x3c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST (0x30389800UL + 0x40) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST_SET (0x30389800UL + 0x44) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST_CLR (0x30389800UL + 0x48) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST_TOGGL (0x30389800UL + 0x4c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE (0x30389800UL + 0x50) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE_SET (0x30389800UL + 0x54) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE_CLR (0x30389800UL + 0x58) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE_TOGGLE (0x30389800UL + 0x5c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL (0x30389800UL + 0x70) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL_SET (0x30389800UL + 0x74) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL_CLR (0x30389800UL + 0x78) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL_TOGGLE (0x30389800UL + 0x7c) + +/* CCGR: i ranges from 0 to 191 */ +#define CCM_CCGR(i) (0x30384000UL + 0x10 * (i) + 0x00) +#define CCM_CCGR_SET(i) (0x30384000UL + 0x10 * (i) + 0x04) +#define CCM_CCGR_CLR(i) (0x30384000UL + 0x10 * (i) + 0x08) +#define CCM_CCGR_TOGGLE(i) (0x30384000UL + 0x10 * (i) + 0x0c) + +/* Source Control: i ranges from 0 to 38 */ +#define CCM_SRC(i) (0x30380800UL + 0x10 * (i) + 0x00) +#define CCM_SRC_SET(i) (0x30380800UL + 0x10 * (i) + 0x04) +#define CCM_SRC_CLR(i) (0x30380800UL + 0x10 * (i) + 0x08) +#define CCM_SRC_TOGGLE(i) (0x30380800UL + 0x10 * (i) + 0x0c) + +/* Observe Control: i ranges from 0 to 7 */ +#define CCM_OBSERVE(i) (0x30380400UL + 0x10 * (i) + 0x00) +#define CCM_OBSERVE_SET(i) (0x30380400UL + 0x10 * (i) + 0x04) +#define CCM_OBSERVE_CLR(i) (0x30380400UL + 0x10 * (i) + 0x08) +#define CCM_OBSERVE_TOGGLE(i) (0x30380400UL + 0x10 * (i) + 0x0c) + +/* Generic Control: i ranges from 0 to 9 */ +#define CCM_GEN(i) (0x30380000UL + 0x10 * (i) + 0x00) +#define CCM_GEN_SET(i) (0x30380000UL + 0x10 * (i) + 0x04) +#define CCM_GEN_CLR(i) (0x30380000UL + 0x10 * (i) + 0x08) +#define CCM_GEN_TOGGLE(i) (0x30380000UL + 0x10 * (i) + 0x0c) + +#define CCGR_CLK_ON_MASK 0x03 +#define CLK_SRC_ON_MASK 0x03 + +#define CLK_ROOT_ON BIT(28) +#define CLK_ROOT_OFF (0 << 28) +#define CLK_ROOT_ENABLE_MASK BIT(28) +#define CLK_ROOT_ENABLE_SHIFT 28 +#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24) + +/* For SEL, only use 1 bit */ +#define CLK_ROOT_SRC_MUX_MASK 0x07000000 +#define CLK_ROOT_SRC_MUX_SHIFT 24 +#define CLK_ROOT_SRC_0 0x00000000 +#define CLK_ROOT_SRC_1 0x01000000 +#define CLK_ROOT_SRC_2 0x02000000 +#define CLK_ROOT_SRC_3 0x03000000 +#define CLK_ROOT_SRC_4 0x04000000 +#define CLK_ROOT_SRC_5 0x05000000 +#define CLK_ROOT_SRC_6 0x06000000 +#define CLK_ROOT_SRC_7 0x07000000 + +#define CLK_ROOT_PRE_DIV_MASK (0x00070000) +#define CLK_ROOT_PRE_DIV_SHIFT 16 +#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000) + +#define CLK_ROOT_AUDO_SLOW_EN 0x1000 + +#define CLK_ROOT_AUDO_DIV_MASK 0x700 +#define CLK_ROOT_AUDO_DIV_SHIFT 0x8 +#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700) + +/* For CORE: mask is 0x7; For IPG: mask is 0x3 */ +#define CLK_ROOT_POST_DIV_MASK 0x3f +#define CLK_ROOT_CORE_POST_DIV_MASK 0x7 +#define CLK_ROOT_IPG_POST_DIV_MASK 0x3 +#define CLK_ROOT_POST_DIV_SHIFT 0 +#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f) + +/* TODO check more */ +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 +#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000 +#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 + +enum enet_freq { + ENET_25MHZ = 0, + ENET_50MHZ, + ENET_125MHZ, +}; +void dram_pll_init(enum dram_pll_out_val pll_val); +void dram_enable_bypass(enum dram_bypassclk_val clk_val); +void dram_disable_bypass(void); +u32 imx_get_fecclk(void); +u32 imx_get_uartclk(void); +int clock_init(void); +u32 mxc_get_clock(enum mxc_clock clk); +int clock_enable(enum clk_ccgr_index index, bool enable); +int clock_root_enabled(enum clk_root_index clock_id); +int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, + enum root_post_div post_div, enum clk_root_src clock_src); +int clock_set_target_val(enum clk_root_index clock_id, u32 val); +int clock_get_target_val(enum clk_root_index clock_id, u32 *val); +int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); +int clock_get_postdiv(enum clk_root_index clock_id, + enum root_post_div *post_div); +int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); +void mxs_set_lcdclk(u32 base_addr, u32 freq); +int set_clk_qspi(void); +void enable_ocotp_clk(unsigned char enable); +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); +int set_clk_enet(enum enet_freq type); +void hab_caam_clock_enable(unsigned char enable); +void enable_usboh3_clk(unsigned char enable); +#endif diff --git a/arch/arm/include/asm/arch-mx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h similarity index 94% rename from arch/arm/include/asm/arch-mx8m/clock.h rename to arch/arm/include/asm/arch-imx8m/clock_imx8mq.h index 555512b4536..3f1b18f7244 100644 --- a/arch/arm/include/asm/arch-mx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h @@ -503,6 +503,12 @@ struct ccm_reg { #define CLK_ROOT_POST_DIV_SHIFT 0 #define CLK_ROOT_POST_DIV(n) ((n) & 0x3f) +/* IP clock generation: i ranges from 0 to 77 */ +#define CCM_IP_CLK_ROOT_GEN_TAGET(i) (0x3038a000UL + 0x80 * (i) + 0x00) +#define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (0x3038a000UL + 0x80 * (i) + 0x04) +#define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x08) +#define CCM_IP_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x0c) + /* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/ #define FRAC_PLL_LOCK_MASK BIT(31) #define FRAC_PLL_CLKE_MASK BIT(21) @@ -632,11 +638,40 @@ enum frac_pll_out_val { FRAC_PLL_OUT_1600M, }; +enum sscg_pll_out_val { + SSCG_PLL_OUT_400M, + SSCG_PLL_OUT_600M, + SSCG_PLL_OUT_800M, +}; + +enum dram_pll_out_val { + DRAM_PLL_OUT_100M, + DRAM_PLL_OUT_167M, + DRAM_PLL_OUT_266M, + DRAM_PLL_OUT_667M, + DRAM_PLL_OUT_400M, + DRAM_PLL_OUT_600M, + DRAM_PLL_OUT_700M, + DRAM_PLL_OUT_750M, + DRAM_PLL_OUT_800M, +}; + +enum dram_bypassclk_val { + DRAM_BYPASSCLK_100M, + DRAM_BYPASSCLK_250M, + DRAM_BYPASSCLK_400M, +}; + +void dram_pll_init(enum dram_pll_out_val pll_val); +void dram_enable_bypass(enum dram_bypassclk_val clk_val); +void dram_disable_bypass(void); u32 imx_get_fecclk(void); u32 imx_get_uartclk(void); int clock_init(void); void init_clk_usdhc(u32 index); +void init_nand_clk(void); void init_uart_clk(u32 index); +void init_usb_clk(void); void init_wdog_clk(void); unsigned int mxc_get_clock(enum clk_root_index clk); int clock_enable(enum clk_ccgr_index index, bool enable); @@ -654,4 +689,5 @@ int set_clk_qspi(void); void enable_ocotp_clk(unsigned char enable); int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); int set_clk_enet(enum enet_freq type); +void hab_caam_clock_enable(unsigned char enable); #endif diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h b/arch/arm/include/asm/arch-imx8m/crm_regs.h similarity index 100% rename from arch/arm/include/asm/arch-mx8m/crm_regs.h rename to arch/arm/include/asm/arch-imx8m/crm_regs.h diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h new file mode 100644 index 00000000000..0ec9fc62588 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -0,0 +1,856 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX8M_DDR_H +#define __ASM_ARCH_MX8M_DDR_H + +#define DDRC_DDR_SS_GPR0 0x3d000000 +#define DDRC_IPS_BASE_ADDR_0 0x3f400000 +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) +#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) + +struct ddrc_freq { + u32 res0[8]; + u32 derateen; + u32 derateint; + u32 res1[10]; + u32 rfshctl0; + u32 res2[4]; + u32 rfshtmg; + u32 rfshtmg1; + u32 res3[28]; + u32 init3; + u32 init4; + u32 res; + u32 init6; + u32 init7; + u32 res4[4]; + u32 dramtmg0; + u32 dramtmg1; + u32 dramtmg2; + u32 dramtmg3; + u32 dramtmg4; + u32 dramtmg5; + u32 dramtmg6; + u32 dramtmg7; + u32 dramtmg8; + u32 dramtmg9; + u32 dramtmg10; + u32 dramtmg11; + u32 dramtmg12; + u32 dramtmg13; + u32 dramtmg14; + u32 dramtmg15; + u32 dramtmg16; + u32 dramtmg17; + u32 res5[10]; + u32 mramtmg0; + u32 mramtmg1; + u32 mramtmg4; + u32 mramtmg9; + u32 zqctl0; + u32 res6[3]; + u32 dfitmg0; + u32 dfitmg1; + u32 res7[7]; + u32 dfitmg2; + u32 dfitmg3; + u32 res8[33]; + u32 odtcfg; +}; + +struct imx8m_ddrc_regs { + u32 mstr; + u32 stat; + u32 mstr1; + u32 res1; + u32 mrctrl0; + u32 mrctrl1; + u32 mrstat; + u32 mrctrl2; + u32 derateen; + u32 derateint; + u32 mstr2; + u32 res2; + u32 pwrctl; + u32 pwrtmg; + u32 hwlpctl; + u32 hwffcctl; + u32 hwffcstat; + u32 res3[3]; + u32 rfshctl0; + u32 rfshctl1; + u32 rfshctl2; + u32 rfshctl4; + u32 rfshctl3; + u32 rfshtmg; + u32 rfshtmg1; + u32 res4; + u32 ecccfg0; + u32 ecccfg1; + u32 eccstat; + u32 eccclr; + u32 eccerrcnt; + u32 ecccaddr0; + u32 ecccaddr1; + u32 ecccsyn0; + u32 ecccsyn1; + u32 ecccsyn2; + u32 eccbitmask0; + u32 eccbitmask1; + u32 eccbitmask2; + u32 eccuaddr0; + u32 eccuaddr1; + u32 eccusyn0; + u32 eccusyn1; + u32 eccusyn2; + u32 eccpoisonaddr0; + u32 eccpoisonaddr1; + u32 crcparctl0; + u32 crcparctl1; + u32 crcparctl2; + u32 crcparstat; + u32 init0; + u32 init1; + u32 init2; + u32 init3; + u32 init4; + u32 init5; + u32 init6; + u32 init7; + u32 dimmctl; + u32 rankctl; + u32 res5; + u32 chctl; + u32 dramtmg0; + u32 dramtmg1; + u32 dramtmg2; + u32 dramtmg3; + u32 dramtmg4; + u32 dramtmg5; + u32 dramtmg6; + u32 dramtmg7; + u32 dramtmg8; + u32 dramtmg9; + u32 dramtmg10; + u32 dramtmg11; + u32 dramtmg12; + u32 dramtmg13; + u32 dramtmg14; + u32 dramtmg15; + u32 dramtmg16; + u32 dramtmg17; + u32 res6[10]; + u32 mramtmg0; + u32 mramtmg1; + u32 mramtmg4; + u32 mramtmg9; + u32 zqctl0; + u32 zqctl1; + u32 zqctl2; + u32 zqstat; + u32 dfitmg0; + u32 dfitmg1; + u32 dfilpcfg0; + u32 dfilpcfg1; + u32 dfiupd0; + u32 dfiupd1; + u32 dfiupd2; + u32 res7; + u32 dfimisc; + u32 dfitmg2; + u32 dfitmg3; + u32 dfistat; + u32 dbictl; + u32 dfiphymstr; + u32 res8[14]; + u32 addrmap0; + u32 addrmap1; + u32 addrmap2; + u32 addrmap3; + u32 addrmap4; + u32 addrmap5; + u32 addrmap6; + u32 addrmap7; + u32 addrmap8; + u32 addrmap9; + u32 addrmap10; + u32 addrmap11; + u32 res9[4]; + u32 odtcfg; + u32 odtmap; + u32 res10[2]; + u32 sched; + u32 sched1; + u32 sched2; + u32 perfhpr1; + u32 res11; + u32 perflpr1; + u32 res12; + u32 perfwr1; + u32 res13[4]; + u32 dqmap0; + u32 dqmap1; + u32 dqmap2; + u32 dqmap3; + u32 dqmap4; + u32 dqmap5; + u32 res14[26]; + u32 dbg0; + u32 dbg1; + u32 dbgcam; + u32 dbgcmd; + u32 dbgstat; + u32 res15[3]; + u32 swctl; + u32 swstat; + u32 res16[2]; + u32 ocparcfg0; + u32 ocparcfg1; + u32 ocparcfg2; + u32 ocparcfg3; + u32 ocparstat0; + u32 ocparstat1; + u32 ocparwlog0; + u32 ocparwlog1; + u32 ocparwlog2; + u32 ocparawlog0; + u32 ocparawlog1; + u32 ocparrlog0; + u32 ocparrlog1; + u32 ocpararlog0; + u32 ocpararlog1; + u32 poisoncfg; + u32 poisonstat; + u32 adveccindex; + union { + u32 adveccstat; + u32 eccapstat; + }; + u32 eccpoisonpat0; + u32 eccpoisonpat1; + u32 eccpoisonpat2; + u32 res17[6]; + u32 caparpoisonctl; + u32 caparpoisonstat; + u32 res18[2]; + u32 dynbsmstat; + u32 res19[18]; + u32 pstat; + u32 pccfg; + struct { + u32 pcfgr; + u32 pcfgw; + u32 pcfgc; + struct { + u32 pcfgidmaskch0; + u32 pcfidvaluech0; + } pcfgid[16]; + u32 pctrl; + u32 pcfgqos0; + u32 pcfgqos1; + u32 pcfgwqos0; + u32 pcfgwqos1; + u32 res[4]; + } pcfg[16]; + struct { + u32 sarbase; + u32 sarsize; + } sar[4]; + u32 sbrctl; + u32 sbrstat; + u32 sbrwdata0; + u32 sbrwdata1; + u32 pdch; + u32 res20[755]; + /* umctl2_regs_dch1 */ + u32 ch1_stat; + u32 res21[2]; + u32 ch1_mrctrl0; + u32 ch1_mrctrl1; + u32 ch1_mrstat; + u32 ch1_mrctrl2; + u32 res22[4]; + u32 ch1_pwrctl; + u32 ch1_pwrtmg; + u32 ch1_hwlpctl; + u32 res23[15]; + u32 ch1_eccstat; + u32 ch1_eccclr; + u32 ch1_eccerrcnt; + u32 ch1_ecccaddr0; + u32 ch1_ecccaddr1; + u32 ch1_ecccsyn0; + u32 ch1_ecccsyn1; + u32 ch1_ecccsyn2; + u32 ch1_eccbitmask0; + u32 ch1_eccbitmask1; + u32 ch1_eccbitmask2; + u32 ch1_eccuaddr0; + u32 ch1_eccuaddr1; + u32 ch1_eccusyn0; + u32 ch1_eccusyn1; + u32 ch1_eccusyn2; + u32 res24[2]; + u32 ch1_crcparctl0; + u32 res25[2]; + u32 ch1_crcparstat; + u32 res26[46]; + u32 ch1_zqctl2; + u32 ch1_zqstat; + u32 res27[11]; + u32 ch1_dfistat; + u32 res28[33]; + u32 ch1_odtmap; + u32 res29[47]; + u32 ch1_dbg1; + u32 ch1_dbgcam; + u32 ch1_dbgcmd; + u32 ch1_dbgstat; + u32 res30[123]; + /* umctl2_regs_freq1 */ + struct ddrc_freq freq1; + u32 res31[109]; + /* umctl2_regs_addrmap_alt */ + u32 addrmap0_alt; + u32 addrmap1_alt; + u32 addrmap2_alt; + u32 addrmap3_alt; + u32 addrmap4_alt; + u32 addrmap5_alt; + u32 addrmap6_alt; + u32 addrmap7_alt; + u32 addrmap8_alt; + u32 addrmap9_alt; + u32 addrmap10_alt; + u32 addrmap11_alt; + u32 res32[758]; + /* umctl2_regs_freq2 */ + struct ddrc_freq freq2; + u32 res33[879]; + /* umctl2_regs_freq3 */ + struct ddrc_freq freq3; +}; + +struct imx8m_ddrphy_regs { + u32 reg[0xf0000]; +}; + +/* PHY State */ +enum pstate { + PS0, + PS1, + PS2, + PS3, +}; + +enum msg_response { + TRAIN_SUCCESS = 0x7, + TRAIN_STREAM_START = 0x8, + TRAIN_FAIL = 0xff, +}; + +#define DDRC_MSTR_0 0x3d400000 +#define DDRC_STAT_0 0x3d400004 +#define DDRC_MSTR1_0 0x3d400008 +#define DDRC_MRCTRL0_0 0x3d400010 +#define DDRC_MRCTRL1_0 0x3d400014 +#define DDRC_MRSTAT_0 0x3d400018 +#define DDRC_MRCTRL2_0 0x3d40001c +#define DDRC_DERATEEN_0 0x3d400020 +#define DDRC_DERATEINT_0 0x3d400024 +#define DDRC_MSTR2_0 0x3d400028 +#define DDRC_PWRCTL_0 0x3d400030 +#define DDRC_PWRTMG_0 0x3d400034 +#define DDRC_HWLPCTL_0 0x3d400038 +#define DDRC_HWFFCCTL_0 0x3d40003c +#define DDRC_HWFFCSTAT_0 0x3d400040 +#define DDRC_RFSHCTL0_0 0x3d400050 +#define DDRC_RFSHCTL1_0 0x3d400054 +#define DDRC_RFSHCTL2_0 0x3d400058 +#define DDRC_RFSHCTL3_0 0x3d400060 +#define DDRC_RFSHTMG_0 0x3d400064 +#define DDRC_ECCCFG0_0 0x3d400070 +#define DDRC_ECCCFG1_0 0x3d400074 +#define DDRC_ECCSTAT_0 0x3d400078 +#define DDRC_ECCCLR_0 0x3d40007c +#define DDRC_ECCERRCNT_0 0x3d400080 +#define DDRC_ECCCADDR0_0 0x3d400084 +#define DDRC_ECCCADDR1_0 0x3d400088 +#define DDRC_ECCCSYN0_0 0x3d40008c +#define DDRC_ECCCSYN1_0 0x3d400090 +#define DDRC_ECCCSYN2_0 0x3d400094 +#define DDRC_ECCBITMASK0_0 0x3d400098 +#define DDRC_ECCBITMASK1_0 0x3d40009c +#define DDRC_ECCBITMASK2_0 0x3d4000a0 +#define DDRC_ECCUADDR0_0 0x3d4000a4 +#define DDRC_ECCUADDR1_0 0x3d4000a8 +#define DDRC_ECCUSYN0_0 0x3d4000ac +#define DDRC_ECCUSYN1_0 0x3d4000b0 +#define DDRC_ECCUSYN2_0 0x3d4000b4 +#define DDRC_ECCPOISONADDR0_0 0x3d4000b8 +#define DDRC_ECCPOISONADDR1_0 0x3d4000bc +#define DDRC_CRCPARCTL0_0 0x3d4000c0 +#define DDRC_CRCPARCTL1_0 0x3d4000c4 +#define DDRC_CRCPARCTL2_0 0x3d4000c8 +#define DDRC_CRCPARSTAT_0 0x3d4000cc +#define DDRC_INIT0_0 0x3d4000d0 +#define DDRC_INIT1_0 0x3d4000d4 +#define DDRC_INIT2_0 0x3d4000d8 +#define DDRC_INIT3_0 0x3d4000dc +#define DDRC_INIT4_0 0x3d4000e0 +#define DDRC_INIT5_0 0x3d4000e4 +#define DDRC_INIT6_0 0x3d4000e8 +#define DDRC_INIT7_0 0x3d4000ec +#define DDRC_DIMMCTL_0 0x3d4000f0 +#define DDRC_RANKCTL_0 0x3d4000f4 +#define DDRC_DRAMTMG0_0 0x3d400100 +#define DDRC_DRAMTMG1_0 0x3d400104 +#define DDRC_DRAMTMG2_0 0x3d400108 +#define DDRC_DRAMTMG3_0 0x3d40010c +#define DDRC_DRAMTMG4_0 0x3d400110 +#define DDRC_DRAMTMG5_0 0x3d400114 +#define DDRC_DRAMTMG6_0 0x3d400118 +#define DDRC_DRAMTMG7_0 0x3d40011c +#define DDRC_DRAMTMG8_0 0x3d400120 +#define DDRC_DRAMTMG9_0 0x3d400124 +#define DDRC_DRAMTMG10_0 0x3d400128 +#define DDRC_DRAMTMG11_0 0x3d40012c +#define DDRC_DRAMTMG12_0 0x3d400130 +#define DDRC_DRAMTMG13_0 0x3d400134 +#define DDRC_DRAMTMG14_0 0x3d400138 +#define DDRC_DRAMTMG15_0 0x3d40013C +#define DDRC_DRAMTMG16_0 0x3d400140 +#define DDRC_DRAMTMG17_0 0x3d400144 + +#define DDRC_ZQCTL0_0 0x3d400180 +#define DDRC_ZQCTL1_0 0x3d400184 +#define DDRC_ZQCTL2_0 0x3d400188 +#define DDRC_ZQSTAT_0 0x3d40018c +#define DDRC_DFITMG0_0 0x3d400190 +#define DDRC_DFITMG1_0 0x3d400194 +#define DDRC_DFILPCFG0_0 0x3d400198 +#define DDRC_DFILPCFG1_0 0x3d40019c +#define DDRC_DFIUPD0_0 0x3d4001a0 +#define DDRC_DFIUPD1_0 0x3d4001a4 +#define DDRC_DFIUPD2_0 0x3d4001a8 + +#define DDRC_DFIMISC_0 0x3d4001b0 +#define DDRC_DFITMG2_0 0x3d4001b4 +#define DDRC_DFITMG3_0 0x3d4001b8 +#define DDRC_DFISTAT_0 0x3d4001bc + +#define DDRC_DBICTL_0 0x3d4001c0 +#define DDRC_DFIPHYMSTR_0 0x3d4001c4 +#define DDRC_TRAINCTL0_0 0x3d4001d0 +#define DDRC_TRAINCTL1_0 0x3d4001d4 +#define DDRC_TRAINCTL2_0 0x3d4001d8 +#define DDRC_TRAINSTAT_0 0x3d4001dc +#define DDRC_ADDRMAP0_0 0x3d400200 +#define DDRC_ADDRMAP1_0 0x3d400204 +#define DDRC_ADDRMAP2_0 0x3d400208 +#define DDRC_ADDRMAP3_0 0x3d40020c +#define DDRC_ADDRMAP4_0 0x3d400210 +#define DDRC_ADDRMAP5_0 0x3d400214 +#define DDRC_ADDRMAP6_0 0x3d400218 +#define DDRC_ADDRMAP7_0 0x3d40021c +#define DDRC_ADDRMAP8_0 0x3d400220 +#define DDRC_ADDRMAP9_0 0x3d400224 +#define DDRC_ADDRMAP10_0 0x3d400228 +#define DDRC_ADDRMAP11_0 0x3d40022c + +#define DDRC_ODTCFG_0 0x3d400240 +#define DDRC_ODTMAP_0 0x3d400244 +#define DDRC_SCHED_0 0x3d400250 +#define DDRC_SCHED1_0 0x3d400254 +#define DDRC_PERFHPR1_0 0x3d40025c +#define DDRC_PERFLPR1_0 0x3d400264 +#define DDRC_PERFWR1_0 0x3d40026c +#define DDRC_PERFVPR1_0 0x3d400274 + +#define DDRC_PERFVPW1_0 0x3d400278 + +#define DDRC_DQMAP0_0 0x3d400280 +#define DDRC_DQMAP1_0 0x3d400284 +#define DDRC_DQMAP2_0 0x3d400288 +#define DDRC_DQMAP3_0 0x3d40028c +#define DDRC_DQMAP4_0 0x3d400290 +#define DDRC_DQMAP5_0 0x3d400294 +#define DDRC_DBG0_0 0x3d400300 +#define DDRC_DBG1_0 0x3d400304 +#define DDRC_DBGCAM_0 0x3d400308 +#define DDRC_DBGCMD_0 0x3d40030c +#define DDRC_DBGSTAT_0 0x3d400310 + +#define DDRC_SWCTL_0 0x3d400320 +#define DDRC_SWSTAT_0 0x3d400324 +#define DDRC_OCPARCFG0_0 0x3d400330 +#define DDRC_OCPARCFG1_0 0x3d400334 +#define DDRC_OCPARCFG2_0 0x3d400338 +#define DDRC_OCPARCFG3_0 0x3d40033c +#define DDRC_OCPARSTAT0_0 0x3d400340 +#define DDRC_OCPARSTAT1_0 0x3d400344 +#define DDRC_OCPARWLOG0_0 0x3d400348 +#define DDRC_OCPARWLOG1_0 0x3d40034c +#define DDRC_OCPARWLOG2_0 0x3d400350 +#define DDRC_OCPARAWLOG0_0 0x3d400354 +#define DDRC_OCPARAWLOG1_0 0x3d400358 +#define DDRC_OCPARRLOG0_0 0x3d40035c +#define DDRC_OCPARRLOG1_0 0x3d400360 +#define DDRC_OCPARARLOG0_0 0x3d400364 +#define DDRC_OCPARARLOG1_0 0x3d400368 +#define DDRC_POISONCFG_0 0x3d40036C +#define DDRC_POISONSTAT_0 0x3d400370 +#define DDRC_ADVECCINDEX_0 0x3d400003 +#define DDRC_ADVECCSTAT_0 0x3d400003 +#define DDRC_ECCPOISONPAT0_0 0x3d400003 +#define DDRC_ECCPOISONPAT1_0 0x3d400003 +#define DDRC_ECCPOISONPAT2_0 0x3d400003 +#define DDRC_HIFCTL_0 0x3d400003 + +#define DDRC_PSTAT_0 0x3d4003fc +#define DDRC_PCCFG_0 0x3d400400 +#define DDRC_PCFGR_0_0 0x3d400404 +#define DDRC_PCFGR_1_0 0x3d4004b4 +#define DDRC_PCFGR_2_0 0x3d400564 +#define DDRC_PCFGR_3_0 0x3d400614 +#define DDRC_PCFGW_0_0 0x3d400408 +#define DDRC_PCFGW_1_0 0x3d400408 +#define DDRC_PCFGW_2_0 0x3d400568 +#define DDRC_PCFGW_3_0 0x3d400618 +#define DDRC_PCFGC_0_0 0x3d40040c +#define DDRC_PCFGIDMASKCH_0 0x3d400410 +#define DDRC_PCFGIDVALUECH_0 0x3d400414 +#define DDRC_PCTRL_0_0 0x3d400490 +#define DDRC_PCTRL_1_0 0x3d400540 +#define DDRC_PCTRL_2_0 0x3d4005f0 +#define DDRC_PCTRL_3_0 0x3d4006a0 +#define DDRC_PCFGQOS0_0_0 0x3d400494 +#define DDRC_PCFGQOS1_0_0 0x3d400498 +#define DDRC_PCFGWQOS0_0_0 0x3d40049c +#define DDRC_PCFGWQOS1_0_0 0x3d4004a0 +#define DDRC_SARBASE0_0 0x3d400f04 +#define DDRC_SARSIZE0_0 0x3d400f08 +#define DDRC_SBRCTL_0 0x3d400f24 +#define DDRC_SBRSTAT_0 0x3d400f28 +#define DDRC_SBRWDATA0_0 0x3d400f2c +#define DDRC_SBRWDATA1_0 0x3d400f30 +#define DDRC_PDCH_0 0x3d400f34 + +/**********************/ +#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) +#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) +#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) +#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) +#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) +#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) +#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) +#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) +#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24) +#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28) +#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) +#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34) +#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38) +#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c) +#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40) +#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50) +#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54) +#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58) +#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) +#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64) +#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70) +#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74) +#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78) +#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c) +#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80) +#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84) +#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88) +#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c) +#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90) +#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94) +#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98) +#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c) +#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0) +#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4) +#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8) +#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac) +#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0) +#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4) +#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8) +#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc) +#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0) +#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4) +#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8) +#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc) +#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0) +#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4) +#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8) +#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc) +#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0) +#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4) +#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8) +#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec) +#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0) +#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4) +#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100) +#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104) +#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108) +#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c) +#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110) +#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114) +#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118) +#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c) +#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120) +#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124) +#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128) +#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c) +#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130) +#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134) +#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138) +#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C) +#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140) +#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144) +#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180) +#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184) +#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188) +#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c) +#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190) +#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194) +#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198) +#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c) +#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0) +#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4) +#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8) +#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) +#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4) +#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8) +#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) +#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0) +#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4) +#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0) +#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4) +#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8) +#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc) +#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200) +#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204) +#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208) +#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c) +#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210) +#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214) +#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218) +#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c) +#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220) +#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224) +#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228) +#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c) +#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240) +#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244) +#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250) +#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254) +#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c) +#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264) +#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c) +#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274) +#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278) +#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280) +#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284) +#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288) +#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c) +#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290) +#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294) +#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300) +#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) +#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308) +#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c) +#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310) +#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) +#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324) +#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330) +#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334) +#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338) +#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c) +#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340) +#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344) +#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348) +#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c) +#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350) +#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354) +#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358) +#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c) +#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360) +#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364) +#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368) +#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C) +#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370) +#define DDRC_ADVECCINDEX(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ADVECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_HIFCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) + +#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc) +#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400) +#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404) +#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1*0xb0+0x404) +#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2*0xb0+0x404) +#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3*0xb0+0x404) +#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408) +#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1*0xb0+0x408) +#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2*0xb0+0x408) +#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3*0xb0+0x408) +#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c) +#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410) +#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414) +#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) +#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1*0xb0) +#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2*0xb0) +#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3*0xb0) +#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) +#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) +#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c) +#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0) +#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04) +#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08) +#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24) +#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28) +#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c) +#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30) +#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34) + +#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020) +#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024) +#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050) +#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064) +#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc) +#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0) +#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8) +#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec) +#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100) +#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104) +#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108) +#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c) +#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110) +#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114) +#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118) +#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c) +#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120) +#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124) +#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128) +#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c) +#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130) +#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134) +#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138) +#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C) +#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140) +#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144) +#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180) +#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020) +#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024) +#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050) +#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064) +#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc) +#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0) +#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8) +#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec) +#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100) +#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104) +#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108) +#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c) +#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110) +#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114) +#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118) +#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c) +#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120) +#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124) +#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128) +#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c) +#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130) +#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134) +#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138) +#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C) +#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140) +#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144) +#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180) +#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190) +#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194) +#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4) +#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8) +#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240) + +#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020) +#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024) +#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050) +#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064) +#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc) +#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0) +#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8) +#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec) +#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100) +#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104) +#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108) +#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c) +#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110) +#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114) +#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118) +#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c) +#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120) +#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124) +#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128) +#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c) +#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130) +#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134) +#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138) +#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C) +#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140) + +#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180) +#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190) +#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194) +#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4) +#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8) +#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240) +#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020097) + +#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + (X * 0x2000000)) +#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0) +#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4) +#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8) +#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC) +#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20) +#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24) +#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28) +#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C) +#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40) +#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44) +#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48) +#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C) +#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50) +#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54) +#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58) +#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C) +#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60) +#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64) +#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68) +#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C) +#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70) +#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74) +#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) +#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) + +#endif diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h b/arch/arm/include/asm/arch-imx8m/gpio.h similarity index 100% rename from arch/arm/include/asm/arch-mx8m/gpio.h rename to arch/arm/include/asm/arch-imx8m/gpio.h diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h b/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h new file mode 100644 index 00000000000..1fe316e19d0 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h @@ -0,0 +1,570 @@ +/* + * Copyright 2018-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_IMX8M_REGS_H +#define __ARCH_IMX8M_REGS_H + +#include + +/* Based on version 0.2.2 */ + +#define ROM_VERSION_A0 0x800 +#define ROM_VERSION_B0 0x800 +#define M4_BOOTROM_BASE_ADDR 0x007E0000 + +#define SAI1_BASE_ADDR 0x30010000 +#define SAI2_BASE_ADDR 0x30020000 +#define SAI3_BASE_ADDR 0x30030000 +#define SAI5_BASE_ADDR 0x30050000 +#define SAI6_BASE_ADDR 0x30060000 +#define MICFIL_BASE_ADDR 0x30080000 +#define SPDIF1_BASE_ADDR 0x30090000 +#define SPDIF2_BASE_ADDR 0x300A0000 +#define SPBA2_BASE_ADDR 0x300F0000 +#define AIPS1_BASE_ADDR 0x301F0000 +#define GPIO1_BASE_ADDR 0x30200000 +#define GPIO2_BASE_ADDR 0x30210000 +#define GPIO3_BASE_ADDR 0x30220000 +#define GPIO4_BASE_ADDR 0x30230000 +#define GPIO5_BASE_ADDR 0x30240000 +#define ANA_TSENSOR_ADDR 0x30260000 +#define ANA_OSC_BASE_ADDR 0x30270000 +#define WDOG1_BASE_ADDR 0x30280000 +#define WDOG2_BASE_ADDR 0x30290000 +#define WDOG3_BASE_ADDR 0x302A0000 +#define SDMA3_BASE_ADDR 0x302B0000 +#define SDMA2_BASE_ADDR 0x302C0000 +#define GPT1_BASE_ADDR 0x302D0000 +#define GPT2_BASE_ADDR 0x302E0000 +#define GPT3_BASE_ADDR 0x302F0000 +#define ROMCP_BASE_ADDR 0x30310000 +#define IOMUXC_BASE_ADDR 0x30330000 +#define IOMUXC_GPR_BASE_ADDR 0x30340000 +#define OCOTP_BASE_ADDR 0x30350000 +#define ANATOP_BASE_ADDR 0x30360000 +#define SNVS_HP_BASE_ADDR 0x30370000 +#define CCM_BASE_ADDR 0x30380000 +#define SRC_BASE_ADDR 0x30390000 +#define GPC_BASE_ADDR 0x303A0000 +#define SEMA1_BASE_ADDR 0x303B0000 +#define SEMA2_BASE_ADDR 0x303C0000 +#define RDC_BASE_ADDR 0x303D0000 +#define CSU_BASE_ADDR 0x303E0000 + +#define AIPS2_BASE_ADDR 0x305E0000 +#define PWM1_BASE_ADDR 0x30650000 +#define PWM2_BASE_ADDR 0x30660000 +#define PWM3_BASE_ADDR 0x30670000 +#define PWM4_BASE_ADDR 0x30680000 +#define SYSCNT_CTRL_BASE_ADDR 0x306C0000 +#define GPT6_BASE_ADDR 0x306D0000 +#define GPT5_BASE_ADDR 0x306E0000 +#define GPT4_BASE_ADDR 0x306F0000 +#define PERFMON1_ADDR 0x307B0000 +#define PERFMON2_ADDR 0x307C0000 +#define QOSC_BASE_ADDR 0x307E0000 + +#define ECSPI1_BASE_ADDR 0x30820000 +#define ECSPI2_BASE_ADDR 0x30830000 +#define ECSPI3_BASE_ADDR 0x30840000 +#define UART1_BASE_ADDR 0x30860000 +#define UART3_BASE_ADDR 0x30880000 +#define UART2_BASE_ADDR 0x30890000 +#define SPBA_BASE_ADDR 0x308F0000 +#define CAAM_BASE_ADDR 0x30900000 +#define AIPS3_BASE_ADDR 0x309F0000 +#define I2C1_BASE_ADDR 0x30A20000 +#define I2C2_BASE_ADDR 0x30A30000 +#define I2C3_BASE_ADDR 0x30A40000 +#define I2C4_BASE_ADDR 0x30A50000 +#define UART4_BASE_ADDR 0x30A60000 +#define MUA_BASE_ADDR 0x30AA0000 +#define MUB_BASE_ADDR 0x30AB0000 +#define SEMAHS_BASE_ADDR 0x30AC0000 +#define USDHC1_BASE_ADDR 0x30B40000 +#define USDHC2_BASE_ADDR 0x30B50000 +#define USDHC3_BASE_ADDR 0x30B60000 +#define QSPI_BASE_ADDR 0x30BB0000 +#define QSPI0_BASE_ADDR 0x30BB0000 +#define QSPI0_AMBA_BASE 0x08000000 +#define SDMA1_BASE_ADDR 0x30BD0000 +#define ENET1_BASE_ADDR 0x30BE0000 + +#define AIPS4_BASE_ADDR 0x32DF0000 +#define LCDIF_BASE_ADDR 0x32E00000 +#define MIPI_DSI_BASE_ADDR 0x32E10000 +#define CSI_BASE_ADDR 0x32E20000 +#define MIPI_CSI_BASE_ADDR 0x32E30000 +#define USB1_BASE_ADDR 0x32E40000 +#define USB2_BASE_ADDR 0x32E50000 +#define PCIE_PHY1_BASE_ADDR 0x32F00000 +#define TZASC_BASE_ADDR 0x32F80000 +#define PLAT_CTRL_BASE_ADDR 0x32FE0000 + +#define MXS_APBH_BASE 0x33000000 +#define MXS_GPMI_BASE 0x33002000 +#define MXS_BCH_BASE 0x33004000 + +#define USB_BASE_ADDR USB1_BASE_ADDR + +#define MXS_LCDIF_BASE LCDIF_BASE_ADDR + +#define IOMUXC_GPR0 (IOMUXC_GPR_BASE_ADDR + 0x00) +#define IOMUXC_GPR1 (IOMUXC_GPR_BASE_ADDR + 0x04) +#define IOMUXC_GPR2 (IOMUXC_GPR_BASE_ADDR + 0x08) +#define IOMUXC_GPR3 (IOMUXC_GPR_BASE_ADDR + 0x0c) +#define IOMUXC_GPR4 (IOMUXC_GPR_BASE_ADDR + 0x10) +#define IOMUXC_GPR5 (IOMUXC_GPR_BASE_ADDR + 0x14) +#define IOMUXC_GPR6 (IOMUXC_GPR_BASE_ADDR + 0x18) +#define IOMUXC_GPR7 (IOMUXC_GPR_BASE_ADDR + 0x1c) +#define IOMUXC_GPR8 (IOMUXC_GPR_BASE_ADDR + 0x20) +#define IOMUXC_GPR9 (IOMUXC_GPR_BASE_ADDR + 0x24) +#define IOMUXC_GPR10 (IOMUXC_GPR_BASE_ADDR + 0x28) +#define IOMUXC_GPR11 (IOMUXC_GPR_BASE_ADDR + 0x2C) +#define IOMUXC_GPR22 (IOMUXC_GPR_BASE_ADDR + 0x58) + +#define GPR_TZASC_EN (1 << 0) +#define GPR_TZASC_SWAP_ID (1 << 1) +#define GPR_TZASC_EN_LOCK (1 << 16) + +#define CNTCR_OFF 0x00 +#define CNTFID0_OFF 0x20 +#define CNTFID1_OFF 0x24 + +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) + +#define IMX_CSPI1_BASE 0x30820000 +#define IMX_CSPI2_BASE 0x30830000 +#define IMX_CSPI3_BASE 0x30840000 + +#define MXC_SPI_BASE_ADDRESSES \ + IMX_CSPI1_BASE, \ + IMX_CSPI2_BASE, \ + IMX_CSPI3_BASE + +#define SRC_IPS_BASE_ADDR 0x30390000 +#define SRC_DDRC_RCR_ADDR 0x30391000 +#define SRC_DDRC2_RCR_ADDR 0x30391004 + +#define DDRC_DDR_SS_GPR0 0x3d000000 +#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) +#define DDR_CSD1_BASE_ADDR 0x40000000 + +#define CAAM_ARB_BASE_ADDR (0x00100000) +#define CAAM_ARB_END_ADDR (0x00107FFF) +#define CAAM_IPS_BASE_ADDR (0x30900000) +#define CONFIG_SYS_FSL_SEC_OFFSET (0) +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include + +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 + +struct iomuxc_gpr_base_regs { + u32 gpr[48]; +}; + +struct ocotp_regs { + u32 ctrl; + u32 ctrl_set; + u32 ctrl_clr; + u32 ctrl_tog; + u32 timing; + u32 rsvd0[3]; + u32 data; + u32 rsvd1[3]; + u32 read_ctrl; + u32 rsvd2[3]; + u32 read_fuse_data; + u32 rsvd3[3]; + u32 sw_sticky; + u32 rsvd4[3]; + u32 scs; + u32 scs_set; + u32 scs_clr; + u32 scs_tog; + u32 crc_addr; + u32 rsvd5[3]; + u32 crc_value; + u32 rsvd6[3]; + u32 version; + u32 rsvd7[0xdb]; + + /* fuse banks */ + struct fuse_bank { + u32 fuse_regs[0x10]; + } bank[0]; +}; + +struct fuse_bank0_regs { + u32 lock; + u32 rsvd0[3]; + u32 uid_low; + u32 rsvd1[3]; + u32 uid_high; + u32 rsvd2[7]; +}; + +struct fuse_bank1_regs { + u32 tester3; + u32 rsvd0[3]; + u32 tester4; + u32 rsvd1[3]; + u32 tester5; + u32 rsvd2[3]; + u32 cfg0; + u32 rsvd3[3]; +}; + +struct fuse_bank3_regs { + u32 mem_trim0; + u32 rsvd0[3]; + u32 mem_trim1; + u32 rsvd1[3]; + u32 mem_trim2; + u32 rsvd2[3]; + u32 ana0; + u32 rsvd3[3]; +}; + +struct fuse_bank9_regs { + u32 mac_addr0; + u32 rsvd0[3]; + u32 mac_addr1; + u32 rsvd1[11]; +}; + +struct anamix_pll { + u32 audio_pll1_gnrl_ctl; + u32 audio_pll1_fdiv_ctl0; + u32 audio_pll1_fdiv_ctl1; + u32 audio_pll1_sscg_ctl; + u32 audio_pll1_mnit_ctl; + u32 audio_pll2_gnrl_ctl; + u32 audio_pll2_fdiv_ctl0; + u32 audio_pll2_fdiv_ctl1; + u32 audio_pll2_sscg_ctl; + u32 audio_pll2_mnit_ctl; + u32 video_pll1_gnrl_ctl; + u32 video_pll1_fdiv_ctl0; + u32 video_pll1_fdiv_ctl1; + u32 video_pll1_sscg_ctl; + u32 video_pll1_mnit_ctl; + u32 reserved[5]; + u32 dram_pll_gnrl_ctl; + u32 dram_pll_fdiv_ctl0; + u32 dram_pll_fdiv_ctl1; + u32 dram_pll_sscg_ctl; + u32 dram_pll_mnit_ctl; + u32 gpu_pll_gnrl_ctl; + u32 gpu_pll_div_ctl; + u32 gpu_pll_locked_ctl1; + u32 gpu_pll_mnit_ctl; + u32 vpu_pll_gnrl_ctl; + u32 vpu_pll_div_ctl; + u32 vpu_pll_locked_ctl1; + u32 vpu_pll_mnit_ctl; + u32 arm_pll_gnrl_ctl; + u32 arm_pll_div_ctl; + u32 arm_pll_locked_ctl1; + u32 arm_pll_mnit_ctl; + u32 sys_pll1_gnrl_ctl; + u32 sys_pll1_div_ctl; + u32 sys_pll1_locked_ctl1; + u32 reserved2[24]; + u32 sys_pll1_mnit_ctl; + u32 sys_pll2_gnrl_ctl; + u32 sys_pll2_div_ctl; + u32 sys_pll2_locked_ctl1; + u32 sys_pll2_mnit_ctl; + u32 sys_pll3_gnrl_ctl; + u32 sys_pll3_div_ctl; + u32 sys_pll3_locked_ctl1; + u32 sys_pll3_mnit_ctl; + u32 anamix_misc_ctl; + u32 anamix_clk_mnit_ctl; + u32 reserved3[437]; + u32 digprog; +}; + + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 a53rcr; + u32 a53rcr1; + u32 m4rcr; + u32 reserved1[4]; + u32 usbophy1_rcr; + u32 usbophy2_rcr; + u32 mipiphy_rcr; + u32 pciephy_rcr; + u32 reserved2; + u32 disp_rcr; + u32 reserved3[2]; + u32 gpu_rcr; + u32 vpu_rcr; + u32 reserved4[4]; + u32 sbmr1; + u32 srsr; + u32 reserved5[2]; + u32 sisr; + u32 simr; + u32 sbmr2; + u32 gpr1; + u32 gpr2; + u32 gpr3; + u32 gpr4; + u32 gpr5; + u32 gpr6; + u32 gpr7; + u32 gpr8; + u32 gpr9; + u32 gpr10; + u32 reserved6[985]; + u32 ddr1_rcr; +}; + +struct gpc_reg { + u32 lpcr_bsc; + u32 lpcr_ad; + u32 lpcr_cpu1; + u32 lpcr_cpu2; + u32 lpcr_cpu3; + u32 slpcr; + u32 mst_cpu_mapping; + u32 mmdc_cpu_mapping; + u32 mlpcr; + u32 pgc_ack_sel; + u32 pgc_ack_sel_m4; + u32 gpc_misc; + u32 imr1_core0; + u32 imr2_core0; + u32 imr3_core0; + u32 imr4_core0; + u32 imr1_core1; + u32 imr2_core1; + u32 imr3_core1; + u32 imr4_core1; + u32 imr1_cpu1; + u32 imr2_cpu1; + u32 imr3_cpu1; + u32 imr4_cpu1; + u32 imr1_cpu3; + u32 imr2_cpu3; + u32 imr3_cpu3; + u32 imr4_cpu3; + u32 isr1_cpu0; + u32 isr2_cpu0; + u32 isr3_cpu0; + u32 isr4_cpu0; + u32 isr1_cpu1; + u32 isr2_cpu1; + u32 isr3_cpu1; + u32 isr4_cpu1; + u32 isr1_cpu2; + u32 isr2_cpu2; + u32 isr3_cpu2; + u32 isr4_cpu2; + u32 isr1_cpu3; + u32 isr2_cpu3; + u32 isr3_cpu3; + u32 isr4_cpu3; + u32 slt0_cfg; + u32 slt1_cfg; + u32 slt2_cfg; + u32 slt3_cfg; + u32 slt4_cfg; + u32 slt5_cfg; + u32 slt6_cfg; + u32 slt7_cfg; + u32 slt8_cfg; + u32 slt9_cfg; + u32 slt10_cfg; + u32 slt11_cfg; + u32 slt12_cfg; + u32 slt13_cfg; + u32 slt14_cfg; + u32 pgc_cpu_0_1_mapping; + u32 cpu_pgc_up_trg; + u32 mix_pgc_up_trg; + u32 pu_pgc_up_trg; + u32 cpu_pgc_dn_trg; + u32 mix_pgc_dn_trg; + u32 pu_pgc_dn_trg; + u32 lpcr_bsc2; + u32 pgc_cpu_2_3_mapping; + u32 lps_cpu0; + u32 lps_cpu1; + u32 lps_cpu2; + u32 lps_cpu3; + u32 gpc_gpr; + u32 gtor; + u32 debug_addr1; + u32 debug_addr2; + u32 cpu_pgc_up_status1; + u32 mix_pgc_up_status0; + u32 mix_pgc_up_status1; + u32 mix_pgc_up_status2; + u32 m4_mix_pgc_up_status0; + u32 m4_mix_pgc_up_status1; + u32 m4_mix_pgc_up_status2; + u32 pu_pgc_up_status0; + u32 pu_pgc_up_status1; + u32 pu_pgc_up_status2; + u32 m4_pu_pgc_up_status0; + u32 m4_pu_pgc_up_status1; + u32 m4_pu_pgc_up_status2; + u32 a53_lp_io_0; + u32 a53_lp_io_1; + u32 a53_lp_io_2; + u32 cpu_pgc_dn_status1; + u32 mix_pgc_dn_status0; + u32 mix_pgc_dn_status1; + u32 mix_pgc_dn_status2; + u32 m4_mix_pgc_dn_status0; + u32 m4_mix_pgc_dn_status1; + u32 m4_mix_pgc_dn_status2; + u32 pu_pgc_dn_status0; + u32 pu_pgc_dn_status1; + u32 pu_pgc_dn_status2; + u32 m4_pu_pgc_dn_status0; + u32 m4_pu_pgc_dn_status1; + u32 m4_pu_pgc_dn_status2; + u32 res[3]; + u32 mix_pdn_flg; + u32 pu_pdn_flg; + u32 m4_mix_pdn_flg; + u32 m4_pu_pdn_flg; + u32 imr1_core2; + u32 imr2_core2; + u32 imr3_core2; + u32 imr4_core2; + u32 imr1_core3; + u32 imr2_core3; + u32 imr3_core3; + u32 imr4_core3; + u32 pgc_ack_sel_pu; + u32 pgc_ack_sel_m4_pu; + u32 slt15_cfg; + u32 slt16_cfg; + u32 slt17_cfg; + u32 slt18_cfg; + u32 slt19_cfg; + u32 gpc_pu_pwrhsk; + u32 slt0_cfg_pu; + u32 slt1_cfg_pu; + u32 slt2_cfg_pu; + u32 slt3_cfg_pu; + u32 slt4_cfg_pu; + u32 slt5_cfg_pu; + u32 slt6_cfg_pu; + u32 slt7_cfg_pu; + u32 slt8_cfg_pu; + u32 slt9_cfg_pu; + u32 slt10_cfg_pu; + u32 slt11_cfg_pu; + u32 slt12_cfg_pu; + u32 slt13_cfg_pu; + u32 slt14_cfg_pu; + u32 slt15_cfg_pu; + u32 slt16_cfg_pu; + u32 slt17_cfg_pu; + u32 slt18_cfg_pu; + u32 slt19_cfg_pu; +}; + +struct pgc_reg { + u32 pgcr; + u32 pgpupscr; + u32 pgpdnscr; + u32 pgsr; + u32 pgauxsw; + u32 pgdr; +}; + +#define WDOG_WDT_MASK BIT(3) +#define WDOG_WDZST_MASK BIT(0) +struct wdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + u16 wicr; /* Interrupt Control */ + u16 wmcr; /* Miscellaneous Control */ +}; + +#define ROM_SW_INFO_ADDR_A0 0x000009e8 +#define ROM_SW_INFO_ADDR 0x000009e8 + +struct bootrom_sw_info { + u8 reserved_1; + u8 boot_dev_instance; + u8 boot_dev_type; + u8 reserved_2; + u32 core_freq; + u32 axi_freq; + u32 ddr_freq; + u32 tick_freq; + u32 reserved_3[3]; +}; + +/* ECSPI registers */ +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 cfg; + u32 intr; + u32 dma; + u32 stat; + u32 period; +}; + +/* + * CSPI register definitions + */ +#define MXC_ECSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_MODE_MASK (0xf << 4) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_PHA 0 /* SCLK phase control */ +#define MXC_CSPICON_POL 4 /* SCLK polarity */ +#define MXC_CSPICON_SSPOL 12 /* SS polarity */ +#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ + +#include +bool is_usb_boot(void); +#define is_boot_from_usb is_usb_boot +#define disconnect_from_pc(void) clrbits_le32(USB1_BASE_ADDR + 0xc704, (1 << 31)); + +#endif +#endif diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mq.h similarity index 90% rename from arch/arm/include/asm/arch-mx8m/imx-regs.h rename to arch/arm/include/asm/arch-imx8m/imx-regs-imx8mq.h index a10034cc35a..50116d638ed 100644 --- a/arch/arm/include/asm/arch-mx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mq.h @@ -1,5 +1,5 @@ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -129,6 +129,16 @@ #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) #define DDR_CSD1_BASE_ADDR 0x40000000 +#define CAAM_ARB_BASE_ADDR (0x00100000) +#define CAAM_ARB_END_ADDR (0x00107FFF) +#define CAAM_IPS_BASE_ADDR (0x30900000) +#define CONFIG_SYS_FSL_SEC_OFFSET (0) +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #if !defined(__ASSEMBLY__) #include #include @@ -148,8 +158,11 @@ #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 + struct iomuxc_gpr_base_regs { - u32 gpr[47]; + u32 gpr[48]; }; struct ocotp_regs { @@ -204,6 +217,17 @@ struct fuse_bank1_regs { u32 rsvd3[3]; }; +struct fuse_bank3_regs { + u32 mem_trim0; + u32 rsvd0[3]; + u32 mem_trim1; + u32 rsvd1[3]; + u32 ana0; + u32 rsvd2[3]; + u32 ana1; + u32 rsvd3[3]; +}; + struct anamix_pll { u32 audio_pll1_cfg0; u32 audio_pll1_cfg1; @@ -436,6 +460,15 @@ struct gpc_reg { u32 slt19_cfg_pu; }; +struct pgc_reg { + u32 pgcr; + u32 pgpupscr; + u32 pgpdnscr; + u32 pgsr; + u32 pgauxsw; + u32 pgdr; +}; + #define WDOG_WDT_MASK BIT(3) #define WDOG_WDZST_MASK BIT(0) struct wdog_regs { @@ -464,5 +497,11 @@ struct bootrom_sw_info { #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0 + +#include +bool is_usb_boot(void); +#define is_boot_from_usb is_usb_boot +#define disconnect_from_pc(void) clrbits_le32(USB1_BASE_ADDR + 0xc704, (1 << 31)); + #endif #endif diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h new file mode 100644 index 00000000000..08a06c32e81 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -0,0 +1,13 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef CONFIG_IMX8MQ +#include +#elif defined(CONFIG_IMX8MM) +#include +#else +#error "Error no imx-regs.h" +#endif diff --git a/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h b/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h new file mode 100644 index 00000000000..b319592c930 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h @@ -0,0 +1,85 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * Common file for ddr code + */ + +#ifndef __IMX8M_DDR_H__ +#define __IMX8M_DDR_H__ + +#include +#include +#include + +/* user data type */ +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_fsp_msg { + unsigned int drate; + enum fw_type fw_type; + struct dram_cfg_param *fsp_cfg; + unsigned int fsp_cfg_num; +}; + +struct dram_timing_info { + /* umctl2 config */ + struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; + /* ddrphy config */ + struct dram_cfg_param *ddrphy_cfg; + unsigned int ddrphy_cfg_num; + /* ddr fsp train info */ + struct dram_fsp_msg *fsp_msg; + unsigned int fsp_msg_num; + /* ddr phy trained CSR */ + struct dram_cfg_param *ddrphy_trained_csr; + unsigned int ddrphy_trained_csr_num; + /* ddr phy PIE */ + struct dram_cfg_param *ddrphy_pie; + unsigned int ddrphy_pie_num; + /* initialized drate table */ + unsigned int fsp_table[4]; +}; + +extern struct dram_timing_info dram_timing; + +void ddr_load_train_firmware(enum fw_type type); +void ddr_init(struct dram_timing_info *timing_info); +void ddr_cfg_phy(struct dram_timing_info *timing_info); +void load_lpddr4_phy_pie(void); +void ddrphy_trained_csr_save(struct dram_cfg_param *, unsigned int); +void dram_config_save(struct dram_timing_info *, unsigned long); + +/* utils function for ddr phy training */ +void wait_ddrphy_training_complete(void); +void ddrphy_init_set_dfi_clk(unsigned int drate); +void ddrphy_init_read_msg_block(enum fw_type type); + +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline u32 reg32_read(unsigned long addr) +{ + return readl(addr); +} + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} + +#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(addr), data) +#define dwc_ddrphy_apb_rd(addr) reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(addr)) + +#endif /* __IMX8M_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h new file mode 100644 index 00000000000..829cdbf3d01 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h @@ -0,0 +1,694 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or later, + * available at https://www.gnu.org/licenses/gpl-2.0.html. + */ + +#ifndef __ASM_ARCH_IMX8MM_PINS_H__ +#define __ASM_ARCH_IMX8MM_PINS_H__ + +#include + +enum { + IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), + IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), + IMX8MM_PAD_GPIO1_IO07_USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), + IMX8MM_PAD_GPIO1_IO11_CCM_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_CCM_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_CCM_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0), + IMX8MM_PAD_GPIO1_IO14_PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0), + IMX8MM_PAD_GPIO1_IO15_PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_MDC_ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_MDC_GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_MDIO_ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), + IMX8MM_PAD_ENET_MDIO_GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD3_GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD1_GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD0_GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TXC_ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TXC_GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RXC_ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RXC_GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD0_GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD1_GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD2_GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD3_GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_CLK_USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_CLK_GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_CMD_USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_CMD_GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA0_GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA1_GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA2_GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA3_GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA4_GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA5_GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA6_GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA7_GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_STROBE_GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CLK_USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CLK_GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CMD_USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CMD_GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA0_GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA1_GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA1_CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA2_GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA2_CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_WP_USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_WP_GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_ALE_RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_ALE_GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CLE_RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0), + IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA03_USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0), + IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DQS_RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DQS_QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DQS_GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_READY_B_GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WE_B_GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WP_B_GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), + IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), + IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXC_PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXC_GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), + IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0), + IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), + IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0), + IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), + IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), + IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), + IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0), + IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), + IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), + IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0), + IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), + IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), + IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), + IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), + IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), + IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXC_GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), + IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1 = IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0), + IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), + IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0), + IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), + IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0), + IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0), + IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0), + IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), + IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), + IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), + IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), + IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), + IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), + IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), + IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), + IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXC_GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), + IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), + IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), + IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), + IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), + IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), + IMX8MM_PAD_SAI1_TXD7_PDM_CLK = IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), + IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), + IMX8MM_PAD_SAI1_MCLK_PDM_CLK = IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), + IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_UART1_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_UART1_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0), + IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), + IMX8MM_PAD_SAI2_RXC_UART1_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0), + IMX8MM_PAD_SAI2_RXC_UART1_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0), + IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0), + IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXC_GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), + IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), + IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), + IMX8MM_PAD_SAI3_RXC_UART2_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_UART2_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0), + IMX8MM_PAD_SAI3_RXC_GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), + IMX8MM_PAD_SAI3_RXD_UART2_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0), + IMX8MM_PAD_SAI3_RXD_UART2_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), + IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_UART2_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0), + IMX8MM_PAD_SAI3_TXFS_UART2_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), + IMX8MM_PAD_SAI3_TXC_UART2_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_UART2_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0), + IMX8MM_PAD_SAI3_TXC_GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), + IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_MCLK_PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), + IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_TX_PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_RX_SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_RX_PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_RX_GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_UART3_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MOSI_UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MOSI_UART3_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), + IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), + IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_UART4_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MOSI_UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MOSI_UART4_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), + IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C1_SCL_I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SCL_ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C1_SDA_I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SDA_ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), + IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0), + IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SDA_USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0), + IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C3_SCL_I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C3_SDA_I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C4_SCL_I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SCL_PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), + IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C4_SDA_I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SDA_PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART1_RXD_UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), + IMX8MM_PAD_UART1_RXD_UART1_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART1_RXD_GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART1_TXD_UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART1_TXD_UART1_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0), + IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART1_TXD_GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART2_RXD_UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), + IMX8MM_PAD_UART2_RXD_UART2_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART2_RXD_ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART2_RXD_GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART2_TXD_UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART2_TXD_UART2_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0), + IMX8MM_PAD_UART2_TXD_ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART2_TXD_GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART3_RXD_UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), + IMX8MM_PAD_UART3_RXD_UART3_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_UART1_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), + IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART3_TXD_UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_UART3_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0), + IMX8MM_PAD_UART3_TXD_UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), + IMX8MM_PAD_UART3_TXD_UART1_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART4_RXD_UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), + IMX8MM_PAD_UART4_RXD_UART4_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART4_RXD_UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART4_RXD_UART2_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), + IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), + IMX8MM_PAD_UART4_RXD_GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART4_TXD_UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART4_TXD_UART4_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0), + IMX8MM_PAD_UART4_TXD_UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), + IMX8MM_PAD_UART4_TXD_UART2_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART4_TXD_GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), +}; +#endif diff --git a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h similarity index 99% rename from arch/arm/include/asm/arch-mx8m/mx8mq_pins.h rename to arch/arm/include/asm/arch-imx8m/imx8mq_pins.h index 062bea7299f..f66c2bb6dc2 100644 --- a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h +++ b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __ASM_ARCH_MX8MQ_PINS_H__ -#define __ASM_ARCH_MX8MQ_PINS_H__ +#ifndef __ASM_ARCH_IMX8MQ_PINS_H__ +#define __ASM_ARCH_IMX8MQ_PINS_H__ #include diff --git a/arch/arm/include/asm/arch-imx8m/lpddr4_define.h b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h new file mode 100644 index 00000000000..b8124c17d96 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h @@ -0,0 +1,99 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LPDDR4_DEFINE_H_ +#define __LPDDR4_DEFINE_H_ + +#define LPDDR4_DVFS_DBI +#define DDR_ONE_RANK +/* #define LPDDR4_DBI_ON */ +#define DFI_BUG_WR +#define M845S_4GBx2 +#define PRETRAIN + +/* DRAM MR setting */ +#ifdef LPDDR4_DBI_ON +#define LPDDR4_MR3 0xf1 +#define LPDDR4_PHY_DMIPinPresent 0x1 +#else +#define LPDDR4_MR3 0x31 +#define LPDDR4_PHY_DMIPinPresent 0x0 +#endif + +#ifdef DDR_ONE_RANK +#define LPDDR4_CS 0x1 +#else +#define LPDDR4_CS 0x3 +#endif + +/* PHY training feature */ +#define LPDDR4_HDT_CTL_2D 0xC8 +#define LPDDR4_HDT_CTL_3200_1D 0xC8 +#define LPDDR4_HDT_CTL_400_1D 0xC8 +#define LPDDR4_HDT_CTL_100_1D 0xC8 + +#define LPDDR4_HDT_CTL_2D 0xC8 +#define LPDDR4_HDT_CTL_3200_1D 0xC8 +#define LPDDR4_HDT_CTL_400_1D 0xC8 +#define LPDDR4_HDT_CTL_100_1D 0xC8 + +/* 400/100 training seq */ +#define LPDDR4_TRAIN_SEQ_P2 0x121f +#define LPDDR4_TRAIN_SEQ_P1 0x121f +#define LPDDR4_TRAIN_SEQ_P0 0x121f + +/* 2D share & weight */ +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 +#define LPDDR4_CATRAIN_3200_1d 0 +#define LPDDR4_CATRAIN_400 0 +#define LPDDR4_CATRAIN_100 0 +#define LPDDR4_CATRAIN_3200_2d 0 + +/* MRS parameter */ +/* for LPDDR4 Rtt */ +#define LPDDR4_RTT40 6 +#define LPDDR4_RTT48 5 +#define LPDDR4_RTT60 4 +#define LPDDR4_RTT80 3 +#define LPDDR4_RTT120 2 +#define LPDDR4_RTT240 1 +#define LPDDR4_RTT_DIS 0 + +/* for LPDDR4 Ron */ +#define LPDDR4_RON34 7 +#define LPDDR4_RON40 6 +#define LPDDR4_RON48 5 +#define LPDDR4_RON60 4 +#define LPDDR4_RON80 3 + +#define LPDDR4_PHY_ADDR_RON60 0x1 +#define LPDDR4_PHY_ADDR_RON40 0x3 +#define LPDDR4_PHY_ADDR_RON30 0x7 +#define LPDDR4_PHY_ADDR_RON24 0xf +#define LPDDR4_PHY_ADDR_RON20 0x1f + +/* for read channel */ +#define LPDDR4_RON LPDDR4_RON40 +#define LPDDR4_PHY_RTT 30 +#define LPDDR4_PHY_VREF_VALUE 17 + +/* for write channel */ +#define LPDDR4_PHY_RON 30 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 +#define LPDDR4_RTT_DQ LPDDR4_RTT40 +#define LPDDR4_RTT_CA LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 +#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd)) +#define LPDDR4_MR22_RANK0 ((0 << 5) | (0 << 4) | (0 << 3) | (LPDDR4_RTT40)) +#define LPDDR4_MR22_RANK1 ((1 << 5) | (0 << 4) | (1 << 3) | (LPDDR4_RTT40)) + +#define LPDDR4_MR3_PU_CAL 1 + +#endif /* __LPDDR4_DEFINE_H__ */ diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h similarity index 73% rename from arch/arm/include/asm/arch-mx8m/sys_proto.h rename to arch/arm/include/asm/arch-imx8m/sys_proto.h index 8bf9ac6697f..e01a685f4d6 100644 --- a/arch/arm/include/asm/arch-mx8m/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 NXP + * Copyright (C) 2017-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,7 +12,11 @@ void set_wdog_reset(struct wdog_regs *wdog); void enable_tzc380(void); void restore_boot_params(void); +int imx8m_usb_power(int usb_id, bool on); extern unsigned long rom_pointer[]; enum boot_device get_boot_device(void); bool is_usb_boot(void); +#ifdef CONFIG_IMX8MQ +bool check_dcss_fused(void); +#endif #endif diff --git a/arch/arm/include/asm/arch-imx8m/video_common.h b/arch/arm/include/asm/arch-imx8m/video_common.h new file mode 100644 index 00000000000..cdeec6999ce --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/video_common.h @@ -0,0 +1,40 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_VIDEO_COMMON_H__ +#define __ASM_ARCH_VIDEO_COMMON_H__ +#include +#include + +struct video_mode_settings { + uint32_t pixelclock; /* horizontal resolution */ + uint16_t xres; /* horizontal resolution */ + uint16_t yres; /* vertical resolution */ + uint16_t hfp; /* horizontal front porch */ + uint16_t hbp; /* horizontal back porch */ + uint16_t vfp; /* vertical front porch */ + uint16_t vbp; /* vertical back porch */ + uint16_t hsync; /* horizontal sync pulse width */ + uint16_t vsync; /* vertical sync pulse width */ + bool hpol; /* horizontal pulse polarity */ + bool vpol; /* vertical pulse polarity */ +}; + +#define PS2KHZ(ps) (1000000000UL / (ps)) +struct video_mode_settings *imx8m_get_gmode(void); +GraphicDevice *imx8m_get_gd(void); +void imx8m_show_gmode(void); +void imx8m_create_color_bar( + void *start_address, + struct video_mode_settings *vms); +int imx8m_fb_init( + struct fb_videomode const *mode, + uint8_t disp, + uint32_t pixfmt); +void imx8m_fb_disable(void); + +#endif /* __ASM_ARCH_VIDEO_COMMON_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 26afefb0818..8772677c3c4 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -75,10 +75,13 @@ void enable_ipu_clock(void); int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void enable_enet_clk(unsigned char enable); int enable_lcdif_clock(u32 base_addr, bool enable); +int enable_lvds_bridge(u32 lcd_base_addr); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); +void enable_epdc_clock(void); void mxs_set_lcdclk(u32 base_addr, u32 freq); void select_ldb_di_clock_source(enum ldb_di_clock clk); void enable_eim_clk(unsigned char enable); +void mxs_set_vadcclk(void); int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 74ed91230f5..0531cac8f44 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -265,11 +265,20 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 -/* LCDIF on i.MX6SX/UL */ +/* LCDIF on i.MX6SX/UL/SLL */ #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23) #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23 -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 +#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_PODF_MASK (0x7 << 23) +#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_PODF_OFFSET 23 + +/* For i.MX6SL */ +#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 29) +#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 29 +#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_PODF_MASK (0x7 << 26) +#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_PODF_OFFSET 26 +#define MXC_CCM_CBCMR_EPDC_PIX_PODF_MASK (0x7 << 23) +#define MXC_CCM_CBCMR_EPDC_PIX_PODF_OFFSET 23 + #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) @@ -291,6 +300,14 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 + +/* For i.MX6SL */ +#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_SEL_OFFSET 8 +#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_CLK_SEL_OFFSET 4 + + /* Exists on i.MX6QP */ #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) @@ -432,15 +449,15 @@ struct mxc_ccm_reg { #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) @@ -500,7 +517,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 -/* i.MX6ULL */ +/* i.MX6ULL/SLL */ #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12) @@ -517,13 +534,20 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) -/* LCDIF1 on i.MX6SX/UL */ +/* LCDIF1 on i.MX6SX/UL/SLL */ #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15) #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12) #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9) #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9 + +/* EPDC on i.MX6SL */ +#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_OFFSET 15 +#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_DIV_MASK (0x7 << 12) +#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_DIV_OFFSET 12 + /* LCDIF2 on i.MX6SX */ #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6) #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6 @@ -568,6 +592,16 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET 16 #define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK (0x3 << 14) #define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET 14 +#define MXC_CCM_CSCDR3_CSI_CORE_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR3_CSI_CORE_PODF_OFFSET 11 +#define MXC_CCM_CSCDR3_CSI_CORE_CLK_SEL_MASK (0x3 << 9) +#define MXC_CCM_CSCDR3_CSI_CORE_CLK_SEL_OFFSET 9 + +/* For i.MX6SLL */ +#define MXC_CCM_CSCDR3_PXP_PODF_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_PXP_PODF_OFFSET 16 +#define MXC_CCM_CSCDR3_PXP_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCDR3_PXP_CLK_SEL_OFFSET 14 /* Define the bits in register CDHIPR */ #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) @@ -770,7 +804,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) -/* i.MX6SX/UL LCD and PXP */ +/* i.MX6SX/UL/SLL LCD and PXP */ #define MXC_CCM_CCGR2_LCD_OFFSET 28 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) #define MXC_CCM_CCGR2_PXP_OFFSET 30 @@ -799,10 +833,18 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) /* i.MX6SL */ -#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6 -#define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET) -#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8 -#define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET) +#define MXC_CCM_CCGR3_CSI_CORE_OFFSET 0 +#define MXC_CCM_CCGR3_CSI_CORE_MASK (3 << MXC_CCM_CCGR3_CSI_CORE_OFFSET) +#define MXC_CCM_CCGR3_PXP_AXI_OFFSET 2 +#define MXC_CCM_CCGR3_PXP_AXI_MASK (3 << MXC_CCM_CCGR3_PXP_AXI_OFFSET) +#define MXC_CCM_CCGR3_EPDC_AXI_OFFSET 4 +#define MXC_CCM_CCGR3_EPDC_AXI_MASK (3 << MXC_CCM_CCGR3_EPDC_AXI_OFFSET) +#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6 +#define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET) +#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8 +#define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET) +#define MXC_CCM_CCGR3_EPDC_PIX_OFFSET 10 +#define MXC_CCM_CCGR3_EPDC_PIX_MASK (3 << MXC_CCM_CCGR3_EPDC_PIX_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 8513406a8e2..e5476602dcf 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -123,7 +123,7 @@ #define MMDC1_ARB_END_ADDR 0xFFFFFFFF #endif -#ifndef CONFIG_MX6SX +#if (!(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL))) #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR #define IPU_SOC_OFFSET 0x00200000 #endif @@ -159,12 +159,21 @@ #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define SAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) +#define SAI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) +#define SAI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) +#else #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) +#endif #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) -#ifndef CONFIG_MX6SX +#if defined(CONFIG_MX6UL) +#define TOUCH_CTRL_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) +#define BEE_BASE_ADDR (ATZ1_BASE_ADDR + 0x44000) +#elif !defined(CONFIG_MX6SX) #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) #endif @@ -186,8 +195,13 @@ #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) #define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#else #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#endif #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) @@ -212,6 +226,7 @@ #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) #elif defined(CONFIG_MX6SX) #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) @@ -219,10 +234,19 @@ #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) + +#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define GPT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define PWM5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) +#define PWM6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#define PWM7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define PWM8_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) #else #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) #endif #define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) @@ -232,8 +256,14 @@ #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) + +#if defined(CONFIG_MX6UL) +#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) +#define ARM_BASE_ADDR (ATZ2_BASE_ADDR) +#else #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) +#endif #define CONFIG_SYS_FSL_SEC_OFFSET 0 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ @@ -249,6 +279,8 @@ #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) #ifdef CONFIG_MX6SL #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) +#elif defined(CONFIG_MX6UL) +#define SIM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) #else #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) #endif @@ -257,6 +289,9 @@ #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) + +#define MX6UL_ADC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) +#define MX6UL_ADC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) @@ -276,12 +311,16 @@ #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) -#ifdef CONFIG_MX6SLL +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define CSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) +#define PXP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) +#elif defined(CONFIG_MX6SLL) #define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) -#endif +#else #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#endif #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #ifdef CONFIG_MX6SX @@ -291,9 +330,10 @@ #endif #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) +#define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) +#define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #elif defined(CONFIG_MX6SX) #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) @@ -311,9 +351,20 @@ #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) +/* i.MX6SLL */ +#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +/* i.MX6SX/UL */ #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) +/* i.MX6UL */ +#define MX6UL_UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) + +#define OTG_BASE_ADDR USB_BASE_ADDR + +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR +#endif /* i.MX6SLL */ #define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) @@ -328,19 +379,18 @@ #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) -#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) -#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) +#define MX6SX_ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) +#define MX6SX_ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) -#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) -#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#elif defined(CONFIG_MX6ULL) #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) #define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) #define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) @@ -356,6 +406,7 @@ #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) +#define MX6SX_UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) #if !(defined(CONFIG_MX6SX) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ @@ -365,6 +416,7 @@ #define IRAM_SIZE 0x00020000 #endif #define FEC_QUIRK_ENET_MAC +#define SNVS_LPGPR 0x68 #include #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) @@ -381,6 +433,12 @@ MX6UL_LCDIF1_BASE_ADDR : \ ((is_mx6ull()) ? \ MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) +#define UART6_BASE_ADDR ((is_mx6ul() || is_mx6ull()) ? \ + MX6UL_UART6_BASE_ADDR : MX6SX_UART6_BASE_ADDR) + +#define MXS_LCDIF_BASE LCDIF1_BASE_ADDR + +#define MXS_LCDIF_BASE LCDIF1_BASE_ADDR extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); @@ -581,7 +639,12 @@ struct iomuxc { #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) u8 reserved[0x4000]; #endif + +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) + u32 gpr[15]; +#else u32 gpr[14]; +#endif }; struct gpc { @@ -664,6 +727,12 @@ struct gpc { #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0< +bool is_usb_boot(void); +#define is_boot_from_usb is_usb_boot +#define is_usbphy_power_on(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) +#define disconnect_from_pc(void) writel(0x0, OTG_BASE_ADDR + 0x140) + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/module_fuse.h b/arch/arm/include/asm/arch-mx6/module_fuse.h new file mode 100644 index 00000000000..4745091cb65 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/module_fuse.h @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MODULE_FUSE_H__ +#define __MODULE_FUSE_H__ + +enum fuse_module_type{ + MX6_MODULE_TSC, + MX6_MODULE_ADC1, + MX6_MODULE_ADC2, + MX6_MODULE_SIM1, + MX6_MODULE_SIM2, + MX6_MODULE_FLEXCAN1, + MX6_MODULE_FLEXCAN2, + MX6_MODULE_SPDIF, + MX6_MODULE_EIM, + MX6_MODULE_SD1, + MX6_MODULE_SD2, + MX6_MODULE_SD3, + MX6_MODULE_SD4, + MX6_MODULE_QSPI1, + MX6_MODULE_QSPI2, + MX6_MODULE_GPMI, + MX6_MODULE_APBHDMA, + MX6_MODULE_LCDIF, + MX6_MODULE_PXP, + MX6_MODULE_CSI, + MX6_MODULE_ENET1, + MX6_MODULE_ENET2, + MX6_MODULE_CAAM, + MX6_MODULE_USB_OTG1, + MX6_MODULE_USB_OTG2, + MX6_MODULE_SAI2, + MX6_MODULE_SAI3, + MX6_MODULE_BEE, + MX6_MODULE_UART1, + MX6_MODULE_UART2, + MX6_MODULE_UART3, + MX6_MODULE_UART4, + MX6_MODULE_UART5, + MX6_MODULE_UART6, + MX6_MODULE_UART7, + MX6_MODULE_UART8, + MX6_MODULE_PWM5, + MX6_MODULE_PWM6, + MX6_MODULE_PWM7, + MX6_MODULE_PWM8, + MX6_MODULE_ECSPI1, + MX6_MODULE_ECSPI2, + MX6_MODULE_ECSPI3, + MX6_MODULE_ECSPI4, + MX6_MODULE_ECSPI5, + MX6_MODULE_I2C1, + MX6_MODULE_I2C2, + MX6_MODULE_I2C3, + MX6_MODULE_I2C4, + MX6_MODULE_GPT1, + MX6_MODULE_GPT2, + MX6_MODULE_EPIT1, + MX6_MODULE_EPIT2, + MX6_MODULE_EPDC, + MX6_MODULE_ESAI, + MX6_MODULE_DCP, + MX6_MODULE_DCP_CRYPTO, +}; + +#if !defined(CONFIG_MODULE_FUSE) +static inline u32 check_module_fused(enum fuse_module_type module) +{ + return 0; +}; + +static inline u32 mx6_esdhc_fused(u32 base_addr) +{ + return 0; +}; + +static inline u32 mx6_ecspi_fused(u32 base_addr) +{ + return 0; +}; +static inline u32 mx6_uart_fused(u32 base_addr) +{ + return 0; +}; +static inline u32 mx6_usb_fused(u32 base_addr) +{ + return 0; +}; +static inline u32 mx6_qspi_fused(u32 base_addr) +{ + return 0; +}; +static inline u32 mx6_i2c_fused(u32 base_addr) +{ + return 0; +}; +static inline u32 mx6_enet_fused(u32 base_addr) +{ + return 0; +}; + +#else +u32 check_module_fused(enum fuse_module_type module); +u32 mx6_esdhc_fused(u32 base_addr); +u32 mx6_ecspi_fused(u32 base_addr); +u32 mx6_uart_fused(u32 base_addr); +u32 mx6_usb_fused(u32 base_addr); +u32 mx6_qspi_fused(u32 base_addr); +u32 mx6_i2c_fused(u32 base_addr); +u32 mx6_enet_fused(u32 base_addr); +#endif + +#ifdef DEBUG +void print_fuse_status(); +void simulate_fuse(); +#endif + +#endif /* __MODULE_FUSE_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6_bee.h b/arch/arm/include/asm/arch-mx6/mx6_bee.h new file mode 100644 index 00000000000..eb51dfef75d --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6_bee.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#define GPR0 0x0 +#define GPR1 0x4 +#define GPR2 0x8 +#define GPR3 0xC +#define GPR4 0x10 +#define GPR5 0x14 +#define GPR6 0x18 +#define GPR7 0x1C +#define GPR8 0x20 +#define GPR9 0x24 +#define GPR10 0x28 +#define GPR11 0x2C + +#define GPR0_CTRL_CLK_EN_LOCK (1 << 31) +#define GPR0_CTRL_CLK_EN (1 << 15) +#define GPR0_CTRL_SFTRST_N_LOCK (1 << 30) +#define GPR0_CTRL_SFTRST (0 << 14) +#define GPR0_CTRL_SFTRST_N (1 << 14) +#define GPR0_CTRL_AES_MODE_LOCK (1 << 29) +#define GPR0_CTRL_AES_MODE_ECB (0 << 13) +#define GPR0_CTRL_AES_MODE_CTR (1 << 13) +#define GPR0_SEC_LEVEL_LOCK (3 << 24) +#define GPR0_SEC_LEVEL (3 << 8) +#define GPR0_AES_KEY_SEL_LOCK (1 << 20) +#define GPR0_AES_KEY_SEL_SNVS (0 << 4) +#define GPR0_AES_KEY_SEL_SOFT (1 << 4) +#define GPR0_BEE_ENABLE_LOCK (1 << 16) +#define GPR0_BEE_ENABLE (1 << 0) + +/* + * SECURITY LEVEL + * Non-Secure User | Non-Secure Spvr | Secure User | Secure Spvr + * Level + * (0)00 RD + WR RD + WR RD + WR RD + WR + * (1)01 None RD + WR RD + WR RD + WR + * (2)10 None None RD + WR RD + WR + * (3)11 None None None RD + WR + */ +#define GPR0_SEC_LEVEL_0 (0 << 8) +#define GPR0_SEC_LEVEL_1 (1 << 8) +#define GPR0_SEC_LEVEL_2 (2 << 8) +#define GPR0_SEC_LEVEL_3 (3 << 8) diff --git a/arch/arm/include/asm/arch-mx6/mx6_plugin.S b/arch/arm/include/asm/arch-mx6/mx6_plugin.S index b7d1b20315f..02d855fbc30 100644 --- a/arch/arm/include/asm/arch-mx6/mx6_plugin.S +++ b/arch/arm/include/asm/arch-mx6/mx6_plugin.S @@ -64,7 +64,7 @@ plugin_start: before_calling_rom___pu_irom_hwcnfg_setup: ldr r3, =ROM_VERSION_OFFSET ldr r4, [r3] -#if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL) +#if defined(CONFIG_MX6S) || defined(CONFIG_MX6DL) ldr r3, =ROM_VERSION_TO12 cmp r4, r3 ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 158e47cd3bc..275469f3d93 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -60,14 +60,70 @@ enum { MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), + MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x0474, 0x016C, 0, 0x0734, 0, 0), + MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x0478, 0x0170, 0, 0x0738, 0, 0), + MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x047C, 0x0174, 0, 0x073C, 0, 0), + MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x0480, 0x0178, 0, 0x0740, 0, 0), + MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, 0), + MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, 0), + MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, 0), + MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, 0), MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__GPIO_4_4 = IOMUX_PAD(0x048C, 0x0184, 5, 0x0000, 0, 0), MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0), MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0), MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0), MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), + MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 = IOMUX_PAD(0x03DC, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 = IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 = IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__GPIO_2_3 = IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 = IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 = IOMUX_PAD(0x03D4, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D0__EPDC_SDDO_0 = IOMUX_PAD(0x0380, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D1__EPDC_SDDO_1 = IOMUX_PAD(0x0384, 0x0094, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D2__EPDC_SDDO_2 = IOMUX_PAD(0x03A0, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D3__EPDC_SDDO_3 = IOMUX_PAD(0x03A4, 0x00B4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D4__EPDC_SDDO_4 = IOMUX_PAD(0x03A8, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D5__EPDC_SDDO_5 = IOMUX_PAD(0x03AC, 0x00BC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D6__EPDC_SDDO_6 = IOMUX_PAD(0x03B0, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D7__EPDC_SDDO_7 = IOMUX_PAD(0x03B4, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x03C0, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x03CC, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x03C4, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x03C8, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x0400, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x0408, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x0404, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x040C, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__EPDC_BDR_0 = IOMUX_PAD(0x0378, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0 = IOMUX_PAD(0x03F0, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1 = IOMUX_PAD(0x03F4, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2 = IOMUX_PAD(0x03F8, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D0__GPIO_1_7 = IOMUX_PAD(0x0380, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D1__GPIO_1_8 = IOMUX_PAD(0x0384, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D2__GPIO_1_9 = IOMUX_PAD(0x03A0, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D3__GPIO_1_10 = IOMUX_PAD(0x03A4, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D4__GPIO_1_11 = IOMUX_PAD(0x03A8, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D5__GPIO_1_12 = IOMUX_PAD(0x03AC, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D6__GPIO_1_13 = IOMUX_PAD(0x03B0, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D7__GPIO_1_14 = IOMUX_PAD(0x03B4, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__GPIO_1_31 = IOMUX_PAD(0x03C0, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__GPIO_2_2 = IOMUX_PAD(0x03CC, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__GPIO_2_0 = IOMUX_PAD(0x03C4, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__GPIO_2_1 = IOMUX_PAD(0x03C8, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCLK__GPIO_1_23 = IOMUX_PAD(0x0400, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__GPIO_1_25 = IOMUX_PAD(0x0408, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDLE__GPIO_1_24 = IOMUX_PAD(0x0404, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__GPIO_1_26 = IOMUX_PAD(0x040C, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__GPIO_2_5 = IOMUX_PAD(0x0378, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__GPIO_1_27 = IOMUX_PAD(0x03F0, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__GPIO_1_28 = IOMUX_PAD(0x03F4, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__GPIO_1_29 = IOMUX_PAD(0x03F8, 0x0108, 5, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6ul_pins.h b/arch/arm/include/asm/arch-mx6/mx6ul_pins.h index 900e062de41..c80d27bc231 100644 --- a/arch/arm/include/asm/arch-mx6/mx6ul_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6ul_pins.h @@ -67,6 +67,7 @@ enum { MX6_PAD_JTAG_TCK__SAI2_RX_DATA = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0), MX6_PAD_JTAG_TCK__PWM7_OUT = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0), MX6_PAD_JTAG_TCK__GPIO1_IO14 = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__REF_CLK_32K = IOMUX_PAD(0x02E0, 0x0054, 6, 0x0000, 0, 0), MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0), MX6_PAD_JTAG_TRST_B__SJC_TRSTB = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0), @@ -74,6 +75,7 @@ enum { MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0), MX6_PAD_JTAG_TRST_B__PWM8_OUT = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0), MX6_PAD_JTAG_TRST_B__GPIO1_IO15 = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__REF_CLK_24M = IOMUX_PAD(0x02E4, 0x0058, 6, 0x0000, 0, 0), MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0), MX6_PAD_GPIO1_IO00__I2C2_SCL = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0), @@ -110,6 +112,7 @@ enum { MX6_PAD_GPIO1_IO03__I2C1_SDA = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0), MX6_PAD_GPIO1_IO03__GPT1_COMPARE3 = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0), MX6_PAD_GPIO1_IO03__USB_OTG2_OC = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0), + MX6_PAD_GPIO1_IO03__REF_CLK_32K = IOMUX_PAD(0x02F4, 0x0068, 3, 0x0000, 0, 0), MX6_PAD_GPIO1_IO03__USDHC1_CD_B = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0), MX6_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0), MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0), @@ -120,6 +123,7 @@ enum { MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1 = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0), MX6_PAD_GPIO1_IO04__PWM3_OUT = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0), MX6_PAD_GPIO1_IO04__USB_OTG1_PWR = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__REF_CLK_24M = IOMUX_PAD(0x02F8, 0x006C, 3, 0x0000, 0, 0), MX6_PAD_GPIO1_IO04__USDHC1_RESET_B = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0), MX6_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0), MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0), @@ -366,6 +370,7 @@ enum { MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0), MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__REF_CLK_32K = IOMUX_PAD(0x0358, 0x00CC, 2, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__GPIO2_IO02 = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0), @@ -375,6 +380,7 @@ enum { MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0), + MX6_PAD_ENET1_TX_DATA0__REF_CLK_24M = IOMUX_PAD(0x035C, 0x00D0, 2, 0x0000, 0, 0), MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), @@ -459,6 +465,7 @@ enum { MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__REF_CLK_24M = IOMUX_PAD(0x037C, 0x00F0, 8, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0), @@ -546,6 +553,7 @@ enum { MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 = IOMUX_PAD(0x03A4, 0x0118, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__I2C3_SDA = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0), MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0), @@ -554,6 +562,7 @@ enum { MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 = IOMUX_PAD(0x03A8, 0x011C, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__I2C3_SCL = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0), MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0), @@ -562,6 +571,7 @@ enum { MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 = IOMUX_PAD(0x03AC, 0x0120, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__I2C4_SDA = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0), MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0), @@ -570,6 +580,7 @@ enum { MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 = IOMUX_PAD(0x03B0, 0x0124, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__I2C4_SCL = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0), MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0), @@ -579,6 +590,7 @@ enum { MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__UART8_DTE_RTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0), + MX6_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 = IOMUX_PAD(0x03B4, 0x0128, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__SPDIF_SR_CLK = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0), @@ -588,6 +600,7 @@ enum { MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0), MX6_PAD_LCD_DATA05__UART8_DTE_CTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 = IOMUX_PAD(0x03B8, 0x012C, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__SPDIF_OUT = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0), @@ -597,6 +610,7 @@ enum { MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__UART7_DTE_RTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0), + MX6_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 = IOMUX_PAD(0x03BC, 0x0130, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__SPDIF_LOCK = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0), @@ -606,6 +620,7 @@ enum { MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0), MX6_PAD_LCD_DATA07__UART7_DTE_CTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 = IOMUX_PAD(0x03C0, 0x0134, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0), MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0), @@ -614,6 +629,7 @@ enum { MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0), + MX6_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 = IOMUX_PAD(0x03C4, 0x0138, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA08__CSI_DATA16 = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0), MX6_PAD_LCD_DATA08__EIM_DATA00 = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0), @@ -622,6 +638,7 @@ enum { MX6_PAD_LCD_DATA09__LCDIF_DATA09 = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA09__SAI3_MCLK = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0), + MX6_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 = IOMUX_PAD(0x03C8, 0x013C, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA09__CSI_DATA17 = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0), MX6_PAD_LCD_DATA09__EIM_DATA01 = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0), @@ -630,6 +647,7 @@ enum { MX6_PAD_LCD_DATA10__LCDIF_DATA10 = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA10__SAI3_RX_SYNC = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 = IOMUX_PAD(0x03CC, 0x0140, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA10__CSI_DATA18 = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0), MX6_PAD_LCD_DATA10__EIM_DATA02 = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0), @@ -638,6 +656,7 @@ enum { MX6_PAD_LCD_DATA11__LCDIF_DATA11 = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA11__SAI3_RX_BCLK = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 = IOMUX_PAD(0x03D0, 0x0144, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA11__CSI_DATA19 = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0), MX6_PAD_LCD_DATA11__EIM_DATA03 = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0), @@ -646,6 +665,7 @@ enum { MX6_PAD_LCD_DATA12__LCDIF_DATA12 = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA12__SAI3_TX_SYNC = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0), + MX6_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 = IOMUX_PAD(0x03D4, 0x0148, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA12__CSI_DATA20 = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0), MX6_PAD_LCD_DATA12__EIM_DATA04 = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0), @@ -654,6 +674,7 @@ enum { MX6_PAD_LCD_DATA13__LCDIF_DATA13 = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA13__SAI3_TX_BCLK = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0), + MX6_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 = IOMUX_PAD(0x03D8, 0x014C, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA13__CSI_DATA21 = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0), MX6_PAD_LCD_DATA13__EIM_DATA05 = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0), @@ -662,6 +683,7 @@ enum { MX6_PAD_LCD_DATA14__LCDIF_DATA14 = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA14__SAI3_RX_DATA = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0), + MX6_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 = IOMUX_PAD(0x03DC, 0x0150, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA14__CSI_DATA22 = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0), MX6_PAD_LCD_DATA14__EIM_DATA06 = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0), @@ -670,6 +692,7 @@ enum { MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 = IOMUX_PAD(0x03E0, 0x0154, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__CSI_DATA23 = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0), MX6_PAD_LCD_DATA15__EIM_DATA07 = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0), @@ -679,6 +702,7 @@ enum { MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__UART7_DTE_RX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0), + MX6_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK = IOMUX_PAD(0x03E4, 0x0158, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0), MX6_PAD_LCD_DATA16__EIM_DATA08 = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0), @@ -688,6 +712,7 @@ enum { MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0), MX6_PAD_LCD_DATA17__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL = IOMUX_PAD(0x03E8, 0x015C, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0), MX6_PAD_LCD_DATA17__EIM_DATA09 = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h index 9c0390a2497..981d069b0a8 100644 --- a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h @@ -430,6 +430,7 @@ enum { MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08 = IOMUX_PAD(0x0370, 0x00E4, 9, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0), @@ -440,6 +441,7 @@ enum { MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0), + MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09 = IOMUX_PAD(0x0374, 0x00E8, 9, 0x0000, 0, 0), MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0), MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0), @@ -450,6 +452,7 @@ enum { MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0), MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0), MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__EPDC_SDDO10 = IOMUX_PAD(0x0378, 0x00EC, 9, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0), @@ -459,6 +462,7 @@ enum { MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11 = IOMUX_PAD(0x037C, 0x00F0, 9, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0), @@ -469,6 +473,7 @@ enum { MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12 = IOMUX_PAD(0x0380, 0x00F4, 9, 0x0000, 0, 0), MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0), MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0), @@ -479,6 +484,7 @@ enum { MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0), MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0), MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0), + MX6_PAD_ENET2_TX_EN__EPDC_SDDO13 = IOMUX_PAD(0x0384, 0x00F8, 9, 0x0000, 0, 0), MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0), @@ -489,6 +495,7 @@ enum { MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0), MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0), MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0), + MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14 = IOMUX_PAD(0x0388, 0x00FC, 9, 0x0000, 0, 0), MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0), MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0), @@ -499,6 +506,7 @@ enum { MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0), MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0), MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__EPDC_SDDO15 = IOMUX_PAD(0x038C, 0x0100, 9, 0x0000, 0, 0), MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0), MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0), @@ -508,6 +516,7 @@ enum { MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0), MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0), MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__EPDC_SDCLK = IOMUX_PAD(0x0390, 0x0104, 9, 0x0000, 0, 0), MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0), MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0), @@ -517,6 +526,7 @@ enum { MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0), MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0), MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__EPDC_SDLE = IOMUX_PAD(0x0394, 0x0108, 9, 0x0000, 0, 0), MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0), MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0), @@ -526,6 +536,7 @@ enum { MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0), MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0), MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__EPDC_SDOE = IOMUX_PAD(0x0398, 0x010C, 9, 0x0000, 0, 0), MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0), MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0), @@ -535,6 +546,7 @@ enum { MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0), MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0), MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__EPDC_SDCE0 = IOMUX_PAD(0x039C, 0x0110, 9, 0x0000, 0, 0), MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0), MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0), @@ -543,6 +555,7 @@ enum { MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0), MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0), MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__EPDC_GDOE = IOMUX_PAD(0x03A0, 0x0114, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0), @@ -551,6 +564,7 @@ enum { MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0), + MX6_PAD_LCD_DATA00__EPDC_SDDO00 = IOMUX_PAD(0x03A4, 0x0118, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0), @@ -559,6 +573,7 @@ enum { MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0), + MX6_PAD_LCD_DATA01__EPDC_SDDO01 = IOMUX_PAD(0x03A8, 0x011C, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0), @@ -567,6 +582,7 @@ enum { MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0), + MX6_PAD_LCD_DATA02__EPDC_SDDO02 = IOMUX_PAD(0x03AC, 0x0120, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0), @@ -575,6 +591,7 @@ enum { MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0), + MX6_PAD_LCD_DATA03__EPDC_SDDO03 = IOMUX_PAD(0x03B0, 0x0124, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0), @@ -584,6 +601,7 @@ enum { MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__EPDC_SDDO04 = IOMUX_PAD(0x03B4, 0x0128, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0), @@ -593,6 +611,7 @@ enum { MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__EPDC_SDDO05 = IOMUX_PAD(0x03B8, 0x012C, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0), @@ -602,6 +621,7 @@ enum { MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__EPDC_SDDO06 = IOMUX_PAD(0x03BC, 0x0130, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0), @@ -611,6 +631,7 @@ enum { MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__EPDC_SDDO07 = IOMUX_PAD(0x03C0, 0x0134, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0), @@ -667,6 +688,7 @@ enum { MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0), + MX6_PAD_LCD_DATA14__EPDC_SDSHR = IOMUX_PAD(0x03DC, 0x0150, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0), @@ -675,6 +697,7 @@ enum { MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0), + MX6_PAD_LCD_DATA15__EPDC_GDRL = IOMUX_PAD(0x03E0, 0x0154, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0), @@ -684,6 +707,7 @@ enum { MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0), + MX6_PAD_LCD_DATA16__EPDC_GDCLK = IOMUX_PAD(0x03E4, 0x0158, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0), @@ -693,6 +717,7 @@ enum { MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0), + MX6_PAD_LCD_DATA17__EPDC_GDSP = IOMUX_PAD(0x03E8, 0x015C, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0), @@ -731,6 +756,7 @@ enum { MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0), + MX6_PAD_LCD_DATA21__EPDC_SDCE1 = IOMUX_PAD(0x03F8, 0x016C, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 33458cd0008..ebb52f8388a 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -1,6 +1,8 @@ /* * (C) Copyright 2009 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,6 +12,7 @@ #include #include +#include #define USBPHY_PWD 0x00000000 @@ -31,4 +34,16 @@ static inline void iomuxc_set_rgmii_io_voltage(int io_vol) __raw_writel(io_vol, IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII); } +void set_wdog_reset(struct wdog_regs *wdog); +enum boot_device get_boot_device(void); + +#ifdef CONFIG_LDO_BYPASS_CHECK +int check_ldo_bypass(void); +int check_1_2G(void); +int set_anatop_bypass(int wdog_reset_pin); +void ldo_mode_set(int ldo_bypass); +void prep_anatop_bypass(void); +void finish_anatop_bypass(void); +#endif + #endif /* __SYS_PROTO_IMX6_ */ diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h index 611190eee73..12f894532ac 100644 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -1999,6 +1999,14 @@ struct mxc_ccm_anatop_reg { #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))< +bool is_usb_boot(void); +#define is_boot_from_usb is_usb_boot + /* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB * If boot from the other mode, USB0_PWD will keep reset value */ -#define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \ +#define is_usbotg_boot_enabled(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \ readl(USBOTG2_IPS_BASE_ADDR + 0x158)) #define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140) diff --git a/arch/arm/include/asm/arch-mx7/snvs.h b/arch/arm/include/asm/arch-mx7/snvs.h new file mode 100644 index 00000000000..a18f8535109 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/snvs.h @@ -0,0 +1,41 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7_SNVS_H__ +#define __MX7_SNVS_H__ + +#define SNVS_HPCOMR SNVS_BASE_ADDR + 0x04 +#define SNVS_HPSICR SNVS_BASE_ADDR + 0x0C +#define SNVS_HPSVCR SNVS_BASE_ADDR + 0x10 +#define SNVS_HPSR SNVS_BASE_ADDR + 0x14 +#define SNVS_HPSVSR SNVS_BASE_ADDR + 0x18 +#define SNVS_LPCR SNVS_BASE_ADDR + 0x38 +#define SNVS_LPMKCR SNVS_BASE_ADDR + 0x3C +#define SNVS_LPTGFCR SNVS_BASE_ADDR + 0x44 +#define SNVS_LPTDCR SNVS_BASE_ADDR + 0x48 +#define SNVS_LPSR SNVS_BASE_ADDR + 0x4C +#define SNVS_LPPGDR SNVS_BASE_ADDR + 0x64 +#define SNVS_LPZMKR0 SNVS_BASE_ADDR + 0x6C +#define SNVS_LPZMKR1 SNVS_BASE_ADDR + 0x70 +#define SNVS_LPZMKR2 SNVS_BASE_ADDR + 0x74 +#define SNVS_LPZMKR3 SNVS_BASE_ADDR + 0x78 +#define SNVS_LPZMKR4 SNVS_BASE_ADDR + 0x7C +#define SNVS_LPZMKR5 SNVS_BASE_ADDR + 0x80 +#define SNVS_LPZMKR6 SNVS_BASE_ADDR + 0x84 +#define SNVS_LPZMKR7 SNVS_BASE_ADDR + 0x88 +#define SNVS_LPTDC2R SNVS_BASE_ADDR + 0xA0 +#define SNVS_LPTDSR SNVS_BASE_ADDR + 0xA4 +#define SNVS_LPTGF1CR SNVS_BASE_ADDR + 0xA8 +#define SNVS_LPTGF2CR SNVS_BASE_ADDR + 0xAC +#define SNVS_LPAT1CR SNVS_BASE_ADDR + 0xC0 +#define SNVS_LPATCTLR SNVS_BASE_ADDR + 0xE0 +#define SNVS_LPATCLKR SNVS_BASE_ADDR + 0xE4 +#define SNVS_LPATRC1R SNVS_BASE_ADDR + 0xE8 +#define SNVS_LPATRC2R SNVS_BASE_ADDR + 0xEC + +#define AT5_POLYSEED 0x12345678 + +#endif diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h index 6424fafe146..b24f257ebb6 100644 --- a/arch/arm/include/asm/arch-mx7ulp/clock.h +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -27,7 +28,7 @@ enum mxc_clock { u32 mxc_get_clock(enum mxc_clock clk); u32 get_lpuart_clk(void); -#ifdef CONFIG_SYS_LPI2C_IMX +#ifdef CONFIG_SYS_I2C_IMX_LPI2C int enable_i2c_clk(unsigned char enable, unsigned i2c_num); u32 imx_get_i2cclk(unsigned i2c_num); #endif @@ -37,6 +38,8 @@ void enable_ocotp_clk(unsigned char enable); #ifdef CONFIG_USB_EHCI_HCD void enable_usboh3_clk(unsigned char enable); #endif +void enable_mipi_dsi_clk(unsigned char enable); +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz); void init_clk_usdhc(u32 index); void clock_init(void); void hab_caam_clock_enable(unsigned char enable); diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index dd9db73db26..9e0eada4b11 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,10 +10,14 @@ #include +#define ROM_SW_INFO_ADDR 0x000001E8 + #define CAAM_SEC_SRAM_BASE (0x26000000) #define CAAM_SEC_SRAM_SIZE (SZ_32K) #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) +#define CAAM_ARB_BASE_ADDR CAAM_SEC_SRAM_BASE + #define OCRAM_0_BASE (0x2F000000) #define OCRAM_0_SIZE (SZ_128K) #define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) @@ -55,12 +60,15 @@ #define USDHC1_AIPS2_SLOT (56) #define RGPIO2P0_AIPS0_SLOT (15) #define RGPIO2P1_AIPS2_SLOT (15) +#define SNVS_AIPS2_SLOT (35) #define IOMUXC0_AIPS0_SLOT (61) #define OCOTP_CTRL_AIPS1_SLOT (38) #define OCOTP_CTRL_PCC1_SLOT (38) #define SIM1_PCC1_SLOT (48) #define MMDC0_AIPS3_SLOT (43) #define IOMUXC_DDR_AIPS3_SLOT (45) +#define DSI_AIPS3_SLOT (41) +#define LCDIF_AIPS3_SLOT (42) #define LPI2C0_AIPS0_SLOT (51) #define LPI2C1_AIPS0_SLOT (52) @@ -123,6 +131,9 @@ #define SIM_SOPT1_PMIC_STBY_REQ (1<<2) #define SIM_SOPT1_A7_SW_RESET (1<<0) +#define WKPU_WAKEUP_EN 0x88 +#define WKPU_QSPI_CHANNEL BIT(20) + #define IOMUXC_PCR_MUX_ALT_SHIFT (8) #define IOMUXC_PCR_MUX_ALT_MASK (0xF00) #define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) @@ -174,6 +185,13 @@ #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) +#define DSI_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * DSI_AIPS3_SLOT))) +#define LCDIF_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LCDIF_AIPS3_SLOT))) +#define MXS_LCDIF_BASE LCDIF_RBASE + +#define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT))) +#define SNVS_LP_LPCR (SNVS_BASE + 0x38) + #define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) #define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT))) @@ -217,6 +235,16 @@ #define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) #define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) +#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */ + +#define CONFIG_SYS_FSL_SEC_OFFSET 0 +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) @@ -936,6 +964,11 @@ #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL)) +#define SNVS_LPCR_DPEN (0x20) +#define SNVS_LPCR_SRTC_ENV (0x1) + +#include + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include @@ -1111,10 +1144,23 @@ struct usbphy_regs { u32 usb1_pfda_ctrl1_tog; /* 0x14c */ }; - -#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) +#include +bool is_usb_boot(void); +#define is_boot_from_usb is_usb_boot #define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) +struct bootrom_sw_info { + u8 reserved_1; + u8 boot_dev_instance; + u8 boot_dev_type; + u8 reserved_2; + u32 core_freq; + u32 axi_freq; + u32 ddr_freq; + u32 rom_tick_freq; + u32 reserved_3[3]; +}; + #endif #endif /* _MX7ULP_REGS_H_*/ diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h index 4e4740c9648..ec61b0bd2db 100644 --- a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h +++ b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h @@ -13,7 +13,7 @@ enum { MX7ULP_PAD_PTA0__CMP0_IN1_3V = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA0__PTA0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA0__LPSPI0_PCS1 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x2, 0), - MX7ULP_PAD_PTA0__LPUART0_CTS_b = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0), + MX7ULP_PAD_PTA0__LPUART0_CTS_B = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0), MX7ULP_PAD_PTA0__LPI2C0_SCL = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x2, 0), MX7ULP_PAD_PTA0__TPM0_CLKIN = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x2, 0), MX7ULP_PAD_PTA0__I2S0_RX_BCLK = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x2, 0), @@ -21,7 +21,7 @@ enum { MX7ULP_PAD_PTA1__CMP0_IN2_3V = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA1__PTA1 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA1__LPSPI0_PCS2 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x1, 0), - MX7ULP_PAD_PTA1__LPUART0_RTS_b = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA1__LPUART0_RTS_B = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA1__LPI2C0_SDA = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x1, 0), MX7ULP_PAD_PTA1__TPM0_CH0 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x1, 0), MX7ULP_PAD_PTA1__I2S0_RX_FS = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x1, 0), @@ -43,72 +43,72 @@ enum { MX7ULP_PAD_PTA4__ADC1_CH3A = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA4__PTA4 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA4__LPSPI0_SIN = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x1, 0), - MX7ULP_PAD_PTA4__LPUART1_CTS_b = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0), + MX7ULP_PAD_PTA4__LPUART1_CTS_B = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0), MX7ULP_PAD_PTA4__LPI2C1_SCL = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x1, 0), MX7ULP_PAD_PTA4__TPM0_CH3 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x1, 0), MX7ULP_PAD_PTA4__I2S0_MCLK = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x1, 0), MX7ULP_PAD_PTA5__ADC1_CH3B = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA5__PTA5 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA5__LPSPI0_SOUT = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x1, 0), - MX7ULP_PAD_PTA5__LPUART1_RTS_b = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA5__LPUART1_RTS_B = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA5__LPI2C1_SDA = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x1, 0), MX7ULP_PAD_PTA5__TPM0_CH4 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x1, 0), MX7ULP_PAD_PTA5__I2S0_TX_BCLK = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x1, 0), - MX7ULP_PAD_PTA6__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA6__ADC1_CH4A = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA6__PTA6 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA6__LPSPI0_SCK = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x1, 0), MX7ULP_PAD_PTA6__LPUART1_TX = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x1, 0), MX7ULP_PAD_PTA6__LPI2C1_HREQ = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x1, 0), MX7ULP_PAD_PTA6__TPM0_CH5 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x1, 0), MX7ULP_PAD_PTA6__I2S0_TX_FS = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x1, 0), - MX7ULP_PAD_PTA7__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA7__ADC1_CH4B = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA7__PTA7 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA7__LPUART1_RX = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x1, 0), MX7ULP_PAD_PTA7__TPM1_CH1 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x1, 0), MX7ULP_PAD_PTA7__I2S0_TXD0 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA8__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA8__ADC1_CH5A = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA8__PTA8 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA8__LPSPI1_PCS1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x1, 0), - MX7ULP_PAD_PTA8__LPUART2_CTS_b = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0), + MX7ULP_PAD_PTA8__LPUART2_CTS_B = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0), MX7ULP_PAD_PTA8__LPI2C2_SCL = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x1, 0), MX7ULP_PAD_PTA8__TPM1_CLKIN = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x1, 0), MX7ULP_PAD_PTA8__I2S0_TXD1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA9__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__ADC1_CH5B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA9__PTA9 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA9__LPSPI1_PCS2 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x1, 0), - MX7ULP_PAD_PTA9__LPUART2_RTS_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__LPUART2_RTS_B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA9__LPI2C2_SDA = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x1, 0), MX7ULP_PAD_PTA9__TPM1_CH0 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x1, 0), - MX7ULP_PAD_PTA9__NMI0_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA10__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__NMI0_B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA10__ADC1_CH6A = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA10__PTA10 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA10__LPSPI1_PCS3 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x1, 0), MX7ULP_PAD_PTA10__LPUART2_TX = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x1, 0), MX7ULP_PAD_PTA10__LPI2C2_HREQ = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x1, 0), MX7ULP_PAD_PTA10__TPM2_CLKIN = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x1, 0), MX7ULP_PAD_PTA10__I2S0_RX_BCLK = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x1, 0), - MX7ULP_PAD_PTA11__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA11__ADC1_CH6B = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA11__PTA11 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA11__LPUART2_RX = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x1, 0), MX7ULP_PAD_PTA11__TPM2_CH0 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x1, 0), MX7ULP_PAD_PTA11__I2S0_RX_FS = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x2, 0), - MX7ULP_PAD_PTA12__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA12__ADC1_CH7A = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA12__PTA12 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA12__LPSPI1_SIN = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x1, 0), - MX7ULP_PAD_PTA12__LPUART3_CTS_b = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0), + MX7ULP_PAD_PTA12__LPUART3_CTS_B = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0), MX7ULP_PAD_PTA12__LPI2C3_SCL = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x1, 0), MX7ULP_PAD_PTA12__TPM2_CH1 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x1, 0), MX7ULP_PAD_PTA12__I2S0_RXD0 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x2, 0), - MX7ULP_PAD_PTA13__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__ADC1_CH7B = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA13__PTA13 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA13__LPSPI1_SOUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x2, 0), - MX7ULP_PAD_PTA13__LPUART3_RTS_b = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__LPUART3_RTS_B = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA13__LPI2C3_SDA = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x2, 0), MX7ULP_PAD_PTA13__TPM3_CLKIN = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x1, 0), MX7ULP_PAD_PTA13__I2S0_RXD1 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x2, 0), MX7ULP_PAD_PTA13__CMP0_OUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTA13__LLWU0_P2 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA14__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA14__ADC1_CH8A = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA14__PTA14 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA14__LPSPI1_SCK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x2, 0), MX7ULP_PAD_PTA14__LPUART3_TX = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x2, 0), @@ -116,7 +116,7 @@ enum { MX7ULP_PAD_PTA14__TPM3_CH0 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x1, 0), MX7ULP_PAD_PTA14__I2S0_MCLK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x2, 0), MX7ULP_PAD_PTA14__LLWU0_P3 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA15__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA15__ADC1_CH8B = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA15__PTA15 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA15__LPSPI1_PCS0 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x1, 0), MX7ULP_PAD_PTA15__LPUART3_RX = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x1, 0), @@ -126,7 +126,7 @@ enum { MX7ULP_PAD_PTA16__PTA16 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA16__FXIO0_D0 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA16__LPSPI0_SOUT = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x2, 0), - MX7ULP_PAD_PTA16__LPUART0_CTS_b = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0), + MX7ULP_PAD_PTA16__LPUART0_CTS_B = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0), MX7ULP_PAD_PTA16__LPI2C0_SCL = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x1, 0), MX7ULP_PAD_PTA16__TPM3_CH2 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x1, 0), MX7ULP_PAD_PTA16__I2S0_TX_FS = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x2, 0), @@ -134,7 +134,7 @@ enum { MX7ULP_PAD_PTA17__PTA17 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA17__FXIO0_D1 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA17__LPSPI0_SCK = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x2, 0), - MX7ULP_PAD_PTA17__LPUART0_RTS_b = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA17__LPUART0_RTS_B = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA17__LPI2C0_SDA = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x2, 0), MX7ULP_PAD_PTA17__TPM3_CH3 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x1, 0), MX7ULP_PAD_PTA17__I2S0_TXD0 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), @@ -155,23 +155,23 @@ enum { MX7ULP_PAD_PTA19__I2S1_RX_BCLK = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x1, 0), MX7ULP_PAD_PTA19__LPTMR0_ALT3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTA19__LLWU0_P5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA20__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA20__ADC0_10A = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA20__PTA20 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA20__FXIO0_D4 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA20__LPSPI0_SIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x2, 0), - MX7ULP_PAD_PTA20__LPUART1_CTS_b = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0), + MX7ULP_PAD_PTA20__LPUART1_CTS_B = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0), MX7ULP_PAD_PTA20__LPI2C1_SCL = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x2, 0), MX7ULP_PAD_PTA20__TPM0_CLKIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x1, 0), MX7ULP_PAD_PTA20__I2S1_RX_FS = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x1, 0), - MX7ULP_PAD_PTA21__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__ADC0_CH10B = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA21__PTA21 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA21__FXIO0_D5 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA21__LPSPI0_PCS1 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x1, 0), - MX7ULP_PAD_PTA21__LPUART1_RTS_b = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__LPUART1_RTS_B = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA21__LPI2C1_SDA = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x2, 0), MX7ULP_PAD_PTA21__TPM0_CH0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x2, 0), MX7ULP_PAD_PTA21__I2S1_RXD0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x1, 0), - MX7ULP_PAD_PTA22__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__ADC0_CH9A = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA22__PTA22 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA22__FXIO0_D6 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA22__LPSPI0_PCS2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x2, 0), @@ -180,8 +180,8 @@ enum { MX7ULP_PAD_PTA22__TPM0_CH1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x2, 0), MX7ULP_PAD_PTA22__I2S1_RXD1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x1, 0), MX7ULP_PAD_PTA22__LPTMR0_ALT2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA22__EWM_OUT_b = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA23__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__EWM_OUT_B = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA23__ADC0_CH9B = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA23__PTA23 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA23__FXIO0_D7 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA23__LPSPI0_PCS3 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x2, 0), @@ -189,19 +189,19 @@ enum { MX7ULP_PAD_PTA23__TPM0_CH2 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x2, 0), MX7ULP_PAD_PTA23__I2S1_MCLK = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x1, 0), MX7ULP_PAD_PTA23__LLWU0_P6 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA24__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA24__ADC0_CH8A = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA24__PTA24 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA24__FXIO0_D8 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA24__LPSPI1_PCS1 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x2, 0), - MX7ULP_PAD_PTA24__LPUART2_CTS_b = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0), + MX7ULP_PAD_PTA24__LPUART2_CTS_B = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0), MX7ULP_PAD_PTA24__LPI2C2_SCL = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x2, 0), MX7ULP_PAD_PTA24__TPM0_CH3 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x2, 0), MX7ULP_PAD_PTA24__I2S1_TX_BCLK = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x1, 0), - MX7ULP_PAD_PTA25__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__ADC0_CH8B = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA25__PTA25 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA25__FXIO0_D9 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA25__LPSPI1_PCS2 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x2, 0), - MX7ULP_PAD_PTA25__LPUART2_RTS_b = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__LPUART2_RTS_B = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA25__LPI2C2_SDA = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x2, 0), MX7ULP_PAD_PTA25__TPM0_CH4 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x2, 0), MX7ULP_PAD_PTA25__I2S1_TX_FS = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x1, 0), @@ -223,7 +223,7 @@ enum { MX7ULP_PAD_PTA28__JTAG_TDI = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), MX7ULP_PAD_PTA28__FXIO0_D12 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA28__LPSPI1_SIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x2, 0), - MX7ULP_PAD_PTA28__LPUART3_CTS_b = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0), + MX7ULP_PAD_PTA28__LPUART3_CTS_B = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0), MX7ULP_PAD_PTA28__LPI2C3_SCL = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x2, 0), MX7ULP_PAD_PTA28__TPM1_CLKIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x2, 0), MX7ULP_PAD_PTA28__I2S1_TXD2 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), @@ -231,7 +231,7 @@ enum { MX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), MX7ULP_PAD_PTA29__FXIO0_D13 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA29__LPSPI1_SOUT = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x1, 0), - MX7ULP_PAD_PTA29__LPUART3_RTS_b = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__LPUART3_RTS_B = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA29__LPI2C3_SDA = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x1, 0), MX7ULP_PAD_PTA29__TPM1_CH0 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x2, 0), MX7ULP_PAD_PTA29__I2S1_TXD3 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), @@ -243,7 +243,7 @@ enum { MX7ULP_PAD_PTA30__LPI2C3_HREQ = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x1, 0), MX7ULP_PAD_PTA30__TPM2_CLKIN = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x2, 0), MX7ULP_PAD_PTA30__I2S1_TXD0 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__JTAG_TRST_b = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__JTAG_TRST_B = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), MX7ULP_PAD_PTA31__ADC0_CH1B = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA31__PTA31 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA31__FXIO0_D15 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), @@ -262,7 +262,7 @@ enum { MX7ULP_PAD_PTB0__TPM2_CH1 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x2, 0), MX7ULP_PAD_PTB0__CLKOUT0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTB0__CMP1_OUT = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__EWM_OUT_b = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__EWM_OUT_B = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTB1__ADC0_CH0B = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB1__PTB1 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB1__FXIO0_D17 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), @@ -273,7 +273,7 @@ enum { MX7ULP_PAD_PTB1__RTC_CLKOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTB1__EWM_IN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x2, 0), MX7ULP_PAD_PTB1__LLWU0_P8 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB2__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB2__ADC0_CH6A = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB2__PTB2 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB2__FXIO0_D18 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTB2__LPSPI0_SCK = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x3, 0), @@ -281,7 +281,7 @@ enum { MX7ULP_PAD_PTB2__TPM3_CH0 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x2, 0), MX7ULP_PAD_PTB2__I2S1_TX_FS = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x2, 0), MX7ULP_PAD_PTB2__TRACE_CLKOUT = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__ADC0_CH6B = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB3__PTB3 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB3__FXIO0_D19 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTB3__LPSPI0_PCS0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x3, 0), @@ -300,6 +300,7 @@ enum { MX7ULP_PAD_PTB4__I2S1_TXD1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), MX7ULP_PAD_PTB4__QSPIA_DATA7 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTB4__TRACE_D1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__SEC_VIO_B = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTB5__PTB5 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB5__FXIO0_D21 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTB5__LPSPI0_PCS2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x3, 0), @@ -309,6 +310,7 @@ enum { MX7ULP_PAD_PTB5__I2S1_TXD2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), MX7ULP_PAD_PTB5__QSPIA_DATA6 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTB5__TRACE_D2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__RTC_CLKOUT = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTB6__ADC1_CH1A = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB6__PTB6 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB6__FXIO0_D22 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), @@ -370,6 +372,7 @@ enum { MX7ULP_PAD_PTB12__PTB12 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB12__FXIO0_D28 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTB12__LPSPI1_PCS2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x3, 0), + MX7ULP_PAD_PTB12__LPUART2_TX = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x4, 0), MX7ULP_PAD_PTB12__LPI2C3_SCL = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x3, 0), MX7ULP_PAD_PTB12__TPM1_CH0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x3, 0), MX7ULP_PAD_PTB12__I2S1_RXD2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x2, 0), @@ -378,6 +381,7 @@ enum { MX7ULP_PAD_PTB13__PTB13 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB13__FXIO0_D29 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTB13__LPSPI1_PCS3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x3, 0), + MX7ULP_PAD_PTB13__LPUART2_RX = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x4, 0), MX7ULP_PAD_PTB13__LPI2C3_SDA = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x3, 0), MX7ULP_PAD_PTB13__TPM1_CH1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x3, 0), MX7ULP_PAD_PTB13__I2S1_RXD3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x2, 0), @@ -389,7 +393,8 @@ enum { MX7ULP_PAD_PTB14__LPI2C2_HREQ = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x3, 0), MX7ULP_PAD_PTB14__TPM2_CLKIN = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x3, 0), MX7ULP_PAD_PTB14__QSPIA_SS1_B = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__QSPIA_SCLK_b = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__QSPIA_SCLK_B = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__RTC_CLKOUT = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTB14__LLWU0_P13 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), MX7ULP_PAD_PTB15__ADC1_CH2B = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB15__PTB15 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), @@ -397,70 +402,64 @@ enum { MX7ULP_PAD_PTB15__LPI2C3_HREQ = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x3, 0), MX7ULP_PAD_PTB15__TPM2_CH0 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x3, 0), MX7ULP_PAD_PTB15__QSPIA_SCLK = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB16__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB16__ADC0_CH4A = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB16__PTB16 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB16__TPM2_CH1 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x3, 0), MX7ULP_PAD_PTB16__QSPIA_DATA3 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTB16__LLWU0_P14 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB17__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB17__ADC0_CH4B = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB17__PTB17 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB17__TPM3_CLKIN = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x2, 0), MX7ULP_PAD_PTB17__QSPIA_DATA2 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB18__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB18__ADC0_CH5A = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB18__PTB18 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB18__TPM3_CH0 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x3, 0), MX7ULP_PAD_PTB18__QSPIA_DATA1 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__ADC0_CH5B = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB19__PTB19 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB19__TPM3_CH1 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x3, 0), MX7ULP_PAD_PTB19__QSPIA_DATA0 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__USB0_ID = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__USB0_ID = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0xD338, 0x0, 0), MX7ULP_PAD_PTB19__LLWU0_P15 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), MX7ULP_PAD_PTC0__PTC0 = IOMUX_PAD(0x0000, 0x0000, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__LPUART4_CTS_b = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0), + MX7ULP_PAD_PTC0__LPUART4_CTS_B = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0), MX7ULP_PAD_PTC0__LPI2C4_SCL = IOMUX_PAD(0x0000, 0x0000, 0x5, 0x0278, 0x1, 0), MX7ULP_PAD_PTC0__TPM4_CLKIN = IOMUX_PAD(0x0000, 0x0000, 0x6, 0x0298, 0x1, 0), MX7ULP_PAD_PTC0__FB_AD0 = IOMUX_PAD(0x0000, 0x0000, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC0__TRACE_D15 = IOMUX_PAD(0x0000, 0x0000, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__DEBUG_MUX0 = IOMUX_PAD(0x0000, 0x0000, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC1__PTC1 = IOMUX_PAD(0x0004, 0x0004, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__LPUART4_RTS_b = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__LPUART4_RTS_B = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTC1__LPI2C4_SDA = IOMUX_PAD(0x0004, 0x0004, 0x5, 0x027C, 0x1, 0), MX7ULP_PAD_PTC1__TPM4_CH0 = IOMUX_PAD(0x0004, 0x0004, 0x6, 0x0280, 0x1, 0), MX7ULP_PAD_PTC1__FB_AD1 = IOMUX_PAD(0x0004, 0x0004, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC1__TRACE_D14 = IOMUX_PAD(0x0004, 0x0004, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__DEBUG_MUX1 = IOMUX_PAD(0x0004, 0x0004, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC2__PTC2 = IOMUX_PAD(0x0008, 0x0008, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC2__LPUART4_TX = IOMUX_PAD(0x0008, 0x0008, 0x4, 0x024C, 0x1, 0), MX7ULP_PAD_PTC2__LPI2C4_HREQ = IOMUX_PAD(0x0008, 0x0008, 0x5, 0x0274, 0x1, 0), MX7ULP_PAD_PTC2__TPM4_CH1 = IOMUX_PAD(0x0008, 0x0008, 0x6, 0x0284, 0x1, 0), MX7ULP_PAD_PTC2__FB_AD2 = IOMUX_PAD(0x0008, 0x0008, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC2__TRACE_D13 = IOMUX_PAD(0x0008, 0x0008, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC2__DEBUG_MUX2 = IOMUX_PAD(0x0008, 0x0008, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC3__PTC3 = IOMUX_PAD(0x000C, 0x000C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC3__LPUART4_RX = IOMUX_PAD(0x000C, 0x000C, 0x4, 0x0248, 0x1, 0), MX7ULP_PAD_PTC3__TPM4_CH2 = IOMUX_PAD(0x000C, 0x000C, 0x6, 0x0288, 0x1, 0), MX7ULP_PAD_PTC3__FB_AD3 = IOMUX_PAD(0x000C, 0x000C, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC3__TRACE_D12 = IOMUX_PAD(0x000C, 0x000C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC3__DEBUG_MUX3 = IOMUX_PAD(0x000C, 0x000C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC4__PTC4 = IOMUX_PAD(0x0010, 0x0010, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC4__FXIO1_D0 = IOMUX_PAD(0x0010, 0x0010, 0x2, 0x0204, 0x1, 0), MX7ULP_PAD_PTC4__LPSPI2_PCS1 = IOMUX_PAD(0x0010, 0x0010, 0x3, 0x02A0, 0x1, 0), - MX7ULP_PAD_PTC4__LPUART5_CTS_b = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0), + MX7ULP_PAD_PTC4__LPUART5_CTS_B = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0), MX7ULP_PAD_PTC4__LPI2C5_SCL = IOMUX_PAD(0x0010, 0x0010, 0x5, 0x02BC, 0x1, 0), MX7ULP_PAD_PTC4__TPM4_CH3 = IOMUX_PAD(0x0010, 0x0010, 0x6, 0x028C, 0x1, 0), MX7ULP_PAD_PTC4__FB_AD4 = IOMUX_PAD(0x0010, 0x0010, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC4__TRACE_D11 = IOMUX_PAD(0x0010, 0x0010, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC4__DEBUG_MUX4 = IOMUX_PAD(0x0010, 0x0010, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC5__PTC5 = IOMUX_PAD(0x0014, 0x0014, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC5__FXIO1_D1 = IOMUX_PAD(0x0014, 0x0014, 0x2, 0x0208, 0x1, 0), MX7ULP_PAD_PTC5__LPSPI2_PCS2 = IOMUX_PAD(0x0014, 0x0014, 0x3, 0x02A4, 0x1, 0), - MX7ULP_PAD_PTC5__LPUART5_RTS_b = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__LPUART5_RTS_B = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTC5__LPI2C5_SDA = IOMUX_PAD(0x0014, 0x0014, 0x5, 0x02C0, 0x1, 0), MX7ULP_PAD_PTC5__TPM4_CH4 = IOMUX_PAD(0x0014, 0x0014, 0x6, 0x0290, 0x1, 0), MX7ULP_PAD_PTC5__FB_AD5 = IOMUX_PAD(0x0014, 0x0014, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC5__TRACE_D10 = IOMUX_PAD(0x0014, 0x0014, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__DEBUG_MUX5 = IOMUX_PAD(0x0014, 0x0014, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC6__PTC6 = IOMUX_PAD(0x0018, 0x0018, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC6__FXIO1_D2 = IOMUX_PAD(0x0018, 0x0018, 0x2, 0x020C, 0x1, 0), MX7ULP_PAD_PTC6__LPSPI2_PCS3 = IOMUX_PAD(0x0018, 0x0018, 0x3, 0x02A8, 0x1, 0), @@ -469,32 +468,28 @@ enum { MX7ULP_PAD_PTC6__TPM4_CH5 = IOMUX_PAD(0x0018, 0x0018, 0x6, 0x0294, 0x1, 0), MX7ULP_PAD_PTC6__FB_AD6 = IOMUX_PAD(0x0018, 0x0018, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC6__TRACE_D9 = IOMUX_PAD(0x0018, 0x0018, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC6__DEBUG_MUX6 = IOMUX_PAD(0x0018, 0x0018, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC7__PTC7 = IOMUX_PAD(0x001C, 0x001C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC7__FXIO1_D3 = IOMUX_PAD(0x001C, 0x001C, 0x2, 0x0210, 0x1, 0), MX7ULP_PAD_PTC7__LPUART5_RX = IOMUX_PAD(0x001C, 0x001C, 0x4, 0x0254, 0x1, 0), MX7ULP_PAD_PTC7__TPM5_CH1 = IOMUX_PAD(0x001C, 0x001C, 0x6, 0x02C8, 0x1, 0), MX7ULP_PAD_PTC7__FB_AD7 = IOMUX_PAD(0x001C, 0x001C, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC7__TRACE_D8 = IOMUX_PAD(0x001C, 0x001C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC7__DEBUG_MUX7 = IOMUX_PAD(0x001C, 0x001C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC8__PTC8 = IOMUX_PAD(0x0020, 0x0020, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC8__FXIO1_D4 = IOMUX_PAD(0x0020, 0x0020, 0x2, 0x0214, 0x1, 0), MX7ULP_PAD_PTC8__LPSPI2_SIN = IOMUX_PAD(0x0020, 0x0020, 0x3, 0x02B0, 0x1, 0), - MX7ULP_PAD_PTC8__LPUART6_CTS_b = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0), + MX7ULP_PAD_PTC8__LPUART6_CTS_B = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0), MX7ULP_PAD_PTC8__LPI2C6_SCL = IOMUX_PAD(0x0020, 0x0020, 0x5, 0x02FC, 0x1, 0), MX7ULP_PAD_PTC8__TPM5_CLKIN = IOMUX_PAD(0x0020, 0x0020, 0x6, 0x02CC, 0x1, 0), MX7ULP_PAD_PTC8__FB_AD8 = IOMUX_PAD(0x0020, 0x0020, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC8__TRACE_D7 = IOMUX_PAD(0x0020, 0x0020, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC8__DEBUG_MUX8 = IOMUX_PAD(0x0020, 0x0020, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC9__PTC9 = IOMUX_PAD(0x0024, 0x0024, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC9__FXIO1_D5 = IOMUX_PAD(0x0024, 0x0024, 0x2, 0x0218, 0x1, 0), MX7ULP_PAD_PTC9__LPSPI2_SOUT = IOMUX_PAD(0x0024, 0x0024, 0x3, 0x02B4, 0x1, 0), - MX7ULP_PAD_PTC9__LPUART6_RTS_b = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__LPUART6_RTS_B = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTC9__LPI2C6_SDA = IOMUX_PAD(0x0024, 0x0024, 0x5, 0x0300, 0x1, 0), MX7ULP_PAD_PTC9__TPM5_CH0 = IOMUX_PAD(0x0024, 0x0024, 0x6, 0x02C4, 0x1, 0), MX7ULP_PAD_PTC9__FB_AD9 = IOMUX_PAD(0x0024, 0x0024, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC9__TRACE_D6 = IOMUX_PAD(0x0024, 0x0024, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__DEBUG_MUX9 = IOMUX_PAD(0x0024, 0x0024, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC10__PTC10 = IOMUX_PAD(0x0028, 0x0028, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC10__FXIO1_D6 = IOMUX_PAD(0x0028, 0x0028, 0x2, 0x021C, 0x1, 0), MX7ULP_PAD_PTC10__LPSPI2_SCK = IOMUX_PAD(0x0028, 0x0028, 0x3, 0x02AC, 0x1, 0), @@ -503,7 +498,6 @@ enum { MX7ULP_PAD_PTC10__TPM7_CH3 = IOMUX_PAD(0x0028, 0x0028, 0x6, 0x02E8, 0x1, 0), MX7ULP_PAD_PTC10__FB_AD10 = IOMUX_PAD(0x0028, 0x0028, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC10__TRACE_D5 = IOMUX_PAD(0x0028, 0x0028, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC10__DEBUG_MUX10 = IOMUX_PAD(0x0028, 0x0028, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC11__PTC11 = IOMUX_PAD(0x002C, 0x002C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC11__FXIO1_D7 = IOMUX_PAD(0x002C, 0x002C, 0x2, 0x0220, 0x1, 0), MX7ULP_PAD_PTC11__LPSPI2_PCS0 = IOMUX_PAD(0x002C, 0x002C, 0x3, 0x029C, 0x1, 0), @@ -511,25 +505,23 @@ enum { MX7ULP_PAD_PTC11__TPM7_CH4 = IOMUX_PAD(0x002C, 0x002C, 0x6, 0x02EC, 0x1, 0), MX7ULP_PAD_PTC11__FB_AD11 = IOMUX_PAD(0x002C, 0x002C, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC11__TRACE_D4 = IOMUX_PAD(0x002C, 0x002C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC11__DEBUG_MUX11 = IOMUX_PAD(0x002C, 0x002C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC12__PTC12 = IOMUX_PAD(0x0030, 0x0030, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC12__FXIO1_D8 = IOMUX_PAD(0x0030, 0x0030, 0x2, 0x0224, 0x1, 0), MX7ULP_PAD_PTC12__LPSPI3_PCS1 = IOMUX_PAD(0x0030, 0x0030, 0x3, 0x0314, 0x1, 0), - MX7ULP_PAD_PTC12__LPUART7_CTS_b = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0), + MX7ULP_PAD_PTC12__LPUART7_CTS_B = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0), MX7ULP_PAD_PTC12__LPI2C7_SCL = IOMUX_PAD(0x0030, 0x0030, 0x5, 0x0308, 0x1, 0), MX7ULP_PAD_PTC12__TPM7_CH5 = IOMUX_PAD(0x0030, 0x0030, 0x6, 0x02F0, 0x1, 0), MX7ULP_PAD_PTC12__FB_AD12 = IOMUX_PAD(0x0030, 0x0030, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC12__TRACE_D3 = IOMUX_PAD(0x0030, 0x0030, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC12__DEBUG_MUX12 = IOMUX_PAD(0x0030, 0x0030, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC13__PTC13 = IOMUX_PAD(0x0034, 0x0034, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC13__FXIO1_D9 = IOMUX_PAD(0x0034, 0x0034, 0x2, 0x0228, 0x1, 0), MX7ULP_PAD_PTC13__LPSPI3_PCS2 = IOMUX_PAD(0x0034, 0x0034, 0x3, 0x0318, 0x1, 0), - MX7ULP_PAD_PTC13__LPUART7_RTS_b = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__LPUART7_RTS_B = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTC13__LPI2C7_SDA = IOMUX_PAD(0x0034, 0x0034, 0x5, 0x030C, 0x1, 0), MX7ULP_PAD_PTC13__TPM7_CLKIN = IOMUX_PAD(0x0034, 0x0034, 0x6, 0x02F4, 0x1, 0), MX7ULP_PAD_PTC13__FB_AD13 = IOMUX_PAD(0x0034, 0x0034, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC13__TRACE_D2 = IOMUX_PAD(0x0034, 0x0034, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC13__DEBUG_MUX13 = IOMUX_PAD(0x0034, 0x0034, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__USB0_ID = IOMUX_PAD(0x0034, 0x0034, 0xb, 0x0338, 0x1, 0), MX7ULP_PAD_PTC14__PTC14 = IOMUX_PAD(0x0038, 0x0038, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC14__FXIO1_D10 = IOMUX_PAD(0x0038, 0x0038, 0x2, 0x022C, 0x1, 0), MX7ULP_PAD_PTC14__LPSPI3_PCS3 = IOMUX_PAD(0x0038, 0x0038, 0x3, 0x031C, 0x1, 0), @@ -538,122 +530,107 @@ enum { MX7ULP_PAD_PTC14__TPM7_CH0 = IOMUX_PAD(0x0038, 0x0038, 0x6, 0x02DC, 0x1, 0), MX7ULP_PAD_PTC14__FB_AD14 = IOMUX_PAD(0x0038, 0x0038, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC14__TRACE_D1 = IOMUX_PAD(0x0038, 0x0038, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC14__DEBUG_MUX14 = IOMUX_PAD(0x0038, 0x0038, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC15__PTC15 = IOMUX_PAD(0x003C, 0x003C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC15__FXIO1_D11 = IOMUX_PAD(0x003C, 0x003C, 0x2, 0x0230, 0x1, 0), MX7ULP_PAD_PTC15__LPUART7_RX = IOMUX_PAD(0x003C, 0x003C, 0x4, 0x026C, 0x1, 0), MX7ULP_PAD_PTC15__TPM7_CH1 = IOMUX_PAD(0x003C, 0x003C, 0x6, 0x02E0, 0x1, 0), MX7ULP_PAD_PTC15__FB_AD15 = IOMUX_PAD(0x003C, 0x003C, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC15__TRACE_D0 = IOMUX_PAD(0x003C, 0x003C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC15__DEBUG_MUX15 = IOMUX_PAD(0x003C, 0x003C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC16__PTC16 = IOMUX_PAD(0x0040, 0x0040, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC16__FXIO1_D12 = IOMUX_PAD(0x0040, 0x0040, 0x2, 0x0234, 0x1, 0), MX7ULP_PAD_PTC16__LPSPI3_SIN = IOMUX_PAD(0x0040, 0x0040, 0x3, 0x0324, 0x1, 0), MX7ULP_PAD_PTC16__TPM7_CH2 = IOMUX_PAD(0x0040, 0x0040, 0x6, 0x02E4, 0x1, 0), - MX7ULP_PAD_PTC16__FB_ALE_FB_CS1_b_FB_TS_b = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC16__TRACE_CLKOUT = IOMUX_PAD(0x0040, 0x0040, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC16__USB1_ULPI_OC2 = IOMUX_PAD(0x0040, 0x0040, 0xb, 0x0334, 0x1, 0), + MX7ULP_PAD_PTC16__USB1_OC2 = IOMUX_PAD(0x0040, 0x0040, 0xb, 0x0334, 0x1, 0), MX7ULP_PAD_PTC17__PTC17 = IOMUX_PAD(0x0044, 0x0044, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC17__FXIO1_D13 = IOMUX_PAD(0x0044, 0x0044, 0x2, 0x0238, 0x1, 0), MX7ULP_PAD_PTC17__LPSPI3_SOUT = IOMUX_PAD(0x0044, 0x0044, 0x3, 0x0328, 0x1, 0), MX7ULP_PAD_PTC17__TPM6_CLKIN = IOMUX_PAD(0x0044, 0x0044, 0x6, 0x02D8, 0x1, 0), - MX7ULP_PAD_PTC17__FB_CS0_b = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC17__DEBUG_MUX16 = IOMUX_PAD(0x0044, 0x0044, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC17__FB_CS0_B = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC18__PTC18 = IOMUX_PAD(0x0048, 0x0048, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC18__FXIO1_D14 = IOMUX_PAD(0x0048, 0x0048, 0x2, 0x023C, 0x1, 0), MX7ULP_PAD_PTC18__LPSPI3_SCK = IOMUX_PAD(0x0048, 0x0048, 0x3, 0x0320, 0x1, 0), MX7ULP_PAD_PTC18__TPM6_CH0 = IOMUX_PAD(0x0048, 0x0048, 0x6, 0x02D0, 0x1, 0), - MX7ULP_PAD_PTC18__FB_OE_b = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC18__DEBUG_MUX17 = IOMUX_PAD(0x0048, 0x0048, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC18__FB_OE_B = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC18__USB0_ID = IOMUX_PAD(0x0048, 0x0048, 0xb, 0x0338, 0x2, 0), + MX7ULP_PAD_PTC18__VIU_DE = IOMUX_PAD(0x0048, 0x0048, 0xc, 0x033c, 0x1, 0), MX7ULP_PAD_PTC19__PTC19 = IOMUX_PAD(0x004C, 0x004C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC19__FXIO1_D15 = IOMUX_PAD(0x004C, 0x004C, 0x2, 0x0240, 0x1, 0), MX7ULP_PAD_PTC19__LPSPI3_PCS0 = IOMUX_PAD(0x004C, 0x004C, 0x3, 0x0310, 0x1, 0), MX7ULP_PAD_PTC19__TPM6_CH1 = IOMUX_PAD(0x004C, 0x004C, 0x6, 0x02D4, 0x1, 0), MX7ULP_PAD_PTC19__FB_A16 = IOMUX_PAD(0x004C, 0x004C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC19__USB1_ULPI_PWR2 = IOMUX_PAD(0x004C, 0x004C, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC19__USB0_ID = IOMUX_PAD(0x004C, 0x004C, 0xa, 0x0338, 0x3, 0), + MX7ULP_PAD_PTC19__USB1_PWR2 = IOMUX_PAD(0x004C, 0x004C, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC19__VIU_DE = IOMUX_PAD(0x004C, 0x004C, 0xc, 0x033c, 0x3, 0), MX7ULP_PAD_PTD0__PTD0 = IOMUX_PAD(0x0080, 0x0080, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD0__SDHC0_RESET_b = IOMUX_PAD(0x0080, 0x0080, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD0__DEBUG_MUX18 = IOMUX_PAD(0x0080, 0x0080, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD0__SDHC0_RESET_B = IOMUX_PAD(0x0080, 0x0080, 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTD1__PTD1 = IOMUX_PAD(0x0084, 0x0084, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD1__SDHC0_CMD = IOMUX_PAD(0x0084, 0x0084, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD1__DEBUG_MUX19 = IOMUX_PAD(0x0084, 0x0084, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD2__PTD2 = IOMUX_PAD(0x0088, 0x0088, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD2__SDHC0_CLK = IOMUX_PAD(0x0088, 0x0088, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD2__DEBUG_MUX20 = IOMUX_PAD(0x0088, 0x0088, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD3__PTD3 = IOMUX_PAD(0x008C, 0x008C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD3__SDHC0_D7 = IOMUX_PAD(0x008C, 0x008C, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD3__DEBUG_MUX21 = IOMUX_PAD(0x008C, 0x008C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD4__PTD4 = IOMUX_PAD(0x0090, 0x0090, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD4__SDHC0_D6 = IOMUX_PAD(0x0090, 0x0090, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD4__DEBUG_MUX22 = IOMUX_PAD(0x0090, 0x0090, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD5__PTD5 = IOMUX_PAD(0x0094, 0x0094, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD5__SDHC0_D5 = IOMUX_PAD(0x0094, 0x0094, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD5__DEBUG_MUX23 = IOMUX_PAD(0x0094, 0x0094, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD6__PTD6 = IOMUX_PAD(0x0098, 0x0098, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD6__SDHC0_D4 = IOMUX_PAD(0x0098, 0x0098, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD6__DEBUG_MUX24 = IOMUX_PAD(0x0098, 0x0098, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD7__PTD7 = IOMUX_PAD(0x009C, 0x009C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD7__SDHC0_D3 = IOMUX_PAD(0x009C, 0x009C, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD7__DEBUG_MUX25 = IOMUX_PAD(0x009C, 0x009C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD8__PTD8 = IOMUX_PAD(0x00A0, 0x00A0, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD8__TPM4_CLKIN = IOMUX_PAD(0x00A0, 0x00A0, 0x6, 0x0298, 0x2, 0), MX7ULP_PAD_PTD8__SDHC0_D2 = IOMUX_PAD(0x00A0, 0x00A0, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD8__DEBUG_MUX26 = IOMUX_PAD(0x00A0, 0x00A0, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD9__PTD9 = IOMUX_PAD(0x00A4, 0x00A4, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD9__TPM4_CH0 = IOMUX_PAD(0x00A4, 0x00A4, 0x6, 0x0280, 0x2, 0), MX7ULP_PAD_PTD9__SDHC0_D1 = IOMUX_PAD(0x00A4, 0x00A4, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD9__DEBUG_MUX27 = IOMUX_PAD(0x00A4, 0x00A4, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD10__PTD10 = IOMUX_PAD(0x00A8, 0x00A8, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD10__TPM4_CH1 = IOMUX_PAD(0x00A8, 0x00A8, 0x6, 0x0284, 0x2, 0), MX7ULP_PAD_PTD10__SDHC0_D0 = IOMUX_PAD(0x00A8, 0x00A8, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD10__DEBUG_MUX28 = IOMUX_PAD(0x00A8, 0x00A8, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD11__PTD11 = IOMUX_PAD(0x00AC, 0x00AC, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD11__TPM4_CH2 = IOMUX_PAD(0x00AC, 0x00AC, 0x6, 0x0288, 0x2, 0), MX7ULP_PAD_PTD11__SDHC0_DQS = IOMUX_PAD(0x00AC, 0x00AC, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD11__DEBUG_MUX29 = IOMUX_PAD(0x00AC, 0x00AC, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTE0__PTE0 = IOMUX_PAD(0x0100, 0x0100, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE0__FXIO1_D31 = IOMUX_PAD(0x0100, 0x0100, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE0__LPSPI2_PCS1 = IOMUX_PAD(0x0100, 0x0100, 0x3, 0x02A0, 0x2, 0), - MX7ULP_PAD_PTE0__LPUART4_CTS_b = IOMUX_PAD(0x0100, 0x0100, 0x4, 0x0244, 0x2, 0), + MX7ULP_PAD_PTE0__LPUART4_CTS_B = IOMUX_PAD(0x0100, 0x0100, 0x4, 0x0244, 0x2, 0), MX7ULP_PAD_PTE0__LPI2C4_SCL = IOMUX_PAD(0x0100, 0x0100, 0x5, 0x0278, 0x2, 0), MX7ULP_PAD_PTE0__SDHC1_D1 = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTE0__FB_A25 = IOMUX_PAD(0x0100, 0x0100, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE0__DEBUG_MUX30 = IOMUX_PAD(0x0100, 0x0100, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTE1__PTE1 = IOMUX_PAD(0x0104, 0x0104, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE1__FXIO1_D30 = IOMUX_PAD(0x0104, 0x0104, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE1__LPSPI2_PCS2 = IOMUX_PAD(0x0104, 0x0104, 0x3, 0x02A4, 0x2, 0), - MX7ULP_PAD_PTE1__LPUART4_RTS_b = IOMUX_PAD(0x0104, 0x0104, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__LPUART4_RTS_B = IOMUX_PAD(0x0104, 0x0104, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTE1__LPI2C4_SDA = IOMUX_PAD(0x0104, 0x0104, 0x5, 0x027C, 0x2, 0), MX7ULP_PAD_PTE1__SDHC1_D0 = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTE1__FB_A26 = IOMUX_PAD(0x0104, 0x0104, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE1__DEBUG_MUX31 = IOMUX_PAD(0x0104, 0x0104, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTE2__PTE2 = IOMUX_PAD(0x0108, 0x0108, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE2__FXIO1_D29 = IOMUX_PAD(0x0108, 0x0108, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE2__LPSPI2_PCS3 = IOMUX_PAD(0x0108, 0x0108, 0x3, 0x02A8, 0x2, 0), MX7ULP_PAD_PTE2__LPUART4_TX = IOMUX_PAD(0x0108, 0x0108, 0x4, 0x024C, 0x2, 0), MX7ULP_PAD_PTE2__LPI2C4_HREQ = IOMUX_PAD(0x0108, 0x0108, 0x5, 0x0274, 0x2, 0), MX7ULP_PAD_PTE2__SDHC1_CLK = IOMUX_PAD(0x0108, 0x0108, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE2__DEBUG_MUX32 = IOMUX_PAD(0x0108, 0x0108, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTE3__PTE3 = IOMUX_PAD(0x010C, 0x010C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE3__FXIO1_D28 = IOMUX_PAD(0x010C, 0x010C, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE3__LPUART4_RX = IOMUX_PAD(0x010C, 0x010C, 0x4, 0x0248, 0x2, 0), MX7ULP_PAD_PTE3__TPM5_CH1 = IOMUX_PAD(0x010C, 0x010C, 0x6, 0x02C8, 0x2, 0), MX7ULP_PAD_PTE3__SDHC1_CMD = IOMUX_PAD(0x010C, 0x010C, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE3__DEBUG_MUX33 = IOMUX_PAD(0x010C, 0x010C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTE4__PTE4 = IOMUX_PAD(0x0110, 0x0110, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE4__FXIO1_D27 = IOMUX_PAD(0x0110, 0x0110, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE4__LPSPI2_SIN = IOMUX_PAD(0x0110, 0x0110, 0x3, 0x02B0, 0x2, 0), - MX7ULP_PAD_PTE4__LPUART5_CTS_b = IOMUX_PAD(0x0110, 0x0110, 0x4, 0x0250, 0x2, 0), + MX7ULP_PAD_PTE4__LPUART5_CTS_B = IOMUX_PAD(0x0110, 0x0110, 0x4, 0x0250, 0x2, 0), MX7ULP_PAD_PTE4__LPI2C5_SCL = IOMUX_PAD(0x0110, 0x0110, 0x5, 0x02BC, 0x2, 0), MX7ULP_PAD_PTE4__TPM5_CLKIN = IOMUX_PAD(0x0110, 0x0110, 0x6, 0x02CC, 0x2, 0), MX7ULP_PAD_PTE4__SDHC1_D3 = IOMUX_PAD(0x0110, 0x0110, 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTE5__PTE5 = IOMUX_PAD(0x0114, 0x0114, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE5__FXIO1_D26 = IOMUX_PAD(0x0114, 0x0114, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE5__LPSPI2_SOUT = IOMUX_PAD(0x0114, 0x0114, 0x3, 0x02B4, 0x2, 0), - MX7ULP_PAD_PTE5__LPUART5_RTS_b = IOMUX_PAD(0x0114, 0x0114, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__LPUART5_RTS_B = IOMUX_PAD(0x0114, 0x0114, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTE5__LPI2C5_SDA = IOMUX_PAD(0x0114, 0x0114, 0x5, 0x02C0, 0x2, 0), MX7ULP_PAD_PTE5__TPM5_CH0 = IOMUX_PAD(0x0114, 0x0114, 0x6, 0x02C4, 0x2, 0), MX7ULP_PAD_PTE5__SDHC1_D2 = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__VIU_DE = IOMUX_PAD(0x0114, 0x0114, 0xc, 0x033c, 0x2, 0), MX7ULP_PAD_PTE6__PTE6 = IOMUX_PAD(0x0118, 0x0118, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE6__FXIO1_D25 = IOMUX_PAD(0x0118, 0x0118, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE6__LPSPI2_SCK = IOMUX_PAD(0x0118, 0x0118, 0x3, 0x02AC, 0x2, 0), @@ -678,23 +655,23 @@ enum { MX7ULP_PAD_PTE8__VIU_D16 = IOMUX_PAD(0x0120, 0x0120, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTE8__FXIO1_D23 = IOMUX_PAD(0x0120, 0x0120, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE8__LPSPI3_PCS1 = IOMUX_PAD(0x0120, 0x0120, 0x3, 0x0314, 0x2, 0), - MX7ULP_PAD_PTE8__LPUART6_CTS_b = IOMUX_PAD(0x0120, 0x0120, 0x4, 0x025C, 0x2, 0), + MX7ULP_PAD_PTE8__LPUART6_CTS_B = IOMUX_PAD(0x0120, 0x0120, 0x4, 0x025C, 0x2, 0), MX7ULP_PAD_PTE8__LPI2C6_SCL = IOMUX_PAD(0x0120, 0x0120, 0x5, 0x02FC, 0x2, 0), MX7ULP_PAD_PTE8__TPM7_CH5 = IOMUX_PAD(0x0120, 0x0120, 0x6, 0x02F0, 0x2, 0), MX7ULP_PAD_PTE8__SDHC1_WP = IOMUX_PAD(0x0120, 0x0120, 0x7, 0x0200, 0x1, 0), MX7ULP_PAD_PTE8__SDHC1_D6 = IOMUX_PAD(0x0120, 0x0120, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE8__FB_CS3_b_FB_BE7_0_BLS31_24_b = IOMUX_PAD(0x0120, 0x0120, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B = IOMUX_PAD(0x0120, 0x0120, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__PTE9 = IOMUX_PAD(0x0124, 0x0124, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__TRACE_D5 = IOMUX_PAD(0x0124, 0x0124, 0xa, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__VIU_D17 = IOMUX_PAD(0x0124, 0x0124, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__FXIO1_D22 = IOMUX_PAD(0x0124, 0x0124, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__LPSPI3_PCS2 = IOMUX_PAD(0x0124, 0x0124, 0x3, 0x0318, 0x2, 0), - MX7ULP_PAD_PTE9__LPUART6_RTS_b = IOMUX_PAD(0x0124, 0x0124, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE9__LPUART6_RTS_B = IOMUX_PAD(0x0124, 0x0124, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__LPI2C6_SDA = IOMUX_PAD(0x0124, 0x0124, 0x5, 0x0300, 0x2, 0), MX7ULP_PAD_PTE9__TPM7_CLKIN = IOMUX_PAD(0x0124, 0x0124, 0x6, 0x02F4, 0x2, 0), MX7ULP_PAD_PTE9__SDHC1_CD = IOMUX_PAD(0x0124, 0x0124, 0x7, 0x032C, 0x1, 0), MX7ULP_PAD_PTE9__SDHC1_D7 = IOMUX_PAD(0x0124, 0x0124, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE9__FB_TBST_b_FB_CS2_b_FB_BE15_8_BLS23_16_b = IOMUX_PAD(0x0124, 0x0124, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B = IOMUX_PAD(0x0124, 0x0124, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTE10__PTE10 = IOMUX_PAD(0x0128, 0x0128, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE10__TRACE_D4 = IOMUX_PAD(0x0128, 0x0128, 0xa, 0x0000, 0x0, 0), MX7ULP_PAD_PTE10__VIU_D18 = IOMUX_PAD(0x0128, 0x0128, 0xc, 0x0000, 0x0, 0), @@ -712,29 +689,29 @@ enum { MX7ULP_PAD_PTE11__FXIO1_D20 = IOMUX_PAD(0x012C, 0x012C, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE11__LPUART6_RX = IOMUX_PAD(0x012C, 0x012C, 0x4, 0x0260, 0x2, 0), MX7ULP_PAD_PTE11__TPM7_CH1 = IOMUX_PAD(0x012C, 0x012C, 0x6, 0x02E0, 0x2, 0), - MX7ULP_PAD_PTE11__SDHC1_RESET_b = IOMUX_PAD(0x012C, 0x012C, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE11__SDHC1_RESET_B = IOMUX_PAD(0x012C, 0x012C, 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTE11__FB_A20 = IOMUX_PAD(0x012C, 0x012C, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTE12__PTE12 = IOMUX_PAD(0x0130, 0x0130, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE12__FXIO1_D19 = IOMUX_PAD(0x0130, 0x0130, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE12__LPSPI3_SIN = IOMUX_PAD(0x0130, 0x0130, 0x3, 0x0324, 0x2, 0), - MX7ULP_PAD_PTE12__LPUART7_CTS_b = IOMUX_PAD(0x0130, 0x0130, 0x4, 0x0268, 0x2, 0), + MX7ULP_PAD_PTE12__LPUART7_CTS_B = IOMUX_PAD(0x0130, 0x0130, 0x4, 0x0268, 0x2, 0), MX7ULP_PAD_PTE12__LPI2C7_SCL = IOMUX_PAD(0x0130, 0x0130, 0x5, 0x0308, 0x2, 0), MX7ULP_PAD_PTE12__TPM7_CH2 = IOMUX_PAD(0x0130, 0x0130, 0x6, 0x02E4, 0x2, 0), MX7ULP_PAD_PTE12__SDHC1_WP = IOMUX_PAD(0x0130, 0x0130, 0x8, 0x0200, 0x2, 0), MX7ULP_PAD_PTE12__FB_A21 = IOMUX_PAD(0x0130, 0x0130, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTE12__TRACE_D2 = IOMUX_PAD(0x0130, 0x0130, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE12__USB1_ULPI_OC2 = IOMUX_PAD(0x0130, 0x0130, 0xb, 0x0334, 0x2, 0), + MX7ULP_PAD_PTE12__USB1_OC2 = IOMUX_PAD(0x0130, 0x0130, 0xb, 0x0334, 0x2, 0), MX7ULP_PAD_PTE12__VIU_D20 = IOMUX_PAD(0x0130, 0x0130, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__PTE13 = IOMUX_PAD(0x0134, 0x0134, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__FXIO1_D18 = IOMUX_PAD(0x0134, 0x0134, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__LPSPI3_SOUT = IOMUX_PAD(0x0134, 0x0134, 0x3, 0x0328, 0x2, 0), - MX7ULP_PAD_PTE13__LPUART7_RTS_b = IOMUX_PAD(0x0134, 0x0134, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__LPUART7_RTS_B = IOMUX_PAD(0x0134, 0x0134, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__LPI2C7_SDA = IOMUX_PAD(0x0134, 0x0134, 0x5, 0x030C, 0x2, 0), MX7ULP_PAD_PTE13__TPM6_CLKIN = IOMUX_PAD(0x0134, 0x0134, 0x6, 0x02D8, 0x2, 0), MX7ULP_PAD_PTE13__SDHC1_CD = IOMUX_PAD(0x0134, 0x0134, 0x8, 0x032C, 0x2, 0), MX7ULP_PAD_PTE13__FB_A22 = IOMUX_PAD(0x0134, 0x0134, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__TRACE_D1 = IOMUX_PAD(0x0134, 0x0134, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE13__USB1_ULPI_PWR2 = IOMUX_PAD(0x0134, 0x0134, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__USB1_PWR2 = IOMUX_PAD(0x0134, 0x0134, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__VIU_D21 = IOMUX_PAD(0x0134, 0x0134, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTE14__PTE14 = IOMUX_PAD(0x0138, 0x0138, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE14__FXIO1_D17 = IOMUX_PAD(0x0138, 0x0138, 0x2, 0x0000, 0x0, 0), @@ -757,13 +734,13 @@ enum { MX7ULP_PAD_PTE15__USB0_PWR = IOMUX_PAD(0x013C, 0x013C, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTE15__VIU_D23 = IOMUX_PAD(0x013C, 0x013C, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF0__PTF0 = IOMUX_PAD(0x0180, 0x0180, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF0__LPUART4_CTS_b = IOMUX_PAD(0x0180, 0x0180, 0x4, 0x0244, 0x3, 0), + MX7ULP_PAD_PTF0__LPUART4_CTS_B = IOMUX_PAD(0x0180, 0x0180, 0x4, 0x0244, 0x3, 0), MX7ULP_PAD_PTF0__LPI2C4_SCL = IOMUX_PAD(0x0180, 0x0180, 0x5, 0x0278, 0x3, 0), MX7ULP_PAD_PTF0__TPM4_CLKIN = IOMUX_PAD(0x0180, 0x0180, 0x6, 0x0298, 0x3, 0), - MX7ULP_PAD_PTF0__FB_RW_b = IOMUX_PAD(0x0180, 0x0180, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF0__VIU_DE = IOMUX_PAD(0x0180, 0x0180, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF0__FB_RW_B = IOMUX_PAD(0x0180, 0x0180, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF0__VIU_DE = IOMUX_PAD(0x0180, 0x0180, 0xc, 0x033C, 0x0, 0), MX7ULP_PAD_PTF1__PTF1 = IOMUX_PAD(0x0184, 0x0184, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF1__LPUART4_RTS_b = IOMUX_PAD(0x0184, 0x0184, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF1__LPUART4_RTS_B = IOMUX_PAD(0x0184, 0x0184, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTF1__LPI2C4_SDA = IOMUX_PAD(0x0184, 0x0184, 0x5, 0x027C, 0x3, 0), MX7ULP_PAD_PTF1__TPM4_CH0 = IOMUX_PAD(0x0184, 0x0184, 0x6, 0x0280, 0x3, 0), MX7ULP_PAD_PTF1__CLKOUT = IOMUX_PAD(0x0184, 0x0184, 0x9, 0x0000, 0x0, 0), @@ -772,7 +749,7 @@ enum { MX7ULP_PAD_PTF2__LPUART4_TX = IOMUX_PAD(0x0188, 0x0188, 0x4, 0x024C, 0x3, 0), MX7ULP_PAD_PTF2__LPI2C4_HREQ = IOMUX_PAD(0x0188, 0x0188, 0x5, 0x0274, 0x3, 0), MX7ULP_PAD_PTF2__TPM4_CH1 = IOMUX_PAD(0x0188, 0x0188, 0x6, 0x0284, 0x3, 0), - MX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_b_FB_BE23_16_BLS15_8_b = IOMUX_PAD(0x0188, 0x0188, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B = IOMUX_PAD(0x0188, 0x0188, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTF2__VIU_VSYNC = IOMUX_PAD(0x0188, 0x0188, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF3__PTF3 = IOMUX_PAD(0x018C, 0x018C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF3__LPUART4_RX = IOMUX_PAD(0x018C, 0x018C, 0x4, 0x0248, 0x3, 0), @@ -782,7 +759,7 @@ enum { MX7ULP_PAD_PTF4__PTF4 = IOMUX_PAD(0x0190, 0x0190, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF4__FXIO1_D0 = IOMUX_PAD(0x0190, 0x0190, 0x2, 0x0204, 0x2, 0), MX7ULP_PAD_PTF4__LPSPI2_PCS1 = IOMUX_PAD(0x0190, 0x0190, 0x3, 0x02A0, 0x3, 0), - MX7ULP_PAD_PTF4__LPUART5_CTS_b = IOMUX_PAD(0x0190, 0x0190, 0x4, 0x0250, 0x3, 0), + MX7ULP_PAD_PTF4__LPUART5_CTS_B = IOMUX_PAD(0x0190, 0x0190, 0x4, 0x0250, 0x3, 0), MX7ULP_PAD_PTF4__LPI2C5_SCL = IOMUX_PAD(0x0190, 0x0190, 0x5, 0x02BC, 0x3, 0), MX7ULP_PAD_PTF4__TPM4_CH3 = IOMUX_PAD(0x0190, 0x0190, 0x6, 0x028C, 0x2, 0), MX7ULP_PAD_PTF4__FB_AD17 = IOMUX_PAD(0x0190, 0x0190, 0x9, 0x0000, 0x0, 0), @@ -790,7 +767,7 @@ enum { MX7ULP_PAD_PTF5__PTF5 = IOMUX_PAD(0x0194, 0x0194, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF5__FXIO1_D1 = IOMUX_PAD(0x0194, 0x0194, 0x2, 0x0208, 0x2, 0), MX7ULP_PAD_PTF5__LPSPI2_PCS2 = IOMUX_PAD(0x0194, 0x0194, 0x3, 0x02A4, 0x3, 0), - MX7ULP_PAD_PTF5__LPUART5_RTS_b = IOMUX_PAD(0x0194, 0x0194, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF5__LPUART5_RTS_B = IOMUX_PAD(0x0194, 0x0194, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTF5__LPI2C5_SDA = IOMUX_PAD(0x0194, 0x0194, 0x5, 0x02C0, 0x3, 0), MX7ULP_PAD_PTF5__TPM4_CH4 = IOMUX_PAD(0x0194, 0x0194, 0x6, 0x0290, 0x2, 0), MX7ULP_PAD_PTF5__FB_AD18 = IOMUX_PAD(0x0194, 0x0194, 0x9, 0x0000, 0x0, 0), @@ -812,20 +789,20 @@ enum { MX7ULP_PAD_PTF8__PTF8 = IOMUX_PAD(0x01A0, 0x01A0, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF8__FXIO1_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0x2, 0x0214, 0x2, 0), MX7ULP_PAD_PTF8__LPSPI2_SIN = IOMUX_PAD(0x01A0, 0x01A0, 0x3, 0x02B0, 0x3, 0), - MX7ULP_PAD_PTF8__LPUART6_CTS_b = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0), + MX7ULP_PAD_PTF8__LPUART6_CTS_B = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0), MX7ULP_PAD_PTF8__LPI2C6_SCL = IOMUX_PAD(0x01A0, 0x01A0, 0x5, 0x02FC, 0x3, 0), MX7ULP_PAD_PTF8__TPM5_CLKIN = IOMUX_PAD(0x01A0, 0x01A0, 0x6, 0x02CC, 0x3, 0), MX7ULP_PAD_PTF8__FB_AD21 = IOMUX_PAD(0x01A0, 0x01A0, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF8__USB1_ULPI_CLK = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF8__USB1_CLK = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF8__VIU_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF9__PTF9 = IOMUX_PAD(0x01A4, 0x01A4, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF9__FXIO1_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0x2, 0x0218, 0x2, 0), MX7ULP_PAD_PTF9__LPSPI2_SOUT = IOMUX_PAD(0x01A4, 0x01A4, 0x3, 0x02B4, 0x3, 0), - MX7ULP_PAD_PTF9__LPUART6_RTS_b = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__LPUART6_RTS_B = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTF9__LPI2C6_SDA = IOMUX_PAD(0x01A4, 0x01A4, 0x5, 0x0300, 0x3, 0), MX7ULP_PAD_PTF9__TPM5_CH0 = IOMUX_PAD(0x01A4, 0x01A4, 0x6, 0x02C4, 0x3, 0), MX7ULP_PAD_PTF9__FB_AD22 = IOMUX_PAD(0x01A4, 0x01A4, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__USB1_ULPI_NXT = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__USB1_NXT = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF9__VIU_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF10__PTF10 = IOMUX_PAD(0x01A8, 0x01A8, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF10__FXIO1_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0x2, 0x021C, 0x2, 0), @@ -834,33 +811,33 @@ enum { MX7ULP_PAD_PTF10__LPI2C6_HREQ = IOMUX_PAD(0x01A8, 0x01A8, 0x5, 0x02F8, 0x3, 0), MX7ULP_PAD_PTF10__TPM7_CH3 = IOMUX_PAD(0x01A8, 0x01A8, 0x6, 0x02E8, 0x3, 0), MX7ULP_PAD_PTF10__FB_AD23 = IOMUX_PAD(0x01A8, 0x01A8, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF10__USB1_ULPI_STP = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF10__USB1_STP = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF10__VIU_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF11__PTF11 = IOMUX_PAD(0x01AC, 0x01AC, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF11__FXIO1_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0x2, 0x0220, 0x2, 0), MX7ULP_PAD_PTF11__LPSPI2_PCS0 = IOMUX_PAD(0x01AC, 0x01AC, 0x3, 0x029C, 0x3, 0), MX7ULP_PAD_PTF11__LPUART6_RX = IOMUX_PAD(0x01AC, 0x01AC, 0x4, 0x0260, 0x3, 0), MX7ULP_PAD_PTF11__TPM7_CH4 = IOMUX_PAD(0x01AC, 0x01AC, 0x6, 0x02EC, 0x3, 0), - MX7ULP_PAD_PTF11__FB_CS4_b_FB_TSIZ0_FB_BE31_24_BLS7_0_b = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF11__USB1_ULPI_DIR = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__USB1_DIR = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF11__VIU_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF12__PTF12 = IOMUX_PAD(0x01B0, 0x01B0, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF12__FXIO1_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0x2, 0x0224, 0x2, 0), MX7ULP_PAD_PTF12__LPSPI3_PCS1 = IOMUX_PAD(0x01B0, 0x01B0, 0x3, 0x0314, 0x3, 0), - MX7ULP_PAD_PTF12__LPUART7_CTS_b = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0), + MX7ULP_PAD_PTF12__LPUART7_CTS_B = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0), MX7ULP_PAD_PTF12__LPI2C7_SCL = IOMUX_PAD(0x01B0, 0x01B0, 0x5, 0x0308, 0x3, 0), MX7ULP_PAD_PTF12__TPM7_CH5 = IOMUX_PAD(0x01B0, 0x01B0, 0x6, 0x02F0, 0x3, 0), MX7ULP_PAD_PTF12__FB_AD24 = IOMUX_PAD(0x01B0, 0x01B0, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF12__USB1_ULPI_DATA0 = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF12__USB1_DATA0 = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF12__VIU_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF13__PTF13 = IOMUX_PAD(0x01B4, 0x01B4, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF13__FXIO1_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0x2, 0x0228, 0x2, 0), MX7ULP_PAD_PTF13__LPSPI3_PCS2 = IOMUX_PAD(0x01B4, 0x01B4, 0x3, 0x0318, 0x3, 0), - MX7ULP_PAD_PTF13__LPUART7_RTS_b = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__LPUART7_RTS_B = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTF13__LPI2C7_SDA = IOMUX_PAD(0x01B4, 0x01B4, 0x5, 0x030C, 0x3, 0), MX7ULP_PAD_PTF13__TPM7_CLKIN = IOMUX_PAD(0x01B4, 0x01B4, 0x6, 0x02F4, 0x3, 0), MX7ULP_PAD_PTF13__FB_AD25 = IOMUX_PAD(0x01B4, 0x01B4, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__USB1_ULPI_DATA1 = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__USB1_DATA1 = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF13__VIU_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF14__PTF14 = IOMUX_PAD(0x01B8, 0x01B8, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF14__FXIO1_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0x2, 0x022C, 0x2, 0), @@ -869,38 +846,38 @@ enum { MX7ULP_PAD_PTF14__LPI2C7_HREQ = IOMUX_PAD(0x01B8, 0x01B8, 0x5, 0x0304, 0x3, 0), MX7ULP_PAD_PTF14__TPM7_CH0 = IOMUX_PAD(0x01B8, 0x01B8, 0x6, 0x02DC, 0x3, 0), MX7ULP_PAD_PTF14__FB_AD26 = IOMUX_PAD(0x01B8, 0x01B8, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF14__USB1_ULPI_DATA2 = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF14__USB1_DATA2 = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF14__VIU_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF15__PTF15 = IOMUX_PAD(0x01BC, 0x01BC, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF15__FXIO1_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0x2, 0x0230, 0x2, 0), MX7ULP_PAD_PTF15__LPUART7_RX = IOMUX_PAD(0x01BC, 0x01BC, 0x4, 0x026C, 0x3, 0), MX7ULP_PAD_PTF15__TPM7_CH1 = IOMUX_PAD(0x01BC, 0x01BC, 0x6, 0x02E0, 0x3, 0), MX7ULP_PAD_PTF15__FB_AD27 = IOMUX_PAD(0x01BC, 0x01BC, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF15__USB1_ULPI_DATA3 = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF15__USB1_DATA3 = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF15__VIU_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF16__PTF16 = IOMUX_PAD(0x01C0, 0x01C0, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF16__USB1_ULPI_DATA4 = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF16__USB1_DATA4 = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF16__VIU_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF16__FXIO1_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0x2, 0x0234, 0x2, 0), MX7ULP_PAD_PTF16__LPSPI3_SIN = IOMUX_PAD(0x01C0, 0x01C0, 0x3, 0x0324, 0x3, 0), MX7ULP_PAD_PTF16__TPM7_CH2 = IOMUX_PAD(0x01C0, 0x01C0, 0x6, 0x02E4, 0x3, 0), MX7ULP_PAD_PTF16__FB_AD28 = IOMUX_PAD(0x01C0, 0x01C0, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTF17__PTF17 = IOMUX_PAD(0x01C4, 0x01C4, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF17__USB1_ULPI_DATA5 = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF17__USB1_DATA5 = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF17__VIU_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF17__FXIO1_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0x2, 0x0238, 0x2, 0), MX7ULP_PAD_PTF17__LPSPI3_SOUT = IOMUX_PAD(0x01C4, 0x01C4, 0x3, 0x0328, 0x3, 0), MX7ULP_PAD_PTF17__TPM6_CLKIN = IOMUX_PAD(0x01C4, 0x01C4, 0x6, 0x02D8, 0x3, 0), MX7ULP_PAD_PTF17__FB_AD29 = IOMUX_PAD(0x01C4, 0x01C4, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTF18__PTF18 = IOMUX_PAD(0x01C8, 0x01C8, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF18__USB1_ULPI_DATA6 = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF18__USB1_DATA6 = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF18__VIU_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF18__FXIO1_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0x2, 0x023C, 0x2, 0), MX7ULP_PAD_PTF18__LPSPI3_SCK = IOMUX_PAD(0x01C8, 0x01C8, 0x3, 0x0320, 0x3, 0), MX7ULP_PAD_PTF18__TPM6_CH0 = IOMUX_PAD(0x01C8, 0x01C8, 0x6, 0x02D0, 0x3, 0), MX7ULP_PAD_PTF18__FB_AD30 = IOMUX_PAD(0x01C8, 0x01C8, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTF19__PTF19 = IOMUX_PAD(0x01CC, 0x01CC, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF19__USB1_ULPI_DATA7 = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF19__USB1_DATA7 = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF19__VIU_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF19__FXIO1_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0x2, 0x0240, 0x2, 0), MX7ULP_PAD_PTF19__LPSPI3_PCS0 = IOMUX_PAD(0x01CC, 0x01CC, 0x3, 0x0310, 0x3, 0), diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S new file mode 100644 index 00000000000..1bf1abf6482 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 +#define ROM_VERSION_OFFSET 0x80 +#define ROM_API_HWCNFG_SETUP_OFFSET 0x08 + +plugin_start: + + push {r0-r4, lr} + + imx7ulp_ddr_setting + imx7ulp_clock_gating + imx7ulp_qos_setting + +normal_boot: + +/* + * The following is to fill in those arguments for this ROM function + * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data) + * This function is used to copy data from the storage media into DDR. + * start - Initial (possibly partial) image load address on entry. + * Final image load address on exit. + * bytes - Initial (possibly partial) image size on entry. + * Final image size on exit. + * boot_data - Initial @ref ivt Boot Data load address. + */ + adr r0, boot_data2 + adr r1, image_len2 + adr r2, boot_data2 + +/* + * check the _pu_irom_api_table for the address + */ +before_calling_rom___pu_irom_hwcnfg_setup: + ldr r3, =ROM_VERSION_OFFSET + ldr r4, [r3] + ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY + ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] + blx r4 +after_calling_rom___pu_irom_hwcnfg_setup: + + +/* To return to ROM from plugin, we need to fill in these argument. + * Here is what need to do: + * Need to construct the paramters for this function before return to ROM: + * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset) + */ + pop {r0-r4, lr} + push {r5} + ldr r5, boot_data2 + str r5, [r0] + ldr r5, image_len2 + str r5, [r1] + ldr r5, second_ivt_offset + str r5, [r2] + mov r0, #1 + pop {r5} + + /* return back to ROM code */ + bx lr + +/* make the following data right in the end of the output*/ +.ltorg + +#define FLASH_OFFSET 0x400 + +/* + * second_ivt_offset is the offset from the "second_ivt_header" to + * "image_copy_start", which involves FLASH_OFFSET, plus the first + * ivt_header, the plugin code size itself recorded by "ivt2_header" + */ + +second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET) + +/* + * The following is the second IVT header plus the second boot data + */ +ivt2_header: .long 0x0 +app2_code_jump_v: .long 0x0 +reserv3: .long 0x0 +dcd2_ptr: .long 0x0 +boot_data2_ptr: .long 0x0 +self_ptr2: .long 0x0 +app_code_csf2: .long 0x0 +reserv4: .long 0x0 +boot_data2: .long 0x0 +image_len2: .long 0x0 +plugin2: .long 0x0 diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h index 8a571755f86..fd0f9335e7d 100644 --- a/arch/arm/include/asm/arch-mx7ulp/pcc.h +++ b/arch/arm/include/asm/arch-mx7ulp/pcc.h @@ -290,10 +290,10 @@ enum pcc3_entry { #define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET) #define PCC_PCS_OFFSET 24 #define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET) -#define PCC_FRAC_OFFSET 4 +#define PCC_FRAC_OFFSET 3 #define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET) #define PCC_PCD_OFFSET 0 -#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET) +#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET) enum pcc_clksrc_type { diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h index 06a6e9f4f9c..bf1005dd4e1 100644 --- a/arch/arm/include/asm/arch-mx7ulp/scg.h +++ b/arch/arm/include/asm/arch-mx7ulp/scg.h @@ -326,6 +326,7 @@ typedef struct scg_regs { u32 scg_clk_get_rate(enum scg_clk clk); int scg_enable_pll_pfd(enum scg_clk clk, u32 frac); +int scg_disable_pll_pfd(enum scg_clk clk); int scg_enable_usb_pll(bool usb_control); u32 decode_pll(enum pll_clocks pll); @@ -338,5 +339,6 @@ void scg_a7_nicclk_init(void); void scg_a7_sys_clk_sel(enum scg_sys_src clk); void scg_a7_info(void); void scg_a7_soscdiv_init(void); +void scg_a7_init_core_clk(void); #endif diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h index d53bfcc12a5..9a2a4943248 100644 --- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h @@ -18,4 +18,5 @@ enum bt_mode { SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ }; +enum boot_device get_boot_device(void); #endif diff --git a/arch/arm/include/asm/arch-mx8m/ddr.h b/arch/arm/include/asm/arch-mx8m/ddr.h deleted file mode 100644 index b37382eab0e..00000000000 --- a/arch/arm/include/asm/arch-mx8m/ddr.h +++ /dev/null @@ -1,356 +0,0 @@ -/* - * Copyright 2017 NXP - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MX8M_DDR_H -#define __ASM_ARCH_MX8M_DDR_H - -#define DDRC_DDR_SS_GPR0 0x3d000000 -#define DDRC_IPS_BASE_ADDR_0 0x3f400000 -#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) -#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) - -struct ddrc_freq { - u32 res0[8]; - u32 derateen; - u32 derateint; - u32 res1[10]; - u32 rfshctl0; - u32 res2[4]; - u32 rfshtmg; - u32 rfshtmg1; - u32 res3[28]; - u32 init3; - u32 init4; - u32 res; - u32 init6; - u32 init7; - u32 res4[4]; - u32 dramtmg0; - u32 dramtmg1; - u32 dramtmg2; - u32 dramtmg3; - u32 dramtmg4; - u32 dramtmg5; - u32 dramtmg6; - u32 dramtmg7; - u32 dramtmg8; - u32 dramtmg9; - u32 dramtmg10; - u32 dramtmg11; - u32 dramtmg12; - u32 dramtmg13; - u32 dramtmg14; - u32 dramtmg15; - u32 dramtmg16; - u32 dramtmg17; - u32 res5[10]; - u32 mramtmg0; - u32 mramtmg1; - u32 mramtmg4; - u32 mramtmg9; - u32 zqctl0; - u32 res6[3]; - u32 dfitmg0; - u32 dfitmg1; - u32 res7[7]; - u32 dfitmg2; - u32 dfitmg3; - u32 res8[33]; - u32 odtcfg; -}; - -struct imx8m_ddrc_regs { - u32 mstr; - u32 stat; - u32 mstr1; - u32 res1; - u32 mrctrl0; - u32 mrctrl1; - u32 mrstat; - u32 mrctrl2; - u32 derateen; - u32 derateint; - u32 mstr2; - u32 res2; - u32 pwrctl; - u32 pwrtmg; - u32 hwlpctl; - u32 hwffcctl; - u32 hwffcstat; - u32 res3[3]; - u32 rfshctl0; - u32 rfshctl1; - u32 rfshctl2; - u32 rfshctl4; - u32 rfshctl3; - u32 rfshtmg; - u32 rfshtmg1; - u32 res4; - u32 ecccfg0; - u32 ecccfg1; - u32 eccstat; - u32 eccclr; - u32 eccerrcnt; - u32 ecccaddr0; - u32 ecccaddr1; - u32 ecccsyn0; - u32 ecccsyn1; - u32 ecccsyn2; - u32 eccbitmask0; - u32 eccbitmask1; - u32 eccbitmask2; - u32 eccuaddr0; - u32 eccuaddr1; - u32 eccusyn0; - u32 eccusyn1; - u32 eccusyn2; - u32 eccpoisonaddr0; - u32 eccpoisonaddr1; - u32 crcparctl0; - u32 crcparctl1; - u32 crcparctl2; - u32 crcparstat; - u32 init0; - u32 init1; - u32 init2; - u32 init3; - u32 init4; - u32 init5; - u32 init6; - u32 init7; - u32 dimmctl; - u32 rankctl; - u32 res5; - u32 chctl; - u32 dramtmg0; - u32 dramtmg1; - u32 dramtmg2; - u32 dramtmg3; - u32 dramtmg4; - u32 dramtmg5; - u32 dramtmg6; - u32 dramtmg7; - u32 dramtmg8; - u32 dramtmg9; - u32 dramtmg10; - u32 dramtmg11; - u32 dramtmg12; - u32 dramtmg13; - u32 dramtmg14; - u32 dramtmg15; - u32 dramtmg16; - u32 dramtmg17; - u32 res6[10]; - u32 mramtmg0; - u32 mramtmg1; - u32 mramtmg4; - u32 mramtmg9; - u32 zqctl0; - u32 zqctl1; - u32 zqctl2; - u32 zqstat; - u32 dfitmg0; - u32 dfitmg1; - u32 dfilpcfg0; - u32 dfilpcfg1; - u32 dfiupd0; - u32 dfiupd1; - u32 dfiupd2; - u32 res7; - u32 dfimisc; - u32 dfitmg2; - u32 dfitmg3; - u32 dfistat; - u32 dbictl; - u32 dfiphymstr; - u32 res8[14]; - u32 addrmap0; - u32 addrmap1; - u32 addrmap2; - u32 addrmap3; - u32 addrmap4; - u32 addrmap5; - u32 addrmap6; - u32 addrmap7; - u32 addrmap8; - u32 addrmap9; - u32 addrmap10; - u32 addrmap11; - u32 res9[4]; - u32 odtcfg; - u32 odtmap; - u32 res10[2]; - u32 sched; - u32 sched1; - u32 sched2; - u32 perfhpr1; - u32 res11; - u32 perflpr1; - u32 res12; - u32 perfwr1; - u32 res13[4]; - u32 dqmap0; - u32 dqmap1; - u32 dqmap2; - u32 dqmap3; - u32 dqmap4; - u32 dqmap5; - u32 res14[26]; - u32 dbg0; - u32 dbg1; - u32 dbgcam; - u32 dbgcmd; - u32 dbgstat; - u32 res15[3]; - u32 swctl; - u32 swstat; - u32 res16[2]; - u32 ocparcfg0; - u32 ocparcfg1; - u32 ocparcfg2; - u32 ocparcfg3; - u32 ocparstat0; - u32 ocparstat1; - u32 ocparwlog0; - u32 ocparwlog1; - u32 ocparwlog2; - u32 ocparawlog0; - u32 ocparawlog1; - u32 ocparrlog0; - u32 ocparrlog1; - u32 ocpararlog0; - u32 ocpararlog1; - u32 poisoncfg; - u32 poisonstat; - u32 adveccindex; - union { - u32 adveccstat; - u32 eccapstat; - }; - u32 eccpoisonpat0; - u32 eccpoisonpat1; - u32 eccpoisonpat2; - u32 res17[6]; - u32 caparpoisonctl; - u32 caparpoisonstat; - u32 res18[2]; - u32 dynbsmstat; - u32 res19[18]; - u32 pstat; - u32 pccfg; - struct { - u32 pcfgr; - u32 pcfgw; - u32 pcfgc; - struct { - u32 pcfgidmaskch0; - u32 pcfidvaluech0; - } pcfgid[16]; - u32 pctrl; - u32 pcfgqos0; - u32 pcfgqos1; - u32 pcfgwqos0; - u32 pcfgwqos1; - u32 res[4]; - } pcfg[16]; - struct { - u32 sarbase; - u32 sarsize; - } sar[4]; - u32 sbrctl; - u32 sbrstat; - u32 sbrwdata0; - u32 sbrwdata1; - u32 pdch; - u32 res20[755]; - /* umctl2_regs_dch1 */ - u32 ch1_stat; - u32 res21[2]; - u32 ch1_mrctrl0; - u32 ch1_mrctrl1; - u32 ch1_mrstat; - u32 ch1_mrctrl2; - u32 res22[4]; - u32 ch1_pwrctl; - u32 ch1_pwrtmg; - u32 ch1_hwlpctl; - u32 res23[15]; - u32 ch1_eccstat; - u32 ch1_eccclr; - u32 ch1_eccerrcnt; - u32 ch1_ecccaddr0; - u32 ch1_ecccaddr1; - u32 ch1_ecccsyn0; - u32 ch1_ecccsyn1; - u32 ch1_ecccsyn2; - u32 ch1_eccbitmask0; - u32 ch1_eccbitmask1; - u32 ch1_eccbitmask2; - u32 ch1_eccuaddr0; - u32 ch1_eccuaddr1; - u32 ch1_eccusyn0; - u32 ch1_eccusyn1; - u32 ch1_eccusyn2; - u32 res24[2]; - u32 ch1_crcparctl0; - u32 res25[2]; - u32 ch1_crcparstat; - u32 res26[46]; - u32 ch1_zqctl2; - u32 ch1_zqstat; - u32 res27[11]; - u32 ch1_dfistat; - u32 res28[33]; - u32 ch1_odtmap; - u32 res29[47]; - u32 ch1_dbg1; - u32 ch1_dbgcam; - u32 ch1_dbgcmd; - u32 ch1_dbgstat; - u32 res30[123]; - /* umctl2_regs_freq1 */ - struct ddrc_freq freq1; - u32 res31[109]; - /* umctl2_regs_addrmap_alt */ - u32 addrmap0_alt; - u32 addrmap1_alt; - u32 addrmap2_alt; - u32 addrmap3_alt; - u32 addrmap4_alt; - u32 addrmap5_alt; - u32 addrmap6_alt; - u32 addrmap7_alt; - u32 addrmap8_alt; - u32 addrmap9_alt; - u32 addrmap10_alt; - u32 addrmap11_alt; - u32 res32[758]; - /* umctl2_regs_freq2 */ - struct ddrc_freq freq2; - u32 res33[879]; - /* umctl2_regs_freq3 */ - struct ddrc_freq freq3; -}; - -struct imx8m_ddrphy_regs { - u32 reg[0xf0000]; -}; - -/* PHY State */ -enum pstate { - PS0, - PS1, - PS2, - PS3, -}; - -enum msg_response { - TRAIN_SUCCESS = 0x7, - TRAIN_STREAM_START = 0x8, - TRAIN_FAIL = 0xff, -}; - -#endif diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 287466800e4..4f2ac95f73c 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -14,7 +14,7 @@ static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) { - *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN)); return (void *)*handle; } diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 3cc0e5fa34a..4d1dac7489e 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -75,6 +75,10 @@ struct arch_global_data { #if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) unsigned long mem2_clk; #endif + +#ifdef CONFIG_HAVE_SC_FIRMWARE + uint64_t ipc_channel_handle; +#endif }; #include diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h b/arch/arm/include/asm/mach-imx/boot_mode.h index 300868a45e6..fd28506bca5 100644 --- a/arch/arm/include/asm/mach-imx/boot_mode.h +++ b/arch/arm/include/asm/mach-imx/boot_mode.h @@ -26,6 +26,7 @@ enum boot_device { MMC4_BOOT, NAND_BOOT, QSPI_BOOT, + FLEXSPI_BOOT, USB_BOOT, UNKNOWN_BOOT, BOOT_DEV_NUM = UNKNOWN_BOOT, diff --git a/arch/arm/include/asm/mach-imx/dma.h b/arch/arm/include/asm/mach-imx/dma.h index 0244947b6e0..6cd8db78831 100644 --- a/arch/arm/include/asm/mach-imx/dma.h +++ b/arch/arm/include/asm/mach-imx/dma.h @@ -6,6 +6,7 @@ * * Based on code from LTIB: * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -54,7 +55,7 @@ enum { MXS_DMA_CHANNEL_AHB_APBH_RESERVED1, MXS_MAX_DMA_CHANNELS, }; -#elif defined(CONFIG_MX6) || defined(CONFIG_MX7) +#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) enum { MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0, MXS_DMA_CHANNEL_AHB_APBH_GPMI1, @@ -96,13 +97,13 @@ enum { #define MXS_DMA_DESC_BYTES_OFFSET 16 struct mxs_dma_cmd { - unsigned long next; - unsigned long data; + uint32_t next; + uint32_t data; union { - dma_addr_t address; - unsigned long alternate; + uint32_t address; + uint32_t alternate; }; - unsigned long pio_words[DMA_PIO_WORDS]; + uint32_t pio_words[DMA_PIO_WORDS]; }; /* @@ -118,7 +119,7 @@ struct mxs_dma_cmd { struct mxs_dma_desc { struct mxs_dma_cmd cmd; unsigned int flags; - dma_addr_t address; + uint32_t address; void *buffer; struct list_head node; } __aligned(MXS_DMA_ALIGNMENT); diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index ce9a44dacda..d8392bd5f15 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -19,8 +19,6 @@ */ #define IVT_HEADER_MAGIC 0xD1 #define IVT_TOTAL_LENGTH 0x20 -#define IVT_HEADER_V1 0x40 -#define IVT_HEADER_V2 0x41 struct __packed ivt_header { uint8_t magic; @@ -45,6 +43,15 @@ struct __packed hab_hdr { u8 par; /* Parameters field */ }; +/* Default event structure */ +struct __packed evt_def { + struct hab_hdr hdr; /* Header */ + uint32_t sts; /* Status */ + uint32_t ctx; /* Default context */ + uint8_t *data; /* Default data location */ + size_t bytes; /* Size of default data */ +}; + /* -------- start of HAB API updates ------------*/ /* The following are taken from HAB4 SIS */ @@ -166,6 +173,22 @@ typedef void hapi_clock_init_t(void); #define HAB_ENG_RTL 0x77 /* RTL simulation engine */ #define HAB_ENG_SW 0xff /* Software engine */ +#ifdef CONFIG_ARM64 +#ifdef CONFIG_IMX8MQ +#define HAB_RVT_BASE 0x00000880 +#else +#define HAB_RVT_BASE 0x00000900 +#endif + +#define HAB_RVT_ENTRY (*(ulong *)(HAB_RVT_BASE + 0x08)) +#define HAB_RVT_EXIT (*(ulong *)(HAB_RVT_BASE + 0x10)) +#define HAB_RVT_CHECK_TARGET (*(ulong *)(HAB_RVT_BASE + 0x18)) +#define HAB_RVT_AUTHENTICATE_IMAGE (*(ulong *)(HAB_RVT_BASE + 0x20)) +#define HAB_RVT_REPORT_EVENT (*(ulong *)(HAB_RVT_BASE + 0x40)) +#define HAB_RVT_REPORT_STATUS (*(ulong *)(HAB_RVT_BASE + 0x48)) +#define HAB_RVT_FAILSAFE (*(ulong *)(HAB_RVT_BASE + 0x50)) +#else + #ifdef CONFIG_ROM_UNIFIED_SECTIONS #define HAB_RVT_BASE 0x00000100 #else @@ -173,7 +196,7 @@ typedef void hapi_clock_init_t(void); #define HAB_RVT_BASE_OLD 0x00000094 #define HAB_RVT_BASE ((is_mx6dqp()) ? \ HAB_RVT_BASE_NEW : \ - (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_3)) ? \ HAB_RVT_BASE_NEW : \ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ HAB_RVT_BASE_NEW : HAB_RVT_BASE_OLD) @@ -187,6 +210,8 @@ typedef void hapi_clock_init_t(void); #define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24)) #define HAB_RVT_FAILSAFE (*(uint32_t *)(HAB_RVT_BASE + 0x28)) +#endif /*CONFIG_ARM64*/ + #define HAB_CID_ROM 0 /**< ROM Caller ID */ #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ @@ -199,6 +224,12 @@ typedef void hapi_clock_init_t(void); #define IVT_SIZE 0x20 #define CSF_PAD_SIZE 0x2000 +#define HAB_TAG_EVT 0xDB +#define HAB_TAG_EVT_DEF 0x0C + +#define HAB_MAJ_VER 0x40 +#define HAB_MAJ_MASK 0xF0 + /* ----------- end of HAB API updates ------------*/ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, diff --git a/arch/arm/include/asm/mach-imx/imx_vservice.h b/arch/arm/include/asm/mach-imx/imx_vservice.h new file mode 100644 index 00000000000..baedab96441 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/imx_vservice.h @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + */ + +#ifndef __IMX_VSERVICE_H__ +#define __IMX_VSERVICE_H__ + +#include +#include +#include + +struct imx_vservice_channel +{ + u32 msg_seq; + struct udevice *mu_dev; + struct list_head channel_head; +}; + +void * imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size); +int imx_vservice_blocking_request(struct imx_vservice_channel *node, u8 *buf, u32* size); +struct imx_vservice_channel * imx_vservice_setup(struct udevice *virt_dev); + +#endif diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 0c0ccf44037..34f2af4838f 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -4,6 +4,7 @@ * * * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -87,7 +88,7 @@ typedef u64 iomux_v3_cfg_t; #define IOMUX_CONFIG_LPSR 0x20 #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M #define PAD_CTL_DSE0 (0x0 << 0) #define PAD_CTL_DSE1 (0x1 << 0) #define PAD_CTL_DSE2 (0x2 << 0) @@ -105,7 +106,11 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_ODE (0x1 << 5) #define PAD_CTL_PUE (0x1 << 6) #define PAD_CTL_HYS (0x1 << 7) +#if defined(CONFIG_IMX8MM) +#define PAD_CTL_PE (0x1 << 8) +#else #define PAD_CTL_LVTTL (0x1 << 8) +#endif #elif defined CONFIG_MX7 @@ -267,10 +272,10 @@ if (is_mx6dq() || is_mx6dqp()) { \ } #define SETUP_IOMUX_PADS(x) \ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2) -#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) -#define IOMUX_PADS(x) MX6Q_##x +#elif defined(CONFIG_MX6Q) +#define IOMUX_PADS(x) MX6_##x #define SETUP_IOMUX_PAD(def) \ - imx_iomux_v3_setup_pad(MX6Q_##def); + imx_iomux_v3_setup_pad(MX6_##def); #define SETUP_IOMUX_PADS(x) \ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) #elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) @@ -280,9 +285,9 @@ if (is_mx6dq() || is_mx6dqp()) { \ #define SETUP_IOMUX_PADS(x) \ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) #else -#define IOMUX_PADS(x) MX6DL_##x +#define IOMUX_PADS(x) MX6_##x #define SETUP_IOMUX_PAD(def) \ - imx_iomux_v3_setup_pad(MX6DL_##def); + imx_iomux_v3_setup_pad(MX6_##def); #define SETUP_IOMUX_PADS(x) \ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) #endif diff --git a/arch/arm/include/asm/mach-imx/mxc_key_defs.h b/arch/arm/include/asm/mach-imx/mxc_key_defs.h new file mode 100644 index 00000000000..f0765c4c12a --- /dev/null +++ b/arch/arm/include/asm/mach-imx/mxc_key_defs.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MXC_KEYPAD_H_ +#define _MXC_KEYPAD_H_ + +#define KEY_1 2 +#define KEY_2 3 +#define KEY_3 4 +#define KEY_F1 59 +#define KEY_UP 103 +#define KEY_F2 60 + +#define KEY_4 5 +#define KEY_5 6 +#define KEY_6 7 +#define KEY_LEFT 105 +#define KEY_SELECT 0x161 +#define KEY_RIGHT 106 + +#define KEY_7 8 +#define KEY_8 9 +#define KEY_9 10 +#define KEY_F3 61 +#define KEY_DOWN 108 +#define KEY_F4 62 + +#define KEY_0 11 +#define KEY_OK 0x160 +#define KEY_ESC 1 +#define KEY_ENTER 28 +#define KEY_MENU 139 /* Menu (show menu) */ +#define KEY_BACK 158 /* AC Back */ + +#endif diff --git a/arch/arm/include/asm/mach-imx/regs-apbh.h b/arch/arm/include/asm/mach-imx/regs-apbh.h index 4cc4abaf855..a6c2158ec02 100644 --- a/arch/arm/include/asm/mach-imx/regs-apbh.h +++ b/arch/arm/include/asm/mach-imx/regs-apbh.h @@ -6,6 +6,7 @@ * * Based on code from LTIB: * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -96,7 +97,7 @@ struct mxs_apbh_regs { mxs_reg_32(hw_apbh_version) }; -#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7)) +#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) struct mxs_apbh_regs { mxs_reg_32(hw_apbh_ctrl0) mxs_reg_32(hw_apbh_ctrl1) @@ -275,7 +276,7 @@ struct mxs_apbh_regs { #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 -#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7)) +#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002 @@ -391,7 +392,7 @@ struct mxs_apbh_regs { #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 #endif -#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 #endif diff --git a/arch/arm/include/asm/mach-imx/regs-bch.h b/arch/arm/include/asm/mach-imx/regs-bch.h index c0f673cc33b..dc2363a8aee 100644 --- a/arch/arm/include/asm/mach-imx/regs-bch.h +++ b/arch/arm/include/asm/mach-imx/regs-bch.h @@ -5,7 +5,8 @@ * on behalf of DENX Software Engineering GmbH * * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -41,6 +42,7 @@ struct mxs_bch_regs { mxs_reg_32(hw_bch_dbgahbmread) mxs_reg_32(hw_bch_blockname) mxs_reg_32(hw_bch_version) + mxs_reg_32(hw_bch_debug1) }; #endif @@ -76,6 +78,9 @@ struct mxs_bch_regs { #define BCH_MODE_ERASE_THRESHOLD_MASK 0xff #define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 +#define BCH_MODE_ERASE_THRESHOLD(v) \ + (((v) << BCH_MODE_ERASE_THRESHOLD_OFFSET) & \ + BCH_MODE_ERASE_THRESHOLD_MASK) #define BCH_ENCODEPTR_ADDR_MASK 0xffffffff #define BCH_ENCODEPTR_ADDR_OFFSET 0 @@ -123,7 +128,7 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 #define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) #define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 -#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) #define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11) #define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 #else @@ -154,7 +159,7 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) #define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 -#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) #define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11) #define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 #else diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h index 38a2c6d4eea..3abb45b50d6 100644 --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h @@ -23,7 +23,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ @@ -62,7 +62,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ @@ -74,7 +74,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_thres) mxs_reg_32(hw_lcdif_as_ctrl) mxs_reg_32(hw_lcdif_as_buf) diff --git a/arch/arm/include/asm/mach-imx/sci/ipc.h b/arch/arm/include/asm/mach-imx/sci/ipc.h new file mode 100644 index 00000000000..145df1db805 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/ipc.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the IPC implementation. + */ + +#ifndef SC_IPC_H +#define SC_IPC_H + +/* Includes */ + +#include + +/* Defines */ + +/* Types */ + +/* Functions */ + +/*! + * This function opens an IPC channel. + * + * @param[out] ipc return pointer for ipc handle + * @param[in] id id of channel to open + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_IPC + * otherwise). + * + * The \a id parameter is implementation specific. Could be an MU + * address, pointer to a driver path, channel index, etc. + */ +sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id); + +/*! + * This function closes an IPC channel. + * + * @param[in] ipc id of channel to close + */ +void sc_ipc_close(sc_ipc_t ipc); + +/*! + * This function reads a message from an IPC channel. + * + * @param[in] ipc id of channel read from + * @param[out] data pointer to message buffer to read + * + * This function will block if no message is available to be read. + */ +void sc_ipc_read(sc_ipc_t ipc, void *data); + +/*! + * This function writes a message to an IPC channel. + * + * @param[in] ipc id of channel to write to + * @param[in] data pointer to message buffer to write + * + * This function will block if the outgoing buffer is full. + */ +void sc_ipc_write(sc_ipc_t ipc, const void *data); + +#endif /* SC_IPC_H */ + diff --git a/arch/arm/include/asm/mach-imx/sci/rpc.h b/arch/arm/include/asm/mach-imx/sci/rpc.h new file mode 100644 index 00000000000..845197bec5f --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/rpc.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the RPC implementation. + */ + +#ifndef SC_RPC_H +#define SC_RPC_H + +/* Includes */ + +#include +#include + +/* Defines */ + +#define SCFW_API_VERSION_MAJOR 1U +#define SCFW_API_VERSION_MINOR 4U + +#define SC_RPC_VERSION 1U + +#define SC_RPC_MAX_MSG 8U + +#define RPC_VER(MESG) ((MESG)->version) +#define RPC_SIZE(MESG) ((MESG)->size) +#define RPC_SVC(MESG) ((MESG)->svc) +#define RPC_FUNC(MESG) ((MESG)->func) +#define RPC_R8(MESG) ((MESG)->func) +#define RPC_I32(MESG, IDX) ((MESG)->DATA.i32[(IDX) / 4U]) +#define RPC_I16(MESG, IDX) ((MESG)->DATA.i16[(IDX) / 2U]) +#define RPC_I8(MESG, IDX) ((MESG)->DATA.i8[(IDX)]) +#define RPC_U32(MESG, IDX) ((MESG)->DATA.u32[(IDX) / 4U]) +#define RPC_U16(MESG, IDX) ((MESG)->DATA.u16[(IDX) / 2U]) +#define RPC_U8(MESG, IDX) ((MESG)->DATA.u8[(IDX)]) + +#define SC_RPC_SVC_UNKNOWN 0U +#define SC_RPC_SVC_RETURN 1U +#define SC_RPC_SVC_PM 2U +#define SC_RPC_SVC_RM 3U +#define SC_RPC_SVC_TIMER 5U +#define SC_RPC_SVC_PAD 6U +#define SC_RPC_SVC_MISC 7U +#define SC_RPC_SVC_IRQ 8U +#define SC_RPC_SVC_SECO 9U +#define SC_RPC_SVC_ABORT 10U + +#define SC_RPC_ASYNC_STATE_RD_START 0U +#define SC_RPC_ASYNC_STATE_RD_ACTIVE 1U +#define SC_RPC_ASYNC_STATE_RD_DONE 2U +#define SC_RPC_ASYNC_STATE_WR_START 3U +#define SC_RPC_ASYNC_STATE_WR_ACTIVE 4U +#define SC_RPC_ASYNC_STATE_WR_DONE 5U + +#define SC_RPC_MU_GIR_SVC 0x1U +#define SC_RPC_MU_GIR_WAKE 0x2U +#define SC_RPC_MU_GIR_BOOT 0x4U +#define SC_RPC_MU_GIR_DBG 0x8U + +#define I8(X) ((int8_t) (X)) +#define I16(X) ((int16_t) (X)) +#define I32(X) ((int32_t) (X)) +#define I64(X) ((int64_t) (X)) +#define U8(X) ((uint8_t) (X)) +#define U16(X) ((uint16_t) (X)) +#define U32(X) ((uint32_t) (X)) +#define U64(X) ((uint64_t) (X)) + +#define PTR_I8(X) ((int8_t*) (X)) +#define PTR_I16(X) ((int16_t*) (X)) +#define PTR_I32(X) ((int32_t*) (X)) +#define PTR_I64(X) ((int64_t*) (X)) +#define PTR_U8(X) ((uint8_t*) (X)) +#define PTR_U16(X) ((uint16_t*) (X)) +#define PTR_U32(X) ((uint32_t*) (X)) +#define PTR_U64(X) ((uint64_t*) (X)) + +#define U2B(X) (((X) != 0U) ? SC_TRUE : SC_FALSE) +#define U2B32(X) (((X) != 0UL) ? SC_TRUE : SC_FALSE) +#define B2U8(X) (((X) != SC_FALSE) ? U8(0x01U) : U8(0x00U)) +#define B2U16(X) (((X) != SC_FALSE) ? U16(0x01U) : U16(0x00U)) +#define B2U32(X) (((X) != SC_FALSE) ? U32(0x01U) : U32(0x00U)) + +/* Types */ + +typedef uint8_t sc_rpc_svc_t; + +typedef struct +{ + uint8_t version; + uint8_t size; + uint8_t svc; + uint8_t func; + union + { + int32_t i32[(SC_RPC_MAX_MSG - 1U)]; + int16_t i16[(SC_RPC_MAX_MSG - 1U) * 2U]; + int8_t i8[(SC_RPC_MAX_MSG - 1U) * 4U]; + uint32_t u32[(SC_RPC_MAX_MSG - 1U)]; + uint16_t u16[(SC_RPC_MAX_MSG - 1U) * 2U]; + uint8_t u8[(SC_RPC_MAX_MSG - 1U) * 4U]; + } DATA; +} sc_rpc_msg_t; + +typedef uint8_t sc_rpc_async_state_t; + +typedef struct +{ + sc_rpc_async_state_t state; + uint8_t wordIdx; + sc_rpc_msg_t msg; + uint32_t timeStamp; +} sc_rpc_async_msg_t; + +/* Functions */ + +/*! + * This is an internal function to send an RPC message over an IPC + * channel. It is called by client-side SCFW API function shims. + * + * @param[in] ipc IPC handle + * @param[in,out] msg handle to a message + * @param[in] no_resp response flag + * + * If \a no_resp is SC_FALSE then this function waits for a response + * and returns the result in \a msg. + */ +void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp); + +/*! + * This is an internal function to dispath an RPC call that has + * arrived via IPC over an MU. It is called by server-side SCFW. + * + * @param[in] mu MU message arrived on + * @param[in,out] msg handle to a message + * + * The function result is returned in \a msg. + */ +void sc_rpc_dispatch(sc_rsrc_t mu, sc_rpc_msg_t *msg); + +/*! + * This function translates an RPC message and forwards on to the + * normal RPC API. It is used only by hypervisors. + * + * @param[in] ipc IPC handle + * @param[in,out] msg handle to a message + * + * This function decodes a message, calls macros to translate the + * resources, pads, addresses, partitions, memory regions, etc. and + * then forwards on to the hypervisors SCFW API.Return results are + * translated back abd placed back into the message to be returned + * to the original API. + */ +void sc_rpc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); + +#endif /* SC_RPC_H */ + diff --git a/arch/arm/include/asm/mach-imx/sci/scfw.h b/arch/arm/include/asm/mach-imx/sci/scfw.h new file mode 100644 index 00000000000..a2dbd15f383 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/scfw.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*==========================================================================*/ +/*! + * @file scfw.h + * + * Header file containing includes to system headers. + */ +/*==========================================================================*/ + +#ifndef _SC_SCFW_H +#define _SC_SCFW_H + +/* Includes */ + +#include + +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*! + * This type is used to declare a handle for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef uint64_t sc_ipc_t; + +/*! + * This type is used to declare an ID for an IPC communication + * channel. For the reference IPC implementation, this ID + * selects the base address of the MU used for IPC. + */ +typedef uint64_t sc_ipc_id_t; + +#endif /* _SC_SCFW_H */ + diff --git a/arch/arm/include/asm/mach-imx/sci/sci.h b/arch/arm/include/asm/mach-imx/sci/sci.h new file mode 100644 index 00000000000..8c1b4e4450f --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/sci.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*==========================================================================*/ +/*! + * @file sci.h + * + * Header file containing the public System Controller Interface (SCI) + * definitions. + * + * + * @{ + */ +/*==========================================================================*/ + +#ifndef _SC_SCI_H +#define _SC_SCI_H + +/* Defines */ + +/* Includes */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SC_IPC_AP_CH0 (MU_BASE_ADDR(0)) +#define SC_IPC_AP_CH1 (MU_BASE_ADDR(1)) +#define SC_IPC_AP_CH2 (MU_BASE_ADDR(2)) +#define SC_IPC_AP_CH3 (MU_BASE_ADDR(3)) +#define SC_IPC_AP_CH4 (MU_BASE_ADDR(4)) + +#ifndef SC_IPC_CH +#define SC_IPC_CH SC_IPC_AP_CH1 +#endif + +/* Types */ + +/* Functions */ + +#endif /* _SC_SCI_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/mach-imx/sci/svc/irq/api.h b/arch/arm/include/asm/mach-imx/sci/svc/irq/api.h new file mode 100644 index 00000000000..b065e457060 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/svc/irq/api.h @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Interrupt (IRQ) function. + * + * @addtogroup IRQ_SVC (SVC) Interrupt Service + * + * Module for the Interrupt (IRQ) service. + * + * @{ + */ + +#ifndef SC_IRQ_API_H +#define SC_IRQ_API_H + +/* Includes */ + +#include + +/* Defines */ + +#define SC_IRQ_NUM_GROUP 7U /*!< Number of groups */ + +/*! + * @name Defines for sc_irq_group_t + */ +/*@{*/ +#define SC_IRQ_GROUP_TEMP 0U /*!< Temp interrupts */ +#define SC_IRQ_GROUP_WDOG 1U /*!< Watchdog interrupts */ +#define SC_IRQ_GROUP_RTC 2U /*!< RTC interrupts */ +#define SC_IRQ_GROUP_WAKE 3U /*!< Wakeup interrupts */ +#define SC_IRQ_GROUP_SYSCTR 4U /*!< System counter interrupts */ +#define SC_IRQ_GROUP_REBOOTED 5U /*!< Partition reboot complete */ +#define SC_IRQ_GROUP_REBOOT 6U /*!< Partition reboot starting */ +/*@}*/ + +/*! + * @name Defines for sc_irq_temp_t + */ +/*@{*/ +#define SC_IRQ_TEMP_HIGH (1UL << 0U) /*!< Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /*!< CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /*!< CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /*!< GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /*!< DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /*!< DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /*!< DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /*!< PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /*!< PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_LOW (1UL << 10U) /*!< Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /*!< CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /*!< CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /*!< GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /*!< GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /*!< DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /*!< DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /*!< DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /*!< PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /*!< PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /*!< PMIC2 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /*!< PMIC2 temp alarm interrupt */ +/*@}*/ + +/*! + * @name Defines for sc_irq_wdog_t + */ +/*@{*/ +#define SC_IRQ_WDOG (1U << 0U) /*!< Watchdog interrupt */ +/*@}*/ + +/*! + * @name Defines for sc_irq_rtc_t + */ +/*@{*/ +#define SC_IRQ_RTC (1U << 0U) /*!< RTC interrupt */ +/*@}*/ + +/*! + * @name Defines for sc_irq_wake_t + */ +/*@{*/ +#define SC_IRQ_BUTTON (1U << 0U) /*!< Button interrupt */ +#define SC_IRQ_PAD (1U << 1U) /*!< Pad wakeup */ +#define SC_IRQ_USR1 (1U << 2U) /*!< User defined 1 */ +#define SC_IRQ_USR2 (1U << 3U) /*!< User defined 2 */ +#define SC_IRQ_BC_PAD (1U << 4U) /*!< Pad wakeup (broadcast to all partitions) */ +/*@}*/ + +/*! + * @name Defines for sc_irq_sysctr_t + */ +/*@{*/ +#define SC_IRQ_SYSCTR (1U << 0U) /*!< SYSCTR interrupt */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare an interrupt group. + */ +typedef uint8_t sc_irq_group_t; + +/*! + * This type is used to declare a bit mask of temp interrupts. + */ +typedef uint8_t sc_irq_temp_t; + +/*! + * This type is used to declare a bit mask of watchdog interrupts. + */ +typedef uint8_t sc_irq_wdog_t; + +/*! + * This type is used to declare a bit mask of RTC interrupts. + */ +typedef uint8_t sc_irq_rtc_t; + +/*! + * This type is used to declare a bit mask of wakeup interrupts. + */ +typedef uint8_t sc_irq_wake_t; + +/* Functions */ + +/*! + * This function enables/disables interrupts. If pending interrupts + * are unmasked, an interrupt will be triggered. + * + * @param[in] ipc IPC handle + * @param[in] resource MU channel + * @param[in] group group the interrupts are in + * @param[in] mask mask of interrupts to affect + * @param[in] enable state to change interrupts to + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if group invalid + */ +sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t mask, sc_bool_t enable); + +/*! + * This function returns the current interrupt status (regardless if + * masked). Automatically clears pending interrupts. + * + * @param[in] ipc IPC handle + * @param[in] resource MU channel + * @param[in] group groups the interrupts are in + * @param[in] status status of interrupts + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if group invalid + * + * The returned \a status may show interrupts pending that are + * currently masked. + */ +sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t *status); + +#endif /* SC_IRQ_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/mach-imx/sci/svc/misc/api.h b/arch/arm/include/asm/mach-imx/sci/svc/misc/api.h new file mode 100644 index 00000000000..13e2791def6 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/svc/misc/api.h @@ -0,0 +1,547 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Miscellaneous (MISC) function. + * + * @addtogroup MISC_SVC (SVC) Miscellaneous Service + * + * Module for the Miscellaneous (MISC) service. + * + * @{ + */ + +#ifndef SC_MISC_API_H +#define SC_MISC_API_H + +/* Includes */ + +#include +#include + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_MISC_DMA_GRP_W 5U /*!< Width of sc_misc_dma_group_t */ +/*@}*/ + +/*! Max DMA channel priority group */ +#define SC_MISC_DMA_GRP_MAX 31U + +/*! + * @name Defines for sc_misc_boot_status_t + */ +/*@{*/ +#define SC_MISC_BOOT_STATUS_SUCCESS 0U /*!< Success */ +#define SC_MISC_BOOT_STATUS_SECURITY 1U /*!< Security violation */ +/*@}*/ + +/*! + * @name Defines for sc_misc_temp_t + */ +/*@{*/ +#define SC_MISC_TEMP 0U /*!< Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /*!< Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /*!< Temp low alarm */ +/*@}*/ + +/*! + * @name Defines for sc_misc_seco_auth_cmd_t + */ +/*@{*/ +#define SC_MISC_AUTH_CONTAINER 0U /*!< Authenticate container */ +#define SC_MISC_VERIFY_IMAGE 1U /*!< Verify image */ +#define SC_MISC_REL_CONTAINER 2U /*!< Release container */ +#define SC_MISC_SECO_AUTH_SECO_FW 3U /*!< SECO Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_TX_FW 4U /*!< HDMI TX Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_RX_FW 5U /*!< HDMI RX Firmware */ +/*@}*/ + +/*! + * @name Defines for sc_misc_bt_t + */ +/*@{*/ +#define SC_MISC_BT_PRIMARY 0U /*!< Primary boot */ +#define SC_MISC_BT_SECONDARY 1U /*!< Secondary boot */ +#define SC_MISC_BT_RECOVERY 2U /*!< Recovery boot */ +#define SC_MISC_BT_MANUFACTURE 3U /*!< Manufacture boot */ +#define SC_MISC_BT_SERIAL 4U /*!< Serial boot */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to store a DMA channel priority group. + */ +typedef uint8_t sc_misc_dma_group_t; + +/*! + * This type is used report boot status. + */ +typedef uint8_t sc_misc_boot_status_t; + +/*! + * This type is used to issue SECO authenticate commands. + */ +typedef uint8_t sc_misc_seco_auth_cmd_t; + +/*! + * This type is used report boot status. + */ +typedef uint8_t sc_misc_temp_t; + +/*! + * This type is used report the boot type. + */ +typedef uint8_t sc_misc_bt_t; + +/* Functions */ + +/*! + * @name Control Functions + * @{ + */ + +/*! + * This function sets a miscellaneous control value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource the control is associated with + * @param[in] ctrl control to change + * @param[in] val value to apply to the control + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner + * + * Refer to the [Control List](@ref CONTROLS) for valid control values. + */ +sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t val); + +/*! + * This function gets a miscellaneous control value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource the control is associated with + * @param[in] ctrl control to get + * @param[out] val pointer to return the control value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner + * + * Refer to the [Control List](@ref CONTROLS) for valid control values. + */ +sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t *val); + +/* @} */ + +/*! + * @name DMA Functions + * @{ + */ + +/*! + * This function configures the max DMA channel priority group for a + * partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to assign \a max + * @param[in] max max priority group (0-31) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the parent + * of the affected partition + * + * Valid \a max range is 0-31 with 0 being the lowest and 31 the highest. + * Default is the max priority group for the parent partition of \a pt. + */ +sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_misc_dma_group_t max); + +/*! + * This function configures the priority group for a DMA channel. + * + * @param[in] ipc IPC handle + * @param[in] resource DMA channel resource + * @param[in] group priority group (0-31) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the owner or parent + * of the owner of the DMA channel + * + * Valid \a group range is 0-31 with 0 being the lowest and 31 the highest. + * The max value of \a group is limited by the partition max set using + * sc_misc_set_max_dma_group(). + */ +sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_dma_group_t group); + +/* @} */ + +/*! + * @name Security Functions + * @{ + */ + +/*! + * @deprecated Use sc_seco_image_load() instead. + */ +sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw); + +/*! + * @deprecated Use sc_seco_authenticate() instead. + */ +sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc, + sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr); + +/*! + * @deprecated Use sc_seco_fuse_write() instead. + */ +sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * @deprecated Use sc_seco_enable_debug() instead. + */ +sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * @deprecated Use sc_seco_forward_lifecycle() instead. + */ +sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change); + +/*! + * @deprecated Use sc_seco_return_lifecycle() instead. + */ +sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * @deprecated Use sc_seco_build_info() instead. + */ +void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, + uint32_t *commit); + +/*! + * @deprecated Use sc_seco_chip_info() instead. + */ +sc_err_t sc_misc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc, + uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h); + +/*! + * @deprecated Use sc_seco_attest_mode() instead. + */ +sc_err_t sc_misc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode); + +/*! + * @deprecated Use sc_seco_attest() instead. + */ +sc_err_t sc_misc_seco_attest(sc_ipc_t ipc, uint64_t nonce); + +/*! + * @deprecated Use sc_seco_get_attest_pkey() instead. + */ +sc_err_t sc_misc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * @deprecated Use sc_seco_get_attest_sign() instead. + */ +sc_err_t sc_misc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * @deprecated Use sc_seco_attest_verify() instead. + */ +sc_err_t sc_misc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * @deprecated Use sc_seco_commit() instead. + */ +sc_err_t sc_misc_seco_commit(sc_ipc_t ipc, uint32_t *info); + +/* @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function is used output a debug character from the SCU UART. + * + * @param[in] ipc IPC handle + * @param[in] ch character to output + */ +void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch); + +/*! + * This function starts/stops emulation waveform capture. + * + * @param[in] ipc IPC handle + * @param[in] enable flag to enable/disable capture + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_UNAVAILABLE if not running on emulation + */ +sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable); + +/*! + * This function is used to return the SCFW build info. + * + * @param[in] ipc IPC handle + * @param[out] build pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + */ +void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, + uint32_t *commit); + +/*! + * This function is used to return the SCFW API versions. + * + * @param[in] ipc IPC handle + * @param[out] cl_maj pointer to return major part of client version + * @param[out] cl_min pointer to return minor part of client version + * @param[out] sv_maj pointer to return major part of SCFW version + * @param[out] sv_min pointer to return minor part of SCFW version + * + * Client verion is the version of the API ported to and used by the caller. + * SCFW version is the version of the SCFW binary running on the CPU. + * + * Note a major version difference indicates a break in compatibility. + */ +void sc_misc_api_ver(sc_ipc_t ipc, uint16_t *cl_maj, + uint16_t *cl_min, uint16_t *sv_maj, uint16_t *sv_min); + +/*! + * This function is used to return the device's unique ID. + * + * @param[in] ipc IPC handle + * @param[out] id_l pointer to return lower 32-bit of ID [31:0] + * @param[out] id_h pointer to return upper 32-bits of ID [63:32] + */ +void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, + uint32_t *id_h); + +/* @} */ + +/*! + * @name Other Functions + * @{ + */ + +/*! + * This function configures the ARI match value for PCIe/SATA resources. + * + * @param[in] ipc IPC handle + * @param[in] resource match resource + * @param[in] resource_mst PCIe/SATA master to match + * @param[in] ari ARI to match + * @param[in] enable enable match or not + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the owner or parent + * of the owner of the resource and translation + * + * For PCIe, the ARI is the 16-bit value that includes the bus number, + * device number, and function number. For SATA, this value includes the + * FISType and PM_Port. + */ +sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable); + +/*! + * This function reports boot status. + * + * @param[in] ipc IPC handle + * @param[in] status boot status + * + * This is used by SW partitions to report status of boot. This is + * normally used to report a boot failure. + */ +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); + +/*! + * This function tells the SCFW that a CPU is done booting. + * + * @param[in] ipc IPC handle + * @param[in] cpu CPU that is done booting + * + * This is called by early booting CPUs to report they are done with + * initialization. After starting early CPUs, the SCFW halts the + * booting process until they are done. During this time, early + * CPUs can call the SCFW with lower latency as the SCFW is idle. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the CPU owner + */ +sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu); + +/*! + * This function reads a given fuse word index. + * + * @param[in] ipc IPC handle + * @param[in] word fuse word index + * @param[out] val fuse read value + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_NOACCESS if read operation failed + * - SC_ERR_LOCKED if read operation is locked + */ +sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val); + +/*! + * This function writes a given fuse word index. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. + * + * @param[in] ipc IPC handle + * @param[in] word fuse word index + * @param[in] val fuse write value + * + * The command is passed as is to SECO. SECO uses part of the + * \a word parameter to indicate if the fuse should be locked + * after programming. See the "Write common fuse" section of + * the Security Reference Manual (SRM) for more info. + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access + * - SC_ERR_NOACCESS if write operation failed + * - SC_ERR_LOCKED if write operation is locked + */ +sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val); + +/*! + * This function sets a temp sensor alarm. + * + * @param[in] ipc IPC handle + * @param[in] resource resource with sensor + * @param[in] temp alarm to set + * @param[in] celsius whole part of temp to set + * @param[in] tenths fractional part of temp to set + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * This function will enable the alarm interrupt if the temp requested is + * not the min/max temp. This enable automatically clears when the alarm + * occurs and this function has to be called again to re-enable. + * + * Return errors codes: + * - SC_ERR_PARM if parameters invalid + * - SC_ERR_NOACCESS if caller does not own the resource + * - SC_ERR_NOPOWER if power domain of resource not powered + */ +sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t celsius, int8_t tenths); + +/*! + * This function gets a temp sensor value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource with sensor + * @param[in] temp value to get (sensor or alarm) + * @param[out] celsius whole part of temp to get + * @param[out] tenths fractional part of temp to get + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if parameters invalid + * - SC_ERR_BUSY if temp not ready yet (time delay after power on) + * - SC_ERR_NOPOWER if power domain of resource not powered + */ +sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths); + +/*! + * This function returns the boot device. + * + * @param[in] ipc IPC handle + * @param[out] dev pointer to return boot device + */ +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev); + +/*! + * This function returns the boot type. + * + * @param[in] ipc IPC handle + * @param[out] type pointer to return boot type + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors code: + * - SC_ERR_UNAVAILABLE if type not passed by ROM + */ +sc_err_t sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type); + +/*! + * This function returns the current status of the ON/OFF button. + * + * @param[in] ipc IPC handle + * @param[out] status pointer to return button status + */ +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status); + +/*! + * This function returns the ROM patch checksum. + * + * @param[in] ipc IPC handle + * @param[out] checksum pointer to return checksum + * + * @return Returns and error code (SC_ERR_NONE = success). + */ +sc_err_t sc_misc_rompatch_checksum(sc_ipc_t ipc, uint32_t *checksum); + +/*! + * This function calls the board IOCTL function. + * + * @param[in] ipc IPC handle + * @param[in,out] parm1 pointer to pass parameter 1 + * @param[in,out] parm2 pointer to pass parameter 2 + * @param[in,out] parm3 pointer to pass parameter 3 + * + * @return Returns and error code (SC_ERR_NONE = success). + */ +sc_err_t sc_misc_board_ioctl(sc_ipc_t ipc, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3); + +/* @} */ + +#endif /* SC_MISC_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/mach-imx/sci/svc/pad/api.h b/arch/arm/include/asm/mach-imx/sci/svc/pad/api.h new file mode 100644 index 00000000000..b7d536f0e62 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/svc/pad/api.h @@ -0,0 +1,571 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Pad Control (PAD) function. + * + * @addtogroup PAD_SVC (SVC) Pad Service + * + * Module for the Pad Control (PAD) service. + * + * @details + * + * Pad configuration is managed by SC firmware. The pad configuration + * features supported by the SC firmware include: + * + * - Configuring the mux, input/output connection, and low-power isolation + mode. + * - Configuring the technology-specific pad setting such as drive strength, + * pullup/pulldown, etc. + * - Configuring compensation for pad groups with dual voltage capability. + * + * Pad functions fall into one of three categories. Generic functions are + * common to all SoCs and all process technologies. SoC functions are raw + * low-level functions. Technology-specific functions are specific to the + * process technology. + * + * The list of pads is SoC specific. Refer to the SoC [Pad List](@ref PADS) + * for valid pad values. Note that all pads exist on a die but may or + * may not be brought out by the specific package. Mapping of pads to + * package pins/balls is documented in the associated Data Sheet. Some pads + * may not be brought out because the part (die+package) is defeatured and + * some pads may connect to the substrate in the package. + * + * Some pads (SC_P_COMP_*) that can be specified are not individual pads + * but are in fact pad groups. These groups have additional configuration + * that can be done using the sc_pad_set_gp_28fdsoi_comp() function. More + * info on these can be found in the associated Reference Manual. + * + * Pads are managed as a resource by the Resource Manager (RM). They have + * assigned owners and only the owners can configure the pads. Some of the + * pads are reserved for use by the SCFW itself and this can be overriden + * with the implementation of board_config_sc(). Additionally, pads may + * be assigned to various other partitions via the implementation of + * board_system_config(). + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * + * @includedoc pad/details.dox + * + * @{ + */ + +#ifndef SC_PAD_API_H +#define SC_PAD_API_H + +/* Includes */ + +#include +#include + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_PAD_MUX_W 3U /*!< Width of mux parameter */ +/*@}*/ + +/*! + * @name Defines for sc_pad_config_t + */ +/*@{*/ +#define SC_PAD_CONFIG_NORMAL 0U /*!< Normal */ +#define SC_PAD_CONFIG_OD 1U /*!< Open Drain */ +#define SC_PAD_CONFIG_OD_IN 2U /*!< Open Drain and input */ +#define SC_PAD_CONFIG_OUT_IN 3U /*!< Output and input */ +/*@}*/ + +/*! + * @name Defines for sc_pad_iso_t + */ +/*@{*/ +#define SC_PAD_ISO_OFF 0U /*!< ISO latch is transparent */ +#define SC_PAD_ISO_EARLY 1U /*!< Follow EARLY_ISO */ +#define SC_PAD_ISO_LATE 2U /*!< Follow LATE_ISO */ +#define SC_PAD_ISO_ON 3U /*!< ISO latched data is held */ +/*@}*/ + +/*! + * @name Defines for sc_pad_28fdsoi_dse_t + */ +/*@{*/ +#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /*!< Drive strength of 1mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /*!< Drive strength of 2mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /*!< Drive strength of 4mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /*!< Drive strength of 6mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /*!< Drive strength of 8mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /*!< Drive strength of 10mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /*!< Drive strength of 12mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_HS 7U /*!< High-speed drive strength for 1.8v */ +#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /*!< Drive strength of 2mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /*!< Drive strength of 4mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /*!< Drive strength of 8mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /*!< Drive strength of 12mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /*!< High drive strength for dual volt */ +#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /*!< Low drive strength for dual volt */ +/*@}*/ + +/*! + * @name Defines for sc_pad_28fdsoi_ps_t + */ +/*@{*/ +#define SC_PAD_28FDSOI_PS_KEEPER 0U /*!< Bus-keeper (only valid for 1.8v) */ +#define SC_PAD_28FDSOI_PS_PU 1U /*!< Pull-up */ +#define SC_PAD_28FDSOI_PS_PD 2U /*!< Pull-down */ +#define SC_PAD_28FDSOI_PS_NONE 3U /*!< No pull (disabled) */ +/*@}*/ + +/*! + * @name Defines for sc_pad_28fdsoi_pus_t + */ +/*@{*/ +#define SC_PAD_28FDSOI_PUS_30K_PD 0U /*!< 30K pull-down */ +#define SC_PAD_28FDSOI_PUS_100K_PU 1U /*!< 100K pull-up */ +#define SC_PAD_28FDSOI_PUS_3K_PU 2U /*!< 3K pull-up */ +#define SC_PAD_28FDSOI_PUS_30K_PU 3U /*!< 30K pull-up */ +/*@}*/ + +/*! + * @name Defines for sc_pad_wakeup_t + */ +/*@{*/ +#define SC_PAD_WAKEUP_OFF 0U /*!< Off */ +#define SC_PAD_WAKEUP_CLEAR 1U /*!< Clears pending flag */ +#define SC_PAD_WAKEUP_LOW_LVL 4U /*!< Low level */ +#define SC_PAD_WAKEUP_FALL_EDGE 5U /*!< Falling edge */ +#define SC_PAD_WAKEUP_RISE_EDGE 6U /*!< Rising edge */ +#define SC_PAD_WAKEUP_HIGH_LVL 7U /*!< High-level */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare a pad config. It determines how the + * output data is driven, pull-up is controlled, and input signal is + * connected. Normal and OD are typical and only connect the input + * when the output is not driven. The IN options are less common and + * force an input connection even when driving the output. + */ +typedef uint8_t sc_pad_config_t; + +/*! + * This type is used to declare a pad low-power isolation config. + * ISO_LATE is the most common setting. ISO_EARLY is only used when + * an output pad is directly determined by another input pad. The + * other two are only used when SW wants to directly contol isolation. + */ +typedef uint8_t sc_pad_iso_t; + +/*! + * This type is used to declare a drive strength. Note it is specific + * to 28FDSOI. Also note that valid values depend on the pad type. + */ +typedef uint8_t sc_pad_28fdsoi_dse_t; + +/*! + * This type is used to declare a pull select. Note it is specific + * to 28FDSOI. + */ +typedef uint8_t sc_pad_28fdsoi_ps_t; + +/*! + * This type is used to declare a pull-up select. Note it is specific + * to 28FDSOI HSIC pads. + */ +typedef uint8_t sc_pad_28fdsoi_pus_t; + +/*! + * This type is used to declare a wakeup mode of a pad. + */ +typedef uint8_t sc_pad_wakeup_t; + +/* Functions */ + +/*! + * @name Generic Functions + * @{ + */ + +/*! + * This function configures the mux settings for a pad. This includes + * the signal mux, pad config, and low-power isolation mode. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] mux mux setting + * @param[in] config pad config + * @param[in] iso low-power isolation mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso); + +/*! + * This function gets the mux settings for a pad. This includes + * the signal mux, pad config, and low-power isolation mode. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] mux pointer to return mux setting + * @param[out] config pointer to return pad config + * @param[out] iso pointer to return low-power isolation mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso); + +/*! + * This function configures the general purpose pad control. This + * is technology dependent and includes things like drive strength, + * slew rate, pull up/down, etc. Refer to the SoC Reference Manual + * for bit field details. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] ctrl control value to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl); + +/*! + * This function gets the general purpose pad control. This + * is technology dependent and includes things like drive strength, + * slew rate, pull up/down, etc. Refer to the SoC Reference Manual + * for bit field details. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] ctrl pointer to return control value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl); + +/*! + * This function configures the wakeup mode of the pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] wakeup wakeup to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t wakeup); + +/*! + * This function gets the wakeup mode of a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] wakeup pointer to return wakeup + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t *wakeup); + +/*! + * This function configures a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] mux mux setting + * @param[in] config pad config + * @param[in] iso low-power isolation mode + * @param[in] ctrl control value + * @param[in] wakeup wakeup to set + * + * @see sc_pad_set_mux(). + * @see sc_pad_set_gp(). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, + sc_pad_wakeup_t wakeup); + +/*! + * This function gets a pad's config. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] mux pointer to return mux setting + * @param[out] config pointer to return pad config + * @param[out] iso pointer to return low-power isolation mode + * @param[out] ctrl pointer to return control value + * @param[out] wakeup pointer to return wakeup to set + * + * @see sc_pad_set_mux(). + * @see sc_pad_set_gp(). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl, + sc_pad_wakeup_t *wakeup); + +/* @} */ + +/*! + * @name SoC Specific Functions + * @{ + */ + +/*! + * This function configures the settings for a pad. This setting is SoC + * specific. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] val value to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val); + +/*! + * This function gets the settings for a pad. This setting is SoC + * specific. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] val pointer to return setting + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); + +/* @} */ + +/*! + * @name Technology Specific Functions + * @{ + */ + +/*! + * This function configures the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] dse drive strength + * @param[in] ps pull select + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps); + +/*! + * This function gets the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] dse pointer to return drive strength + * @param[out] ps pointer to return pull select + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps); + +/*! + * This function configures the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] dse drive strength + * @param[in] hys hysteresis + * @param[in] pus pull-up select + * @param[in] pke pull keeper enable + * @param[in] pue pull-up enable + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus, + sc_bool_t pke, sc_bool_t pue); + +/*! + * This function gets the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] dse pointer to return drive strength + * @param[out] hys pointer to return hysteresis + * @param[out] pus pointer to return pull-up select + * @param[out] pke pointer to return pull keeper enable + * @param[out] pue pointer to return pull-up enable + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus, + sc_bool_t *pke, sc_bool_t *pue); + +/*! + * This function configures the compensation control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] compen compensation/freeze mode + * @param[in] fastfrz fast freeze + * @param[in] rasrcp compensation code for PMOS + * @param[in] rasrcn compensation code for NMOS + * @param[in] nasrc_sel NASRC read select + * @param[in] psw_ovr 2.5v override + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + * + * Note \a psw_ovr is only applicable to pads supporting 2.5 volt + * operation (e.g. some Ethernet pads). + */ +sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn, + sc_bool_t nasrc_sel, sc_bool_t psw_ovr); + +/*! + * This function gets the compensation control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] compen pointer to return compensation/freeze mode + * @param[out] fastfrz pointer to return fast freeze + * @param[out] rasrcp pointer to return compensation code for PMOS + * @param[out] rasrcn pointer to return compensation code for NMOS + * @param[out] nasrc_sel pointer to return NASRC read select + * @param[out] compok pointer to return compensation status + * @param[out] nasrc pointer to return NASRCP/NASRCN + * @param[out] psw_ovr pointer to return the 2.5v override + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn, + sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr); + +/* @} */ + +#endif /* SC_PAD_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/mach-imx/sci/svc/pm/api.h b/arch/arm/include/asm/mach-imx/sci/svc/pm/api.h new file mode 100644 index 00000000000..026aa27c1a8 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/svc/pm/api.h @@ -0,0 +1,808 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Power Management (PM) function. This includes functions for power state + * control, clock control, reset control, and wake-up event control. + * + * @addtogroup PM_SVC (SVC) Power Management Service + * + * Module for the Power Management (PM) service. + * + * @includedoc pm/details.dox + * + * @{ + */ + +#ifndef SC_PM_API_H +#define SC_PM_API_H + +/* Includes */ + +#include +#include + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_PM_POWER_MODE_W 2U /*!< Width of sc_pm_power_mode_t */ +#define SC_PM_CLOCK_MODE_W 3U /*!< Width of sc_pm_clock_mode_t */ +#define SC_PM_RESET_TYPE_W 2U /*!< Width of sc_pm_reset_type_t */ +#define SC_PM_RESET_REASON_W 4U /*!< Width of sc_pm_reset_reason_t */ +/*@}*/ + +/*! + * @name Defines for clock indexes (sc_pm_clk_t) + */ +/*@{*/ +/*@}*/ + +/*! + * @name Defines for ALL parameters + */ +/*@{*/ +#define SC_PM_CLK_ALL ((sc_pm_clk_t) UINT8_MAX) /*!< All clocks */ +/*@}*/ + +/*! + * @name Defines for sc_pm_power_mode_t + */ +/*@{*/ +#define SC_PM_PW_MODE_OFF 0U /*!< Power off */ +#define SC_PM_PW_MODE_STBY 1U /*!< Power in standby */ +#define SC_PM_PW_MODE_LP 2U /*!< Power in low-power */ +#define SC_PM_PW_MODE_ON 3U /*!< Power on */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_t + */ +/*@{*/ +#define SC_PM_CLK_SLV_BUS 0U /*!< Slave bus clock */ +#define SC_PM_CLK_MST_BUS 1U /*!< Master bus clock */ +#define SC_PM_CLK_PER 2U /*!< Peripheral clock */ +#define SC_PM_CLK_PHY 3U /*!< Phy clock */ +#define SC_PM_CLK_MISC 4U /*!< Misc clock */ +#define SC_PM_CLK_MISC0 0U /*!< Misc 0 clock */ +#define SC_PM_CLK_MISC1 1U /*!< Misc 1 clock */ +#define SC_PM_CLK_MISC2 2U /*!< Misc 2 clock */ +#define SC_PM_CLK_MISC3 3U /*!< Misc 3 clock */ +#define SC_PM_CLK_MISC4 4U /*!< Misc 4 clock */ +#define SC_PM_CLK_CPU 2U /*!< CPU clock */ +#define SC_PM_CLK_PLL 4U /*!< PLL */ +#define SC_PM_CLK_BYPASS 4U /*!< Bypass clock */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_mode_t + */ +/*@{*/ +#define SC_PM_CLK_MODE_ROM_INIT 0U /*!< Clock is initialized by ROM. */ +#define SC_PM_CLK_MODE_OFF 1U /*!< Clock is disabled */ +#define SC_PM_CLK_MODE_ON 2U /*!< Clock is enabled. */ +#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /*!< Clock is in SW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /*!< Clock is in HW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /*!< Clock is in SW-HW autogate mode */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_parent_t + */ +/*@{*/ +#define SC_PM_PARENT_XTAL 0U /*!< Parent is XTAL. */ +#define SC_PM_PARENT_PLL0 1U /*!< Parent is PLL0 */ +#define SC_PM_PARENT_PLL1 2U /*!< Parent is PLL1 or PLL0/2 */ +#define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */ +#define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */ +/*@}*/ + +/*! + * @name Defines for sc_pm_reset_type_t + */ +/*@{*/ +#define SC_PM_RESET_TYPE_COLD 0U /*!< Cold reset */ +#define SC_PM_RESET_TYPE_WARM 1U /*!< Warm reset */ +#define SC_PM_RESET_TYPE_BOARD 2U /*!< Board reset */ +/*@}*/ + +/*! + * @name Defines for sc_pm_reset_reason_t + */ +/*@{*/ +#define SC_PM_RESET_REASON_POR 0U /*!< Power on reset */ +#define SC_PM_RESET_REASON_JTAG 1U /*!< JTAG reset */ +#define SC_PM_RESET_REASON_SW 2U /*!< Software reset */ +#define SC_PM_RESET_REASON_WDOG 3U /*!< Partition watchdog reset */ +#define SC_PM_RESET_REASON_LOCKUP 4U /*!< SCU lockup reset */ +#define SC_PM_RESET_REASON_SNVS 5U /*!< SNVS reset */ +#define SC_PM_RESET_REASON_TEMP 6U /*!< Temp panic reset */ +#define SC_PM_RESET_REASON_MSI 7U /*!< MSI reset */ +#define SC_PM_RESET_REASON_UECC 8U /*!< ECC reset */ +#define SC_PM_RESET_REASON_SCFW_WDOG 9U /*!< SCFW watchdog reset */ +#define SC_PM_RESET_REASON_ROM_WDOG 10U /*!< SCU ROM watchdog reset */ +#define SC_PM_RESET_REASON_SECO 11U /*!< SECO reset */ +#define SC_PM_RESET_REASON_SCFW_FAULT 12U /*!< SCFW fault reset */ +/*@}*/ + +/*! + * @name Defines for sc_pm_sys_if_t + */ +/*@{*/ +#define SC_PM_SYS_IF_INTERCONNECT 0U /*!< System interconnect */ +#define SC_PM_SYS_IF_MU 1U /*!< AP -> SCU message units */ +#define SC_PM_SYS_IF_OCMEM 2U /*!< On-chip memory (ROM/OCRAM) */ +#define SC_PM_SYS_IF_DDR 3U /*!< DDR memory */ +/*@}*/ + +/*! + * @name Defines for sc_pm_wake_src_t + */ +/*@{*/ +#define SC_PM_WAKE_SRC_NONE 0U /*!< No wake source, used for self-kill */ +#define SC_PM_WAKE_SRC_SCU 1U /*!< Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER 2U /*!< Wakeup from IRQSTEER to resume CPU (GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /*!< Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */ +#define SC_PM_WAKE_SRC_GIC 4U /*!< Wakeup from GIC to wake CPU */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare a power mode. Note resources only use + * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only + * as system power modes. + */ +typedef uint8_t sc_pm_power_mode_t; + +/*! + * This type is used to declare a clock. + */ +typedef uint8_t sc_pm_clk_t; + +/*! + * This type is used to declare a clock mode. + */ +typedef uint8_t sc_pm_clk_mode_t; + +/*! + * This type is used to declare the clock parent. + */ +typedef uint8_t sc_pm_clk_parent_t; + +/*! + * This type is used to declare clock rates. + */ +typedef uint32_t sc_pm_clock_rate_t; + +/*! + * This type is used to declare a desired reset type. + */ +typedef uint8_t sc_pm_reset_type_t; + +/*! + * This type is used to declare a reason for a reset. + */ +typedef uint8_t sc_pm_reset_reason_t; + +/*! + * This type is used to specify a system-level interface to be power managed. + */ +typedef uint8_t sc_pm_sys_if_t; + +/*! + * This type is used to specify a wake source for CPU resources. + */ +typedef uint8_t sc_pm_wake_src_t; + +/* Functions */ + +/*! + * @name Power Functions + * @{ + */ + +/*! + * This function sets the system power mode. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. + * + * @param[in] ipc IPC handle + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid mode, + * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access + * + * @see sc_pm_set_sys_power_mode(). + */ +sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode); + +/*! + * This function sets the power mode of a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition or mode, + * - SC_ERR_NOACCESS if caller's partition is not the owner or + * parent of \a pt + * + * The power mode of the partitions is a max power any resource will + * be set to. Calling this will result in all resources owned + * by \a pt to have their power changed to the lower of \a mode or the + * individual resource mode set using sc_pm_set_resource_power_mode(). + */ +sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t mode); + +/*! + * This function gets the power mode of a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition + * @param[out] mode pointer to return power mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition + */ +sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t *mode); + +/*! + * This function sets the power mode of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or mode, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner + * + * Resources must be at SC_PM_PW_MODE_LP mode or higher to access them, + * otherwise the master will get a bus error or hang. + * + * This function will record the individual resource power mode + * and change it if the requested mode is lower than or equal to the + * partition power mode set with sc_pm_set_partition_power_mode(). + * In other words, the power mode of the resource will be the minimum + * of the resource power mode and the partition power mode. + * + * Note some resources are still not accessible even when powered up if bus + * transactions go through a fabric not powered up. Examples of this are + * resources in display and capture subsystems which require the display + * controller or the imaging subsytem to be powered up first. + * + * Not that resources are grouped into power domains by the underlying + * hardware. If any resource in the domain is on, the entire power domain + * will be on. Other power domains required to access the resource will + * also be turned on. Clocks required to access the peripheral will be + * turned on. Refer to the SoC RM for more info on power domains and access + * infrastructure (bus fabrics, clock domains, etc.). + */ +sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); + +/*! +* This function sets the power mode for all the resources owned +* by a child partition. +* +* @param[in] ipc IPC handle +* @param[in] pt handle of child partition +* @param[in] mode power mode to apply +* @param[in] exclude resource to exclude +* +* @return Returns an error code (SC_ERR_NONE = success). +* +* Return errors: +* - SC_ERR_PARM if invalid partition or mode, +* - SC_ERR_NOACCESS if caller's partition is not the parent +* of \a pt +* +* This functions loops through all the resources owned by \a pt +* and sets the power mode to \a mode. It will skip setting +* \a exclude (SC_R_LAST to skip none). +* +* This function can only be called by the parent. It is used to +* implement some aspects of virtualization. +*/ +sc_err_t sc_pm_set_resource_power_mode_all(sc_ipc_t ipc, + sc_rm_pt_t pt, sc_pm_power_mode_t mode, sc_rsrc_t exclude); + +/*! + * This function gets the power mode of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[out] mode pointer to return power mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. The value + * returned does not reflect the power mode of the partition.. + */ +sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode); + +/*! + * This function requests the low power mode some of the resources + * can enter based on their state. This API is only valid for the + * following resources : SC_R_A53, SC_R_A53_0, SC_R_A53_1, SC_A53_2, + * SC_A53_3, SC_R_A72, SC_R_A72_0, SC_R_A72_1, SC_R_CC1, SC_R_A35, + * SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3. + * For all other resources it will return SC_ERR_PARAM. + * This function will set the low power mode the cores, cluster + * and cluster associated resources will enter when all the cores + * in a given cluster execute WFI + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); + +/*! + * This function requests low-power mode entry for CPU/cluster + * resources. This API is only valid for the following resources: + * SC_R_A53, SC_R_A53_x, SC_R_A72, SC_R_A72_x, SC_R_A35, SC_R_A35_x, + * SC_R_CCI. For all other resources it will return SC_ERR_PARAM. + * For individual core resources, the specified power mode + * and wake source will be applied after the core has entered + * WFI. For cluster resources, the specified power mode is + * applied after all cores in the cluster have entered low-power mode. + * For multicluster resources, the specified power mode is applied + * after all clusters have reached low-power mode. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * @param[in] wake_src wake source for low-power exit + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src); + +/*! + * This function is used to set the resume address of a CPU. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] address 64-bit resume address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + */ +sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource, + sc_faddr_t address); + +/*! + * This function is used to set parameters for CPU resume from + * low-power mode. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] isPrimary set SC_TRUE if primary wake CPU + * @param[in] address 64-bit resume address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + */ +sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t isPrimary, sc_faddr_t address); + +/*! + * This function requests the power mode configuration for system-level + * interfaces including messaging units, interconnect, and memories. This API + * is only valid for the following resources : SC_R_A53, SC_R_A72, and + * SC_R_M4_x_PID_y. For all other resources, it will return SC_ERR_PARAM. + * The requested power mode will be captured and applied to system-level + * resources as system conditions allow. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] sys_if system-level interface to be configured + * @param[in] hpm high-power mode for the system interface + * @param[in] lpm low-power mode for the system interface + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm); + +/* @} */ + +/*! + * @name Clock/PLL Functions + * @{ + */ + +/*! + * This function sets the rate of a resource's clock/PLL. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock/PLL to affect + * @param[in,out] rate pointer to rate to set, + * return actual rate + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock/PLL, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource, + * - SC_ERR_LOCKED if rate locked (usually because shared clock/PLL) + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. + */ +sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + +/*! + * This function gets the rate of a resource's clock/PLL. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock/PLL to affect + * @param[out] rate pointer to return rate + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock/PLL, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. + */ +sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + +/*! + * This function enables/disables a resource's clock. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[in] enable enable if SC_TRUE; otherwise disabled + * @param[in] autog HW auto clock gating + * + * If \a resource is SC_R_ALL then all resources owned will be affected. + * No error will be returned. + * + * If \a clk is SC_PM_CLK_ALL, then an error will be returned if any + * of the available clocks returns an error. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); + +/*! + * This function sets the parent of a resource's clock. + * This function should only be called when the clock is disabled. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[in] parent New parent of the clock. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * - SC_ERR_BUSY if clock is currently enabled. + * - SC_ERR_NOPOWER if resource not powered + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t parent); + +/*! + * This function gets the parent of a resource's clock. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[out] parent pointer to return parent of clock. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent); + +/* @} */ + +/*! + * @name Reset Functions + * @{ + */ + +/*! + * This function is used to reset the system. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. + * + * @param[in] ipc IPC handle + * @param[in] type reset type + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid type, + * - SC_ERR_NOACCESS if caller cannot access SC_R_SYSTEM + * + * If this function returns, then the reset did not occur due to an + * invalid parameter. + */ +sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type); + +/*! + * This function gets a caller's reset reason. + * + * @param[in] ipc IPC handle + * @param[out] reason pointer to return the reset reason + * + * This function returns the reason a partition was reset. If the reason + * is POR, then the system reset reason will be returned. + * + * Note depending on the connection of the WDOG_OUT signal and the OTP + * programming of the PMIC, some resets may trigger a system POR + * and the original reason will be lost. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason); + +/*! + * This function gets the partition that caused a reset. + * + * @param[in] ipc IPC handle + * @param[out] pt pointer to return the resetting partition + * + * If the reset reason obtained via sc_pm_reset_reason() is POR then the + * result from this function will be 0. Some SECO causes of reset will + * also return 0. + * + * Note depending on the connection of the WDOG_OUT signal and the OTP + * programming of the PMIC, some resets may trigger a system POR + * and the partition info will be lost. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_pm_get_reset_part(sc_ipc_t ipc, sc_rm_pt_t *pt); + +/*! + * This function is used to boot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to boot + * @param[in] resource_cpu ID of the CPU resource to start + * @param[in] boot_addr 64-bit boot address + * @param[in] resource_mu ID of the MU that must be powered + * @param[in] resource_dev ID of the boot device that must be powered + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition, resource, or addr, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * partition to boot + * + * This must be used to boot a partition. Only a partition booted this + * way can be rebooted using the watchdog, sc_pm_boot() or + * sc_pm_reboot_partition(). + */ +sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); + +/*! + * This function is used to change the boot parameters for a partition. + * + * @param[in] ipc IPC handle + * @param[in] resource_cpu ID of the CPU resource to start + * @param[in] boot_addr 64-bit boot address + * @param[in] resource_mu ID of the MU that must be powered (0=none) + * @param[in] resource_dev ID of the boot device that must be powered (0=none) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource, or addr + * + * This function can be used to change the boot parameters for a partition. + * This can be useful if a partitions reboots differently from the initial + * boot done via sc_pm_boot() or via ROM. + */ +sc_err_t sc_pm_set_boot_parm(sc_ipc_t ipc, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); + +/*! + * This function is used to reboot the caller's partition. + * + * @param[in] ipc IPC handle + * @param[in] type reset type + * + * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by + * the calling partition will be reset if possible. SC state (partitions, + * power, clocks, etc.) is reset. The boot SW of the booting CPU must be + * able to handle peripherals that that are not reset. + * + * If \a type is SC_PM_RESET_TYPE_WARM or SC_PM_RESET_TYPE_BOARD, then + * returns SC_ERR_PARM as these are not supported. + * + * If this function returns, then the reset did not occur due to an + * invalid parameter. + */ +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); + +/*! + * This function is used to reboot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to reboot + * @param[in] type reset type + * + * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by + * the calling partition will be reset if possible. SC state (partitions, + * power, clocks, etc.) is reset. The boot SW of the booting CPU must be + * able to handle peripherals that that are not reset. + * + * If \a type is SC_PM_RESET_TYPE_WARM or SC_PM_RESET_TYPE_BOARD, then + * returns SC_ERR_PARM as these are not supported. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition or type + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt + * and the caller does not have access to SC_R_SYSTEM + * + * Most peripherals owned by the partition will be reset if + * possible. SC state (partitions, power, clocks, etc.) is reset. The + * boot SW of the booting CPU must be able to handle peripherals that + * that are not reset. + * + * If board_reboot_part() returns a non-0 mask, then the reboot will + * be delayed until all partitions indicated in the mask have called + * sc_pm_reboot_continue() to continue the boot. + */ +sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_reset_type_t type); + +/*! + * This function is used to continue the reboot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to continue + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition + */ +sc_err_t sc_pm_reboot_continue(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function is used to start/stop a CPU. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] enable start if SC_TRUE; otherwise stop + * @param[in] address 64-bit boot address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + * + * This function is usually used to start a secondar CPU in the + * same partition as the caller. It is not used to start the first + * CPU in a dedicated partition. That would be started by calling + * sc_pm_boot(). + * + * A CPU started with sc_pm_cpu_start() will not restart as a result + * of a watchdog event or calling sc_pm_reboot() or sc_pm_reboot_partition(). + * Those will reboot that partition which will start the CPU started with + * sc_pm_boot(). + */ +sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address); + +/*! + * This function is used to reset a CPU. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] address 64-bit boot address + * + * This function does not return anything as the calling core may have been + * reset. It can still fail if the resource or address is invalid. It can also + * fail if the caller's partition is not the owner of the CPU, not the parent + * of the CPU resource owner, or has access to SC_R_SYSTEM. Will also fail if + * the resource is not powered on. No indication of failure is returned. + * + * Note this just resets the CPU. None of the peripherals or bus fabric used by + * the CPU is reset. State configured in the SCFW is not reset. The SW running + * on the core has to understand and deal with this. + */ +void sc_pm_cpu_reset(sc_ipc_t ipc, sc_rsrc_t resource, sc_faddr_t address); + +/*! + * This function returns a bool indicating if a partition was started. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to check + * + * @return Returns a bool (SC_TRUE = started). + * + * Note this indicates if a partition was started. It does not indicate if a + * partition is currently running or in a low power state. + */ +sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); + +/* @} */ + +#endif /* SC_PM_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/mach-imx/sci/svc/rm/api.h b/arch/arm/include/asm/mach-imx/sci/svc/rm/api.h new file mode 100644 index 00000000000..8ac304e80fc --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/svc/rm/api.h @@ -0,0 +1,852 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Resource Management (RM) function. This includes functions for + * partitioning resources, pads, and memory regions. + * + * @addtogroup RM_SVC (SVC) Resource Management Service + * + * Module for the Resource Management (RM) service. + * + * @includedoc rm/details.dox + * + * @{ + */ + +#ifndef SC_RM_API_H +#define SC_RM_API_H + +/* Includes */ + +#include + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_RM_PARTITION_W 5U /*!< Width of sc_rm_pt_t */ +#define SC_RM_MEMREG_W 6U /*!< Width of sc_rm_mr_t */ +#define SC_RM_DID_W 4U /*!< Width of sc_rm_did_t */ +#define SC_RM_SID_W 6U /*!< Width of sc_rm_sid_t */ +#define SC_RM_SPA_W 2U /*!< Width of sc_rm_spa_t */ +#define SC_RM_PERM_W 3U /*!< Width of sc_rm_perm_t */ +/*@}*/ + +/*! + * @name Defines for ALL parameters + */ +/*@{*/ +#define SC_RM_PT_ALL ((sc_rm_pt_t) UINT8_MAX) /*!< All partitions */ +#define SC_RM_MR_ALL ((sc_rm_mr_t) UINT8_MAX) /*!< All memory regions */ +/*@}*/ + +/*! + * @name Defines for sc_rm_spa_t + */ +/*@{*/ +#define SC_RM_SPA_PASSTHRU 0U /*!< Pass through (attribute driven by master) */ +#define SC_RM_SPA_PASSSID 1U /*!< Pass through and output on SID */ +#define SC_RM_SPA_ASSERT 2U /*!< Assert (force to be secure/privileged) */ +#define SC_RM_SPA_NEGATE 3U /*!< Negate (force to be non-secure/user) */ +/*@}*/ + +/*! + * @name Defines for sc_rm_perm_t + */ +/*@{*/ +#define SC_RM_PERM_NONE 0U /*!< No access */ +#define SC_RM_PERM_SEC_R 1U /*!< Secure RO */ +#define SC_RM_PERM_SECPRIV_RW 2U /*!< Secure privilege R/W */ +#define SC_RM_PERM_SEC_RW 3U /*!< Secure R/W */ +#define SC_RM_PERM_NSPRIV_R 4U /*!< Secure R/W, non-secure privilege RO */ +#define SC_RM_PERM_NS_R 5U /*!< Secure R/W, non-secure RO */ +#define SC_RM_PERM_NSPRIV_RW 6U /*!< Secure R/W, non-secure privilege R/W */ +#define SC_RM_PERM_FULL 7U /*!< Full access */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare a resource partition. + */ +typedef uint8_t sc_rm_pt_t; + +/*! + * This type is used to declare a memory region. + */ +typedef uint8_t sc_rm_mr_t; + +/*! + * This type is used to declare a resource domain ID used by the + * isolation HW. + */ +typedef uint8_t sc_rm_did_t; + +/*! + * This type is used to declare an SMMU StreamID. + */ +typedef uint16_t sc_rm_sid_t; + +/*! + * This type is a used to declare master transaction attributes. + */ +typedef uint8_t sc_rm_spa_t; + +/*! + * This type is used to declare a resource/memory region access permission. + * Refer to the XRDC2 Block Guide for more information. + */ +typedef uint8_t sc_rm_perm_t; + +/* Functions */ + +/*! + * @name Partition Functions + * @{ + */ + +/*! + * This function requests that the SC create a new resource partition. + * + * @param[in] ipc IPC handle + * @param[out] pt return handle for partition; used for subsequent function + * calls associated with this partition + * @param[in] secure boolean indicating if this partition should be secure; only + * valid if caller is secure + * @param[in] isolated boolean indicating if this partition should be HW isolated + * via XRDC; set SC_TRUE if new DID is desired + * @param[in] restricted boolean indicating if this partition should be restricted; set + * SC_TRUE if masters in this partition cannot create new partitions + * @param[in] grant boolean indicating if this partition should always grant + * access and control to the parent + * @param[in] coherent boolean indicating if this partition is coherent; + * set SC_TRUE if only this partition will contain both AP clusters + * and they will be coherent via the CCI + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_ERR_PARM if caller's partition is not secure but a new secure partition is requested, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_UNAVAILABLE if partition table is full (no more allocation space) + * + * Marking as non-secure prevents subsequent functions from configuring masters in this + * partition to assert the secure signal. Basically, if TrustZone SW is used, the Cortex-A + * cores and peripherals the TZ SW will use should be in a secure partition. Almost all + * other partitions (for a non-secure OS or M4 cores) should be in non-secure partitions. + * + * Isolated should be true for almost all partitions. The exception is the non-secure + * partition for a Cortex-A core used to run a non-secure OS. This isn't isolated by + * domain but is instead isolated by the TZ security hardware. + * + * If restricted then the new partition is limited in what functions it can call, + * especially those associated with managing partitions. + * + * The grant option is usually used to isolate a bus master's traffic to specific + * memory without isolating the peripheral interface of the master or the API + * controls of that master. This is only used when creating a sub-partition with + * no CPU. It's useful to separate out a master and the memory it uses. + */ +sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t coherent); + +/*! + * This function makes a partition confidential. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition that is granting + * @param[in] retro retroactive + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a pt out of range, + * - SC_ERR_NOACCESS if caller's not allowed to change \a pt + * - SC_ERR_LOCKED if partition \a pt is locked + * + * Call to make a partition confidential. Confidential means only this + * partition should be able to grant access permissions to this partition. + * + * If retroactive, then all resources owned by other partitions will have + * access rights for this partition removed, even if locked. + */ +sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro); + +/*! + * This function frees a partition and assigns all resources to the caller. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to free + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if \a pt out of range or invalid, + * - SC_ERR_NOACCESS if \a pt is the SC partition, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if \a pt or caller's partition is locked + * + * All resources, memory regions, and pads are assigned to the caller/parent. + * The partition watchdog is disabled (even if locked). DID is freed. + */ +sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function returns the DID of a partition. + * + * @param[in] ipc IPC handle + * + * @return Returns the domain ID (DID) of the caller's partition. + * + * The DID is a SoC-specific internal ID used by the HW resource + * protection mechanism. It is only required by clients when using the + * SEMA42 module as the DID is sometimes connected to the master ID. + */ +sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc); + +/*! + * This function forces a partition to use a specific static DID. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to assign \a did + * @param[in] did static DID to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if \a pt or \a did out of range, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if \a pt is locked + * + * Assumes no assigned resources or memory regions yet! The number of static + * DID is fixed by the SC at boot. + */ +sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_did_t did); + +/*! + * This function locks a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to lock + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a pt out of range, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt + * + * If a partition is locked it cannot be freed, have resources/pads assigned + * to/from it, memory regions created/assigned, DID changed, or parent changed. + */ +sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function gets the partition handle of the caller. + * + * @param[in] ipc IPC handle + * @param[out] pt return handle for caller's partition + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt); + +/*! + * This function sets a new parent for a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition for which parent is to be + * changed + * @param[in] pt_parent handle of partition to set as parent + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if either partition is locked + */ +sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_pt_t pt_parent); + +/*! + * This function moves all movable resources/pads owned by a source partition + * to a destination partition. It can be used to more quickly set up a new + * partition if a majority of the caller's resources are to be moved to a + * new partition. + * + * @param[in] ipc IPC handle + * @param[in] pt_src handle of partition from which resources should + * be moved from + * @param[in] pt_dst handle of partition to which resources should be + * moved to + * @param[in] move_rsrc boolean to indicate if resources should be moved + * @param[in] move_pads boolean to indicate if pads should be moved + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * By default, all resources are movable. This can be changed using the + * sc_rm_set_resource_movable() function. Note all masters defaulted to SMMU + * bypass. + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not \a pt_src or the + * parent of \a pt_src, + * - SC_ERR_LOCKED if either partition is locked + */ +sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst, + sc_bool_t move_rsrc, sc_bool_t move_pads); + +/* @} */ + +/*! + * @name Resource Functions + * @{ + */ + +/*! + * This function assigns ownership of a resource to a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to which resource should be + * assigned + * @param[in] resource resource to assign + * + * This function assigned a resource to a partition. This partition is then + * the owner. All resources always have an owner (one owner). The owner + * has various rights to make API calls affecting the resource. Ownership + * does not imply access to the peripheral itself (that is based on access + * rights). + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * This action resets the resource's master and peripheral attributes. + * Privilege attribute will be PASSTHRU, security attribute will be + * ASSERT if the partition si secure and NEGATE if it is not, and + * masters will defaulted to SMMU bypass. Access permissions will reset + * to SEC_RW for the owning partition only for secure partitions, FULL for + * non-secure. Default is no access by other partitions. + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource); + +/*! + * This function flags resources as movable or not. + * + * @param[in] ipc IPC handle + * @param[in] resource_fst first resource for which flag should be set + * @param[in] resource_lst last resource for which flag should be set + * @param[in] movable movable flag (SC_TRUE is movable) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if resources are out of range, + * - SC_ERR_NOACCESS if caller's partition is not a parent of a resource owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function is used to determine the set of resources that will be + * moved using the sc_rm_move_all() function. All resources are movable + * by default so this function is normally used to prevent a set of + * resources from moving. + */ +sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst, + sc_rsrc_t resource_lst, sc_bool_t movable); + +/*! + * This function flags all of a subsystem's resources as movable + * or not. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to use to identify subsystem + * @param[in] movable movable flag (SC_TRUE is movable) + * + * A subsystem is a physical grouping within the chip of related resources; + * this is SoC specific. This function is used to optimize moving resource + * for these groupings, for instance, an M4 core and its associated resources. + * The list of subsystems and associated resources can be found in the + * SoC-specific API document [Resources](@ref RESOURCES) chapter. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if a function argument is out of range + * + * Note \a resource is used to find the associated subsystem. Only + * resources owned by the caller are set. + */ +sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t movable); + +/*! + * This function sets attributes for a resource which is a bus master (i.e. + * capable of DMA). + * + * @param[in] ipc IPC handle + * @param[in] resource master resource for which attributes should apply + * @param[in] sa security attribute + * @param[in] pa privilege attribute + * @param[in] smmu_bypass SMMU bypass mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not a parent of the resource owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * Masters are IP blocks that generate bus transactions. This function configures + * how the isolation HW will define these bus transactions from the specified master. + * Note the security attribute will only be changed if the caller's partition is + * secure. + * + * Note an IP block can be both a master and peripheral (have both a programming model + * and generate bus transactions). + */ +sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass); + +/*! + * This function sets the StreamID for a resource which is a bus master (i.e. + * capable of DMA). + * + * @param[in] ipc IPC handle + * @param[in] resource master resource for which attributes should apply + * @param[in] sid StreamID + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function configures the SID attribute associated with all bus transactions + * from this master. Note 0 is not a valid SID as it is reserved to indicate + * bypass. + */ +sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t sid); + +/*! + * This function sets access permissions for a peripheral resource. + * + * @param[in] ipc IPC handle + * @param[in] resource peripheral resource for which permissions should apply + * @param[in] pt handle of partition \a perm should by applied for + * @param[in] perm permissions to apply to \a resource for \a pt + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt + * + * Peripherals are IP blocks that have a programming model that can be + * accessed. + * + * This function configures how the isolation HW will restrict access to a + * peripheral based on the attributes of a transaction from bus master. It + * also allows the access permissions of SC_R_SYSTEM to be set. + * + * Note an IP block can be both a master and peripheral (have both a programming + * model and generate bus transactions). + */ +sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t pt, sc_rm_perm_t perm); + +/*! + * This function gets ownership status of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the resource). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to get the owner of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * @param[out] pt pointer to return owning partition + * + * @return Returns a boolean (SC_TRUE if the resource is a bus master). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid + * + * If \a resource is out of range then SC_ERR_PARM is returned. + */ +sc_err_t sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t *pt); + +/*! + * This function is used to test if a resource is a bus master. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * Masters are IP blocks that generate bus transactions. Note an IP block + * can be both a master and peripheral (have both a programming model + * and generate bus transactions). + * + * @return Returns a boolean (SC_TRUE if the resource is a bus master). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to test if a resource is a peripheral. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * Peripherals are IP blocks that have a programming model that can be + * accessed. Note an IP block can be both a master and peripheral (have + * both a programming model and generate bus transactions) + * + * @return Returns a boolean (SC_TRUE if the resource is a peripheral). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to obtain info about a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to inquire about + * @param[out] sid pointer to return StreamID + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a resource is out of range + */ +sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t *sid); + +/* @} */ + +/*! + * @name Memory Region Functions + * @{ + */ + +/*! + * This function requests that the SC create a new memory region. + * + * @param[in] ipc IPC handle + * @param[out] mr return handle for region; used for + * subsequent function calls + * associated with this region + * @param[in] addr_start start address of region (physical) + * @param[in] addr_end end address of region (physical) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if the new memory region is misaligned, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_PARM if the new memory region spans multiple existing regions, + * - SC_ERR_NOACCESS if caller's partition does not own the memory containing + * the new region, + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation + * space) + * + * The area covered by the memory region must currently be owned by the caller. + * By default, the new region will have access permission set to allow the + * caller to access. + */ +sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function requests that the SC split a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to split + * @param[out] mr_ret return handle for new region; used for + * subsequent function calls + * associated with this region + * @param[in] addr_start start address of region (physical) + * @param[in] addr_end end address of region (physical) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if the new memory region is not start/end part of mr, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_PARM if the new memory region spans multiple existing regions, + * - SC_ERR_NOACCESS if caller's partition does not own the memory containing + * the new region, + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation + * space) + * + * Note the new region must start or end on the split region. + */ +sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function requests that the SC fragment a memory region. + * + * @param[in] ipc IPC handle + * @param[out] mr_ret return handle for new region; used for + * subsequent function calls + * associated with this region + * @param[in] addr_start start address of region (physical) + * @param[in] addr_end end address of region (physical) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_PARM if the new memory region spans multiple existing regions, + * - SC_ERR_NOACCESS if caller's partition does not own the memory containing + * the new region, + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation + * space) + * + * This function finds the memory region containing the address range. + * It then splits it as required and returns the extracted region. + */ +sc_err_t sc_rm_memreg_frag(sc_ipc_t ipc, sc_rm_mr_t *mr_ret, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function frees a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to free + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a mr out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not a parent of \a mr, + * - SC_ERR_LOCKED if the owning partition of \a mr is locked + */ +sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr); + +/*! + * Internal SC function to find a memory region. + * + * @see sc_rm_find_memreg(). + */ +/*! + * This function finds a memory region. + * + * @param[in] ipc IPC handle + * @param[out] mr return handle for region; used for + * subsequent function calls + * associated with this region + * @param[in] addr_start start address of region to search for + * @param[in] addr_end end address of region to search for + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOTFOUND if region not found, + * + * Searches only for regions owned by the caller. Finds first + * region containing the range specified. + */ +sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function assigns ownership of a memory region. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to which memory region + * should be assigned + * @param[in] mr handle of memory region to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the \a mr owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr); + +/*! + * This function sets access permissions for a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region for which permissions + * should apply + * @param[in] pt handle of partition \a perm should by + * applied for + * @param[in] perm permissions to apply to \a mr for \a pt + * + * This function assigned a memory region to a partition. This partition is then + * the owner. All regions always have an owner (one owner). The owner + * has various rights to make API calls affecting the region. Ownership + * does not imply access to the memory itself (that is based on access + * rights). + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the region owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt + * + * This function configures how the HW isolation will restrict access to a + * memory region based on the attributes of a transaction from bus master. + */ +sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm); + +/*! + * This function gets ownership status of a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the + * memory region). + * + * If \a mr is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); + +/*! + * This function is used to obtain info about a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to inquire about + * @param[out] addr_start pointer to return start address + * @param[out] addr_end pointer to return end address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a mr is out of range + */ +sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_faddr_t *addr_start, sc_faddr_t *addr_end); + +/* @} */ + +/*! + * @name Pad Functions + * @{ + */ + +/*! + * This function assigns ownership of a pad to a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to which pad should + * be assigned + * @param[in] pad pad to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad); + +/*! + * This function flags pads as movable or not. + * + * @param[in] ipc IPC handle + * @param[in] pad_fst first pad for which flag should be set + * @param[in] pad_lst last pad for which flag should be set + * @param[in] movable movable flag (SC_TRUE is movable) + * + * This function assigned a pad to a partition. This partition is then + * the owner. All pads always have an owner (one owner). The owner + * has various rights to make API calls affecting the pad. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if pads are out of range, + * - SC_ERR_NOACCESS if caller's partition is not a parent of a pad owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function is used to determine the set of pads that will be + * moved using the sc_rm_move_all() function. All pads are movable + * by default so this function is normally used to prevent a set of + * pads from moving. + */ +sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst, + sc_pad_t pad_lst, sc_bool_t movable); + +/*! + * This function gets ownership status of a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the pad). + * + * If \a pad is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad); + +/* @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function dumps the RM state for debug. + * + * @param[in] ipc IPC handle + */ +void sc_rm_dump(sc_ipc_t ipc); + +/* @} */ + +#endif /* SC_RM_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/mach-imx/sci/svc/seco/api.h b/arch/arm/include/asm/mach-imx/sci/svc/seco/api.h new file mode 100644 index 00000000000..529028c5a51 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/svc/seco/api.h @@ -0,0 +1,512 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Security (SECO) function. + * + * @addtogroup SECO_SVC (SVC) Security Service + * + * Module for the Security (SECO) service. + * + * @{ + */ + +#ifndef SC_SECO_API_H +#define SC_SECO_API_H + +/* Includes */ + +#include +#include + +/* Defines */ + +/*! + * @name Defines for sc_seco_auth_cmd_t + */ +/*@{*/ +#define SC_SECO_AUTH_CONTAINER 0U /*!< Authenticate container */ +#define SC_SECO_VERIFY_IMAGE 1U /*!< Verify image */ +#define SC_SECO_REL_CONTAINER 2U /*!< Release container */ +#define SC_SECO_AUTH_SECO_FW 3U /*!< SECO Firmware */ +#define SC_SECO_AUTH_HDMI_TX_FW 4U /*!< HDMI TX Firmware */ +#define SC_SECO_AUTH_HDMI_RX_FW 5U /*!< HDMI RX Firmware */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to issue SECO authenticate commands. + */ +typedef uint8_t sc_seco_auth_cmd_t; + +/* Functions */ + +/*! + * @name Image Functions + * @{ + */ + +/*! + * This function loads a SECO image. + * + * @param[in] ipc IPC handle + * @param[in] addr_src address of image source + * @param[in] addr_dst address of image destination + * @param[in] len lenth of image to load + * @param[in] fw SC_TRUE = firmware load + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This is used to load images via the SECO. Examples include SECO + * Firmware and IVT/CSF data used for authentication. These are usually + * loaded into SECO TCM. \a addr_src is in secure memory. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw); + +/*! + * This function is used to authenticate a SECO image or command. + * + * @param[in] ipc IPC handle + * @param[in] cmd authenticate command + * @param[in] addr address of/or metadata + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This is used to authenticate a SECO image or issue a security + * command. \a addr often points to an container. It is also + * just data (or even unused) for some commands. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_authenticate(sc_ipc_t ipc, + sc_seco_auth_cmd_t cmd, sc_faddr_t addr); + +/* @} */ + +/*! + * @name Lifecycle Functions + * @{ + */ + +/*! + * This function updates the lifecycle of the device. + * + * @param[in] ipc IPC handle + * @param[in] change desired lifecycle transistion + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This message is used for going from Open to NXP Closed to OEM Closed. + * Note \a change is NOT the new desired lifecycle. It is a lifecycle + * transition as documented in the Security Reference Manual (SRM). + * + * If any SECO request fails or only succeeds because the part is in an + * "OEM open" lifecycle, then a request to transition from "NXP closed" + * to "OEM closed" will also fail. For example, booting a signed container + * when the OEM SRK is not fused will succeed, but as it is an abnormal + * situation, a subsequent request to transition the lifecycle will return + * an error. + */ +sc_err_t sc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change); + +/*! + * This function updates the lifecycle to one of the return lifecycles. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * Note \a addr must be a pointer to a signed message block. + * + * To switch back to NXP states (Full Field Return), message must be signed + * by NXP SRK. For OEM States (Partial Field Return), must be signed by OEM + * SRK. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to commit into the fuses any new SRK revocation + * and FW version information that have been found in the primary and + * secondary containers. + * + * @param[in] ipc IPC handle + * @param[in,out] info pointer to information type to be committed + * + * The return \a info will contain what was actually committed. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a info is invalid + * - SC_ERR_UNAVAILABLE if SECO not available + */ +sc_err_t sc_seco_commit(sc_ipc_t ipc, uint32_t *info); + +/* @} */ + +/*! + * @name Attestation Functions + * @{ + */ + +/*! + * This function is used to set the attestation mode. Only the owner of + * the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] mode mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a mode is invalid + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This is used to set the SECO attestation mode. This can be prover + * or verfier. See the Security Reference Manual (SRM) for more on the + * suported modes, mode values, and mode behavior. + */ +sc_err_t sc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode); + +/*! + * This function is used to request atestation. Only the owner of + * the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] nonce unique value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This is used to ask SECO to perform an attestation. The result depends + * on the attestation mode. After this call, the signature can be + * requested or a verify can be requested. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_attest(sc_ipc_t ipc, uint64_t nonce); + +/*! + * This function is used to retrieve the attestation public key. + * Mode must be verifier. Only the owner of the SC_R_ATTESTATION resource + * may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address to write response + * + * Result will be written to \a addr. The \a addr parmater must point + * to an address SECO can access. It must be 64-bit aligned. There + * should be 96 bytes of space. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller + * - SC_ERR_UNAVAILABLE if SECO not available + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to retrieve attestation signature and parameters. + * Mode must be provider. Only the owner of the SC_R_ATTESTATION resource + * may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address to write response + * + * Result will be written to \a addr. The \a addr parmater must point + * to an address SECO can access. It must be 64-bit aligned. There + * should be 120 bytes of space. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller + * - SC_ERR_UNAVAILABLE if SECO not available + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to verify attestation. Mode must be verifier. + * Only the owner of the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address of signature + * + * The \a addr parmater must point to an address SECO can access. It must be + * 64-bit aligned. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller + * - SC_ERR_UNAVAILABLE if SECO not available + * - SC_ERR_FAIL if signature doesn't match + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr); + +/* @} */ + +/*! + * @name Key Functions + * @{ + */ + +/*! + * This function is used to generate a SECO key blob. + * + * @param[in] ipc IPC handle + * @param[in] id key identifier + * @param[in] load_addr load address + * @param[in] export_addr export address + * @param[in] max_size max export size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This function is used to encapsulate sensitive keys in a specific structure + * called a blob, which provides both confidentiality and integrity protection. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_gen_key_blob(sc_ipc_t ipc, uint32_t id, + sc_faddr_t load_addr, sc_faddr_t export_addr, uint16_t max_size); + +/*! + * This function is used to load a SECO key. + * + * @param[in] ipc IPC handle + * @param[in] id key identifier + * @param[in] addr key address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This function is used to install private cryptographic keys encapsulated + * in a blob previously generated by SECO. The controller can be either the + * IEE or the VPU. The blob header carries the controller type and the key + * size, as provided by the user when generating the key blob. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_load_key(sc_ipc_t ipc, uint32_t id, + sc_faddr_t addr); + +/* @} */ + +/*! + * @name Manufacturing Protection Functions + * @{ + */ + +/*! + * This function is used to get the manufacturing protection public key. + * + * @param[in] ipc IPC handle + * @param[in] dst_addr destination address + * @param[in] dst_size destination size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This function is supported only in OEM-closed lifecycle. It generates + * the mfg public key and stores it in a specific location in the secure + * memory. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, + uint16_t dst_size); + +/*! + * This function is used to update the manufacturing protection message + * register. + * + * @param[in] ipc IPC handle + * @param[in] addr data address + * @param[in] size size + * @param[in] lock lock_reg + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This function is supported only in OEM-closed lifecycle. It updates the + * content of the MPMR (Manufacturing Protection Message register of 256 + * bits). This register will be appended to the input-data message when + * generating the signature. Please refer to the CAAM block guide for details. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, + uint8_t size, uint8_t lock); + +/*! + * This function is used to get the manufacturing protection signature. + * + * @param[in] ipc IPC handle + * @param[in] msg_addr message address + * @param[in] msg_size message size + * @param[in] dst_addr destination address + * @param[in] dst_size destination size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This function is used to generate an ECDSA signature for an input-data + * message and to store it in a specific location in the secure memory. It + * is only supported in OEM-closed lifecycle. In order to get the ECDSA + * signature, the RNG must be initialized. In case it has not been started + * an error will be returned. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, + uint16_t msg_size, sc_faddr_t dst_addr, uint16_t dst_size); + +/* @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function is used to return the SECO FW build info. + * + * @param[in] ipc IPC handle + * @param[out] version pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + */ +void sc_seco_build_info(sc_ipc_t ipc, uint32_t *version, + uint32_t *commit); + +/*! + * This function is used to return SECO chip info. + * + * @param[in] ipc IPC handle + * @param[out] lc pointer to return lifecycle + * @param[out] monotonic pointer to return monotonic counter + * @param[out] uid_l pointer to return UID (lower 32 bits) + * @param[out] uid_h pointer to return UID (upper 32 bits) + * + * @return Returns and error code (SC_ERR_NONE = success). + */ +sc_err_t sc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc, + uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h); + +/*! + * This function securely enables debug. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * Note \a addr must be a pointer to a signed message block. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to return an event from the SECO error log. + * + * @param[in] ipc IPC handle + * @param[out] idx index of event to return + * @param[out] event pointer to return event + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Read of \a idx 0 captures events from SECO. Loop starting + * with 0 until an error is returned to dump all events. + */ +sc_err_t sc_seco_get_event(sc_ipc_t ipc, uint8_t idx, + uint32_t *event); + +/* @} */ + +/*! + * @name Miscellaneous Functions + * @{ + */ + +/*! + * This function securely writes a group of fuse words. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * Note \a addr must be a pointer to a signed message block. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr); + +/* @} */ + +#endif /* SC_SECO_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/mach-imx/sci/svc/timer/api.h b/arch/arm/include/asm/mach-imx/sci/svc/timer/api.h new file mode 100644 index 00000000000..bd1ccbd5bfd --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/svc/timer/api.h @@ -0,0 +1,364 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Timer function. + * + * @addtogroup TIMER_SVC (SVC) Timer Service + * + * Module for the Timer service. This includes support for the watchdog, RTC, + * and system counter. Note every resource partition has a watchdog it can + * use. + * + * @{ + */ + +#ifndef SC_TIMER_API_H +#define SC_TIMER_API_H + +/* Includes */ + +#include +#include + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_TIMER_ACTION_W 3U /*!< Width of sc_timer_wdog_action_t */ +/*@}*/ + +/*! + * @name Defines for sc_timer_wdog_action_t + */ +/*@{*/ +#define SC_TIMER_WDOG_ACTION_PARTITION 0U /*!< Reset partition */ +#define SC_TIMER_WDOG_ACTION_WARM 1U /*!< Warm reset system */ +#define SC_TIMER_WDOG_ACTION_COLD 2U /*!< Cold reset system */ +#define SC_TIMER_WDOG_ACTION_BOARD 3U /*!< Reset board */ +#define SC_TIMER_WDOG_ACTION_IRQ 4U /*!< Only generate IRQs */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to configure the watchdog action. + */ +typedef uint8_t sc_timer_wdog_action_t; + +/*! + * This type is used to declare a watchdog time value in milliseconds. + */ +typedef uint32_t sc_timer_wdog_time_t; + +/* Functions */ + +/*! + * @name Wathdog Functions + * @{ + */ + +/*! + * This function sets the watchdog timeout in milliseconds. If not + * set then the timeout defaults to the max. Once locked this value + * cannot be changed. + * + * @param[in] ipc IPC handle + * @param[in] timeout timeout period for the watchdog + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED + * = locked). + */ +sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t timeout); + +/*! + * This function sets the watchdog pre-timeout in milliseconds. If not + * set then the pre-timeout defaults to the max. Once locked this value + * cannot be changed. + * + * @param[in] ipc IPC handle + * @param[in] pre_timeout pre-timeout period for the watchdog + * + * When the pre-timout expires an IRQ will be generated. Note this timeout + * clears when the IRQ is triggered. An IRQ is generated for the failing + * partition and all of its child partitions. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t pre_timeout); + +/*! + * This function starts the watchdog. + * + * @param[in] ipc IPC handle + * @param[in] lock boolean indicating the lock status + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * If \a lock is set then the watchdog cannot be stopped or the timeout + * period changed. + */ +sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock); + +/*! + * This function stops the watchdog if it is not locked. + * + * @param[in] ipc IPC handle + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED + * = locked). + */ +sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc); + +/*! + * This function pings (services, kicks) the watchdog resetting the time + * before expiration back to the timeout. + * + * @param[in] ipc IPC handle + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc); + +/*! + * This function gets the status of the watchdog. All arguments are + * in milliseconds. + * + * @param[in] ipc IPC handle + * @param[out] timeout pointer to return the timeout + * @param[out] max_timeout pointer to return the max timeout + * @param[out] remaining_time pointer to return the time remaining + * until trigger + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout, + sc_timer_wdog_time_t *remaining_time); + +/*! + * This function gets the status of the watchdog of a partition. All + * arguments are in milliseconds. + * + * @param[in] ipc IPC handle + * @param[in] pt partition to query + * @param[out] enb pointer to return enable status + * @param[out] timeout pointer to return the timeout + * @param[out] remaining_time pointer to return the time remaining + * until trigger + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t *enb, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time); + +/*! + * This function configures the action to be taken when a watchdog + * expires. + * + * @param[in] ipc IPC handle + * @param[in] pt partition to affect + * @param[in] action action to take + * + * Default action is inherited from the parent. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid parameters, + * - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner, + * - SC_ERR_LOCKED if the watchdog is locked + */ +sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc, + sc_rm_pt_t pt, sc_timer_wdog_action_t action); + +/* @} */ + +/*! + * @name Real-Time Clock (RTC) Functions + * @{ + */ + +/*! + * This function sets the RTC time. Only the owner of the SC_R_SYSTEM + * resource or a partition with access permissions to SC_R_SYSTEM can + * set the time. + * + * @param[in] ipc IPC handle + * @param[in] year year (min 1970) + * @param[in] mon month (1-12) + * @param[in] day day of the month (1-31) + * @param[in] hour hour (0-23) + * @param[in] min minute (0-59) + * @param[in] sec second (0-59) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters, + * - SC_ERR_NOACCESS if caller's partition cannot access SC_R_SYSTEM + */ +sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); + +/*! + * This function gets the RTC time. + * + * @param[in] ipc IPC handle + * @param[out] year pointer to return year (min 1970) + * @param[out] mon pointer to return month (1-12) + * @param[out] day pointer to return day of the month (1-31) + * @param[out] hour pointer to return hour (0-23) + * @param[out] min pointer to return minute (0-59) + * @param[out] sec pointer to return second (0-59) + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon, + uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec); + +/*! + * This function gets the RTC time in seconds since 1/1/1970. + * + * @param[in] ipc IPC handle + * @param[out] sec pointer to return second + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec); + +/*! + * This function sets the RTC alarm. + * + * @param[in] ipc IPC handle + * @param[in] year year (min 1970) + * @param[in] mon month (1-12) + * @param[in] day day of the month (1-31) + * @param[in] hour hour (0-23) + * @param[in] min minute (0-59) + * @param[in] sec second (0-59) + * + * Note this alarm setting clears when the alarm is triggered. This is an + * absolute time. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); + +/*! + * This function sets the RTC alarm (periodic mode). + * + * @param[in] ipc IPC handle + * @param[in] sec period in seconds + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note this is a relative time. + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec); + +/*! + * This function cancels the RTC alarm. + * + * @param[in] ipc IPC handle + * + * Note this alarm setting clears when the alarm is triggered. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc); + +/*! + * This function sets the RTC calibration value. Only the owner of the SC_R_SYSTEM + * resource or a partition with access permissions to SC_R_SYSTEM can set the + * calibration. + * + * @param[in] ipc IPC handle + * @param[in] count calbration count (-16 to 15) + * + * The calibration value is a 5-bit value including the sign bit, which is + * implemented in 2's complement. It is added or subtracted from the RTC on + * a perdiodic basis, once per 32768 cycles of the RTC clock. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count); + +/* @} */ + +/*! + * @name System Counter (SYSCTR) Functions + * @{ + */ + +/*! + * This function sets the SYSCTR alarm. + * + * @param[in] ipc IPC handle + * @param[in] ticks number of 8MHz cycles + * + * Note the \a ticks parameter is an absolute time. This alarm + * setting clears when the alarm is triggered. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_set_sysctr_alarm(sc_ipc_t ipc, uint64_t ticks); + +/*! + * This function sets the SYSCTR alarm (periodic mode). + * + * @param[in] ipc IPC handle + * @param[in] ticks number of 8MHz cycles + * + * Note the \a ticks parameter is a relative time. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, + uint64_t ticks); + +/*! + * This function cancels the SYSCTR alarm. + * + * @param[in] ipc IPC handle + * + * Note this alarm setting clears when the alarm is triggered. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_cancel_sysctr_alarm(sc_ipc_t ipc); + +/* @} */ + +#endif /* SC_TIMER_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/mach-imx/sci/types.h b/arch/arm/include/asm/mach-imx/sci/types.h new file mode 100644 index 00000000000..5e146c1655a --- /dev/null +++ b/arch/arm/include/asm/mach-imx/sci/types.h @@ -0,0 +1,886 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing types used across multiple service APIs. + */ + +#ifndef SC_TYPES_H +#define SC_TYPES_H + +/* Includes */ + +#include + +/* Defines */ + +#define SCFW_API_VERSION 100U + +/*! + * @name Defines for common frequencies + */ +/*@{*/ +#define SC_32KHZ 32768U /*!< 32KHz */ +#define SC_10MHZ 10000000U /*!< 10MHz */ +#define SC_20MHZ 20000000U /*!< 20MHz */ +#define SC_25MHZ 25000000U /*!< 25MHz */ +#define SC_27MHZ 27000000U /*!< 27MHz */ +#define SC_40MHZ 40000000U /*!< 40MHz */ +#define SC_45MHZ 45000000U /*!< 45MHz */ +#define SC_50MHZ 50000000U /*!< 50MHz */ +#define SC_60MHZ 60000000U /*!< 60MHz */ +#define SC_66MHZ 66666666U /*!< 66MHz */ +#define SC_74MHZ 74250000U /*!< 74.25MHz */ +#define SC_80MHZ 80000000U /*!< 80MHz */ +#define SC_83MHZ 83333333U /*!< 83MHz */ +#define SC_84MHZ 84375000U /*!< 84.37MHz */ +#define SC_100MHZ 100000000U /*!< 100MHz */ +#define SC_125MHZ 125000000U /*!< 125MHz */ +#define SC_133MHZ 133333333U /*!< 133MHz */ +#define SC_135MHZ 135000000U /*!< 135MHz */ +#define SC_150MHZ 150000000U /*!< 150MHz */ +#define SC_160MHZ 160000000U /*!< 160MHz */ +#define SC_166MHZ 166666666U /*!< 166MHz */ +#define SC_175MHZ 175000000U /*!< 175MHz */ +#define SC_180MHZ 180000000U /*!< 180MHz */ +#define SC_200MHZ 200000000U /*!< 200MHz */ +#define SC_250MHZ 250000000U /*!< 250MHz */ +#define SC_266MHZ 266666666U /*!< 266MHz */ +#define SC_300MHZ 300000000U /*!< 300MHz */ +#define SC_312MHZ 312500000U /*!< 312.5MHZ */ +#define SC_320MHZ 320000000U /*!< 320MHz */ +#define SC_325MHZ 325000000U /*!< 325MHz */ +#define SC_333MHZ 333333333U /*!< 333MHz */ +#define SC_350MHZ 350000000U /*!< 350MHz */ +#define SC_372MHZ 372000000U /*!< 372MHz */ +#define SC_375MHZ 375000000U /*!< 375MHz */ +#define SC_400MHZ 400000000U /*!< 400MHz */ +#define SC_500MHZ 500000000U /*!< 500MHz */ +#define SC_594MHZ 594000000U /*!< 594MHz */ +#define SC_625MHZ 625000000U /*!< 625MHz */ +#define SC_640MHZ 640000000U /*!< 640MHz */ +#define SC_648MHZ 648000000U /*!< 648MHz */ +#define SC_650MHZ 650000000U /*!< 650MHz */ +#define SC_667MHZ 666666667U /*!< 667MHz */ +#define SC_675MHZ 675000000U /*!< 675MHz */ +#define SC_700MHZ 700000000U /*!< 700MHz */ +#define SC_720MHZ 720000000U /*!< 720MHz */ +#define SC_750MHZ 750000000U /*!< 750MHz */ +#define SC_753MHZ 753000000U /*!< 753MHz */ +#define SC_793MHZ 793000000U /*!< 793MHz */ +#define SC_800MHZ 800000000U /*!< 800MHz */ +#define SC_850MHZ 850000000U /*!< 850MHz */ +#define SC_858MHZ 858000000U /*!< 858MHz */ +#define SC_900MHZ 900000000U /*!< 900MHz */ +#define SC_953MHZ 953000000U /*!< 953MHz */ +#define SC_963MHZ 963000000U /*!< 963MHz */ +#define SC_1000MHZ 1000000000U /*!< 1GHz */ +#define SC_1060MHZ 1060000000U /*!< 1.06GHz */ +#define SC_1068MHZ 1068000000U /*!< 1.068GHz */ +#define SC_1121MHZ 1121000000U /*!< 1.121GHz */ +#define SC_1173MHZ 1173000000U /*!< 1.173GHz */ +#define SC_1188MHZ 1188000000U /*!< 1.188GHz */ +#define SC_1260MHZ 1260000000U /*!< 1.26GHz */ +#define SC_1278MHZ 1278000000U /*!< 1.278GHz */ +#define SC_1280MHZ 1280000000U /*!< 1.28GHz */ +#define SC_1300MHZ 1300000000U /*!< 1.3GHz */ +#define SC_1313MHZ 1313000000U /*!< 1.313GHz */ +#define SC_1345MHZ 1345000000U /*!< 1.345GHz */ +#define SC_1400MHZ 1400000000U /*!< 1.4GHz */ +#define SC_1500MHZ 1500000000U /*!< 1.5GHz */ +#define SC_1600MHZ 1600000000U /*!< 1.6GHz */ +#define SC_1800MHZ 1800000000U /*!< 1.8GHz */ +#define SC_2000MHZ 2000000000U /*!< 2.0GHz */ +#define SC_2112MHZ 2112000000U /*!< 2.12GHz */ +/*@}*/ + +/*! + * @name Defines for 24M related frequencies + */ +/*@{*/ +#define SC_8MHZ 8000000U /*!< 8MHz */ +#define SC_12MHZ 12000000U /*!< 12MHz */ +#define SC_19MHZ 19800000U /*!< 19.8MHz */ +#define SC_24MHZ 24000000U /*!< 24MHz */ +#define SC_48MHZ 48000000U /*!< 48MHz */ +#define SC_120MHZ 120000000U /*!< 120MHz */ +#define SC_132MHZ 132000000U /*!< 132MHz */ +#define SC_144MHZ 144000000U /*!< 144MHz */ +#define SC_192MHZ 192000000U /*!< 192MHz */ +#define SC_211MHZ 211200000U /*!< 211.2MHz */ +#define SC_240MHZ 240000000U /*!< 240MHz */ +#define SC_264MHZ 264000000U /*!< 264MHz */ +#define SC_352MHZ 352000000U /*!< 352MHz */ +#define SC_360MHZ 360000000U /*!< 360MHz */ +#define SC_384MHZ 384000000U /*!< 384MHz */ +#define SC_396MHZ 396000000U /*!< 396MHz */ +#define SC_432MHZ 432000000U /*!< 432MHz */ +#define SC_480MHZ 480000000U /*!< 480MHz */ +#define SC_600MHZ 600000000U /*!< 600MHz */ +#define SC_744MHZ 744000000U /*!< 744MHz */ +#define SC_792MHZ 792000000U /*!< 792MHz */ +#define SC_864MHZ 864000000U /*!< 864MHz */ +#define SC_960MHZ 960000000U /*!< 960MHz */ +#define SC_1056MHZ 1056000000U /*!< 1056MHz */ +#define SC_1104MHZ 1104000000U /*!< 1104MHz */ +#define SC_1200MHZ 1200000000U /*!< 1.2GHz */ +#define SC_1464MHZ 1464000000U /*!< 1.464GHz */ +#define SC_2400MHZ 2400000000U /*!< 2.4GHz */ +/*@}*/ + +/*! + * @name Defines for A/V related frequencies + */ +/*@{*/ +#define SC_62MHZ 62937500U /*!< 62.9375MHz */ +#define SC_755MHZ 755250000U /*!< 755.25MHz */ +/*@}*/ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_BOOL_W 1U /*!< Width of sc_bool_t */ +#define SC_ERR_W 4U /*!< Width of sc_err_t */ +#define SC_RSRC_W 10U /*!< Width of sc_rsrc_t */ +#define SC_CTRL_W 6U /*!< Width of sc_ctrl_t */ +/*@}*/ + +/*! + * @name Defines for sc_bool_t + */ +/*@{*/ +#define SC_FALSE ((sc_bool_t) 0U) /*!< False */ +#define SC_TRUE ((sc_bool_t) 1U) /*!< True */ +/*@}*/ + +/*! + * @name Defines for sc_err_t. + */ +/*@{*/ +#define SC_ERR_NONE 0U /*!< Success */ +#define SC_ERR_VERSION 1U /*!< Incompatible API version */ +#define SC_ERR_CONFIG 2U /*!< Configuration error */ +#define SC_ERR_PARM 3U /*!< Bad parameter */ +#define SC_ERR_NOACCESS 4U /*!< Permission error (no access) */ +#define SC_ERR_LOCKED 5U /*!< Permission error (locked) */ +#define SC_ERR_UNAVAILABLE 6U /*!< Unavailable (out of resources) */ +#define SC_ERR_NOTFOUND 7U /*!< Not found */ +#define SC_ERR_NOPOWER 8U /*!< No power */ +#define SC_ERR_IPC 9U /*!< Generic IPC error */ +#define SC_ERR_BUSY 10U /*!< Resource is currently busy/active */ +#define SC_ERR_FAIL 11U /*!< General I/O failure */ +#define SC_ERR_LAST 12U +/*@}*/ + +/*! + * @name Defines for sc_rsrc_t. + */ +/*@{*/ +#define SC_R_A53 0U +#define SC_R_A53_0 1U +#define SC_R_A53_1 2U +#define SC_R_A53_2 3U +#define SC_R_A53_3 4U +#define SC_R_A72 5U +#define SC_R_A72_0 6U +#define SC_R_A72_1 7U +#define SC_R_A72_2 8U +#define SC_R_A72_3 9U +#define SC_R_CCI 10U +#define SC_R_DB 11U +#define SC_R_DRC_0 12U +#define SC_R_DRC_1 13U +#define SC_R_GIC_SMMU 14U +#define SC_R_IRQSTR_M4_0 15U +#define SC_R_IRQSTR_M4_1 16U +#define SC_R_SMMU 17U +#define SC_R_GIC 18U +#define SC_R_DC_0_BLIT0 19U +#define SC_R_DC_0_BLIT1 20U +#define SC_R_DC_0_BLIT2 21U +#define SC_R_DC_0_BLIT_OUT 22U +#define SC_R_PERF 23U +#define SC_R_UNUSED5 24U +#define SC_R_DC_0_WARP 25U +#define SC_R_UNUSED7 26U +#define SC_R_UNUSED8 27U +#define SC_R_DC_0_VIDEO0 28U +#define SC_R_DC_0_VIDEO1 29U +#define SC_R_DC_0_FRAC0 30U +#define SC_R_UNUSED6 31U +#define SC_R_DC_0 32U +#define SC_R_GPU_2_PID0 33U +#define SC_R_DC_0_PLL_0 34U +#define SC_R_DC_0_PLL_1 35U +#define SC_R_DC_1_BLIT0 36U +#define SC_R_DC_1_BLIT1 37U +#define SC_R_DC_1_BLIT2 38U +#define SC_R_DC_1_BLIT_OUT 39U +#define SC_R_UNUSED9 40U +#define SC_R_UNUSED10 41U +#define SC_R_DC_1_WARP 42U +#define SC_R_UNUSED11 43U +#define SC_R_UNUSED12 44U +#define SC_R_DC_1_VIDEO0 45U +#define SC_R_DC_1_VIDEO1 46U +#define SC_R_DC_1_FRAC0 47U +#define SC_R_UNUSED13 48U +#define SC_R_DC_1 49U +#define SC_R_UNUSED14 50U +#define SC_R_DC_1_PLL_0 51U +#define SC_R_DC_1_PLL_1 52U +#define SC_R_SPI_0 53U +#define SC_R_SPI_1 54U +#define SC_R_SPI_2 55U +#define SC_R_SPI_3 56U +#define SC_R_UART_0 57U +#define SC_R_UART_1 58U +#define SC_R_UART_2 59U +#define SC_R_UART_3 60U +#define SC_R_UART_4 61U +#define SC_R_EMVSIM_0 62U +#define SC_R_EMVSIM_1 63U +#define SC_R_DMA_0_CH0 64U +#define SC_R_DMA_0_CH1 65U +#define SC_R_DMA_0_CH2 66U +#define SC_R_DMA_0_CH3 67U +#define SC_R_DMA_0_CH4 68U +#define SC_R_DMA_0_CH5 69U +#define SC_R_DMA_0_CH6 70U +#define SC_R_DMA_0_CH7 71U +#define SC_R_DMA_0_CH8 72U +#define SC_R_DMA_0_CH9 73U +#define SC_R_DMA_0_CH10 74U +#define SC_R_DMA_0_CH11 75U +#define SC_R_DMA_0_CH12 76U +#define SC_R_DMA_0_CH13 77U +#define SC_R_DMA_0_CH14 78U +#define SC_R_DMA_0_CH15 79U +#define SC_R_DMA_0_CH16 80U +#define SC_R_DMA_0_CH17 81U +#define SC_R_DMA_0_CH18 82U +#define SC_R_DMA_0_CH19 83U +#define SC_R_DMA_0_CH20 84U +#define SC_R_DMA_0_CH21 85U +#define SC_R_DMA_0_CH22 86U +#define SC_R_DMA_0_CH23 87U +#define SC_R_DMA_0_CH24 88U +#define SC_R_DMA_0_CH25 89U +#define SC_R_DMA_0_CH26 90U +#define SC_R_DMA_0_CH27 91U +#define SC_R_DMA_0_CH28 92U +#define SC_R_DMA_0_CH29 93U +#define SC_R_DMA_0_CH30 94U +#define SC_R_DMA_0_CH31 95U +#define SC_R_I2C_0 96U +#define SC_R_I2C_1 97U +#define SC_R_I2C_2 98U +#define SC_R_I2C_3 99U +#define SC_R_I2C_4 100U +#define SC_R_ADC_0 101U +#define SC_R_ADC_1 102U +#define SC_R_FTM_0 103U +#define SC_R_FTM_1 104U +#define SC_R_CAN_0 105U +#define SC_R_CAN_1 106U +#define SC_R_CAN_2 107U +#define SC_R_DMA_1_CH0 108U +#define SC_R_DMA_1_CH1 109U +#define SC_R_DMA_1_CH2 110U +#define SC_R_DMA_1_CH3 111U +#define SC_R_DMA_1_CH4 112U +#define SC_R_DMA_1_CH5 113U +#define SC_R_DMA_1_CH6 114U +#define SC_R_DMA_1_CH7 115U +#define SC_R_DMA_1_CH8 116U +#define SC_R_DMA_1_CH9 117U +#define SC_R_DMA_1_CH10 118U +#define SC_R_DMA_1_CH11 119U +#define SC_R_DMA_1_CH12 120U +#define SC_R_DMA_1_CH13 121U +#define SC_R_DMA_1_CH14 122U +#define SC_R_DMA_1_CH15 123U +#define SC_R_DMA_1_CH16 124U +#define SC_R_DMA_1_CH17 125U +#define SC_R_DMA_1_CH18 126U +#define SC_R_DMA_1_CH19 127U +#define SC_R_DMA_1_CH20 128U +#define SC_R_DMA_1_CH21 129U +#define SC_R_DMA_1_CH22 130U +#define SC_R_DMA_1_CH23 131U +#define SC_R_DMA_1_CH24 132U +#define SC_R_DMA_1_CH25 133U +#define SC_R_DMA_1_CH26 134U +#define SC_R_DMA_1_CH27 135U +#define SC_R_DMA_1_CH28 136U +#define SC_R_DMA_1_CH29 137U +#define SC_R_DMA_1_CH30 138U +#define SC_R_DMA_1_CH31 139U +#define SC_R_UNUSED1 140U +#define SC_R_UNUSED2 141U +#define SC_R_UNUSED3 142U +#define SC_R_UNUSED4 143U +#define SC_R_GPU_0_PID0 144U +#define SC_R_GPU_0_PID1 145U +#define SC_R_GPU_0_PID2 146U +#define SC_R_GPU_0_PID3 147U +#define SC_R_GPU_1_PID0 148U +#define SC_R_GPU_1_PID1 149U +#define SC_R_GPU_1_PID2 150U +#define SC_R_GPU_1_PID3 151U +#define SC_R_PCIE_A 152U +#define SC_R_SERDES_0 153U +#define SC_R_MATCH_0 154U +#define SC_R_MATCH_1 155U +#define SC_R_MATCH_2 156U +#define SC_R_MATCH_3 157U +#define SC_R_MATCH_4 158U +#define SC_R_MATCH_5 159U +#define SC_R_MATCH_6 160U +#define SC_R_MATCH_7 161U +#define SC_R_MATCH_8 162U +#define SC_R_MATCH_9 163U +#define SC_R_MATCH_10 164U +#define SC_R_MATCH_11 165U +#define SC_R_MATCH_12 166U +#define SC_R_MATCH_13 167U +#define SC_R_MATCH_14 168U +#define SC_R_PCIE_B 169U +#define SC_R_SATA_0 170U +#define SC_R_SERDES_1 171U +#define SC_R_HSIO_GPIO 172U +#define SC_R_MATCH_15 173U +#define SC_R_MATCH_16 174U +#define SC_R_MATCH_17 175U +#define SC_R_MATCH_18 176U +#define SC_R_MATCH_19 177U +#define SC_R_MATCH_20 178U +#define SC_R_MATCH_21 179U +#define SC_R_MATCH_22 180U +#define SC_R_MATCH_23 181U +#define SC_R_MATCH_24 182U +#define SC_R_MATCH_25 183U +#define SC_R_MATCH_26 184U +#define SC_R_MATCH_27 185U +#define SC_R_MATCH_28 186U +#define SC_R_LCD_0 187U +#define SC_R_LCD_0_PWM_0 188U +#define SC_R_LCD_0_I2C_0 189U +#define SC_R_LCD_0_I2C_1 190U +#define SC_R_PWM_0 191U +#define SC_R_PWM_1 192U +#define SC_R_PWM_2 193U +#define SC_R_PWM_3 194U +#define SC_R_PWM_4 195U +#define SC_R_PWM_5 196U +#define SC_R_PWM_6 197U +#define SC_R_PWM_7 198U +#define SC_R_GPIO_0 199U +#define SC_R_GPIO_1 200U +#define SC_R_GPIO_2 201U +#define SC_R_GPIO_3 202U +#define SC_R_GPIO_4 203U +#define SC_R_GPIO_5 204U +#define SC_R_GPIO_6 205U +#define SC_R_GPIO_7 206U +#define SC_R_GPT_0 207U +#define SC_R_GPT_1 208U +#define SC_R_GPT_2 209U +#define SC_R_GPT_3 210U +#define SC_R_GPT_4 211U +#define SC_R_KPP 212U +#define SC_R_MU_0A 213U +#define SC_R_MU_1A 214U +#define SC_R_MU_2A 215U +#define SC_R_MU_3A 216U +#define SC_R_MU_4A 217U +#define SC_R_MU_5A 218U +#define SC_R_MU_6A 219U +#define SC_R_MU_7A 220U +#define SC_R_MU_8A 221U +#define SC_R_MU_9A 222U +#define SC_R_MU_10A 223U +#define SC_R_MU_11A 224U +#define SC_R_MU_12A 225U +#define SC_R_MU_13A 226U +#define SC_R_MU_5B 227U +#define SC_R_MU_6B 228U +#define SC_R_MU_7B 229U +#define SC_R_MU_8B 230U +#define SC_R_MU_9B 231U +#define SC_R_MU_10B 232U +#define SC_R_MU_11B 233U +#define SC_R_MU_12B 234U +#define SC_R_MU_13B 235U +#define SC_R_ROM_0 236U +#define SC_R_FSPI_0 237U +#define SC_R_FSPI_1 238U +#define SC_R_IEE 239U +#define SC_R_IEE_R0 240U +#define SC_R_IEE_R1 241U +#define SC_R_IEE_R2 242U +#define SC_R_IEE_R3 243U +#define SC_R_IEE_R4 244U +#define SC_R_IEE_R5 245U +#define SC_R_IEE_R6 246U +#define SC_R_IEE_R7 247U +#define SC_R_SDHC_0 248U +#define SC_R_SDHC_1 249U +#define SC_R_SDHC_2 250U +#define SC_R_ENET_0 251U +#define SC_R_ENET_1 252U +#define SC_R_MLB_0 253U +#define SC_R_DMA_2_CH0 254U +#define SC_R_DMA_2_CH1 255U +#define SC_R_DMA_2_CH2 256U +#define SC_R_DMA_2_CH3 257U +#define SC_R_DMA_2_CH4 258U +#define SC_R_USB_0 259U +#define SC_R_USB_1 260U +#define SC_R_USB_0_PHY 261U +#define SC_R_USB_2 262U +#define SC_R_USB_2_PHY 263U +#define SC_R_DTCP 264U +#define SC_R_NAND 265U +#define SC_R_LVDS_0 266U +#define SC_R_LVDS_0_PWM_0 267U +#define SC_R_LVDS_0_I2C_0 268U +#define SC_R_LVDS_0_I2C_1 269U +#define SC_R_LVDS_1 270U +#define SC_R_LVDS_1_PWM_0 271U +#define SC_R_LVDS_1_I2C_0 272U +#define SC_R_LVDS_1_I2C_1 273U +#define SC_R_LVDS_2 274U +#define SC_R_LVDS_2_PWM_0 275U +#define SC_R_LVDS_2_I2C_0 276U +#define SC_R_LVDS_2_I2C_1 277U +#define SC_R_M4_0_PID0 278U +#define SC_R_M4_0_PID1 279U +#define SC_R_M4_0_PID2 280U +#define SC_R_M4_0_PID3 281U +#define SC_R_M4_0_PID4 282U +#define SC_R_M4_0_RGPIO 283U +#define SC_R_M4_0_SEMA42 284U +#define SC_R_M4_0_TPM 285U +#define SC_R_M4_0_PIT 286U +#define SC_R_M4_0_UART 287U +#define SC_R_M4_0_I2C 288U +#define SC_R_M4_0_INTMUX 289U +#define SC_R_UNUSED15 290U +#define SC_R_UNUSED16 291U +#define SC_R_M4_0_MU_0B 292U +#define SC_R_M4_0_MU_0A0 293U +#define SC_R_M4_0_MU_0A1 294U +#define SC_R_M4_0_MU_0A2 295U +#define SC_R_M4_0_MU_0A3 296U +#define SC_R_M4_0_MU_1A 297U +#define SC_R_M4_1_PID0 298U +#define SC_R_M4_1_PID1 299U +#define SC_R_M4_1_PID2 300U +#define SC_R_M4_1_PID3 301U +#define SC_R_M4_1_PID4 302U +#define SC_R_M4_1_RGPIO 303U +#define SC_R_M4_1_SEMA42 304U +#define SC_R_M4_1_TPM 305U +#define SC_R_M4_1_PIT 306U +#define SC_R_M4_1_UART 307U +#define SC_R_M4_1_I2C 308U +#define SC_R_M4_1_INTMUX 309U +#define SC_R_UNUSED17 310U +#define SC_R_UNUSED18 311U +#define SC_R_M4_1_MU_0B 312U +#define SC_R_M4_1_MU_0A0 313U +#define SC_R_M4_1_MU_0A1 314U +#define SC_R_M4_1_MU_0A2 315U +#define SC_R_M4_1_MU_0A3 316U +#define SC_R_M4_1_MU_1A 317U +#define SC_R_SAI_0 318U +#define SC_R_SAI_1 319U +#define SC_R_SAI_2 320U +#define SC_R_IRQSTR_SCU2 321U +#define SC_R_IRQSTR_DSP 322U +#define SC_R_ELCDIF_PLL 323U +#define SC_R_OCRAM 324U +#define SC_R_AUDIO_PLL_0 325U +#define SC_R_PI_0 326U +#define SC_R_PI_0_PWM_0 327U +#define SC_R_PI_0_PWM_1 328U +#define SC_R_PI_0_I2C_0 329U +#define SC_R_PI_0_PLL 330U +#define SC_R_PI_1 331U +#define SC_R_PI_1_PWM_0 332U +#define SC_R_PI_1_PWM_1 333U +#define SC_R_PI_1_I2C_0 334U +#define SC_R_PI_1_PLL 335U +#define SC_R_SC_PID0 336U +#define SC_R_SC_PID1 337U +#define SC_R_SC_PID2 338U +#define SC_R_SC_PID3 339U +#define SC_R_SC_PID4 340U +#define SC_R_SC_SEMA42 341U +#define SC_R_SC_TPM 342U +#define SC_R_SC_PIT 343U +#define SC_R_SC_UART 344U +#define SC_R_SC_I2C 345U +#define SC_R_SC_MU_0B 346U +#define SC_R_SC_MU_0A0 347U +#define SC_R_SC_MU_0A1 348U +#define SC_R_SC_MU_0A2 349U +#define SC_R_SC_MU_0A3 350U +#define SC_R_SC_MU_1A 351U +#define SC_R_SYSCNT_RD 352U +#define SC_R_SYSCNT_CMP 353U +#define SC_R_DEBUG 354U +#define SC_R_SYSTEM 355U +#define SC_R_SNVS 356U +#define SC_R_OTP 357U +#define SC_R_VPU_PID0 358U +#define SC_R_VPU_PID1 359U +#define SC_R_VPU_PID2 360U +#define SC_R_VPU_PID3 361U +#define SC_R_VPU_PID4 362U +#define SC_R_VPU_PID5 363U +#define SC_R_VPU_PID6 364U +#define SC_R_VPU_PID7 365U +#define SC_R_VPU_UART 366U +#define SC_R_VPUCORE 367U +#define SC_R_VPUCORE_0 368U +#define SC_R_VPUCORE_1 369U +#define SC_R_VPUCORE_2 370U +#define SC_R_VPUCORE_3 371U +#define SC_R_DMA_4_CH0 372U +#define SC_R_DMA_4_CH1 373U +#define SC_R_DMA_4_CH2 374U +#define SC_R_DMA_4_CH3 375U +#define SC_R_DMA_4_CH4 376U +#define SC_R_ISI_CH0 377U +#define SC_R_ISI_CH1 378U +#define SC_R_ISI_CH2 379U +#define SC_R_ISI_CH3 380U +#define SC_R_ISI_CH4 381U +#define SC_R_ISI_CH5 382U +#define SC_R_ISI_CH6 383U +#define SC_R_ISI_CH7 384U +#define SC_R_MJPEG_DEC_S0 385U +#define SC_R_MJPEG_DEC_S1 386U +#define SC_R_MJPEG_DEC_S2 387U +#define SC_R_MJPEG_DEC_S3 388U +#define SC_R_MJPEG_ENC_S0 389U +#define SC_R_MJPEG_ENC_S1 390U +#define SC_R_MJPEG_ENC_S2 391U +#define SC_R_MJPEG_ENC_S3 392U +#define SC_R_MIPI_0 393U +#define SC_R_MIPI_0_PWM_0 394U +#define SC_R_MIPI_0_I2C_0 395U +#define SC_R_MIPI_0_I2C_1 396U +#define SC_R_MIPI_1 397U +#define SC_R_MIPI_1_PWM_0 398U +#define SC_R_MIPI_1_I2C_0 399U +#define SC_R_MIPI_1_I2C_1 400U +#define SC_R_CSI_0 401U +#define SC_R_CSI_0_PWM_0 402U +#define SC_R_CSI_0_I2C_0 403U +#define SC_R_CSI_1 404U +#define SC_R_CSI_1_PWM_0 405U +#define SC_R_CSI_1_I2C_0 406U +#define SC_R_HDMI 407U +#define SC_R_HDMI_I2S 408U +#define SC_R_HDMI_I2C_0 409U +#define SC_R_HDMI_PLL_0 410U +#define SC_R_HDMI_RX 411U +#define SC_R_HDMI_RX_BYPASS 412U +#define SC_R_HDMI_RX_I2C_0 413U +#define SC_R_ASRC_0 414U +#define SC_R_ESAI_0 415U +#define SC_R_SPDIF_0 416U +#define SC_R_SPDIF_1 417U +#define SC_R_SAI_3 418U +#define SC_R_SAI_4 419U +#define SC_R_SAI_5 420U +#define SC_R_GPT_5 421U +#define SC_R_GPT_6 422U +#define SC_R_GPT_7 423U +#define SC_R_GPT_8 424U +#define SC_R_GPT_9 425U +#define SC_R_GPT_10 426U +#define SC_R_DMA_2_CH5 427U +#define SC_R_DMA_2_CH6 428U +#define SC_R_DMA_2_CH7 429U +#define SC_R_DMA_2_CH8 430U +#define SC_R_DMA_2_CH9 431U +#define SC_R_DMA_2_CH10 432U +#define SC_R_DMA_2_CH11 433U +#define SC_R_DMA_2_CH12 434U +#define SC_R_DMA_2_CH13 435U +#define SC_R_DMA_2_CH14 436U +#define SC_R_DMA_2_CH15 437U +#define SC_R_DMA_2_CH16 438U +#define SC_R_DMA_2_CH17 439U +#define SC_R_DMA_2_CH18 440U +#define SC_R_DMA_2_CH19 441U +#define SC_R_DMA_2_CH20 442U +#define SC_R_DMA_2_CH21 443U +#define SC_R_DMA_2_CH22 444U +#define SC_R_DMA_2_CH23 445U +#define SC_R_DMA_2_CH24 446U +#define SC_R_DMA_2_CH25 447U +#define SC_R_DMA_2_CH26 448U +#define SC_R_DMA_2_CH27 449U +#define SC_R_DMA_2_CH28 450U +#define SC_R_DMA_2_CH29 451U +#define SC_R_DMA_2_CH30 452U +#define SC_R_DMA_2_CH31 453U +#define SC_R_ASRC_1 454U +#define SC_R_ESAI_1 455U +#define SC_R_SAI_6 456U +#define SC_R_SAI_7 457U +#define SC_R_AMIX 458U +#define SC_R_MQS_0 459U +#define SC_R_DMA_3_CH0 460U +#define SC_R_DMA_3_CH1 461U +#define SC_R_DMA_3_CH2 462U +#define SC_R_DMA_3_CH3 463U +#define SC_R_DMA_3_CH4 464U +#define SC_R_DMA_3_CH5 465U +#define SC_R_DMA_3_CH6 466U +#define SC_R_DMA_3_CH7 467U +#define SC_R_DMA_3_CH8 468U +#define SC_R_DMA_3_CH9 469U +#define SC_R_DMA_3_CH10 470U +#define SC_R_DMA_3_CH11 471U +#define SC_R_DMA_3_CH12 472U +#define SC_R_DMA_3_CH13 473U +#define SC_R_DMA_3_CH14 474U +#define SC_R_DMA_3_CH15 475U +#define SC_R_DMA_3_CH16 476U +#define SC_R_DMA_3_CH17 477U +#define SC_R_DMA_3_CH18 478U +#define SC_R_DMA_3_CH19 479U +#define SC_R_DMA_3_CH20 480U +#define SC_R_DMA_3_CH21 481U +#define SC_R_DMA_3_CH22 482U +#define SC_R_DMA_3_CH23 483U +#define SC_R_DMA_3_CH24 484U +#define SC_R_DMA_3_CH25 485U +#define SC_R_DMA_3_CH26 486U +#define SC_R_DMA_3_CH27 487U +#define SC_R_DMA_3_CH28 488U +#define SC_R_DMA_3_CH29 489U +#define SC_R_DMA_3_CH30 490U +#define SC_R_DMA_3_CH31 491U +#define SC_R_AUDIO_PLL_1 492U +#define SC_R_AUDIO_CLK_0 493U +#define SC_R_AUDIO_CLK_1 494U +#define SC_R_MCLK_OUT_0 495U +#define SC_R_MCLK_OUT_1 496U +#define SC_R_PMIC_0 497U +#define SC_R_PMIC_1 498U +#define SC_R_SECO 499U +#define SC_R_CAAM_JR1 500U +#define SC_R_CAAM_JR2 501U +#define SC_R_CAAM_JR3 502U +#define SC_R_SECO_MU_2 503U +#define SC_R_SECO_MU_3 504U +#define SC_R_SECO_MU_4 505U +#define SC_R_HDMI_RX_PWM_0 506U +#define SC_R_A35 507U +#define SC_R_A35_0 508U +#define SC_R_A35_1 509U +#define SC_R_A35_2 510U +#define SC_R_A35_3 511U +#define SC_R_DSP 512U +#define SC_R_DSP_RAM 513U +#define SC_R_CAAM_JR1_OUT 514U +#define SC_R_CAAM_JR2_OUT 515U +#define SC_R_CAAM_JR3_OUT 516U +#define SC_R_VPU_DEC_0 517U +#define SC_R_VPU_ENC_0 518U +#define SC_R_CAAM_JR0 519U +#define SC_R_CAAM_JR0_OUT 520U +#define SC_R_PMIC_2 521U +#define SC_R_DBLOGIC 522U +#define SC_R_HDMI_PLL_1 523U +#define SC_R_BOARD_R0 524U +#define SC_R_BOARD_R1 525U +#define SC_R_BOARD_R2 526U +#define SC_R_BOARD_R3 527U +#define SC_R_BOARD_R4 528U +#define SC_R_BOARD_R5 529U +#define SC_R_BOARD_R6 530U +#define SC_R_BOARD_R7 531U +#define SC_R_MJPEG_DEC_MP 532U +#define SC_R_MJPEG_ENC_MP 533U +#define SC_R_VPU_TS_0 534U +#define SC_R_VPU_MU_0 535U +#define SC_R_VPU_MU_1 536U +#define SC_R_VPU_MU_2 537U +#define SC_R_VPU_MU_3 538U +#define SC_R_VPU_ENC_1 539U +#define SC_R_VPU 540U +#define SC_R_DMA_5_CH0 541U +#define SC_R_DMA_5_CH1 542U +#define SC_R_DMA_5_CH2 543U +#define SC_R_DMA_5_CH3 544U +#define SC_R_ATTESTATION 545U +#define SC_R_LAST 546U +#define SC_R_ALL ((sc_rsrc_t) UINT16_MAX) /*!< All resources */ +/*@}*/ + +/*! + * Define for ATF/Linux. Not used by SCFW. Not a valid parameter + * for any SCFW API calls! + */ +#define SC_R_NONE 0xFFF0U + +/* NOTE - please add by replacing some of the UNUSED from above! */ + +/*! + * Defines for sc_ctrl_t. + */ +#define SC_C_TEMP 0U +#define SC_C_TEMP_HI 1U +#define SC_C_TEMP_LOW 2U +#define SC_C_PXL_LINK_MST1_ADDR 3U +#define SC_C_PXL_LINK_MST2_ADDR 4U +#define SC_C_PXL_LINK_MST_ENB 5U +#define SC_C_PXL_LINK_MST1_ENB 6U +#define SC_C_PXL_LINK_MST2_ENB 7U +#define SC_C_PXL_LINK_SLV1_ADDR 8U +#define SC_C_PXL_LINK_SLV2_ADDR 9U +#define SC_C_PXL_LINK_MST_VLD 10U +#define SC_C_PXL_LINK_MST1_VLD 11U +#define SC_C_PXL_LINK_MST2_VLD 12U +#define SC_C_SINGLE_MODE 13U +#define SC_C_ID 14U +#define SC_C_PXL_CLK_POLARITY 15U +#define SC_C_LINESTATE 16U +#define SC_C_PCIE_G_RST 17U +#define SC_C_PCIE_BUTTON_RST 18U +#define SC_C_PCIE_PERST 19U +#define SC_C_PHY_RESET 20U +#define SC_C_PXL_LINK_RATE_CORRECTION 21U +#define SC_C_PANIC 22U +#define SC_C_PRIORITY_GROUP 23U +#define SC_C_TXCLK 24U +#define SC_C_CLKDIV 25U +#define SC_C_DISABLE_50 26U +#define SC_C_DISABLE_125 27U +#define SC_C_SEL_125 28U +#define SC_C_MODE 29U +#define SC_C_SYNC_CTRL0 30U +#define SC_C_KACHUNK_CNT 31U +#define SC_C_KACHUNK_SEL 32U +#define SC_C_SYNC_CTRL1 33U +#define SC_C_DPI_RESET 34U +#define SC_C_MIPI_RESET 35U +#define SC_C_DUAL_MODE 36U +#define SC_C_VOLTAGE 37U +#define SC_C_PXL_LINK_SEL 38U +#define SC_C_OFS_SEL 39U +#define SC_C_OFS_AUDIO 40U +#define SC_C_OFS_PERIPH 41U +#define SC_C_OFS_IRQ 42U +#define SC_C_RST0 43U +#define SC_C_RST1 44U +#define SC_C_SEL0 45U +#define SC_C_CALIB0 46U +#define SC_C_CALIB1 47U +#define SC_C_CALIB2 48U +#define SC_C_IPG_DEBUG 49U +#define SC_C_IPG_DOZE 50U +#define SC_C_IPG_WAIT 51U +#define SC_C_IPG_STOP 52U +#define SC_C_IPG_STOP_MODE 53U +#define SC_C_IPG_STOP_ACK 54U +#define SC_C_SYNC_CTRL 55U +#define SC_C_LAST 56U + +#define SC_P_ALL ((sc_pad_t) UINT16_MAX) /*!< All pads */ + +/* Types */ + +/*! + * This type is used to store a boolean + */ +typedef uint8_t sc_bool_t; + +/*! + * This type is used to store a system (full-size) address. + */ +typedef uint64_t sc_faddr_t; + +/*! + * This type is used to indicate error response for most functions. + */ +typedef uint8_t sc_err_t; + +/*! + * This type is used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +typedef uint16_t sc_rsrc_t; + +/*! + * This type is used to indicate a control. + */ +typedef uint32_t sc_ctrl_t; + +/*! + * This type is used to indicate a pad. Valid values are SoC specific. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +typedef uint16_t sc_pad_t; + +/* Extra documentation of standard types */ + +#ifdef DOXYGEN + /*! + * Type used to declare an 8-bit integer. + */ + typedef __INT8_TYPE__ int8_t; + + /*! + * Type used to declare a 16-bit integer. + */ + typedef __INT16_TYPE__ int16_t; + + /*! + * Type used to declare a 32-bit integer. + */ + typedef __INT32_TYPE__ int32_t; + + /*! + * Type used to declare a 64-bit integer. + */ + typedef __INT64_TYPE__ int64_t; + + /*! + * Type used to declare an 8-bit unsigned integer. + */ + typedef __UINT8_TYPE__ uint8_t; + + /*! + * Type used to declare a 16-bit unsigned integer. + */ + typedef __UINT16_TYPE__ uint16_t; + + /*! + * Type used to declare a 32-bit unsigned integer. + */ + typedef __UINT32_TYPE__ uint32_t; + + /*! + * Type used to declare a 64-bit unsigned integer. + */ + typedef __UINT64_TYPE__ uint64_t; +#endif + +#endif /* SC_TYPES_H */ + diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 96795e18148..90f605346fe 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -1,6 +1,7 @@ /* * (C) Copyright 2009 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -27,7 +28,8 @@ #define is_mx6() (is_soc_type(MXC_SOC_MX6)) #define is_mx7() (is_soc_type(MXC_SOC_MX7)) -#define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) +#define is_imx8() (is_soc_type(MXC_SOC_IMX8)) +#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) @@ -37,11 +39,29 @@ #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) -#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) +#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ)) #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) +#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL)) +#define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD)) +#define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL)) +#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ + is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ + is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL)) +#define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML)) +#define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD)) +#define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL)) +#define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) +#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) +#define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) +#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) +#define is_imx8dx() (is_cpu_type(MXC_CPU_IMX8DX)) + + /* gd->flags reserves high 16 bits for arch-specific flags */ +#define GD_FLG_ARCH_IMX_USB_BOOT 0x80000000 /* Only used for MX6/7, If set, the u-boot is booting from USB serial download */ + #ifdef CONFIG_MX6 #define IMX6_SRC_GPR10_BMODE BIT(28) @@ -128,6 +148,18 @@ int mxs_reset_block(struct mxs_register_32 *reg); int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); +void board_late_mmc_env_init(void); + +void vadc_power_up(void); +void vadc_power_down(void); + +void pcie_power_up(void); +void pcie_power_off(void); +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data); +int arch_auxiliary_core_check_up(u32 core_id); + unsigned long call_imx_sip(unsigned long id, unsigned long reg0, - unsigned long reg1, unsigned long reg2); + unsigned long reg1, unsigned long reg2, unsigned long reg3); +unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, + unsigned long *reg1, unsigned long reg2, unsigned long reg3); #endif diff --git a/arch/arm/include/asm/mach-imx/video.h b/arch/arm/include/asm/mach-imx/video.h index 941a031964c..ca626ce3d9d 100644 --- a/arch/arm/include/asm/mach-imx/video.h +++ b/arch/arm/include/asm/mach-imx/video.h @@ -1,4 +1,7 @@ /* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -6,7 +9,16 @@ #define __IMX_VIDEO_H_ #include +#if defined(CONFIG_VIDEO_IPUV3) #include +#elif defined(CONFIG_VIDEO_IMXDPUV1) +#include +#include +#elif defined(CONFIG_VIDEO_MXS) +#include +#elif defined(CONFIG_VIDEO_IMXDCSS) +#include +#endif struct display_info_t { int bus; diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index d588f943503..3ba90da515c 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -20,6 +20,11 @@ #define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) #define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) +#define L2X0_CACHE_ID_PART_MASK (0xf << 6) +#define L2X0_CACHE_ID_PART_L310 (3 << 6) +#define L2X0_CACHE_ID_RTL_MASK 0x3f +#define L2X0_CACHE_ID_RTL_R3P2 0x8 + struct pl310_regs { u32 pl310_cache_id; u32 pl310_cache_type; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 4f043cad0ba..c2d90188e04 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -470,7 +470,11 @@ enum dcache_option { DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, +#ifdef CONFIG_IMX_TRUSTY_OS + DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1) | TTB_SECT_S_MASK, +#else DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), +#endif }; #else #define TTB_SECT_AP (3 << 10) diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h new file mode 100644 index 00000000000..eb50b34deac --- /dev/null +++ b/arch/arm/include/asm/xen/hypercall.h @@ -0,0 +1,66 @@ +/****************************************************************************** + * hypercall.h + * + * Linux-specific hypervisor handling. + * + * Stefano Stabellini , Citrix, 2012 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation; or, when distributed + * separately from the Linux kernel or incorporated into other + * software packages, subject to the following license: + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this source file (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, modify, + * merge, publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef _ASM_ARM_XEN_HYPERCALL_H +#define _ASM_ARM_XEN_HYPERCALL_H + +#include + +#include +//#include +#include + +struct xen_dm_op_buf; + +long privcmd_call(unsigned call, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5); +int HYPERVISOR_xen_version(int cmd, void *arg); +int HYPERVISOR_console_io(int cmd, int count, char *str); +int HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count); +int HYPERVISOR_sched_op(int cmd, void *arg); +int HYPERVISOR_event_channel_op(int cmd, void *arg); +unsigned long HYPERVISOR_hvm_op(int op, void *arg); +int HYPERVISOR_memory_op(unsigned int cmd, void *arg); +int HYPERVISOR_physdev_op(int cmd, void *arg); +int HYPERVISOR_vcpu_op(int cmd, int vcpuid, void *extra_args); +int HYPERVISOR_tmem_op(void *arg); +int HYPERVISOR_vm_assist(unsigned int cmd, unsigned int type); +int HYPERVISOR_dm_op(domid_t domid, unsigned int nr_bufs, + struct xen_dm_op_buf *bufs); +int HYPERVISOR_platform_op_raw(void *arg); +static inline int HYPERVISOR_platform_op(struct xen_platform_op *op) +{ + op->interface_version = XENPF_INTERFACE_VERSION; + return HYPERVISOR_platform_op_raw(op); +} +#endif /* _ASM_ARM_XEN_HYPERCALL_H */ diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h new file mode 100644 index 00000000000..c3eada2642a --- /dev/null +++ b/arch/arm/include/asm/xen/interface.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * Guest OS interface to ARM Xen. + * + * Stefano Stabellini , Citrix, 2012 + */ + +#ifndef _ASM_ARM_XEN_INTERFACE_H +#define _ASM_ARM_XEN_INTERFACE_H + +#include + +#define uint64_aligned_t uint64_t __attribute__((aligned(8))) + +#define __DEFINE_GUEST_HANDLE(name, type) \ + typedef struct { union { type *p; uint64_aligned_t q; }; } \ + __guest_handle_ ## name + +#define DEFINE_GUEST_HANDLE_STRUCT(name) \ + __DEFINE_GUEST_HANDLE(name, struct name) +#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name) +#define GUEST_HANDLE(name) __guest_handle_ ## name + +#define set_xen_guest_handle(hnd, val) \ + do { \ + if (sizeof(hnd) == 8) \ + *(uint64_t *)&(hnd) = 0; \ + (hnd).p = val; \ + } while (0) + +#define __HYPERVISOR_platform_op_raw __HYPERVISOR_platform_op + +#ifndef __ASSEMBLY__ +/* Explicitly size integers that represent pfns in the interface with + * Xen so that we can have one ABI that works for 32 and 64 bit guests. + * Note that this means that the xen_pfn_t type may be capable of + * representing pfn's which the guest cannot represent in its own pfn + * type. However since pfn space is controlled by the guest this is + * fine since it simply wouldn't be able to create any sure pfns in + * the first place. + */ +typedef uint64_t xen_pfn_t; +#define PRI_xen_pfn "llx" +typedef uint64_t xen_ulong_t; +#define PRI_xen_ulong "llx" +typedef int64_t xen_long_t; +#define PRI_xen_long "llx" +/* Guest handles for primitive C types. */ +__DEFINE_GUEST_HANDLE(uchar, unsigned char); +__DEFINE_GUEST_HANDLE(uint, unsigned int); +DEFINE_GUEST_HANDLE(char); +DEFINE_GUEST_HANDLE(int); +DEFINE_GUEST_HANDLE(void); +DEFINE_GUEST_HANDLE(uint64_t); +DEFINE_GUEST_HANDLE(uint32_t); +DEFINE_GUEST_HANDLE(xen_pfn_t); +DEFINE_GUEST_HANDLE(xen_ulong_t); + +/* Maximum number of virtual CPUs in multi-processor guests. */ +#define MAX_VIRT_CPUS 1 + +struct arch_vcpu_info { }; +struct arch_shared_info { }; + +/* TODO: Move pvclock definitions some place arch independent */ +struct pvclock_vcpu_time_info { + u32 version; + u32 pad0; + u64 tsc_timestamp; + u64 system_time; + u32 tsc_to_system_mul; + s8 tsc_shift; + u8 flags; + u8 pad[2]; +} __attribute__((__packed__)); /* 32 bytes */ + +/* It is OK to have a 12 bytes struct with no padding because it is packed */ +struct pvclock_wall_clock { + u32 version; + u32 sec; + u32 nsec; + u32 sec_hi; +} __attribute__((__packed__)); +#endif + +#endif /* _ASM_ARM_XEN_INTERFACE_H */ diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index cfc236f964e..d730cc6253e 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -108,7 +108,9 @@ static void announce_and_cleanup(int fake) * This may be useful for last-stage operations, like cancelling * of DMA operation or releasing device internal buffers. */ +#ifndef CONFIG_POWER_DOMAIN dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); +#endif cleanup_before_linux(); } diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f0c1b03728b..b7a2337eb4e 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -231,8 +231,11 @@ static void cache_disable(uint32_t cache_bit) } reg = get_cr(); - if (cache_bit == (CR_C | CR_M)) + if (cache_bit == (CR_C | CR_M)) { flush_dcache_all(); + set_cr(reg & ~CR_C); + flush_dcache_all(); + } set_cr(reg & ~cache_bit); } #endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3aec89d440a..f6d05c1e12b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -4,6 +4,11 @@ config HAS_CAAM config IMX_CONFIG string +config IMX_OPTEE + bool "Support OP-TEE" + help + Enable support for OP-TEE + config ROM_UNIFIED_SECTIONS bool @@ -13,6 +18,17 @@ config SYSCOUNTER_TIMER config GPT_TIMER bool +config FSL_CAAM_KB + bool + +config IMX_SEC_INIT + bool + help + In most of i.MX board with CAAM this option is used + to init RNG from U-Boot + select FSL_CAAM_KB + select SPL_CRYPTO_SUPPORT if SPL + config IMX_RDC bool "i.MX Resource domain controller driver" depends on ARCH_MX6 || ARCH_MX7 @@ -23,22 +39,56 @@ config IMX_RDC config IMX_BOOTAUX bool "Support boot auxiliary core" - depends on ARCH_MX7 || ARCH_MX6 + depends on ARCH_MX7 || ARCH_MX6 || ARCH_IMX8 || ARCH_IMX8M help bootaux [addr] to boot auxiliary core. +config BOOTAUX_RESERVED_MEM_BASE + hex "Define the reserved memory base address" + default 0x00 + depends on ARCH_IMX8 + help + reserve DDR memory for bootaux + +config BOOTAUX_RESERVED_MEM_SIZE + hex "Define the reserved memory size" + default 0x00 + depends on ARCH_IMX8 + help + This memory will be reserved by system and linux cannot access. + +config IMX_VSERVICE_SHARED_BUFFER + hex "Define the buffer address used for virtual service" + depends on IMX_VSERVICE + help + IMX virtual service will use this buffer for exchanging data with remote core. + +config IMX_VSERVICE_SHARED_BUFFER_SIZE + hex "Define the size of buffer address used for virtual service" + default 0x400000 + depends on IMX_VSERVICE + help + The buffer size for IMX virtual service needs enough large to fit all possible message. + +config IMX_VSERVICE + bool + select MISC + select IMX_M4_MU + help + This enables imx virtual service provides framework for imx virtual driver working. + config USE_IMXIMG_PLUGIN bool "Use imximage plugin code" - depends on ARCH_MX7 || ARCH_MX6 + depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX7ULP help i.MX6/7 supports DCD and Plugin. Enable this configuration to use Plugin, otherwise DCD will be used. config SECURE_BOOT bool "Support i.MX HAB features" - depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 + depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_MX7ULP || ARCH_IMX8M select FSL_CAAM if HAS_CAAM - imply CMD_DEKBLOB + imply CMD_DEKBLOB if HAS_CAAM help This option enables the support for secure boot (HAB). See doc/README.mxc_hab for more details. @@ -65,12 +115,36 @@ config CMD_DEKBLOB creates a blob of data. See also CMD_BLOB and doc/README.mxc_hab for more information. +config CMD_PRIBLOB + bool "Support the set_priblob_bitfield command" + depends on HAS_CAAM && SECURE_BOOT + help + This option enables the priblob command which can be used + to set the priblob setting to 0x3. + config CMD_HDMIDETECT bool "Support the 'hdmidet' command" help This enables the 'hdmidet' command which detects if an HDMI monitor is connected. +config FSL_MFGPROT + bool "Support the 'mfgprot' command" + depends on SECURE_BOOT && ARCH_MX7 + help + This option enables the manufacturing protection command + which can be used has a protection feature for Manufacturing + process. With this tool is possible to authenticate the + chip to the OEM's server. + +config DBG_MONITOR + bool "Enable the AXI debug monitor" + depends on ARCH_MX6 || ARCH_MX7 + help + This option enables the debug monitor which prints out last + failed AXI access info when system reboot is caused by AXI + access failure. + config NXP_BOARD_REVISION bool "Read NXP board revision from fuses" depends on ARCH_MX6 || ARCH_MX7 @@ -78,3 +152,17 @@ config NXP_BOARD_REVISION NXP boards based on i.MX6/7 contain the board revision information stored in the fuses. Select this option if you want to be able to retrieve the board revision information. + +config FLASH_MCUFIRMWARE_SUPPORT + bool "Enable mcu firmware flash support" + depends on ARCH_MX7ULP || ARCH_IMX8M + help + This enables the mcu firmware flash support for some SOCs. + +config IMX_TRUSTY_OS + bool "Support Trusty OS related feature" + depends on ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M + select SYS_ARM_CACHE_WRITEALLOC + +config SYS_ARM_CACHE_WRITEALLOC + bool "support cache write alloc" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 95a542fa01f..e56bd92bbd1 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -7,15 +7,17 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610)) obj-y = iomux-v3.o endif -ifeq ($(SOC),$(filter $(SOC),mx8m)) +ifeq ($(SOC),$(filter $(SOC),imx8m)) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o -obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o +obj-y += mmc_env.o obj-$(CONFIG_FEC_MXC) += mac.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o +obj-$(CONFIG_SECURE_BOOT) += hab.o +obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o obj-y += cpu.o endif @@ -24,14 +26,16 @@ obj-y += cpu.o speed.o obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m)) +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx7ulp imx8m imx8)) obj-y += misc.o +obj-$(CONFIG_CMD_PRIBLOB) += priblob.o obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx7)) obj-y += cpu.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o -obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o +obj-y += mmc_env.o +obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o endif ifeq ($(SOC),$(filter $(SOC),mx6 mx7)) obj-y += cache.o init.o @@ -44,18 +48,29 @@ endif obj-$(CONFIG_SATA) += sata.o obj-$(CONFIG_SECURE_BOOT) += hab.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o +obj-$(CONFIG_IMX_TRUSTY_OS) += trusty.o endif ifeq ($(SOC),$(filter $(SOC),mx7ulp)) obj-y += cache.o +obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o obj-$(CONFIG_SECURE_BOOT) += hab.o endif ifeq ($(SOC),$(filter $(SOC),vf610)) obj-y += ddrmc-vf610.o endif +ifeq ($(SOC),$(filter $(SOC),imx8)) +obj-$(CONFIG_HAVE_SC_FIRMWARE) += sci/ +ifneq ($(CONFIG_SPL_BUILD),y) +obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o +endif +obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o +obj-y += misc.o +endif ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o +obj-$(CONFIG_IMX_VSERVICE) += imx_vservice.o endif PLUGIN = board/$(BOARDDIR)/plugin @@ -84,20 +99,60 @@ $(IMX_CONFIG): %.cfgtmp: % FORCE $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cpp_cfg) -MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \ +MKIMAGEFLAGS_u-boot.imx = -n $(filter-out %$(PLUGIN).bin $(QSPI_HEADER) $< $(PHONY),$^) -T imximage \ -e $(CONFIG_SYS_TEXT_BASE) u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log -u-boot.imx: u-boot.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE +QSPI_HEADER_SOURCE = board/freescale/common/qspi_header +QSPI_HEADER = qspi_header +QSPI_HEADER_OFF = 1 +QSPI_UBOOT_OFF = 4 +ifeq ($(SOC),$(filter $(SOC),mx7)) +QSPI_HEADER_OFF = 0 +QSPI_UBOOT_OFF = 1 +endif + +ifeq ($(CONFIG_QSPI_BOOT),y) +$(QSPI_HEADER): $(QSPI_HEADER_SOURCE) FORCE + @cp $< $@ + +else +$(QSPI_HEADER): + +endif + +u-boot.imx: u-boot.bin $(IMX_CONFIG) $(PLUGIN).bin $(QSPI_HEADER) FORCE $(call if_changed,mkimage) +ifeq ($(CONFIG_QSPI_BOOT),y) + @awk '{s="0000000"$$1;l=length(s);if(!((NR-1)%4))printf "%08x ",(NR-1)*4; \ + for(i=1;i<8;i+=2)printf " %s",substr(s,l-i,2);if(!(NR%4))printf "\n";}' \ + $(QSPI_HEADER) > qspi.tmp + @xxd -r qspi.tmp qspi.bin + @dd if=$@ of=u-boot.tmp bs=1k seek=$(QSPI_UBOOT_OFF) + @dd if=qspi.bin of=u-boot.tmp bs=1k seek=$(QSPI_HEADER_OFF) conv=notrunc + @mv u-boot.tmp $@ + @rm qspi.tmp qspi.bin + @echo "Packed QSPI header with $@" +endif ifeq ($(CONFIG_OF_SEPARATE),y) -MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \ +MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out %$(PLUGIN).bin $(QSPI_HEADER) $< $(PHONY),$^) -T imximage \ -e $(CONFIG_SYS_TEXT_BASE) u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log -u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE +u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) $(PLUGIN).bin $(QSPI_HEADER) FORCE $(call if_changed,mkimage) +ifeq ($(CONFIG_QSPI_BOOT),y) + @awk '{s="0000000"$$1;l=length(s);if(!((NR-1)%4))printf "%08x ",(NR-1)*4; \ + for(i=1;i<8;i+=2)printf " %s",substr(s,l-i,2);if(!(NR%4))printf "\n";}' \ + $(QSPI_HEADER) > qspi.tmp + @xxd -r qspi.tmp qspi.bin + @dd if=$@ of=u-boot.tmp bs=1k seek=$(QSPI_UBOOT_OFF) + @dd if=qspi.bin of=u-boot.tmp bs=1k seek=$(QSPI_HEADER_OFF) conv=notrunc + @mv u-boot.tmp $@ + @rm qspi.tmp qspi.bin + @echo "Packed QSPI header with $@" +endif endif MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \ @@ -141,4 +196,5 @@ obj-$(CONFIG_MX5) += mx5/ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ -obj-$(CONFIG_MX8M) += mx8m/ +obj-$(CONFIG_IMX8) += imx8/ +obj-$(CONFIG_IMX8M) += imx8m/ diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index c5279a7c8a7..fe32469fd37 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -1,5 +1,6 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,6 +11,34 @@ #include #include +static void enable_ca7_smp(void) +{ + uint32_t val; + + /* Read MIDR */ + asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val)); + val = (val >> 4); + val &= 0xf; + + /* Only set the SMP for Cortex A7 */ + if (val == 0x7) { + /* Read auxiliary control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val)); + + if (val & (1 << 6)) + return; + + /* Enable SMP */ + val |= (1 << 6); + + /* Write auxiliary control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val)); + + DSB; + ISB; + } +} + #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { @@ -21,6 +50,9 @@ void enable_caches(void) /* Avoid random hang when download by usb */ invalidate_dcache_all(); + /* Set ACTLR.SMP bit for Cortex-A7 */ + enable_ca7_smp(); + /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); @@ -32,6 +64,14 @@ void enable_caches(void) IRAM_SIZE, option); } +#else +void enable_caches(void) +{ + /* Set ACTLR.SMP bit for Cortex-A7, even the caches are disabled by u-boot */ + enable_ca7_smp(); + + puts("WARNING: Caches not enabled\n"); +} #endif #ifndef CONFIG_SYS_L2CACHE_OFF @@ -41,7 +81,7 @@ void v7_outer_cache_enable(void) { struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - unsigned int val; + unsigned int val, cache_id; /* @@ -71,22 +111,24 @@ void v7_outer_cache_enable(void) val = readl(&pl310->pl310_prefetch_ctrl); - /* Turn on the L2 I/D prefetch */ - val |= 0x30000000; + /* Turn on the L2 I/D prefetch, double linefill */ + /* Set prefetch offset with any value except 23 as per errata 765569 */ + val |= 0x7000000f; /* * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 - * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL/SX/DQP + * is r3p2. * But according to ARM PL310 errata: 752271 * ID: 752271: Double linefill feature can cause data corruption * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 * Workaround: The only workaround to this erratum is to disable the * double linefill feature. This is the default behavior. */ - -#ifndef CONFIG_MX6Q - val |= 0x40800000; -#endif + cache_id = readl(&pl310->pl310_cache_id); + if (((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310) + && ((cache_id & L2X0_CACHE_ID_RTL_MASK) < L2X0_CACHE_ID_RTL_R3P2)) + val &= ~(1 << 30); writel(val, &pl310->pl310_prefetch_ctrl); val = readl(&pl310->pl310_power_ctrl); diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index ada8adf2f4f..bda7b433593 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -29,13 +29,13 @@ DECLARE_GLOBAL_DATA_PTR; static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) { int ret = 0; - u32 jr_size = 4; - u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c); - if (out_jr_size != jr_size) { - hab_caam_clock_enable(1); + hab_caam_clock_enable(1); + + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + FSL_CAAM_ORSR_JRa_OFFSET); + if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) sec_init(); - } if (!((len == 128) | (len == 192) | (len == 256))) { debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c new file mode 100644 index 00000000000..de846aba672 --- /dev/null +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -0,0 +1,151 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * These commands enable the use of the CAAM MPPubK-generation and MPSign + * functions in supported i.MX devices. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * do_mfgprot() - Handle the "mfgprot" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +static int do_mfgprot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + u8 *m_ptr, *dgst_ptr, *c_ptr, *d_ptr, *dst_ptr; + char *pubk, *sign, *sel; + int m_size, i, ret; + u32 m_addr; + + pubk = "pubk"; + sign = "sign"; + sel = argv[1]; + + /* Enable HAB clock */ + hab_caam_clock_enable(1); + + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + FSL_CAAM_ORSR_JRa_OFFSET); + + if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) + sec_init(); + + if (strcmp(sel, pubk) == 0) { + dst_ptr = malloc_cache_aligned(FSL_CAAM_MP_PUBK_BYTES); + if (!dst_ptr) + return -ENOMEM; + + ret = gen_mppubk(dst_ptr); + if (ret) { + free(dst_ptr); + return ret; + } + + /* Output results */ + puts("Public key:\n"); + for (i = 0; i < FSL_CAAM_MP_PUBK_BYTES; i++) + printf("%02X", (dst_ptr)[i]); + puts("\n"); + free(dst_ptr); + + } else if (strcmp(sel, sign) == 0) { + if (argc != 4) + return CMD_RET_USAGE; + + m_addr = simple_strtoul(argv[2], NULL, 16); + m_size = simple_strtoul(argv[3], NULL, 10); + m_ptr = map_physmem(m_addr, m_size, MAP_NOCACHE); + if (!m_ptr) + return -ENOMEM; + + dgst_ptr = malloc_cache_aligned(FSL_CAAM_MP_MES_DGST_BYTES); + if (!dgst_ptr) { + ret = -ENOMEM; + goto free_m; + } + + c_ptr = malloc_cache_aligned(FSL_CAAM_MP_PRVK_BYTES); + if (!c_ptr) { + ret = -ENOMEM; + goto free_dgst; + } + + d_ptr = malloc_cache_aligned(FSL_CAAM_MP_PRVK_BYTES); + if (!d_ptr) { + ret = -ENOMEM; + goto free_c; + } + + ret = sign_mppubk(m_ptr, m_size, dgst_ptr, c_ptr, d_ptr); + if (ret) + goto free_d; + + /* Output results */ + puts("Message: "); + for (i = 0; i < m_size; i++) + printf("%02X ", (m_ptr)[i]); + puts("\n"); + + puts("Message Representative Digest(SHA-256):\n"); + for (i = 0; i < FSL_CAAM_MP_MES_DGST_BYTES; i++) + printf("%02X", (dgst_ptr)[i]); + puts("\n"); + + puts("Signature:\n"); + puts("C:\n"); + for (i = 0; i < FSL_CAAM_MP_PRVK_BYTES; i++) + printf("%02X", (c_ptr)[i]); + puts("\n"); + + puts("d:\n"); + for (i = 0; i < FSL_CAAM_MP_PRVK_BYTES; i++) + printf("%02X", (d_ptr)[i]); + puts("\n"); +free_d: + free(d_ptr); +free_c: + free(c_ptr); +free_dgst: + free(dgst_ptr); +free_m: + unmap_sysmem(m_ptr); + + } else { + return CMD_RET_USAGE; + } + return ret; +} + +/***************************************************/ +static char mfgprot_help_text[] = + "Usage:\n" + "Print the public key for Manufacturing Protection\n" + "\tmfgprot pubk\n" + "Generates a Manufacturing Protection signature\n" + "\tmfgprot sign "; + +U_BOOT_CMD( + mfgprot, 4, 1, do_mfgprot, + "Manufacturing Protection\n", + mfgprot_help_text +); diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 4d4d434906f..111f1e46825 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -2,7 +2,8 @@ * (C) Copyright 2007 * Sascha Hauer, Pengutronix * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,11 +18,18 @@ #include #include #include +#if defined(CONFIG_VIDEO_IMXDCSS) +#include +#endif #include #include #include #include +#ifdef CONFIG_VIDEO_GIS +#include +#endif + #ifdef CONFIG_FSL_ESDHC #include #endif @@ -35,7 +43,12 @@ static char *get_reset_cause(void) struct src *src_regs = (struct src *)SRC_BASE_ADDR; cause = readl(&src_regs->srsr); +#ifndef CONFIG_ANDROID_BOOT_IMAGE + /* We will read the ssrs states later for android so we don't + * clear the states here. + */ writel(cause, &src_regs->srsr); +#endif reset_cause = cause; switch (cause) { @@ -63,7 +76,7 @@ static char *get_reset_cause(void) return "WDOG4"; case 0x00200: return "TEMPSENSE"; -#elif defined(CONFIG_MX8M) +#elif defined(CONFIG_IMX8M) case 0x00100: return "WDOG2"; case 0x00200: @@ -79,6 +92,17 @@ static char *get_reset_cause(void) } } +#ifdef CONFIG_ANDROID_BOOT_IMAGE +void get_reboot_reason(char *ret) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + + strcpy(ret, (char *)get_reset_cause()); + /* clear the srsr here, its state has been recorded in reset_cause */ + writel(reset_cause, &src_regs->srsr); +} +#endif + u32 get_imx_reset_cause(void) { return reset_cause; @@ -143,8 +167,24 @@ unsigned imx_ddr_size(void) const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case MXC_CPU_MX8MQ: - return "8MQ"; /* Quad-core version of the mx8m */ + case MXC_CPU_IMX8MM: + return "8MMQ"; /* Quad-core version of the imx8mm */ + case MXC_CPU_IMX8MML: + return "8MMQL"; /* Quad-core Lite version of the imx8mm */ + case MXC_CPU_IMX8MMD: + return "8MMD"; /* Dual-core version of the imx8mm */ + case MXC_CPU_IMX8MMDL: + return "8MMDL"; /* Dual-core Lite version of the imx8mm */ + case MXC_CPU_IMX8MMS: + return "8MMS"; /* Single-core version of the imx8mm */ + case MXC_CPU_IMX8MMSL: + return "8MMSL"; /* Single-core Lite version of the imx8mm */ + case MXC_CPU_IMX8MQ: + return "8MQ"; /* Quad-core version of the imx8mq */ + case MXC_CPU_IMX8MQL: + return "8MQLite"; /* Quad-core Lite version of the imx8mq */ + case MXC_CPU_IMX8MD: + return "8MD"; /* Dual-core version of the imx8mq */ case MXC_CPU_MX7S: return "7S"; /* Single-core version of the mx7 */ case MXC_CPU_MX7D: @@ -171,6 +211,8 @@ const char *get_imx_type(u32 imxtype) return "6UL"; /* Ultra-Lite version of the mx6 */ case MXC_CPU_MX6ULL: return "6ULL"; /* ULL version of the mx6 */ + case MXC_CPU_MX6ULZ: + return "6ULZ"; /* ULL version of the mx6 */ case MXC_CPU_MX51: return "51"; case MXC_CPU_MX53: @@ -184,10 +226,14 @@ int print_cpuinfo(void) { u32 cpurev; __maybe_unused u32 max_freq; +#if defined(CONFIG_DBG_MONITOR) + struct dbg_monitor_regs *dbg = + (struct dbg_monitor_regs *)DEBUG_MONITOR_BASE_ADDR; +#endif cpurev = get_cpu_rev(); -#if defined(CONFIG_IMX_THERMAL) +#if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_NXP_TMU) struct udevice *thermal_dev; int cpu_tmp, minc, maxc, ret; @@ -210,7 +256,7 @@ int print_cpuinfo(void) mxc_get_clock(MXC_ARM_CLK) / 1000000); #endif -#if defined(CONFIG_IMX_THERMAL) +#if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_NXP_TMU) puts("CPU: "); switch (get_cpu_temp_grade(&minc, &maxc)) { case TEMP_AUTOMOTIVE: @@ -227,7 +273,11 @@ int print_cpuinfo(void) break; } printf("(%dC to %dC)", minc, maxc); +#if defined(CONFIG_NXP_TMU) + ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal", &thermal_dev); +#else ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev); +#endif if (!ret) { ret = thermal_get_temp(thermal_dev, &cpu_tmp); @@ -240,6 +290,14 @@ int print_cpuinfo(void) } #endif +#if defined(CONFIG_DBG_MONITOR) + if (readl(&dbg->snvs_addr)) + printf("DBG snvs regs addr 0x%x, data 0x%x, info 0x%x\n", + readl(&dbg->snvs_addr), + readl(&dbg->snvs_data), + readl(&dbg->snvs_info)); +#endif + printf("Reset cause: %s\n", get_reset_cause()); return 0; } @@ -267,7 +325,7 @@ int cpu_mmc_init(bd_t *bis) } #endif -#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M)) +#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) u32 get_ahb_clk(void) { struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -292,16 +350,26 @@ void arch_preboot_os(void) disable_sata_clock(); #endif #endif +#if defined(CONFIG_LDO_BYPASS_CHECK) + ldo_mode_set(check_ldo_bypass()); +#endif #if defined(CONFIG_VIDEO_IPUV3) /* disable video before launching O/S */ ipuv3_fb_shutdown(); #endif +#ifdef CONFIG_VIDEO_GIS + /* Entry for GIS */ + mxc_disable_gis(); +#endif #if defined(CONFIG_VIDEO_MXS) lcdif_power_down(); #endif +#if defined(CONFIG_VIDEO_IMXDCSS) + imx8m_fb_disable(); +#endif } -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M void set_chipselect_size(int const cs_size) { unsigned int reg; @@ -334,7 +402,7 @@ void set_chipselect_size(int const cs_size) } #endif -#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) /* * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) * defines a 2-bit SPEED_GRADING @@ -345,6 +413,7 @@ enum cpu_speed { OCOTP_TESTER3_SPEED_GRADE1, OCOTP_TESTER3_SPEED_GRADE2, OCOTP_TESTER3_SPEED_GRADE3, + OCOTP_TESTER3_SPEED_GRADE4, }; u32 get_cpu_speed_grade_hz(void) @@ -357,17 +426,22 @@ u32 get_cpu_speed_grade_hz(void) val = readl(&fuse->tester3); val >>= OCOTP_TESTER3_SPEED_SHIFT; - val &= 0x3; + if (is_imx8mm()) + val &= 0x7; + else + val &= 0x3; switch(val) { case OCOTP_TESTER3_SPEED_GRADE0: return 800000000; case OCOTP_TESTER3_SPEED_GRADE1: - return is_mx7() ? 500000000 : 1000000000; + return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000)); case OCOTP_TESTER3_SPEED_GRADE2: - return is_mx7() ? 1000000000 : 1300000000; + return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000)); case OCOTP_TESTER3_SPEED_GRADE3: - return is_mx7() ? 1200000000 : 1500000000; + return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000)); + case OCOTP_TESTER3_SPEED_GRADE4: + return 2000000000; } return 0; @@ -410,7 +484,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) } #endif -#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) enum boot_device get_boot_device(void) { struct bootrom_sw_info **p = @@ -439,12 +513,14 @@ enum boot_device get_boot_device(void) case BOOT_TYPE_SPINOR: boot_dev = SPI_NOR_BOOT; break; -#ifdef CONFIG_MX8M case BOOT_TYPE_USB: boot_dev = USB_BOOT; break; -#endif default: +#ifdef CONFIG_IMX8M + if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4) + boot_dev = QSPI_BOOT; +#endif break; } diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index c730c8f7a91..bc4f6622d89 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -13,13 +13,21 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #define ALIGN_SIZE 0x1000 #define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8 #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 #define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 #define IS_HAB_ENABLED_BIT \ (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ - (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) + ((is_soc_type(MXC_SOC_MX7) || is_soc_type(MXC_SOC_IMX8M))? 0x2000000 : 0x2)) + +#ifdef CONFIG_MX7ULP +#define HAB_M4_PERSISTENT_START ((soc_rev() >= CHIP_REV_2_0) ? 0x20008040 : \ + 0x20008180) +#define HAB_M4_PERSISTENT_BYTES 0xB80 +#endif static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr) { @@ -39,13 +47,195 @@ static int verify_ivt_header(struct ivt_header *ivt_hdr) if (be16_to_cpu(ivt_hdr->length) != IVT_TOTAL_LENGTH) result = ivt_header_error("bad length", ivt_hdr); - if (ivt_hdr->version != IVT_HEADER_V1 && - ivt_hdr->version != IVT_HEADER_V2) + if ((ivt_hdr->version & HAB_MAJ_MASK) != HAB_MAJ_VER) result = ivt_header_error("bad version", ivt_hdr); return result; } +#ifdef CONFIG_ARM64 +#define FSL_SIP_HAB 0xC2000007 +#define FSL_SIP_HAB_AUTHENTICATE 0x00 +#define FSL_SIP_HAB_ENTRY 0x01 +#define FSL_SIP_HAB_EXIT 0x02 +#define FSL_SIP_HAB_REPORT_EVENT 0x03 +#define FSL_SIP_HAB_REPORT_STATUS 0x04 +#define FSL_SIP_HAB_FAILSAFE 0x05 +#define FSL_SIP_HAB_CHECK_TARGET 0x06 +static volatile gd_t *gd_save; +#endif + +static inline void save_gd(void) +{ +#ifdef CONFIG_ARM64 + gd_save = gd; +#endif +} + +static inline void restore_gd(void) +{ +#ifdef CONFIG_ARM64 + /* + * Make will already error that reserving x18 is not supported at the + * time of writing, clang: error: unknown argument: '-ffixed-x18' + */ + __asm__ volatile("mov x18, %0\n" : : "r" (gd_save)); +#endif +} + +enum hab_status hab_rvt_report_event(enum hab_status status, uint32_t index, + uint8_t *event, size_t *bytes) +{ + enum hab_status ret; + hab_rvt_report_event_t *hab_rvt_report_event_func; + hab_rvt_report_event_func = (hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + ret = (enum hab_status)call_imx_sip(FSL_SIP_HAB, FSL_SIP_HAB_REPORT_EVENT, (unsigned long)index, + (unsigned long)event, (unsigned long)bytes); + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_report_event_func(status, index, event, bytes); + restore_gd(); + + return ret; + +} + +enum hab_status hab_rvt_report_status(enum hab_config *config, + enum hab_state *state) +{ + enum hab_status ret; + hab_rvt_report_status_t *hab_rvt_report_status_func; + hab_rvt_report_status_func = (hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + ret = (enum hab_status)call_imx_sip(FSL_SIP_HAB, FSL_SIP_HAB_REPORT_STATUS, + (unsigned long)config, (unsigned long)state, 0); + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_report_status_func(config, state); + restore_gd(); + + return ret; +} + +enum hab_status hab_rvt_entry(void) +{ + enum hab_status ret; + hab_rvt_entry_t *hab_rvt_entry_func; + hab_rvt_entry_func = (hab_rvt_entry_t *)HAB_RVT_ENTRY; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + ret = (enum hab_status)call_imx_sip(FSL_SIP_HAB, FSL_SIP_HAB_ENTRY, 0, 0, 0); + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_entry_func(); + restore_gd(); + + return ret; +} + +enum hab_status hab_rvt_exit(void) +{ + enum hab_status ret; + hab_rvt_exit_t *hab_rvt_exit_func; + hab_rvt_exit_func = (hab_rvt_exit_t *)HAB_RVT_EXIT; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + ret = (enum hab_status)call_imx_sip(FSL_SIP_HAB, FSL_SIP_HAB_EXIT, 0, 0, 0); + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_exit_func(); + restore_gd(); + + return ret; +} + +void hab_rvt_failsafe(void) +{ + hab_rvt_failsafe_t *hab_rvt_failsafe_func; + hab_rvt_failsafe_func = (hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + call_imx_sip(FSL_SIP_HAB, FSL_SIP_HAB_FAILSAFE, 0, 0, 0); + return; + } +#endif + + save_gd(); + hab_rvt_failsafe_func(); + restore_gd(); +} + +enum hab_status hab_rvt_check_target(enum hab_target type, const void *start, + size_t bytes) +{ + enum hab_status ret; + hab_rvt_check_target_t *hab_rvt_check_target_func; + hab_rvt_check_target_func = (hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + ret = (enum hab_status)call_imx_sip(FSL_SIP_HAB, FSL_SIP_HAB_CHECK_TARGET, (unsigned long)type, + (unsigned long)start, (unsigned long)bytes); + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_check_target_func(type, start, bytes); + restore_gd(); + + return ret; +} + +void *hab_rvt_authenticate_image(uint8_t cid, ptrdiff_t ivt_offset, + void **start, size_t *bytes, hab_loader_callback_f_t loader) +{ + void *ret; + hab_rvt_authenticate_image_t *hab_rvt_authenticate_image_func; + hab_rvt_authenticate_image_func = (hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + ret = (void *)call_imx_sip(FSL_SIP_HAB, FSL_SIP_HAB_AUTHENTICATE, (unsigned long)ivt_offset, + (unsigned long)start, (unsigned long)bytes); + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_authenticate_image_func(cid, ivt_offset, start, bytes, loader); + restore_gd(); + + return ret; +} + #if !defined(CONFIG_SPL_BUILD) #define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */ @@ -251,12 +441,6 @@ static int get_hab_status(void) size_t bytes = sizeof(event_data); /* Event size in bytes */ enum hab_config config = 0; enum hab_state state = 0; - hab_rvt_report_event_t *hab_rvt_report_event; - hab_rvt_report_status_t *hab_rvt_report_status; - - hab_rvt_report_event = (hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT; - hab_rvt_report_status = - (hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS; if (imx_hab_is_enabled()) puts("\nSecure boot enabled\n"); @@ -268,8 +452,8 @@ static int get_hab_status(void) printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", config, state); - /* Display HAB Error events */ - while (hab_rvt_report_event(HAB_FAILURE, index, event_data, + /* Display HAB events */ + while (hab_rvt_report_event(HAB_STS_ANY, index, event_data, &bytes) == HAB_SUCCESS) { puts("\n"); printf("--------- HAB Event %d -----------------\n", @@ -290,15 +474,99 @@ static int get_hab_status(void) return 0; } +#ifdef CONFIG_MX7ULP + +static int get_record_len(struct record *rec) +{ + return (size_t)((rec->len[0] << 8) + (rec->len[1])); +} + +static int get_hab_status_m4(void) +{ + unsigned int index = 0; + uint8_t event_data[128]; + size_t record_len, offset = 0; + enum hab_config config = 0; + enum hab_state state = 0; + + if (imx_hab_is_enabled()) + puts("\nSecure boot enabled\n"); + else + puts("\nSecure boot disabled\n"); + + /* + * HAB in both A7 and M4 gather the security state + * and configuration of the chip from + * shared SNVS module + */ + hab_rvt_report_status(&config, &state); + printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + + struct record *rec = (struct record *)(HAB_M4_PERSISTENT_START); + + record_len = get_record_len(rec); + + /* Check if HAB persistent memory is valid */ + if (rec->tag != HAB_TAG_EVT_DEF || + record_len != sizeof(struct evt_def) || + (rec->par & HAB_MAJ_MASK) != HAB_MAJ_VER) { + puts("\nERROR: Invalid HAB persistent memory\n"); + return 1; + } + + /* Parse events in HAB M4 persistent memory region */ + while (offset < HAB_M4_PERSISTENT_BYTES) { + rec = (struct record *)(HAB_M4_PERSISTENT_START + offset); + + record_len = get_record_len(rec); + + if (rec->tag == HAB_TAG_EVT) { + memcpy(&event_data, rec, record_len); + puts("\n"); + printf("--------- HAB Event %d -----------------\n", + index + 1); + puts("event data:\n"); + display_event(event_data, record_len); + puts("\n"); + index++; + } + + offset += record_len; + + /* Ensure all records start on a word boundary */ + if ((offset % 4) != 0) + offset = offset + (4 - (offset % 4)); + } + + if (!index) + puts("No HAB Events Found!\n\n"); + + return 0; +} +#endif + static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +#ifdef CONFIG_MX7ULP + if ((argc > 2)) { + cmd_usage(cmdtp); + return 1; + } + + if (strcmp("m4", argv[1]) == 0) + get_hab_status_m4(); + else + get_hab_status(); +#else if ((argc != 1)) { cmd_usage(cmdtp); return 1; } get_hab_status(); +#endif return 0; } @@ -328,24 +596,30 @@ static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc, static int do_hab_failsafe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - hab_rvt_failsafe_t *hab_rvt_failsafe; - if (argc != 1) { cmd_usage(cmdtp); return 1; } - hab_rvt_failsafe = (hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE; hab_rvt_failsafe(); return 0; } +#ifdef CONFIG_MX7ULP +U_BOOT_CMD( + hab_status, CONFIG_SYS_MAXARGS, 2, do_hab_status, + "display HAB status and events", + "hab_status - A7 HAB event and status\n" + "hab_status m4 - M4 HAB event and status" + ); +#else U_BOOT_CMD( hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, "display HAB status", "" ); +#endif U_BOOT_CMD( hab_auth_img, 4, 0, do_authenticate_image, @@ -412,7 +686,7 @@ static bool csf_is_valid(struct ivt *ivt, ulong start_addr, size_t bytes) return false; } - csf_hdr = (u8 *)ivt->csf; + csf_hdr = (u8 *)(ulong)ivt->csf; /* Verify if CSF Header exist */ if (*csf_hdr != HAB_CMD_HDR) { @@ -461,6 +735,48 @@ static bool csf_is_valid(struct ivt *ivt, ulong start_addr, size_t bytes) return true; } +/* + * Validate IVT structure of the image being authenticated + */ +static int validate_ivt(struct ivt *ivt_initial) +{ + struct ivt_header *ivt_hdr = &ivt_initial->hdr; + + if ((ulong)ivt_initial & 0x3) { + puts("Error: Image's start address is not 4 byte aligned\n"); + return 0; + } + + /* Check IVT fields before allowing authentication */ + if ((!verify_ivt_header(ivt_hdr)) && \ + (ivt_initial->entry != 0x0) && \ + (ivt_initial->reserved1 == 0x0) && \ + (ivt_initial->self == \ + (uint32_t)((ulong)ivt_initial & 0xffffffff)) && \ + (ivt_initial->csf != 0x0) && \ + (ivt_initial->reserved2 == 0x0)) { + /* Report boot failure if DCD pointer is found in IVT */ + if (ivt_initial->dcd != 0x0) + puts("Error: DCD pointer must be 0\n"); + else + return 1; + } + + puts("Error: Invalid IVT structure\n"); + puts("\nAllowed IVT structure:\n"); + puts("IVT HDR = 0x4X2000D1\n"); + puts("IVT ENTRY = 0xXXXXXXXX\n"); + puts("IVT RSV1 = 0x0\n"); + puts("IVT DCD = 0x0\n"); /* Recommended */ + puts("IVT BOOT_DATA = 0xXXXXXXXX\n"); /* Commonly 0x0 */ + puts("IVT SELF = 0xXXXXXXXX\n"); /* = ddr_start + ivt_offset */ + puts("IVT CSF = 0xXXXXXXXX\n"); + puts("IVT RSV2 = 0x0\n"); + + /* Invalid IVT structure */ + return 0; +} + bool imx_hab_is_enabled(void) { struct imx_sec_config_fuse_t *fuse = @@ -480,29 +796,16 @@ bool imx_hab_is_enabled(void) int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, uint32_t ivt_offset) { - uint32_t load_addr = 0; + ulong load_addr = 0; size_t bytes; - uint32_t ivt_addr = 0; + ulong ivt_addr = 0; int result = 1; ulong start; - hab_rvt_authenticate_image_t *hab_rvt_authenticate_image; - hab_rvt_entry_t *hab_rvt_entry; - hab_rvt_exit_t *hab_rvt_exit; - hab_rvt_check_target_t *hab_rvt_check_target; struct ivt *ivt; - struct ivt_header *ivt_hdr; enum hab_status status; - hab_rvt_authenticate_image = - (hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE; - hab_rvt_entry = (hab_rvt_entry_t *)HAB_RVT_ENTRY; - hab_rvt_exit = (hab_rvt_exit_t *)HAB_RVT_EXIT; - hab_rvt_check_target = (hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET; - - if (!imx_hab_is_enabled()) { + if (!imx_hab_is_enabled()) puts("hab fuse not enabled\n"); - return 0; - } printf("\nAuthenticate image from DDR location 0x%x...\n", ddr_start); @@ -510,24 +813,12 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, hab_caam_clock_enable(1); /* Calculate IVT address header */ - ivt_addr = ddr_start + ivt_offset; + ivt_addr = (ulong) (ddr_start + ivt_offset); ivt = (struct ivt *)ivt_addr; - ivt_hdr = &ivt->hdr; /* Verify IVT header bugging out on error */ - if (verify_ivt_header(ivt_hdr)) - goto hab_authentication_exit; - - /* Verify IVT body */ - if (ivt->self != ivt_addr) { - printf("ivt->self 0x%08x pointer is 0x%08x\n", - ivt->self, ivt_addr); + if (!validate_ivt(ivt)) goto hab_authentication_exit; - } - - /* Verify if IVT DCD pointer is NULL */ - if (ivt->dcd) - puts("Warning: DCD pointer should be NULL\n"); start = ddr_start; bytes = image_size; @@ -541,14 +832,14 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, goto hab_exit_failure_print_status; } - status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)ddr_start, bytes); + status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)(ulong)ddr_start, bytes); if (status != HAB_SUCCESS) { - printf("HAB check target 0x%08x-0x%08x fail\n", - ddr_start, ddr_start + bytes); + printf("HAB check target 0x%08x-0x%08lx fail\n", + ddr_start, ddr_start + (ulong)bytes); goto hab_exit_failure_print_status; } #ifdef DEBUG - printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr); + printf("\nivt_offset = 0x%x, ivt addr = 0x%lx\n", ivt_offset, ivt_addr); printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry, ivt->dcd, ivt->csf); puts("Dumping IVT\n"); @@ -566,6 +857,8 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, printf("\tstart = 0x%08lx\n", start); printf("\tbytes = 0x%x\n", bytes); #endif + +#ifndef CONFIG_ARM64 /* * If the MMU is enabled, we have to notify the ROM * code, or it won't flush the caches when needed. @@ -593,8 +886,9 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, writel(1, MX6SL_PU_IROM_MMU_EN_VAR); } } +#endif - load_addr = (uint32_t)hab_rvt_authenticate_image( + load_addr = (ulong)hab_rvt_authenticate_image( HAB_CID_UBOOT, ivt_offset, (void **)&start, (size_t *)&bytes, NULL); @@ -610,8 +904,20 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, hab_authentication_exit: - if (load_addr != 0) + if (load_addr != 0 || !imx_hab_is_enabled()) result = 0; return result; } + +int authenticate_image(uint32_t ddr_start, uint32_t raw_image_size) +{ + uint32_t ivt_offset; + size_t bytes; + + ivt_offset = (raw_image_size + ALIGN_SIZE - 1) & + ~(ALIGN_SIZE - 1); + bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE; + + return imx_hab_authenticate_image(ddr_start, bytes, ivt_offset); +} diff --git a/arch/arm/mach-imx/i2c-mxv7.c b/arch/arm/mach-imx/i2c-mxv7.c index dfb5c1e82f9..89bd362dbba 100644 --- a/arch/arm/mach-imx/i2c-mxv7.c +++ b/arch/arm/mach-imx/i2c-mxv7.c @@ -1,5 +1,7 @@ /* * Copyright (C) 2012 Boundary Devices Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -33,13 +35,36 @@ int force_idle_bus(void *priv) printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__, sda, scl, p->sda.gp, p->scl.gp); + gpio_direction_output(p->scl.gp, 1); + udelay(1000); /* Send high and low on the SCL line */ for (i = 0; i < 9; i++) { - gpio_direction_output(p->scl.gp, 0); + gpio_direction_output(p->scl.gp, 1); udelay(50); - gpio_direction_input(p->scl.gp); + gpio_direction_output(p->scl.gp, 0); udelay(50); } + + /* Simulate the NACK */ + gpio_direction_output(p->sda.gp, 1); + udelay(50); + gpio_direction_output(p->scl.gp, 1); + udelay(50); + gpio_direction_output(p->scl.gp, 0); + udelay(50); + + /* Simulate the STOP signal */ + gpio_direction_output(p->sda.gp, 0); + udelay(50); + gpio_direction_output(p->scl.gp, 1); + udelay(50); + gpio_direction_output(p->sda.gp, 1); + udelay(50); + + /* Get the bus status */ + gpio_direction_input(p->sda.gp); + gpio_direction_input(p->scl.gp); + start_time = get_timer(0); for (;;) { sda = gpio_get_value(p->sda.gp); diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig new file mode 100644 index 00000000000..4d01db7668c --- /dev/null +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -0,0 +1,97 @@ +if ARCH_IMX8 + +config HAVE_SC_FIRMWARE + bool + help + Have SCU on the SoC + +config RECOVER_SPL_DATA_SECTION + bool + help + Save SPL DATA section for cold boot, restore at warm boot + +config IMX_SMMU + bool "Enable SMMU on i.MX8" + help + Enable the SMMU for peripherals on i.MX8 + +config AHAB_BOOT + bool "Support i.MX8 AHAB features" + help + This option enables the support for AHAB secure boot. + +config IMX8 + bool + default y + +config IMX8QM + bool + select HAVE_SC_FIRMWARE + select RECOVER_SPL_DATA_SECTION + +config IMX8QXP + bool + select HAVE_SC_FIRMWARE + select RECOVER_SPL_DATA_SECTION + +config SYS_SOC + default "imx8" + +config SMC_FUSE + bool "Call fuse commands through SMC" + +config IMX8_TRUSTY_XEN + bool "Support Trusty Xen feature" + +choice + prompt "MX8 board select" + optional + +config TARGET_IMX8QM_LPDDR4_ARM2 + bool "Support i.MX8QM lpddr4 validation board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QM + +config TARGET_IMX8QM_DDR4_ARM2 + bool "Support i.MX8QM ddr4 validation board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QM + +config TARGET_IMX8QM_MEK + bool "Support i.MX8QM MEK board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QM + +config TARGET_IMX8QXP_LPDDR4_ARM2 + bool "Support i.MX8QXP lpddr4 validation board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QXP + +config TARGET_IMX8QXP_DDR3_ARM2 + bool "Support i.MX8QXP ddr3 validation board" + select BOARD_LATE_INIT + select IMX8QXP + +config TARGET_IMX8X_17X17_VAL + bool "Support i.MX8QXP/DX 17x17 validation board" + select BOARD_LATE_INIT + select IMX8QXP + +config TARGET_IMX8QXP_MEK + bool "Support i.MX8QXP MEK board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QXP + +endchoice + +source "board/freescale/imx8qm_arm2/Kconfig" +source "board/freescale/imx8qm_mek/Kconfig" +source "board/freescale/imx8qxp_arm2/Kconfig" +source "board/freescale/imx8qxp_mek/Kconfig" + +endif diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile new file mode 100644 index 00000000000..17572754950 --- /dev/null +++ b/arch/arm/mach-imx/imx8/Makefile @@ -0,0 +1,19 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += lowlevel_init.o +obj-y += cpu.o +obj-y += clock.o +obj-y += lpcg.o +obj-y += fsl_mu_hal.o +obj-y += fuse.o +obj-y += iomux.o +obj-$(CONFIG_SPL_BUILD) += image.o +obj-$(CONFIG_SPL_BUILD) += parser.o +ifneq ($(CONFIG_SPL_BUILD),y) +obj-y += partition.o +endif +obj-$(CONFIG_AHAB_BOOT) += ahab.o +obj-$(CONFIG_VIDEO_IMXDPUV1) += video_common.o diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c new file mode 100644 index 00000000000..df50862e9bd --- /dev/null +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -0,0 +1,339 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SEC_SECURE_RAM_BASE (0x31800000UL) +#define SEC_SECURE_RAM_END_BASE (SEC_SECURE_RAM_BASE + 0xFFFFUL) +#define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE (0x60000000UL) + +#define SECO_PT 2U + +static inline bool check_in_dram(ulong addr) +{ + int i; + bd_t *bd = gd->bd; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + if (bd->bi_dram[i].size) { + if (addr >= bd->bi_dram[i].start && + addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + return true; + } + } + + return false; +} + +int authenticate_os_container(ulong addr) +{ + struct container_hdr *phdr; + int i, ret = 0; + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + sc_err_t err; + sc_rm_mr_t mr; + sc_faddr_t start, end; + uint16_t length; + + if (addr % 4) { + puts("Error: Image's address is not 4 byte aligned\n"); + return -EINVAL; + } + + if (!check_in_dram(addr)) { + puts("Error: Image's address is invalid \n"); + return -EINVAL; + } + + phdr = (struct container_hdr *)addr; + if (phdr->tag != 0x87 && phdr->version != 0x0) { + printf("Error: Wrong container header\n"); + return -EFAULT; + } + + if (!phdr->num_images) { + printf("Error: Wrong container, no image found\n"); + return -EFAULT; + } + + length = phdr->length_lsb + (phdr->length_msb << 8); + + debug("container length %u\n", length); + memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)addr, ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); + + err = sc_seco_authenticate(ipcHndl, SC_MISC_AUTH_CONTAINER, SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); + if (err) { + printf("Error: authenticate container hdr failed, return %d\n", err); + ret = -EIO; + goto exit; + } + + /* Copy images to dest address */ + for (i=0; i < phdr->num_images; i++) { + struct boot_img_t *img = (struct boot_img_t *)(addr + sizeof(struct container_hdr) + i * sizeof(struct boot_img_t)); + + debug("img %d, dst 0x%llx, src 0x%lx, size 0x%x\n", i, img->dst, img->offset + addr, img->size); + + memcpy((void *)img->dst, (const void *)(img->offset + addr), img->size); + flush_dcache_range(img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE)); + + /* Find the memreg and set permission for seco pt */ + err = sc_rm_find_memreg(ipcHndl, &mr, + img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE)); + + if (err) { + printf("Error: can't find memreg for image load address %d, error %d\n", i, err); + ret = -ENOMEM; + goto exit; + } + + err = sc_rm_get_memreg_info(ipcHndl, mr, &start, &end); + if (!err) + debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); + + err = sc_rm_set_memreg_permissions(ipcHndl, mr, SECO_PT, SC_RM_PERM_FULL); + if (err) { + printf("Error: set permission failed for img %d, error %d\n", i, err); + ret = -EPERM; + goto exit; + } + + err = sc_seco_authenticate(ipcHndl, SC_MISC_VERIFY_IMAGE, (1 << i)); + if (err) { + printf("Error: authenticate img %d failed, return %d\n", i, err); + ret = -EIO; + } + + err = sc_rm_set_memreg_permissions(ipcHndl, mr, SECO_PT, SC_RM_PERM_NONE); + if (err) { + printf("Error: remove permission failed for img %d, error %d\n", i, err); + ret = -EPERM; + } + + if (ret) + goto exit; + } + +exit: + if (sc_seco_authenticate(ipcHndl, SC_MISC_REL_CONTAINER, 0) != SC_ERR_NONE) + printf("Error: release container failed!\n"); + + return ret; +} + + +static int do_authenticate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong addr; + if (argc < 2) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + + printf("Authenticate OS container at 0x%lx \n", addr); + + if (authenticate_os_container(addr)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static void display_life_cycle(uint16_t lc) +{ + printf("Lifecycle: 0x%04X, ", lc); + switch (lc) { + case 0x1: + printf("Pristine\n\n"); + break; + case 0x2: + printf("Fab\n\n"); + break; + case 0x8: + printf("Open\n\n"); + break; + case 0x20: + printf("NXP closed\n\n"); + break; + case 0x80: + printf("OEM closed\n\n"); + break; + case 0x100: + printf("Partial field return\n\n"); + break; + case 0x200: + printf("Full field return\n\n"); + break; + case 0x400: + printf("No return\n\n"); + break; + default: + printf("Unknown\n\n"); + break; + } +} + +#define AHAB_AUTH_CONTAINER_REQ 0x87 +#define AHAB_VERIFY_IMAGE_REQ 0x88 + +#define AHAB_NO_AUTHENTICATION_IND 0xee +#define AHAB_BAD_KEY_HASH_IND 0xfa +#define AHAB_INVALID_KEY_IND 0xf9 +#define AHAB_BAD_SIGNATURE_IND 0xf0 +#define AHAB_BAD_HASH_IND 0xf1 + +static void display_ahab_auth_event(uint32_t event) +{ + uint8_t cmd = (event >> 16) & 0xff; + uint8_t resp_ind =(event >> 8) & 0xff; + + switch (cmd) { + case AHAB_AUTH_CONTAINER_REQ: + printf("\tCMD = AHAB_AUTH_CONTAINER_REQ (0x%02X)\n", cmd); + printf("\tIND = "); + break; + case AHAB_VERIFY_IMAGE_REQ: + printf("\tCMD = AHAB_VERIFY_IMAGE_REQ (0x%02X)\n", cmd); + printf("\tIND = "); + break; + default: + return; + } + + switch (resp_ind) { + case AHAB_NO_AUTHENTICATION_IND: + printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_BAD_KEY_HASH_IND: + printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_INVALID_KEY_IND: + printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_BAD_SIGNATURE_IND: + printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_BAD_HASH_IND: + printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind); + break; + default: + printf("Unknown Indicator (0x%02X)\n\n", resp_ind); + break; + } +} + + +static int do_ahab_status(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + sc_err_t err; + uint8_t idx = 0U; + uint32_t event; + uint16_t lc; + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + + err = sc_seco_chip_info(ipcHndl, &lc, NULL, NULL, NULL); + if (err != SC_ERR_NONE) { + printf("Error in get lifecycle\n"); + return -EIO; + } + + display_life_cycle(lc); + + err = sc_seco_get_event(ipcHndl, idx, &event); + while (err == SC_ERR_NONE) { + printf ("SECO Event[%u] = 0x%08X\n", idx, event); + display_ahab_auth_event(event); + + idx++; + err = sc_seco_get_event(ipcHndl, idx, &event); + } + + if (idx == 0) + printf("No SECO Events Found!\n\n"); + + return 0; +} + +static int confirm_close(void) +{ + puts("Warning: Please ensure your sample is in NXP closed state, " + "OEM SRK hash has been fused, \n" + " and you are able to boot a signed image successfully " + "without any SECO events reported.\n" + " If not, your sample will be unrecoverable.\n" + "\nReally perform this operation? \n"); + + if (confirm_yesno()) + return 1; + + puts("Ahab close aborted\n"); + return 0; +} + +static int do_ahab_close(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + sc_err_t err; + uint16_t lc; + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + + if (!confirm_close()) + return -EACCES; + + err = sc_seco_chip_info(ipcHndl, &lc, NULL, NULL, NULL); + if (err != SC_ERR_NONE) { + printf("Error in get lifecycle\n"); + return -EIO; + } + + if (lc != 0x20) { + printf("Current lifecycle is NOT NXP closed, can't move to OEM closed\n"); + display_life_cycle(lc); + return -EPERM; + } + + err = sc_seco_forward_lifecycle(ipcHndl, 16); + if (err != SC_ERR_NONE) { + printf("Error in forward lifecycle to OEM closed\n"); + return -EIO; + } + + printf("Change to OEM closed successfully\n"); + + return 0; +} + +U_BOOT_CMD( + auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, + "autenticate OS container via AHAB", + "addr\n" + "addr - OS container hex address\n" +); + +U_BOOT_CMD( + ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status, + "display AHAB lifecycle and events from seco", + "" + ); + +U_BOOT_CMD( + ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close, + "Change AHAB lifecycle to OEM closed", + "" +); diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c new file mode 100644 index 00000000000..55c4aefd98f --- /dev/null +++ b/arch/arm/mach-imx/imx8/clock.c @@ -0,0 +1,466 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_lpuart_clk(void) +{ + return mxc_get_clock(MXC_UART_CLK); +} + +static u32 get_arm_main_clk(void) +{ + sc_err_t err; + sc_pm_clock_rate_t clkrate; + + if (is_cortex_a53()) + err = sc_pm_get_clock_rate((sc_ipc_t)gd->arch.ipc_channel_handle, + SC_R_A53, SC_PM_CLK_CPU, &clkrate); + else if (is_cortex_a72()) + err = sc_pm_get_clock_rate((sc_ipc_t)gd->arch.ipc_channel_handle, + SC_R_A72, SC_PM_CLK_CPU, &clkrate); + else if (is_cortex_a35()) + err = sc_pm_get_clock_rate((sc_ipc_t)gd->arch.ipc_channel_handle, + SC_R_A35, SC_PM_CLK_CPU, &clkrate); + else + err = SC_ERR_UNAVAILABLE; + + if (err != SC_ERR_NONE) { + printf("sc get ARM clk failed! err=%d\n", err); + return 0; + } + return clkrate; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + sc_err_t err; + sc_pm_clock_rate_t clkrate; + + switch (clk) { + case MXC_UART_CLK: + err = sc_pm_get_clock_rate((sc_ipc_t)gd->arch.ipc_channel_handle, + SC_R_UART_0, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get UART clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_ESDHC_CLK: + err = sc_pm_get_clock_rate((sc_ipc_t)gd->arch.ipc_channel_handle, + SC_R_SDHC_0, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get uSDHC1 clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_ESDHC2_CLK: + err = sc_pm_get_clock_rate((sc_ipc_t)gd->arch.ipc_channel_handle, + SC_R_SDHC_1, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get uSDHC2 clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_ESDHC3_CLK: + err = sc_pm_get_clock_rate((sc_ipc_t)gd->arch.ipc_channel_handle, + SC_R_SDHC_2, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get uSDHC3 clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_FEC_CLK: + err = sc_pm_get_clock_rate((sc_ipc_t)gd->arch.ipc_channel_handle, + SC_R_ENET_0, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get ENET clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_FSPI_CLK: + err = sc_pm_get_clock_rate((sc_ipc_t)gd->arch.ipc_channel_handle, + SC_R_FSPI_0, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get FSPI clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_DDR_CLK: + err = sc_pm_get_clock_rate((sc_ipc_t)gd->arch.ipc_channel_handle, + SC_R_DRC_0, 0, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get DRC0 clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_ARM_CLK: + return get_arm_main_clk(); + default: + printf("Unsupported mxc_clock %d\n", clk); + break; + } + + return 0; +} + +u32 imx_get_fecclk(void) +{ + return mxc_get_clock(MXC_FEC_CLK); +} + +static struct imx_i2c_map *get_i2c_desc(unsigned i2c_num) +{ + int i; + for (i = 0; i < ARRAY_SIZE(imx_i2c_desc); i++) { + if (imx_i2c_desc[i].index == i2c_num) + return &imx_i2c_desc[i]; + } + return NULL; +} + +int enable_i2c_clk(unsigned char enable, unsigned i2c_num) +{ + sc_ipc_t ipc; + sc_err_t err; + struct imx_i2c_map *desc; + int i; + + desc = get_i2c_desc(i2c_num); + if (!desc) + return -EINVAL; + + ipc = gd->arch.ipc_channel_handle; + + if (enable) + err = sc_pm_clock_enable(ipc, + desc->rsrc, 2, true, false); + else + err = sc_pm_clock_enable(ipc, + desc->rsrc, 2, false, false); + + if (err != SC_ERR_NONE) { + printf("i2c clock error %d\n", err); + return -EPERM; + } + + for (i = 0; i < 4; i++) { + if (desc->lpcg[i] == 0) + break; + LPCG_AllClockOn(desc->lpcg[i]); + } + + return 0; +} + +u32 imx_get_i2cclk(unsigned i2c_num) +{ + sc_err_t err; + sc_ipc_t ipc; + u32 clock_rate; + struct imx_i2c_map *desc; + + desc = get_i2c_desc(i2c_num); + if (!desc) + return -EINVAL; + + ipc = gd->arch.ipc_channel_handle; + err = sc_pm_get_clock_rate(ipc, desc->rsrc, 2, + &clock_rate); + if (err != SC_ERR_NONE) + return 0; + + return clock_rate; +} + +void init_clk_fspi(int index) +{ + sc_err_t sciErr = 0; + sc_pm_clock_rate_t rate; + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + + /* Set FSPI0 clock root to 29 MHz */ + rate = 29000000; + sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_FSPI_0, SC_PM_CLK_PER, &rate); + if (sciErr != SC_ERR_NONE) { + puts("FSPI0 setrate failed\n"); + return; + } + + /* Enable FSPI0 clock root */ + sciErr = sc_pm_clock_enable(ipcHndl, SC_R_FSPI_0, SC_PM_CLK_PER, true, false); + if (sciErr != SC_ERR_NONE) { + puts("FSPI0 enable clock failed\n"); + return; + } + + LPCG_AllClockOn(FSPI_0_LPCG); + + return; +} + +void init_clk_gpmi_nand(void) +{ + sc_err_t sciErr = 0; + sc_pm_clock_rate_t rate; + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + + /* Set NAND BCH clock root to 50 MHz */ + rate = 50000000; + sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_NAND, SC_PM_CLK_PER, &rate); + if (sciErr != SC_ERR_NONE) { + puts("NAND BCH set rate failed\n"); + return; + } + + /* Enable NAND BCH clock root */ + sciErr = sc_pm_clock_enable(ipcHndl, SC_R_NAND, SC_PM_CLK_PER, true, false); + if (sciErr != SC_ERR_NONE) { + puts("NAND BCH enable clock failed\n"); + return; + } + + /* Set NAND GPMI clock root to 50 MHz */ + rate = 50000000; + sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_NAND, SC_PM_CLK_MST_BUS, &rate); + if (sciErr != SC_ERR_NONE) { + puts("NAND GPMI set rate failed\n"); + return; + } + + /* Enable NAND GPMI clock root */ + sciErr = sc_pm_clock_enable(ipcHndl, SC_R_NAND, SC_PM_CLK_MST_BUS, true, false); + if (sciErr != SC_ERR_NONE) { + puts("NAND GPMI enable clock failed\n"); + return; + } + + LPCG_AllClockOn(NAND_LPCG); + + return; +} + +void enable_usboh3_clk(unsigned char enable) +{ + LPCG_AllClockOn(USB_2_LPCG); + return; +} + +void init_clk_usb3(int index) +{ + sc_err_t err; + sc_ipc_t ipc; + + ipc = gd->arch.ipc_channel_handle; + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_MISC, true, false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_MST_BUS, true, false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_PER, true, false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + LPCG_AllClockOn(USB_3_LPCG); + return; +} + +int cdns3_enable_clks(int index) +{ + init_clk_usb3(index); + return 0; +} + +int cdns3_disable_clks(int index) +{ + sc_err_t err; + sc_ipc_t ipc; + + ipc = gd->arch.ipc_channel_handle; + + LPCG_AllClockOff(USB_3_LPCG); + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_MISC, false, false); + if (err != SC_ERR_NONE) + printf("USB3 disable clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_MST_BUS, false, false); + if (err != SC_ERR_NONE) + printf("USB3 disable clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_PER, false, false); + if (err != SC_ERR_NONE) + printf("USB3 disable clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + return 0; +} + +void init_clk_usdhc(u32 index) +{ +#ifdef CONFIG_IMX8QM + sc_rsrc_t usdhcs[] = {SC_R_SDHC_0, SC_R_SDHC_1, SC_R_SDHC_2}; + u32 instances = 3; +#else + sc_rsrc_t usdhcs[] = {SC_R_SDHC_0, SC_R_SDHC_1}; + u32 instances = 2; +#endif + + sc_err_t err; + sc_ipc_t ipc; + sc_pm_clock_rate_t actual = 400000000; + + ipc = gd->arch.ipc_channel_handle; + + if (index >= instances) + return; + + /* Must disable the clock before set clock parent */ + err = sc_pm_clock_enable(ipc, usdhcs[index], SC_PM_CLK_PER, false, false); + if (err != SC_ERR_NONE) { + printf("SDHC_%d per clk enable failed!\n", index); + return; + } + + /* + * IMX8QXP USDHC_CLK_ROOT default source from DPLL, but this DPLL + * do not stable, will cause usdhc data transfer crc error. So here + * is a workaround, let USDHC_CLK_ROOT source from AVPLL. Due to + * AVPLL is fixed to 1000MHz, so here config USDHC1_CLK_ROOT to 333MHz, + * USDHC2_CLK_ROOT to 200MHz, make eMMC HS400ES work at 166MHz, and SD + * SDR104 work at 200MHz. + */ + if (is_imx8qxp()) { + err = sc_pm_set_clock_parent(ipc, usdhcs[index], 2, SC_PM_PARENT_PLL1); + if (err != SC_ERR_NONE) + printf("SDHC_%d set clock parent failed!(error = %d)\n", index, err); + + if (index == 1) + actual = 200000000; + } + + err = sc_pm_set_clock_rate(ipc, usdhcs[index], 2, &actual); + if (err != SC_ERR_NONE) { + printf("SDHC_%d set clock failed! (error = %d)\n", index, err); + return; + } + + if (actual != 400000000) + debug("Actual rate for SDHC_%d is %d\n", index, actual); + + err = sc_pm_clock_enable(ipc, usdhcs[index], SC_PM_CLK_PER, true, false); + if (err != SC_ERR_NONE) { + printf("SDHC_%d per clk enable failed!\n", index); + return; + } + + LPCG_AllClockOn(USDHC_0_LPCG + index * 0x10000); +} + +void init_clk_fec(int index) +{ + sc_err_t err; + sc_ipc_t ipc; + sc_pm_clock_rate_t rate = 24000000; + sc_rsrc_t enet[2] = {SC_R_ENET_0, SC_R_ENET_1}; + + if (index > 1) + return; + + if (index == -1) + index = 0; + + ipc = gd->arch.ipc_channel_handle; + + /* Disable SC_R_ENET_0 clock root */ + err = sc_pm_clock_enable(ipc, enet[index], 0, false, false); + err |= sc_pm_clock_enable(ipc, enet[index], 2, false, false); + err |= sc_pm_clock_enable(ipc, enet[index], 4, false, false); + if (err != SC_ERR_NONE) { + printf("\nSC_R_ENET_0 set clock disable failed! (error = %d)\n", err); + return; + } + + /* Set SC_R_ENET_0 clock root to 250 MHz, the clkdiv is set to div 2 + * so finally RGMII TX clk is 125Mhz + */ + rate = 250000000; + + /* div = 8 clk_source = PLL_1 ss_slice #7 in verfication codes */ + err = sc_pm_set_clock_rate(ipc, enet[index], 2, &rate); + if (err != SC_ERR_NONE) { + printf("\nSC_R_ENET_0 set clock ref clock 125M failed! (error = %d)\n", err); + return; + } + + /* Enable SC_R_ENET_0 clock root */ + err = sc_pm_clock_enable(ipc, enet[index], 0, true, true); + err |= sc_pm_clock_enable(ipc, enet[index], 2, true, true); + err |= sc_pm_clock_enable(ipc, enet[index], 4, true, true); + if (err != SC_ERR_NONE) { + printf("\nSC_R_ENET_0 set clock enable failed! (error = %d)\n", err); + return; + } + + /* Configure GPR regisers */ + if (sc_misc_set_control(ipc, enet[index], SC_C_TXCLK, 0) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_TXCLK); + /* Enable divclk */ + if (sc_misc_set_control(ipc, enet[index], SC_C_CLKDIV, 1) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_CLKDIV); + if (sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_50, 1) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_DISABLE_50); + if (sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_125, 1) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_DISABLE_125); + if (sc_misc_set_control(ipc, enet[index], SC_C_SEL_125, 0) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_SEL_125); + if (sc_misc_set_control(ipc, enet[index], SC_C_IPG_STOP, 0) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_IPG_STOP); + + LPCG_AllClockOn(ENET_0_LPCG + index * 0x10000); +} + +/* + * Dump some core clockes. + */ +int do_mx8_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000); + printf("DRC %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); + printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); + printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); + printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); + printf("UART0 %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); + printf("FEC0 %8d kHz\n", mxc_get_clock(MXC_FEC_CLK) / 1000); + printf("FLEXSPI0 %8d kHz\n", mxc_get_clock(MXC_FSPI_CLK) / 1000); + + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_mx8_showclocks, + "display clocks", + "" +); diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c new file mode 100644 index 00000000000..5e970cb108c --- /dev/null +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -0,0 +1,2019 @@ +/* + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct edma_ch_map { + sc_rsrc_t ch_start_rsrc; + u32 ch_start_regs; + u32 ch_num; + const char* node_path; +}; + +u32 get_cpu_rev(void) +{ + sc_ipc_t ipcHndl; + uint32_t id = 0, rev = 0; + sc_err_t err; + + ipcHndl = gd->arch.ipc_channel_handle; + + err = sc_misc_get_control(ipcHndl, SC_R_SYSTEM, SC_C_ID, &id); + if (err != SC_ERR_NONE) + return 0; + + rev = (id >> 5) & 0xf; + id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */ + + return (id << 12) | rev; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +const char *get_imx8_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX8QM: + return "8QM"; /* i.MX8 Quad MAX */ + case MXC_CPU_IMX8QXP: + return "8QXP"; /* i.MX8 Quad XP */ + case MXC_CPU_IMX8DX: + return "8DX"; /* i.MX8 Dual X */ + default: + return "??"; + } +} + +const char *get_imx8_rev(u32 rev) +{ + switch (rev) { + case CHIP_REV_A: + return "A"; + case CHIP_REV_B: + return "B"; + default: + return "?"; + } +} + +const char *get_core_name(void) +{ + if (is_cortex_a53()) + return "A53"; + else if (is_cortex_a35()) + return "A35"; + else if (is_cortex_a72()) + return "A72"; + else + return "?"; +} + + +int print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX%s rev%s %s at %d MHz", + get_imx8_type((cpurev & 0xFF000) >> 12), + get_imx8_rev((cpurev & 0xFFF)), + get_core_name(), + mxc_get_clock(MXC_ARM_CLK) / 1000000); + +#if defined(CONFIG_IMX_SC_THERMAL) + struct udevice *thermal_dev; + int cpu_tmp, ret; + + if (is_imx8qm() && is_cortex_a72()) + ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal1", &thermal_dev); + else + ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0", &thermal_dev); + + if (!ret) { + ret = thermal_get_temp(thermal_dev, &cpu_tmp); + + if (!ret) + printf(" at %dC", cpu_tmp); + else + debug(" - invalid sensor data"); + } else { + debug(" - invalid sensor device"); + } +#endif + + printf("\n"); + return 0; +} +#endif + +#define BT_PASSOVER_TAG (0x504F) +struct pass_over_info_t *get_pass_over_info(void) +{ + struct pass_over_info_t *p = (struct pass_over_info_t *)PASS_OVER_INFO_ADDR; + + if (p->barker != BT_PASSOVER_TAG || p->len != sizeof(struct pass_over_info_t)) + return NULL; + + return p; +} + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_RECOVER_SPL_DATA_SECTION) +char __data_save_start[0] __attribute__((section(".__data_save_start"))); +char __data_save_end[0] __attribute__((section(".__data_save_end"))); + +u32 cold_reboot_flag = 1; + +static void save_restore_data(void) +{ + u32 data_size = __data_save_end - __data_save_start; + + if (cold_reboot_flag == 1) { + /* Save data section to data_save section */ + memcpy(__data_save_start, __data_save_start - data_size, data_size); + } else { + /* Restore the data_save section to data section */ + memcpy(__data_save_start - data_size, __data_save_start, data_size); + } + cold_reboot_flag++; +} +#endif + +int arch_cpu_init(void) +{ + sc_ipc_t ipcHndl = 0; + sc_err_t sciErr = 0; + struct pass_over_info_t *pass_over; + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_RECOVER_SPL_DATA_SECTION) + save_restore_data(); +#endif + + gd->arch.ipc_channel_handle = 0; + + /* Open IPC channel */ + sciErr = sc_ipc_open(&ipcHndl, SC_IPC_CH); + if (sciErr != SC_ERR_NONE) + return -EPERM; + + gd->arch.ipc_channel_handle = ipcHndl; + +/* Dual bootloader feature will require CAAM access, but JR0 and JR1 will be + * assigned to seco for imx8, use JR3 instead. + */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER) + if (sc_pm_set_resource_power_mode(ipcHndl, + SC_R_CAAM_JR3, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EPERM; + if (sc_pm_set_resource_power_mode(ipcHndl, + SC_R_CAAM_JR3_OUT, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EPERM; +#endif + + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + if (is_soc_rev(CHIP_REV_A)) { + pass_over = get_pass_over_info(); + if (pass_over && pass_over->g_ap_mu == 0) { + /* When ap_mu is 0, means the u-boot is boot from first container */ + sc_misc_boot_status(ipcHndl, SC_MISC_BOOT_STATUS_SUCCESS); + } + } + +#ifdef CONFIG_IMX_SMMU + sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SMMU, + SC_PM_PW_MODE_ON); + if (sciErr != SC_ERR_NONE) + return 0; +#endif + + return 0; +} + +u32 cpu_mask(void) +{ +#ifdef CONFIG_IMX8QM + return 0x3f; +#else + return 0xf; /*For IMX8QXP*/ +#endif +} + +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 +#define CHANGE_PENDING_BIT (1 << 0) +int imx8qm_wake_seconday_cores(void) +{ +#ifdef CONFIG_ARMV8_MULTIENTRY + sc_ipc_t ipcHndl; + u64 *table = get_spin_tbl_addr(); + + /* Clear spin table so that secondary processors + * observe the correct value after waking up from wfe. + */ + memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); + flush_dcache_range((unsigned long)table, + (unsigned long)table + + (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); + + /* Open IPC channel */ + if (sc_ipc_open(&ipcHndl, SC_IPC_CH) != SC_ERR_NONE) + return -EIO; + + __raw_writel(0xc, 0x52090000); + __raw_writel(1, 0x52090008); + + /* IPC to pwr up and boot other cores */ + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A53_1, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + if (sc_pm_cpu_start(ipcHndl, SC_R_A53_1, true, 0x80000000) != SC_ERR_NONE) + return -EIO; + + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A53_2, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + if (sc_pm_cpu_start(ipcHndl, SC_R_A53_2, true, 0x80000000) != SC_ERR_NONE) + return -EIO; + + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A53_3, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + if (sc_pm_cpu_start(ipcHndl, SC_R_A53_3, true, 0x80000000) != SC_ERR_NONE) + return -EIO; + + /* Enable snoop and dvm msg requests for a53 port on CCI slave interface 3 */ + __raw_writel(CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN, 0x52094000); + + while (__raw_readl(0x5209000c) & CHANGE_PENDING_BIT) + ; + + /* Pwr up cluster 1 and boot core 0*/ + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A72, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A72_0, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + if (sc_pm_cpu_start(ipcHndl, SC_R_A72_0, true, 0x80000000) != SC_ERR_NONE) + return -EIO; + + /* IPC to pwr up and boot core 1 */ + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A72_1, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + if (sc_pm_cpu_start(ipcHndl, SC_R_A72_1, true, 0x80000000) != SC_ERR_NONE) + return -EIO; + + /* Enable snoop and dvm msg requests for a72 port on CCI slave interface 4 */ + __raw_writel(CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN, 0x52095000); + + while (__raw_readl(0x5209000c) & CHANGE_PENDING_BIT) + ; +#endif + return 0; +} + +int imx8qxp_wake_secondary_cores(void) +{ +#ifdef CONFIG_ARMV8_MULTIENTRY + sc_ipc_t ipcHndl; + u64 *table = get_spin_tbl_addr(); + + /* Clear spin table so that secondary processors + * observe the correct value after waking up from wfe. + */ + memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); + flush_dcache_range((unsigned long)table, + (unsigned long)table + + (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); + + /* Open IPC channel */ + if (sc_ipc_open(&ipcHndl, SC_IPC_CH) != SC_ERR_NONE) + return -EIO; + + /* IPC to pwr up and boot other cores */ + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A35_1, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + if (sc_pm_cpu_start(ipcHndl, SC_R_A35_1, true, 0x80000000) != SC_ERR_NONE) + return -EIO; + + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A35_2, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + if (sc_pm_cpu_start(ipcHndl, SC_R_A35_2, true, 0x80000000) != SC_ERR_NONE) + return -EIO; + + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A35_3, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + if (sc_pm_cpu_start(ipcHndl, SC_R_A35_3, true, 0x80000000) != SC_ERR_NONE) + return -EIO; + +#endif + return 0; +} + +#if defined(CONFIG_IMX8QM) +#define FUSE_MAC0_WORD0 452 +#define FUSE_MAC0_WORD1 453 +#define FUSE_MAC1_WORD0 454 +#define FUSE_MAC1_WORD1 455 +#elif defined(CONFIG_IMX8QXP) +#define FUSE_MAC0_WORD0 708 +#define FUSE_MAC0_WORD1 709 +#define FUSE_MAC1_WORD0 710 +#define FUSE_MAC1_WORD1 711 +#endif + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + sc_err_t err; + sc_ipc_t ipc; + uint32_t val1 = 0, val2 = 0; + uint32_t word1, word2; + + ipc = gd->arch.ipc_channel_handle; + + if (dev_id == 0) { + word1 = FUSE_MAC0_WORD0; + word2 = FUSE_MAC0_WORD1; + } else { + word1 = FUSE_MAC1_WORD0; + word2 = FUSE_MAC1_WORD1; + } + + err = sc_misc_otp_fuse_read(ipc, word1, &val1); + if (err != SC_ERR_NONE) { + printf("%s fuse %d read error: %d\n", __func__, word1, err); + return; + } + + err = sc_misc_otp_fuse_read(ipc, word2, &val2); + if (err != SC_ERR_NONE) { + printf("%s fuse %d read error: %d\n", __func__, word2, err); + return; + } + + mac[0] = val1; + mac[1] = val1 >> 8; + mac[2] = val1 >> 16; + mac[3] = val1 >> 24; + mac[4] = val2; + mac[5] = val2 >> 8; +} + +#ifdef CONFIG_IMX_BOOTAUX + +#ifdef CONFIG_IMX8QM +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) +{ + sc_ipc_t ipcHndl; + sc_rsrc_t core_rsrc, mu_rsrc; + sc_faddr_t tcml_addr; + u32 tcml_size = SZ_128K; + ulong addr; + + ipcHndl = gd->arch.ipc_channel_handle; + + switch (core_id) { + case 0: + core_rsrc = SC_R_M4_0_PID0; + tcml_addr = 0x34FE0000; + mu_rsrc = SC_R_M4_0_MU_1A; + break; + case 1: + core_rsrc = SC_R_M4_1_PID0; + tcml_addr = 0x38FE0000; + mu_rsrc = SC_R_M4_1_MU_1A; + break; + default: + printf("Not support this core boot up, ID:%u\n", core_id); + return -EINVAL; + } + + addr = (sc_faddr_t)boot_private_data; + + if (addr >= tcml_addr && addr <= tcml_addr + tcml_size) { + printf("Wrong image address 0x%lx, should not in TCML\n", + addr); + return -EINVAL; + } + + printf("Power on M4 and MU\n"); + + if (sc_pm_set_resource_power_mode(ipcHndl, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + + if (sc_pm_set_resource_power_mode(ipcHndl, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + + printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr); + + if (addr != tcml_addr) + memcpy((void *)tcml_addr, (void *)addr, tcml_size); + + printf("Start M4 %u\n", core_id); + if (sc_pm_cpu_start(ipcHndl, core_rsrc, true, tcml_addr) != SC_ERR_NONE) + return -EIO; + + printf("bootaux complete\n"); + return 0; +} +#endif + +#ifdef CONFIG_IMX8QXP +static unsigned long load_elf_image_shdr(unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* Elf header structure pointer */ + Elf32_Shdr *shdr; /* Section header structure pointer */ + unsigned char *strtab = 0; /* String table pointer */ + unsigned char *image; /* Binary image pointer */ + int i; /* Loop counter */ + + ehdr = (Elf32_Ehdr *)addr; + + /* Find the section header string table for output info */ + shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + + (ehdr->e_shstrndx * sizeof(Elf32_Shdr))); + + if (shdr->sh_type == SHT_STRTAB) + strtab = (unsigned char *)(addr + shdr->sh_offset); + + /* Load each appropriate section */ + for (i = 0; i < ehdr->e_shnum; ++i) { + shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + + (i * sizeof(Elf32_Shdr))); + + if (!(shdr->sh_flags & SHF_ALLOC) || + shdr->sh_addr == 0 || shdr->sh_size == 0) { + continue; + } + + if (strtab) { + debug("%sing %s @ 0x%08lx (%ld bytes)\n", + (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load", + &strtab[shdr->sh_name], + (unsigned long)shdr->sh_addr, + (long)shdr->sh_size); + } + + if (shdr->sh_type == SHT_NOBITS) { + memset((void *)(uintptr_t)shdr->sh_addr, 0, + shdr->sh_size); + } else { + image = (unsigned char *)addr + shdr->sh_offset; + memcpy((void *)(uintptr_t)shdr->sh_addr, + (const void *)image, shdr->sh_size); + } + flush_cache(shdr->sh_addr, shdr->sh_size); + } + + return ehdr->e_entry; +} + +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) +{ + sc_ipc_t ipcHndl; + sc_rsrc_t core_rsrc, mu_rsrc = -1; + sc_faddr_t aux_core_ram; + u32 size; + ulong addr; + + ipcHndl = gd->arch.ipc_channel_handle; + + switch (core_id) { + case 0: + core_rsrc = SC_R_M4_0_PID0; + aux_core_ram = 0x34FE0000; + mu_rsrc = SC_R_M4_0_MU_1A; + size = SZ_128K; + break; + case 1: + core_rsrc = SC_R_DSP; + aux_core_ram = 0x596f8000; + size = SZ_2K; + break; + default: + printf("Not support this core boot up, ID:%u\n", core_id); + return -EINVAL; + } + + addr = (sc_faddr_t)boot_private_data; + + if (addr >= aux_core_ram && addr <= aux_core_ram + size) { + printf("Wrong image address 0x%lx, should not in aux core ram\n", + addr); + return -EINVAL; + } + + printf("Power on aux core %d\n", core_id); + + if (sc_pm_set_resource_power_mode(ipcHndl, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + + if (mu_rsrc != -1) { + if (sc_pm_set_resource_power_mode(ipcHndl, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + } + + if (core_id == 1) { + struct power_domain pd; + + if (sc_pm_clock_enable(ipcHndl, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) { + printf("Error enable clock\n"); + return -EIO; + } + + LPCG_AllClockOn(AUD_DSP_LPCG); + + if (!power_domain_lookup_name("audio_sai0", &pd)) { + if (power_domain_on(&pd)) { + printf("Error power on SAI0\n"); + return -EIO; + } + } + + if (!power_domain_lookup_name("audio_ocram", &pd)) { + if (power_domain_on(&pd)) { + printf("Error power on HIFI RAM\n"); + return -EIO; + } + } + + LPCG_AllClockOn(AUD_OCRAM_LPCG); + LPCG_AllClockOn(AUD_SAI_0_LPCG); + } + + printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram); + if (core_id == 0) { + /* M4 use bin file */ + memcpy((void *)aux_core_ram, (void *)addr, size); + } else { + /* HIFI use elf file */ + if (!valid_elf_image(addr)) + return -1; + addr = load_elf_image_shdr(addr); + } + + printf("Start %s\n", core_id == 0 ? "M4" : "HIFI"); + + if (sc_pm_cpu_start(ipcHndl, core_rsrc, true, aux_core_ram) != SC_ERR_NONE) + return -EIO; + + printf("bootaux complete\n"); + return 0; +} +#endif + +int arch_auxiliary_core_check_up(u32 core_id) +{ + sc_rsrc_t core_rsrc; + sc_pm_power_mode_t power_mode; + sc_ipc_t ipcHndl; + + ipcHndl = gd->arch.ipc_channel_handle; + + switch (core_id) { + case 0: + core_rsrc = SC_R_M4_0_PID0; + break; +#ifdef CONFIG_IMX8QM + case 1: + core_rsrc = SC_R_M4_1_PID0; + break; +#endif + default: + printf("Not support this core, ID:%u\n", core_id); + return 0; + } + + if (sc_pm_get_resource_power_mode(ipcHndl, core_rsrc, &power_mode) != SC_ERR_NONE) + return 0; + + if (power_mode != SC_PM_PW_MODE_OFF) + return 1; + + return 0; +} +#endif + +static bool check_owned_resource(sc_rsrc_t rsrc_id) +{ + sc_ipc_t ipcHndl = 0; + bool owned; + + ipcHndl = gd->arch.ipc_channel_handle; + + owned = sc_rm_is_resource_owned(ipcHndl, rsrc_id); + + return owned; +} + +#ifdef CONFIG_IMX_SMMU +struct smmu_sid dev_sids[] = { +}; + +sc_err_t imx8_config_smmu_sid(struct smmu_sid *dev_sids, int size) +{ + int i; + sc_err_t sciErr = SC_ERR_NONE; + + if ((dev_sids == NULL) || (size <= 0)) + return SC_ERR_NONE; + + for (i = 0; i < size; i++) { + if (!check_owned_resource(dev_sids[i].rsrc)) { + printf("%s rsrc[%d] not owned\n", __func__, dev_sids[i].rsrc); + continue; + } + sciErr = sc_rm_set_master_sid(gd->arch.ipc_channel_handle, + dev_sids[i].rsrc, + dev_sids[i].sid); + if (sciErr != SC_ERR_NONE) { + printf("set master sid error\n"); + return sciErr; + } + } + + return SC_ERR_NONE; +} +#endif + +void arch_preboot_os(void) +{ +#if defined(CONFIG_VIDEO_IMXDPUV1) + imxdpuv1_fb_disable(); +#endif +#ifdef CONFIG_IMX_SMMU + imx8_config_smmu_sid(dev_sids, ARRAY_SIZE(dev_sids)); +#endif +} + +enum boot_device get_boot_device(void) +{ + enum boot_device boot_dev = SD1_BOOT; + + sc_ipc_t ipcHndl = 0; + sc_rsrc_t dev_rsrc; + + /* Note we only support android in EMMC SDHC0 */ + if (IS_ENABLED(CONFIG_XEN)) + return MMC1_BOOT; + + ipcHndl = gd->arch.ipc_channel_handle; + sc_misc_get_boot_dev(ipcHndl, &dev_rsrc); + + switch (dev_rsrc) { + case SC_R_SDHC_0: + boot_dev = MMC1_BOOT; + break; + case SC_R_SDHC_1: + boot_dev = SD2_BOOT; + break; + case SC_R_SDHC_2: + boot_dev = SD3_BOOT; + break; + case SC_R_NAND: + boot_dev = NAND_BOOT; + break; + case SC_R_FSPI_0: + boot_dev = FLEXSPI_BOOT; + break; + case SC_R_SATA_0: + boot_dev = SATA_BOOT; + break; + case SC_R_USB_0: + case SC_R_USB_1: + case SC_R_USB_2: + boot_dev = USB_BOOT; + break; + default: + break; + } + + return boot_dev; +} + +bool is_usb_boot(void) +{ + return get_boot_device() == USB_BOOT; +} + +#if defined(CONFIG_ARCH_MISC_INIT) +#define FSL_SIP_BUILDINFO 0xC2000003 +#define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00 +extern uint32_t _end_ofs; + +static void set_buildinfo_to_env(uint32_t scfw, uint32_t secofw, char *mkimage, char *atf) +{ + if (!mkimage || !atf) + return; + + env_set("commit_mkimage", mkimage); + env_set("commit_atf", atf); + env_set_hex("commit_scfw", (ulong)scfw); + env_set_hex("commit_secofw", (ulong)secofw); +} + +static void acquire_buildinfo(void) +{ + sc_ipc_t ipc; + uint32_t sc_build = 0, sc_commit = 0; + uint32_t seco_build = 0, seco_commit = 0; + char *mkimage_commit, *temp; + uint64_t atf_commit = 0; + + ipc = gd->arch.ipc_channel_handle; + + /* Get SCFW build and commit id */ + sc_misc_build_info(ipc, &sc_build, &sc_commit); + if (sc_build == 0) { + debug("SCFW does not support build info\n"); + sc_commit = 0; /* Display 0 when the build info is not supported*/ + } + + /* Get SECO FW build and commit id */ + sc_seco_build_info(ipc, &seco_build, &seco_commit); + if (seco_build == 0) { + debug("SECO FW does not support build info\n"); + seco_commit = 0; /* Display 0 when the build info is not supported*/ + } + + /* Get imx-mkimage commit id. + * The imx-mkimage puts the commit hash behind the end of u-boot.bin + */ + mkimage_commit = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob)); + temp = mkimage_commit + 8; + *temp = '\0'; + + if (strlen(mkimage_commit) == 0) { + debug("IMX-MKIMAGE does not support build info\n"); + mkimage_commit = "0"; /* Display 0 */ + } + + /* Get ARM Trusted Firmware commit id */ + atf_commit = call_imx_sip(FSL_SIP_BUILDINFO, FSL_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0); + if (atf_commit == 0xffffffff) { + debug("ATF does not support build info\n"); + atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */ + } + + /* Set all to env */ + set_buildinfo_to_env(sc_commit, seco_commit, mkimage_commit, (char *)&atf_commit); + + printf("\n BuildInfo: \n - SCFW %08x, SECO-FW %08x, IMX-MKIMAGE %s, ATF %s\n - %s \n\n", + sc_commit, seco_commit, mkimage_commit, (char *)&atf_commit, U_BOOT_VERSION); +} + +int arch_misc_init(void) +{ + acquire_buildinfo(); + + return 0; +} +#endif + +int print_bootinfo(void) +{ + enum boot_device bt_dev; + bt_dev = get_boot_device(); + + puts("Boot: "); + switch (bt_dev) { + case SD1_BOOT: + puts("SD0\n"); + break; + case SD2_BOOT: + puts("SD1\n"); + break; + case SD3_BOOT: + puts("SD2\n"); + break; + case MMC1_BOOT: + puts("MMC0\n"); + break; + case MMC2_BOOT: + puts("MMC1\n"); + break; + case MMC3_BOOT: + puts("MMC2\n"); + break; + case FLEXSPI_BOOT: + puts("FLEXSPI\n"); + break; + case SATA_BOOT: + puts("SATA\n"); + break; + case NAND_BOOT: + puts("NAND\n"); + break; + case USB_BOOT: + puts("USB\n"); + break; + default: + printf("Unknown device %u\n", bt_dev); + break; + } + + return 0; +} + +#ifdef CONFIG_SERIAL_TAG +#define FUSE_UNIQUE_ID_WORD0 16 +#define FUSE_UNIQUE_ID_WORD1 17 +void get_board_serial(struct tag_serialnr *serialnr) +{ + sc_err_t err; + sc_ipc_t ipc; + uint32_t val1 = 0, val2 = 0; + uint32_t word1, word2; + + ipc = gd->arch.ipc_channel_handle; + + word1 = FUSE_UNIQUE_ID_WORD0; + word2 = FUSE_UNIQUE_ID_WORD1; + + err = sc_misc_otp_fuse_read(ipc, word1, &val1); + if (err != SC_ERR_NONE) { + printf("%s fuse %d read error: %d\n", __func__,word1, err); + return; + } + + err = sc_misc_otp_fuse_read(ipc, word2, &val2); + if (err != SC_ERR_NONE) { + printf("%s fuse %d read error: %d\n", __func__, word2, err); + return; + } + serialnr->low = val1; + serialnr->high = val2; +} +#endif /*CONFIG_SERIAL_TAG*/ + +__weak int board_mmc_get_env_dev(int devno) +{ + return CONFIG_SYS_MMC_ENV_DEV; +} + +int mmc_get_env_dev(void) +{ + sc_ipc_t ipcHndl = 0; + sc_rsrc_t dev_rsrc; + int devno; + + ipcHndl = gd->arch.ipc_channel_handle; + sc_misc_get_boot_dev(ipcHndl, &dev_rsrc); + + switch(dev_rsrc) { + case SC_R_SDHC_0: + devno = 0; + break; + case SC_R_SDHC_1: + devno = 1; + break; + case SC_R_SDHC_2: + devno = 2; + break; + default: + /* If not boot from sd/mmc, use default value */ + return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); + } + + return board_mmc_get_env_dev(devno); +} + +static bool check_owned_resources_in_pd_tree(void *blob, int nodeoff, + unsigned int *unowned_rsrc) +{ + unsigned int rsrc_id; + const fdt32_t *php; + + /* Search the ancestors nodes in current SS power-domain tree, + * if all ancestors' resources are owned, we can enable the node, + * otherwise any ancestor is not owned, we should disable the node. + */ + + do { + php = fdt_getprop(blob, nodeoff, "power-domains", NULL); + if (!php) { + debug(" - ignoring no power-domains\n"); + break; + } + nodeoff = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*php)); + + rsrc_id = fdtdec_get_uint(blob, nodeoff, "reg", 0); + if (rsrc_id == SC_R_NONE) { + debug("%s's power domain use SC_R_NONE\n", + fdt_get_name(blob, nodeoff, NULL)); + break; + } + + debug("power-domains node 0x%x, resource id %u\n", nodeoff, rsrc_id); + + if (!check_owned_resource(rsrc_id)) { + if (unowned_rsrc != NULL) + *unowned_rsrc = rsrc_id; + return false; + } + } while (fdt_node_check_compatible(blob, nodeoff, "nxp,imx8-pd")); + + return true; +} + +static int disable_fdt_node(void *blob, int nodeoffset) +{ + int rc, ret; + const char *status = "disabled"; + + do { + rc = fdt_setprop(blob, nodeoffset, "status", status, strlen(status) + 1); + if (rc) { + if (rc == -FDT_ERR_NOSPACE) { + ret = fdt_increase_size(blob, 512); + if (ret) + return ret; + } + } + } while (rc == -FDT_ERR_NOSPACE); + + return rc; +} + +static void fdt_edma_debug_int_array(u32 *array, int count, u32 stride) +{ +#ifdef DEBUG + int i; + for (i = 0; i < count; i++) { + printf("0x%x ", array[i]); + if (i % stride == stride - 1) + printf("\n"); + } + + printf("\n"); +#endif +} + +static void fdt_edma_debug_stringlist(const char *stringlist, int length) +{ +#ifdef DEBUG + int i = 0, len; + while (i < length) { + printf("%s\n", stringlist); + + len = strlen(stringlist) + 1; + i += len; + stringlist += len; + } + + printf("\n"); +#endif +} + +static void fdt_edma_swap_int_array(u32 *array, int count) +{ + int i; + for (i = 0; i < count; i++) { + array[i] = cpu_to_fdt32(array[i]); + } +} + +static int fdt_edma_update_int_array(u32 *array, int count, u32 *new_array, u32 stride, int *remove_array, int remove_count) +{ + int i = 0, j, curr = 0, new_cnt = 0; + + do { + if (remove_count && curr == remove_array[i]) { + i++; + remove_count--; + array += stride; + } else { + for (j = 0; j< stride; j++) { + *new_array = *array; + new_array++; + array++; + } + new_cnt+= j; + } + curr++; + } while ((curr * stride) < count); + + return new_cnt; +} + +static int fdt_edma_update_stringlist(const char *stringlist, int stringlist_count, char *newlist, int *remove_array, int remove_count) +{ + int i = 0, curr = 0, new_len = 0; + int length; + + debug("fdt_edma_update_stringlist, remove_cnt %d\n", remove_count); + + do { + if (remove_count && curr == remove_array[i]) { + debug("remove %s at %d\n", stringlist, remove_array[i]); + + length = strlen(stringlist) + 1; + stringlist += length; + i++; + remove_count--; + } else { + length = strlen(stringlist) + 1; + strcpy(newlist, stringlist); + + debug("copy %s, %s, curr %d, len %d\n", newlist, stringlist, curr, length); + + stringlist += length; + newlist += length; + new_len += length; + } + curr++; + } while (curr < stringlist_count); + + return new_len; +} + +static int fdt_edma_get_channel_id(u32 *regs, int index, struct edma_ch_map *edma) +{ + u32 ch_reg = regs[(index << 2) + 1]; + u32 ch_reg_size = regs[(index << 2) + 3]; + int ch_id = (ch_reg - edma->ch_start_regs) / ch_reg_size; + if (ch_id >= edma->ch_num) + return -1; + + return ch_id; +} + +static void update_fdt_edma_nodes(void *blob) +{ + struct edma_ch_map edma_qm[] = { + { SC_R_DMA_0_CH0, 0x5a200000, 32, "/dma-controller@5a1f0000"}, + { SC_R_DMA_1_CH0, 0x5aa00000, 32, "/dma-controller@5a9f0000"}, + { SC_R_DMA_2_CH0, 0x59200000, 5, "/dma-controller@591F0000"}, + { SC_R_DMA_2_CH5, 0x59250000, 27, "/dma-controller@591F0000"}, + { SC_R_DMA_3_CH0, 0x59a00000, 32, "/dma-controller@599F0000"}, + }; + + struct edma_ch_map edma_qxp[] = { + { SC_R_DMA_0_CH0, 0x59200000, 32, "/dma-controller@591F0000"}, + { SC_R_DMA_1_CH0, 0x59a00000, 32, "/dma-controller@599F0000"}, + { SC_R_DMA_2_CH0, 0x5a200000, 5, "/dma-controller@5a1f0000"}, + { SC_R_DMA_2_CH5, 0x5a250000, 27, "/dma-controller@5a1f0000"}, + { SC_R_DMA_3_CH0, 0x5aa00000, 32, "/dma-controller@5a9f0000"}, + }; + + u32 i, j, edma_size; + int nodeoff, ret; + struct edma_ch_map *edma_array; + + if (is_imx8qm()) { + edma_array = edma_qm; + edma_size = ARRAY_SIZE(edma_qm); + } else { + edma_array = edma_qxp; + edma_size = ARRAY_SIZE(edma_qxp); + } + + for (i = 0; i < edma_size; i++, edma_array++) { + u32 regs[128]; + u32 interrupts[96]; + u32 dma_channels; + int regs_count, interrupts_count, int_names_count; + + const char *list; + int list_len, newlist_len; + int remove[32]; + int remove_cnt = 0; + char * newlist; + + nodeoff = fdt_path_offset(blob, edma_array->node_path); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + printf("%s, %d\n", edma_array->node_path, nodeoff); + + regs_count = fdtdec_get_int_array_count(blob, nodeoff, "reg", regs, 128); + debug("regs_count %d\n", regs_count); + if (regs_count < 0) + continue; + + interrupts_count = fdtdec_get_int_array_count(blob, nodeoff, "interrupts", interrupts, 96); + debug("interrupts_count %d\n", interrupts_count); + if (interrupts_count < 0) + continue; + + dma_channels = fdtdec_get_uint(blob, nodeoff, "dma-channels", 0); + if (dma_channels == 0) + continue; + + list = fdt_getprop(blob, nodeoff, "interrupt-names", &list_len); + if (!list) + continue; + + int_names_count = fdt_stringlist_count(blob, nodeoff, "interrupt-names"); + + fdt_edma_debug_int_array(regs, regs_count, 4); + fdt_edma_debug_int_array(interrupts, interrupts_count, 3); + fdt_edma_debug_stringlist(list, list_len); + + for (j = 0; j < (regs_count >> 2); j++) { + int ch_id = fdt_edma_get_channel_id(regs, j, edma_array); + if (ch_id < 0) + continue; + + if (!check_owned_resource(edma_array->ch_start_rsrc + ch_id)) { + printf("remove edma items %d\n", j); + + dma_channels--; + + remove[remove_cnt] = j; + remove_cnt++; + } + } + + if (remove_cnt > 0) { + u32 new_regs[128]; + u32 new_interrupts[96]; + + regs_count = fdt_edma_update_int_array(regs, regs_count, new_regs, 4, remove, remove_cnt); + interrupts_count = fdt_edma_update_int_array(interrupts, interrupts_count, new_interrupts, 3, remove, remove_cnt); + + fdt_edma_debug_int_array(new_regs, regs_count, 4); + fdt_edma_debug_int_array(new_interrupts, interrupts_count, 3); + + fdt_edma_swap_int_array(new_regs, regs_count); + fdt_edma_swap_int_array(new_interrupts, interrupts_count); + + /* malloc a new string list */ + newlist = (char *)malloc(list_len); + if (!newlist) { + printf("malloc new string list failed, len=%d\n", list_len); + continue; + } + + newlist_len = fdt_edma_update_stringlist(list, int_names_count, newlist, remove, remove_cnt); + fdt_edma_debug_stringlist(newlist, newlist_len); + + ret = fdt_setprop(blob, nodeoff, "reg", new_regs, regs_count * sizeof(u32)); + if (ret) + printf("fdt_setprop regs error %d\n", ret); + + ret = fdt_setprop(blob, nodeoff, "interrupts", new_interrupts, interrupts_count * sizeof(u32)); + if (ret) + printf("fdt_setprop interrupts error %d\n", ret); + + ret = fdt_setprop_u32(blob, nodeoff, "dma-channels", dma_channels); + if (ret) + printf("fdt_setprop_u32 dma-channels error %d\n", ret); + + ret = fdt_setprop(blob, nodeoff, "interrupt-names", newlist, newlist_len); + if (ret) + printf("fdt_setprop interrupt-names error %d\n", ret); + + free(newlist); + } + } +} + +static void update_fdt_with_owned_resources(void *blob) +{ + /* Traverses the fdt nodes, + * check its power domain and use the resource id in the power domain + * for checking whether it is owned by current partition + */ + + int offset = 0, next_off; + int depth = 0, next_depth; + unsigned int rsrc_id; + int rc; + + for (offset = fdt_next_node(blob, offset, &depth); offset > 0; + offset = fdt_next_node(blob, offset, &depth)) { + + debug("Node name: %s, depth %d\n", fdt_get_name(blob, offset, NULL), depth); + + if (!fdtdec_get_is_enabled(blob, offset)) { + debug(" - ignoring disabled device\n"); + continue; + } + + if (!fdt_node_check_compatible(blob, offset, "nxp,imx8-pd")) { + /* Skip to next depth=1 node*/ + next_off = offset; + next_depth = depth; + do { + offset = next_off; + depth = next_depth; + next_off = fdt_next_node(blob, offset, &next_depth); + if (next_off < 0 || next_depth < 1) + break; + + debug("PD name: %s, offset %d, depth %d\n", + fdt_get_name(blob, next_off, NULL), next_off, next_depth); + } while (next_depth > 1); + + continue; + } + + if (!check_owned_resources_in_pd_tree(blob, offset, &rsrc_id)) { + /* If the resource is not owned, disable it in FDT */ + rc = disable_fdt_node(blob, offset); + if (!rc) + printf("Disable %s, resource id %u not owned\n", + fdt_get_name(blob, offset, NULL), rsrc_id); + else + printf("Unable to disable %s, err=%s\n", + fdt_get_name(blob, offset, NULL), fdt_strerror(rc)); + } + + } +} + +#ifdef CONFIG_IMX_SMMU +static int get_srsc_from_fdt_node_power_domain(void *blob, int device_offset) +{ + const fdt32_t *prop; + int pdnode_offset; + + prop = fdt_getprop(blob, device_offset, "power-domains", NULL); + if (!prop) { + debug("node %s has no power-domains\n", + fdt_get_name(blob, device_offset, NULL)); + return -ENOENT; + } + + pdnode_offset = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*prop)); + if (pdnode_offset < 0) { + pr_err("failed to fetch node %s power-domain", + fdt_get_name(blob, device_offset, NULL)); + return pdnode_offset; + } + + return fdtdec_get_uint(blob, pdnode_offset, "reg", -ENOENT); +} + +static int config_smmu_resource_sid(int rsrc, int sid) +{ + sc_err_t err; + + if (!check_owned_resource(rsrc)) { + printf("%s rsrc[%d] not owned\n", __func__, rsrc); + return -1; + } + err = sc_rm_set_master_sid(gd->arch.ipc_channel_handle, rsrc, sid); + debug("set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err); + if (err != SC_ERR_NONE) { + pr_err("fail set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err); + return -EINVAL; + } + + return 0; +} + +static int config_smmu_fdt_device_sid(void *blob, int device_offset, int sid) +{ + int rsrc; + int proplen; + const fdt32_t *prop; + const char *name = fdt_get_name(blob, device_offset, NULL); + + prop = fdt_getprop(blob, device_offset, "fsl,sc_rsrc_id", &proplen); + if (prop) { + int i; + + debug("configure node %s sid 0x%x for %d resources\n", + name, sid, (int)(proplen / sizeof(fdt32_t))); + for (i = 0; i < proplen / sizeof(fdt32_t); ++i) { + config_smmu_resource_sid(fdt32_to_cpu(prop[i]), sid); + } + + return 0; + } + + rsrc = get_srsc_from_fdt_node_power_domain(blob, device_offset); + debug("configure node %s sid 0x%x rsrc=%d\n", name, sid, rsrc); + if (rsrc < 0) { + debug("failed to determine SC_R_* for node %s\n", name); + return rsrc; + } + + return config_smmu_resource_sid(rsrc, sid); +} + +/* assign master sid based on iommu properties in fdt */ +static int config_smmu_fdt(void *blob) +{ + int offset, proplen, i; + const fdt32_t *prop; + const char *name; + + /* Legacy smmu bindings, still used by xen. */ + offset = fdt_node_offset_by_compatible(blob, 0, "arm,mmu-500"); + if (offset > 0 && (prop = fdt_getprop(blob, offset, "mmu-masters", &proplen))) + { + debug("found legacy mmu-masters property\n"); + + for (i = 0; i < proplen / 8; ++i) { + uint32_t phandle = fdt32_to_cpu(prop[2 * i]); + int sid = fdt32_to_cpu(prop[2 * i + 1]); + int device_offset; + + device_offset = fdt_node_offset_by_phandle(blob, phandle); + if (device_offset < 0) { + pr_err("Failed to fetch device reference from mmu_masters: %d", device_offset); + continue; + } + config_smmu_fdt_device_sid(blob, device_offset, sid); + } + + /* Ignore new bindings if old bindings found, just like linux. */ + return 0; + } + + /* Generic smmu bindings */ + offset = 0; + while ((offset = fdt_next_node(blob, offset, NULL)) > 0) + { + name = fdt_get_name(blob, offset, NULL); + prop = fdt_getprop(blob, offset, "iommus", &proplen); + if (!prop) + continue; + debug("node %s iommus proplen %d\n", name, proplen); + + if (proplen == 12) { + int sid = fdt32_to_cpu(prop[1]); + config_smmu_fdt_device_sid(blob, offset, sid); + } else if (proplen != 4) { + debug("node %s ignore unexpected iommus proplen=%d\n", name, proplen); + } + } + + return 0; +} +#endif + +#ifdef CONFIG_OF_SYSTEM_SETUP +static int ft_add_optee_node(void *fdt, bd_t *bd) +{ + const char *path, *subpath; + int offs; + + /* + * No TEE space allocated indicating no TEE running, so no + * need to add optee node in dts + */ + if (!rom_pointer[1]) + return 0; + + offs = fdt_increase_size(fdt, 512); + if (offs) { + printf("No Space for dtb\n"); + return 1; + } + + path = "/firmware"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + path = "/"; + offs = fdt_path_offset(fdt, path); + + if (offs < 0) { + printf("Could not find root node.\n"); + return 1; + } + + subpath = "firmware"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s node.\n", subpath); + } + } + + subpath = "optee"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s node.\n", subpath); + } + + fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz"); + fdt_setprop_string(fdt, offs, "method", "smc"); + + return 0; +} + +int ft_system_setup(void *blob, bd_t *bd) +{ +#if (CONFIG_BOOTAUX_RESERVED_MEM_SIZE != 0x00) + int off; + off = fdt_add_mem_rsv(blob, CONFIG_BOOTAUX_RESERVED_MEM_BASE, + CONFIG_BOOTAUX_RESERVED_MEM_SIZE); + if (off < 0) + printf("Failed to reserve memory for bootaux: %s\n", + fdt_strerror(off)); +#endif + +#ifndef CONFIG_SKIP_RESOURCE_CHECING + update_fdt_with_owned_resources(blob); +#endif + + update_fdt_edma_nodes(blob); +#ifdef CONFIG_IMX_SMMU + config_smmu_fdt(blob); +#endif + + ft_add_optee_node(blob, bd); + return 0; +} +#endif + +#define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */ + +static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, sc_faddr_t *addr_end) +{ + sc_ipc_t ipcHndl = 0; + sc_err_t sciErr = 0; + bool owned; + sc_faddr_t start, end; + + ipcHndl = gd->arch.ipc_channel_handle; + + if (ipcHndl) { + owned = sc_rm_is_memreg_owned(ipcHndl, mr); + if (owned) { + sciErr = sc_rm_get_memreg_info(ipcHndl, mr, &start, &end); + if (sciErr) { + printf("Memreg get info failed, %d\n", sciErr); + return -EINVAL; + } else { + debug("0x%llx -- 0x%llx\n", start, end); + + *addr_start = start; + *addr_end = end; + + return 0; + } + } + } + + return -EINVAL; +} + +phys_size_t get_effective_memsize(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end, start_aligned; + int err; + + if (IS_ENABLED(CONFIG_XEN)) + return PHYS_SDRAM_1_SIZE; + + for (mr = 0; mr < 64; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + start_aligned = roundup(start, MEMSTART_ALIGNMENT); + if (start_aligned > end) /* Too small memory region, not use it */ + continue; + + /* Find the memory region runs the u-boot */ + if (start >= PHYS_SDRAM_1 && start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) + && (start <= CONFIG_SYS_TEXT_BASE && CONFIG_SYS_TEXT_BASE <= end)){ + if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + return (end - PHYS_SDRAM_1 + 1); + else + return PHYS_SDRAM_1_SIZE; + } + } + } + + return PHYS_SDRAM_1_SIZE; +} + +int dram_init(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end; + int err; + + if (IS_ENABLED(CONFIG_XEN)) { + gd->ram_size = PHYS_SDRAM_1_SIZE; + gd->ram_size += PHYS_SDRAM_2_SIZE; + + return 0; + } + + for (mr = 0; mr < 64; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + start = roundup(start, MEMSTART_ALIGNMENT); + if (start > end) /* Too small memory region, not use it */ + continue; + + if (start >= PHYS_SDRAM_1 && start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) { + + if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + gd->ram_size += end - start + 1; + else + gd->ram_size += ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - start; + + } else if (start >= PHYS_SDRAM_2 && start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) { + + if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) + gd->ram_size += end - start + 1; + else + gd->ram_size += ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE) - start; + } + } + } + + /* If error, set to the default value */ + if (!gd->ram_size) { + gd->ram_size = PHYS_SDRAM_1_SIZE; + gd->ram_size += PHYS_SDRAM_2_SIZE; + } + return 0; +} + +static void dram_bank_sort(int current_bank) +{ + phys_addr_t start; + phys_size_t size; + while (current_bank > 0) { + if (gd->bd->bi_dram[current_bank - 1].start > gd->bd->bi_dram[current_bank].start) { + start = gd->bd->bi_dram[current_bank - 1].start; + size = gd->bd->bi_dram[current_bank - 1].size; + + gd->bd->bi_dram[current_bank - 1].start = gd->bd->bi_dram[current_bank].start; + gd->bd->bi_dram[current_bank - 1].size = gd->bd->bi_dram[current_bank].size; + + gd->bd->bi_dram[current_bank].start = start; + gd->bd->bi_dram[current_bank].size = size; + } + + current_bank--; + } +} + +int dram_init_banksize(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end; + int i = 0; + int err; + + if (IS_ENABLED(CONFIG_XEN)) { + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + + return 0; + } + + for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + start = roundup(start, MEMSTART_ALIGNMENT); + if (start > end) /* Too small memory region, not use it */ + continue; + + if (start >= PHYS_SDRAM_1 && start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) { + gd->bd->bi_dram[i].start = start; + + if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + gd->bd->bi_dram[i].size = end - start + 1; + else + gd->bd->bi_dram[i].size = ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - start; + + dram_bank_sort(i); + i++; + } else if (start >= PHYS_SDRAM_2 && start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) { + gd->bd->bi_dram[i].start = start; + + if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) + gd->bd->bi_dram[i].size = end - start + 1; + else + gd->bd->bi_dram[i].size = ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE) - start; + + dram_bank_sort(i); + i++; + } + + } + } + + /* If error, set to the default value */ + if (!i) { + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + } + + return 0; +} + +static u64 get_block_attrs(sc_faddr_t addr_start) +{ + if ((addr_start >= PHYS_SDRAM_1 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + || (addr_start >= PHYS_SDRAM_2 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) +#ifdef CONFIG_IMX_TRUSTY_OS + return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); +#else + return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); +#endif + + return (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN); +} + +static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + if (addr_start >= PHYS_SDRAM_1 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) { + if ((addr_end + 1) > ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + return ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - addr_start; + + } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) { + + if ((addr_end + 1) > ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) + return ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE) - addr_start; + } + + return (addr_end - addr_start + 1); +} + +#define MAX_PTE_ENTRIES 512 +#define MAX_MEM_MAP_REGIONS 16 + +static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS]; +struct mm_region *mem_map = imx8_mem_map; + +void enable_caches(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end; + int err, i; + + if (IS_ENABLED(CONFIG_XEN)) { + imx8_mem_map[0].virt = 0x00000000UL; + imx8_mem_map[0].phys = 0x00000000UL; + imx8_mem_map[0].size = 0x39000000UL; + imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + imx8_mem_map[1].virt = 0x39000000UL; + imx8_mem_map[1].phys = 0x39000000UL; + imx8_mem_map[1].size = 0x01000000UL; + imx8_mem_map[1].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); + + imx8_mem_map[2].virt = 0x40000000UL; + imx8_mem_map[2].phys = 0x40000000UL; + imx8_mem_map[2].size = 0x40000000UL; + imx8_mem_map[2].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + imx8_mem_map[3].virt = 0x80000000UL; + imx8_mem_map[3].phys = 0x80000000UL; + imx8_mem_map[3].size = 0x80000000UL; + imx8_mem_map[3].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); + + imx8_mem_map[4].virt = 0x100000000UL; + imx8_mem_map[4].phys = 0x100000000UL; + imx8_mem_map[4].size = 0x100000000UL; + imx8_mem_map[4].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + icache_enable(); + dcache_enable(); + + return; + } + + /* Create map for registers access from 0x1c000000 to 0x80000000*/ + imx8_mem_map[0].virt = 0x1c000000UL; + imx8_mem_map[0].phys = 0x1c000000UL; + imx8_mem_map[0].size = 0x64000000UL; + imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + i = 1; + +#ifdef CONFIG_IMX_VSERVICE_SHARED_BUFFER + imx8_mem_map[i].virt = CONFIG_IMX_VSERVICE_SHARED_BUFFER; + imx8_mem_map[i].phys = CONFIG_IMX_VSERVICE_SHARED_BUFFER; + imx8_mem_map[i].size = CONFIG_IMX_VSERVICE_SHARED_BUFFER_SIZE; + imx8_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + i++; +#endif + + for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + imx8_mem_map[i].virt = start; + imx8_mem_map[i].phys = start; + imx8_mem_map[i].size = get_block_size(start, end); + imx8_mem_map[i].attrs = get_block_attrs(start); + i++; + } + } + + if (i < MAX_MEM_MAP_REGIONS) { + imx8_mem_map[i].size = 0; + imx8_mem_map[i].attrs = 0; + } else { + printf("Error, need more MEM MAP REGIONS reserved\n"); + icache_enable(); + return; + } + + for (i = 0;i < MAX_MEM_MAP_REGIONS;i++) { + debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n", i, + imx8_mem_map[i].virt, imx8_mem_map[i].phys, imx8_mem_map[i].size, imx8_mem_map[i].attrs); + } + + icache_enable(); + dcache_enable(); +} + +#ifndef CONFIG_SYS_DCACHE_OFF +u64 get_page_table_size(void) +{ + u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); + u64 size = 0; + + /* For each memory region, the max table size: 2 level 3 tables + 2 level 2 tables + 1 level 1 table*/ + size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt; + + /* + * We need to duplicate our page table once to have an emergency pt to + * resort to when splitting page tables later on + */ + size *= 2; + + /* + * We may need to split page tables later on if dcache settings change, + * so reserve up to 4 (random pick) page tables for that. + */ + size += one_pt * 4; + + return size; +} +#endif + +static bool check_device_power_off(struct udevice *dev, + const char* permanent_on_devices[], int size) +{ + int i; + + for (i = 0; i < size; i++) { + if (!strcmp(dev->name, permanent_on_devices[i])) + return false; + } + + return true; +} + +void power_off_pd_devices(const char* permanent_on_devices[], int size) +{ + struct udevice *dev; + struct power_domain pd; + + for (uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); dev; + uclass_find_next_device(&dev)) { + + if (device_active(dev)) { + /* Power off active pd devices except the permanent power on devices */ + if (check_device_power_off(dev, permanent_on_devices, size)) { + pd.dev = dev; + power_domain_off(&pd); + } + } + } +} + +void disconnect_from_pc(void) +{ + int ret; + struct power_domain pd; + + if (!power_domain_lookup_name("conn_usb0", &pd)) { + ret = power_domain_on(&pd); + if (ret) { + printf("conn_usb0 Power up failed! (error = %d)\n", ret); + return; + } + + writel(0x0, USB_BASE_ADDR + 0x140); + + ret = power_domain_off(&pd); + if (ret) { + printf("conn_usb0 Power off failed! (error = %d)\n", ret); + return; + } + } else { + printf("conn_usb0 finding failed!\n"); + return; + } +} + +bool check_owned_udevice(struct udevice *dev) +{ + int ret; + sc_rsrc_t resource_id; + struct ofnode_phandle_args args; + + /* Get the resource id from its power-domain */ + ret = dev_read_phandle_with_args(dev, "power-domains", + "#power-domain-cells", 0, 0, &args); + if (ret) { + printf("no power-domains found\n"); + return false; + } + + /* Get the owner partition for resource*/ + resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE); + if (resource_id == SC_R_NONE) { + printf("Can't find the resource id for udev %s\n", dev->name); + return false; + } + + debug("udev %s, resource id %d\n", dev->name, resource_id); + + return check_owned_resource(resource_id); +} + +bool check_m4_parts_boot(void) +{ + sc_rm_pt_t m4_parts[2]; + sc_ipc_t ipc; + sc_err_t err; + + ipc = gd->arch.ipc_channel_handle; + + err = sc_rm_get_resource_owner(ipc, SC_R_M4_0_PID0, &m4_parts[0]); + if (err != SC_ERR_NONE) { + printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err); + return false; + } + + if (sc_pm_is_partition_started(ipc, m4_parts[0])) + return true; + + if (is_imx8qm()) { + err = sc_rm_get_resource_owner(ipc, SC_R_M4_1_PID0, &m4_parts[1]); + if (err != SC_ERR_NONE) { + printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err); + return false; + } + + if (sc_pm_is_partition_started(ipc, m4_parts[1])) + return true; + } + + return false; +} + +#ifdef CONFIG_IMX_VSERVICE +struct udevice * board_imx_vservice_find_mu(struct udevice *dev) +{ + int ret; + const char *m4_mu_name[2] = { + "mu@5d230000", + "mu@5d240000" + }; + struct udevice *m4_mu[2]; + sc_rm_pt_t m4_parts[2]; + sc_ipc_t ipc; + sc_err_t err; + struct ofnode_phandle_args args; + sc_rsrc_t resource_id; + sc_rm_pt_t resource_part; + + ipc = gd->arch.ipc_channel_handle; + + /* Get the resource id from its power-domain */ + ret = dev_read_phandle_with_args(dev, "power-domains", + "#power-domain-cells", 0, 0, &args); + if (ret) { + printf("Can't find the power-domains property for udev %s\n", dev->name); + return NULL; + } + + /* Get the owner partition for resource*/ + resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE); + if (resource_id == SC_R_NONE) { + printf("Can't find the resource id for udev %s\n", dev->name); + return NULL; + } + + err = sc_rm_get_resource_owner(ipc, resource_id, &resource_part); + if (err != SC_ERR_NONE) { + printf("%s get resource [%d] owner error: %d\n", __func__, resource_id, err); + return NULL; + } + + debug("udev %s, resource id %d, resource part %d\n", dev->name, resource_id, resource_part); + + /* MU8 for communication between M4_0 and u-boot, MU9 for M4_1 and u-boot */ + err = sc_rm_get_resource_owner(ipc, SC_R_M4_0_PID0, &m4_parts[0]); + if (err != SC_ERR_NONE) { + printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err); + return NULL; + } + + ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[0], &m4_mu[0]); + if (!ret) { + /* If the i2c is in m4_0 partition, return the mu8 */ + if (resource_part == m4_parts[0]) + return m4_mu[0]; + } + + if (is_imx8qm()) { + err = sc_rm_get_resource_owner(ipc, SC_R_M4_1_PID0, &m4_parts[1]); + if (err != SC_ERR_NONE) { + printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err); + return NULL; + } + + ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[1], &m4_mu[1]); + if (!ret) { + /* If the i2c is in m4_1 partition, return the mu9 */ + if (resource_part == m4_parts[1]) + return m4_mu[1]; + } + } + + return NULL; +} + +void * board_imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size) +{ + const char *m4_mu_name[2] = { + "mu@5d230000", + "mu@5d240000" + }; + + /* Each MU ownes 1M buffer */ + if (size <= 0x100000) { + if (!strcmp(node->mu_dev->name, m4_mu_name[0])) + return (void * )CONFIG_IMX_VSERVICE_SHARED_BUFFER; + else if (!strcmp(node->mu_dev->name, m4_mu_name[1])) + return (void * )(CONFIG_IMX_VSERVICE_SHARED_BUFFER + 0x100000); + else + return NULL; + } + + return NULL; +} +#endif + +/* imx8qxp i2c1 has lots of devices may used by both M4 and A core +* If A core partition does not own the resource, we will start +* virtual i2c driver. Otherwise use local i2c driver. +*/ +int board_imx_virt_i2c_bind(struct udevice *dev) +{ + if (check_owned_udevice(dev)) + return -ENODEV; + + return 0; +} + +int board_imx_lpi2c_bind(struct udevice *dev) +{ + if (check_owned_udevice(dev)) + return 0; + + return -ENODEV; +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + + if (spl_boot_list[0] == BOOT_DEVICE_SPI) { + /* Check whether we own the flexspi0, if not, use NOR boot */ + if (!check_owned_resource(SC_R_FSPI_0)) + spl_boot_list[0] = BOOT_DEVICE_NOR; + } +} diff --git a/arch/arm/mach-imx/imx8/fsl_mu_hal.c b/arch/arm/mach-imx/imx8/fsl_mu_hal.c new file mode 100644 index 00000000000..bff8994fd42 --- /dev/null +++ b/arch/arm/mach-imx/imx8/fsl_mu_hal.c @@ -0,0 +1,151 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*==========================================================================*/ +/*! + * @file fsl_mu_hal.c + * + * Source file containing the HAL API for the MU. + * + * @addtogroup MU_HAL + * @{ + */ +/*==========================================================================*/ + +#include +#if FSL_FEATURE_SOC_MU_COUNT + +/*FUNCTION********************************************************************** + * + * Function Name : MU_HAL_TrySendMsg + * Description : Try to send message to the other core. + * + *END**************************************************************************/ +mu_status_t MU_HAL_TrySendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg) +{ + assert(regIndex < MU_TR_COUNT); + + /* TX register is empty. */ + if (MU_HAL_IsTxEmpty(base, regIndex)) { + MU_WR_TR(base, regIndex, msg); + return kStatus_MU_Success; + } + + return kStatus_MU_TxNotEmpty; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_HAL_SendMsg + * Description : Wait and send message to the other core. + * + *END**************************************************************************/ +void MU_HAL_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg) +{ + assert(regIndex < MU_TR_COUNT); + uint32_t mask = MU_SR_TE0_MASK >> regIndex; + /* Wait TX register to be empty. */ + while (!(MU_RD_SR(base) & mask)) { } + MU_WR_TR(base, regIndex, msg); +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_HAL_TryReceiveMsg + * Description : Try to receive message from the other core. + * + *END**************************************************************************/ +mu_status_t MU_HAL_TryReceiveMsg(MU_Type *base, uint32_t regIndex, uint32_t *msg) +{ + assert(regIndex < MU_RR_COUNT); + + /* RX register is full. */ + if (MU_HAL_IsRxFull(base, regIndex)) { + *msg = MU_RD_RR(base, regIndex); + return kStatus_MU_Success; + } + + return kStatus_MU_RxNotFull; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_HAL_ReceiveMsg + * Description : Wait to receive message from the other core. + * + *END**************************************************************************/ +void MU_HAL_ReceiveMsg(MU_Type *base, uint32_t regIndex, uint32_t *msg) +{ + assert(regIndex < MU_TR_COUNT); + uint32_t mask = MU_SR_RF0_MASK >> regIndex; + + /* Wait RX register to be full. */ + while (!(MU_RD_SR(base) & mask)) { } + *msg = MU_RD_RR(base, regIndex); +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_HAL_TriggerGeneralInt + * Description : Trigger general purpose interrupt to the other core. + * + *END**************************************************************************/ +mu_status_t MU_HAL_TriggerGeneralInt(MU_Type *base, uint32_t index) +{ + /* Previous interrupt has been accepted. */ + if (MU_HAL_IsGeneralIntAccepted(base, index)) { + /* All interrupts have been accepted, trigger now. */ + MU_WR_CR_GIRn(base, (1U << (MU_GPn_COUNT - 1U)) >> index); + return kStatus_MU_Success; + } + + return kStatus_MU_IntPending; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_HAL_TrySetFlags + * Description : Try to set some bits of the 3-bit flag. + * + *END**************************************************************************/ +mu_status_t MU_HAL_TrySetFlags(MU_Type *base, uint32_t flags) +{ + if (MU_RD_SR_FUP(base)) + { + return kStatus_MU_FlagPending; + } + + MU_WR_CR(base, (MU_RD_CR(base) + & ~(MU_CR_GIRn_MASK | + MU_CR_NMI_MASK | + MU_CR_Fn_MASK)) + | flags); + return kStatus_MU_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_HAL_SetFlags + * Description : Block to set some bits of the 3-bit flag. + * + *END**************************************************************************/ +void MU_HAL_SetFlags(MU_Type *base, uint32_t flags) +{ + while (MU_RD_SR_FUP(base)) { } + MU_WR_CR(base, (MU_RD_CR(base) + & ~(MU_CR_GIRn_MASK | + MU_CR_NMI_MASK | + MU_CR_Fn_MASK)) + | flags); +} +#endif + +/******************************************************************************* + * EOF + ******************************************************************************/ + +/**@}*/ diff --git a/arch/arm/mach-imx/imx8/fuse.c b/arch/arm/mach-imx/imx8/fuse.c new file mode 100644 index 00000000000..104833ca704 --- /dev/null +++ b/arch/arm/mach-imx/imx8/fuse.c @@ -0,0 +1,111 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + + +#define FSL_ECC_WORD_START_1 0x10 +#define FSL_ECC_WORD_END_1 0x10F + +#ifdef CONFIG_IMX8QM +#define FSL_ECC_WORD_START_2 0x1A0 +#define FSL_ECC_WORD_END_2 0x1FF +#endif + +#ifdef CONFIG_IMX8QXP +#define FSL_ECC_WORD_START_2 0x220 +#define FSL_ECC_WORD_END_2 0x31F + +#define FSL_QXP_FUSE_GAP_START 0x110 +#define FSL_QXP_FUSE_GAP_END 0x21F +#endif + +#define FSL_SIP_OTP_READ 0xc200000A +#define FSL_SIP_OTP_WRITE 0xc200000B + +int fuse_read(u32 bank, u32 word, u32 *val) +{ + return fuse_sense(bank, word, val); +} + +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + if (bank != 0) { + printf("Invalid bank argument, ONLY bank 0 is supported\n"); + return -EINVAL; + } +#if defined(CONFIG_SMC_FUSE) + unsigned long ret = 0, value = 0; + ret = call_imx_sip_ret2(FSL_SIP_OTP_READ, (unsigned long)word, + &value, 0, 0); + *val = (u32)value; + return ret; +#else + sc_err_t err; + sc_ipc_t ipc; + + ipc = gd->arch.ipc_channel_handle; + + err = sc_misc_otp_fuse_read(ipc, word, val); + if (err != SC_ERR_NONE) { + printf("fuse read error: %d\n", err); + return -EIO; + } + + return 0; +#endif +} + +int fuse_prog(u32 bank, u32 word, u32 val) +{ + if (bank != 0) { + printf("Invalid bank argument, ONLY bank 0 is supported\n"); + return -EINVAL; + } +#ifdef CONFIG_IMX8QXP + if ((word >= FSL_QXP_FUSE_GAP_START) && (word <= FSL_QXP_FUSE_GAP_END)) { + printf("Invalid word argument for this SoC\n"); + return -EINVAL; + } +#endif + + if (((word >= FSL_ECC_WORD_START_1) && (word <= FSL_ECC_WORD_END_1)) || + ((word >= FSL_ECC_WORD_START_2) && (word <= FSL_ECC_WORD_END_2))) + { + puts("Warning: Words in this index range have ECC protection and\n" + "can only be programmed once per word. Individual bit operations will\n" + "be rejected after the first one. \n" + "\n\n Really program this word? \n"); + + if(!confirm_yesno()) { + puts("Word programming aborted\n"); + return -EPERM; + } + } + +#if defined(CONFIG_SMC_FUSE) + return call_imx_sip(FSL_SIP_OTP_WRITE, (unsigned long)word,\ + (unsigned long)val, 0, 0); +#else + printf("Program fuse to i.MX8 in u-boot is forbidden\n"); + return -EPERM; +#endif +} + +int fuse_override(u32 bank, u32 word, u32 val) +{ + printf("Override fuse to i.MX8 in u-boot is forbidden\n"); + return -EPERM; +} diff --git a/arch/arm/mach-imx/imx8/image.c b/arch/arm/mach-imx/imx8/image.c new file mode 100644 index 00000000000..6bae8debb06 --- /dev/null +++ b/arch/arm/mach-imx/imx8/image.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MMC_DEV 0 +#define QSPI_DEV 1 +#define NAND_DEV 2 +#define QSPI_NOR_DEV 3 + +static int __get_container_size(ulong addr) +{ + struct container_hdr *phdr; + struct boot_img_t *img_entry; + struct signature_block_hdr *sign_hdr; + uint8_t i = 0; + uint32_t max_offset = 0, img_end; + + phdr = (struct container_hdr *)addr; + if (phdr->tag != 0x87 && phdr->version != 0x0) { + debug("Wrong container header\n"); + return -EFAULT; + } + + max_offset = sizeof(struct container_hdr); + + img_entry = (struct boot_img_t *)(addr + sizeof(struct container_hdr)); + for (i=0; i< phdr->num_images; i++) { + img_end = img_entry->offset + img_entry->size; + if (img_end > max_offset) + max_offset = img_end; + + debug("img[%u], end = 0x%x\n", i, img_end); + + img_entry++; + } + + if (phdr->sig_blk_offset != 0) { + sign_hdr = (struct signature_block_hdr *)(addr + phdr->sig_blk_offset); + uint16_t len = sign_hdr->length_lsb + (sign_hdr->length_msb << 8); + + if (phdr->sig_blk_offset + len > max_offset) + max_offset = phdr->sig_blk_offset + len; + + debug("sigblk, end = 0x%x\n", phdr->sig_blk_offset + len); + } + + return max_offset; +} + +static int get_container_size(void *dev, int dev_type, unsigned long offset) +{ + uint8_t *buf = malloc(CONTAINER_HDR_ALIGNMENT); + int ret = 0; + + if (!buf) { + printf("Malloc buffer failed\n"); + return -ENOMEM; + } + +#ifdef CONFIG_SPL_MMC_SUPPORT + if (dev_type == MMC_DEV) { + unsigned long count = 0; + struct mmc *mmc = (struct mmc*)dev; + count = blk_dread(mmc_get_blk_desc(mmc), offset/mmc->read_bl_len, + CONTAINER_HDR_ALIGNMENT/mmc->read_bl_len, buf); + if (count == 0) { + printf("Read container image from MMC/SD failed\n"); + return -EIO; + } + } +#endif + +#ifdef CONFIG_SPL_SPI_LOAD + if (dev_type == QSPI_DEV) { + struct spi_flash *flash = (struct spi_flash *)dev; + ret = spi_flash_read(flash, offset, + CONTAINER_HDR_ALIGNMENT, buf); + if (ret != 0) { + printf("Read container image from QSPI failed\n"); + return -EIO; + } + } +#endif + +#ifdef CONFIG_SPL_NAND_SUPPORT + if (dev_type == NAND_DEV) { + ret = nand_spl_load_image(offset, CONTAINER_HDR_ALIGNMENT, buf); + if (ret != 0) { + printf("Read container image from NAND failed\n"); + return -EIO; + } + } +#endif + +#ifdef CONFIG_SPL_NOR_SUPPORT + if (dev_type == QSPI_NOR_DEV) { + memcpy(buf, (const void *)offset, CONTAINER_HDR_ALIGNMENT); + } +#endif + + ret = __get_container_size((ulong)buf); + + free(buf); + + return ret; +} + +static unsigned long get_boot_device_offset(void *dev, int dev_type) +{ + unsigned long offset = 0; + if (dev_type == MMC_DEV) { + struct mmc *mmc = (struct mmc*)dev; + + if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) { + offset = CONTAINER_HDR_MMCSD_OFFSET; + } else { + u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + + if (part == 1 || part == 2) { + if (is_imx8qxp() && is_soc_rev(CHIP_REV_B)) + offset = CONTAINER_HDR_MMCSD_OFFSET; + else + offset = CONTAINER_HDR_EMMC_OFFSET; + } else { + offset = CONTAINER_HDR_MMCSD_OFFSET; + } + } + } else if (dev_type == QSPI_DEV) { + offset = CONTAINER_HDR_QSPI_OFFSET; + } else if (dev_type == NAND_DEV) { + offset = CONTAINER_HDR_NAND_OFFSET; + } else if (dev_type == QSPI_NOR_DEV) { + offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000; + } + + return offset; +} + +static int get_imageset_end(void *dev, int dev_type) +{ + unsigned long offset1 = 0, offset2 = 0; + int value_container[2]; + + offset1 = get_boot_device_offset(dev, dev_type); + offset2 = CONTAINER_HDR_ALIGNMENT + offset1; + + value_container[0] = get_container_size(dev, dev_type, offset1); + if (value_container[0] < 0) { + printf("Parse seco container failed %d\n", value_container[0]); + return value_container[0]; + } + + debug("seco container size 0x%x\n", value_container[0]); + + value_container[1] = get_container_size(dev, dev_type, offset2); + if (value_container[1] < 0) { + debug("Parse scu container image failed %d, only seco container\n", value_container[1]); + return value_container[0] + offset1; /* return seco container total size */ + } + + debug("scu container size 0x%x\n", value_container[1]); + + return value_container[1] + offset2; +} + +#ifdef CONFIG_SPL_SPI_LOAD +unsigned long spl_spi_get_uboot_raw_sector(struct spi_flash *flash) +{ + int end; + + end = get_imageset_end(flash, QSPI_DEV); + end = ROUND(end, SZ_1K); + + printf("Load image from QSPI 0x%x\n", end); + + return end; +} +#endif + +#ifdef CONFIG_SPL_MMC_SUPPORT +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc) +{ + int end; + + end = get_imageset_end(mmc, MMC_DEV); + end = ROUND(end, SZ_1K); + + printf("Load image from MMC/SD 0x%x\n", end); + + return end/mmc->read_bl_len; +} +#endif + +#ifdef CONFIG_SPL_NAND_SUPPORT +uint32_t spl_nand_get_uboot_raw_page(void) +{ + int end; + + end = get_imageset_end((void *)NULL, NAND_DEV); + end = ROUND(end, SZ_16K); + + printf("Load image from NAND 0x%x\n", end); + + return end; +} +#endif + +#ifdef CONFIG_SPL_NOR_SUPPORT +unsigned long spl_nor_get_uboot_base(void) +{ + int end; + + /* Calculate the image set end, + * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000), + * we use CONFIG_SYS_UBOOT_BASE + * Otherwise, use the calculated address + */ + end = get_imageset_end((void *)NULL, QSPI_NOR_DEV); + if (end <= CONFIG_SYS_UBOOT_BASE) + end = CONFIG_SYS_UBOOT_BASE; + else + end = ROUND(end, SZ_1K); + + printf("Load image from NOR 0x%x\n", end); + + return end; +} +#endif diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c new file mode 100644 index 00000000000..a08066cd46a --- /dev/null +++ b/arch/arm/mach-imx/imx8/iomux.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * configures a single pad in the iomuxer + */ +void imx8_iomux_setup_pad(iomux_cfg_t pad) +{ + sc_err_t err; + sc_ipc_t ipc; + + sc_pad_t pin_id = pad & PIN_ID_MASK; + + uint32_t val = (uint32_t)((pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT); + + ipc = gd->arch.ipc_channel_handle; + + val |= PADRING_IFMUX_EN_MASK; + val |= PADRING_GP_EN_MASK; + + err = sc_pad_set(ipc, pin_id, val); + if (err != SC_ERR_NONE) + printf("imx8_iomux sc_pad_set failed!, pin = %u, val = 0x%x\n", pin_id, val); + + debug("iomux: pin %d, val = 0x%x\n", pin_id, val); +} + +/* configures a list of pads within declared with IOMUX_PADS macro */ +void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, + unsigned count) +{ + iomux_cfg_t const *p = pad_list; + int i; + + for (i = 0; i < count; i++) { + imx8_iomux_setup_pad(*p); + p++; + } +} diff --git a/arch/arm/mach-imx/imx8/lowlevel_init.S b/arch/arm/mach-imx/imx8/lowlevel_init.S new file mode 100644 index 00000000000..141b82dcb90 --- /dev/null +++ b/arch/arm/mach-imx/imx8/lowlevel_init.S @@ -0,0 +1,33 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +.align 8 +.global rom_pointer +rom_pointer: + .space 32 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: + /* The firmware provided ATAG/FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 + + /* Returns */ + b save_boot_params_ret + +.global restore_boot_params +restore_boot_params: + adr x0, rom_pointer + ldp x1, x2, [x0], #16 + ldp x3, x4, [x0], #16 + ret diff --git a/arch/arm/mach-imx/imx8/lpcg.c b/arch/arm/mach-imx/imx8/lpcg.c new file mode 100644 index 00000000000..22cbc605639 --- /dev/null +++ b/arch/arm/mach-imx/imx8/lpcg.c @@ -0,0 +1,101 @@ +/* + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define LPCG_CLOCK_MASK 0x3U +#define LPCG_CLOCK_OFF 0x0U +#define LPCG_CLOCK_ON 0x2U +#define LPCG_CLOCK_AUTO 0x3U +#define LPCG_CLOCK_STOP 0x8U + +#define LPCG_ALL_CLOCK_OFF 0x00000000U +#define LPCG_ALL_CLOCK_ON 0x22222222U +#define LPCG_ALL_CLOCK_AUTO 0x33333333U +#define LPCG_ALL_CLOCK_STOP 0x88888888U + +static inline void lpcg_write(u32 lpcgVal, ulong lpcg_addr) +{ + /* + * Write twice with 4x DSC clock cycles (40x IPS clock cycles) interval + * to work around LPCG issue + */ + writel(lpcgVal, lpcg_addr); + udelay(10); /* 10us is enough. Worst case is 40x IPS cycle (200Mhz) */ + writel(lpcgVal, lpcg_addr); + udelay(10); +} + +void LPCG_ClockOff(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_OFF) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +void LPCG_ClockOn(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_ON) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +void LPCG_ClockAutoGate(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_AUTO) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +void LPCG_AllClockOff(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_OFF, (ulong)lpcg_addr); +} + +void LPCG_AllClockOn(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_ON, (ulong)lpcg_addr); + + /* Wait for clocks to start */ + while ((readl((ulong)lpcg_addr) & LPCG_ALL_CLOCK_STOP) != 0U) + { + } +} + +void LPCG_AllClockAutoGate(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_AUTO, (ulong)lpcg_addr); +} diff --git a/arch/arm/mach-imx/imx8/parser.c b/arch/arm/mach-imx/imx8/parser.c new file mode 100644 index 00000000000..e639edbc2ca --- /dev/null +++ b/arch/arm/mach-imx/imx8/parser.c @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MMC_DEV 0 +#define QSPI_DEV 1 +#define NAND_DEV 2 +#define RAM_DEV 3 + +#define SEC_SECURE_RAM_BASE (0x31800000UL) +#define SEC_SECURE_RAM_END_BASE (SEC_SECURE_RAM_BASE + 0xFFFFUL) +#define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE (0x60000000UL) + +#define SECO_PT 2U + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_IMX_TRUSTY_OS) +/* Pre-declaration of check_rpmb_blob. */ +int check_rpmb_blob(struct mmc *mmc); +#endif + +static int current_dev_type = MMC_DEV; +static int start_offset; +static void *device; + +static int read(u32 start, u32 len, void *load_addr) +{ + int ret = -ENODEV; + + if (current_dev_type != NAND_DEV && current_dev_type != RAM_DEV + && !device) { + debug("No device selected\n"); + return ret; + } + +#ifdef CONFIG_SPL_MMC_SUPPORT + if (current_dev_type == MMC_DEV) { + struct mmc *mmc = (struct mmc *)device; + unsigned long count; + + ret = 0; + + count = blk_dread(mmc_get_blk_desc(mmc), + start / mmc->read_bl_len, + len / mmc->read_bl_len, + load_addr); + if (count == 0) { + debug("Read container image failed\n"); + return -EIO; + } + } +#endif +#ifdef CONFIG_SPL_SPI_LOAD + if (current_dev_type == QSPI_DEV) { + struct spi_flash *flash = (struct spi_flash *)device; + + ret = spi_flash_read(flash, start, + len, load_addr); + if (ret != 0) { + debug("Read container image from QSPI failed\n"); + return -EIO; + } + } +#endif +#ifdef CONFIG_SPL_NAND_SUPPORT + if (current_dev_type == NAND_DEV) { + ret = nand_spl_load_image(start, len, load_addr); + if (ret != 0) { + debug("Read container image from NAND failed\n"); + return -EIO; + } + } +#endif + + if (current_dev_type == RAM_DEV) { + memcpy(load_addr, (const void *)(ulong)start, len); + ret = 0; + } + + return ret; +} + +#ifdef CONFIG_AHAB_BOOT +static int authenticate_image(struct boot_img_t *img, int image_index) +{ + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + sc_faddr_t start, end; + sc_rm_mr_t mr; + sc_err_t err; + int ret = 0; + + debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n", + image_index, img->dst, img->offset, img->size); + + /* Find the memreg and set permission for seco pt */ + err = sc_rm_find_memreg(ipcHndl, &mr, + img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE)); + + if (err) { + printf("can't find memreg for image load address %d, error %d\n", + image_index, err); + return -ENOMEM; + } + + err = sc_rm_get_memreg_info(ipcHndl, mr, &start, &end); + if (!err) + debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); + + err = sc_rm_set_memreg_permissions(ipcHndl, mr, + SECO_PT, SC_RM_PERM_FULL); + if (err) { + printf("set permission failed for img %d, error %d\n", + image_index, err); + return -EPERM; + } + + err = sc_seco_authenticate(ipcHndl, SC_MISC_VERIFY_IMAGE, + 1 << image_index); + if (err) { + printf("authenticate img %d failed, return %d\n", + image_index, err); + ret = -EIO; + } + + err = sc_rm_set_memreg_permissions(ipcHndl, mr, + SECO_PT, SC_RM_PERM_NONE); + if (err) { + printf("remove permission failed for img %d, error %d\n", + image_index, err); + ret = -EPERM; + } + + return ret; +} +#endif + +static struct boot_img_t *read_auth_image(struct container_hdr *container, + int image_index) +{ + struct boot_img_t *images; + + if (image_index > container->num_images) { + debug("Invalid image number\n"); + return NULL; + } + + images = (struct boot_img_t *) + ((uint8_t *)container + sizeof(struct container_hdr)); + + if (read(images[image_index].offset + start_offset, + images[image_index].size, + (void *)images[image_index].entry) < 0) { + return NULL; + } + +#ifdef CONFIG_AHAB_BOOT + if (authenticate_image(&images[image_index], image_index)) { + printf("Failed to authenticate image %d\n", image_index); + return NULL; + } +#endif + + return &images[image_index]; +} + +static int read_auth_container(struct spl_image_info *spl_image) +{ +#ifdef CONFIG_AHAB_BOOT + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; +#endif + struct container_hdr *container = NULL; + uint16_t length; + int ret; + int i; + + container = malloc(CONTAINER_HDR_ALIGNMENT); + if (!container) + return -ENOMEM; + + ret = read(start_offset, CONTAINER_HDR_ALIGNMENT, (void *)container); + if (ret) { + printf("Error in read container %d\n", ret); + goto out; + } + + if (container->tag != 0x87 && container->version != 0x0) { + printf("Wrong container header\n"); + ret = -EFAULT; + goto out; + } + + if (!container->num_images) { + printf("Wrong container, no image found\n"); + ret = -EFAULT; + goto out; + } + + length = container->length_lsb + (container->length_msb << 8); + + debug("container length %u\n", length); + + if (length > CONTAINER_HDR_ALIGNMENT) { + length = ALIGN(length, CONTAINER_HDR_ALIGNMENT); + + free(container); + container = malloc(length); + if (!container) + return -ENOMEM; + + ret = read(start_offset, length, (void *)container); + if (ret) { + printf("Error in read full container %d\n", ret); + goto out; + } + } + +#ifdef CONFIG_AHAB_BOOT + memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container, + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); + + ret = sc_seco_authenticate(ipcHndl, SC_MISC_AUTH_CONTAINER, + SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); + if (ret) { + printf("authenticate container hdr failed, return %d\n", ret); + ret = -EFAULT; + goto out; + } +#endif + + for (i = 0; i < container->num_images; i++) { + struct boot_img_t *image = read_auth_image(container, i); + + if (!image) { + ret = -EINVAL; + goto end_auth; + } + + if (i == 0) { + spl_image->load_addr = image->dst; + spl_image->entry_point = image->entry; + } + } + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER) + /* Everything checks out, get the sw_version now. */ + spl_image->rbindex = (uint64_t)container->sw_version; +#endif + +end_auth: +#ifdef CONFIG_AHAB_BOOT + if (sc_seco_authenticate(ipcHndl, SC_MISC_REL_CONTAINER, 0) != SC_ERR_NONE) + printf("Error: release container failed!\n"); +#endif +out: + free(container); + + return ret; +} + +int mmc_load_image_parse_container(struct spl_image_info *spl_image, + struct mmc *mmc, unsigned long sector) +{ + int ret = 0; + + current_dev_type = MMC_DEV; + device = mmc; + + start_offset = sector * mmc->read_bl_len; + + ret = read_auth_container(spl_image); + + if (!ret) + { + /* Images loaded, now check the rpmb keyblob for Trusty OS. + * Skip this step when the dual bootloader feature is enabled + * since the blob should be checked earlier. + */ +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_DUAL_BOOTLOADER) + ret = check_rpmb_blob(mmc); +#endif +#if defined(CONFIG_IMX8_TRUSTY_XEN) + struct mmc *rpmb_mmc; + + rpmb_mmc = find_mmc_device(0); + if (ret = mmc_init(rpmb_mmc)) + printf("mmc init failed %s\n", __func__); + else + ret = check_rpmb_blob(rpmb_mmc); +#endif + } + return ret; +} + +int spi_load_image_parse_container(struct spl_image_info *spl_image, + struct spi_flash *flash, + unsigned long offset) +{ + int ret = 0; + + current_dev_type = QSPI_DEV; + device = flash; + + start_offset = offset; + + ret = read_auth_container(spl_image); + + return ret; +} + +int nand_load_image_parse_container(struct spl_image_info *spl_image, + unsigned long offset) +{ + int ret = 0; + + current_dev_type = NAND_DEV; + device = NULL; + + start_offset = offset; + + ret = read_auth_container(spl_image); + + return ret; +} + +int sdp_load_image_parse_container(struct spl_image_info *spl_image, + unsigned long offset) +{ + int ret = 0; + + current_dev_type = RAM_DEV; + device = NULL; + + start_offset = offset; + + ret = read_auth_container(spl_image); + + return ret; +} + +int __weak nor_load_image_parse_container(struct spl_image_info *spl_image, + unsigned long offset) +{ + int ret = 0; + + current_dev_type = RAM_DEV; + device = NULL; + + start_offset = offset; + + ret = read_auth_container(spl_image); + + return ret; +} diff --git a/arch/arm/mach-imx/imx8/partition.c b/arch/arm/mach-imx/imx8/partition.c new file mode 100644 index 00000000000..9fe545d570a --- /dev/null +++ b/arch/arm/mach-imx/imx8/partition.c @@ -0,0 +1,387 @@ +/* + * Copyright 2018 NXP. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SC_MAX_PARTS 32 + +struct scu_rm_part_data { + bool used; + bool isolated; + bool restricted; + bool grant; + sc_rm_did_t did; + sc_rm_pt_t self; + sc_rm_pt_t parent; + char *name; +}; + +static struct scu_rm_part_data rm_part_data[SC_MAX_PARTS]; + +static int partition_alloc(bool isolated, bool restricted, bool grant, sc_rm_pt_t *pt) +{ + sc_rm_pt_t parent_part, os_part; + sc_ipc_t ipc_handle; + sc_err_t err; + int i; + + for (i = 0; i < SC_MAX_PARTS; i++) { + if (!rm_part_data[i].used) + break; + } + + if (i == SC_MAX_PARTS) { + puts("No empty slots\n"); + return -EINVAL; + } + + ipc_handle = gd->arch.ipc_channel_handle; + + err = sc_rm_get_partition(ipc_handle, &parent_part); + if (err != SC_ERR_NONE) { + puts("sc_rm_get_partition failure\n"); + return -EINVAL; + } + + debug("isolated %d, restricted %d, grant %d\n", isolated, restricted, grant); + err = sc_rm_partition_alloc(ipc_handle, &os_part, false, isolated, + restricted, grant, false); + if (err != SC_ERR_NONE) { + printf("sc_rm_partition_alloc failure %d\n", err); + return -EINVAL; + } + + err = sc_rm_set_parent(ipc_handle, os_part, parent_part); + if (err != SC_ERR_NONE) { + sc_rm_partition_free(ipc_handle, os_part); + return -EINVAL; + } + + + rm_part_data[i].self = os_part; + rm_part_data[i].parent = parent_part; + rm_part_data[i].used = true; + rm_part_data[i].restricted = restricted; + rm_part_data[i].isolated = isolated; + rm_part_data[i].grant = grant; + + if (pt) + *pt = os_part; + + printf("%s: os_part, %d: parent_part, %d\n", __func__, os_part, + parent_part); + + return 0; +} + +static int do_part_alloc(int argc, char * const argv[]) +{ + bool restricted = false, isolated = false, grant = false; + int ret; + + if (argv[0]) + isolated = simple_strtoul(argv[0], NULL, 10); + if (argv[1]) + restricted = simple_strtoul(argv[1], NULL, 10); + if (argv[2]) + grant = simple_strtoul(argv[2], NULL, 10); + + ret = partition_alloc(isolated, restricted, grant, NULL); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int do_part_dtb(int argc, char * const argv[]) +{ + sc_ipc_t ipc_handle; + sc_err_t err; + sc_rm_pt_t pt; + char *pathp = "/domu"; + int nodeoffset, subnode; + int rsrc_size = 0, pad_size = 0; + int i, ret; + u32 *rsrc_data = NULL, *pad_data = NULL; + const struct fdt_property *prop; + bool init_ignore_domu_power = false; + char *tmp; + void *fdt; + + ipc_handle = gd->arch.ipc_channel_handle; + + tmp = env_get("domu-init-ignore-poweroff"); + if (tmp && !strncmp(tmp, "yes", 3)) { + init_ignore_domu_power = true; + printf("ignore init power off domu power\n"); + } + + if (argc) + fdt = (void *)simple_strtoul(argv[0], NULL, 16); + else + fdt = working_fdt; + printf("fdt addr %p\n", fdt); + nodeoffset = fdt_path_offset(fdt, pathp); + debug("%s %s %p\n", __func__, fdt_get_name(fdt, nodeoffset, NULL), fdt); + fdt_for_each_subnode(subnode, fdt, nodeoffset) { + if (!fdtdec_get_is_enabled(fdt, subnode)) + continue; + if (!fdt_node_check_compatible(fdt, subnode, "xen,domu")) { + u32 temp; + prop = fdt_getprop(fdt, subnode, "rsrcs", &rsrc_size); + if (!prop) + debug("No rsrcs %s\n", fdt_get_name(fdt, subnode, NULL)); + if (rsrc_size > 0) { + rsrc_data = kmalloc(rsrc_size, __GFP_ZERO); + if (!rsrc_data) { + debug("No mem\n"); + return CMD_RET_FAILURE; + } + if (fdtdec_get_int_array(fdt, subnode, "rsrcs", + rsrc_data, rsrc_size >> 2)) { + debug("Error reading rsrcs\n"); + free(rsrc_data); + return CMD_RET_FAILURE; + } + } + + prop = fdt_getprop(fdt, subnode, "pads", &pad_size); + if (!prop) + debug("No pads %s %d\n", fdt_get_name(fdt, subnode, NULL), pad_size); + if (pad_size > 0) { + pad_data = kmalloc(pad_size, __GFP_ZERO); + if (!pad_data) { + debug("No mem\n"); + if (rsrc_data != NULL) + free(rsrc_data); + return CMD_RET_FAILURE; + } + if (fdtdec_get_int_array(fdt, subnode, "pads", + pad_data, pad_size >> 2)) { + debug("Error reading pad\n"); + free(pad_data); + free(rsrc_data); + return CMD_RET_FAILURE; + } + } + + if ((rsrc_size <= 0) && (pad_size <= 0)) + continue; + + ret = partition_alloc(false, false, true, &pt); + if (ret) + goto free_data; + + temp = cpu_to_fdt32(pt); + ret = fdt_setprop(fdt, subnode, "reg", &temp, + sizeof(u32)); + if (ret) { + printf("Could not set reg property %d\n", ret); + sc_rm_partition_free(ipc_handle, pt); + goto free_data; + } + + if (rsrc_size > 0) { + for (i = 0; i < rsrc_size >> 2; i++) { + switch (rsrc_data[i]) { + case SC_R_MU_2A: + case SC_R_MU_3A: + case SC_R_MU_4A: + err = sc_pm_set_resource_power_mode(ipc_handle, rsrc_data[i], SC_PM_PW_MODE_ON); + if (err) + debug("power on resource %d, err %d\n", rsrc_data[i], err); + break; + default: + if (init_ignore_domu_power) + break; + err = sc_pm_set_resource_power_mode(ipc_handle, rsrc_data[i], SC_PM_PW_MODE_OFF); + if (err) + debug("power off resource %d, err %d\n", rsrc_data[i], err); + break; + } + if (sc_rm_is_resource_owned(ipc_handle, rsrc_data[i])) { + err = sc_rm_assign_resource(ipc_handle, pt, rsrc_data[i]); + debug("pt %d, resource %d, err %d\n", pt, rsrc_data[i], err); + } + } + } + + if (pad_size > 0) { + for (i = 0; i < pad_size >> 2; i++) { + if (sc_rm_is_pad_owned(ipc_handle, pad_data[i])) { + err = sc_rm_assign_pad(ipc_handle, pt, pad_data[i]); + debug("pt %d, pad %d, err %d\n", pt, pad_data[i], err); + } + } + } + + free_data: + if (pad_size > 0) + free(pad_data); + if (rsrc_size > 0) { + free(rsrc_data); + rsrc_data = NULL; + } + } + + } + + return 0; +} + +static int do_part_free(int argc, char * const argv[]) +{ + sc_rm_pt_t os_part; + sc_ipc_t ipc_handle; + sc_err_t err; + ipc_handle = gd->arch.ipc_channel_handle; + int i; + + if (argc == 0) + return CMD_RET_FAILURE; + + os_part = simple_strtoul(argv[0], NULL, 10); + + err = sc_rm_partition_free(ipc_handle, os_part); + if (err != SC_ERR_NONE) { + printf("free partiiton %d err %d\n", os_part, err); + return CMD_RET_FAILURE; + } + + for (i = 0; i < SC_MAX_PARTS; i++) { + if ((rm_part_data[i].self == os_part) && rm_part_data[i].used) { + rm_part_data[i].used = false; + break; + } + } + + return CMD_RET_SUCCESS; +} + +static int do_resource_assign(int argc, char * const argv[]) +{ + sc_rm_pt_t os_part; + sc_ipc_t ipc_handle; + sc_err_t err; + sc_rsrc_t resource; + sc_pad_t pad; + int i, flag; + + ipc_handle = gd->arch.ipc_channel_handle; + + if (argc < 3) + return CMD_RET_FAILURE; + + os_part = simple_strtoul(argv[0], NULL, 10); + flag = simple_strtoul(argv[1], NULL, 10); + if (flag) + pad = simple_strtoul(argv[2], NULL, 10); + else + resource = simple_strtoul(argv[2], NULL, 10); + + for (i = 0; i < SC_MAX_PARTS; i++) { + if ((rm_part_data[i].self == os_part) && rm_part_data[i].used) + break; + } + + if (i == SC_MAX_PARTS) { + puts("Not valid partition\n"); + return CMD_RET_FAILURE; + } + + if (flag) + err = sc_rm_assign_pad(ipc_handle, os_part, pad); + else + err = sc_rm_assign_resource(ipc_handle, os_part, resource); + if (err != SC_ERR_NONE) { + printf("assign resource/pad error %d\n", err); + return CMD_RET_FAILURE; + } + + printf("%s: os_part, %d, %d\n", __func__, os_part, + flag ? pad : resource); + + return CMD_RET_SUCCESS; +} + +static int do_part_list(int argc, char * const argv[]) +{ + int i; + + for (i = 0; i < SC_MAX_PARTS; i++) { + if (rm_part_data[i].used) + printf("part id: %d %d\n", rm_part_data[i].self, + rm_part_data[i].parent); + } + + return CMD_RET_SUCCESS; +} + +static int do_part_test(int argc, char * const argv[]) +{ + sc_err_t err; + sc_rsrc_t resource; + + if (argc < 1) + return CMD_RET_FAILURE; + + resource = simple_strtoul(argv[0], NULL, 10); + + err = sc_pm_set_resource_power_mode(gd->arch.ipc_channel_handle, resource, SC_PM_PW_MODE_ON); + if (err == SC_ERR_NOACCESS) + puts("NO ACCESS\n"); + + return CMD_RET_SUCCESS; +} + +static int do_scu_rm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + + if (!strcmp(argv[1], "alloc")) + return do_part_alloc(argc - 2, argv + 2); + else if (!strcmp(argv[1], "dtb")) + return do_part_dtb(argc - 2, argv + 2); + else if (!strcmp(argv[1], "free")) + return do_part_free(argc - 2, argv + 2); + else if (!strcmp(argv[1], "assign")) + return do_resource_assign(argc - 2, argv + 2); + else if (!strcmp(argv[1], "test")) + return do_part_test(argc - 2, argv + 2); + else if (!strcmp(argv[1], "print")) + return do_part_list(argc - 2, argv + 2); + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + scu_rm, CONFIG_SYS_MAXARGS, 1, do_scu_rm, + "scu partition function", + "\n" + "scu_rm alloc [isolated] [restricted] [grant]\n" + "scu_rm dtb [fdt]\n" + "scu_rm free pt\n" + "scu_rm assign pt 0 resource\n" + "scu_rm assign pt 1 pad\n" + "scu_rm test resource\n" + "scu_rm print\n" +); diff --git a/arch/arm/mach-imx/imx8/video_common.c b/arch/arm/mach-imx/imx8/video_common.c new file mode 100644 index 00000000000..01ab94a00eb --- /dev/null +++ b/arch/arm/mach-imx/imx8/video_common.c @@ -0,0 +1,640 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct imxdpuv1_videomode gmode; +static int8_t gdisp, gdc; +static uint32_t gpixfmt; +static GraphicDevice panel; + +static int hdmi_i2c_reg_write(struct udevice *dev, uint addr, uint mask, uint data) +{ + uint8_t valb; + int err; + + if (mask != 0xff) { + err = dm_i2c_read(dev, addr, &valb, 1); + if (err) + return err; + + valb &= ~mask; + valb |= data; + } else { + valb = data; + } + + err = dm_i2c_write(dev, addr, &valb, 1); + return err; +} + +static int hdmi_i2c_reg_read(struct udevice *dev, uint8_t addr, uint8_t *data) +{ + uint8_t valb; + int err; + + err = dm_i2c_read(dev, addr, &valb, 1); + if (err) + return err; + + *data = (int)valb; + return 0; +} + +/* On 8QXP ARM2, the LVDS1 signals are connected to LVDS2HDMI card's LVDS2 channel, + * LVDS0 signals are connected to LVDS2HDMI card's LVDS4 channel. + * There totally 6 channels on the cards, from 0-5. + */ +int lvds2hdmi_setup(int i2c_bus) +{ + struct udevice *bus, *dev; + uint8_t chip = 0x4c; + uint8_t data; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: No bus %d\n", __func__, i2c_bus); + return ret; + } + + ret = dm_i2c_probe(bus, chip, 0, &dev); + if (ret) { + printf("%s: Can't find device id=0x%x, on bus %d\n", + __func__, chip, i2c_bus); + return ret; + } + + /* InitIT626X(): start */ + hdmi_i2c_reg_write(dev, 0x04, 0xff, 0x3d); + hdmi_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0x05, 0xff, 0x40); + hdmi_i2c_reg_write(dev, 0x04, 0xff, 0x15); + hdmi_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0x1d, 0xff, 0x66); + hdmi_i2c_reg_write(dev, 0x1e, 0xff, 0x01); + + hdmi_i2c_reg_write(dev, 0x61, 0xff, 0x30); + hdmi_i2c_reg_read(dev, 0xf3, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0xf3, 0xff, data & ~0x30); + hdmi_i2c_reg_read(dev, 0xf3, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0xf3, 0xff, data | 0x20); + + hdmi_i2c_reg_write(dev, 0x09, 0xff, 0x30); + hdmi_i2c_reg_write(dev, 0x0a, 0xff, 0xf8); + hdmi_i2c_reg_write(dev, 0x0b, 0xff, 0x37); + hdmi_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0xc9, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0xca, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0xcb, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0xcc, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0xcd, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0xce, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0xcf, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0xd0, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0x0f, 0xff, 0x01); + + hdmi_i2c_reg_read(dev, 0x58, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0x58, 0xff, data & ~(3 << 5)); + + hdmi_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0xe1, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0x0c, 0xff, 0xff); + hdmi_i2c_reg_write(dev, 0x0d, 0xff, 0xff); + hdmi_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0x0e, 0xff, (data | 0x3)); + hdmi_i2c_reg_write(dev, 0x0e, 0xff, (data & 0xfe)); + hdmi_i2c_reg_write(dev, 0x0f, 0xff, 0x01); + hdmi_i2c_reg_write(dev, 0x33, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0x34, 0xff, 0x18); + hdmi_i2c_reg_write(dev, 0x35, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0xc4, 0xff, 0xfe); + hdmi_i2c_reg_read(dev, 0xc5, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0xc5, 0xff, data | 0x30); + /* InitIT626X end */ + + hdmi_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0x04, 0xff, 0x3d); + hdmi_i2c_reg_write(dev, 0x04, 0xff, 0x15); + hdmi_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0x1d, 0xff, 0x66); + hdmi_i2c_reg_write(dev, 0x1e, 0xff, 0x01); + + hdmi_i2c_reg_read(dev, 0xc1, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0x61, 0xff, 0x10); + + /* SetupAFE(): */ + hdmi_i2c_reg_write(dev, 0x62, 0xff, 0x88); + hdmi_i2c_reg_write(dev, 0x63, 0xff, 0x10); + hdmi_i2c_reg_write(dev, 0x64, 0xff, 0x84); + /* SetupAFE(): end */ + + hdmi_i2c_reg_read(dev, 0x04, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0x04, 0xff, 0x1d); + + hdmi_i2c_reg_read(dev, 0x04, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0x04, 0xff, 0x15); + + hdmi_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */ + + /* Wait video stable */ + hdmi_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */ + + /* Reset Video */ + hdmi_i2c_reg_read(dev, 0x0d, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0x0d, 0xff, 0x40); + hdmi_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0x0e, 0xff, 0x7d); + hdmi_i2c_reg_write(dev, 0x0e, 0xff, 0x7c); + hdmi_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0x61, 0xff, 0x00); + hdmi_i2c_reg_read(dev, 0x61, &data); /* -> 0x00 */ + hdmi_i2c_reg_read(dev, 0x62, &data); /* -> 0x00 */ + hdmi_i2c_reg_read(dev, 0x63, &data); /* -> 0x00 */ + hdmi_i2c_reg_read(dev, 0x64, &data); /* -> 0x00 */ + hdmi_i2c_reg_read(dev, 0x65, &data); /* -> 0x00 */ + hdmi_i2c_reg_read(dev, 0x66, &data); /* -> 0x00 */ + hdmi_i2c_reg_read(dev, 0x67, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + hdmi_i2c_reg_read(dev, 0xc1, &data); /* -> 0x00 */ + hdmi_i2c_reg_write(dev, 0xc1, 0xff, 0x00); + hdmi_i2c_reg_write(dev, 0xc6, 0xff, 0x03); + /* Clear AV mute */ + + return 0; +} + + +int lvds_soc_setup(int lvds_id, sc_pm_clock_rate_t pixel_clock) +{ + sc_err_t err; + sc_rsrc_t lvds_rsrc, mipi_rsrc; + const char *pd_name; + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + + struct power_domain pd; + int ret; + + if (lvds_id == 0) { + lvds_rsrc = SC_R_LVDS_0; + mipi_rsrc = SC_R_MIPI_0; + pd_name = "lvds0_power_domain"; + } else { + lvds_rsrc = SC_R_LVDS_1; + mipi_rsrc = SC_R_MIPI_1; + pd_name = "lvds1_power_domain"; + } + /* Power up LVDS */ + if (!power_domain_lookup_name(pd_name, &pd)) { + ret = power_domain_on(&pd); + if (ret) { + printf("%s Power up failed! (error = %d)\n", pd_name, ret); + return -EIO; + } + } else { + printf("%s lookup failed!\n", pd_name); + return -EIO; + } + + /* Setup clocks */ + err = sc_pm_set_clock_rate(ipcHndl, lvds_rsrc, SC_PM_CLK_BYPASS, &pixel_clock); + if (err != SC_ERR_NONE) { + printf("LVDS set rate SC_PM_CLK_BYPASS failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_rate(ipcHndl, lvds_rsrc, SC_PM_CLK_PER, &pixel_clock); + if (err != SC_ERR_NONE) { + printf("LVDS set rate SC_PM_CLK_BYPASS failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_rate(ipcHndl, lvds_rsrc, SC_PM_CLK_PHY, &pixel_clock); + if (err != SC_ERR_NONE) { + printf("LVDS set rate SC_PM_CLK_BYPASS failed! (error = %d)\n", err); + return -EIO; + } + + if (is_imx8qxp()) { + /* For QXP, there is only one DC, and two pixel links to each LVDS with a mux provided. + * We connect LVDS0 to pixel link 0, lVDS1 to pixel link 1 from DC + */ + + /* Configure to LVDS mode not MIPI DSI */ + err = sc_misc_set_control(ipcHndl, mipi_rsrc, SC_C_MODE, 1); + if (err != SC_ERR_NONE) { + printf("LVDS sc_misc_set_control SC_C_MODE failed! (error = %d)\n", err); + return -EIO; + } + + /* Configure to LVDS mode with single channel */ + err = sc_misc_set_control(ipcHndl, mipi_rsrc, SC_C_DUAL_MODE, 0); + if (err != SC_ERR_NONE) { + printf("LVDS sc_misc_set_control SC_C_DUAL_MODE failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(ipcHndl, mipi_rsrc, SC_C_PXL_LINK_SEL, lvds_id); + if (err != SC_ERR_NONE) { + printf("LVDS sc_misc_set_control SC_C_PXL_LINK_SEL failed! (error = %d)\n", err); + return -EIO; + } + } + + err = sc_pm_clock_enable(ipcHndl, lvds_rsrc, SC_PM_CLK_BYPASS, true, false); + if (err != SC_ERR_NONE) { + printf("LVDS enable clock SC_PM_CLK_BYPASS failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(ipcHndl, lvds_rsrc, SC_PM_CLK_PER, true, false); + if (err != SC_ERR_NONE) { + printf("LVDS enable clock SC_PM_CLK_PER failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(ipcHndl, lvds_rsrc, SC_PM_CLK_PHY, true, false); + if (err != SC_ERR_NONE) { + printf("LVDS enable clock SC_PM_CLK_PHY failed! (error = %d)\n", err); + return -EIO; + } + + return 0; +} + +void lvds_configure(int lvds_id) +{ + void __iomem *lvds_base; + void __iomem *mipi_base; + uint32_t phy_setting; + uint32_t mode; + + if (lvds_id == 0) { + lvds_base = (void __iomem *)LVDS0_PHYCTRL_BASE; + mipi_base = (void __iomem *)MIPI0_SS_BASE; + } else { + lvds_base = (void __iomem *)LVDS1_PHYCTRL_BASE; + mipi_base = (void __iomem *)MIPI1_SS_BASE; + } + + if (is_imx8qm()) { + mode = + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_MODE, LVDS_CTRL_CH0_MODE__DI0) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_DATA_WIDTH, LVDS_CTRL_CH0_DATA_WIDTH__24BIT) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_BIT_MAP, LVDS_CTRL_CH0_BIT_MAP__JEIDA) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_10BIT_ENABLE, LVDS_CTRL_CH0_10BIT_ENABLE__10BIT) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_DI0_DATA_WIDTH, LVDS_CTRL_DI0_DATA_WIDTH__USE_30BIT); + + writel(mode, lvds_base + LVDS_CTRL); + + phy_setting = + LVDS_PHY_CTRL_RFB_MASK | + LVDS_PHY_CTRL_CH0_EN_MASK | + (0 << LVDS_PHY_CTRL_M_SHIFT) | + (0x04 << LVDS_PHY_CTRL_CCM_SHIFT) | + (0x04 << LVDS_PHY_CTRL_CA_SHIFT); + writel(phy_setting, lvds_base + LVDS_PHY_CTRL); + } else if (is_imx8qxp()) { + mode = + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_MODE, LVDS_CTRL_CH0_MODE__DI0) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_DATA_WIDTH, LVDS_CTRL_CH0_DATA_WIDTH__24BIT) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_BIT_MAP, LVDS_CTRL_CH0_BIT_MAP__JEIDA); + + phy_setting = 0x4 << 5 | 0x4 << 2 | 1 << 1 | 0x1; + writel(phy_setting, lvds_base + 0 /* PHY_CTRL*/); + writel(mode, lvds_base + LVDS_CTRL); + writel(0, lvds_base + MIPIv2_CSR_TX_ULPS); + writel(MIPI_CSR_PXL2DPI_24_BIT, lvds_base + MIPIv2_CSR_PXL2DPI); + + /* Power up PLL in MIPI DSI PHY */ + writel(0, mipi_base + MIPI_DSI_OFFSET + DPHY_PD_PLL); + writel(0, mipi_base + MIPI_DSI_OFFSET + DPHY_PD_TX); + } +} + +int display_controller_setup(sc_pm_clock_rate_t pixel_clock) +{ + sc_err_t err; + sc_rsrc_t dc_rsrc, pll0_rsrc, pll1_rsrc; + sc_pm_clock_rate_t pll_clk; + const char *pll1_pd_name; + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + u32 dc_lpcg; + + int dc_id = gdc; + + struct power_domain pd; + int ret; + + if (dc_id == 0) { + dc_rsrc = SC_R_DC_0; + pll0_rsrc = SC_R_DC_0_PLL_0; + pll1_rsrc = SC_R_DC_0_PLL_1; + pll1_pd_name = "dc0_pll1"; + dc_lpcg = DC_0_LPCG; + } else { + dc_rsrc = SC_R_DC_1; + pll0_rsrc = SC_R_DC_1_PLL_0; + pll1_rsrc = SC_R_DC_1_PLL_1; + pll1_pd_name = "dc1_pll1"; + dc_lpcg = DC_1_LPCG; + } + + if (!power_domain_lookup_name(pll1_pd_name, &pd)) { + ret = power_domain_on(&pd); + if (ret) { + printf("%s Power up failed! (error = %d)\n", pll1_pd_name, ret); + return -EIO; + } + } else { + printf("%s lookup failed!\n", pll1_pd_name); + return -EIO; + } + + /* Setup the pll1/2 and DISP0/1 clock */ + if (pixel_clock >= 40000000) + pll_clk = 1188000000; + else + pll_clk = 675000000; + + err = sc_pm_set_clock_rate(ipcHndl, pll0_rsrc, SC_PM_CLK_PLL, &pll_clk); + if (err != SC_ERR_NONE) { + printf("PLL0 set clock rate failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_rate(ipcHndl, pll1_rsrc, SC_PM_CLK_PLL, &pll_clk); + if (err != SC_ERR_NONE) { + printf("PLL1 set clock rate failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_rate(ipcHndl, dc_rsrc, SC_PM_CLK_MISC0, &pixel_clock); + if (err != SC_ERR_NONE) { + printf("DISP0 set clock rate failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_rate(ipcHndl, dc_rsrc, SC_PM_CLK_MISC1, &pixel_clock); + if (err != SC_ERR_NONE) { + printf("DISP1 set clock rate failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(ipcHndl, pll0_rsrc, SC_PM_CLK_PLL, true, false); + if (err != SC_ERR_NONE) { + printf("PLL0 clock enable failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(ipcHndl, pll1_rsrc, SC_PM_CLK_PLL, true, false); + if (err != SC_ERR_NONE) { + printf("PLL1 clock enable failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(ipcHndl, dc_rsrc, SC_PM_CLK_MISC0, true, false); + if (err != SC_ERR_NONE) { + printf("DISP0 clock enable failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(ipcHndl, dc_rsrc, SC_PM_CLK_MISC1, true, false); + if (err != SC_ERR_NONE) { + printf("DISP1 clock enable failed! (error = %d)\n", err); + return -EIO; + } + + LPCG_AllClockOn(dc_lpcg); + + err = sc_misc_set_control(ipcHndl, dc_rsrc, SC_C_PXL_LINK_MST1_ADDR, 0); + if (err != SC_ERR_NONE) { + printf("DC Set control fSC_C_PXL_LINK_MST1_ADDR ailed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(ipcHndl, dc_rsrc, SC_C_PXL_LINK_MST1_ENB, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_PXL_LINK_MST1_ENB failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(ipcHndl, dc_rsrc, SC_C_PXL_LINK_MST1_VLD, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_PXL_LINK_MST1_VLD failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(ipcHndl, dc_rsrc, SC_C_PXL_LINK_MST2_ADDR, 0); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_PXL_LINK_MST2_ADDR ailed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(ipcHndl, dc_rsrc, SC_C_PXL_LINK_MST2_ENB, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_PXL_LINK_MST2_ENB failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(ipcHndl, dc_rsrc, SC_C_PXL_LINK_MST2_VLD, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_PXL_LINK_MST2_VLD failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(ipcHndl, dc_rsrc, SC_C_SYNC_CTRL0, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_SYNC_CTRL0 failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(ipcHndl, dc_rsrc, SC_C_SYNC_CTRL1, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_SYNC_CTRL1 failed! (error = %d)\n", err); + return -EIO; + } + + return 0; +} + +void *video_hw_init(void) +{ + imxdpuv1_channel_params_t channel; + imxdpuv1_layer_t layer; + void *fb; + + int8_t imxdpuv1_id = gdc; + + if (imxdpuv1_id != 0 || (imxdpuv1_id == 1 && !is_imx8qm())) { + printf("%s(): invalid imxdpuv1_id %d", __func__, imxdpuv1_id); + return NULL; + } + + panel.winSizeX = gmode.hlen; + panel.winSizeY = gmode.vlen; + panel.plnSizeX = gmode.hlen; + panel.plnSizeY = gmode.vlen; + + panel.gdfBytesPP = 4; + panel.gdfIndex = GDF_32BIT_X888RGB; + + panel.memSize = gmode.hlen * gmode.vlen * panel.gdfBytesPP; + + /* Allocate framebuffer */ + fb = memalign(0x1000, + roundup(panel.memSize, 0x1000)); + if (!fb) { + printf("IMXDPUv1: Error allocating framebuffer!\n"); + return NULL; + } + + /* Wipe framebuffer */ + memset(fb, 0, panel.memSize); + + panel.frameAdrs = (ulong)fb; + + imxdpuv1_init(imxdpuv1_id); + imxdpuv1_disp_enable_frame_gen(imxdpuv1_id, 0, IMXDPUV1_FALSE); + imxdpuv1_disp_enable_frame_gen(imxdpuv1_id, 1, IMXDPUV1_FALSE); + + imxdpuv1_disp_setup_frame_gen(imxdpuv1_id, gdisp, + (const struct imxdpuv1_videomode *)&gmode, + 0x3ff, 0, 0, 1, IMXDPUV1_DISABLE); + imxdpuv1_disp_init(imxdpuv1_id, gdisp); + imxdpuv1_disp_setup_constframe(imxdpuv1_id, + gdisp, 0, 0, 0xff, 0); /* blue */ + + if (gdisp == 0) + channel.common.chan = IMXDPUV1_CHAN_VIDEO_0; + else + channel.common.chan = IMXDPUV1_CHAN_VIDEO_1; + channel.common.src_pixel_fmt = gpixfmt; + channel.common.dest_pixel_fmt = gpixfmt; + channel.common.src_width = gmode.hlen; + channel.common.src_height = gmode.vlen; + + channel.common.clip_width = 0; + channel.common.clip_height = 0; + channel.common.clip_top = 0; + channel.common.clip_left = 0; + + channel.common.dest_width = gmode.hlen; + channel.common.dest_height = gmode.vlen; + channel.common.dest_top = 0; + channel.common.dest_left = 0; + channel.common.stride = + gmode.hlen * imxdpuv1_bytes_per_pixel(IMXDPUV1_PIX_FMT_BGRA32); + channel.common.disp_id = gdisp; + channel.common.const_color = 0; + channel.common.use_global_alpha = 0; + channel.common.use_local_alpha = 0; + imxdpuv1_init_channel(imxdpuv1_id, &channel); + + imxdpuv1_init_channel_buffer(imxdpuv1_id, + channel.common.chan, + gmode.hlen * imxdpuv1_bytes_per_pixel(IMXDPUV1_PIX_FMT_RGB32), + IMXDPUV1_ROTATE_NONE, + (dma_addr_t)fb, + 0, + 0); + + layer.enable = IMXDPUV1_TRUE; + layer.secondary = get_channel_blk(channel.common.chan); + + if (gdisp == 0) { + layer.stream = IMXDPUV1_DISPLAY_STREAM_0; + layer.primary = IMXDPUV1_ID_CONSTFRAME0; + } else { + layer.stream = IMXDPUV1_DISPLAY_STREAM_1; + layer.primary = IMXDPUV1_ID_CONSTFRAME1; + } + + imxdpuv1_disp_setup_layer( + imxdpuv1_id, &layer, IMXDPUV1_LAYER_0, 1); + imxdpuv1_disp_set_layer_global_alpha( + imxdpuv1_id, IMXDPUV1_LAYER_0, 0xff); + + imxdpuv1_disp_set_layer_position( + imxdpuv1_id, IMXDPUV1_LAYER_0, 0, 0); + imxdpuv1_disp_set_chan_position( + imxdpuv1_id, channel.common.chan, 0, 0); + + imxdpuv1_disp_enable_frame_gen(imxdpuv1_id, gdisp, IMXDPUV1_ENABLE); + + debug("IMXDPU display start ...\n"); + + return &panel; +} + +void imxdpuv1_fb_disable(void) +{ + /* Disable video only when video init is done */ + if (panel.frameAdrs) + imxdpuv1_disp_enable_frame_gen(gdc, gdisp, IMXDPUV1_DISABLE); +} + +int imxdpuv1_fb_init(struct fb_videomode const *mode, + uint8_t disp, uint32_t pixfmt) +{ + if (disp > 1) { + printf("Invalid disp parameter %d for imxdpuv1_fb_init\n", disp); + return -EINVAL; + } + + memset(&gmode, 0, sizeof(struct imxdpuv1_videomode)); + gmode.pixelclock = PS2KHZ(mode->pixclock) * 1000; + gmode.hlen = mode->xres; + gmode.hbp = mode->left_margin; + gmode.hfp = mode->right_margin; + + gmode.vlen = mode->yres; + gmode.vbp = mode->upper_margin; + gmode.vfp = mode->lower_margin; + + gmode.hsync = mode->hsync_len; + gmode.vsync = mode->vsync_len; + gmode.flags = IMXDPUV1_MODE_FLAGS_HSYNC_POL | IMXDPUV1_MODE_FLAGS_VSYNC_POL | IMXDPUV1_MODE_FLAGS_DE_POL; + + if (is_imx8qm()) { /* QM has two DCs each contains one LVDS as secondary display output */ + gdisp = 1; + gdc = disp; + } else if (is_imx8qxp()) { /* QXP has one DC which contains 2 LVDS/MIPI_DSI combo */ + gdisp = disp; + gdc = 0; + } else { + printf("Unsupported SOC for imxdpuv1_fb_init\n"); + return -EPERM; + } + + gpixfmt = pixfmt; + + debug("imxdpuv1_fb_init, dc=%d, disp=%d\n", gdc, gdisp); + + return 0; +} + diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig new file mode 100644 index 00000000000..09779cda647 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -0,0 +1,81 @@ +if ARCH_IMX8M + +config IMX8M + bool + select HAS_CAAM + select ROM_UNIFIED_SECTIONS + +config IMX8MQ + bool + select IMX8M + +config IMX8MM + bool + select IMX8M + +choice + prompt "NXP i.MX8M board select" + optional + +config TARGET_IMX8MQ_EVK + bool "imx8mq_evk" + select IMX8MQ + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MQ_DDR3L_ARM2 + bool "imx8mq_ddr3l_arm2" + select IMX8MQ + select SUPPORT_SPL + +config TARGET_IMX8MQ_DDR4_ARM2 + bool "imx8mq_ddr4_arm2" + select IMX8MQ + select SUPPORT_SPL + +config TARGET_IMX8MQ_PHANBELL + bool "imx8mq_phanbell" + select IMX8MQ + select SUPPORT_SPL + +config TARGET_IMX8MQ_AIY + bool "imx8mq_aiy" + select IMX8MQ + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MM_DDR4_VAL + bool "imx8mm DDR4 validation board" + select IMX8MM + select SUPPORT_SPL + +config TARGET_IMX8MM_DDR3L_VAL + bool "imx8mm DDR3L validation board" + select IMX8MM + select SUPPORT_SPL + +config TARGET_IMX8MM_EVK + bool "imx8mm LPDDR4 EVK board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MM_DDR4_EVK + bool "imx8mm DDR4 EVK board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_DDR4 + +endchoice + +config SYS_SOC + default "imx8m" + +source "board/freescale/imx8mq_evk/Kconfig" +source "board/freescale/imx8mq_arm2/Kconfig" +source "board/freescale/imx8mq_phanbell/Kconfig" +source "board/freescale/imx8mq_aiy/Kconfig" +source "board/freescale/imx8mm_evk/Kconfig" +source "board/freescale/imx8mm_val/Kconfig" + +endif diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile new file mode 100644 index 00000000000..d68cdde4112 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += lowlevel_init.o +obj-y += soc.o clock_slice.o +obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o +obj-$(CONFIG_IMX8MM) += clock_imx8mm.o +obj-$(CONFIG_VIDEO_IMXDCSS) += video_common.o diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c new file mode 100644 index 00000000000..3635c0fc3a0 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -0,0 +1,981 @@ +/* Copyright 2018 NXP + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SECURE_BOOT +void hab_caam_clock_enable(unsigned char enable) +{ + /* The CAAM clock is always on for iMX8M */ +} +#endif + +#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk(unsigned char enable) +{ + clock_enable(CCGR_OCOTP, !!enable); +} +#endif + +int enable_i2c_clk(unsigned char enable, unsigned i2c_num) +{ + /* 0 - 3 is valid i2c num */ + if (i2c_num > 3) + return -EINVAL; + + clock_enable(CCGR_I2C1 + i2c_num, !!enable); + + return 0; +} + +u32 decode_intpll(enum clk_root_src intpll) +{ + u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask; + u32 main_div, pre_div, post_div, div; + u64 freq; + + switch (intpll) { + case ARM_PLL_CLK: + pll_gnrl_ctl = readl((void __iomem *)ARM_PLL_GNRL_CTL); + pll_div_ctl = readl((void __iomem *)ARM_PLL_DIV_CTL); + break; + case GPU_PLL_CLK: + pll_gnrl_ctl = readl((void __iomem *)GPU_PLL_GNRL_CTL); + pll_div_ctl = readl((void __iomem *)GPU_PLL_DIV_CTL); + break; + case VPU_PLL_CLK: + pll_gnrl_ctl = readl((void __iomem *)VPU_PLL_GNRL_CTL); + pll_div_ctl = readl((void __iomem *)VPU_PLL_DIV_CTL); + break; + case SYSTEM_PLL1_800M_CLK: + case SYSTEM_PLL1_400M_CLK: + case SYSTEM_PLL1_266M_CLK: + case SYSTEM_PLL1_200M_CLK: + case SYSTEM_PLL1_160M_CLK: + case SYSTEM_PLL1_133M_CLK: + case SYSTEM_PLL1_100M_CLK: + case SYSTEM_PLL1_80M_CLK: + case SYSTEM_PLL1_40M_CLK: + pll_gnrl_ctl = readl((void __iomem *)SYS_PLL1_GNRL_CTL); + pll_div_ctl = readl((void __iomem *)SYS_PLL1_DIV_CTL); + break; + case SYSTEM_PLL2_1000M_CLK: + case SYSTEM_PLL2_500M_CLK: + case SYSTEM_PLL2_333M_CLK: + case SYSTEM_PLL2_250M_CLK: + case SYSTEM_PLL2_200M_CLK: + case SYSTEM_PLL2_166M_CLK: + case SYSTEM_PLL2_125M_CLK: + case SYSTEM_PLL2_100M_CLK: + case SYSTEM_PLL2_50M_CLK: + pll_gnrl_ctl = readl((void __iomem *)SYS_PLL2_GNRL_CTL); + pll_div_ctl = readl((void __iomem *)SYS_PLL2_DIV_CTL); + break; + case SYSTEM_PLL3_CLK: + pll_gnrl_ctl = readl((void __iomem *)SYS_PLL3_GNRL_CTL); + pll_div_ctl = readl((void __iomem *)SYS_PLL3_DIV_CTL); + break; + default: + return -EINVAL; + } + + /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */ + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0) + return 0; + + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0) + return 0; + + /* + * When BYPASS is equal to 1, PLL enters the bypass mode + * regardless of the values of RESETB + */ + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) + return 24000000u; + + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { + puts("pll not locked\n"); + return 0; + } + + switch (intpll) { + case ARM_PLL_CLK: + case GPU_PLL_CLK: + case VPU_PLL_CLK: + case SYSTEM_PLL3_CLK: + case SYSTEM_PLL1_800M_CLK: + case SYSTEM_PLL2_1000M_CLK: + pll_clke_mask = INTPLL_CLKE_MASK; + div = 1; + break; + + case SYSTEM_PLL1_400M_CLK: + case SYSTEM_PLL2_500M_CLK: + pll_clke_mask = INTPLL_DIV2_CLKE_MASK; + div = 2; + break; + + case SYSTEM_PLL1_266M_CLK: + case SYSTEM_PLL2_333M_CLK: + pll_clke_mask = INTPLL_DIV3_CLKE_MASK; + div = 3; + break; + + case SYSTEM_PLL1_200M_CLK: + case SYSTEM_PLL2_250M_CLK: + pll_clke_mask = INTPLL_DIV4_CLKE_MASK; + div = 4; + break; + + case SYSTEM_PLL1_160M_CLK: + case SYSTEM_PLL2_200M_CLK: + pll_clke_mask = INTPLL_DIV5_CLKE_MASK; + div = 5; + break; + + case SYSTEM_PLL1_133M_CLK: + case SYSTEM_PLL2_166M_CLK: + pll_clke_mask = INTPLL_DIV6_CLKE_MASK; + div = 6; + break; + + case SYSTEM_PLL1_100M_CLK: + case SYSTEM_PLL2_125M_CLK: + pll_clke_mask = INTPLL_DIV8_CLKE_MASK; + div = 8; + break; + + case SYSTEM_PLL1_80M_CLK: + case SYSTEM_PLL2_100M_CLK: + pll_clke_mask = INTPLL_DIV10_CLKE_MASK; + div = 10; + break; + + case SYSTEM_PLL1_40M_CLK: + case SYSTEM_PLL2_50M_CLK: + pll_clke_mask = INTPLL_DIV20_CLKE_MASK; + div = 20; + break; + default: + return -EINVAL; + } + + if ((pll_gnrl_ctl & pll_clke_mask) == 0) + return 0; + + main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >> + INTPLL_MAIN_DIV_SHIFT; + pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >> + INTPLL_PRE_DIV_SHIFT; + post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >> + INTPLL_POST_DIV_SHIFT; + + /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */ + freq = 24000000ULL * main_div; + return lldiv(freq, pre_div * (1 << post_div) * div); +} + +u32 decode_fracpll(enum clk_root_src frac_pll) +{ + u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1; + u32 main_div, pre_div, post_div, k; + + switch (frac_pll) { + case DRAM_PLL1_CLK: + pll_gnrl_ctl = readl((void __iomem *)DRAM_PLL_GNRL_CTL); + pll_fdiv_ctl0 = readl((void __iomem *)DRAM_PLL_FDIV_CTL0); + pll_fdiv_ctl1 = readl((void __iomem *)DRAM_PLL_FDIV_CTL1); + break; + case AUDIO_PLL1_CLK: + pll_gnrl_ctl = readl((void __iomem *)AUDIO_PLL1_GNRL_CTL); + pll_fdiv_ctl0 = readl((void __iomem *)AUDIO_PLL1_FDIV_CTL0); + pll_fdiv_ctl1 = readl((void __iomem *)AUDIO_PLL1_FDIV_CTL1); + break; + case AUDIO_PLL2_CLK: + pll_gnrl_ctl = readl((void __iomem *)AUDIO_PLL2_GNRL_CTL); + pll_fdiv_ctl0 = readl((void __iomem *)AUDIO_PLL2_FDIV_CTL0); + pll_fdiv_ctl1 = readl((void __iomem *)AUDIO_PLL2_FDIV_CTL1); + break; + case VIDEO_PLL_CLK: + pll_gnrl_ctl = readl((void __iomem *)VIDEO_PLL1_GNRL_CTL); + pll_fdiv_ctl0 = readl((void __iomem *)VIDEO_PLL1_FDIV_CTL0); + pll_fdiv_ctl1 = readl((void __iomem *)VIDEO_PLL1_FDIV_CTL1); + break; + default: + printf("Not supported\n"); + return 0; + } + + /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */ + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0) + return 0; + + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0) + return 0; + /* + * When BYPASS is equal to 1, PLL enters the bypass mode + * regardless of the values of RESETB + */ + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) + return 24000000u; + + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { + puts("pll not locked\n"); + return 0; + } + + if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK)) + return 0; + + main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >> + INTPLL_MAIN_DIV_SHIFT; + pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >> + INTPLL_PRE_DIV_SHIFT; + post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >> + INTPLL_POST_DIV_SHIFT; + + k = pll_fdiv_ctl1 & GENMASK(15, 0); + + /* FFOUT = ((m + k / 65536) * FFIN) / (p * 2^s), 1 ≤ p ≤ 63, 64 ≤ m ≤ 1023, 0 ≤ s ≤ 6 */ + return lldiv((main_div * 65536 + k) * 24000000ULL, 65536 * pre_div * (1 << post_div)); +} + +enum intpll_out_freq { + INTPLL_OUT_750M, + INTPLL_OUT_800M, + INTPLL_OUT_1200M, + INTPLL_OUT_1000M, + INTPLL_OUT_2000M, +}; + +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .kdiv = (_k), \ + } + +#define LOCK_STATUS BIT(31) +#define LOCK_SEL_MASK BIT(29) +#define CLKE_MASK BIT(11) +#define RST_MASK BIT(9) +#define BYPASS_MASK BIT(4) +#define MDIV_SHIFT 12 +#define MDIV_MASK GENMASK(21, 12) +#define PDIV_SHIFT 4 +#define PDIV_MASK GENMASK(9, 4) +#define SDIV_SHIFT 0 +#define SDIV_MASK GENMASK(2, 0) +#define KDIV_SHIFT 0 +#define KDIV_MASK GENMASK(15, 0) + +struct imx_int_pll_rate_table { + u32 rate; + int mdiv; + int pdiv; + int sdiv; + int kdiv; +}; + +static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { + PLL_1443X_RATE(800000000U, 200, 3, 1, 0), + PLL_1443X_RATE(750000000U, 250, 2, 2, 0), + PLL_1443X_RATE(650000000U, 325, 3, 2, 0), + PLL_1443X_RATE(600000000U, 300, 3, 2, 0), + PLL_1443X_RATE(594000000U, 99, 1, 2, 0), + PLL_1443X_RATE(400000000U, 400, 3, 3, 0), + PLL_1443X_RATE(266000000U, 266, 3, 3, 0), + PLL_1443X_RATE(167000000U, 334, 3, 4, 0), + PLL_1443X_RATE(100000000U, 200, 3, 4, 0), +}; + +#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ + { \ + .clk = (_rate), \ + .alt_root_sel = (_m), \ + .alt_pre_div = (_p), \ + .apb_root_sel = (_s), \ + .apb_pre_div = (_k), \ + } + +struct dram_bypass_clk_setting { + enum dram_bypassclk_val clk; + int alt_root_sel; + enum root_pre_div alt_pre_div; + int apb_root_sel; + enum root_pre_div apb_pre_div; +}; + +static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = { + DRAM_BYPASS_ROOT_CONFIG(DRAM_BYPASSCLK_100M, 2, CLK_ROOT_PRE_DIV1, 2, CLK_ROOT_PRE_DIV2), + DRAM_BYPASS_ROOT_CONFIG(DRAM_BYPASSCLK_250M, 3, CLK_ROOT_PRE_DIV2, 2, CLK_ROOT_PRE_DIV2), + DRAM_BYPASS_ROOT_CONFIG(DRAM_BYPASSCLK_400M, 1, CLK_ROOT_PRE_DIV2, 3, CLK_ROOT_PRE_DIV2), +}; + +int fracpll_configure(enum pll_clocks pll, u32 freq) +{ + int i; + u32 tmp, div_val; + void *pll_base; + struct imx_int_pll_rate_table *rate; + + for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) { + if (freq == imx8mm_fracpll_tbl[i].rate) + break; + } + + if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) { + printf("No matched freq table %u\n", freq); + return -EINVAL; + } + + rate = &imx8mm_fracpll_tbl[i]; + + switch (pll) { + case ANATOP_DRAM_PLL: + #define SRC_DDR1_ENABLE_MASK (0x8F000000UL) + setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); + setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); + writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); + + pll_base = (void __iomem *)DRAM_PLL_GNRL_CTL; + break; + case ANATOP_VIDEO_PLL: + pll_base = (void __iomem *)VIDEO_PLL1_GNRL_CTL; + break; + default: + return 0; + } + /* Bypass clock and set lock to pll output lock */ + tmp = readl(pll_base); + tmp |= BYPASS_MASK; + writel(tmp, pll_base); + + /* Enable RST */ + tmp &= ~RST_MASK; + writel(tmp, pll_base); + + div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | + (rate->sdiv << SDIV_SHIFT); + writel(div_val, pll_base + 4); + writel(rate->kdiv << KDIV_SHIFT, pll_base + 8); + + __udelay(100); + + /* Disable RST */ + tmp |= RST_MASK; + writel(tmp, pll_base); + + /* Wait Lock*/ + while (!(readl(pll_base) & LOCK_STATUS)) + ; + + /* Bypass */ + tmp &= ~BYPASS_MASK; + writel(tmp, pll_base); + + return 0; +} + +void dram_pll_init(enum dram_pll_out_val pll_val) +{ + u32 freq; + + switch (pll_val) { + case DRAM_PLL_OUT_100M: + freq = 100000000UL; + break; + case DRAM_PLL_OUT_167M: + freq = 167000000UL; + break; + case DRAM_PLL_OUT_266M: + freq = 266000000UL; + break; + case DRAM_PLL_OUT_667M: + freq = 667000000UL; + break; + case DRAM_PLL_OUT_400M: + freq = 400000000UL; + break; + case DRAM_PLL_OUT_600M: + freq = 600000000UL; + break; + case DRAM_PLL_OUT_750M: + freq = 750000000UL; + break; + case DRAM_PLL_OUT_800M: + freq = 800000000UL; + break; + default: + return; + } + + fracpll_configure(ANATOP_DRAM_PLL, freq); +} + +void dram_enable_bypass(enum dram_bypassclk_val clk_val) +{ + int i; + struct dram_bypass_clk_setting *config; + + for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) { + if (clk_val == imx8mm_dram_bypass_tbl[i].clk) + break; + } + + if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) { + printf("No matched freq table %u\n", clk_val); + return; + } + + config = &imx8mm_dram_bypass_tbl[i]; + + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(config->alt_root_sel) | CLK_ROOT_PRE_DIV(config->alt_pre_div)); + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(config->apb_root_sel) | CLK_ROOT_PRE_DIV(config->apb_pre_div)); + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); +} + +void dram_disable_bypass(void) +{ + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); +} + +int intpll_configure(enum pll_clocks pll, enum intpll_out_freq freq) +{ + void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl; + u32 pll_div_ctl_val, pll_clke_masks; + + switch (pll) { + case ANATOP_SYSTEM_PLL1: + pll_gnrl_ctl = (void __iomem *)SYS_PLL1_GNRL_CTL; + pll_div_ctl = (void __iomem *)SYS_PLL1_DIV_CTL; + pll_clke_masks = INTPLL_DIV20_CLKE_MASK | + INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK | + INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK | + INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK | + INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK; + break; + case ANATOP_SYSTEM_PLL2: + pll_gnrl_ctl = (void __iomem *)SYS_PLL2_GNRL_CTL; + pll_div_ctl = (void __iomem *)SYS_PLL2_DIV_CTL; + pll_clke_masks = INTPLL_DIV20_CLKE_MASK | + INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK | + INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK | + INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK | + INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK; + break; + case ANATOP_SYSTEM_PLL3: + pll_gnrl_ctl = (void __iomem *)SYS_PLL3_GNRL_CTL; + pll_div_ctl = (void __iomem *)SYS_PLL3_DIV_CTL; + pll_clke_masks = INTPLL_CLKE_MASK; + break; + case ANATOP_ARM_PLL: + pll_gnrl_ctl = (void __iomem *)ARM_PLL_GNRL_CTL; + pll_div_ctl = (void __iomem *)ARM_PLL_DIV_CTL; + pll_clke_masks = INTPLL_CLKE_MASK; + break; + case ANATOP_GPU_PLL: + pll_gnrl_ctl = (void __iomem *)GPU_PLL_GNRL_CTL; + pll_div_ctl = (void __iomem *)GPU_PLL_DIV_CTL; + pll_clke_masks = INTPLL_CLKE_MASK; + break; + case ANATOP_VPU_PLL: + pll_gnrl_ctl = (void __iomem *)VPU_PLL_GNRL_CTL; + pll_div_ctl = (void __iomem *)VPU_PLL_DIV_CTL; + pll_clke_masks = INTPLL_CLKE_MASK; + break; + default: + return -EINVAL; + }; + + switch (freq) { + case INTPLL_OUT_750M: + /* 24 * 0xfa / 2 / 2 ^ 2 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) | + INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(2); + break; + case INTPLL_OUT_800M: + /* 24 * 0x190 / 3 / 2 ^ 2 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) | + INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2); + break; + case INTPLL_OUT_1000M: + /* 24 * 0xfa / 3 / 2 ^ 1 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) | + INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1); + break; + case INTPLL_OUT_1200M: + /* 24 * 0xc8 / 2 / 2 ^ 1 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) | + INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(1); + break; + case INTPLL_OUT_2000M: + /* 24 * 0xfa / 3 / 2 ^ 0 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) | + INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0); + break; + default: + return -EINVAL; + }; + /* Bypass clock and set lock to pll output lock */ + setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK | INTPLL_LOCK_SEL_MASK); + /* Enable reset */ + clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK); + /* Configure */ + writel(pll_div_ctl_val, pll_div_ctl); + + __udelay(100); + + /* Disable reset */ + setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK); + /* Wait Lock */ + while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK)) + ; + /* Clear bypass */ + clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK); + setbits_le32(pll_gnrl_ctl, pll_clke_masks); + + return 0; +} + +#define VIDEO_PLL_RATE 594000000U + +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) +{ + uint32_t div, pre, post; + + div = VIDEO_PLL_RATE / 1000; + div = (div + freq - 1) / freq; + + if (div < 1) + div = 1; + + for (pre = 1; pre <= 8; pre++) { + for (post = 1; post <= 64; post++) { + if (pre * post == div) { + goto find; + } + } + } + + printf("Fail to set rate to %dkhz", freq); + return; + +find: + /* Select to video PLL */ + debug("mxs_set_lcdclk, pre = %d, post = %d\n", pre, post); + clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(pre - 1) | CLK_ROOT_POST_DIV(post - 1)); + +} + +void enable_display_clk(unsigned char enable) +{ + if (enable) { + clock_enable(CCGR_DISPMIX, false); + + /* Set Video PLL to 594Mhz, p = 1, m = 99, k = 0, s = 2 */ + fracpll_configure(ANATOP_VIDEO_PLL, VIDEO_PLL_RATE); + + /* 500Mhz */ + clock_set_target_val(DISPLAY_AXI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2)); + + /* 200Mhz */ + clock_set_target_val(DISPLAY_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + clock_set_target_val(MIPI_DSI_CORE_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + + /* 27Mhz MIPI DPHY PLL ref from video PLL */ + clock_set_target_val(MIPI_DSI_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV22)); + + clock_enable(CCGR_DISPMIX, true); + } else { + clock_enable(CCGR_DISPMIX, false); + } +} + +int clock_init() +{ + uint32_t val_cfg0; + + /* + * According to ANAMIX SPEC + * sys pll1 fixed at 800MHz + * sys pll2 fixed at 1GHz + * Here we only enable the outputs. + */ + val_cfg0 = readl(SYS_PLL1_GNRL_CTL); + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK | + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK | + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK | + INTPLL_DIV20_CLKE_MASK; + writel(val_cfg0, SYS_PLL1_GNRL_CTL); + + val_cfg0 = readl(SYS_PLL2_GNRL_CTL); + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK | + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK | + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK | + INTPLL_DIV20_CLKE_MASK; + writel(val_cfg0, SYS_PLL2_GNRL_CTL); + + /* Configure ARM at 1.2GHz */ + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \ + CLK_ROOT_SOURCE_SEL(2)); + + intpll_configure(ANATOP_ARM_PLL, INTPLL_OUT_1200M); + + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \ + CLK_ROOT_SOURCE_SEL(1) | \ + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1)); + + intpll_configure(ANATOP_SYSTEM_PLL3, INTPLL_OUT_750M); + clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2)); + + /* config GIC to sys_pll2_100m */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3)); + clock_enable(CCGR_GIC, 1); + + /* + * set uart clock root + * 24M OSC + */ + clock_enable(CCGR_UART1, 0); + clock_enable(CCGR_UART2, 0); + clock_enable(CCGR_UART3, 0); + clock_enable(CCGR_UART4, 0); + clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_UART1, 1); + clock_enable(CCGR_UART2, 1); + clock_enable(CCGR_UART3, 1); + clock_enable(CCGR_UART4, 1); + + /* + * set usdhc clock root + * sys pll1 400M + */ + clock_enable(CCGR_USDHC1, 0); + clock_enable(CCGR_USDHC2, 0); + clock_enable(CCGR_USDHC3, 0); + clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + clock_enable(CCGR_USDHC1, 1); + clock_enable(CCGR_USDHC2, 1); + clock_enable(CCGR_USDHC3, 1); + + clock_enable(CCGR_DDR1, 0); + clock_set_target_val(DRAM_ALT_CLK_ROOT,CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + clock_set_target_val(DRAM_APB_CLK_ROOT,CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + clock_enable(CCGR_DDR1, 1); + + /* + * set rawnand root + * sys pll1 400M + */ + clock_enable(CCGR_RAWNAND, 0); + clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */ + clock_enable(CCGR_RAWNAND, 1); + + clock_enable(CCGR_WDOG1, 0); + clock_enable(CCGR_WDOG2, 0); + clock_enable(CCGR_WDOG3, 0); + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_WDOG1, 1); + clock_enable(CCGR_WDOG2, 1); + clock_enable(CCGR_WDOG3, 1); + + clock_enable(CCGR_TEMP_SENSOR, 1); + + clock_enable(CCGR_ECSPI1, 0); + clock_enable(CCGR_ECSPI2, 0); + clock_enable(CCGR_ECSPI3, 0); + clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_ECSPI1, 1); + clock_enable(CCGR_ECSPI2, 1); + clock_enable(CCGR_ECSPI3, 1); + + clock_enable(CCGR_SEC_DEBUG, 1); + + enable_display_clk(1); + return 0; +}; + +int set_clk_qspi(void) +{ + /* + * set qspi root + * sys pll1 100M + */ + clock_enable(CCGR_QSPI, 0); + clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(7)); + clock_enable(CCGR_QSPI, 1); + + return 0; +} + +#ifdef CONFIG_FEC_MXC +int set_clk_enet(enum enet_freq type) +{ + u32 target; + u32 enet1_ref; + + /* disable the clock first */ + clock_enable(CCGR_ENET1, 0); + clock_enable(CCGR_SIM_ENET, 0); + + switch (type) { + case ENET_125MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; + break; + case ENET_50MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; + break; + case ENET_25MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; + break; + default: + return -EINVAL; + } + + /* set enet axi clock 266Mhz */ + target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_AXI_CLK_ROOT, target); + + target = CLK_ROOT_ON | enet1_ref | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_REF_CLK_ROOT, target); + + target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ENET_TIMER_CLK_ROOT, target); + +#ifdef CONFIG_FEC_MXC_25M_REF_CLK + target = CLK_ROOT_ON | + ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target); +#endif + /* enable clock */ + clock_enable(CCGR_SIM_ENET, 1); + clock_enable(CCGR_ENET1, 1); + + return 0; +} +#endif + +u32 get_root_src_clk(enum clk_root_src root_src) +{ + switch (root_src) { + case OSC_24M_CLK: + return 24000000u; + case OSC_HDMI_CLK: + return 26000000u; + case OSC_32K_CLK: + return 32000u; + case ARM_PLL_CLK: + case GPU_PLL_CLK: + case VPU_PLL_CLK: + case SYSTEM_PLL1_800M_CLK: + case SYSTEM_PLL1_400M_CLK: + case SYSTEM_PLL1_266M_CLK: + case SYSTEM_PLL1_200M_CLK: + case SYSTEM_PLL1_160M_CLK: + case SYSTEM_PLL1_133M_CLK: + case SYSTEM_PLL1_100M_CLK: + case SYSTEM_PLL1_80M_CLK: + case SYSTEM_PLL1_40M_CLK: + case SYSTEM_PLL2_1000M_CLK: + case SYSTEM_PLL2_500M_CLK: + case SYSTEM_PLL2_333M_CLK: + case SYSTEM_PLL2_250M_CLK: + case SYSTEM_PLL2_200M_CLK: + case SYSTEM_PLL2_166M_CLK: + case SYSTEM_PLL2_125M_CLK: + case SYSTEM_PLL2_100M_CLK: + case SYSTEM_PLL2_50M_CLK: + case SYSTEM_PLL3_CLK: + return decode_intpll(root_src); + case DRAM_PLL1_CLK: + case AUDIO_PLL1_CLK: + case AUDIO_PLL2_CLK: + case VIDEO_PLL_CLK: + return decode_fracpll(root_src); + default: + return 0; + } + + return 0; +} + +u32 get_root_clk(enum clk_root_index clock_id) +{ + enum clk_root_src root_src; + u32 post_podf, pre_podf, root_src_clk; + + if (clock_root_enabled(clock_id) <= 0) + return 0; + + if (clock_get_prediv(clock_id, &pre_podf) < 0) + return 0; + + if (clock_get_postdiv(clock_id, &post_podf) < 0) + return 0; + + if (clock_get_src(clock_id, &root_src) < 0) + return 0; + + root_src_clk = get_root_src_clk(root_src); + + return root_src_clk / (post_podf + 1) / (pre_podf + 1); +} + +u32 mxc_get_clock(enum mxc_clock clk) +{ + u32 val; + + switch (clk) { + case MXC_ARM_CLK: + return get_root_clk(ARM_A53_CLK_ROOT); + case MXC_IPG_CLK: + clock_get_target_val(IPG_CLK_ROOT, &val); + val = val & 0x3; + return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1); + case MXC_CSPI_CLK: + return get_root_clk(ECSPI1_CLK_ROOT); + case MXC_ESDHC_CLK: + return get_root_clk(USDHC1_CLK_ROOT); + case MXC_ESDHC2_CLK: + return get_root_clk(USDHC2_CLK_ROOT); + case MXC_ESDHC3_CLK: + return get_root_clk(USDHC3_CLK_ROOT); + case MXC_I2C_CLK: + return get_root_clk(I2C1_CLK_ROOT); + case MXC_UART_CLK: + return get_root_clk(UART1_CLK_ROOT); + case MXC_QSPI_CLK: + return get_root_clk(QSPI_CLK_ROOT); + default: + printf("Unsupported mxc_clock %d\n", clk); + break; + } + + return 0; +} + +u32 imx_get_uartclk(void) +{ + return mxc_get_clock(MXC_UART_CLK); +} + +u32 imx_get_fecclk(void) +{ + return get_root_clk(ENET_AXI_CLK_ROOT); +} + +void enable_usboh3_clk(unsigned char enable) +{ + if (enable) { + clock_enable(CCGR_USB_MSCALE_PL301, 0); + /* 500M */ + clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + /* 100M */ + clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + /* 100M */ + clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + clock_enable(CCGR_USB_MSCALE_PL301, 1); + } else { + clock_enable(CCGR_USB_MSCALE_PL301, 0); + } +} + +/* + * Dump some clockes. + */ +#ifndef CONFIG_SPL_BUILD +int do_mscale_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 freq; + + freq = decode_intpll(ARM_PLL_CLK); + printf("ARM_PLL %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_800M_CLK); + printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_400M_CLK); + printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_266M_CLK); + printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_160M_CLK); + printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_133M_CLK); + printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_100M_CLK); + printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_80M_CLK); + printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_40M_CLK); + printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_1000M_CLK); + printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_500M_CLK); + printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_333M_CLK); + printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_250M_CLK); + printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_200M_CLK); + printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_166M_CLK); + printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_125M_CLK); + printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_100M_CLK); + printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_50M_CLK); + printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL3_CLK); + printf("SYS_PLL3 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_UART_CLK); + printf("UART1 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_ESDHC_CLK); + printf("USDHC1 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_QSPI_CLK); + printf("QSPI %8d MHz\n", freq / 1000000); + + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_mscale_showclocks, + "display clocks", + "" +); +#endif diff --git a/arch/arm/mach-imx/mx8m/clock.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c similarity index 82% rename from arch/arm/mach-imx/mx8m/clock.c rename to arch/arm/mach-imx/imx8m/clock_imx8mq.c index c56ba99d5c6..33a4d51f9cb 100644 --- a/arch/arm/mach-imx/mx8m/clock.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -307,6 +307,13 @@ static u32 get_root_clk(enum clk_root_index clock_id) return root_src_clk / (post_podf + 1) / (pre_podf + 1); } +#ifdef CONFIG_SECURE_BOOT +void hab_caam_clock_enable(unsigned char enable) +{ + /* The CAAM clock is always on for iMX8M */ +} +#endif + #ifdef CONFIG_MXC_OCOTP void enable_ocotp_clk(unsigned char enable) { @@ -399,6 +406,18 @@ void init_usb_clk(void) } } +void init_nand_clk(void) +{ + /* + * set rawnand root + * sys pll1 400M + */ + clock_enable(CCGR_RAWNAND, 0); + clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */ + clock_enable(CCGR_RAWNAND, 1); +} + void init_uart_clk(u32 index) { /* Set uart clock root 25M OSC */ @@ -528,41 +547,125 @@ u32 imx_get_fecclk(void) return get_root_clk(ENET_AXI_CLK_ROOT); } -#ifdef CONFIG_SPL_BUILD -void dram_pll_init(void) +#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ + { \ + .clk = (_rate), \ + .alt_root_sel = (_m), \ + .alt_pre_div = (_p), \ + .apb_root_sel = (_s), \ + .apb_pre_div = (_k), \ + } + +struct dram_bypass_clk_setting { + enum dram_bypassclk_val clk; + int alt_root_sel; + enum root_pre_div alt_pre_div; + int apb_root_sel; + enum root_pre_div apb_pre_div; +}; + +static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = { + DRAM_BYPASS_ROOT_CONFIG(DRAM_BYPASSCLK_100M, 2, CLK_ROOT_PRE_DIV1, 2, CLK_ROOT_PRE_DIV2), + DRAM_BYPASS_ROOT_CONFIG(DRAM_BYPASSCLK_250M, 3, CLK_ROOT_PRE_DIV2, 2, CLK_ROOT_PRE_DIV2), + DRAM_BYPASS_ROOT_CONFIG(DRAM_BYPASSCLK_400M, 1, CLK_ROOT_PRE_DIV2, 3, CLK_ROOT_PRE_DIV2), +}; + +void dram_enable_bypass(enum dram_bypassclk_val clk_val) { - struct src *src = (struct src *)SRC_BASE_ADDR; - void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; - u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0; - u32 val; - int ret; + int i; + struct dram_bypass_clk_setting *config; - setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7)); - setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5)); + for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) { + if (clk_val == imx8mm_dram_bypass_tbl[i].clk) + break; + } - pwdn_mask = SSCG_PLL_PD_MASK; - pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK; - bypass1 = SSCG_PLL_BYPASS1_MASK; - bypass2 = SSCG_PLL_BYPASS2_MASK; + if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) { + printf("No matched freq table %u\n", clk_val); + return; + } - /* Enable DDR1 and DDR2 domain */ - writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr); - writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr); + config = &imx8mm_dram_bypass_tbl[i]; + + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(config->alt_root_sel) | CLK_ROOT_PRE_DIV(config->alt_pre_div)); + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(config->apb_root_sel) | CLK_ROOT_PRE_DIV(config->apb_pre_div)); + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); +} + +void dram_disable_bypass(void) +{ + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); +} + +#ifdef CONFIG_SPL_BUILD +void dram_pll_init(enum dram_pll_out_val pll_val) +{ + u32 val; + void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; + void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2; + + /* Bypass */ + setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); + setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); + + switch (pll_val) { + case DRAM_PLL_OUT_800M: + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(0); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); + val |= SSCG_PLL_REF_DIVR2_VAL(29); + writel(val, pll_cfg_reg2); + break; + case DRAM_PLL_OUT_600M: + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(1); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); + val |= SSCG_PLL_REF_DIVR2_VAL(29); + writel(val, pll_cfg_reg2); + break; + case DRAM_PLL_OUT_400M: + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(1); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); + val |= SSCG_PLL_REF_DIVR2_VAL(29); + writel(val, pll_cfg_reg2); + break; + case DRAM_PLL_OUT_167M: + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(3); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45); + val |= SSCG_PLL_REF_DIVR2_VAL(30); + writel(val, pll_cfg_reg2); + break; + default: + break; + } /* Clear power down bit */ - clrbits_le32(pll_control_reg, pwdn_mask); + clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK); /* Eanble ARM_PLL/SYS_PLL */ - setbits_le32(pll_control_reg, pll_clke); + setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK); /* Clear bypass */ - clrbits_le32(pll_control_reg, bypass1); + clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); __udelay(100); - clrbits_le32(pll_control_reg, bypass2); + clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); /* Wait lock */ - ret = readl_poll_timeout(pll_control_reg, val, - val & SSCG_PLL_LOCK_MASK, 1); - if (ret) - printf("%s timeout\n", __func__); + while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK)) + ; } int frac_pll_init(u32 pll, enum frac_pll_out_val val) @@ -724,6 +827,12 @@ int clock_init(void) init_wdog_clk(); clock_enable(CCGR_TSENSOR, 1); + clock_enable(CCGR_OCOTP, 1); + + /* config GIC to sys_pll2_200m */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + clock_enable(CCGR_GIC, 1); return 0; } diff --git a/arch/arm/mach-imx/mx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c similarity index 57% rename from arch/arm/mach-imx/mx8m/clock_slice.c rename to arch/arm/mach-imx/imx8m/clock_slice.c index e734498b947..09900bcde57 100644 --- a/arch/arm/mach-imx/mx8m/clock_slice.c +++ b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -16,6 +16,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR; +#ifdef CONFIG_IMX8MQ static struct clk_root_map root_array[] = { {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0, {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK, @@ -477,6 +478,466 @@ static struct clk_root_map root_array[] = { {DRAM_PLL1_CLK} }, }; +#else +static struct clk_root_map root_array[] = { + {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0, + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK} + }, + {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, + {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2, + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK} + }, + {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3, + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4, + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK} + }, + {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, + {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK} + }, + {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK} + }, + {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4, + {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK, + EXT_CLK_1, EXT_CLK_4} + }, + {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK, + EXT_CLK_1, EXT_CLK_3} + }, + {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + EXT_CLK_2, EXT_CLK_3} + }, + {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7, + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK} + }, + {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2, + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK} + }, + {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3, + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK} + }, + {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4, + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK} + }, + {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5, + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK} + }, + {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6, + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK} + }, + {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, + SYSTEM_PLL1_400M_CLK} + }, + {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK} + }, + {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9, + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4} + }, + {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10, + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4} + }, + {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2} + }, + {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2} + }, + {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4} + }, + {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, + VIDEO_PLL_CLK} + }, + {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21, + {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22, + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK} + }, + {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK, + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK} + }, + {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34, + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35, + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1} + }, + {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2} + }, + {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3} + }, + {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1} + }, + {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2} + }, + {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3} + }, + {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK, + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3} + }, + {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK, + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK} + }, + {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51, + {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK} + }, + {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK, + SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK} + }, + {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK} + }, + {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64, + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK} + }, + {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, + EXT_CLK_4, SYSTEM_PLL1_400M_CLK} + }, + {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK} + }, + {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}, + }, + {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69, + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK} + }, + {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0, + {DRAM_PLL1_CLK} + }, + {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0, + {DRAM_PLL1_CLK} + }, +}; +#endif static int select(enum clk_root_index clock_id) { diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S b/arch/arm/mach-imx/imx8m/lowlevel_init.S similarity index 100% rename from arch/arm/mach-imx/mx8m/lowlevel_init.S rename to arch/arm/mach-imx/imx8m/lowlevel_init.S diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c new file mode 100644 index 00000000000..6d8c22c27f1 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -0,0 +1,763 @@ +/* + * Copyright 2017-2019 NXP + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_IMX_SEC_INIT +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SECURE_BOOT) || defined(CONFIG_AVB_ATX) +struct imx_sec_config_fuse_t const imx_sec_config_fuse = { + .bank = 1, + .word = 3, +}; +#endif + +int timer_init(void) +{ +#ifdef CONFIG_SPL_BUILD + struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; + unsigned long freq = readl(&sctr->cntfid0); + + /* Update with accurate clock frequency */ + asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory"); + + clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1, + SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG); +#endif + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + return 0; +} + +void enable_tzc380(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable TZASC and lock setting */ + setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); + setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); +#ifdef CONFIG_IMX8MM + setbits_le32(&gpr->gpr[10], GPR_TZASC_SWAP_ID); +#endif + + /* + * set Region 0 attribute to allow secure and non-secure read/write permission + * Found some masters like usb dwc3 controllers can't work with secure memory. + */ + writel(0xf0000000, TZASC_BASE_ADDR + 0x108); +} + +void set_wdog_reset(struct wdog_regs *wdog) +{ + /* + * Output WDOG_B signal to reset external pmic or POR_B decided by + * the board design. Without external reset, the peripherals/DDR/ + * PMIC are not reset, that may cause system working abnormal. + * WDZST bit is write-once only bit. Align this bit in kernel, + * otherwise kernel code will have no chance to set this bit. + */ + setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); +} + +static struct mm_region imx8m_mem_map[] = { + { + /* ROM */ + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + .virt = 0x100000UL, + .phys = 0x100000UL, + .size = 0x8000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x7C0000UL, + .phys = 0x7C0000UL, + .size = 0x80000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OCRAM */ + .virt = 0x900000UL, + .phys = 0x900000UL, + .size = 0x200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* AIPS */ + .virt = 0xB00000UL, + .phys = 0xB00000UL, + .size = 0x3f500000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* DRAM1 */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = PHYS_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#ifdef CONFIG_IMX_TRUSTY_OS + PTE_BLOCK_INNER_SHARE +#else + PTE_BLOCK_OUTER_SHARE +#endif +#if CONFIG_NR_DRAM_BANKS > 1 + }, { + /* DRAM2 */ + .virt = 0x100000000UL, + .phys = 0x100000000UL, + .size = PHYS_SDRAM_2_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#ifdef CONFIG_IMX_TRUSTY_OS + PTE_BLOCK_INNER_SHARE +#else + PTE_BLOCK_OUTER_SHARE +#endif +#endif + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = imx8m_mem_map; + +void enable_caches(void) +{ + /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */ + if (rom_pointer[1]) { + imx8m_mem_map[5].size -= rom_pointer[1]; + } + + icache_enable(); + dcache_enable(); +} + +static u32 get_cpu_variant_type(u32 type) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + + u32 value = readl(&fuse->tester4); + + if (type == MXC_CPU_IMX8MQ) { + if ((value & 0x3) == 0x2) + return MXC_CPU_IMX8MD; + else if (value & 0x200000) + return MXC_CPU_IMX8MQL; + + } else if (type == MXC_CPU_IMX8MM) { + switch (value & 0x3) { + case 2: + if (value & 0x1c0000) + return MXC_CPU_IMX8MMDL; + else + return MXC_CPU_IMX8MMD; + case 3: + if (value & 0x1c0000) + return MXC_CPU_IMX8MMSL; + else + return MXC_CPU_IMX8MMS; + default: + if (value & 0x1c0000) + return MXC_CPU_IMX8MML; + break; + } + } + + return type; +} + +u32 get_cpu_rev(void) +{ + struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; + u32 reg = readl(&ana_pll->digprog); + u32 type = (reg >> 16) & 0xff; + u32 major_low = (reg >> 8) & 0xff; + u32 rom_version; + + reg &= 0xff; + + /* iMX8MM */ + if (major_low == 0x41) { + type = get_cpu_variant_type(MXC_CPU_IMX8MM); + return (type << 12) | reg; + } else { + /* iMX8MQ */ + if (reg == CHIP_REV_1_0) { + /* + * For B0 chip, the DIGPROG is not updated, still TO1.0. + * we have to check ROM version or OCOTP_READ_FUSE_DATA + */ + if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) + == 0xff0055aa) { + /* 0xff0055aa is magic number for B1 */ + reg = CHIP_REV_2_1; + } else { + rom_version = readb((void __iomem *)ROM_VERSION_A0); + if (rom_version != CHIP_REV_1_0) { + rom_version = readb((void __iomem *)ROM_VERSION_B0); + if (rom_version == CHIP_REV_2_0) + reg = CHIP_REV_2_0; + } + } + } + + type = get_cpu_variant_type(type); + + return (type << 12) | reg; + } +} + +static void imx_set_wdog_powerdown(bool enable) +{ + struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; + struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; + struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; + + /* Write to the PDE (Power Down Enable) bit */ + writew(enable, &wdog1->wmcr); + writew(enable, &wdog2->wmcr); + writew(enable, &wdog3->wmcr); +} + +int arch_cpu_init(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + /* + * Init timer at very early state, because pll setting will use it, + * Rom Turnned off SCTR, enable it before timer_init + */ + + clock_enable(CCGR_SCTR, 1); + timer_init(); + + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + clock_init(); + imx_set_wdog_powerdown(false); + + if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() || is_imx8mmsl()) { + /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */ + struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840); + struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880); + struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0); + struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR; + + writel(0x1, &pgc_core2->pgcr); + writel(0x1, &pgc_core3->pgcr); + if (is_imx8mms() || is_imx8mmsl()) { + writel(0x1, &pgc_core1->pgcr); + writel(0xE, &gpc->cpu_pgc_dn_trg); + } else { + writel(0xC, &gpc->cpu_pgc_dn_trg); + } + } + } + +#ifdef CONFIG_IMX_SEC_INIT + /* Secure init function such RNG */ + imx_sec_init(); +#endif +#if defined(CONFIG_ANDROID_SUPPORT) + /* Enable RTC */ + writel(0x21, 0x30370038); +#endif + + if (is_imx8mq()) { + clock_enable(CCGR_OCOTP, 1); + if (readl(&ocotp->ctrl) & 0x200) + writel(0x200, &ocotp->ctrl_clr); + } + + return 0; +} + +bool is_usb_boot(void) +{ + return get_boot_device() == USB_BOOT; +} +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + serialnr->low = fuse->uid_low; + serialnr->high = fuse->uid_high; +} +#endif + +#ifdef CONFIG_OF_SYSTEM_SETUP +static int ft_add_optee_node(void *fdt, bd_t *bd) +{ + const char *path, *subpath; + int offs; + + /* + * No TEE space allocated indicating no TEE running, so no + * need to add optee node in dts + */ + if (!rom_pointer[1]) + return 0; + + offs = fdt_increase_size(fdt, 512); + if (offs) { + printf("No Space for dtb\n"); + return 1; + } + + path = "/firmware"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + path = "/"; + offs = fdt_path_offset(fdt, path); + + if (offs < 0) { + printf("Could not find root node.\n"); + return 1; + } + + subpath = "firmware"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s node.\n", subpath); + } + } + + subpath = "optee"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s node.\n", subpath); + } + + fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz"); + fdt_setprop_string(fdt, offs, "method", "smc"); + + return 0; +} + +static int disable_fdt_nodes(void *blob, const char *nodes_path[], int size_array) +{ + int i = 0; + int rc; + int nodeoff; + const char *status = "disabled"; + + for (i = 0; i < size_array; i++) { + nodeoff = fdt_path_offset(blob, nodes_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + printf("Found %s node\n", nodes_path[i]); + +add_status: + rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1); + if (rc) { + if (rc == -FDT_ERR_NOSPACE) { + rc = fdt_increase_size(blob, 512); + if (!rc) + goto add_status; + } + printf("Unable to update property %s:%s, err=%s\n", + nodes_path[i], "status", fdt_strerror(rc)); + } else { + printf("Modify %s:%s disabled\n", + nodes_path[i], "status"); + } + } + + return 0; +} + +#ifdef CONFIG_IMX8MQ +bool check_dcss_fused(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + + u32 value = readl(&fuse->tester4); + if (value & 0x4000000) + return true; + + return false; +} + +static int disable_mipi_dsi_nodes(void *blob) +{ + const char *nodes_path[] = { + "/mipi_dsi@30A00000", + "/mipi_dsi_bridge@30A00000", + "/dsi_phy@30A00300" + }; + + return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path)); +} + +static int disable_dcss_nodes(void *blob) +{ + const char *nodes_path[] = { + "/dcss@0x32e00000", + "/dcss@32e00000", + "/hdmi@32c00000", + "/hdmi_cec@32c33800", + "/hdmi_drm@32c00000", + "/display-subsystem", + "/sound-hdmi", + "/sound-hdmi-arc" + }; + + return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path)); +} + +static int check_mipi_dsi_nodes(void *blob) +{ + const char *lcdif_path = "/lcdif@30320000"; + const char *mipi_dsi_path = "/mipi_dsi@30A00000"; + + const char *lcdif_ep_path = "/lcdif@30320000/port@0/mipi-dsi-endpoint"; + const char *mipi_dsi_ep_path = "/mipi_dsi@30A00000/port@1/endpoint"; + + int nodeoff; + nodeoff = fdt_path_offset(blob, lcdif_path); + if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) { + /* If can't find lcdif node or lcdif node is disabled, then disable all mipi dsi, + since they only can input from DCSS */ + return disable_mipi_dsi_nodes(blob); + } + + nodeoff = fdt_path_offset(blob, mipi_dsi_path); + if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) + return 0; + + nodeoff = fdt_path_offset(blob, lcdif_ep_path); + if (nodeoff < 0) { + /* If can't find lcdif endpoint, then disable all mipi dsi, + since they only can input from DCSS */ + return disable_mipi_dsi_nodes(blob); + } else { + int lookup_node; + lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint"); + nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path); + + if (nodeoff >0 && nodeoff == lookup_node) + return 0; + + return disable_mipi_dsi_nodes(blob); + } + +} + +void board_quiesce_devices(void) +{ +#ifdef CONFIG_USB_DWC3 + if (is_usb_boot()) + disconnect_from_pc(); +#endif +} +#endif + +static int disable_vpu_nodes(void *blob) +{ + const char *nodes_path_8mq[] = { + "/vpu@38300000" + }; + + const char *nodes_path_8mm[] = { + "/vpu_g1@38300000", + "/vpu_g2@38310000", + "/vpu_h1@38320000" + }; + + if (is_imx8mq()) + return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq)); + else if (is_imx8mm()) + return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm)); + else + return -EPERM; + +} + +static int disable_cpu_nodes(void *blob, u32 disabled_cores) +{ + const char *nodes_path[] = { + "/cpus/cpu@1", + "/cpus/cpu@2", + "/cpus/cpu@3", + }; + + u32 i = 0; + int rc; + int nodeoff; + + if (disabled_cores > 3) + return -EINVAL; + + i = 3 - disabled_cores; + + for (; i < 3; i++) { + nodeoff = fdt_path_offset(blob, nodes_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + printf("Found %s node\n", nodes_path[i]); + + rc = fdt_del_node(blob, nodeoff); + if (rc < 0) { + printf("Unable to delete node %s, err=%s\n", + nodes_path[i], fdt_strerror(rc)); + } else { + printf("Delete node %s\n", nodes_path[i]); + } + } + + return 0; +} + +int ft_system_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_IMX8MQ + int i = 0; + int rc; + int nodeoff; + + if (get_boot_device() == USB_BOOT) { + + disable_dcss_nodes(blob); + + const char *usb_dwc3_path = "/usb@38100000/dwc3"; + nodeoff = fdt_path_offset(blob, usb_dwc3_path); + if (nodeoff >= 0) { + const char *speed = "high-speed"; + printf("Found %s node\n", usb_dwc3_path); + +usb_modify_speed: + + rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1); + if (rc) { + if (rc == -FDT_ERR_NOSPACE) { + rc = fdt_increase_size(blob, 512); + if (!rc) + goto usb_modify_speed; + } + printf("Unable to set property %s:%s, err=%s\n", + usb_dwc3_path, "maximum-speed", fdt_strerror(rc)); + } else { + printf("Modify %s:%s = %s\n", + usb_dwc3_path, "maximum-speed", speed); + } + }else { + printf("Can't found %s node\n", usb_dwc3_path); + } + } + + /* Disable the CPU idle for A0 chip since the HW does not support it */ + if (is_soc_rev(CHIP_REV_1_0)) { + static const char * const nodes_path[] = { + "/cpus/cpu@0", + "/cpus/cpu@1", + "/cpus/cpu@2", + "/cpus/cpu@3", + }; + + for (i = 0; i < ARRAY_SIZE(nodes_path); i++) { + nodeoff = fdt_path_offset(blob, nodes_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + printf("Found %s node\n", nodes_path[i]); + + rc = fdt_delprop(blob, nodeoff, "cpu-idle-states"); + if (rc) { + printf("Unable to update property %s:%s, err=%s\n", + nodes_path[i], "status", fdt_strerror(rc)); + return rc; + } + + printf("Remove %s:%s\n", nodes_path[i], + "cpu-idle-states"); + } + } + + if (is_imx8mql()) { + disable_vpu_nodes(blob); + if (check_dcss_fused()) { + printf("DCSS is fused\n"); + disable_dcss_nodes(blob); + check_mipi_dsi_nodes(blob); + } + } + + if (is_imx8md()) + disable_cpu_nodes(blob, 2); + +#elif defined(CONFIG_IMX8MM) + if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl()) + disable_vpu_nodes(blob); + + if (is_imx8mmd() || is_imx8mmdl()) + disable_cpu_nodes(blob, 2); + else if (is_imx8mms() || is_imx8mmsl()) + disable_cpu_nodes(blob, 3); +#endif + + return ft_add_optee_node(blob, bd); +} +#endif + +void reset_cpu(ulong addr) +{ + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + + /* Clear WDA to trigger WDOG_B immediately */ + writew((WCR_WDE | WCR_SRS), &wdog->wcr); + + while (1) { + /* + * spin for .5 seconds before reset + */ + } +} + +#if defined(CONFIG_ARCH_MISC_INIT) +#define FSL_SIP_BUILDINFO 0xC2000003 +#define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00 +static void acquire_buildinfo(void) +{ + uint64_t atf_commit = 0; + + /* Get ARM Trusted Firmware commit id */ + atf_commit = call_imx_sip(FSL_SIP_BUILDINFO, + FSL_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0); + if (atf_commit == 0xffffffff) { + debug("ATF does not support build info\n"); + atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */ + } + + printf("\n BuildInfo:\n - ATF %s\n - %s\n\n", (char *)&atf_commit, + U_BOOT_VERSION); +} + +int arch_misc_init(void) +{ + acquire_buildinfo(); + + return 0; +} +#endif + +#define FSL_SIP_GPC 0xC2000000 +#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03 + +#ifdef CONFIG_SPL_BUILD +static uint32_t gpc_pu_m_core_offset[11] = { + 0xc00, 0xc40, 0xc80, 0xcc0, + 0xdc0, 0xe00, 0xe40, 0xe80, + 0xec0, 0xf00, 0xf40, +}; + +#define PGC_PCR 0 + +void imx_gpc_set_m_core_pgc(unsigned int offset, bool pdn) +{ + uint32_t val; + uintptr_t reg = GPC_BASE_ADDR + offset; + + val = readl(reg); + val &= ~(0x1 << PGC_PCR); + + if(pdn) + val |= 0x1 << PGC_PCR; + writel(val, reg); +} + +void imx8m_usb_power_domain(uint32_t domain_id, bool on) +{ + uint32_t val; + uintptr_t reg; + + imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], true); + + reg = GPC_BASE_ADDR + (on ? 0xf8 : 0x104); + val = 1 << (domain_id > 3 ? (domain_id + 3) : domain_id); + writel(val, reg); + while (readl(reg) & val) + ; + imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], false); +} +#endif + +int imx8m_usb_power(int usb_id, bool on) +{ + if (usb_id > 1) + return -EINVAL; +#ifdef CONFIG_SPL_BUILD + imx8m_usb_power_domain(2 + usb_id, on); +#else + if (call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, + 2 + usb_id, on, 0)) + return -EPERM; +#endif + return 0; +} + +void nxp_tmu_arch_init(void *reg_base) +{ + if (is_imx8mm()) { + /* Load TCALIV and TASR from fuses */ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[3]; + struct fuse_bank3_regs *fuse = + (struct fuse_bank3_regs *)bank->fuse_regs; + + u32 tca_rt, tca_hr, tca_en; + u32 buf_vref, buf_slope; + + tca_rt = fuse->ana0 & 0xFF; + tca_hr = (fuse->ana0 & 0xFF00) >> 8; + tca_en = (fuse->ana0 & 0x2000000) >> 25; + + buf_vref = (fuse->ana0 & 0x1F00000) >> 20; + buf_slope = (fuse->ana0 & 0xF0000) >> 16; + + writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28); + writel((tca_en << 31) |(tca_hr <<16) | tca_rt, (ulong)reg_base + 0x30); + } +} diff --git a/arch/arm/mach-imx/imx8m/video_common.c b/arch/arm/mach-imx/imx8m/video_common.c new file mode 100644 index 00000000000..e2c7c01258a --- /dev/null +++ b/arch/arm/mach-imx/imx8m/video_common.c @@ -0,0 +1,742 @@ +/* + * Copyright 2018-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* test congiurations */ +#undef IMXDCSS_LOAD_HDMI_FIRMWARE +#undef IMXDCSS_SET_PIXEL_CLOCK + +static struct video_mode_settings gmode; +static uint32_t gpixfmt; +GraphicDevice panel; +struct video_mode_settings *imx8m_get_gmode(void) +{ + return &gmode; +} + +void imx8m_show_gmode(void) +{ + printf("gmode =\n" + "pixelclock = %u\n" + "xres = %u\n" + "yres = %u\n" + "hfp = %u\n" + "hbp = %u\n" + "vfp = %u\n" + "vbp = %u\n" + "hsync = %u\n" + "vsync = %u\n" + "hpol = %u\n" + "vpol = %u\n", + gmode.pixelclock, + gmode.xres, + gmode.yres, + gmode.hfp, + gmode.hbp, + gmode.vfp, + gmode.vbp, gmode.hsync, gmode.vsync, gmode.hpol, gmode.vpol); +} + +GraphicDevice *imx8m_get_gd(void) +{ + return &panel; +} + +#define REG_BASE_ADDR 0x32e00000UL + +/*#define DEBUGREG*/ +#ifdef DEBUGREG +#define reg32_write(addr, val) \ +do { \ + debug("%s():%d 0x%08x -> 0x%08x\n", __func__, __LINE__, \ + (unsigned int)addr, (unsigned int)val); \ + __raw_writel(val, addr); \ +} while (0) +#else +#define reg32_write(addr, val) __raw_writel(val, addr) +#endif + +#define reg32_read(addr) __raw_readl(addr) + +#define reg32setbit(addr, bitpos) \ + reg32_write((addr), (reg32_read((addr)) | (1<<(bitpos)))) +#define reg32clearbit(addr, bitpos) \ + reg32_write((addr), (reg32_read((addr)) & ~(1<<(bitpos)))) + +#define reg32_read_tst(addr, val, mask) \ +do { \ + u32 temp = reg32_read((addr)); \ + if ((temp & (mask)) == ((val) & (mask))) \ + debug("%s():%d 0x%08x -> 0x%08x\n", \ + __func__, __LINE__, addr, val); \ + else \ + debug("%s():%d 0x%08x -> 0x%08x instead of 0x%08x\n", \ + __func__, __LINE__, addr, temp, val); \ +} while (0) + +#define COLOR_LIST_SIZE 8 +static u32 color_list_argb32[COLOR_LIST_SIZE] = { + 0xFFFFFFFF, /* white */ + 0xFFFF0000, /* red */ + 0xFF00FF00, /* green */ + 0xFF0000FF, /* blue */ + 0xFFFFFF00, /* yellow */ + 0xFF00FFFF, /* cyan */ + 0xFFFF00FF, /* magenta */ + 0xFFC1C2C3, /* silver */ +}; /*AARRGGBB */ + +static unsigned int get_color_index(unsigned short px, unsigned short py, + unsigned short width, unsigned short height, + unsigned short bar_size) +{ + const int mw = 5; /* margin width */ + if ((py >= 0 && py < mw) || (py >= height - mw && py < height) || + (px >= 0 && px < mw) || (px >= width - mw && px < width)) { + return 1; + } + + return py / bar_size; +} + +void imx8m_create_color_bar(void *start_address, + struct video_mode_settings *vms) +{ + /*struct video_mode_settings *vms = &vm_settings[g_vm]; */ + uint32_t color_bar_size = vms->yres / COLOR_LIST_SIZE; + int i, j; + u32 *pointer; + int color_index = 0; + pointer = (u32 *)start_address; + uint32_t *color_map = &color_list_argb32[0]; + debug("%s(), %d: start_address %p\n", + __func__, __LINE__, start_address); + debug("%s(), %d: pointer %p\n", __func__, __LINE__, pointer); + debug("%s(), %d x %d\n", __func__, vms->xres, vms->yres); + for (i = 0; i < vms->yres; i++) { + for (j = 0; j < vms->xres; j++) { + color_index = get_color_index(j, i, vms->xres, + vms->yres, + color_bar_size); + *pointer = color_map[color_index]; + pointer++; + } + } + invalidate_dcache_all(); +} + +static void imx8m_set_clocks(int apb_clk, int b_clk, int hdmi_core_clk, + int p_clk, int rtr_clk) +{ + if (b_clk == 800) { + /* b_clk: bus_clk_root(4) sel 2nd input source and + pre_div to 0; output should be 800M */ + clock_set_target_val(DISPLAY_AXI_CLK_ROOT, CLK_ROOT_ON |CLK_ROOT_SOURCE_SEL(2)); + } else { + printf("b_clk does not match a supported frequency"); + } + if (rtr_clk == 400) { + /* rtr_clk: bus_clk_root(6) sel 1st input source + and pre_div to 1; output should be 400M */ + clock_set_target_val(DISPLAY_RTRM_CLK_ROOT, + CLK_ROOT_ON |CLK_ROOT_SOURCE_SEL(1) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2)); + } else { + debug("rtr_clk does not match a supported frequency"); + } + +#ifdef IMXDCSS_LOAD_HDMI_FIRMWARE + /* If ROM is loading HDMI firmware then this clock should not be set */ + if (hdmi_core_clk == 200) { + /* hdmi_core_clk: ip_clk_root(69) sel 1st input source and + pre_div to 0 */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(69), + (0x7 << 24) | (0x7 << 16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(69), (0x1 << 24)); + g_hdmi_core_clock = 200000000; + } else { + debug("hdmi_core_clk does not match a supported frequency"); + } +#endif + +#ifdef IMXDCSS_SET_PIXEL_CLOCK + /* This would be needed for MIPI-DSI DCSS display */ + if (p_clk == 27) { + /* p_clk: ip_clk_root(9) sel 1st input source and + pre_div to 1; post_div to 5, output 100M */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9), + (0x7 << 24) | (0x7 << 16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9), + (0x1 << 24) | (29 << 16)); + } else if (p_clk == 100) { + /* p_clk: ip_clk_root(9) sel 1st input source and + pre_div to 1; post_div to 5, output 100M */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9), + (0x7 << 24) | (0x7 << 16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9), + (0x1 << 24) | (0x5 << 16)); + } else if (p_clk == 120) { + /* p_clk: ip_clk_root(9) sel 1st input source and + pre_div to 1; post_div to 4, output 120M */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9), + (0x7 << 24) | (0x7 << 16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9), + (0x1 << 24) | (0x4 << 16)); + } else if (p_clk == 200) { + /* I added this to speed up the pixel clock and + get frames out faster. may need to adjust this. + */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9), + (0x7 << 24) | (0x7 << 16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9), + (0x4 << 24) | (0x3 << 16)); /*for emu use 800 / 4 */ + } else if (p_clk == 400) { + /* I added this to speed up the pixel clock and + get frames out faster. may need to adjust this. + */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9), + (0x7 << 24) | (0x7 << 16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9), + (0x4 << 24) | (0x1 << 16)); /*for emu use 800 / 2 */ + } else if (p_clk == 40) { /* Do not reprogram, will get 40MHz */ + } else { + debug("p_clk does not match a supported frequency"); + } +#endif +} + +static int imx8m_power_init(uint32_t clock_control) +{ + u32 temp; + /*struct video_mode_settings *vms = &vm_settings[g_vm]; */ + + debug("\nenabling display clock...\n"); + clock_enable(CCGR_DISPLAY, 1); + + reg32_write(0x303A00EC, 0x0000ffff); /*PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 10); /*PU_PGC_SW_PUP_REQ : disp was 10 */ +#ifdef LOAD_HDMI_FIRMWARE + reg32setbit(0x303A00F8, 9); /*PU_PGC_SW_PUP_REQ : hdmi was 9 */ +#endif + imx8m_set_clocks(133, 800, 200, 27, 400); + + /* DCSS reset */ + reg32_write(0x32e2f000, 0xffffffff); + + /* DCSS clock selection */ + reg32_write(0x32e2f010, clock_control); + temp = reg32_read(0x32e2f010); + debug("%s(): DCSS clock control 0x%08x\n", __func__, temp); + + /* take DCSS out of reset - not needed OFB */ + /*__raw_writel(0xffffffff, 0x32e2f004); */ + + return 0; +} + +static void imx8m_display_init(u64 buffer, int encoding, + struct video_mode_settings *vms) +{ + /*struct video_mode_settings *vms = &vm_settings[g_vm]; */ + + debug("entering %s() ...\n", __func__); + debug("%s() buffer ...\n", __func__); + + /* DTRC-CHAN2/3 */ + reg32_write(REG_BASE_ADDR + 0x160c8, 0x00000002); + reg32_write(REG_BASE_ADDR + 0x170c8, 0x00000002); + + /* CHAN1_DPR */ + reg32_write(REG_BASE_ADDR + 0x180c0, (unsigned int)buffer); + reg32_write(REG_BASE_ADDR + 0x18090, 0x00000002); + reg32_write(REG_BASE_ADDR + 0x180a0, vms->xres); + reg32_write(REG_BASE_ADDR + 0x180b0, vms->yres); + reg32_write(REG_BASE_ADDR + 0x18110, + (unsigned int)buffer + vms->xres * vms->yres); + reg32_write(REG_BASE_ADDR + 0x180f0, 0x00000280); + reg32_write(REG_BASE_ADDR + 0x18100, 0x000000f0); + reg32_write(REG_BASE_ADDR + 0x18070, ((vms->xres * 4) << 16)); + reg32_write(REG_BASE_ADDR + 0x18050, 0x000e4203); + reg32_write(REG_BASE_ADDR + 0x18050, 0x000e4203); + reg32_write(REG_BASE_ADDR + 0x18200, 0x00000038); + reg32_write(REG_BASE_ADDR + 0x18000, 0x00000004); + reg32_write(REG_BASE_ADDR + 0x18000, 0x00000005); + + /* SCALER */ + reg32_write(REG_BASE_ADDR + 0x1c008, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c00c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c010, 0x00000002); + reg32_write(REG_BASE_ADDR + 0x1c014, 0x00000002); + reg32_write(REG_BASE_ADDR + 0x1c018, + ((vms->yres - 1) << 16 | (vms->xres - 1))); + reg32_write(REG_BASE_ADDR + 0x1c01c, + ((vms->yres - 1) << 16 | (vms->xres - 1))); + reg32_write(REG_BASE_ADDR + 0x1c020, + ((vms->yres - 1) << 16 | (vms->xres - 1))); + reg32_write(REG_BASE_ADDR + 0x1c024, + ((vms->yres - 1) << 16 | (vms->xres - 1))); + reg32_write(REG_BASE_ADDR + 0x1c028, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c02c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c030, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c034, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c038, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c03c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c040, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c044, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c048, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c04c, 0x00002000); + reg32_write(REG_BASE_ADDR + 0x1c050, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c054, 0x00002000); + reg32_write(REG_BASE_ADDR + 0x1c058, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c05c, 0x00002000); + reg32_write(REG_BASE_ADDR + 0x1c060, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c064, 0x00002000); + reg32_write(REG_BASE_ADDR + 0x1c080, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0c0, 0x00040000); + reg32_write(REG_BASE_ADDR + 0x1c100, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c084, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0c4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c104, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c088, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0c8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c108, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c08c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0cc, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c10c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c090, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0d0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c110, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c094, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0d4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c114, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c098, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0d8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c118, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c09c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0dc, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c11c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0a0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0e0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c120, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0a4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0e4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c124, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0a8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0e8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c128, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0ac, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0ec, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c12c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0b0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0f0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c130, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0b4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0f4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c134, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0b8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0f8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c138, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0bc, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c0fc, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c13c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c140, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c180, 0x00040000); + reg32_write(REG_BASE_ADDR + 0x1c1c0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c144, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c184, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1c4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c148, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c188, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1c8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c14c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c18c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1cc, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c150, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c190, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1d0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c154, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c194, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1d4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c158, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c198, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1d8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c15c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c19c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1dc, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c160, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1a0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1e0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c164, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1a4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1e4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c168, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1a8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1e8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c16c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1ac, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1ec, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c170, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1b0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1f0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c174, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1b4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1f4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c178, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1b8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1f8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c17c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1bc, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c1fc, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c300, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c340, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c380, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c304, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c344, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c384, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c308, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c348, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c388, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c30c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c34c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c38c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c310, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c350, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c390, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c314, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c354, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c394, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c318, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c358, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c398, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c31c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c35c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c39c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c320, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c360, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c3a0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c324, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c364, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c3a4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c328, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c368, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c3a8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c32c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c36c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c3ac, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c330, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c370, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c3b0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c334, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c374, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c3b4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c338, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c378, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c3b8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c33c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c37c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c3bc, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c200, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c240, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c280, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c204, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c244, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c284, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c208, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c248, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c288, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c20c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c24c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c28c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c210, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c250, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c290, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c214, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c254, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c294, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c218, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c258, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c298, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c21c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c25c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c29c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c220, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c260, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c2a0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c224, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c264, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c2a4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c228, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c268, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c2a8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c22c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c26c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c2ac, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c230, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c270, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c2b0, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c234, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c274, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c2b4, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c238, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c278, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c2b8, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c23c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c27c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c2bc, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c2bc, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x1c000, 0x00000011); + + /* SUBSAM */ + reg32_write(REG_BASE_ADDR + 0x1b070, 0x21612161); + reg32_write(REG_BASE_ADDR + 0x1b080, 0x03ff0000); + reg32_write(REG_BASE_ADDR + 0x1b090, 0x03ff0000); + + reg32_write(REG_BASE_ADDR + 0x1b010, + (((vms->vfp + vms->vbp + vms->vsync + vms->yres - + 1) << 16) | (vms->hfp + vms->hbp + vms->hsync + + vms->xres - 1))); + reg32_write(REG_BASE_ADDR + 0x1b020, + (((vms->hsync - 1) << 16) | vms->hpol << 31 | (vms->hfp + + vms->hbp + + vms->hsync + + vms->xres - + 1))); + reg32_write(REG_BASE_ADDR + 0x1b030, + (((vms->vfp + vms->vsync - + 1) << 16) | vms->vpol << 31 | (vms->vfp - 1))); + + reg32_write(REG_BASE_ADDR + 0x1b040, + ((1 << 31) | ((vms->vsync + vms->vfp + vms->vbp) << 16) | + (vms->hsync + vms->hbp - 1))); + reg32_write(REG_BASE_ADDR + 0x1b050, + (((vms->vsync + vms->vfp + vms->vbp + vms->yres - + 1) << 16) | (vms->hsync + vms->hbp + vms->xres - 1))); + + /* subsample mode 0 none, 1 422, 2 420 */ + switch (encoding) { + case 4: + reg32_write(REG_BASE_ADDR + 0x1b060, 0x00000001); + break; + + case 8: + reg32_write(REG_BASE_ADDR + 0x1b060, 0x00000002); + break; + + case 2: + case 1: + default: + reg32_write(REG_BASE_ADDR + 0x1b060, 0x0000000); + } + + reg32_write(REG_BASE_ADDR + 0x1b000, 0x00000001); +#if 0 + /* not needed for splash setup */ + /* HDR10 Chan3 LUT */ + reg32_write(REG_BASE_ADDR + 0x03874, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x03080, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x03000, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x03800, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x07874, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x07080, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x07000, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x07800, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0b874, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0b080, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0b000, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0b800, 0x00000000); + + /* HDR10 Tables and Registers */ + /*reg32_write(REG_BASE_ADDR+0x0f074, 0x00000003); */ + /*reg32_write(REG_BASE_ADDR+0x0f000, 0x00000004); */ + + reg32_write(REG_BASE_ADDR + 0x0f004, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f008, 0x00000001); + reg32_write(REG_BASE_ADDR + 0x0f00c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f010, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f014, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f018, 0x00000001); + reg32_write(REG_BASE_ADDR + 0x0f01c, 0x00000001); + reg32_write(REG_BASE_ADDR + 0x0f020, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f024, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f028, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f02c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f030, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f034, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f038, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f03c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f040, 0xffffffff); + reg32_write(REG_BASE_ADDR + 0x0f044, 0xffffffff); + reg32_write(REG_BASE_ADDR + 0x0f048, 0xffffffff); + reg32_write(REG_BASE_ADDR + 0x0f04c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f050, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f054, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f058, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f05c, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f060, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f064, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f068, 0xffffffff); + reg32_write(REG_BASE_ADDR + 0x0f06c, 0xffffffff); + reg32_write(REG_BASE_ADDR + 0x0f070, 0xffffffff); + reg32_write(REG_BASE_ADDR + 0x0f074, 0x00000000); + reg32_write(REG_BASE_ADDR + 0x0f000, 0x00000003); +#endif + /* DTG */ + /*reg32_write(REG_BASE_ADDR + 0x20000, 0xff000484); */ + /* disable local alpha */ + reg32_write(REG_BASE_ADDR + 0x20000, 0xff005084); + reg32_write(REG_BASE_ADDR + 0x20004, + (((vms->vfp + vms->vbp + vms->vsync + vms->yres - + 1) << 16) | (vms->hfp + vms->hbp + vms->hsync + + vms->xres - 1))); + reg32_write(REG_BASE_ADDR + 0x20008, + (((vms->vsync + vms->vfp + vms->vbp - + 1) << 16) | (vms->hsync + vms->hbp - 1))); + reg32_write(REG_BASE_ADDR + 0x2000c, + (((vms->vsync + vms->vfp + vms->vbp + vms->yres - + 1) << 16) | (vms->hsync + vms->hbp + vms->xres - 1))); + reg32_write(REG_BASE_ADDR + 0x20010, + (((vms->vsync + vms->vfp + vms->vbp - + 1) << 16) | (vms->hsync + vms->hbp - 1))); + reg32_write(REG_BASE_ADDR + 0x20014, + (((vms->vsync + vms->vfp + vms->vbp + vms->yres - + 1) << 16) | (vms->hsync + vms->hbp + vms->xres - 1))); + reg32_write(REG_BASE_ADDR + 0x20028, 0x000b000a); + + /* disable local alpha */ + reg32_write(REG_BASE_ADDR + 0x20000, 0xff005184); + + debug("leaving %s() ...\n", __func__); +} + +void imx8m_display_shutdown(void) +{ + /* stop the DCSS modules in use */ + /* dtg */ + reg32_write(REG_BASE_ADDR + 0x20000, 0); + /* scaler */ + reg32_write(REG_BASE_ADDR + 0x1c000, 0); + reg32_write(REG_BASE_ADDR + 0x1c400, 0); + reg32_write(REG_BASE_ADDR + 0x1c800, 0); + /* dpr */ + reg32_write(REG_BASE_ADDR + 0x18000, 0); + reg32_write(REG_BASE_ADDR + 0x19000, 0); + reg32_write(REG_BASE_ADDR + 0x1a000, 0); + /* sub-sampler*/ + reg32_write(REG_BASE_ADDR + 0x1b000, 0); +#if 0 + /* reset the DCSS */ + reg32_write(0x32e2f000, 0xffffe8); + udelay(100); + reg32_write(0x32e2f000, 0xffffff); +#endif + +} +void *video_hw_init(void) +{ + void *fb; + int encoding = 1; + int ret; + + debug("%s()\n", __func__); + + imx8m_power_init(0x1); + + panel.winSizeX = gmode.xres; + panel.winSizeY = gmode.yres; + panel.plnSizeX = gmode.xres; + panel.plnSizeY = gmode.yres; + panel.gdfBytesPP = 4; + panel.gdfIndex = GDF_32BIT_X888RGB; + panel.memSize = gmode.xres * gmode.yres * panel.gdfBytesPP; + + /* Allocate framebuffer */ + fb = memalign(0x1000, roundup(panel.memSize, 0x1000)); + debug("%s(): fb %p\n", __func__, fb); + if (!fb) { + printf("%s, %s(): Error allocating framebuffer!\n", + __FILE__, __func__); + return NULL; + } + + imx8m_create_color_bar((void *)((uint64_t) fb), &gmode); + + ret = imx8_hdmi_enable(encoding, &gmode); /* may change gmode */ + if (ret) { + printf("HDMI enable failed!\n"); + return NULL; + } + + /* start dccs */ + imx8m_display_init((uint64_t) fb, encoding, &gmode); + + panel.frameAdrs = (ulong) fb; + debug("IMXDCSS display started ...\n"); + + return &panel; +} + +void imx8m_fb_disable(void) +{ + debug("%s()\n", __func__); + if (panel.frameAdrs) { +#ifdef CONFIG_VIDEO_IMX8_HDMI + imx8_hdmi_disable(); +#endif + imx8m_display_shutdown(); + } + +} + +int imx8m_fb_init(struct fb_videomode const *mode, + uint8_t disp, uint32_t pixfmt) +{ + debug("entering %s()\n", __func__); + + if (is_imx8mql() && check_dcss_fused()) { + printf("dcss is diabled on i.MX8MQL\n"); + return -EPERM; + } + + if (disp > 1) { + debug("Invalid disp parameter %d for imxdcss_fb_init()\n", + disp); + return -EINVAL; + } + + memset(&gmode, 0, sizeof(struct video_mode_settings)); + gmode.pixelclock = PS2KHZ(mode->pixclock) * 1000; + gmode.xres = mode->xres; + gmode.hbp = mode->left_margin; + gmode.hfp = mode->right_margin; + + gmode.yres = mode->yres; + gmode.vbp = mode->upper_margin; + gmode.vfp = mode->lower_margin; + + gmode.hsync = mode->hsync_len; + gmode.vsync = mode->vsync_len; + gmode.hpol = (mode->flag & FB_SYNC_HOR_HIGH_ACT) ? 1 : 0; + gmode.vpol = (mode->flag & FB_SYNC_VERT_HIGH_ACT) ? 1 : 0; + gpixfmt = pixfmt; + + debug("leaving %s()\n", __func__); + + return 0; +} diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 6256b3a778f..14844221d80 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -11,23 +11,24 @@ #include #include +#ifndef CONFIG_IMX8 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) { - ulong stack, pc; + u32 stack, pc; if (!boot_private_data) return -EINVAL; - stack = *(ulong *)boot_private_data; - pc = *(ulong *)(boot_private_data + 4); + stack = *(u32 *)boot_private_data; + pc = *(u32 *)(boot_private_data + 4); /* Set the stack and pc to M4 bootROM */ writel(stack, M4_BOOTROM_BASE_ADDR); writel(pc, M4_BOOTROM_BASE_ADDR + 4); /* Enable M4 */ -#ifdef CONFIG_MX8M - call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0); +#ifdef CONFIG_IMX8M + call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0); #else clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK); @@ -38,8 +39,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) int arch_auxiliary_core_check_up(u32 core_id) { -#ifdef CONFIG_MX8M - return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0); +#ifdef CONFIG_IMX8M + return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0); #else unsigned int val; @@ -51,7 +52,7 @@ int arch_auxiliary_core_check_up(u32 core_id) return 1; #endif } - +#endif /* * To i.MX6SX and i.MX7D, the image supported by bootaux needs * the reset vector at the head for the image, with SP and PC @@ -69,11 +70,15 @@ static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr; int ret, up; + u32 core = 0; if (argc < 2) return CMD_RET_USAGE; - up = arch_auxiliary_core_check_up(0); + if (argc > 2) + core = simple_strtoul(argv[2], NULL, 10); + + up = arch_auxiliary_core_check_up(core); if (up) { printf("## Auxiliary core is already up\n"); return CMD_RET_SUCCESS; @@ -83,7 +88,7 @@ static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("## Starting auxiliary core at 0x%08lX ...\n", addr); - ret = arch_auxiliary_core_up(0, addr); + ret = arch_auxiliary_core_up(core, addr); if (ret) return CMD_RET_FAILURE; @@ -93,5 +98,7 @@ static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux, "Start auxiliary core", - "" + "
[]\n" + " - start auxiliary core [] (default 0),\n" + " at address
\n" ); diff --git a/arch/arm/mach-imx/imx_vservice.c b/arch/arm/mach-imx/imx_vservice.c new file mode 100644 index 00000000000..33f24864538 --- /dev/null +++ b/arch/arm/mach-imx/imx_vservice.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static LIST_HEAD(vservice_channels); + +void * __weak board_imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size) +{ + if (size <= CONFIG_IMX_VSERVICE_SHARED_BUFFER_SIZE) + return (void * )CONFIG_IMX_VSERVICE_SHARED_BUFFER; + + return NULL; +} + +void * imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size) +{ + return board_imx_vservice_get_buffer(node, size); +} + +int imx_vservice_blocking_request(struct imx_vservice_channel *node, u8 *buf, u32* size) +{ + int ret = 0; + union imx_m4_msg msg; + + msg.format.seq = node->msg_seq; + msg.format.type = MU_MSG_REQ; + msg.format.buffer = (u32)(ulong)buf; + msg.format.size = *size; + + ret = misc_call(node->mu_dev, 1000000, &msg, 4, &msg, 4); + if (ret) { + printf("%s: Send request MU message failed, ret %d\n", __func__, ret); + goto MU_ERR; + } + + if (msg.format.type != MU_MSG_RESP|| msg.format.seq != node->msg_seq) { + printf("%s: wrong msg response: type %d, seq %d, expect seq %d\n", + __func__, msg.format.type, msg.format.seq, node->msg_seq); + ret = -EIO; + goto MU_ERR; + } + + *size = msg.format.size; + +MU_ERR: + node->msg_seq++; + + return ret; +} + +static int imx_vservice_connect(struct imx_vservice_channel *node) +{ + int ret = 0; + union imx_m4_msg msg; + + unsigned long timeout = timer_get_us() + 2000000; /* 2s timeout */ + + for (;;) { + msg.format.seq = 0; + msg.format.type = MU_MSG_READY_A; + msg.format.buffer = 0; + msg.format.size = 0; + + ret = misc_call(node->mu_dev, 100000, &msg, 4, &msg, 4); + if (!ret && msg.format.type == MU_MSG_READY_B) + return 0; + + if (time_after(timer_get_us(), timeout)) { + printf("%s: Timeout to connect peer, %d\n", __func__, ret); + return -ETIMEDOUT; + } + } + + return -EIO; +} + +struct udevice * __weak board_imx_vservice_find_mu(struct udevice *virt_dev) +{ + int ret; + struct ofnode_phandle_args args; + struct udevice *mu_dev; + + /* Default get mu from "fsl,vservice-mu" property*/ + ret = dev_read_phandle_with_args(virt_dev, "fsl,vservice-mu", + NULL, 0, 0, &args); + if (ret) { + printf("Can't find \"fsl,vservice-mu\" property\n"); + return NULL; + } + + ret = uclass_find_device_by_ofnode(UCLASS_MISC, args.node, &mu_dev); + if (ret) { + printf("Can't find MU device, err %d\n", ret); + return NULL; + } + + return mu_dev; +} + +static struct udevice * imx_vservice_find_mu(struct udevice *virt_dev) +{ + return board_imx_vservice_find_mu(virt_dev); +} + +struct imx_vservice_channel * imx_vservice_setup(struct udevice *virt_dev) +{ + int ret; + struct udevice *mu_dev; + struct imx_vservice_channel *channel; + + mu_dev = imx_vservice_find_mu(virt_dev); + if (mu_dev == NULL) { + printf("No MU device for virtual service %s connection\n", virt_dev->name); + return NULL; + } + + ret = device_probe(mu_dev); + if (ret) { + printf("Probe MU device failed\n"); + return NULL; + } + + list_for_each_entry(channel, &vservice_channels, channel_head) { + if (channel->mu_dev == mu_dev) + return channel; + } + + channel = malloc(sizeof(struct imx_vservice_channel)); + if (!channel) { + printf("Malloc vservice channel is failed\n"); + return NULL; + } + + channel->msg_seq = 0; + channel->mu_dev = mu_dev; + INIT_LIST_HEAD(&channel->channel_head); + + ret = imx_vservice_connect(channel); + if (ret) { + printf("VService: Connection is failed, ret %d\n", ret); + free(channel); + return NULL; + } + + list_add_tail(&channel->channel_head, &vservice_channels); + + printf("VService: Connection is ok on MU %s\n", mu_dev->name); + + return channel; +} diff --git a/arch/arm/mach-imx/misc.c b/arch/arm/mach-imx/misc.c index c64418390fe..356e5f6fce9 100644 --- a/arch/arm/mach-imx/misc.c +++ b/arch/arm/mach-imx/misc.c @@ -1,5 +1,6 @@ /* * Copyright 2013 Stefan Roese + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,6 +10,9 @@ #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; /* 1 second delay should be plenty of time for block reset. */ #define RESET_MAX_TIMEOUT 1000000 @@ -72,3 +76,40 @@ int mxs_reset_block(struct mxs_register_32 *reg) return 0; } + +void imx_sec_init(void) +{ +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) + caam_open(); +#endif +} + +static ulong get_sp(void) +{ + ulong ret; + + asm("mov %0, sp" : "=r"(ret) : ); + return ret; +} + +void board_lmb_reserve(struct lmb *lmb) +{ + ulong sp, bank_end; + int bank; + + sp = get_sp(); + debug("## Current stack ends at 0x%08lx ", sp); + + /* adjust sp by 16K to be safe */ + sp -= 4096 << 2; + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (sp < gd->bd->bi_dram[bank].start) + continue; + bank_end = gd->bd->bi_dram[bank].start + + gd->bd->bi_dram[bank].size; + if (sp >= bank_end) + continue; + lmb_reserve(lmb, sp, bank_end - sp); + break; + } +} diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c index ccadd2c1e0d..03757573df4 100644 --- a/arch/arm/mach-imx/mmc_env.c +++ b/arch/arm/mach-imx/mmc_env.c @@ -24,7 +24,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) - return CONFIG_SYS_MMC_ENV_DEV; + return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); return board_mmc_get_env_dev(devno); } diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index d4ce38db8d8..d5a5a7a38be 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -15,8 +15,7 @@ config MX6 imply CMD_FUSE config MX6D - select HAS_CAAM - select MX6_SMP + select MX6Q bool config MX6DL @@ -29,6 +28,10 @@ config MX6Q select MX6_SMP bool +config MX6QP + select MX6Q + bool + config MX6QDL select HAS_CAAM select MX6_SMP @@ -88,6 +91,51 @@ config MX6_DDRCAL Say "Y" if your board uses dynamic (per-boot) DDR calibration. If unsure, say N. +config LDO_BYPASS_CHECK + bool "Enable the LDO bypass checking and setting" + default y if !MX6SLL + help + This feature searches the gpc node in loaded DTB and checking the + "fsl,ldo-bypass" property. When the property is set, board relevant + PMIC settings are called to adjust for LDO bypass. + +config CMD_BEE + bool "Enable commands for Bus Encryption Engine(BEE)" + depends on MX6UL + help + Set "Y" to enable the bee commands + +config MODULE_FUSE + bool "Enable the module disable fuse checking on i.MX6" + default n + select OF_SYSTEM_SETUP + help + Once the module is checked as fused to disable, this module driver + won't be called. And it will be modified to disable in kernel DTB. + +config TARGET_MX6SABREAUTO + bool + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select NXP_BOARD_REVISION + +config TARGET_MX6SABRESD + bool + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select NXP_BOARD_REVISION + +config TARGET_MX6QDLARM2 + bool + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + choice prompt "MX6 board select" optional @@ -224,6 +272,13 @@ config TARGET_MX6MEMCAL config TARGET_MX6QARM2 bool "mx6qarm2" + select TARGET_MX6QDLARM2 + select MX6Q + +config TARGET_MX6DLARM2 + bool "mx6dlarm2" + select TARGET_MX6QDLARM2 + select MX6DL config TARGET_MX6Q_ENGICAM bool "Support Engicam i.Core(RQS)" @@ -243,23 +298,45 @@ config TARGET_MX6Q_ENGICAM select SPL_SEPARATE_BSS if SPL select SPL_PINCTRL if SPL -config TARGET_MX6SABREAUTO - bool "mx6sabreauto" - select MX6QDL - select BOARD_LATE_INIT - select SUPPORT_SPL - select DM - select DM_THERMAL - select BOARD_EARLY_INIT_F - -config TARGET_MX6SABRESD - bool "mx6sabresd" - select MX6QDL - select BOARD_LATE_INIT - select SUPPORT_SPL - select DM - select DM_THERMAL - select BOARD_EARLY_INIT_F +config TARGET_MX6QSABREAUTO + bool "mx6qsabreauto" + select TARGET_MX6SABREAUTO + select MX6Q + +config TARGET_MX6QPSABREAUTO + bool "mx6qpsabreauto" + select TARGET_MX6SABREAUTO + select MX6QP + +config TARGET_MX6DLSABREAUTO + bool "mx6dlsabreauto" + select TARGET_MX6SABREAUTO + select MX6DL + +config TARGET_MX6SOLOSABREAUTO + bool "mx6solosabreauto" + select TARGET_MX6SABREAUTO + select MX6S + +config TARGET_MX6QSABRESD + bool "mx6qsabresd" + select TARGET_MX6SABRESD + select MX6Q + +config TARGET_MX6QPSABRESD + bool "mx6qpsabresd" + select TARGET_MX6SABRESD + select MX6QP + +config TARGET_MX6DLSABRESD + bool "mx6dlsabresd" + select TARGET_MX6SABRESD + select MX6DL + +config TARGET_MX6SOLOSABRESD + bool "mx6solosabresd" + select TARGET_MX6SABRESD + select MX6S config TARGET_MX6SLEVK bool "mx6slevk" @@ -273,6 +350,13 @@ config TARGET_MX6SLLEVK select DM select DM_THERMAL +config TARGET_MX6SLL_ARM2 + bool "mx6sll arm2" + select BOARD_LATE_INIT + select MX6SLL + select DM + select DM_THERMAL + config TARGET_MX6SXSABRESD bool "mx6sxsabresd" select BOARD_LATE_INIT @@ -290,6 +374,30 @@ config TARGET_MX6SXSABREAUTO select DM_THERMAL select BOARD_EARLY_INIT_F +config TARGET_MX6SX_14X14_ARM2 + bool "mx6sx_14x14_arm2" + select MX6SX + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + +config TARGET_MX6SX_17X17_ARM2 + bool "mx6sx_17x17_arm2" + select MX6SX + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + +config TARGET_MX6SX_19X19_ARM2 + bool "mx6sx_19x19_arm2" + select MX6SX + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + config TARGET_MX6UL_9X9_EVK bool "mx6ul_9x9_evk" select BOARD_LATE_INIT @@ -306,6 +414,27 @@ config TARGET_MX6UL_14X14_EVK select DM_THERMAL select SUPPORT_SPL +config TARGET_MX6UL_14X14_DDR3_ARM2 + bool "mx6ul_14x14_ddr3_arm2" + select BOARD_LATE_INIT + select MX6UL + select DM + select DM_THERMAL + +config TARGET_MX6UL_14X14_LPDDR2_ARM2 + bool "mx6ul_14x14_lpddr2_arm2" + select BOARD_LATE_INIT + select MX6UL + select DM + select DM_THERMAL + +config TARGET_MX6UL_NXPU_IOPB + bool "Support mx6ul_nxpu_iopb" + select BOARD_LATE_INIT + select MX6UL + select DM + select DM_THERMAL + config TARGET_MX6UL_ENGICAM bool "Support Engicam GEAM6UL/Is.IoT" select BOARD_LATE_INIT @@ -323,6 +452,27 @@ config TARGET_MX6UL_ENGICAM select SPL_SEPARATE_BSS if SPL select SPL_PINCTRL if SPL +config TARGET_MX6UL_SPRIOT + bool "Support mx6ul_spriot" + select BOARD_LATE_INIT + select MX6UL + select DM + select DM_THERMAL + +config TARGET_MX6ULL_DDR3_ARM2 + bool "Support mx6ull_ddr3_arm2" + select BOARD_LATE_INIT + select MX6ULL + select DM + select DM_THERMAL + +config TARGET_MX6ULL_9X9_EVK + bool "Support mx6ull_9x9_evk" + select BOARD_LATE_INIT + select MX6ULL + select DM + select DM_THERMAL + config TARGET_MX6ULL_14X14_EVK bool "Support mx6ull_14x14_evk" select BOARD_LATE_INIT @@ -346,10 +496,25 @@ config TARGET_OT1200 select SUPPORT_SPL imply CMD_SATA +config TARGET_PICO_IMX6DL + bool "Support pico-imx6dl" + select MX6QDL + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + config TARGET_PICO_IMX6UL bool "PICO-IMX6UL-EMMC" select MX6UL +config TARGET_PICOSOM_IMX6UL + bool "Support picosom-imx6ul" + select BOARD_LATE_INIT + select MX6UL + select DM + select DM_THERMAL + config TARGET_LITEBOARD bool "Grinn liteBoard (i.MX6UL)" select BOARD_LATE_INIT @@ -471,11 +636,19 @@ source "board/freescale/mx6memcal/Kconfig" source "board/freescale/mx6sabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" source "board/freescale/mx6slevk/Kconfig" +source "board/freescale/mx6sll_arm2/Kconfig" source "board/freescale/mx6sllevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" +source "board/freescale/mx6sx_17x17_arm2/Kconfig" +source "board/freescale/mx6sx_19x19_arm2/Kconfig" +source "board/freescale/mx6ul_nxpu_iopb/Kconfig" +source "board/freescale/mx6ul_spriot/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" +source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig" +source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig" source "board/freescale/mx6ullevk/Kconfig" +source "board/freescale/mx6ull_ddr3_arm2/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/phytec/pfla02/Kconfig" @@ -489,6 +662,8 @@ source "board/seco/Kconfig" source "board/sks-kinkel/sksimx6/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" +source "board/technexion/pico-imx6dl/Kconfig" +source "board/technexion/picosom-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" diff --git a/arch/arm/mach-imx/mx6/Makefile b/arch/arm/mach-imx/mx6/Makefile index c183eb4a2fb..26566928d11 100644 --- a/arch/arm/mach-imx/mx6/Makefile +++ b/arch/arm/mach-imx/mx6/Makefile @@ -3,6 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2011 Freescale Semiconductor, Inc. +# Copyright 2018 NXP # # SPDX-License-Identifier: GPL-2.0+ # @@ -12,3 +13,7 @@ obj-$(CONFIG_SPL_BUILD) += ddr.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_MX6UL_LITESOM) += litesom.o obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o +ifdef CONFIG_MX6UL +obj-$(CONFIG_CMD_BEE) += bee.o +endif +obj-$(CONFIG_MODULE_FUSE) += module_fuse.o diff --git a/arch/arm/mach-imx/mx6/bee.c b/arch/arm/mach-imx/mx6/bee.c new file mode 100644 index 00000000000..0cd4ed436d9 --- /dev/null +++ b/arch/arm/mach-imx/mx6/bee.c @@ -0,0 +1,464 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if (defined(CONFIG_SYS_DCACHE_OFF) || defined(CONFIG_SYS_ICACHE_OFF)) +#error "Bee needs Cache Open" +#endif + +struct bee_parameters { + int key_method; + int mode; + u32 start1; + u32 size1; + u32 start2; + u32 size2; +}; + +#define SOFT_KEY 0 +#define SNVS_KEY 1 + +#define ECB_MODE 0 +#define CTR_MODE 1 + +#define AES_REGION0_ADDR 0x10000000 +#define AES_REGION1_ADDR 0x30000000 + +static struct bee_parameters para; +static int bee_inited; + +union key_soft { + u8 s_key[16]; + u32 b_key[4]; +}; + +union key_soft key_bad; + +/* software version */ +u8 hw_get_random_byte(void) +{ + static u32 lcg_state; + static u32 nb_soft = 9876543; +#define MAX_SOFT_RNG 1024 + static const u32 a = 1664525; + static const u32 c = 1013904223; + nb_soft = (nb_soft + 1) % MAX_SOFT_RNG; + lcg_state = (a * lcg_state + c); + return (u8) (lcg_state >> 24); +} + +/* + * Lock bee GPR0 bits + * Only reset can release these bits. + */ +static int bee_lock(void) +{ + int val; + + val = readl(BEE_BASE_ADDR + GPR0); + val |= (GPR0_CTRL_CLK_EN_LOCK | GPR0_CTRL_SFTRST_N_LOCK | + GPR0_CTRL_AES_MODE_LOCK | GPR0_SEC_LEVEL_LOCK | + GPR0_AES_KEY_SEL_LOCK | GPR0_BEE_ENABLE_LOCK); + writel(val, BEE_BASE_ADDR + GPR0); + + return 0; +} + +/* Only check bee enable lock is enough */ +static int bee_locked(void) +{ + int val; + + val = readl(BEE_BASE_ADDR + GPR0); + + return val & GPR0_BEE_ENABLE_LOCK ? 1 : 0; +} + +int bee_init(struct bee_parameters *p) +{ + int i; + union key_soft *key = &key_bad; + u32 value; + + if (bee_locked()) { + printf("BEE already enabled and locked.\n"); + return CMD_RET_FAILURE; + } + + /* CLKGATE, SFTRST */ + writel(GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N, BEE_BASE_ADDR + GPR0); + /* OFFSET_ADDR0 */ + writel(p->start1 >> 16, BEE_BASE_ADDR + GPR1); + /* + * OFFSET_ADDR1 + * Default protect IRAM region, if what you want to protect + * bigger that 512M which is the max size that one AES region + * can protect, we need AES region 1 to cover. + */ + writel(p->start2 >> 16, BEE_BASE_ADDR + GPR2); + + if (p->key_method == SOFT_KEY) { + for (i = 0; i < 16; i++) + key->s_key[i] = hw_get_random_byte(); + /* AES 128 key from software */ + /* aes0_key0_w0 */ + writel(key->b_key[0], BEE_BASE_ADDR + GPR3); + /* aes0_key0_w1 */ + writel(key->b_key[1], BEE_BASE_ADDR + GPR4); + /* aes0_key0_w2 */ + writel(key->b_key[2], BEE_BASE_ADDR + GPR5); + /* aes0_key0_w3 */ + writel(key->b_key[3], BEE_BASE_ADDR + GPR6); + } + + if (p->mode == ECB_MODE) { + value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | + GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SNVS | + GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_ECB; + if (p->key_method == SOFT_KEY) + value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | + GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SOFT | + GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_ECB; + writel(value, BEE_BASE_ADDR + GPR0); + } else { + for (i = 0; i < 16; i++) + key->s_key[i] = hw_get_random_byte(); + /* aes_key1_w0 */ + writel(key->b_key[0], BEE_BASE_ADDR + GPR8); + /* aes_key1_w1 */ + writel(key->b_key[1], BEE_BASE_ADDR + GPR9); + /* aes_key1_w2 */ + writel(key->b_key[2], BEE_BASE_ADDR + GPR10); + /* aes_key1_w3 */ + writel(key->b_key[3], BEE_BASE_ADDR + GPR11); + + value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | + GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SNVS | + GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_CTR; + if (p->key_method == SOFT_KEY) + value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | + GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SOFT | + GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_CTR; + writel(value, BEE_BASE_ADDR + GPR0); + } + + bee_lock(); + + printf("BEE is settings as: %s mode, %s %d key\n", + (p->mode == ECB_MODE) ? "ECB" : "CTR", + (p->key_method == SOFT_KEY) ? "SOFT" : "SNVS HW", + (p->mode == ECB_MODE) ? 128 : 256); + + return CMD_RET_SUCCESS; +} + +int bee_test(struct bee_parameters *p, int region) +{ + u32 result = 0, range, address; + int i, val; + /* + * Test instruction running in AES Region: + * int test(void) + * { + * return 0x55aa55aa; + * } + * Assemble: + * 0xe59f0000: ldr r0, [pc] + * 0xe12fff1e: bx lr + * 0x55aa55aa: 0x55aa55aa + */ + u32 inst[3] = {0xe59f0000, 0xe12fff1e, 0x55aa55aa}; + + /* Cache enabled? */ + if ((get_cr() & (CR_I | CR_C)) != (CR_I | CR_C)) { + printf("Enable dcache and icache first!\n"); + return CMD_RET_FAILURE; + } + + printf("Test Region %d\nBegin Data test: Writing... ", region); + + range = (region == 0) ? p->size1 : p->size2; + address = (region == 0) ? AES_REGION0_ADDR : AES_REGION1_ADDR; + for (i = 0; i < range; i = i + 4) + writel(i, address + i); + + printf("Finshed Write!\n"); + + flush_dcache_range(address, address + range); + + printf("Reading... "); + for (i = 0; i < range; i = i + 4) { + val = readl(address + i); + if (val != i) + result++; + } + printf("Finshed Read!\n"); + + if (result > 0) + printf("BEE Data Test check Failed!\n"); + else + printf("BEE Data Test Check Passed!\n"); + + for (i = 0; i < ARRAY_SIZE(inst); i++) + writel(inst[i], address + (i * 4)); + + flush_dcache_range(address, address + sizeof(inst)); + + val = ((int (*)(void))address)(); + + printf("\nBee Instruction test, Program:\n" + "int test(void)\n" + "{\n" + " return 0x55aa55aa;\n" + "}\n" + "Assemble:\n" + "0xe59f0000: ldr r0, [pc]\n" + "0xe12fff1e: bx lr\n" + "0x55aa55aa: 0x55aa55aa\n" + "Runnint at 0x%x\n", address); + if (val == 0x55aa55aa) + printf("Bee Instruction Test Passed!\n"); + else + printf("Bee Instruction Test Failed!\n"); + + return CMD_RET_SUCCESS; +} + +static int region_valid(u32 start, u32 size) +{ + if ((start < PHYS_SDRAM) || (start >= (start + size - 1)) || + (start >= (PHYS_SDRAM + PHYS_SDRAM_SIZE - 1))) { + printf("Invalid start 0x%x, size 0x%x\n", start, size); + return -EINVAL; + } + + if (size > SZ_512M) { + printf("The region size exceeds SZ_512M\n"); + return -EINVAL; + } + + if ((start & 0xFFFF) && (size & 0xFFFF)) { + printf("start or size not 64KB aligned!\n"); + return -EINVAL; + } + + /* 128K for U-Boot Stack */ + if ((start + size - 1) >= (gd->start_addr_sp - SZ_128K)) { + printf("Overlap with uboot execution environment!\n" + "Decrease size or start\n"); + return -EINVAL; + } + + return 0; +} + +static int do_bee_init(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 start, size; + int ret; + struct bee_parameters *p = ¶ + +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + enum dcache_option option = DCACHE_WRITETHROUGH; +#else + enum dcache_option option = DCACHE_WRITEBACK; +#endif + + if (argc > 5) + return CMD_RET_USAGE; + +#ifdef CONFIG_MX6 + if (check_module_fused(MX6_MODULE_BEE)) { + printf("BEE is fused, disable it!\n"); + return CMD_RET_FAILURE; + } +#endif + + /* Cache enabled? */ + if ((get_cr() & (CR_I | CR_C)) != (CR_I | CR_C)) { + /* + * Here we need icache and dcache both enabled, because + * we may take the protected region for instruction and + * data usage. And icache and dcache both enabled are + * better for performance. + */ + printf("Please enable dcache and icache first!\n"); + return CMD_RET_FAILURE; + } + + p->key_method = SOFT_KEY; + p->mode = ECB_MODE; + p->start1 = PHYS_SDRAM; + p->size1 = SZ_512M; + p->start2 = IRAM_BASE_ADDR; + p->size2 = IRAM_SIZE; + + if (argc == 2) { + p->key_method = (int)simple_strtoul(argv[1], NULL, 16); + p->mode = ECB_MODE; + p->start1 = PHYS_SDRAM; + p->size1 = SZ_512M; + } else if (argc == 3) { + p->key_method = (int)simple_strtoul(argv[1], NULL, 16); + p->mode = (int)simple_strtoul(argv[2], NULL, 10); + p->start1 = PHYS_SDRAM; + p->size1 = SZ_512M; + } else if ((argc == 4) || (argc == 5)) { + p->key_method = (int)simple_strtoul(argv[1], NULL, 16); + p->mode = (int)simple_strtoul(argv[2], NULL, 10); + start = (u32)simple_strtoul(argv[3], NULL, 16); + /* Default size that AES Region0 can protected */ + size = SZ_512M; + if (argc == 5) + size = (u32)simple_strtoul(argv[4], NULL, 16); + p->start1 = start; + p->size1 = size; + } + + if ((p->key_method != SOFT_KEY) && (p->key_method != SNVS_KEY)) + return CMD_RET_USAGE; + + if ((p->mode != ECB_MODE) && (p->mode != CTR_MODE)) + return CMD_RET_USAGE; + + /* + * No need to check region valid for IRAM, since it is fixed. + * Only check DRAM region here. + */ + if (region_valid(p->start1, p->size1)) + return CMD_RET_FAILURE; + + ret = bee_init(p); + if (ret) + return CMD_RET_FAILURE; + + /* + * Set DCACHE OFF to AES REGION0 and AES REGION1 first + * to avoid possible unexcepted cache settings. + */ + mmu_set_region_dcache_behaviour(AES_REGION0_ADDR, SZ_1G, DCACHE_OFF); + + mmu_set_region_dcache_behaviour(AES_REGION0_ADDR, p->size1, option); + + mmu_set_region_dcache_behaviour(AES_REGION1_ADDR, p->size2, option); + + printf("Access Region 0x%x - 0x%x to protect 0x%x - 0x%x\n" + "Do not directly access 0x%x - 0x%x\n" + "Access Region 0x%x - 0x%x to protect 0x%x - 0x%x\n" + "Do not directly access 0x%x - 0x%x\n", + AES_REGION0_ADDR, AES_REGION0_ADDR + p->size1 - 1, + p->start1, p->start1 + p->size1 - 1, + p->start1, p->start1 + p->size1 - 1, + AES_REGION1_ADDR, AES_REGION1_ADDR + p->size2 - 1, + p->start2, p->start2 + p->size2 - 1, + p->start2, p->start2 + p->size2 - 1); + + bee_inited = 1; + + return CMD_RET_SUCCESS; +} + +static int do_bee_test(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ret; + int region; + + if (bee_inited == 0) { + printf("Bee not initialized, run bee init first!\n"); + return CMD_RET_FAILURE; + } + if (argc > 2) + return CMD_RET_USAGE; + + region = 0; + if (argc == 2) + region = (int)simple_strtoul(argv[1], NULL, 16); + /* Only two regions are supported, 0 and 1 */ + if (region >= 2) + return CMD_RET_USAGE; + + ret = bee_test(¶, region); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static cmd_tbl_t cmd_bmp_sub[] = { + U_BOOT_CMD_MKENT(init, 5, 0, do_bee_init, "", ""), + U_BOOT_CMD_MKENT(test, 2, 0, do_bee_test, "", ""), +}; + +static int do_bee_ops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *c; + + c = find_cmd_tbl(argv[1], &cmd_bmp_sub[0], ARRAY_SIZE(cmd_bmp_sub)); + + /* Drop off the 'bee' command argument */ + argc--; + argv++; + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + bee, CONFIG_SYS_MAXARGS, 1, do_bee_ops, + "BEE function test", + "init [key] [mode] [start] [size] - BEE block initial\n" + " key: 0 | 1, 0 means software key, 1 means SNVS random key\n" + " mode: 0 | 1, 0 means ECB mode, 1 means CTR mode\n" + " start: start address that you want to protect\n" + " size: The size of the area that you want to protect\n" + " start and end(start + size) addr both should be 64KB aligned.\n" + "\n" + " After initialization, the mapping:\n" + " 1. [0x10000000 - (0x10000000 + size - 1)] <--->\n" + " [start - (start + size - 1)]\n" + " Here [start - (start + size -1)] is fixed mapping to\n" + " [0x10000000 - (0x10000000 + size - 1)], whatever start is.\n" + " 2. [0x30000000 - (0x30000000 + IRAM_SIZE - 1)] <--->\n" + " [IRAM_BASE_ADDR - (IRAM_BASE_ADDR + IRAM_SIZE - 1)]\n" + "\n" + " Note: Here we only use AES region 0 to protect the DRAM\n" + " area that you specified, max size SZ_512M.\n" + " AES region 1 is used to protect IRAM area.\n" + " Example:\n" + " 1. bee init 1 1 0xa0000000 0x10000\n" + " Access 0x10000000 - 0x10010000 to protect 0xa0000000 - 0xa0010000\n" + " 2. bee init 1 1 0x80000000 0x20000\n" + " Access 0x10000000 - 0x10020000 to protect 0x80000000 - 0x80020000\n" + "\n" + " Default configuration if only `bee init` without any args:\n" + " 1. software key\n" + " 2. ECB mode\n" + " 3. Address protected:\n" + " Remapped Region0: PHYS_SDRAM - PHYS_SDRAM + SZ_512M\n" + " Remapped Region1: IRAM_BASE_ADDR - IRAM_BASE_ADDR + IRAM_SIZE\n" + " 4. Default Mapping for 6UL:\n" + " [0x10000000 - 0x2FFFFFFF] <-> [0x80000000 - 0x9FFFFFFF]\n" + " [0x30000000 - 0x3001FFFF] <-> [0x00900000 - 0x0091FFFF]\n" + "\n" + "bee test [region] - BEE function test\n" + " region: 0 | 1, 0 means region0, 1 means regions1\n" +); + diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 71a9e6bca0f..cbb0c20db43 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -59,6 +60,19 @@ void setup_gpmi_io_clk(u32 cfg) cfg); setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); +#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) + /* + * config gpmi and bch clock to 100 MHz + * bch/gpmi select PLL2 PFD2 400M + * 100M = 400M / 4 + */ + clrbits_le32(&imx_ccm->cscmr1, + MXC_CCM_CSCMR1_BCH_CLK_SEL | + MXC_CCM_CSCMR1_GPMI_CLK_SEL); + clrsetbits_le32(&imx_ccm->cscdr1, + MXC_CCM_CSCDR1_BCH_PODF_MASK | + MXC_CCM_CSCDR1_GPMI_PODF_MASK, + cfg); #else clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); @@ -850,6 +864,65 @@ int enable_lcdif_clock(u32 base_addr, bool enable) return 0; } + +int enable_lvds_bridge(u32 lcd_base_addr) +{ + u32 reg = 0; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + if (is_cpu_type(MXC_CPU_MX6SX)) { + if ((lcd_base_addr != LCDIF1_BASE_ADDR) && + (lcd_base_addr != LCDIF2_BASE_ADDR)) { + puts("Wrong LCD interface!\n"); + return -EINVAL; + } + } else { + debug("This chip not support lvds bridge!\n"); + return 0; + } + + /* Turn on LDB DI0 clocks */ + reg = readl(&imx_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &imx_ccm->CCGR3); + + /* set LDB DI0 clk select to 011 PLL2 PFD3 200M*/ + reg = readl(&imx_ccm->cs2cdr); + reg &= ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK; + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET); + writel(reg, &imx_ccm->cs2cdr); + + reg = readl(&imx_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &imx_ccm->cscmr2); + + /* set LDB DI0 clock for LCDIF PIX clock */ + reg = readl(&imx_ccm->cscdr2); + if (lcd_base_addr == LCDIF1_BASE_ADDR) { + reg &= ~MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK; + reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET); + } else { + reg &= ~MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK; + reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET); + } + writel(reg, &imx_ccm->cscdr2); + + reg = IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[6]); + + reg = readl(&iomux->gpr[5]); + if (lcd_base_addr == LCDIF1_BASE_ADDR) + reg &= ~0x8; /* MUX LVDS to LCDIF1 */ + else + reg |= 0x8; /* MUX LVDS to LCDIF2 */ + writel(reg, &iomux->gpr[5]); + + return 0; +} + #endif #ifdef CONFIG_FSL_QSPI @@ -902,6 +975,18 @@ void enable_qspi_clk(int qspi_num) } #endif +#if defined(CONFIG_VIDEO_GIS) +void mxs_set_vadcclk() +{ + u32 reg = 0; + + reg = readl(&imx_ccm->cscmr2); + reg &= ~MXC_CCM_CSCMR2_VID_CLK_SEL_MASK; + reg |= 0x19 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET; + writel(reg, &imx_ccm->cscmr2); +} +#endif + #ifdef CONFIG_FEC_MXC int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) { @@ -1095,6 +1180,15 @@ void disable_sata_clock(void) #endif #ifdef CONFIG_PCIE_IMX +static void ungate_disp_axi_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Enable display axi clock. */ + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_DISP_AXI_MASK); +} + static void ungate_pcie_clock(void) { struct mxc_ccm_reg *const imx_ccm = @@ -1142,14 +1236,22 @@ int enable_pcie_clock(void) /* PCIe reference clock sourced from AXI. */ clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); + if (!is_mx6sx()) { /* Party time! Ungate the clock to the PCIe. */ #ifdef CONFIG_SATA - ungate_sata_clock(); + ungate_sata_clock(); #endif - ungate_pcie_clock(); + ungate_pcie_clock(); + + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | + BM_ANADIG_PLL_ENET_ENABLE_PCIE); + } else { + /* Party time! Ungate the clock to the PCIe. */ + ungate_disp_axi_clock(); + ungate_pcie_clock(); - return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | - BM_ANADIG_PLL_ENET_ENABLE_PCIE); + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_PCIE); + } } #endif @@ -1313,6 +1415,30 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #ifndef CONFIG_MX6SX +static void pre_misc_setting(void) +{ + /* Bypass IPU1 QoS generator */ + writel(0x00000002, 0x00bb048c); + /* Bypass IPU2 QoS generator */ + writel(0x00000002, 0x00bb050c); + /* Bandwidth THR for of PRE0 */ + writel(0x00000200, 0x00bb0690); + /* Bandwidth THR for of PRE1 */ + writel(0x00000200, 0x00bb0710); + /* Bandwidth THR for of PRE2 */ + writel(0x00000200, 0x00bb0790); + /* Bandwidth THR for of PRE3 */ + writel(0x00000200, 0x00bb0810); + /* Saturation THR for of PRE0 */ + writel(0x00000010, 0x00bb0694); + /* Saturation THR for of PRE1 */ + writel(0x00000010, 0x00bb0714); + /* Saturation THR for of PRE2 */ + writel(0x00000010, 0x00bb0794); + /* Saturation THR for of PRE */ + writel(0x00000010, 0x00bb0814); +} + void enable_ipu_clock(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -1324,11 +1450,18 @@ void enable_ipu_clock(void) if (is_mx6dqp()) { setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); + + /* + * Since CONFIG_VIDEO_IPUV3 is always set in mx6sabre_common.h and + * this misc setting is a must for mx6qp, this position is ok + * to do such settings. + */ + pre_misc_setting(); } } #endif -#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \ +#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL) || \ defined(CONFIG_MX6S) static void disable_ldb_di_clock_sources(void) { @@ -1478,6 +1611,38 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk) } #endif + +#if defined(CONFIG_MXC_EPDC) +#if defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) +void enable_epdc_clock(void) +{ + u32 reg = 0; + + /* disable the clock gate first */ + clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK); + + /* PLL3_PFD2 */ + reg = readl(&imx_ccm->chsccdr); + reg &= ~MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK; + reg |= 5 << MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET; + writel(reg, &imx_ccm->chsccdr); + + reg = readl(&imx_ccm->chsccdr); + reg &= ~MXC_CCM_CHSCCDR_EPDC_PODF_MASK; + reg |= 7 << MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET; + writel(reg, &imx_ccm->chsccdr); + + reg = readl(&imx_ccm->chsccdr); + reg &= ~MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK; + reg |= 0 <chsccdr); + + /* enable the clock gate */ + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK); +} +#endif +#endif + /***************************************************/ U_BOOT_CMD( diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 43b77cfa416..1fbff6ba86d 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -730,7 +730,7 @@ void mx6sl_dram_iocfg(unsigned width, } #endif -#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) /* Configure MX6DQ mmdc iomux */ void mx6dq_dram_iocfg(unsigned width, const struct mx6dq_iomux_ddr_regs *ddr, diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c new file mode 100644 index 00000000000..88f7a9b5655 --- /dev/null +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -0,0 +1,307 @@ +/* + * (C) Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +struct fuse_entry_desc { + enum fuse_module_type module; + const char *node_path; + u32 fuse_word_offset; + u32 fuse_bit_offset; + u32 status; +}; + +static struct fuse_entry_desc mx6_fuse_descs[] = { +#if defined(CONFIG_MX6ULL) + {MX6_MODULE_TSC, "/soc/aips-bus@02000000/tsc@02040000", 0x430, 22}, + {MX6_MODULE_ADC2, "/soc/aips-bus@02100000/adc@0219c000", 0x430, 23}, + {MX6_MODULE_EPDC, "/soc/aips-bus@02200000/epdc@0228c000", 0x430, 24}, + {MX6_MODULE_ESAI, "/soc/aips-bus@02000000/spba-bus@02000000/esai@02024000", 0x430, 25}, + {MX6_MODULE_FLEXCAN1, "/soc/aips-bus@02000000/can@02090000", 0x430, 26}, + {MX6_MODULE_FLEXCAN2, "/soc/aips-bus@02000000/can@02094000", 0x430, 27}, + {MX6_MODULE_SPDIF, "/soc/aips-bus@02000000/spba-bus@02000000/spdif@02004000", 0x440, 2}, + {MX6_MODULE_EIM, "/soc/aips-bus@02100000/weim@021b8000", 0x440, 3}, + {MX6_MODULE_SD1, "/soc/aips-bus@02100000/usdhc@02190000", 0x440, 4}, + {MX6_MODULE_SD2, "/soc/aips-bus@02100000/usdhc@02194000", 0x440, 5}, + {MX6_MODULE_QSPI1, "/soc/aips-bus@02100000/qspi@021e0000", 0x440, 6}, + {MX6_MODULE_GPMI, "/soc/gpmi-nand@01806000", 0x440, 7}, + {MX6_MODULE_APBHDMA, "/soc/dma-apbh@01804000", 0x440, 7}, + {MX6_MODULE_LCDIF, "/soc/aips-bus@02100000/lcdif@021c8000", 0x440, 8}, + {MX6_MODULE_PXP, "/soc/aips-bus@02100000/pxp@021cc000", 0x440, 9}, + {MX6_MODULE_CSI, "/soc/aips-bus@02100000/csi@021c4000", 0x440, 10}, + {MX6_MODULE_ADC1, "/soc/aips-bus@02100000/adc@02198000", 0x440, 11}, + {MX6_MODULE_ENET1, "/soc/aips-bus@02100000/ethernet@02188000", 0x440, 12}, + {MX6_MODULE_ENET2, "/soc/aips-bus@02000000/ethernet@020b4000", 0x440, 13}, + {MX6_MODULE_DCP, "/soc/aips-bus@02200000/dcp@02280000", 0x440, 14}, + {MX6_MODULE_USB_OTG2, "/soc/aips-bus@02100000/usb@02184200", 0x440, 15}, + {MX6_MODULE_SAI2, "/soc/aips-bus@02000000/spba-bus@02000000/sai@0202c000", 0x440, 24}, + {MX6_MODULE_SAI3, "/soc/aips-bus@02000000/spba-bus@02000000/sai@02030000", 0x440, 24}, + {MX6_MODULE_DCP_CRYPTO, "/soc/aips-bus@02200000/dcp@02280000", 0x440, 25}, + {MX6_MODULE_UART5, "/soc/aips-bus@02100000/serial@021f4000", 0x440, 26}, + {MX6_MODULE_UART6, "/soc/aips-bus@02100000/serial@021fc000", 0x440, 26}, + {MX6_MODULE_UART7, "/soc/aips-bus@02000000/spba-bus@02000000/serial@02018000", 0x440, 26}, + {MX6_MODULE_UART8, "/soc/aaips-bus@02200000/serial@02288000", 0x440, 26}, + {MX6_MODULE_PWM5, "/soc/aips-bus@02000000/pwm@020f0000", 0x440, 27}, + {MX6_MODULE_PWM6, "/soc/aips-bus@02000000/pwm@020f4000", 0x440, 27}, + {MX6_MODULE_PWM7, "/soc/aips-bus@02000000/pwm@020f8000", 0x440, 27}, + {MX6_MODULE_PWM8, "/soc/aips-bus@02000000/pwm@020fc000", 0x440, 27}, + {MX6_MODULE_ECSPI3, "/soc/aips-bus@02000000/spba-bus@02000000/ecspi@02010000", 0x440, 28}, + {MX6_MODULE_ECSPI4, "/soc/aips-bus@02000000/spba-bus@02000000/ecspi@02014000", 0x440, 28}, + {MX6_MODULE_I2C3, "/soc/aips-bus@02100000/i2c@021a8000", 0x440, 29}, + {MX6_MODULE_I2C4, "/soc/aips-bus@02100000/i2c@021f8000", 0x440, 29}, + {MX6_MODULE_GPT2, "/soc/aips-bus@02000000/gpt@020e8000", 0x440, 30}, + {MX6_MODULE_EPIT2, "/soc/aips-bus@02000000/epit@020d4000", 0x440, 31}, +#elif defined(CONFIG_MX6UL) + {MX6_MODULE_TSC, "/soc/aips-bus@02000000/tsc@02040000", 0x430, 22}, + {MX6_MODULE_ADC2, "/soc/aips-bus@02100000/adc@0219c000", 0x430, 23}, + {MX6_MODULE_SIM1, "/soc/aips-bus@02100000/sim@0218c000", 0x430, 24}, + {MX6_MODULE_SIM2, "/soc/aips-bus@02100000/sim@021b4000", 0x430, 25}, + {MX6_MODULE_FLEXCAN1, "/soc/aips-bus@02000000/can@02090000", 0x430, 26}, + {MX6_MODULE_FLEXCAN2, "/soc/aips-bus@02000000/can@02094000", 0x430, 27}, + {MX6_MODULE_SPDIF, "/soc/aips-bus@02000000/spba-bus@02000000/spdif@02004000", 0x440, 2}, + {MX6_MODULE_EIM, "/soc/aips-bus@02100000/weim@021b8000", 0x440, 3}, + {MX6_MODULE_SD1, "/soc/aips-bus@02100000/usdhc@02190000", 0x440, 4}, + {MX6_MODULE_SD2, "/soc/aips-bus@02100000/usdhc@02194000", 0x440, 5}, + {MX6_MODULE_QSPI1, "/soc/aips-bus@02100000/qspi@021e0000", 0x440, 6}, + {MX6_MODULE_GPMI, "/soc/gpmi-nand@01806000", 0x440, 7}, + {MX6_MODULE_APBHDMA, "/soc/dma-apbh@01804000", 0x440, 7}, + {MX6_MODULE_LCDIF, "/soc/aips-bus@02100000/lcdif@021c8000", 0x440, 8}, + {MX6_MODULE_PXP, "/soc/aips-bus@02100000/pxp@021cc000", 0x440, 9}, + {MX6_MODULE_CSI, "/soc/aips-bus@02100000/csi@021c4000", 0x440, 10}, + {MX6_MODULE_ADC1, "/soc/aips-bus@02100000/adc@02198000", 0x440, 11}, + {MX6_MODULE_ENET1, "/soc/aips-bus@02100000/ethernet@02188000", 0x440, 12}, + {MX6_MODULE_ENET2, "/soc/aips-bus@02000000/ethernet@020b4000", 0x440, 13}, + {MX6_MODULE_CAAM, "/soc/aips-bus@02100000/caam@2140000", 0x440, 14}, + {MX6_MODULE_USB_OTG2, "/soc/aips-bus@02100000/usb@02184200", 0x440, 15}, + {MX6_MODULE_SAI2, "/soc/aips-bus@02000000/spba-bus@02000000/sai@0202c000", 0x440, 24}, + {MX6_MODULE_SAI3, "/soc/aips-bus@02000000/spba-bus@02000000/sai@02030000", 0x440, 24}, + {MX6_MODULE_BEE, "/soc/aips-bus@02000000/bee@02044000", 0x440, 25}, + {MX6_MODULE_UART5, "/soc/aips-bus@02100000/serial@021f4000", 0x440, 26}, + {MX6_MODULE_UART6, "/soc/aips-bus@02100000/serial@021fc000", 0x440, 26}, + {MX6_MODULE_UART7, "/soc/aips-bus@02000000/spba-bus@02000000/serial@02018000", 0x440, 26}, + {MX6_MODULE_UART8, "/soc/aips-bus@02000000/spba-bus@02000000/serial@02024000", 0x440, 26}, + {MX6_MODULE_PWM5, "/soc/aips-bus@02000000/pwm@020f0000", 0x440, 27}, + {MX6_MODULE_PWM6, "/soc/aips-bus@02000000/pwm@020f4000", 0x440, 27}, + {MX6_MODULE_PWM7, "/soc/aips-bus@02000000/pwm@020f8000", 0x440, 27}, + {MX6_MODULE_PWM8, "/soc/aips-bus@02000000/pwm@020fc000", 0x440, 27}, + {MX6_MODULE_ECSPI3, "/soc/aips-bus@02000000/spba-bus@02000000/ecspi@02010000", 0x440, 28}, + {MX6_MODULE_ECSPI4, "/soc/aips-bus@02000000/spba-bus@02000000/ecspi@02014000", 0x440, 28}, + {MX6_MODULE_I2C3, "/soc/aips-bus@02100000/i2c@021a8000", 0x440, 29}, + {MX6_MODULE_I2C4, "/soc/aips-bus@02100000/i2c@021f8000", 0x440, 29}, + {MX6_MODULE_GPT2, "/soc/aips-bus@02000000/gpt@020e8000", 0x440, 30}, + {MX6_MODULE_EPIT2, "/soc/aips-bus@02000000/epit@020d4000", 0x440, 31}, +#endif +}; + +u32 check_module_fused(enum fuse_module_type module) +{ + u32 i, reg; + for (i = 0; i < ARRAY_SIZE(mx6_fuse_descs); i++) { + if (mx6_fuse_descs[i].module == module) { + reg = readl(OCOTP_BASE_ADDR + mx6_fuse_descs[i].fuse_word_offset); + if (reg & (1 << mx6_fuse_descs[i].fuse_bit_offset)) + return 1; /* disabled */ + else + return 0; /* enabled */ + } + } + + return 0; /* Not has a fuse, always enabled */ +} + +#ifdef DEBUG +void print_fuse_status() +{ + u32 i, reg; + + for (i = 0; i < ARRAY_SIZE(mx6_fuse_descs); i++) { + reg = readl(OCOTP_BASE_ADDR + mx6_fuse_descs[i].fuse_word_offset); + if (reg & (1 << mx6_fuse_descs[i].fuse_bit_offset)) + printf("%s, disabled\n", mx6_fuse_descs[i].node_path); + } +} + +void simulate_fuse() +{ + u32 i, reg; + + for (i = 0; i < ARRAY_SIZE(mx6_fuse_descs); i++) { + if (MX6_MODULE_SD2 == mx6_fuse_descs[i].module) + continue; + + reg = readl(OCOTP_BASE_ADDR + mx6_fuse_descs[i].fuse_word_offset); + reg |= (1 << mx6_fuse_descs[i].fuse_bit_offset); + writel(reg, OCOTP_BASE_ADDR + mx6_fuse_descs[i].fuse_word_offset); + } +} +#endif + +#ifdef CONFIG_OF_SYSTEM_SETUP +int ft_system_setup(void *blob, bd_t *bd) +{ + u32 i, reg; + const char *status = "disabled"; + int rc; + + for (i = 0; i < ARRAY_SIZE(mx6_fuse_descs); i++) { + reg = readl(OCOTP_BASE_ADDR + mx6_fuse_descs[i].fuse_word_offset); + if (reg & (1 << mx6_fuse_descs[i].fuse_bit_offset)) { + + int nodeoff = fdt_path_offset(blob, mx6_fuse_descs[i].node_path); + if (nodeoff < 0) + continue; /* Not found, skip it */ +add_status: + rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1); + if (rc) { + if (rc == -FDT_ERR_NOSPACE) { + rc = fdt_increase_size(blob, 512); + if (!rc) + goto add_status; + } + printf("Unable to update property %s:%s, err=%s\n", + mx6_fuse_descs[i].node_path, "status", fdt_strerror(rc)); + } else { + printf("Modify %s:%s disabled\n", + mx6_fuse_descs[i].node_path, "status"); + } + } + } + + printf("ft_system_setup for mx6\n"); + + return 0; +} +#endif + +u32 mx6_esdhc_fused(u32 base_addr) +{ + switch (base_addr) { + case USDHC1_BASE_ADDR: + return check_module_fused(MX6_MODULE_SD1); + case USDHC2_BASE_ADDR: + return check_module_fused(MX6_MODULE_SD2); +#ifdef USDHC3_BASE_ADDR + case USDHC3_BASE_ADDR: + return check_module_fused(MX6_MODULE_SD3); +#endif +#ifdef USDHC4_BASE_ADDR + case USDHC4_BASE_ADDR: + return check_module_fused(MX6_MODULE_SD4); +#endif + default: + return 0; + } +} + +u32 mx6_ecspi_fused(u32 base_addr) +{ + switch (base_addr) { + case ECSPI1_BASE_ADDR: + return check_module_fused(MX6_MODULE_ECSPI1); + case ECSPI2_BASE_ADDR: + return check_module_fused(MX6_MODULE_ECSPI2); + case ECSPI3_BASE_ADDR: + return check_module_fused(MX6_MODULE_ECSPI3); + case ECSPI4_BASE_ADDR: + return check_module_fused(MX6_MODULE_ECSPI4); +#ifdef ECSPI5_BASE_ADDR + case ECSPI5_BASE_ADDR: + return check_module_fused(MX6_MODULE_ECSPI5); +#endif + default: + return 0; + } +} + +u32 mx6_uart_fused(u32 base_addr) +{ + switch (base_addr) { + case UART1_BASE: + return check_module_fused(MX6_MODULE_UART1); + case UART2_BASE: + return check_module_fused(MX6_MODULE_UART2); + case UART3_BASE: + return check_module_fused(MX6_MODULE_UART3); + case UART4_BASE: + return check_module_fused(MX6_MODULE_UART4); + case UART5_BASE: + return check_module_fused(MX6_MODULE_UART5); + case MX6UL_UART6_BASE_ADDR: + case MX6SX_UART6_BASE_ADDR: + return check_module_fused(MX6_MODULE_UART6); +#ifdef UART7_IPS_BASE_ADDR + case UART7_IPS_BASE_ADDR: + return check_module_fused(MX6_MODULE_UART7); +#endif +#ifdef UART8_IPS_BASE_ADDR + case UART8_IPS_BASE_ADDR: + return check_module_fused(MX6_MODULE_UART8); +#endif + } + + return 0; +} + +u32 mx6_usb_fused(u32 base_addr) +{ + int i = (base_addr - USB_BASE_ADDR) / 0x200; + return check_module_fused(MX6_MODULE_USB_OTG1 + i); +} + +u32 mx6_qspi_fused(u32 base_addr) +{ + switch (base_addr) { +#ifdef QSPI1_BASE_ADDR + case QSPI1_BASE_ADDR: + return check_module_fused(MX6_MODULE_QSPI1); +#endif + +#ifdef QSPI2_BASE_ADDR + case QSPI2_BASE_ADDR: + return check_module_fused(MX6_MODULE_QSPI2); +#endif + default: + return 0; + } +} + +u32 mx6_i2c_fused(u32 base_addr) +{ + switch (base_addr) { + case I2C1_BASE_ADDR: + return check_module_fused(MX6_MODULE_I2C1); + case I2C2_BASE_ADDR: + return check_module_fused(MX6_MODULE_I2C2); + case I2C3_BASE_ADDR: + return check_module_fused(MX6_MODULE_I2C3); +#ifdef I2C4_BASE_ADDR + case I2C4_BASE_ADDR: + return check_module_fused(MX6_MODULE_I2C4); +#endif + } + + return 0; +} + +u32 mx6_enet_fused(u32 base_addr) +{ + switch (base_addr) { + case ENET_BASE_ADDR: + return check_module_fused(MX6_MODULE_ENET1); +#ifdef ENET2_BASE_ADDR + case ENET2_BASE_ADDR: + return check_module_fused(MX6_MODULE_ENET2); +#endif + default: + return 0; + } +} diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 9b3d8f69b26..840752bc21c 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -3,6 +3,7 @@ * Sascha Hauer, Pengutronix * * (C) Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -23,6 +24,12 @@ #include #include #include +#include +#ifdef CONFIG_IMX_SEC_INIT +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; enum ldo_reg { LDO_ARM, @@ -86,6 +93,10 @@ u32 get_cpu_rev(void) type = MXC_CPU_MX6D; } + if (type == MXC_CPU_MX6ULL) { + if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6)) + type = MXC_CPU_MX6ULZ; + } } major = ((reg >> 8) & 0xff); if ((major >= 1) && @@ -96,6 +107,11 @@ u32 get_cpu_rev(void) type = MXC_CPU_MX6DP; } reg &= 0xff; /* mx6 silicon revision */ + + /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/ + if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5)) + reg = 0x3; + return (type << 12) | (reg + (0x10 * (major + 1))); } @@ -225,6 +241,35 @@ u32 __weak get_board_rev(void) } #endif +#ifdef CONFIG_IMX_TRUSTY_OS +#ifdef CONFIG_MX6UL +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + return; +} + +void smp_waitloop(unsigned previous_address) +{ + return; +} +#endif +#endif + +static void init_csu(void) +{ +#ifdef CONFIG_ARMV7_NONSEC + int i; + u32 csu = CSU_BASE_ADDR; + /* + * This is to allow device can be accessed in non-secure world. + * All imx6 chips CSU have 40 Config security level registers. + */ + for (i = 0; i < 40; i ++) { + *((u32 *)csu + i) = 0xffffffff; + } +#endif +} + static void clear_ldo_ramp(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; @@ -366,12 +411,162 @@ static void init_bandgap(void) } } +static void set_preclk_from_osc(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&mxc_ccm->cscmr1); + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cscmr1); +} + +#ifdef CONFIG_MX6SX +void vadc_power_up(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + u32 val; + + /* csi0 */ + val = readl(&iomux->gpr[5]); + val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, + val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD; + writel(val, &iomux->gpr[5]); + + /* Power on vadc analog + * Power down vadc ext power */ + val = readl(GPC_BASE_ADDR + 0); + val &= ~0x60000; + writel(val, GPC_BASE_ADDR + 0); + + /* software reset afe */ + val = readl(&iomux->gpr[1]); + writel(val | 0x80000, &iomux->gpr[1]); + + udelay(10*1000); + + /* Release reset bit */ + writel(val & ~0x80000, &iomux->gpr[1]); + + /* Power on vadc ext power */ + val = readl(GPC_BASE_ADDR + 0); + val |= 0x40000; + writel(val, GPC_BASE_ADDR + 0); +} + +void vadc_power_down(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + u32 val; + + /* Power down vadc ext power + * Power off vadc analog */ + val = readl(GPC_BASE_ADDR + 0); + val &= ~0x40000; + val |= 0x20000; + writel(val, GPC_BASE_ADDR + 0); + + /* clean csi0 connect to vadc */ + val = readl(&iomux->gpr[5]); + val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, + writel(val, &iomux->gpr[5]); +} + +void pcie_power_up(void) +{ + set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */ +} + +void pcie_power_off(void) +{ + set_ldo_voltage(LDO_PU, 0); /* Set VDDPU to 1.1V */ +} +#endif + +static void set_uart_from_osc(void) +{ + u32 reg; + + /* set uart clk to OSC */ + reg = readl(CCM_BASE_ADDR + 0x24); + reg |= MXC_CCM_CSCDR1_UART_CLK_SEL; + writel(reg, CCM_BASE_ADDR + 0x24); +} + +static void imx_set_vddpu_power_down(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + u32 val; + + /* need to power down xPU in GPC before turn off PU LDO */ + val = readl(GPC_BASE_ADDR + 0x260); + writel(val | 0x1, GPC_BASE_ADDR + 0x260); + + val = readl(GPC_BASE_ADDR + 0x0); + writel(val | 0x1, GPC_BASE_ADDR + 0x0); + while (readl(GPC_BASE_ADDR + 0x0) & 0x1) + ; + + /* disable VDDPU */ + val = 0x3e00; + writel(val, &anatop->reg_core_clr); +} + +static void imx_set_pcie_phy_power_down(void) +{ + u32 val; + + if (!is_cpu_type(MXC_CPU_MX6SX)) { + val = readl(IOMUXC_BASE_ADDR + 0x4); + val |= 0x1 << 18; + writel(val, IOMUXC_BASE_ADDR + 0x4); + } else { + val = readl(IOMUXC_GPR_BASE_ADDR + 0x30); + val |= 0x1 << 30; + writel(val, IOMUXC_GPR_BASE_ADDR + 0x30); + } +} + +bool is_usb_boot(void) +{ + if (gd->flags & GD_FLG_ARCH_IMX_USB_BOOT) + return true; + + return false; +} + int arch_cpu_init(void) { - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + if (is_usbphy_power_on()) + gd->flags |= GD_FLG_ARCH_IMX_USB_BOOT; + + if (!is_mx6sl() && !is_mx6sx() + && !is_mx6ul() && !is_mx6ull() + && !is_mx6sll()) { + /* + * imx6sl doesn't have pcie at all. + * this bit is not used by imx6sx anymore + */ + u32 val; + + /* + * There are about 0.02% percentage, random pcie link down + * when warm-reset is used. + * clear the ref_ssp_en bit16 of gpr1 to workaround it. + * then warm-reset imx6q/dl/solo again. + */ + val = readl(IOMUXC_BASE_ADDR + 0x4); + if (val & (0x1 << 16)) { + val &= ~(0x1 << 16); + writel(val, IOMUXC_BASE_ADDR + 0x4); + reset_cpu(0); + } + } init_aips(); + init_csu(); + /* Need to clear MMDC_CHx_MASK to make warm reset work. */ clear_mmdc_ch_mask(); @@ -432,21 +627,53 @@ int arch_cpu_init(void) 0x3, MX6UL_SNVS_LP_BASE_ADDR); } + if (is_mx6ull() || is_mx6ul()) { + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + if (iomux->gpr[9] & 0x1) { + /* When trust zone is enabled, + * set Region 0 attribute to allow secure and non-secure read/write permission + * Because PL301 hard code to non-secure for some masters on m_3/4/5 ports. + * Like LCDIF, PXP, CSI can't work with secure memory. + */ + + writel(0xf0000000, IP2APB_TZASC1_BASE_ADDR + 0x108); + } + } + /* Set perclk to source from OSC 24MHz */ if (is_mx6sl()) - setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK); + set_preclk_from_osc(); imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */ if (is_mx6sx()) - setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL); + set_uart_from_osc(); + + if (!is_mx6sl() && !is_mx6ul() && + !is_mx6ull() && !is_mx6sll()) + imx_set_pcie_phy_power_down(); + + if (!is_mx6dqp() && !is_mx6ul() && + !is_mx6ull() && !is_mx6sll()) + imx_set_vddpu_power_down(); init_src(); + if (is_mx6dqp()) + writel(0x80000201, 0xbb0608); + +#ifdef CONFIG_IMX_SEC_INIT + /* Secure init function such RNG */ + imx_sec_init(); +#endif + return 0; } -#ifdef CONFIG_ENV_IS_IN_MMC +#ifndef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV -1 +#endif + __weak int board_mmc_get_env_dev(int devno) { return CONFIG_SYS_MMC_ENV_DEV; @@ -468,7 +695,7 @@ static int mmc_get_boot_dev(void) bootsel = (soc_sbmr & 0x000000FF) >> 6; /* No boot from sd/mmc */ - if (bootsel != 1) + if (is_usb_boot() || bootsel != 1) return -1; /* BOOT_CFG2[3] and BOOT_CFG2[4] */ @@ -483,7 +710,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if (devno < 0) - return CONFIG_SYS_MMC_ENV_DEV; + return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); return board_mmc_get_env_dev(devno); } @@ -505,7 +732,6 @@ uint mmc_get_env_part(struct mmc *mmc) return board_mmc_get_env_part(devno); } #endif -#endif int board_postclk_init(void) { @@ -518,6 +744,19 @@ int board_postclk_init(void) return 0; } +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + serialnr->low = fuse->uid_low; + serialnr->high = fuse->uid_high; +} +#endif + #ifndef CONFIG_SPL_BUILD /* * cfg_val will be used for @@ -531,7 +770,7 @@ const struct boot_mode soc_boot_modes[] = { #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, #else - {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, #endif {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, @@ -547,6 +786,71 @@ const struct boot_mode soc_boot_modes[] = { }; #endif +enum boot_device get_boot_device(void) +{ + enum boot_device boot_dev = UNKNOWN_BOOT; + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; + uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; + uint bt_dev_port = (soc_sbmr & 0x00001800) >> 11; + + switch (bt_mem_ctl) { + case 0x0: + if (bt_mem_type) + boot_dev = ONE_NAND_BOOT; + else + boot_dev = WEIM_NOR_BOOT; + break; + case 0x2: + boot_dev = SATA_BOOT; + break; + case 0x3: + if (bt_mem_type) + boot_dev = I2C_BOOT; + else + boot_dev = SPI_NOR_BOOT; + break; + case 0x4: + case 0x5: + boot_dev = bt_dev_port + SD1_BOOT; + break; + case 0x6: + case 0x7: + boot_dev = bt_dev_port + MMC1_BOOT; + break; + case 0x8 ... 0xf: + boot_dev = NAND_BOOT; + break; + default: + boot_dev = UNKNOWN_BOOT; + break; + } + + return boot_dev; +} + +void set_wdog_reset(struct wdog_regs *wdog) +{ + u32 reg = readw(&wdog->wcr); + /* + * use WDOG_B mode to reset external pmic because it's risky for the + * following watchdog reboot in case of cpu freq at lowest 400Mhz with + * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So + * in ldo-bypass mode watchdog reset will only triger POR reset, not + * WDOG reset. But below code depends on hardware design, if HW didn't + * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip + * these code since it assumed boot from 400Mhz always. + */ + reg = readw(&wdog->wcr); + reg |= 1 << 3; + /* + * WDZST bit is write-once only bit. Align this bit in kernel, + * otherwise kernel code will have no chance to set this bit. + */ + reg |= 1 << 0; + writew(reg, &wdog->wcr); +} + void reset_misc(void) { #ifdef CONFIG_VIDEO_MXS @@ -562,6 +866,10 @@ void s_init(void) u32 mask528; u32 reg, periph1, periph2; +#if defined(CONFIG_ANDROID_SUPPORT) + /* Enable RTC */ + writel(0x21, 0x020cc038); +#endif if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll()) return; @@ -650,6 +958,125 @@ void imx_setup_hdmi(void) } #endif +#ifdef CONFIG_LDO_BYPASS_CHECK +DECLARE_GLOBAL_DATA_PTR; +static int ldo_bypass; + +int check_ldo_bypass(void) +{ + const int *ldo_mode; + int node; + + /* get the right fdt_blob from the global working_fdt */ + gd->fdt_blob = working_fdt; + /* Get the node from FDT for anatop ldo-bypass */ + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, + "fsl,imx6q-gpc"); + if (node < 0) { + printf("No gpc device node %d, force to ldo-enable.\n", node); + return 0; + } + ldo_mode = fdt_getprop(gd->fdt_blob, node, "fsl,ldo-bypass", NULL); + /* + * return 1 if "fsl,ldo-bypass = <1>", else return 0 if + * "fsl,ldo-bypass = <0>" or no "fsl,ldo-bypass" property + */ + ldo_bypass = fdt32_to_cpu(*ldo_mode) == 1 ? 1 : 0; + + return ldo_bypass; +} + +int check_1_2G(void) +{ + u32 reg; + int result = 0; + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse_bank0 = + (struct fuse_bank0_regs *)bank->fuse_regs; + + reg = readl(&fuse_bank0->cfg3); + if (((reg >> 16) & 0x3) == 0x3) { + if (ldo_bypass) { + printf("Wrong dtb file used! i.MX6Q@1.2Ghz only " + "works with ldo-enable mode!\n"); + /* + * Currently, only imx6q-sabresd board might be here, + * since only i.MX6Q support 1.2G and only Sabresd board + * support ldo-bypass mode. So hardcode here. + * You can also modify your board(i.MX6Q) dtb name if it + * supports both ldo-bypass and ldo-enable mode. + */ + printf("Please use imx6q-sabresd-ldo.dtb!\n"); + hang(); + } + result = 1; + } + + return result; +} + +static int arm_orig_podf; +void set_arm_freq_400M(bool is_400M) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + if (is_400M) + writel(0x1, &mxc_ccm->cacrr); + else + writel(arm_orig_podf, &mxc_ccm->cacrr); +} + +void prep_anatop_bypass(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + arm_orig_podf = readl(&mxc_ccm->cacrr); + /* + * Downgrade ARM speed to 400Mhz as half of boot 800Mhz before ldo + * bypassed, also downgrade internal vddarm ldo to 0.975V. + * VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V) + * otherwise at 800Mhz(i.mx6dl): + * VDDARM_IN 1.175V + 125mV = 1.3V = Max(1.3V) + * We need provide enough gap in this case. + * skip if boot from 400M. + */ + if (!arm_orig_podf) + set_arm_freq_400M(true); + + if (!is_mx6dl() && !is_mx6sx()) + set_ldo_voltage(LDO_ARM, 975); + else + set_ldo_voltage(LDO_ARM, 1150); +} + +int set_anatop_bypass(int wdog_reset_pin) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct wdog_regs *wdog; + u32 reg = readl(&anatop->reg_core); + + /* bypass VDDARM/VDDSOC */ + reg = reg | (0x1F << 18) | 0x1F; + writel(reg, &anatop->reg_core); + + if (wdog_reset_pin == 2) + wdog = (struct wdog_regs *) WDOG2_BASE_ADDR; + else if (wdog_reset_pin == 1) + wdog = (struct wdog_regs *) WDOG1_BASE_ADDR; + else + return arm_orig_podf; + set_wdog_reset(wdog); + return arm_orig_podf; +} + +void finish_anatop_bypass(void) +{ + if (!arm_orig_podf) + set_arm_freq_400M(false); +} +#endif + void gpr_init(void) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 2a3db860bbc..242be59798a 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -16,6 +16,11 @@ config MX7D imply CMD_FUSE bool +config IMX_TAMPER + bool "Enable commands for SNVS tamper pin configuration and test" + help + Set "Y" to enable the tamper commands + choice prompt "MX7 board select" optional @@ -34,6 +39,41 @@ config TARGET_MX7DSABRESD select DM select DM_THERMAL +config TARGET_MX7D_12X12_LPDDR3_ARM2 + bool "Support mx7d_12x12_lpddr3_arm2" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + +config TARGET_MX7D_12X12_DDR3_ARM2 + bool "Support mx7d_12x12_ddr3_arm2" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + +config TARGET_MX7D_19X19_DDR3_ARM2 + bool "Support mx7d_19x19_ddr3_arm2" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + +config TARGET_MX7D_19X19_LPDDR3_ARM2 + bool "Support mx7d_19x19_lpddr3_arm2" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + +config TARGET_MX7D_19X19_LPDDR2_ARM2 + bool "Support mx7d_19x19_lpddr2_arm2" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + config TARGET_PICO_IMX7D bool "pico-imx7d" select BOARD_LATE_INIT @@ -41,6 +81,13 @@ config TARGET_PICO_IMX7D select DM select DM_THERMAL +config TARGET_MULTA_IMX7D + bool "Support multa-imx7d" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + config TARGET_WARP7 bool "warp7" select BOARD_LATE_INIT @@ -62,6 +109,11 @@ config SYS_SOC source "board/compulab/cl-som-imx7/Kconfig" source "board/freescale/mx7dsabresd/Kconfig" +source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig" +source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig" +source "board/freescale/mx7d_19x19_ddr3_arm2/Kconfig" +source "board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig" +source "board/freescale/multa-imx7d/Kconfig" source "board/technexion/pico-imx7d/Kconfig" source "board/toradex/colibri_imx7/Kconfig" source "board/warp7/Kconfig" diff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile index ce289c1415a..efb12244b60 100644 --- a/arch/arm/mach-imx/mx7/Makefile +++ b/arch/arm/mach-imx/mx7/Makefile @@ -6,6 +6,7 @@ # obj-y := soc.o clock.o clock_slice.o ddr.o +obj-$(CONFIG_IMX_TAMPER) += tamper.o ifdef CONFIG_ARMV7_PSCI obj-y += psci-mx7.o psci.o diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index d349676b811..4c95b304fce 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -18,6 +19,11 @@ #include #include #include +#include +#include +#ifdef CONFIG_IMX_SEC_INIT +#include +#endif #if defined(CONFIG_IMX_THERMAL) static const struct imx_thermal_plat imx7_thermal_plat = { @@ -91,7 +97,7 @@ static void isolate_resource(void) } #endif -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_SECURE_BOOT) || defined(CONFIG_AVB_ATX) struct imx_sec_config_fuse_t const imx_sec_config_fuse = { .bank = 1, .word = 3, @@ -160,8 +166,43 @@ static void imx_enet_mdio_fixup(void) } } +static void set_epdc_qos(void) +{ + writel(0, REGS_QOS_BASE); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_BASE + 0x60); /* Enable all masters */ + writel(0, REGS_QOS_EPDC); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_PXP0); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_PXP1); /* Disable clkgate & soft_reset */ + + writel(0x0f020722, REGS_QOS_EPDC + 0xd0); /* WR, init = 7 with red flag */ + writel(0x0f020722, REGS_QOS_EPDC + 0xe0); /* RD, init = 7 with red flag */ + + writel(1, REGS_QOS_PXP0); /* OT_CTRL_EN =1 */ + writel(1, REGS_QOS_PXP1); /* OT_CTRL_EN =1 */ + + writel(0x0f020222, REGS_QOS_PXP0 + 0x50); /* WR, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP1 + 0x50); /* WR, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP0 + 0x60); /* rD, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP1 + 0x60); /* rD, init = 2 with red flag */ + writel(0x0f020422, REGS_QOS_PXP0 + 0x70); /* tOTAL, init = 4 with red flag */ + writel(0x0f020422, REGS_QOS_PXP1 + 0x70); /* TOTAL, init = 4 with red flag */ + + writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034); /* EPDC AW/AR CACHE ENABLE */ +} + +bool is_usb_boot(void) +{ + if (gd->flags & GD_FLG_ARCH_IMX_USB_BOOT) + return true; + + return false; +} + int arch_cpu_init(void) { + if (is_usbotg_boot_enabled()) + gd->flags |= GD_FLG_ARCH_IMX_USB_BOOT; + init_aips(); init_csu(); @@ -170,6 +211,8 @@ int arch_cpu_init(void) imx_enet_mdio_fixup(); + set_epdc_qos(); + #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ mxs_dma_init(); @@ -179,6 +222,11 @@ int arch_cpu_init(void) isolate_resource(); #endif +#ifdef CONFIG_IMX_SEC_INIT + /* Secure init function such RNG */ + imx_sec_init(); +#endif + return 0; } @@ -257,16 +305,13 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { -#if !defined CONFIG_SPL_BUILD - /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #1 << 6\n" - "mcr p15, 0, r0, c1, c0, 1\n"); -#endif /* clock configuration. */ clock_init(); +#if defined(CONFIG_ANDROID_SUPPORT) + /* Enable RTC */ + writel(0x21, 0x30370038); +#endif return; } @@ -277,3 +322,30 @@ void reset_misc(void) #endif } +#ifdef CONFIG_IMX_TRUSTY_OS +#ifdef CONFIG_MX7D +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + return; +} + +void smp_waitloop(unsigned previous_address) +{ + return; +} +#endif +#endif + +void reset_cpu(ulong addr) +{ + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + + /* Clear WDA to trigger WDOG_B immediately */ + writew((WCR_WDE | WCR_SRS), &wdog->wcr); + + while (1) { + /* + * spin for .5 seconds before reset + */ + } +} diff --git a/arch/arm/mach-imx/mx7/tamper.c b/arch/arm/mach-imx/mx7/tamper.c new file mode 100644 index 00000000000..89f62397f8c --- /dev/null +++ b/arch/arm/mach-imx/mx7/tamper.c @@ -0,0 +1,384 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void enable_active_tamper(unsigned int tx, unsigned int rx) +{ + int val; + + printf("start active tamper test on %d -> %d\n", tx, rx); + + /**************************** + * Configuring CAAM and SNVS * + ****************************/ + + /* Initialize power glitch detector register */ + val = 0x41736166; + writel(val, SNVS_LPPGDR); + + /* W1C PGD */ + val = readl(SNVS_LPSR) & 0x00000008; + writel(val, SNVS_LPSR); + + /* Programming ZMK via SW */ + writel(0x11110000, SNVS_LPZMKR0); + writel(0x22220000, SNVS_LPZMKR1); + writel(0x33330000, SNVS_LPZMKR2); + writel(0x44440000, SNVS_LPZMKR3); + writel(0x55550000, SNVS_LPZMKR4); + writel(0x66660000, SNVS_LPZMKR5); + writel(0x77770000, SNVS_LPZMKR6); + writel(0x88880000, SNVS_LPZMKR7); + + val = readl(SNVS_LPMKCR) | 0xa; + writel(val, SNVS_LPMKCR); + val = readl(SNVS_HPCOMR) | 0x1000; + writel(val, SNVS_HPCOMR); + + val = readl(SNVS_LPMKCR) | 0x10; + writel(val, SNVS_LPMKCR); + + val = readl(SNVS_HPSVSR); + + /* LP Security Violation is a non-fatal Violation */ + val = 0x40000000; + writel(val, SNVS_HPSVCR); + + /* Enable SRTC invalidation in case of security violation */ + val = readl(SNVS_LPCR); + val |= 0x11; + writel(val, SNVS_LPCR); + + /********************************* + * Configuring active tamper tx output * + *********************************/ + + /* Configure LFSR polynomial and seed for active tamper tx */ + val = AT5_POLYSEED; + writel(val, SNVS_LPAT1CR + (tx - 5) * 4); + + /* Enable active tamper tx external pad */ + val = readl(SNVS_LPATCTLR) | (1 << (tx - 5 + 16)); + writel(val, SNVS_LPATCTLR); + + /* Enable active tamper tx clk 16hz */ + val = readl(SNVS_LPATCLKR); + val &= ~(3 << (tx - 5) * 4); + writel(val, SNVS_LPATCLKR); + + /* Enable active tamper tx LFSR */ + val = readl(SNVS_LPATCTLR) | (1 << (tx - 5)); + writel(val, SNVS_LPATCTLR); + + /* Enable glitch filter for external tamper rx */ + if (rx < 2) { + val = readl(SNVS_LPTGFCR); + if (rx == 0) + val |= 0x800000; + else if (rx == 1) + val |= 0x80000000; + writel(val, SNVS_LPTGFCR); + } else if (rx < 6) { + val = readl(SNVS_LPTGF1CR); + val |= 1 << ((rx - 1) * 8 - 1); + writel(val, SNVS_LPTGF1CR); + } else { + val = readl(SNVS_LPTGF2CR); + val |= 1 << ((rx - 5) * 8 - 1); + writel(val, SNVS_LPTGF2CR); + } + + /* Route active tamper tx to external tamper rx */ + if (rx < 8) { + val = readl(SNVS_LPATRC1R); + val &= ~(0xf << (rx * 4)); + val |= ((tx - 4) << (rx * 4)); + writel(val, SNVS_LPATRC1R); + } else { + val = readl(SNVS_LPATRC2R); + val &= ~(0xf << ((rx - 8) * 4)); + val |= ((tx - 4) << ((rx - 8) * 4)); + writel(val, SNVS_LPATRC2R); + } + + /* Enable external tamper rx */ + if (rx < 2) { + val = readl(SNVS_LPTDCR); + if (rx == 0) + val |= 0x200; + else if (rx == 1) + val |= 0x400; + writel(val, SNVS_LPTDCR); + } else { + val = readl(SNVS_LPTDC2R); + val |= 1 << (rx - 2); + writel(val, SNVS_LPTDC2R); + } +} + +void enable_passive_tamper(unsigned int rx, unsigned int high) +{ + int val; + + printf("start passive tamper test on pin %d\n", rx); + + /**************************** + * Configuring CAAM and SNVS * + ****************************/ + + /* Initialize power glitch detector register */ + val = 0x41736166; + writel(val, SNVS_LPPGDR); + + /* W1C PGD */ + val = readl(SNVS_LPSR) & 0x00000008; + writel(val, SNVS_LPSR); + + /* Programming ZMK via SW */ + writel(0x11111111, SNVS_LPZMKR0); + writel(0x22222222, SNVS_LPZMKR1); + writel(0x33333333, SNVS_LPZMKR2); + writel(0x44444444, SNVS_LPZMKR3); + writel(0x55555555, SNVS_LPZMKR4); + writel(0x66666666, SNVS_LPZMKR5); + writel(0x77777777, SNVS_LPZMKR6); + writel(0x88888888, SNVS_LPZMKR7); + + val = readl(SNVS_LPMKCR) | 0xa; + writel(val, SNVS_LPMKCR); + val = readl(SNVS_HPCOMR) | 0x1000; + writel(val, SNVS_HPCOMR); + + val = readl(SNVS_LPMKCR) | 0x10; + writel(val, SNVS_LPMKCR); + + /* LP Security Violation is a non-fatal Violation */ + val = 0x40000000; + writel(val, SNVS_HPSVCR); + + /* Enable SRTC invalidation in case of security violation */ + val = readl(SNVS_LPCR); + val |= 0x11; + writel(val, SNVS_LPCR); + + /********************************* + * Configuring passive tamper rx * + *********************************/ + + /* Enable glitch filter for external tamper rx */ + if (rx < 2) { + val = readl(SNVS_LPTGFCR); + if (rx == 0) + val |= 0x800000; + else if (rx == 1) + val |= 0x80000000; + writel(val, SNVS_LPTGFCR); + } else if (rx < 6) { + val = readl(SNVS_LPTGF1CR); + val |= 1 << ((rx - 1) * 8 - 1); + writel(val, SNVS_LPTGF1CR); + } else { + val = readl(SNVS_LPTGF2CR); + val |= 1 << ((rx - 5) * 8 - 1); + writel(val, SNVS_LPTGF2CR); + } + + if (high == 1) { + /* Set external tampering rx polarity to high and enable tamper */ + if (rx < 2) { + val = readl(SNVS_LPTDCR); + if (rx == 0) + val |= 0x800; + else if (rx == 1) + val |= 0x1000; + writel(val, SNVS_LPTDCR); + } else { + val = readl(SNVS_LPTDC2R); + val |= 1 << (rx - 2 + 16); + writel(val, SNVS_LPTDC2R); + } + } + /* Enable external tamper rx */ + if (rx < 2) { + val = readl(SNVS_LPTDCR); + if (rx == 0) + val |= 0x200; + else if (rx == 1) + val |= 0x400; + writel(val, SNVS_LPTDCR); + } else { + val = readl(SNVS_LPTDC2R); + val |= 1 << (rx - 2); + writel(val, SNVS_LPTDC2R); + } +} + +void stop_tamper(int rx) +{ + int val; + + /* stop tamper */ + if (rx < 2) { + val = readl(SNVS_LPTDCR); + if (rx == 0) + val &= ~0x200; + else if (rx == 1) + val &= ~0x400; + writel(val, SNVS_LPTDCR); + } else { + val = readl(SNVS_LPTDC2R); + val &= ~(1 << (rx - 2)); + writel(val, SNVS_LPTDC2R); + } + + /* clear tamper status */ + if (rx < 2) { + val = readl(SNVS_LPSR); + val |= 1 << (rx + 9); + writel(val, SNVS_LPSR); + } else if (rx < 10) { + val = readl(SNVS_LPTDSR); + val |= 1 << (rx - 2); + writel(val, SNVS_LPTDSR); + } +} + +static void get_tamper_status(void) +{ + unsigned int lpsr, lptdsr, hpsr, ssm; + + lpsr = readl(SNVS_LPSR); + lptdsr = readl(SNVS_LPTDSR); + hpsr = readl(SNVS_HPSR); + ssm = (hpsr & 0xf00) >> 8; + + if (lpsr & (1 << 9)) + printf("External Tampering 0 Detected\n"); + if (lpsr & (1 << 10)) + printf("External Tampering 1 Detected\n"); + if (lptdsr & (1 << 0)) + printf("External Tampering 2 Detected\n"); + if (lptdsr & (1 << 1)) + printf("External Tampering 3 Detected\n"); + if (lptdsr & (1 << 2)) + printf("External Tampering 4 Detected\n"); + if (lptdsr & (1 << 3)) + printf("External Tampering 5 Detected\n"); + if (lptdsr & (1 << 4)) + printf("External Tampering 6 Detected\n"); + if (lptdsr & (1 << 5)) + printf("External Tampering 7 Detected\n"); + if (lptdsr & (1 << 6)) + printf("External Tampering 8 Detected\n"); + if (lptdsr & (1 << 7)) + printf("External Tampering 9 Detected\n"); + if (!(lpsr & (3 << 9)) && !(lptdsr & 0xff)) + printf("No External Tampering Detected\n"); + + if (hpsr & 0x80000000) + printf("Zeroizable Master Key is clear\n"); + else + printf("Zeroizable Master Key is not zero\n"); + + if (ssm == 0) + printf("System Security Monitor State: Init\n"); + else if (ssm == 0x8) + printf("System Security Monitor State: Init Intermediate\n"); + else if (ssm == 0x9) + printf("System Security Monitor State: Check\n"); + else if (ssm == 0xb) + printf("System Security Monitor State: Non-Secure\n"); + else if (ssm == 0xd) + printf("System Security Monitor State: Trusted\n"); + else if (ssm == 0xf) + printf("System Security Monitor State: Secure\n"); + else if (ssm == 0x3) + printf("System Security Monitor State: Soft Fail\n"); + else if (ssm == 0x1) + printf("System Security Monitor State: Hard Fail\n"); + else + printf("System Security Monitor State: 0x%x\n", ssm); +} + +static void clear_tamper_warning(void) +{ + unsigned int lpsr, lptdsr; + + lpsr = readl(SNVS_LPSR); + lptdsr = readl(SNVS_LPTDSR); + + writel(lpsr, SNVS_LPSR); + writel(lptdsr, SNVS_LPTDSR); +} + +static int do_tamper(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + const char *op = argc >= 2 ? argv[1] : NULL; + unsigned int tx, rx, high; + + if (argc < 2) + return CMD_RET_USAGE; + + if (!strcmp(op, "active")) { + if (argc < 4) + return CMD_RET_USAGE; + + tx = simple_strtoul(argv[2], NULL, 16); + rx = simple_strtoul(argv[3], NULL, 16); + if ((tx > 9) || (tx < 5)) + return CMD_RET_USAGE; + if ((rx > 9) || (rx == tx)) + return CMD_RET_USAGE; + + enable_active_tamper(tx, rx); + + } else if (!strcmp(op, "passive")) { + if (argc < 4) + return CMD_RET_USAGE; + + rx = simple_strtoul(argv[2], NULL, 16); + if (rx > 9) + return CMD_RET_USAGE; + + high = simple_strtoul(argv[3], NULL, 16); + if (high != 0) + high = 1; + enable_passive_tamper(rx, high); + + } else if (!strcmp(op, "status")) { + get_tamper_status(); + } else if (!strcmp(op, "clear")) { + clear_tamper_warning(); + } else if (!strcmp(op, "stop")) { + if (argc < 3) + return CMD_RET_USAGE; + + rx = simple_strtoul(argv[2], NULL, 16); + if (rx > 9) + return CMD_RET_USAGE; + stop_tamper(rx); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + imx_tamper, CONFIG_SYS_MAXARGS, 0, do_tamper, + "imx tamper command for setting for test", + "active - tx is active tamper pin from 9 ~ 5, \n" + " rx pin is from 9 ~ 0 and should not equal to tx pin\n" + "passive - rx is passive tamper pin from 9 ~ 0, \n" + " high: 1 - high assert, 0 - low assert\n" + "status - Get tamper status\n" + "clear - clear tamper warning\n" + "stop rx - rx is tamper pin to stop\n" + ); diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig index 1bdc85a9a03..600ce3b70c9 100644 --- a/arch/arm/mach-imx/mx7ulp/Kconfig +++ b/arch/arm/mach-imx/mx7ulp/Kconfig @@ -3,15 +3,38 @@ if ARCH_MX7ULP config SYS_SOC default "mx7ulp" +config IMX_M4_BIND + bool "Bind ULP M4 image to final u-boot" + help + Select this to bind a ULP M4 image to final u-boot image + User needs put the M4 image ulp_m4.bin under u-boot directory + +config MX7ULP + select HAS_CAAM + bool + choice prompt "MX7ULP board select" optional +config TARGET_MX7ULP_10X10_ARM2 + bool "Support mx7ulp 10x10 validation board" + select BOARD_LATE_INIT + select MX7ULP + +config TARGET_MX7ULP_14X14_ARM2 + bool "Support mx7ulp 14x14 validation board" + select BOARD_LATE_INIT + select MX7ULP + config TARGET_MX7ULP_EVK - bool "Support mx7ulp EVK board" + bool "Support mx7ulp EVK board" + select BOARD_LATE_INIT + select MX7ULP endchoice +source "board/freescale/mx7ulp_arm2/Kconfig" source "board/freescale/mx7ulp_evk/Kconfig" endif diff --git a/arch/arm/mach-imx/mx7ulp/Makefile b/arch/arm/mach-imx/mx7ulp/Makefile index 0248ea85a3a..2a55b971e96 100644 --- a/arch/arm/mach-imx/mx7ulp/Makefile +++ b/arch/arm/mach-imx/mx7ulp/Makefile @@ -6,3 +6,4 @@ # obj-y := soc.o clock.o iomux.o pcc.o scg.o +obj-$(CONFIG_IMX_M4_BIND) += piggy_m4.o diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index 553d62149de..440e835c0bb 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -73,7 +74,7 @@ u32 get_lpuart_clk(void) return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]); } -#ifdef CONFIG_SYS_LPI2C_IMX +#ifdef CONFIG_SYS_I2C_IMX_LPI2C int enable_i2c_clk(unsigned char enable, unsigned i2c_num) { /* Set parent to FIRC DIV2 clock */ @@ -149,8 +150,8 @@ void init_clk_usdhc(u32 index) /*Disable the clock before configure it */ pcc_clock_enable(PER_CLK_USDHC0, false); - /* 158MHz / 1 = 158MHz */ - pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK); + /* 352.8MHz / 1 = 352.8MHz */ + pcc_clock_sel(PER_CLK_USDHC0, SCG_APLL_PFD1_CLK); pcc_clock_div_config(PER_CLK_USDHC0, false, 1); pcc_clock_enable(PER_CLK_USDHC0, true); break; @@ -158,9 +159,9 @@ void init_clk_usdhc(u32 index) /*Disable the clock before configure it */ pcc_clock_enable(PER_CLK_USDHC1, false); - /* 158MHz / 1 = 158MHz */ - pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK); - pcc_clock_div_config(PER_CLK_USDHC1, false, 1); + /* 352.8MHz / 2 = 176.4MHz */ + pcc_clock_sel(PER_CLK_USDHC1, SCG_APLL_PFD1_CLK); + pcc_clock_div_config(PER_CLK_USDHC1, false, 2); pcc_clock_enable(PER_CLK_USDHC1, true); break; default: @@ -301,9 +302,11 @@ void clock_init(void) scg_a7_soscdiv_init(); - /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */ - scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35); - scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20); + scg_a7_init_core_clk(); + + /* APLL PFD1 = 352.8Mhz, PFD2=340.2Mhz, PFD3=793.8Mhz */ + scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 27); + scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28); scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12); init_clk_lpuart(); @@ -323,6 +326,87 @@ void hab_caam_clock_enable(unsigned char enable) } #endif +void enable_mipi_dsi_clk(unsigned char enable) +{ + if (enable) { + pcc_clock_enable(PER_CLK_DSI, false); + + /* mipi dsi escape clock range is 40-80Mhz, we expect to set it to about 60 Mhz + * To avoid PCD issue, we select parent clock with lowest frequency + * NIC1_CLK = 1584000khz, frac = 1, div = 5, output = 63.360Mhz + */ + pcc_clock_sel(PER_CLK_DSI, SCG_NIC1_CLK); + pcc_clock_div_config(PER_CLK_DSI, 1, 5); + + pcc_clock_enable(PER_CLK_DSI, true); + } else { + pcc_clock_enable(PER_CLK_DSI, false); + } +} + +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz) +{ + /* Scan the parent clock to find best fit clock, whose generate actual frequence <= freq + * Otherwise, the higher actual freq may introduce some problem + * 1. The real frequency exceeds max framerate that screen supports + * 2. The DSI PHY clock depends on the lcdif clock, so the higher lcdif clock may violate + * DSI PHY clock requirement + */ + u8 pcd, best_pcd = 0; + u32 parent, frac, rate, parent_rate; + u32 best_parent = 0, best_frac = 0, best = 0; + + static enum scg_clk clksrc_plat[] = { + SCG_NIC1_BUS_CLK, + SCG_NIC1_CLK, + SCG_DDR_CLK, + SCG_APLL_PFD2_CLK, + SCG_APLL_PFD1_CLK, + SCG_APLL_PFD0_CLK, + USB_PLL_OUT, + }; + + pcc_clock_enable(PER_CLK_LCDIF, false); + + for (parent = 0; parent < ARRAY_SIZE(clksrc_plat); parent++) { + parent_rate = scg_clk_get_rate(clksrc_plat[parent]); + if (!parent_rate) + continue; + + parent_rate = parent_rate / 1000; /* Change to khz*/ + + for (pcd = 0; pcd < 8; pcd++) { + for (frac = 0; frac < 2; frac++) { + if (pcd == 0 && frac == 1) + continue; + + rate = parent_rate * (frac + 1) / (pcd + 1); + if (rate > freq_in_khz) + continue; + + if (best == 0 || rate > best) { + best = rate; + best_parent = parent; + best_frac = frac; + best_pcd = pcd; + } + } + } + } + + if (best == 0) { + printf("Can't find parent clock for LCDIF, target freq: %u\n", freq_in_khz); + return; + } + + debug("LCD target rate %ukhz, best rate %ukhz, frac %u, pcd %u, best_parent %u\n", + freq_in_khz, best, best_frac, best_pcd, best_parent); + + pcc_clock_sel(PER_CLK_LCDIF, clksrc_plat[best_parent]); + pcc_clock_div_config(PER_CLK_LCDIF, best_frac, best_pcd + 1); + pcc_clock_enable(PER_CLK_LCDIF, true); +} + #ifndef CONFIG_SPL_BUILD /* * Dump some core clockes. diff --git a/arch/arm/mach-imx/mx7ulp/piggy_m4.S b/arch/arm/mach-imx/mx7ulp/piggy_m4.S new file mode 100644 index 00000000000..b33e8422ea6 --- /dev/null +++ b/arch/arm/mach-imx/mx7ulp/piggy_m4.S @@ -0,0 +1,2 @@ + .section .firmware_image,#alloc + .incbin "ulp_m4.bin" diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index c117af0a0ec..992cb4e93dc 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -355,7 +356,7 @@ static u32 scg_ddr_get_rate(void) static u32 scg_nic_get_rate(enum scg_clk clk) { - u32 reg, val, rate; + u32 reg, val, rate, nic0_rate; u32 shift, mask; reg = readl(&scg1_regs->niccsr); @@ -373,6 +374,7 @@ static u32 scg_nic_get_rate(enum scg_clk clk) val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT; rate = rate / (val + 1); + nic0_rate = rate; clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate); @@ -414,6 +416,10 @@ static u32 scg_nic_get_rate(enum scg_clk clk) return 0; } + /* On RevB, the nic_bus and nic_ext dividers are parallel not chained with nic div */ + if (soc_rev() >= CHIP_REV_2_0) + rate = nic0_rate; + val = (reg & mask) >> shift; rate = rate / (val + 1); @@ -443,7 +449,7 @@ static u32 scg_sys_get_rate(enum scg_clk clk) case SCG_SCS_SLOW_IRC: case SCG_SCS_FAST_IRC: case SCG_SCS_RTC_OSC: - rate = scg_src_get_rate(scg_scs_array[val]); + rate = scg_src_get_rate(scg_scs_array[val - 1]); break; case 5: rate = scg_apll_get_rate(); @@ -506,7 +512,10 @@ u32 decode_pll(enum pll_clocks pll) infreq = infreq / pre_div; - return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult; case PLL_A7_APLL: reg = readl(&scg1_regs->apllcsr); @@ -535,7 +544,10 @@ u32 decode_pll(enum pll_clocks pll) infreq = infreq / pre_div; - return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult; case PLL_USB: reg = readl(&scg1_regs->upllcsr); @@ -702,6 +714,61 @@ int scg_enable_pll_pfd(enum scg_clk clk, u32 frac) return 0; } +int scg_disable_pll_pfd(enum scg_clk clk) +{ + u32 reg; + u32 gate; + u32 addr; + + switch (clk) { + case SCG_SPLL_PFD0_CLK: + case SCG_APLL_PFD0_CLK: + gate = SCG_PLL_PFD0_GATE_MASK; + + if (clk == SCG_SPLL_PFD0_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD1_CLK: + case SCG_APLL_PFD1_CLK: + gate = SCG_PLL_PFD1_GATE_MASK; + + if (clk == SCG_SPLL_PFD1_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD2_CLK: + case SCG_APLL_PFD2_CLK: + gate = SCG_PLL_PFD2_GATE_MASK; + + if (clk == SCG_SPLL_PFD2_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD3_CLK: + case SCG_APLL_PFD3_CLK: + gate = SCG_PLL_PFD3_GATE_MASK; + + if (clk == SCG_SPLL_PFD3_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + default: + return -EINVAL; + } + + /* Gate the PFD */ + reg = readl(addr); + reg |= gate; + writel(reg, addr); + + return 0; +} + #define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2) int scg_enable_usb_pll(bool usb_control) { @@ -1088,3 +1155,39 @@ void scg_a7_info(void) debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr)); debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr)); } + +void scg_a7_init_core_clk(void) +{ + u32 val = 0; + + /* The normal target frequency for ULP B0 is 500Mhz, but ROM set it to 413Mhz, need to change SPLL PFD0 FRAC */ + if (soc_rev() >= CHIP_REV_2_0) { + + /* Switch RCCR SCG to SOSC, firstly check the SOSC is valid */ + if ((readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) { + val = readl(&scg1_regs->rccr); + val &= (~SCG_CCR_SCS_MASK); + val |= ((SCG_SCS_SYS_OSC) << SCG_CCR_SCS_SHIFT); + writel(val, &scg1_regs->rccr); + + /* Swith the PLLS to SPLL clk */ + val = readl(&scg1_regs->spllcfg); + val &= ~SCG_PLL_CFG_PLLSEL_MASK; + writel(val, &scg1_regs->spllcfg); + + /* Re-configure PFD0 to 19, A7 SPLL(528MHz) * 18 / 19 = 500MHz */ + scg_enable_pll_pfd(SCG_SPLL_PFD0_CLK, 19); + + /* Swith the PLLS to SPLL PFD0 */ + val = readl(&scg1_regs->spllcfg); + val |= SCG_PLL_CFG_PLLSEL_MASK; + writel(val, &scg1_regs->spllcfg); + + /* Set RCCR SCG to SPLL clk out */ + val = readl(&scg1_regs->rccr); + val &= (~SCG_CCR_SCS_MASK); + val |= ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT); + writel(val, &scg1_regs->rccr); + } + } +} diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 454665ae4cc..a3fecd70060 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -1,13 +1,21 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include +#include #include #include +#include +#include +#include +#ifdef CONFIG_IMX_SEC_INIT +#include +#endif static char *get_reset_cause(char *); @@ -18,10 +26,29 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = { }; #endif +#define ROM_VERSION_ADDR 0x80 u32 get_cpu_rev(void) { - /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */ - return (MXC_CPU_MX7ULP << 12) | (1 << 4); + /* Check the ROM version for cpu revision */ + uint32_t rom_version; + rom_version = readl((void __iomem *)ROM_VERSION_ADDR); + + rom_version &= 0xFF; + if (rom_version == CHIP_REV_1_0) { + return (MXC_CPU_MX7ULP << 12) | (rom_version); + } else { + /* Check the "Mirror of JTAG ID" SIM register since RevB */ + uint32_t id; + id = readl(SIM0_RBASE + 0x8c); + id = (id >> 28) & 0xFF; + + /* Revision Number ULP1 Version + * 0000 A0 + * 0001 B0 + * 0010 B1 + */ + return (MXC_CPU_MX7ULP << 12) | (CHIP_REV_2_0 + (id - 1)); + } } #ifdef CONFIG_REVISION_TAG @@ -49,8 +76,51 @@ enum bt_mode get_boot_mode(void) return LOW_POWER_BOOT; } +#ifdef CONFIG_IMX_M4_BIND +char __firmware_image_start[0] __attribute__((section(".__firmware_image_start"))); +char __firmware_image_end[0] __attribute__((section(".__firmware_image_end"))); + +int mcore_early_load_and_boot(void) +{ + u32 *src_addr = (u32 *)&__firmware_image_start; + u32 *dest_addr = (u32 *)TCML_BASE; /*TCML*/ + u32 image_size = SZ_128K + SZ_64K; /* 192 KB*/ + u32 pc = 0, tag = 0; + + memcpy(dest_addr, src_addr, image_size); + + /* Set GP register to tell the M4 rom the image entry */ + /* We assume the M4 image has IVT head and padding which + * should be same as the one programmed into QSPI flash + */ + tag = *(dest_addr + 1024); + if (tag != 0x402000d1 && tag !=0x412000d1) + return -1; + + pc = *(dest_addr + 1025); + + writel(pc, SIM0_RBASE + 0x70); /*GP7*/ + + return 0; +} +#endif + int arch_cpu_init(void) { +#ifdef CONFIG_IMX_M4_BIND + int ret; + if (get_boot_mode() == SINGLE_BOOT) { + ret = mcore_early_load_and_boot(); + if (ret) + puts("Invalid M4 image, boot failed\n"); + } +#endif + +#ifdef CONFIG_IMX_SEC_INIT + /* Secure init function such RNG */ + imx_sec_init(); +#endif + return 0; } @@ -106,6 +176,15 @@ void s_init(void) /* clock configuration. */ clock_init(); + if (soc_rev() < CHIP_REV_2_0) { + /* enable dumb pmic */ + writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR); + +#if defined(CONFIG_ANDROID_SUPPORT) + /* Enable RTC */ + writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_SRTC_ENV), SNVS_LP_LPCR); +#endif + } return; } @@ -149,6 +228,10 @@ int print_cpuinfo(void) case SINGLE_BOOT: default: printf("Single boot\n"); +#ifdef CONFIG_IMX_M4_BIND + if (readl(SIM0_RBASE + 0x70)) + printf("M4 start at 0x%x\n", readl(SIM0_RBASE + 0x70)); +#endif break; } @@ -184,7 +267,12 @@ static char *get_reset_cause(char *ret) srs = readl(reg_srs); cause1 = readl(reg_ssrs); +#ifndef CONFIG_ANDROID_BOOT_IMAGE + /* We will read the ssrs states later for android so we don't + * clear the states here. + */ writel(cause1, reg_ssrs); +#endif reset_cause = cause1; @@ -224,6 +312,27 @@ static char *get_reset_cause(char *ret) return ret; } +#ifdef CONFIG_ANDROID_BOOT_IMAGE +void get_reboot_reason(char *ret) +{ + u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28); + + get_reset_cause(ret); + /* clear the ssrs here, its state has been recorded in reset_cause */ + writel(reset_cause, reg_ssrs); +} +#endif + +void arch_preboot_os(void) +{ +#if defined(CONFIG_VIDEO_MXS) + lcdif_power_down(); +#endif + scg_disable_pll_pfd(SCG_APLL_PFD1_CLK); + scg_disable_pll_pfd(SCG_APLL_PFD2_CLK); + scg_disable_pll_pfd(SCG_APLL_PFD3_CLK); +} + #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { @@ -245,3 +354,84 @@ int mmc_get_env_dev(void) return board_mmc_get_env_dev(devno); } #endif + +#ifdef CONFIG_OF_SYSTEM_SETUP +int ft_system_setup(void *blob, bd_t *bd) +{ + if (get_boot_device() == USB_BOOT) { + int rc; + int nodeoff = fdt_path_offset(blob, "/ahb-bridge0@40000000/usdhc@40370000"); + if (nodeoff < 0) + return 0; /* Not found, skip it */ + + printf("Found usdhc0 node\n"); + if (fdt_get_property(blob, nodeoff, "vqmmc-supply", NULL) != NULL) { + rc = fdt_delprop(blob, nodeoff, "vqmmc-supply"); + if (!rc) { + printf("Removed vqmmc-supply property\n"); + +add: + rc = fdt_setprop(blob, nodeoff, "no-1-8-v", NULL, 0); + if (rc == -FDT_ERR_NOSPACE) { + rc = fdt_increase_size(blob, 32); + if (!rc) + goto add; + } else if (rc) { + printf("Failed to add no-1-8-v property, %d\n", rc); + } else { + printf("Added no-1-8-v property\n"); + } + } else { + printf("Failed to remove vqmmc-supply property, %d\n", rc); + } + } + } + return 0; +} +#endif + +enum boot_device get_boot_device(void) +{ + struct bootrom_sw_info **p = + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; + + enum boot_device boot_dev = SD1_BOOT; + u8 boot_type = (*p)->boot_dev_type; + u8 boot_instance = (*p)->boot_dev_instance; + + switch (boot_type) { + case BOOT_TYPE_SD: + boot_dev = boot_instance + SD1_BOOT; + break; + case BOOT_TYPE_MMC: + boot_dev = boot_instance + MMC1_BOOT; + break; + case BOOT_TYPE_USB: + boot_dev = USB_BOOT; + break; + default: + break; + } + + return boot_dev; +} + +bool is_usb_boot(void) +{ + return get_boot_device() == USB_BOOT; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + serialnr->low = (fuse->cfg0 & 0xFFFF) + ((fuse->cfg1 & 0xFFFF) << 16); + serialnr->high = (fuse->cfg2 & 0xFFFF) + ((fuse->cfg3 & 0xFFFF) << 16); +} +#endif /*CONFIG_SERIAL_TAG*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig deleted file mode 100644 index 3a84c2f2b09..00000000000 --- a/arch/arm/mach-imx/mx8m/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -if ARCH_MX8M - -config MX8M - bool - select ROM_UNIFIED_SECTIONS - -config SYS_SOC - default "mx8m" - -endif diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/mx8m/Makefile deleted file mode 100644 index b1c5d74aab7..00000000000 --- a/arch/arm/mach-imx/mx8m/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2017 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += lowlevel_init.o -obj-y += clock.o clock_slice.o soc.o diff --git a/arch/arm/mach-imx/mx8m/soc.c b/arch/arm/mach-imx/mx8m/soc.c deleted file mode 100644 index fe6c19c787d..00000000000 --- a/arch/arm/mach-imx/mx8m/soc.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright 2017 NXP - * - * Peng Fan - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_SECURE_BOOT) -struct imx_sec_config_fuse_t const imx_sec_config_fuse = { - .bank = 1, - .word = 3, -}; -#endif - -int timer_init(void) -{ -#ifdef CONFIG_SPL_BUILD - struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; - unsigned long freq = readl(&sctr->cntfid0); - - /* Update with accurate clock frequency */ - asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory"); - - clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1, - SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG); -#endif - - gd->arch.tbl = 0; - gd->arch.tbu = 0; - - return 0; -} - -void enable_tzc380(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Enable TZASC and lock setting */ - setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); - setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); -} - -void set_wdog_reset(struct wdog_regs *wdog) -{ - /* - * Output WDOG_B signal to reset external pmic or POR_B decided by - * the board design. Without external reset, the peripherals/DDR/ - * PMIC are not reset, that may cause system working abnormal. - * WDZST bit is write-once only bit. Align this bit in kernel, - * otherwise kernel code will have no chance to set this bit. - */ - setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); -} - -static struct mm_region imx8m_mem_map[] = { - { - /* ROM */ - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x100000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE - }, { - /* OCRAM */ - .virt = 0x900000UL, - .phys = 0x900000UL, - .size = 0x200000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE - }, { - /* AIPS */ - .virt = 0xB00000UL, - .phys = 0xB00000UL, - .size = 0x3f500000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* DRAM1 */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0xC0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE - }, { - /* DRAM2 */ - .virt = 0x100000000UL, - .phys = 0x100000000UL, - .size = 0x040000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = imx8m_mem_map; - -u32 get_cpu_rev(void) -{ - struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; - u32 reg = readl(&ana_pll->digprog); - u32 type = (reg >> 16) & 0xff; - u32 rom_version; - - reg &= 0xff; - - if (reg == CHIP_REV_1_0) { - /* - * For B0 chip, the DIGPROG is not updated, still TO1.0. - * we have to check ROM version further - */ - rom_version = readl((void __iomem *)ROM_VERSION_A0); - if (rom_version != CHIP_REV_1_0) { - rom_version = readl((void __iomem *)ROM_VERSION_B0); - if (rom_version >= CHIP_REV_2_0) - reg = CHIP_REV_2_0; - } - } - - return (type << 12) | reg; -} - -static void imx_set_wdog_powerdown(bool enable) -{ - struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; - struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; - struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; - - /* Write to the PDE (Power Down Enable) bit */ - writew(enable, &wdog1->wmcr); - writew(enable, &wdog2->wmcr); - writew(enable, &wdog3->wmcr); -} - -int arch_cpu_init(void) -{ - /* - * Init timer at very early state, because sscg pll setting - * will use it - */ - timer_init(); - - if (IS_ENABLED(CONFIG_SPL_BUILD)) { - clock_init(); - imx_set_wdog_powerdown(false); - } - - return 0; -} - -bool is_usb_boot(void) -{ - return get_boot_device() == USB_BOOT; -} - -#ifdef CONFIG_OF_SYSTEM_SETUP -int ft_system_setup(void *blob, bd_t *bd) -{ - int i = 0; - int rc; - int nodeoff; - - /* Disable the CPU idle for A0 chip since the HW does not support it */ - if (is_soc_rev(CHIP_REV_1_0)) { - static const char * const nodes_path[] = { - "/cpus/cpu@0", - "/cpus/cpu@1", - "/cpus/cpu@2", - "/cpus/cpu@3", - }; - - for (i = 0; i < ARRAY_SIZE(nodes_path); i++) { - nodeoff = fdt_path_offset(blob, nodes_path[i]); - if (nodeoff < 0) - continue; /* Not found, skip it */ - - printf("Found %s node\n", nodes_path[i]); - - rc = fdt_delprop(blob, nodeoff, "cpu-idle-states"); - if (rc) { - printf("Unable to update property %s:%s, err=%s\n", - nodes_path[i], "status", fdt_strerror(rc)); - return rc; - } - - printf("Remove %s:%s\n", nodes_path[i], - "cpu-idle-states"); - } - } - - return 0; -} -#endif - -void reset_cpu(ulong addr) -{ - struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; - - /* Clear WDA to trigger WDOG_B immediately */ - writew((WCR_WDE | WCR_SRS), &wdog->wcr); - - while (1) { - /* - * spin for .5 seconds before reset - */ - } -} diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c new file mode 100644 index 00000000000..4c5ebda7109 --- /dev/null +++ b/arch/arm/mach-imx/priblob.c @@ -0,0 +1,32 @@ +/* + * Copyright 2018 NXP + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Boot command to get and set the PRIBLOB bitfield form the SCFGR register + * of the CAAM IP. It is recommended to set this bitfield to 3 once your + * encrypted boot image is ready, to prevent the generation of blobs usable + * to decrypt an encrypted boot image. + */ +#include +#include +#include +#include "../drivers/crypto/fsl_caam_internal.h" + +int do_priblob_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + writel((readl(CAAM_SCFGR) & 0xFFFFFFFC) | 3, CAAM_SCFGR); + printf("New priblob setting = 0x%x\n", readl(CAAM_SCFGR) & 0x3); + + return 0; +} + +U_BOOT_CMD( + set_priblob_bitfield, 1, 0, do_priblob_write, + "Set the PRIBLOB bitfield to 3", + "\n" + " - Write 3 in PRIBLOB bitfield of SCFGR regiter of CAAM IP.\n" + " Prevent the generation of blobs usable to decrypt an\n" + " encrypted boot image." +); diff --git a/arch/arm/mach-imx/sci/Makefile b/arch/arm/mach-imx/sci/Makefile new file mode 100644 index 00000000000..53f3d76fd17 --- /dev/null +++ b/arch/arm/mach-imx/sci/Makefile @@ -0,0 +1,13 @@ +# Copyright 2015, Freescale Semiconductor +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ipc.o +obj-y += svc/misc/rpc_clnt.o +obj-y += svc/pad/rpc_clnt.o +obj-y += svc/pm/rpc_clnt.o +obj-y += svc/rm/rpc_clnt.o +obj-y += svc/timer/rpc_clnt.o +obj-y += svc/seco/rpc_clnt.o diff --git a/arch/arm/mach-imx/sci/ipc.c b/arch/arm/mach-imx/sci/ipc.c new file mode 100644 index 00000000000..a7a97774717 --- /dev/null +++ b/arch/arm/mach-imx/sci/ipc.c @@ -0,0 +1,144 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*==========================================================================*/ +/*! + * @file ipc.c + * + * Implementation of the IPC functions using MUs (client side). + */ +/*==========================================================================*/ + +/* Includes */ + +#include +#include +#include +#include + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +/* Local Variables */ + + +/*----------------------------------------------------------------------*/ +/* RPC command/response */ +/*----------------------------------------------------------------------*/ +void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp) +{ + sc_ipc_write(ipc, msg); + if (!no_resp) + sc_ipc_read(ipc, msg); +} + +/*--------------------------------------------------------------------------*/ +/* Open an IPC channel */ +/*--------------------------------------------------------------------------*/ +sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id) +{ + MU_Type *base = (MU_Type*) id; + uint32_t i; + + /* Get MU base associated with IPC channel */ + if ((ipc == NULL) || (base == NULL)) + return SC_ERR_IPC; + + /* Init MU */ + MU_HAL_Init(base); + + /* Enable all RX interrupts */ + for (i = 0; i < MU_RR_COUNT; i++) + { + MU_HAL_EnableRxFullInt(base, i); + } + + /* Return MU address as handle */ + *ipc = (sc_ipc_t) id; + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Close an IPC channel */ +/*--------------------------------------------------------------------------*/ +void sc_ipc_close(sc_ipc_t ipc) +{ + MU_Type *base = (MU_Type*) ipc; + + if (base != NULL) + MU_HAL_Init(base); + } + +/*--------------------------------------------------------------------------*/ +/* Read message from an IPC channel */ +/*--------------------------------------------------------------------------*/ +void sc_ipc_read(sc_ipc_t ipc, void *data) +{ + MU_Type *base = (MU_Type*) ipc; + sc_rpc_msg_t *msg = (sc_rpc_msg_t*) data; + uint8_t count = 0; + + /* Check parms */ + if ((base == NULL) || (msg == NULL)) + return; + + /* Read first word */ + MU_HAL_ReceiveMsg(base, 0, (uint32_t*) msg); + count++; + + /* Check size */ + if (msg->size > SC_RPC_MAX_MSG) + { + *((uint32_t*) msg) = 0; + return; + } + + /* Read remaining words */ + while (count < msg->size) + { + MU_HAL_ReceiveMsg(base, count % MU_RR_COUNT, + &(msg->DATA.u32[count - 1])); + + count++; + } +} + +/*--------------------------------------------------------------------------*/ +/* Write a message to an IPC channel */ +/*--------------------------------------------------------------------------*/ +void sc_ipc_write(sc_ipc_t ipc, const void *data) +{ + MU_Type *base = (MU_Type*) ipc; + sc_rpc_msg_t *msg = (sc_rpc_msg_t*) data; + uint8_t count = 0; + + /* Check parms */ + if ((base == NULL) || (msg == NULL)) + return; + + /* Check size */ + if (msg->size > SC_RPC_MAX_MSG) + return; + + /* Write first word */ + MU_HAL_SendMsg(base, 0, *((uint32_t*) msg)); + count++; + + /* Write remaining words */ + while (count < msg->size) + { + MU_HAL_SendMsg(base, count % MU_TR_COUNT, + msg->DATA.u32[count - 1]); + + count++; + } +} + diff --git a/arch/arm/mach-imx/sci/svc/irq/rpc.h b/arch/arm/mach-imx/sci/svc/irq/rpc.h new file mode 100644 index 00000000000..687dc2866d3 --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/irq/rpc.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the IRQ RPC implementation. + * + * @addtogroup IRQ_SVC + * @{ + */ + +#ifndef SC_IRQ_RPC_H +#define SC_IRQ_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC IRQ function calls + */ +/*@{*/ +#define IRQ_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define IRQ_FUNC_ENABLE 1U /*!< Index for irq_enable() RPC call */ +#define IRQ_FUNC_STATUS 2U /*!< Index for irq_status() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming IRQ RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void irq_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_IRQ_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/irq/rpc_clnt.c b/arch/arm/mach-imx/sci/svc/irq/rpc_clnt.c new file mode 100644 index 00000000000..c0cfe16164d --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/irq/rpc_clnt.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the IRQ service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup IRQ_SVC + * @{ + */ + +/* Includes */ + +#include +#include +#include +#include +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t mask, sc_bool_t enable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_IRQ); + RPC_FUNC(&msg) = U8(IRQ_FUNC_ENABLE); + RPC_U32(&msg, 0U) = U32(mask); + RPC_U16(&msg, 4U) = U16(resource); + RPC_U8(&msg, 6U) = U8(group); + RPC_U8(&msg, 7U) = B2U8(enable); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t *status) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_IRQ); + RPC_FUNC(&msg) = U8(IRQ_FUNC_STATUS); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(group); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (status != NULL) + { + *status = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/misc/rpc.h b/arch/arm/mach-imx/sci/svc/misc/rpc.h new file mode 100644 index 00000000000..0a5ff065de6 --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/misc/rpc.h @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the MISC RPC implementation. + * + * @addtogroup MISC_SVC + * @{ + */ + +#ifndef SC_MISC_RPC_H +#define SC_MISC_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC MISC function calls + */ +/*@{*/ +#define MISC_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define MISC_FUNC_SET_CONTROL 1U /*!< Index for misc_set_control() RPC call */ +#define MISC_FUNC_GET_CONTROL 2U /*!< Index for misc_get_control() RPC call */ +#define MISC_FUNC_SET_MAX_DMA_GROUP 4U /*!< Index for misc_set_max_dma_group() RPC call */ +#define MISC_FUNC_SET_DMA_GROUP 5U /*!< Index for misc_set_dma_group() RPC call */ +#define MISC_FUNC_SECO_IMAGE_LOAD 8U /*!< Index for misc_seco_image_load() RPC call */ +#define MISC_FUNC_SECO_AUTHENTICATE 9U /*!< Index for misc_seco_authenticate() RPC call */ +#define MISC_FUNC_SECO_FUSE_WRITE 20U /*!< Index for misc_seco_fuse_write() RPC call */ +#define MISC_FUNC_SECO_ENABLE_DEBUG 21U /*!< Index for misc_seco_enable_debug() RPC call */ +#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U /*!< Index for misc_seco_forward_lifecycle() RPC call */ +#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U /*!< Index for misc_seco_return_lifecycle() RPC call */ +#define MISC_FUNC_SECO_BUILD_INFO 24U /*!< Index for misc_seco_build_info() RPC call */ +#define MISC_FUNC_SECO_CHIP_INFO 25U /*!< Index for misc_seco_chip_info() RPC call */ +#define MISC_FUNC_SECO_ATTEST_MODE 27U /*!< Index for misc_seco_attest_mode() RPC call */ +#define MISC_FUNC_SECO_ATTEST 28U /*!< Index for misc_seco_attest() RPC call */ +#define MISC_FUNC_SECO_GET_ATTEST_PKEY 31U /*!< Index for misc_seco_get_attest_pkey() RPC call */ +#define MISC_FUNC_SECO_GET_ATTEST_SIGN 29U /*!< Index for misc_seco_get_attest_sign() RPC call */ +#define MISC_FUNC_SECO_ATTEST_VERIFY 30U /*!< Index for misc_seco_attest_verify() RPC call */ +#define MISC_FUNC_SECO_COMMIT 32U /*!< Index for misc_seco_commit() RPC call */ +#define MISC_FUNC_DEBUG_OUT 10U /*!< Index for misc_debug_out() RPC call */ +#define MISC_FUNC_WAVEFORM_CAPTURE 6U /*!< Index for misc_waveform_capture() RPC call */ +#define MISC_FUNC_BUILD_INFO 15U /*!< Index for misc_build_info() RPC call */ +#define MISC_FUNC_API_VER 35U /*!< Index for misc_api_ver() RPC call */ +#define MISC_FUNC_UNIQUE_ID 19U /*!< Index for misc_unique_id() RPC call */ +#define MISC_FUNC_SET_ARI 3U /*!< Index for misc_set_ari() RPC call */ +#define MISC_FUNC_BOOT_STATUS 7U /*!< Index for misc_boot_status() RPC call */ +#define MISC_FUNC_BOOT_DONE 14U /*!< Index for misc_boot_done() RPC call */ +#define MISC_FUNC_OTP_FUSE_READ 11U /*!< Index for misc_otp_fuse_read() RPC call */ +#define MISC_FUNC_OTP_FUSE_WRITE 17U /*!< Index for misc_otp_fuse_write() RPC call */ +#define MISC_FUNC_SET_TEMP 12U /*!< Index for misc_set_temp() RPC call */ +#define MISC_FUNC_GET_TEMP 13U /*!< Index for misc_get_temp() RPC call */ +#define MISC_FUNC_GET_BOOT_DEV 16U /*!< Index for misc_get_boot_dev() RPC call */ +#define MISC_FUNC_GET_BOOT_TYPE 33U /*!< Index for misc_get_boot_type() RPC call */ +#define MISC_FUNC_GET_BUTTON_STATUS 18U /*!< Index for misc_get_button_status() RPC call */ +#define MISC_FUNC_ROMPATCH_CHECKSUM 26U /*!< Index for misc_rompatch_checksum() RPC call */ +#define MISC_FUNC_BOARD_IOCTL 34U /*!< Index for misc_board_ioctl() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming MISC RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void misc_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_MISC_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/misc/rpc_clnt.c b/arch/arm/mach-imx/sci/svc/misc/rpc_clnt.c new file mode 100644 index 00000000000..9b278036b27 --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/misc/rpc_clnt.c @@ -0,0 +1,759 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the MISC service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup MISC_SVC + * @{ + */ + +/* Includes */ + +#include +#include +#include +#include +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SET_CONTROL); + RPC_U32(&msg, 0U) = U32(ctrl); + RPC_U32(&msg, 4U) = U32(val); + RPC_U16(&msg, 8U) = U16(resource); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t *val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_GET_CONTROL); + RPC_U32(&msg, 0U) = U32(ctrl); + RPC_U16(&msg, 4U) = U16(resource); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (val != NULL) + { + *val = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_misc_dma_group_t max) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SET_MAX_DMA_GROUP); + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(max); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_dma_group_t group) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SET_DMA_GROUP); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(group); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_IMAGE_LOAD); + RPC_U32(&msg, 0U) = U32(addr_src >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr_src); + RPC_U32(&msg, 8U) = U32(addr_dst >> 32ULL); + RPC_U32(&msg, 12U) = U32(addr_dst); + RPC_U32(&msg, 16U) = U32(len); + RPC_U8(&msg, 20U) = B2U8(fw); + RPC_SIZE(&msg) = 7U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc, + sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_AUTHENTICATE); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_U8(&msg, 8U) = U8(cmd); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_FUSE_WRITE); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ENABLE_DEBUG); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_FORWARD_LIFECYCLE); + RPC_U32(&msg, 0U) = U32(change); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_RETURN_LIFECYCLE); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, + uint32_t *commit) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_BUILD_INFO); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (version != NULL) + { + *version = RPC_U32(&msg, 0U); + } + + if (commit != NULL) + { + *commit = RPC_U32(&msg, 4U); + } + + return; +} + +sc_err_t sc_misc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc, + uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_CHIP_INFO); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (uid_l != NULL) + { + *uid_l = RPC_U32(&msg, 0U); + } + + if (uid_h != NULL) + { + *uid_h = RPC_U32(&msg, 4U); + } + + if (lc != NULL) + { + *lc = RPC_U16(&msg, 8U); + } + + if (monotonic != NULL) + { + *monotonic = RPC_U16(&msg, 10U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ATTEST_MODE); + RPC_U32(&msg, 0U) = U32(mode); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_attest(sc_ipc_t ipc, uint64_t nonce) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ATTEST); + RPC_U32(&msg, 0U) = U32(nonce >> 32ULL); + RPC_U32(&msg, 4U) = U32(nonce); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_GET_ATTEST_PKEY); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_GET_ATTEST_SIGN); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ATTEST_VERIFY); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_commit(sc_ipc_t ipc, uint32_t *info) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_COMMIT); + RPC_U32(&msg, 0U) = *PTR_U32(info); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + *info = RPC_U32(&msg, 0U); + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_DEBUG_OUT); + RPC_U8(&msg, 0U) = U8(ch); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + return; +} + +sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_WAVEFORM_CAPTURE); + RPC_U8(&msg, 0U) = B2U8(enable); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, + uint32_t *commit) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_BUILD_INFO); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (build != NULL) + { + *build = RPC_U32(&msg, 0U); + } + + if (commit != NULL) + { + *commit = RPC_U32(&msg, 4U); + } + + return; +} + +void sc_misc_api_ver(sc_ipc_t ipc, uint16_t *cl_maj, + uint16_t *cl_min, uint16_t *sv_maj, uint16_t *sv_min) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_API_VER); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (cl_maj != NULL) + { + *cl_maj = SCFW_API_VERSION_MAJOR; + } + + if (cl_min != NULL) + { + *cl_min = SCFW_API_VERSION_MINOR; + } + + if (sv_maj != NULL) + { + *sv_maj = RPC_U16(&msg, 4U); + } + + if (sv_min != NULL) + { + *sv_min = RPC_U16(&msg, 6U); + } + + return; +} + +void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, + uint32_t *id_h) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_UNIQUE_ID); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (id_l != NULL) + { + *id_l = RPC_U32(&msg, 0U); + } + + if (id_h != NULL) + { + *id_h = RPC_U32(&msg, 4U); + } + + return; +} + +sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SET_ARI); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U16(&msg, 2U) = U16(resource_mst); + RPC_U16(&msg, 4U) = U16(ari); + RPC_U8(&msg, 6U) = B2U8(enable); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_BOOT_STATUS); + RPC_U8(&msg, 0U) = U8(status); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_TRUE); + + return; +} + +sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_BOOT_DONE); + RPC_U16(&msg, 0U) = U16(cpu); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_OTP_FUSE_READ); + RPC_U32(&msg, 0U) = U32(word); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (val != NULL) + { + *val = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_OTP_FUSE_WRITE); + RPC_U32(&msg, 0U) = U32(word); + RPC_U32(&msg, 4U) = U32(val); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t celsius, int8_t tenths) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SET_TEMP); + RPC_U16(&msg, 0U) = U16(resource); + RPC_I16(&msg, 2U) = I16(celsius); + RPC_U8(&msg, 4U) = U8(temp); + RPC_I8(&msg, 5U) = I8(tenths); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_GET_TEMP); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(temp); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (celsius != NULL) + { + *celsius = RPC_I16(&msg, 0U); + } + + result = RPC_R8(&msg); + if (tenths != NULL) + { + *tenths = RPC_I8(&msg, 2U); + } + + return (sc_err_t) result; +} + +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BOOT_DEV); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (dev != NULL) + { + *dev = RPC_U16(&msg, 0U); + } + + return; +} + +sc_err_t sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BOOT_TYPE); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (type != NULL) + { + *type = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BUTTON_STATUS); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (status != NULL) + { + *status = U2B(RPC_U8(&msg, 0U)); + } + + return; +} + +sc_err_t sc_misc_rompatch_checksum(sc_ipc_t ipc, uint32_t *checksum) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_ROMPATCH_CHECKSUM); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (checksum != NULL) + { + *checksum = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_board_ioctl(sc_ipc_t ipc, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_BOARD_IOCTL); + RPC_U32(&msg, 0U) = *PTR_U32(parm1); + RPC_U32(&msg, 4U) = *PTR_U32(parm2); + RPC_U32(&msg, 8U) = *PTR_U32(parm3); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + *parm1 = RPC_U32(&msg, 0U); + *parm2 = RPC_U32(&msg, 4U); + *parm3 = RPC_U32(&msg, 8U); + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/pad/rpc.h b/arch/arm/mach-imx/sci/svc/pad/rpc.h new file mode 100644 index 00000000000..4589e1f801f --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/pad/rpc.h @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the PAD RPC implementation. + * + * @addtogroup PAD_SVC + * @{ + */ + +#ifndef SC_PAD_RPC_H +#define SC_PAD_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC PAD function calls + */ +/*@{*/ +#define PAD_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define PAD_FUNC_SET_MUX 1U /*!< Index for pad_set_mux() RPC call */ +#define PAD_FUNC_GET_MUX 6U /*!< Index for pad_get_mux() RPC call */ +#define PAD_FUNC_SET_GP 2U /*!< Index for pad_set_gp() RPC call */ +#define PAD_FUNC_GET_GP 7U /*!< Index for pad_get_gp() RPC call */ +#define PAD_FUNC_SET_WAKEUP 4U /*!< Index for pad_set_wakeup() RPC call */ +#define PAD_FUNC_GET_WAKEUP 9U /*!< Index for pad_get_wakeup() RPC call */ +#define PAD_FUNC_SET_ALL 5U /*!< Index for pad_set_all() RPC call */ +#define PAD_FUNC_GET_ALL 10U /*!< Index for pad_get_all() RPC call */ +#define PAD_FUNC_SET 15U /*!< Index for pad_set() RPC call */ +#define PAD_FUNC_GET 16U /*!< Index for pad_get() RPC call */ +#define PAD_FUNC_SET_GP_28FDSOI 11U /*!< Index for pad_set_gp_28fdsoi() RPC call */ +#define PAD_FUNC_GET_GP_28FDSOI 12U /*!< Index for pad_get_gp_28fdsoi() RPC call */ +#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U /*!< Index for pad_set_gp_28fdsoi_hsic() RPC call */ +#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U /*!< Index for pad_get_gp_28fdsoi_hsic() RPC call */ +#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U /*!< Index for pad_set_gp_28fdsoi_comp() RPC call */ +#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U /*!< Index for pad_get_gp_28fdsoi_comp() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming PAD RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void pad_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_PAD_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/pad/rpc_clnt.c b/arch/arm/mach-imx/sci/svc/pad/rpc_clnt.c new file mode 100644 index 00000000000..8e67c95e2cb --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/pad/rpc_clnt.c @@ -0,0 +1,475 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the PAD service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup PAD_SVC + * @{ + */ + +/* Includes */ + +#include +#include +#include +#include +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_MUX); + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(mux); + RPC_U8(&msg, 3U) = U8(config); + RPC_U8(&msg, 4U) = U8(iso); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_MUX); + RPC_U16(&msg, 0U) = U16(pad); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mux != NULL) + { + *mux = RPC_U8(&msg, 0U); + } + + if (config != NULL) + { + *config = RPC_U8(&msg, 1U); + } + + if (iso != NULL) + { + *iso = RPC_U8(&msg, 2U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP); + RPC_U32(&msg, 0U) = U32(ctrl); + RPC_U16(&msg, 4U) = U16(pad); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP); + RPC_U16(&msg, 0U) = U16(pad); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (ctrl != NULL) + { + *ctrl = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t wakeup) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_WAKEUP); + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(wakeup); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t *wakeup) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_WAKEUP); + RPC_U16(&msg, 0U) = U16(pad); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (wakeup != NULL) + { + *wakeup = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, + sc_pad_wakeup_t wakeup) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_ALL); + RPC_U32(&msg, 0U) = U32(ctrl); + RPC_U16(&msg, 4U) = U16(pad); + RPC_U8(&msg, 6U) = U8(mux); + RPC_U8(&msg, 7U) = U8(config); + RPC_U8(&msg, 8U) = U8(iso); + RPC_U8(&msg, 9U) = U8(wakeup); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl, + sc_pad_wakeup_t *wakeup) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_ALL); + RPC_U16(&msg, 0U) = U16(pad); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (ctrl != NULL) + { + *ctrl = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + if (mux != NULL) + { + *mux = RPC_U8(&msg, 4U); + } + + if (config != NULL) + { + *config = RPC_U8(&msg, 5U); + } + + if (iso != NULL) + { + *iso = RPC_U8(&msg, 6U); + } + + if (wakeup != NULL) + { + *wakeup = RPC_U8(&msg, 7U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET); + RPC_U32(&msg, 0U) = U32(val); + RPC_U16(&msg, 4U) = U16(pad); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET); + RPC_U16(&msg, 0U) = U16(pad); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (val != NULL) + { + *val = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI); + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(dse); + RPC_U8(&msg, 3U) = U8(ps); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI); + RPC_U16(&msg, 0U) = U16(pad); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (dse != NULL) + { + *dse = RPC_U8(&msg, 0U); + } + + if (ps != NULL) + { + *ps = RPC_U8(&msg, 1U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus, + sc_bool_t pke, sc_bool_t pue) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI_HSIC); + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(dse); + RPC_U8(&msg, 3U) = U8(pus); + RPC_U8(&msg, 4U) = B2U8(hys); + RPC_U8(&msg, 5U) = B2U8(pke); + RPC_U8(&msg, 6U) = B2U8(pue); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus, + sc_bool_t *pke, sc_bool_t *pue) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI_HSIC); + RPC_U16(&msg, 0U) = U16(pad); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (dse != NULL) + { + *dse = RPC_U8(&msg, 0U); + } + + if (pus != NULL) + { + *pus = RPC_U8(&msg, 1U); + } + + if (hys != NULL) + { + *hys = U2B(RPC_U8(&msg, 2U)); + } + + if (pke != NULL) + { + *pke = U2B(RPC_U8(&msg, 3U)); + } + + if (pue != NULL) + { + *pue = U2B(RPC_U8(&msg, 4U)); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn, + sc_bool_t nasrc_sel, sc_bool_t psw_ovr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI_COMP); + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(compen); + RPC_U8(&msg, 3U) = U8(rasrcp); + RPC_U8(&msg, 4U) = U8(rasrcn); + RPC_U8(&msg, 5U) = B2U8(fastfrz); + RPC_U8(&msg, 6U) = B2U8(nasrc_sel); + RPC_U8(&msg, 7U) = B2U8(psw_ovr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn, + sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI_COMP); + RPC_U16(&msg, 0U) = U16(pad); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (compen != NULL) + { + *compen = RPC_U8(&msg, 0U); + } + + if (rasrcp != NULL) + { + *rasrcp = RPC_U8(&msg, 1U); + } + + if (rasrcn != NULL) + { + *rasrcn = RPC_U8(&msg, 2U); + } + + if (nasrc != NULL) + { + *nasrc = RPC_U8(&msg, 3U); + } + + if (fastfrz != NULL) + { + *fastfrz = U2B(RPC_U8(&msg, 4U)); + } + + if (nasrc_sel != NULL) + { + *nasrc_sel = U2B(RPC_U8(&msg, 5U)); + } + + if (compok != NULL) + { + *compok = U2B(RPC_U8(&msg, 6U)); + } + + if (psw_ovr != NULL) + { + *psw_ovr = U2B(RPC_U8(&msg, 7U)); + } + + return (sc_err_t) result; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/pm/rpc.h b/arch/arm/mach-imx/sci/svc/pm/rpc.h new file mode 100644 index 00000000000..d219b6a9605 --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/pm/rpc.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the PM RPC implementation. + * + * @addtogroup PM_SVC + * @{ + */ + +#ifndef SC_PM_RPC_H +#define SC_PM_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC PM function calls + */ +/*@{*/ +#define PM_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define PM_FUNC_SET_SYS_POWER_MODE 19U /*!< Index for pm_set_sys_power_mode() RPC call */ +#define PM_FUNC_SET_PARTITION_POWER_MODE 1U /*!< Index for pm_set_partition_power_mode() RPC call */ +#define PM_FUNC_GET_SYS_POWER_MODE 2U /*!< Index for pm_get_sys_power_mode() RPC call */ +#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U /*!< Index for pm_set_resource_power_mode() RPC call */ +#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL 22U /*!< Index for pm_set_resource_power_mode_all() RPC call */ +#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U /*!< Index for pm_get_resource_power_mode() RPC call */ +#define PM_FUNC_REQ_LOW_POWER_MODE 16U /*!< Index for pm_req_low_power_mode() RPC call */ +#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U /*!< Index for pm_req_cpu_low_power_mode() RPC call */ +#define PM_FUNC_SET_CPU_RESUME_ADDR 17U /*!< Index for pm_set_cpu_resume_addr() RPC call */ +#define PM_FUNC_SET_CPU_RESUME 21U /*!< Index for pm_set_cpu_resume() RPC call */ +#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U /*!< Index for pm_req_sys_if_power_mode() RPC call */ +#define PM_FUNC_SET_CLOCK_RATE 5U /*!< Index for pm_set_clock_rate() RPC call */ +#define PM_FUNC_GET_CLOCK_RATE 6U /*!< Index for pm_get_clock_rate() RPC call */ +#define PM_FUNC_CLOCK_ENABLE 7U /*!< Index for pm_clock_enable() RPC call */ +#define PM_FUNC_SET_CLOCK_PARENT 14U /*!< Index for pm_set_clock_parent() RPC call */ +#define PM_FUNC_GET_CLOCK_PARENT 15U /*!< Index for pm_get_clock_parent() RPC call */ +#define PM_FUNC_RESET 13U /*!< Index for pm_reset() RPC call */ +#define PM_FUNC_RESET_REASON 10U /*!< Index for pm_reset_reason() RPC call */ +#define PM_FUNC_GET_RESET_PART 26U /*!< Index for pm_get_reset_part() RPC call */ +#define PM_FUNC_BOOT 8U /*!< Index for pm_boot() RPC call */ +#define PM_FUNC_SET_BOOT_PARM 27U /*!< Index for pm_set_boot_parm() RPC call */ +#define PM_FUNC_REBOOT 9U /*!< Index for pm_reboot() RPC call */ +#define PM_FUNC_REBOOT_PARTITION 12U /*!< Index for pm_reboot_partition() RPC call */ +#define PM_FUNC_REBOOT_CONTINUE 25U /*!< Index for pm_reboot_continue() RPC call */ +#define PM_FUNC_CPU_START 11U /*!< Index for pm_cpu_start() RPC call */ +#define PM_FUNC_CPU_RESET 23U /*!< Index for pm_cpu_reset() RPC call */ +#define PM_FUNC_IS_PARTITION_STARTED 24U /*!< Index for pm_is_partition_started() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming PM RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void pm_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_PM_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/pm/rpc_clnt.c b/arch/arm/mach-imx/sci/svc/pm/rpc_clnt.c new file mode 100644 index 00000000000..91bdeda57e7 --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/pm/rpc_clnt.c @@ -0,0 +1,575 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the PM service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup PM_SVC + * @{ + */ + +/* Includes */ + +#include +#include +#include +#include +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_SYS_POWER_MODE); + RPC_U8(&msg, 0U) = U8(mode); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_PARTITION_POWER_MODE); + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(mode); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t *mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_GET_SYS_POWER_MODE); + RPC_U8(&msg, 0U) = U8(pt); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mode != NULL) + { + *mode = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_RESOURCE_POWER_MODE); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(mode); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_resource_power_mode_all(sc_ipc_t ipc, + sc_rm_pt_t pt, sc_pm_power_mode_t mode, sc_rsrc_t exclude) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_RESOURCE_POWER_MODE_ALL); + RPC_U16(&msg, 0U) = U16(exclude); + RPC_U8(&msg, 2U) = U8(pt); + RPC_U8(&msg, 3U) = U8(mode); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_GET_RESOURCE_POWER_MODE); + RPC_U16(&msg, 0U) = U16(resource); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mode != NULL) + { + *mode = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REQ_LOW_POWER_MODE); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(mode); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REQ_CPU_LOW_POWER_MODE); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(mode); + RPC_U8(&msg, 3U) = U8(wake_src); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource, + sc_faddr_t address) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_CPU_RESUME_ADDR); + RPC_U32(&msg, 0U) = U32(address >> 32ULL); + RPC_U32(&msg, 4U) = U32(address); + RPC_U16(&msg, 8U) = U16(resource); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t isPrimary, sc_faddr_t address) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_CPU_RESUME); + RPC_U32(&msg, 0U) = U32(address >> 32ULL); + RPC_U32(&msg, 4U) = U32(address); + RPC_U16(&msg, 8U) = U16(resource); + RPC_U8(&msg, 10U) = B2U8(isPrimary); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REQ_SYS_IF_POWER_MODE); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(sys_if); + RPC_U8(&msg, 3U) = U8(hpm); + RPC_U8(&msg, 4U) = U8(lpm); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_CLOCK_RATE); + RPC_U32(&msg, 0U) = *PTR_U32(rate); + RPC_U16(&msg, 4U) = U16(resource); + RPC_U8(&msg, 6U) = U8(clk); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + *rate = RPC_U32(&msg, 0U); + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_GET_CLOCK_RATE); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(clk); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (rate != NULL) + { + *rate = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_CLOCK_ENABLE); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(clk); + RPC_U8(&msg, 3U) = B2U8(enable); + RPC_U8(&msg, 4U) = B2U8(autog); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t parent) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_CLOCK_PARENT); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(clk); + RPC_U8(&msg, 3U) = U8(parent); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_GET_CLOCK_PARENT); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(clk); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (parent != NULL) + { + *parent = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_RESET); + RPC_U8(&msg, 0U) = U8(type); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_RESET_REASON); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (reason != NULL) + { + *reason = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pm_get_reset_part(sc_ipc_t ipc, sc_rm_pt_t *pt) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_GET_RESET_PART); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (pt != NULL) + { + *pt = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_BOOT); + RPC_U32(&msg, 0U) = U32(boot_addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(boot_addr); + RPC_U16(&msg, 8U) = U16(resource_cpu); + RPC_U16(&msg, 10U) = U16(resource_mu); + RPC_U16(&msg, 12U) = U16(resource_dev); + RPC_U8(&msg, 14U) = U8(pt); + RPC_SIZE(&msg) = 5U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_boot_parm(sc_ipc_t ipc, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_BOOT_PARM); + RPC_U32(&msg, 0U) = U32(boot_addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(boot_addr); + RPC_U16(&msg, 8U) = U16(resource_cpu); + RPC_U16(&msg, 10U) = U16(resource_mu); + RPC_U16(&msg, 12U) = U16(resource_dev); + RPC_SIZE(&msg) = 5U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REBOOT); + RPC_U8(&msg, 0U) = U8(type); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_TRUE); + + return; +} + +sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_reset_type_t type) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REBOOT_PARTITION); + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(type); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_reboot_continue(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REBOOT_CONTINUE); + RPC_U8(&msg, 0U) = U8(pt); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_CPU_START); + RPC_U32(&msg, 0U) = U32(address >> 32ULL); + RPC_U32(&msg, 4U) = U32(address); + RPC_U16(&msg, 8U) = U16(resource); + RPC_U8(&msg, 10U) = B2U8(enable); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +void sc_pm_cpu_reset(sc_ipc_t ipc, sc_rsrc_t resource, sc_faddr_t address) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_CPU_RESET); + RPC_U32(&msg, 0U) = U32(address >> 32ULL); + RPC_U32(&msg, 4U) = U32(address); + RPC_U16(&msg, 8U) = U16(resource); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_TRUE); + + return; +} + +sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_IS_PARTITION_STARTED); + RPC_U8(&msg, 0U) = U8(pt); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = U2B(RPC_R8(&msg)); + return result; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/rm/rpc.h b/arch/arm/mach-imx/sci/svc/rm/rpc.h new file mode 100644 index 00000000000..d8b86fd1aa7 --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/rm/rpc.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the RM RPC implementation. + * + * @addtogroup RM_SVC + * @{ + */ + +#ifndef SC_RM_RPC_H +#define SC_RM_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC RM function calls + */ +/*@{*/ +#define RM_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define RM_FUNC_PARTITION_ALLOC 1U /*!< Index for rm_partition_alloc() RPC call */ +#define RM_FUNC_SET_CONFIDENTIAL 31U /*!< Index for rm_set_confidential() RPC call */ +#define RM_FUNC_PARTITION_FREE 2U /*!< Index for rm_partition_free() RPC call */ +#define RM_FUNC_GET_DID 26U /*!< Index for rm_get_did() RPC call */ +#define RM_FUNC_PARTITION_STATIC 3U /*!< Index for rm_partition_static() RPC call */ +#define RM_FUNC_PARTITION_LOCK 4U /*!< Index for rm_partition_lock() RPC call */ +#define RM_FUNC_GET_PARTITION 5U /*!< Index for rm_get_partition() RPC call */ +#define RM_FUNC_SET_PARENT 6U /*!< Index for rm_set_parent() RPC call */ +#define RM_FUNC_MOVE_ALL 7U /*!< Index for rm_move_all() RPC call */ +#define RM_FUNC_ASSIGN_RESOURCE 8U /*!< Index for rm_assign_resource() RPC call */ +#define RM_FUNC_SET_RESOURCE_MOVABLE 9U /*!< Index for rm_set_resource_movable() RPC call */ +#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U /*!< Index for rm_set_subsys_rsrc_movable() RPC call */ +#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U /*!< Index for rm_set_master_attributes() RPC call */ +#define RM_FUNC_SET_MASTER_SID 11U /*!< Index for rm_set_master_sid() RPC call */ +#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U /*!< Index for rm_set_peripheral_permissions() RPC call */ +#define RM_FUNC_IS_RESOURCE_OWNED 13U /*!< Index for rm_is_resource_owned() RPC call */ +#define RM_FUNC_GET_RESOURCE_OWNER 33U /*!< Index for rm_get_resource_owner() RPC call */ +#define RM_FUNC_IS_RESOURCE_MASTER 14U /*!< Index for rm_is_resource_master() RPC call */ +#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U /*!< Index for rm_is_resource_peripheral() RPC call */ +#define RM_FUNC_GET_RESOURCE_INFO 16U /*!< Index for rm_get_resource_info() RPC call */ +#define RM_FUNC_MEMREG_ALLOC 17U /*!< Index for rm_memreg_alloc() RPC call */ +#define RM_FUNC_MEMREG_SPLIT 29U /*!< Index for rm_memreg_split() RPC call */ +#define RM_FUNC_MEMREG_FRAG 32U /*!< Index for rm_memreg_frag() RPC call */ +#define RM_FUNC_MEMREG_FREE 18U /*!< Index for rm_memreg_free() RPC call */ +#define RM_FUNC_FIND_MEMREG 30U /*!< Index for rm_find_memreg() RPC call */ +#define RM_FUNC_ASSIGN_MEMREG 19U /*!< Index for rm_assign_memreg() RPC call */ +#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U /*!< Index for rm_set_memreg_permissions() RPC call */ +#define RM_FUNC_IS_MEMREG_OWNED 21U /*!< Index for rm_is_memreg_owned() RPC call */ +#define RM_FUNC_GET_MEMREG_INFO 22U /*!< Index for rm_get_memreg_info() RPC call */ +#define RM_FUNC_ASSIGN_PAD 23U /*!< Index for rm_assign_pad() RPC call */ +#define RM_FUNC_SET_PAD_MOVABLE 24U /*!< Index for rm_set_pad_movable() RPC call */ +#define RM_FUNC_IS_PAD_OWNED 25U /*!< Index for rm_is_pad_owned() RPC call */ +#define RM_FUNC_DUMP 27U /*!< Index for rm_dump() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming RM RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void rm_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_RM_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/rm/rpc_clnt.c b/arch/arm/mach-imx/sci/svc/rm/rpc_clnt.c new file mode 100644 index 00000000000..45773545fe5 --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/rm/rpc_clnt.c @@ -0,0 +1,694 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the RM service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup RM_SVC + * @{ + */ + +/* Includes */ + +#include +#include +#include +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t coherent) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_ALLOC); + RPC_U8(&msg, 0U) = B2U8(secure); + RPC_U8(&msg, 1U) = B2U8(isolated); + RPC_U8(&msg, 2U) = B2U8(restricted); + RPC_U8(&msg, 3U) = B2U8(grant); + RPC_U8(&msg, 4U) = B2U8(coherent); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (pt != NULL) + { + *pt = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_CONFIDENTIAL); + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = B2U8(retro); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_FREE); + RPC_U8(&msg, 0U) = U8(pt); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_GET_DID); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_rm_did_t) result; +} + +sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_did_t did) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_STATIC); + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(did); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_LOCK); + RPC_U8(&msg, 0U) = U8(pt); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_GET_PARTITION); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (pt != NULL) + { + *pt = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_pt_t pt_parent) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_PARENT); + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(pt_parent); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst, + sc_bool_t move_rsrc, sc_bool_t move_pads) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_MOVE_ALL); + RPC_U8(&msg, 0U) = U8(pt_src); + RPC_U8(&msg, 1U) = U8(pt_dst); + RPC_U8(&msg, 2U) = B2U8(move_rsrc); + RPC_U8(&msg, 3U) = B2U8(move_pads); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_RESOURCE); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(pt); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst, + sc_rsrc_t resource_lst, sc_bool_t movable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_RESOURCE_MOVABLE); + RPC_U16(&msg, 0U) = U16(resource_fst); + RPC_U16(&msg, 2U) = U16(resource_lst); + RPC_U8(&msg, 4U) = B2U8(movable); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t movable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_SUBSYS_RSRC_MOVABLE); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = B2U8(movable); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_MASTER_ATTRIBUTES); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(sa); + RPC_U8(&msg, 3U) = U8(pa); + RPC_U8(&msg, 4U) = B2U8(smmu_bypass); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t sid) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_MASTER_SID); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U16(&msg, 2U) = U16(sid); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t pt, sc_rm_perm_t perm) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_PERIPHERAL_PERMISSIONS); + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(pt); + RPC_U8(&msg, 3U) = U8(perm); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_OWNED); + RPC_U16(&msg, 0U) = U16(resource); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = U2B(RPC_R8(&msg)); + return result; +} + +sc_err_t sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t *pt) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_GET_RESOURCE_OWNER); + RPC_U16(&msg, 0U) = U16(resource); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (pt != NULL) + { + *pt = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_MASTER); + RPC_U16(&msg, 0U) = U16(resource); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = U2B(RPC_R8(&msg)); + return result; +} + +sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_PERIPHERAL); + RPC_U16(&msg, 0U) = U16(resource); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = U2B(RPC_R8(&msg)); + return result; +} + +sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t *sid) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_GET_RESOURCE_INFO); + RPC_U16(&msg, 0U) = U16(resource); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (sid != NULL) + { + *sid = RPC_U16(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_ALLOC); + RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr_start); + RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL); + RPC_U32(&msg, 12U) = U32(addr_end); + RPC_SIZE(&msg) = 5U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mr != NULL) + { + *mr = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_SPLIT); + RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr_start); + RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL); + RPC_U32(&msg, 12U) = U32(addr_end); + RPC_U8(&msg, 16U) = U8(mr); + RPC_SIZE(&msg) = 6U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mr_ret != NULL) + { + *mr_ret = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_rm_memreg_frag(sc_ipc_t ipc, sc_rm_mr_t *mr_ret, + sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_FRAG); + RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr_start); + RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL); + RPC_U32(&msg, 12U) = U32(addr_end); + RPC_SIZE(&msg) = 5U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mr_ret != NULL) + { + *mr_ret = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_FREE); + RPC_U8(&msg, 0U) = U8(mr); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_FIND_MEMREG); + RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr_start); + RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL); + RPC_U32(&msg, 12U) = U32(addr_end); + RPC_SIZE(&msg) = 5U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mr != NULL) + { + *mr = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_MEMREG); + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(mr); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_MEMREG_PERMISSIONS); + RPC_U8(&msg, 0U) = U8(mr); + RPC_U8(&msg, 1U) = U8(pt); + RPC_U8(&msg, 2U) = U8(perm); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_IS_MEMREG_OWNED); + RPC_U8(&msg, 0U) = U8(mr); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = U2B(RPC_R8(&msg)); + return result; +} + +sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_faddr_t *addr_start, sc_faddr_t *addr_end) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_GET_MEMREG_INFO); + RPC_U8(&msg, 0U) = U8(mr); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (addr_start != NULL) + { + *addr_start = ((uint64_t) RPC_U32(&msg, 0U) << 32U) | RPC_U32(&msg, 4U); + } + + if (addr_end != NULL) + { + *addr_end = ((uint64_t) RPC_U32(&msg, 8U) << 32U) | RPC_U32(&msg, 12U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_PAD); + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(pt); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst, + sc_pad_t pad_lst, sc_bool_t movable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_PAD_MOVABLE); + RPC_U16(&msg, 0U) = U16(pad_fst); + RPC_U16(&msg, 2U) = U16(pad_lst); + RPC_U8(&msg, 4U) = B2U8(movable); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_IS_PAD_OWNED); + RPC_U8(&msg, 0U) = U8(pad); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = U2B(RPC_R8(&msg)); + return result; +} + +void sc_rm_dump(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_DUMP); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + return; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/seco/rpc.h b/arch/arm/mach-imx/sci/svc/seco/rpc.h new file mode 100644 index 00000000000..cfc742cf936 --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/seco/rpc.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the SECO RPC implementation. + * + * @addtogroup SECO_SVC + * @{ + */ + +#ifndef SC_SECO_RPC_H +#define SC_SECO_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC SECO function calls + */ +/*@{*/ +#define SECO_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define SECO_FUNC_IMAGE_LOAD 1U /*!< Index for seco_image_load() RPC call */ +#define SECO_FUNC_AUTHENTICATE 2U /*!< Index for seco_authenticate() RPC call */ +#define SECO_FUNC_FORWARD_LIFECYCLE 3U /*!< Index for seco_forward_lifecycle() RPC call */ +#define SECO_FUNC_RETURN_LIFECYCLE 4U /*!< Index for seco_return_lifecycle() RPC call */ +#define SECO_FUNC_COMMIT 5U /*!< Index for seco_commit() RPC call */ +#define SECO_FUNC_ATTEST_MODE 6U /*!< Index for seco_attest_mode() RPC call */ +#define SECO_FUNC_ATTEST 7U /*!< Index for seco_attest() RPC call */ +#define SECO_FUNC_GET_ATTEST_PKEY 8U /*!< Index for seco_get_attest_pkey() RPC call */ +#define SECO_FUNC_GET_ATTEST_SIGN 9U /*!< Index for seco_get_attest_sign() RPC call */ +#define SECO_FUNC_ATTEST_VERIFY 10U /*!< Index for seco_attest_verify() RPC call */ +#define SECO_FUNC_GEN_KEY_BLOB 11U /*!< Index for seco_gen_key_blob() RPC call */ +#define SECO_FUNC_LOAD_KEY 12U /*!< Index for seco_load_key() RPC call */ +#define SECO_FUNC_GET_MP_KEY 13U /*!< Index for seco_get_mp_key() RPC call */ +#define SECO_FUNC_UPDATE_MPMR 14U /*!< Index for seco_update_mpmr() RPC call */ +#define SECO_FUNC_GET_MP_SIGN 15U /*!< Index for seco_get_mp_sign() RPC call */ +#define SECO_FUNC_BUILD_INFO 16U /*!< Index for seco_build_info() RPC call */ +#define SECO_FUNC_CHIP_INFO 17U /*!< Index for seco_chip_info() RPC call */ +#define SECO_FUNC_ENABLE_DEBUG 18U /*!< Index for seco_enable_debug() RPC call */ +#define SECO_FUNC_GET_EVENT 19U /*!< Index for seco_get_event() RPC call */ +#define SECO_FUNC_FUSE_WRITE 20U /*!< Index for seco_fuse_write() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming SECO RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void seco_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_SECO_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/seco/rpc_clnt.c b/arch/arm/mach-imx/sci/svc/seco/rpc_clnt.c new file mode 100644 index 00000000000..ec3231bcc64 --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/seco/rpc_clnt.c @@ -0,0 +1,444 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the SECO service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup SECO_SVC + * @{ + */ + +/* Includes */ + +#include +#include +#include +#include +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_IMAGE_LOAD); + RPC_U32(&msg, 0U) = U32(addr_src >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr_src); + RPC_U32(&msg, 8U) = U32(addr_dst >> 32ULL); + RPC_U32(&msg, 12U) = U32(addr_dst); + RPC_U32(&msg, 16U) = U32(len); + RPC_U8(&msg, 20U) = B2U8(fw); + RPC_SIZE(&msg) = 7U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_authenticate(sc_ipc_t ipc, + sc_seco_auth_cmd_t cmd, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_AUTHENTICATE); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_U8(&msg, 8U) = U8(cmd); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_FORWARD_LIFECYCLE); + RPC_U32(&msg, 0U) = U32(change); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_RETURN_LIFECYCLE); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_commit(sc_ipc_t ipc, uint32_t *info) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_COMMIT); + RPC_U32(&msg, 0U) = *PTR_U32(info); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + *info = RPC_U32(&msg, 0U); + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_ATTEST_MODE); + RPC_U32(&msg, 0U) = U32(mode); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_attest(sc_ipc_t ipc, uint64_t nonce) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_ATTEST); + RPC_U32(&msg, 0U) = U32(nonce >> 32ULL); + RPC_U32(&msg, 4U) = U32(nonce); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GET_ATTEST_PKEY); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GET_ATTEST_SIGN); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_ATTEST_VERIFY); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_gen_key_blob(sc_ipc_t ipc, uint32_t id, + sc_faddr_t load_addr, sc_faddr_t export_addr, uint16_t max_size) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GEN_KEY_BLOB); + RPC_U32(&msg, 0U) = U32(load_addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(load_addr); + RPC_U32(&msg, 8U) = U32(export_addr >> 32ULL); + RPC_U32(&msg, 12U) = U32(export_addr); + RPC_U32(&msg, 16U) = U32(id); + RPC_U16(&msg, 20U) = U16(max_size); + RPC_SIZE(&msg) = 7U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_load_key(sc_ipc_t ipc, uint32_t id, + sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_LOAD_KEY); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_U32(&msg, 8U) = U32(id); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, + uint16_t dst_size) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GET_MP_KEY); + RPC_U32(&msg, 0U) = U32(dst_addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(dst_addr); + RPC_U16(&msg, 8U) = U16(dst_size); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, + uint8_t size, uint8_t lock) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_UPDATE_MPMR); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_U8(&msg, 8U) = U8(size); + RPC_U8(&msg, 9U) = U8(lock); + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, + uint16_t msg_size, sc_faddr_t dst_addr, uint16_t dst_size) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GET_MP_SIGN); + RPC_U32(&msg, 0U) = U32(msg_addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(msg_addr); + RPC_U32(&msg, 8U) = U32(dst_addr >> 32ULL); + RPC_U32(&msg, 12U) = U32(dst_addr); + RPC_U16(&msg, 16U) = U16(msg_size); + RPC_U16(&msg, 18U) = U16(dst_size); + RPC_SIZE(&msg) = 6U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +void sc_seco_build_info(sc_ipc_t ipc, uint32_t *version, + uint32_t *commit) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_BUILD_INFO); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (version != NULL) + { + *version = RPC_U32(&msg, 0U); + } + + if (commit != NULL) + { + *commit = RPC_U32(&msg, 4U); + } + + return; +} + +sc_err_t sc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc, + uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_CHIP_INFO); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (uid_l != NULL) + { + *uid_l = RPC_U32(&msg, 0U); + } + + if (uid_h != NULL) + { + *uid_h = RPC_U32(&msg, 4U); + } + + if (lc != NULL) + { + *lc = RPC_U16(&msg, 8U); + } + + if (monotonic != NULL) + { + *monotonic = RPC_U16(&msg, 10U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_ENABLE_DEBUG); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_get_event(sc_ipc_t ipc, uint8_t idx, + uint32_t *event) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GET_EVENT); + RPC_U8(&msg, 0U) = U8(idx); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (event != NULL) + { + *event = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_FUSE_WRITE); + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/timer/rpc.h b/arch/arm/mach-imx/sci/svc/timer/rpc.h new file mode 100644 index 00000000000..c97147c5a30 --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/timer/rpc.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the TIMER RPC implementation. + * + * @addtogroup TIMER_SVC + * @{ + */ + +#ifndef SC_TIMER_RPC_H +#define SC_TIMER_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC TIMER function calls + */ +/*@{*/ +#define TIMER_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /*!< Index for timer_set_wdog_timeout() RPC call */ +#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /*!< Index for timer_set_wdog_pre_timeout() RPC call */ +#define TIMER_FUNC_START_WDOG 2U /*!< Index for timer_start_wdog() RPC call */ +#define TIMER_FUNC_STOP_WDOG 3U /*!< Index for timer_stop_wdog() RPC call */ +#define TIMER_FUNC_PING_WDOG 4U /*!< Index for timer_ping_wdog() RPC call */ +#define TIMER_FUNC_GET_WDOG_STATUS 5U /*!< Index for timer_get_wdog_status() RPC call */ +#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /*!< Index for timer_pt_get_wdog_status() RPC call */ +#define TIMER_FUNC_SET_WDOG_ACTION 10U /*!< Index for timer_set_wdog_action() RPC call */ +#define TIMER_FUNC_SET_RTC_TIME 6U /*!< Index for timer_set_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_TIME 7U /*!< Index for timer_get_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_SEC1970 9U /*!< Index for timer_get_rtc_sec1970() RPC call */ +#define TIMER_FUNC_SET_RTC_ALARM 8U /*!< Index for timer_set_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /*!< Index for timer_set_rtc_periodic_alarm() RPC call */ +#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /*!< Index for timer_cancel_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_CALB 11U /*!< Index for timer_set_rtc_calb() RPC call */ +#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /*!< Index for timer_set_sysctr_alarm() RPC call */ +#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /*!< Index for timer_set_sysctr_periodic_alarm() RPC call */ +#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /*!< Index for timer_cancel_sysctr_alarm() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming TIMER RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void timer_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_TIMER_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/sci/svc/timer/rpc_clnt.c b/arch/arm/mach-imx/sci/svc/timer/rpc_clnt.c new file mode 100644 index 00000000000..b35572726ac --- /dev/null +++ b/arch/arm/mach-imx/sci/svc/timer/rpc_clnt.c @@ -0,0 +1,418 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the TIMER service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup TIMER_SVC + * @{ + */ + +/* Includes */ + +#include +#include +#include +#include +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t timeout) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_TIMEOUT); + RPC_U32(&msg, 0U) = U32(timeout); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t pre_timeout) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_PRE_TIMEOUT); + RPC_U32(&msg, 0U) = U32(pre_timeout); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_START_WDOG); + RPC_U8(&msg, 0U) = B2U8(lock); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_STOP_WDOG); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_PING_WDOG); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout, + sc_timer_wdog_time_t *remaining_time) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_WDOG_STATUS); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (timeout != NULL) + { + *timeout = RPC_U32(&msg, 0U); + } + + if (max_timeout != NULL) + { + *max_timeout = RPC_U32(&msg, 4U); + } + + if (remaining_time != NULL) + { + *remaining_time = RPC_U32(&msg, 8U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t *enb, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_PT_GET_WDOG_STATUS); + RPC_U8(&msg, 0U) = U8(pt); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (timeout != NULL) + { + *timeout = RPC_U32(&msg, 0U); + } + + if (remaining_time != NULL) + { + *remaining_time = RPC_U32(&msg, 4U); + } + + result = RPC_R8(&msg); + if (enb != NULL) + { + *enb = U2B(RPC_U8(&msg, 8U)); + } + + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc, + sc_rm_pt_t pt, sc_timer_wdog_action_t action) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_ACTION); + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(action); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_TIME); + RPC_U16(&msg, 0U) = U16(year); + RPC_U8(&msg, 2U) = U8(mon); + RPC_U8(&msg, 3U) = U8(day); + RPC_U8(&msg, 4U) = U8(hour); + RPC_U8(&msg, 5U) = U8(min); + RPC_U8(&msg, 6U) = U8(sec); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon, + uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_RTC_TIME); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (year != NULL) + { + *year = RPC_U16(&msg, 0U); + } + + result = RPC_R8(&msg); + if (mon != NULL) + { + *mon = RPC_U8(&msg, 2U); + } + + if (day != NULL) + { + *day = RPC_U8(&msg, 3U); + } + + if (hour != NULL) + { + *hour = RPC_U8(&msg, 4U); + } + + if (min != NULL) + { + *min = RPC_U8(&msg, 5U); + } + + if (sec != NULL) + { + *sec = RPC_U8(&msg, 6U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_RTC_SEC1970); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (sec != NULL) + { + *sec = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_ALARM); + RPC_U16(&msg, 0U) = U16(year); + RPC_U8(&msg, 2U) = U8(mon); + RPC_U8(&msg, 3U) = U8(day); + RPC_U8(&msg, 4U) = U8(hour); + RPC_U8(&msg, 5U) = U8(min); + RPC_U8(&msg, 6U) = U8(sec); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_PERIODIC_ALARM); + RPC_U32(&msg, 0U) = U32(sec); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_CANCEL_RTC_ALARM); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_CALB); + RPC_I8(&msg, 0U) = I8(count); + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_sysctr_alarm(sc_ipc_t ipc, uint64_t ticks) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_SYSCTR_ALARM); + RPC_U32(&msg, 0U) = U32(ticks >> 32ULL); + RPC_U32(&msg, 4U) = U32(ticks); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, + uint64_t ticks) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM); + RPC_U32(&msg, 0U) = U32(ticks >> 32ULL); + RPC_U32(&msg, 4U) = U32(ticks); + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_cancel_sysctr_alarm(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_CANCEL_SYSCTR_ALARM); + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/sip.c b/arch/arm/mach-imx/sip.c index b724330d358..c425c25b385 100644 --- a/arch/arm/mach-imx/sip.c +++ b/arch/arm/mach-imx/sip.c @@ -8,7 +8,7 @@ #include unsigned long call_imx_sip(unsigned long id, unsigned long reg0, - unsigned long reg1, unsigned long reg2) + unsigned long reg1, unsigned long reg2, unsigned long reg3) { struct pt_regs regs; @@ -16,8 +16,26 @@ unsigned long call_imx_sip(unsigned long id, unsigned long reg0, regs.regs[1] = reg0; regs.regs[2] = reg1; regs.regs[3] = reg2; + regs.regs[4] = reg3; smc_call(®s); return regs.regs[0]; } + +/* do an SMC call to return 2 registers by having reg1 passed in by reference */ +unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, unsigned long *reg1, unsigned long reg2, unsigned long reg3) +{ + struct pt_regs regs; + + regs.regs[0] = id; + regs.regs[1] = reg0; + regs.regs[2] = *reg1; + regs.regs[3] = reg2; + regs.regs[4] = reg3; + + smc_call(®s); + + *reg1 = regs.regs[1]; + return regs.regs[0]; +} diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index b2521b2101c..3a668687ef6 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -97,13 +97,14 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } -#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M) -/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */ +#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) +/* Translate iMX7/iMX8M boot device to the SPL boot device enumeration */ u32 spl_boot_device(void) { enum boot_device boot_device_spl = get_boot_device(); switch (boot_device_spl) { +#if defined(CONFIG_MX7) case SD1_BOOT: case MMC1_BOOT: case SD2_BOOT: @@ -111,17 +112,45 @@ u32 spl_boot_device(void) case SD3_BOOT: case MMC3_BOOT: return BOOT_DEVICE_MMC1; +#elif defined(CONFIG_IMX8) + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + return BOOT_DEVICE_MMC2_2; + case SD3_BOOT: + return BOOT_DEVICE_MMC1; + case FLEXSPI_BOOT: + return BOOT_DEVICE_SPI; +#elif defined(CONFIG_IMX8M) + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; +#if defined(CONFIG_IMX8MM) + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; +#else + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; +#endif +#endif case NAND_BOOT: return BOOT_DEVICE_NAND; case SPI_NOR_BOOT: return BOOT_DEVICE_SPI; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; case USB_BOOT: - return BOOT_DEVICE_USB; + return BOOT_DEVICE_BOARD; default: return BOOT_DEVICE_NONE; } } -#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */ +#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_IMX8M || CONFIG_IMX8 */ #ifdef CONFIG_SPL_USB_GADGET_SUPPORT int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) @@ -130,12 +159,47 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) return 0; } + +#define SDPV_BCD_DEVICE 0x500 +int g_dnl_get_board_bcd_device_number(int gcnum) +{ + return SDPV_BCD_DEVICE; +} #endif #if defined(CONFIG_SPL_MMC_SUPPORT) /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ u32 spl_boot_mode(const u32 boot_device) { +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) + switch (get_boot_device()) { + /* for MMC return either RAW or FAT mode */ + case SD1_BOOT: + case SD2_BOOT: + case SD3_BOOT: +#if defined(CONFIG_SPL_FAT_SUPPORT) + return MMCSD_MODE_FS; +#else + return MMCSD_MODE_RAW; +#endif + break; + case MMC1_BOOT: + case MMC2_BOOT: + case MMC3_BOOT: +#if defined(CONFIG_SPL_FAT_SUPPORT) + return MMCSD_MODE_FS; +#elif defined(CONFIG_SUPPORT_EMMC_BOOT) + return MMCSD_MODE_EMMCBOOT; +#else + return MMCSD_MODE_RAW; +#endif + break; + default: + puts("spl: ERROR: unsupported device\n"); + hang(); + } + +#else /* defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) */ switch (spl_boot_device()) { /* for MMC return either RAW or FAT mode */ case BOOT_DEVICE_MMC1: @@ -152,6 +216,7 @@ u32 spl_boot_mode(const u32 boot_device) puts("spl: ERROR: unsupported device\n"); hang(); } +#endif } #endif @@ -198,19 +263,59 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) debug("image entry point: 0x%lX\n", spl_image->entry_point); - /* HAB looks for the CSF at the end of the authenticated data therefore, - * we need to subtract the size of the CSF from the actual filesize */ - offset = spl_image->size - CONFIG_CSF_SIZE; - if (!imx_hab_authenticate_image(spl_image->load_addr, - offset + IVT_SIZE + CSF_PAD_SIZE, - offset)) { + if (spl_image->flags & SPL_FIT_FOUND) { image_entry(); } else { + /* HAB looks for the CSF at the end of the authenticated data therefore, + * we need to subtract the size of the CSF from the actual filesize */ + offset = spl_image->size - CONFIG_CSF_SIZE; + if (!imx_hab_authenticate_image(spl_image->load_addr, + offset + IVT_SIZE + CSF_PAD_SIZE, + offset)) { + image_entry(); + } else { + puts("spl: ERROR: image authentication unsuccessful\n"); + hang(); + } + } +} + +ulong board_spl_fit_size_align(ulong size) +{ + /* HAB authenticate_image requests the IVT offset is aligned to 0x1000 */ +#define ALIGN_SIZE 0x1000 + + size = ALIGN(size, ALIGN_SIZE); + size += CONFIG_CSF_SIZE; + + return size; +} + +void board_spl_fit_post_load(ulong load_addr, size_t length) +{ + uint32_t offset = length - CONFIG_CSF_SIZE; + if (imx_hab_authenticate_image(load_addr, + offset + IVT_SIZE + CSF_PAD_SIZE, + offset)) { puts("spl: ERROR: image authentication unsuccessful\n"); hang(); } } +void* board_spl_fit_buffer_addr(ulong fit_size, int bl_len) +{ + int align_len = ARCH_DMA_MINALIGN - 1; + + /* Some devices like SDP, NOR, NAND, SPI are using bl_len =1, so their fit address + * is different with SD/MMC, this cause mismatch with signed address. Thus, adjust + * the bl_len to align with SD/MMC. + */ + if (bl_len < 512) + bl_len = 512; + + return (void *)((CONFIG_SYS_TEXT_BASE - fit_size - bl_len - + align_len) & ~align_len); +} #endif #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) diff --git a/arch/arm/mach-imx/spl_qspi.cfg b/arch/arm/mach-imx/spl_qspi.cfg new file mode 100644 index 00000000000..65fb6a1173e --- /dev/null +++ b/arch/arm/mach-imx/spl_qspi.cfg @@ -0,0 +1,18 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define __ASSEMBLY__ +#include + +IMAGE_VERSION 2 +BOOT_FROM qspi + +/* + * Secure boot support + */ +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c index 69dbf3c2ceb..a199af84ec9 100644 --- a/arch/arm/mach-imx/timer.c +++ b/arch/arm/mach-imx/timer.c @@ -2,7 +2,8 @@ * (C) Copyright 2007 * Sascha Hauer, Pengutronix * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -42,16 +43,12 @@ DECLARE_GLOBAL_DATA_PTR; static inline int gpt_has_clk_source_osc(void) { -#if defined(CONFIG_MX6) if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) || is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() || - is_mx6ull() || is_mx6sll()) + is_mx6ull() || is_mx6sll() || is_mx7()) return 1; return 0; -#else - return 0; -#endif } static inline ulong gpt_get_clk(void) @@ -74,7 +71,8 @@ int timer_init(void) __raw_writel(GPTCR_SWR, &cur_gpt->control); /* We have no udelay by now */ - __raw_writel(0, &cur_gpt->control); + for (i = 0; i < 100; i++) + __raw_writel(0, &cur_gpt->control); i = __raw_readl(&cur_gpt->control); i &= ~GPTCR_CLKSOURCE_MASK; @@ -88,7 +86,7 @@ int timer_init(void) * Enable bit and prescaler */ if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() || - is_mx6sll()) { + is_mx6sll() || is_mx7()) { i |= GPTCR_24MEN; /* Produce 3Mhz clock */ @@ -104,6 +102,9 @@ int timer_init(void) #endif __raw_writel(i, &cur_gpt->control); + gd->arch.tbl = __raw_readl(&cur_gpt->counter); + gd->arch.tbu = 0; + return 0; } diff --git a/arch/arm/mach-imx/trusty.S b/arch/arm/mach-imx/trusty.S new file mode 100644 index 00000000000..2ca9b3c83ad --- /dev/null +++ b/arch/arm/mach-imx/trusty.S @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2009-2016 Freescale Semiconductor, Inc. + * + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +_regs_save: + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + +#ifdef CONFIG_IMX_TRUSTY_OS +ENTRY(trusty_os_init) + isb + + /* Save current registers */ + mov ip, r0 + adr r0, _regs_save + str ip, [r0] + add r0, r0, #4 @ Get _regs_save from instruction offset + + str sp, [r0] + add r0, r0, #4 + + stmia r0!, {r1-r12} @ Save r1 - r12 + + str lr, [r0] + adr lr, end_init_tee @ save return address to lr + + dsb + + ldr r1, =TRUSTY_OS_ENTRY + ldr r0, =TRUSTY_OS_RAM_SIZE + movs pc, r1 @ Go to TEE codes +end_init_tee: + /* Restore saved registers */ + adr lr, _regs_save + ldr r0, [lr] + add lr, lr, #4 + + ldr sp, [lr] + add lr, lr, #4 + + ldmfd lr!, {r1-r12} + ldr lr, [lr] + + dsb + + bx lr +ENDPROC(trusty_os_init) +#endif diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c index c670c5dfc9c..0f9464141e6 100644 --- a/arch/arm/mach-imx/video.c +++ b/arch/arm/mach-imx/video.c @@ -1,4 +1,7 @@ /* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,7 +12,7 @@ int board_video_skip(void) { int i; - int ret; + int ret = 0; char const *panel = env_get("panel"); if (!panel) { @@ -34,8 +37,20 @@ int board_video_skip(void) } if (i < display_count) { +#if defined(CONFIG_VIDEO_IPUV3) ret = ipuv3_fb_init(&displays[i].mode, displays[i].di ? 1 : 0, displays[i].pixfmt); +#elif defined(CONFIG_VIDEO_IMXDPUV1) + ret = imxdpuv1_fb_init(&displays[i].mode, displays[i].bus, + displays[i].pixfmt); +#elif defined(CONFIG_VIDEO_IMXDCSS) + ret = imx8m_fb_init(&displays[i].mode, displays[i].bus, + displays[i].pixfmt); +#elif defined(CONFIG_VIDEO_MXS) + ret = mxs_lcd_panel_setup(displays[i].mode, + displays[i].pixfmt, + displays[i].bus); +#endif if (!ret) { if (displays[i].enable) displays[i].enable(displays + i); @@ -48,11 +63,12 @@ int board_video_skip(void) printf("LCD %s cannot be configured: %d\n", displays[i].mode.name, ret); } else { - printf("unsupported panel %s\n", panel); + if (strcmp(panel, "NULL")) + printf("unsupported panel %s\n", panel); return -EINVAL; } - return 0; + return ret; } #ifdef CONFIG_IMX_HDMI diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index b0f0ca8f19c..06d0e8ce850 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -27,6 +27,10 @@ testfdt3 = "/b-test"; testfdt5 = "/some-bus/c-test@5"; testfdt8 = "/a-test"; + fdt_dummy0 = "/translation-test@8000/dev@0,0"; + fdt_dummy1 = "/translation-test@8000/dev@1,100"; + fdt_dummy2 = "/translation-test@8000/dev@2,200"; + fdt_dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42"; usb0 = &usb_0; usb1 = &usb_1; usb2 = &usb_2; @@ -487,6 +491,50 @@ reg = <9 1>; }; }; + + translation-test@8000 { + compatible = "simple-bus"; + reg = <0x8000 0x4000>; + + #address-cells = <0x2>; + #size-cells = <0x1>; + + ranges = <0 0x0 0x8000 0x1000 + 1 0x100 0x9000 0x1000 + 2 0x200 0xA000 0x1000 + 3 0x300 0xB000 0x1000 + >; + + dev@0,0 { + compatible = "denx,u-boot-fdt-dummy"; + reg = <0 0x0 0x1000>; + }; + + dev@1,100 { + compatible = "denx,u-boot-fdt-dummy"; + reg = <1 0x100 0x1000>; + + }; + + dev@2,200 { + compatible = "denx,u-boot-fdt-dummy"; + reg = <2 0x200 0x1000>; + }; + + + noxlatebus@3,300 { + compatible = "simple-bus"; + reg = <3 0x300 0x1000>; + + #address-cells = <0x1>; + #size-cells = <0x0>; + + dev@42 { + compatible = "denx,u-boot-fdt-dummy"; + reg = <0x42>; + }; + }; + }; }; #include "sandbox_pmic.dtsi" diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 8b89c10aba6..5c205bd8304 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -1,3 +1,5 @@ +if !ARCH_IMX8M && !ARCH_IMX8 + config CHAIN_OF_TRUST depends on !FIT_SIGNATURE && SECURE_BOOT imply CMD_BLOB @@ -21,6 +23,8 @@ config CMD_ESBC_VALIDATE esbc_validate - validate signature using RSA verification esbc_halt - put the core in spin loop (Secure Boot Only) +endif + config VOL_MONITOR_LTC3882_READ depends on VID bool "Enable the LTC3882 voltage monitor read" @@ -36,3 +40,9 @@ config VOL_MONITOR_LTC3882_SET help This option enables LTC3882 voltage monitor set functionality. It is used by common VID driver. + +config USB_TCPC + bool "USB Typec port controller simple driver" + default n + help + Enable USB type-c port controller (TCPC) driver diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 939e9c66a56..dfe4ac6cf9b 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -61,8 +61,13 @@ obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o obj-$(CONFIG_ZM7300) += zm7300.o obj-$(CONFIG_POWER_PFUZE100) += pfuze.o -obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o +obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze.o obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o +obj-$(CONFIG_MXC_EPDC) += epdc_setup.o +obj-y += mmc.o +ifdef CONFIG_FSL_FASTBOOT +obj-${CONFIG_ANDROID_RECOVERY} += recovery_keypad.o +endif obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o @@ -80,4 +85,8 @@ obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o endif obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_USB_TCPC) += tcpc.o +endif + endif diff --git a/board/freescale/common/epdc_setup.c b/board/freescale/common/epdc_setup.c new file mode 100644 index 00000000000..409e2217518 --- /dev/null +++ b/board/freescale/common/epdc_setup.c @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +#define is_digit(c) ((c) >= '0' && (c) <= '9') +__weak int mmc_get_env_devno(void) +{ + return 0; +} +__weak int check_mmc_autodetect(void) +{ + return 0; +} + +int board_setup_waveform_file(ulong waveform_buf) +{ + char *fs_argv[5]; + char addr[17]; + ulong file_len, mmc_dev; + + if (!check_mmc_autodetect()) + mmc_dev = env_get_ulong("mmcdev", 10, 0); + else + mmc_dev = mmc_get_env_devno(); + + sprintf(addr, "%lx", waveform_buf); + + fs_argv[0] = "fatload"; + fs_argv[1] = "mmc"; + fs_argv[2] = simple_itoa(mmc_dev); + fs_argv[3] = addr; + fs_argv[4] = env_get("epdc_waveform"); + + if (!fs_argv[4]) + fs_argv[4] = "epdc_splash.bin"; + + if (do_fat_fsload(NULL, 0, 5, fs_argv)) { + printf("File %s not found on MMC Device %lu!\n", fs_argv[4], mmc_dev); + return -1; + } + + file_len = env_get_hex("filesize", 0); + if (!file_len) + return -1; + + flush_cache(waveform_buf, roundup(file_len, ARCH_DMA_MINALIGN)); + + return 0; +} + +int board_setup_logo_file(void *display_buf) +{ + int logo_width, logo_height; + char *fs_argv[5]; + char addr[17]; + int array[3]; + ulong file_len, mmc_dev; + char *buf, *s; + int arg = 0, val = 0, pos = 0; + int i, j, max_check_length; + int row, col, row_end, col_end; + + if (!display_buf) + return -EINVAL; + + /* Assume PGM header not exceeds 128 bytes */ + max_check_length = 128; + + if (!check_mmc_autodetect()) + mmc_dev = env_get_ulong("mmcdev", 10, 0); + else + mmc_dev = mmc_get_env_devno(); + + memset(display_buf, 0xFF, panel_info.vl_col * panel_info.vl_row); + + fs_argv[0] = "fatsize"; + fs_argv[1] = "mmc"; + fs_argv[2] = simple_itoa(mmc_dev); + fs_argv[3] = env_get("epdc_logo"); + if (!fs_argv[3]) + fs_argv[3] = "epdc_logo.pgm"; + if (do_fat_size(NULL, 0, 4, fs_argv)) { + debug("File %s not found on MMC Device %lu, use black border\n", fs_argv[3], mmc_dev); + /* Draw black border around framebuffer*/ + memset(display_buf, 0x0, 24 * panel_info.vl_col); + for (i = 24; i < (panel_info.vl_row - 24); i++) { + memset((u8 *)display_buf + i * panel_info.vl_col, + 0x00, 24); + memset((u8 *)display_buf + i * panel_info.vl_col + + panel_info.vl_col - 24, 0x00, 24); + } + memset((u8 *)display_buf + + panel_info.vl_col * (panel_info.vl_row - 24), + 0x00, 24 * panel_info.vl_col); + return 0; + } + + file_len = env_get_hex("filesize", 0); + if (!file_len) + return -EINVAL; + + buf = memalign(ARCH_DMA_MINALIGN, file_len); + if (!buf) + return -ENOMEM; + + sprintf(addr, "%lx", (ulong)buf); + + fs_argv[0] = "fatload"; + fs_argv[1] = "mmc"; + fs_argv[2] = simple_itoa(mmc_dev); + fs_argv[3] = addr; + fs_argv[4] = env_get("epdc_logo"); + + if (!fs_argv[4]) + fs_argv[4] = "epdc_logo.pgm"; + + if (do_fat_fsload(NULL, 0, 5, fs_argv)) { + printf("File %s not found on MMC Device %lu!\n", fs_argv[4], mmc_dev); + free(buf); + return -1; + } + + if (strncmp(buf, "P5", 2)) { + printf("Wrong format for epdc logo, use PGM-P5 format.\n"); + free(buf); + return -EINVAL; + } + /* Skip P5\n */ + pos += 3; + arg = 0; + for (i = 3; i < max_check_length; ) { + /* skip \n \t and space */ + if ((buf[i] == '\n') || (buf[i] == '\t') || (buf[i] == ' ')) { + i++; + continue; + } + /* skip comment */ + if (buf[i] == '#') { + while (buf[i++] != '\n') + ; + continue; + } + + /* HEIGTH, WIDTH, MAX PIXEL VLAUE total 3 args */ + if (arg > 2) + break; + val = 0; + while (is_digit(buf[i])) { + val = val * 10 + buf[i] - '0'; + i++; + } + array[arg++] = val; + + i++; + } + + /* Point to data area */ + pos = i; + + logo_width = array[0]; + logo_height = array[1]; + + if ((logo_width > panel_info.vl_col) || + (logo_height > panel_info.vl_row)) { + printf("Picture: too big\n"); + free(buf); + return -EINVAL; + } + + /* m,m means center of screen */ + row = 0; + col = 0; + s = env_get("splashpos"); + if (s) { + if (s[0] == 'm') + col = (panel_info.vl_col - logo_width) >> 1; + else + col = simple_strtol(s, NULL, 0); + s = strchr(s + 1, ','); + if (s != NULL) { + if (s[1] == 'm') + row = (panel_info.vl_row - logo_height) >> 1; + else + row = simple_strtol(s + 1, NULL, 0); + } + } + if ((col + logo_width > panel_info.vl_col) || + (row + logo_height > panel_info.vl_row)) { + printf("Incorrect pos, use (0, 0)\n"); + row = 0; + col = 0; + } + + /* Draw picture at the center of screen */ + row_end = row + logo_height; + col_end = col + logo_width; + for (i = row; i < row_end; i++) { + for (j = col; j < col_end; j++) { + *((u8 *)display_buf + i * (panel_info.vl_col) + j) = + buf[pos++]; + } + } + + free(buf); + + flush_cache((ulong)display_buf, file_len - pos - 1); + + return 0; +} diff --git a/board/freescale/common/mmc.c b/board/freescale/common/mmc.c new file mode 100644 index 00000000000..9fc3e687281 --- /dev/null +++ b/board/freescale/common/mmc.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} diff --git a/board/freescale/common/qspi_header b/board/freescale/common/qspi_header new file mode 100644 index 00000000000..d4f3c12d418 --- /dev/null +++ b/board/freescale/common/qspi_header @@ -0,0 +1,128 @@ +0 /*dqs_loopback=0 or 1*/ +0 /*hold_delay=0 to 3*/ +0 /*hsphs=0 (Half Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/ +0 /*hsdly=0 (Half Speed Delay one clk delay) or 1 (two clk cycle delay)*/ +0 /*device_quad_mode_en=1 to enable sending command to SPI device*/ +0 /*device_cmd=command to device for enableing Quad I/O mode*/ +0 /*write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/ +2000000 /*write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/ +3 /*cs_hold_time=0 to 0xF*/ +3 /*cs_setup_time=0 to 0xF*/ +8000000 /*sflash_A1_size=size in byte(hex)*/ +0 /*sflash_A2_size=size in byte(hex)*/ +8000000 /*sflash_B1_size=size in byte(hex)*/ +0 /*sflash_B2_size=size in byte(hex)*/ +0 /*sclk_freq=0 to 6*/ +0 /*busy_bit_offset=bit position of device BUSY in device status register*/ +1 /*sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/ +0 /*sflash_port=0 or 1 (Port B used)*/ +0 /*ddr_mode_enable=0 or 1*/ +0 /*dqs_enable=0 or 1*/ +0 /*parallel_mode_enable=0 or 1*/ +0 /*portA_cs1=0 or 1*/ +0 /*portB_cs1=0 or 1*/ +0 /*fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/ +0 /*fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/ +0 /*ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/ +08180403 /*lut[0] command sequence*/ +24001c00 /*lut[1] command sequence*/ +0 /*lut[2] command sequence*/ +0 /*lut[3] command sequence*/ +0 /*lut[4] command sequence*/ +0 /*lut[5] command sequence*/ +0 /*lut[6] command sequence*/ +0 /*lut[7] command sequence*/ +0 /*lut[8] command sequence*/ +0 /*lut[9] command sequence*/ +0 /*lut[10] command sequence*/ +0 /*lut[11] command sequence*/ +0 /*lut[12] command sequence*/ +0 /*lut[13] command sequence*/ +0 /*lut[14] command sequence*/ +0 /*lut[15] command sequence*/ +0 /*lut[16] command sequence*/ +0 /*lut[17] command sequence*/ +0 /*lut[18] command sequence*/ +0 /*lut[19] command sequence*/ +0 /*lut[20] command sequence*/ +0 /*lut[21] command sequence*/ +0 /*lut[22] command sequence*/ +0 /*lut[23] command sequence*/ +0 /*lut[24] command sequence*/ +0 /*lut[25] command sequence*/ +0 /*lut[26] command sequence*/ +0 /*lut[27] command sequence*/ +0 /*lut[28] command sequence*/ +0 /*lut[29] command sequence*/ +0 /*lut[30] command sequence*/ +0 /*lut[31] command sequence*/ +0 /*lut[32] command sequence*/ +0 /*lut[33] command sequence*/ +0 /*lut[34] command sequence*/ +0 /*lut[35] command sequence*/ +0 /*lut[36] command sequence*/ +0 /*lut[37] command sequence*/ +0 /*lut[38] command sequence*/ +0 /*lut[39] command sequence*/ +0 /*lut[40] command sequence*/ +0 /*lut[41] command sequence*/ +0 /*lut[42] command sequence*/ +0 /*lut[43] command sequence*/ +0 /*lut[44] command sequence*/ +0 /*lut[45] command sequence*/ +0 /*lut[46] command sequence*/ +0 /*lut[47] command sequence*/ +0 /*lut[48] command sequence*/ +0 /*lut[49] command sequence*/ +0 /*lut[50] command sequence*/ +0 /*lut[51] command sequence*/ +0 /*lut[52] command sequence*/ +0 /*lut[53] command sequence*/ +0 /*lut[54] command sequence*/ +0 /*lut[55] command sequence*/ +0 /*lut[56] command sequence*/ +0 /*lut[57] command sequence*/ +0 /*lut[58] command sequence*/ +0 /*lut[59] command sequence*/ +0 /*lut[60] command sequence*/ +0 /*lut[61] command sequence*/ +0 /*lut[62] command sequence*/ +0 /*lut[63] command sequence*/ +1000001 /*read_status_ipcr=hex value to be written to IPCR register for reading status reg of device*/ +0 /*enable_dqs_phase=0 or 1*/ +0 /*config_cmds_en, enable config command*/ +0 /*config_cmds[0]*/ +0 /*config_cmds[1]*/ +0 /*config_cmds[2]*/ +0 /*config_cmds[3]*/ +0 /*config_cmds_args[0]*/ +0 /*config_cmds_args[1]*/ +0 /*config_cmds_args[2]*/ +0 /*config_cmds_args[3]*/ +0 /*io_pad_override_setting QSPI pins override setting*/ +0 /*reserve[0], 25 byte reserved area*/ +0 /*reserve[1], 25 byte reserved area*/ +0 /*reserve[2], 25 byte reserved area*/ +0 /*reserve[3], 25 byte reserved area*/ +0 /*reserve[4], 25 byte reserved area*/ +0 /*reserve[5], 25 byte reserved area*/ +0 /*reserve[6], 25 byte reserved area*/ +0 /*reserve[7], 25 byte reserved area*/ +0 /*reserve[8], 25 byte reserved area*/ +0 /*reserve[9], 25 byte reserved area*/ +0 /*reserve[10], 25 byte reserved area*/ +0 /*reserve[11], 25 byte reserved area*/ +0 /*reserve[12], 25 byte reserved area*/ +0 /*reserve[13], 25 byte reserved area*/ +0 /*reserve[14], 25 byte reserved area*/ +0 /*reserve[15], 25 byte reserved area*/ +0 /*reserve[16], 25 byte reserved area*/ +0 /*reserve[17], 25 byte reserved area*/ +0 /*reserve[18], 25 byte reserved area*/ +0 /*reserve[19], 25 byte reserved area*/ +0 /*reserve[20], 25 byte reserved area*/ +0 /*reserve[21], 25 byte reserved area*/ +0 /*reserve[22], 25 byte reserved area*/ +0 /*reserve[23], 25 byte reserved area*/ +0 /*reserve[24], 25 byte reserved area*/ +c0ffee01 /*tag, QSPI configuration tag, should be 0xc0ffee01*/ diff --git a/board/freescale/common/recovery_keypad.c b/board/freescale/common/recovery_keypad.c new file mode 100644 index 00000000000..fb15626b030 --- /dev/null +++ b/board/freescale/common/recovery_keypad.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#ifdef CONFIG_MXC_KPD +#include +#endif +#include + +#ifdef CONFIG_MXC_KPD +#define PRESSED_VOL_DOWN 0x01 +#define PRESSED_POWER 0x02 +#define RECOVERY_KEY_MASK (PRESSED_VOL_DOWN | PRESSED_POWER) + +inline int test_key(int value, struct kpp_key_info *ki) +{ + return (ki->val == value) && (ki->evt == KDepress); +} + +int is_recovery_keypad_pressing(void) +{ + struct kpp_key_info *key_info = NULL; + int state = 0, keys, i; + + int ret = 0; + + mxc_kpp_init(); + /* due to glitch suppression circuit, + wait sometime to let all keys scanned. */ + udelay(1000); + keys = mxc_kpp_getc(&key_info); + + printf("Detecting VOL_DOWN+POWER key for recovery(%d:%d) ...\n", + keys, keys ? key_info->val : 0); + if (keys > 1) { + for (i = 0; i < keys; i++) { + if (test_key(CONFIG_POWER_KEY, &key_info[i])) + state |= PRESSED_POWER; + else if (test_key(CONFIG_VOL_DOWN_KEY, &key_info[i])) + state |= PRESSED_VOL_DOWN; + } + } + if ((state & RECOVERY_KEY_MASK) == RECOVERY_KEY_MASK) + ret = 1; + if (key_info) + free(key_info); + return ret; +} +#else +/* If not using mxc keypad, currently we will detect power key on board */ +int is_recovery_keypad_pressing(void) +{ + return 0; +} +#endif diff --git a/board/freescale/common/recovery_keypad.h b/board/freescale/common/recovery_keypad.h new file mode 100644 index 00000000000..d315cea780b --- /dev/null +++ b/board/freescale/common/recovery_keypad.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __RECOVERY_KEYPAD_H_ +#define __RECOVERY_KEYPAD_H_ + +int is_recovery_keypad_pressing(void); + +#endif diff --git a/board/freescale/common/tcpc.c b/board/freescale/common/tcpc.c new file mode 100644 index 00000000000..0b945218e00 --- /dev/null +++ b/board/freescale/common/tcpc.c @@ -0,0 +1,1012 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include "tcpc.h" + +#ifdef DEBUG +#define tcpc_debug_log(port, fmt, args...) tcpc_log(port, fmt, ##args) +#else +#define tcpc_debug_log(port, fmt, args...) +#endif + +static int tcpc_log(struct tcpc_port *port, const char *fmt, ...) +{ + va_list args; + int i; + + va_start(args, fmt); + i = vscnprintf(port->log_p, port->log_size, fmt, args); + va_end(args); + + port->log_size -= i; + port->log_p += i; + + return i; +} + +int tcpc_set_cc_to_source(struct tcpc_port *port) +{ + uint8_t valb; + int err; + + if (port == NULL) + return -EINVAL; + + valb = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | + (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) | + (TCPC_ROLE_CTRL_RP_VAL_DEF << + TCPC_ROLE_CTRL_RP_VAL_SHIFT) | TCPC_ROLE_CTRL_DRP; + + err = dm_i2c_write(port->i2c_dev, TCPC_ROLE_CTRL, &valb, 1); + if (err) + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return err; +} + +int tcpc_set_cc_to_sink(struct tcpc_port *port) +{ + uint8_t valb; + int err; + + if (port == NULL) + return -EINVAL; + + valb = (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) | + (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT) | TCPC_ROLE_CTRL_DRP; + + err = dm_i2c_write(port->i2c_dev, TCPC_ROLE_CTRL, &valb, 1); + if (err) + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return err; +} + + +int tcpc_set_plug_orientation(struct tcpc_port *port, enum typec_cc_polarity polarity) +{ + uint8_t valb; + int err; + + if (port == NULL) + return -EINVAL; + + err = dm_i2c_read(port->i2c_dev, TCPC_TCPC_CTRL, &valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + if (polarity == TYPEC_POLARITY_CC2) + valb |= TCPC_TCPC_CTRL_ORIENTATION; + else + valb &= ~TCPC_TCPC_CTRL_ORIENTATION; + + err = dm_i2c_write(port->i2c_dev, TCPC_TCPC_CTRL, &valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return -EIO; + } + + return 0; +} + +int tcpc_get_cc_status(struct tcpc_port *port, enum typec_cc_polarity *polarity, enum typec_cc_state *state) +{ + + uint8_t valb_cc, cc2, cc1; + int err; + + if (port == NULL || polarity == NULL || state == NULL) + return -EINVAL; + + err = dm_i2c_read(port->i2c_dev, TCPC_CC_STATUS, (uint8_t *)&valb_cc, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + tcpc_debug_log(port, "cc status 0x%x\n", valb_cc); + + cc2 = (valb_cc >> TCPC_CC_STATUS_CC2_SHIFT) & TCPC_CC_STATUS_CC2_MASK; + cc1 = (valb_cc >> TCPC_CC_STATUS_CC1_SHIFT) & TCPC_CC_STATUS_CC1_MASK; + + if (valb_cc & TCPC_CC_STATUS_LOOK4CONN) + return -EFAULT; + + *state = TYPEC_STATE_OPEN; + + if (valb_cc & TCPC_CC_STATUS_TERM) { + if (cc2) { + *polarity = TYPEC_POLARITY_CC2; + + switch (cc2) { + case 0x1: + *state = TYPEC_STATE_SNK_DEFAULT; + tcpc_log(port, "SNK.Default on CC2\n"); + break; + case 0x2: + *state = TYPEC_STATE_SNK_POWER15; + tcpc_log(port, "SNK.Power1.5 on CC2\n"); + break; + case 0x3: + *state = TYPEC_STATE_SNK_POWER30; + tcpc_log(port, "SNK.Power3.0 on CC2\n"); + break; + } + } else if (cc1) { + *polarity = TYPEC_POLARITY_CC1; + + switch (cc1) { + case 0x1: + *state = TYPEC_STATE_SNK_DEFAULT; + tcpc_log(port, "SNK.Default on CC1\n"); + break; + case 0x2: + *state = TYPEC_STATE_SNK_POWER15; + tcpc_log(port, "SNK.Power1.5 on CC1\n"); + break; + case 0x3: + *state = TYPEC_STATE_SNK_POWER30; + tcpc_log(port, "SNK.Power3.0 on CC1\n"); + break; + } + } else { + *state = TYPEC_STATE_OPEN; + return -EPERM; + } + + } else { + if (cc2) { + *polarity = TYPEC_POLARITY_CC2; + + switch (cc2) { + case 0x1: + if (cc1 == 0x1) { + *state = TYPEC_STATE_SRC_BOTH_RA; + tcpc_log(port, "SRC.Ra on both CC1 and CC2\n"); + } else if (cc1 == 0x2) { + *state = TYPEC_STATE_SRC_RD_RA; + tcpc_log(port, "SRC.Ra on CC2, SRC.Rd on CC1\n"); + } else if (cc1 == 0x0) { + tcpc_log(port, "SRC.Ra only on CC2\n"); + return -EFAULT; + } else + return -EFAULT; + break; + case 0x2: + if (cc1 == 0x1) { + *state = TYPEC_STATE_SRC_RD_RA; + tcpc_log(port, "SRC.Ra on CC1, SRC.Rd on CC2\n"); + } else if (cc1 == 0x0) { + *state = TYPEC_STATE_SRC_RD; + tcpc_log(port, "SRC.Rd on CC2\n"); + } else + return -EFAULT; + break; + case 0x3: + *state = TYPEC_STATE_SRC_RESERVED; + return -EFAULT; + } + } else if (cc1) { + *polarity = TYPEC_POLARITY_CC1; + + switch (cc1) { + case 0x1: + tcpc_log(port, "SRC.Ra only on CC1\n"); + return -EFAULT; + case 0x2: + *state = TYPEC_STATE_SRC_RD; + tcpc_log(port, "SRC.Rd on CC1\n"); + break; + case 0x3: + *state = TYPEC_STATE_SRC_RESERVED; + return -EFAULT; + } + } else { + *state = TYPEC_STATE_OPEN; + return -EPERM; + } + } + + return 0; +} + +int tcpc_clear_alert(struct tcpc_port *port, uint16_t clear_mask) +{ + int err; + + if (port == NULL) + return -EINVAL; + + err = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&clear_mask, 2); + if (err) { + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return -EIO; + } + + return 0; +} + +int tcpc_send_command(struct tcpc_port *port, uint8_t command) +{ + int err; + + if (port == NULL) + return -EINVAL; + + err = dm_i2c_write(port->i2c_dev, TCPC_COMMAND, (const uint8_t *)&command, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return -EIO; + } + + return 0; +} + +int tcpc_polling_reg(struct tcpc_port *port, uint8_t reg, + uint8_t reg_width, uint16_t mask, uint16_t value, ulong timeout_ms) +{ + uint16_t val = 0; + int err; + ulong start; + + if (port == NULL) + return -EINVAL; + + tcpc_debug_log(port, "%s reg 0x%x, mask 0x%x, value 0x%x\n", __func__, reg, mask, value); + + /* TCPC registers is 8 bits or 16 bits */ + if (reg_width != 1 && reg_width != 2) + return -EINVAL; + + start = get_timer(0); /* Get current timestamp */ + do { + err = dm_i2c_read(port->i2c_dev, reg, (uint8_t *)&val, reg_width); + if (err) + return -EIO; + + if ((val & mask) == value) + return 0; + } while (get_timer(0) < (start + timeout_ms)); + + return -ETIME; +} + +void tcpc_print_log(struct tcpc_port *port) +{ + if (port == NULL) + return; + + if (port->log_print == port->log_p) /*nothing to output*/ + return; + + printf("%s", port->log_print); + + port->log_print = port->log_p; +} + +int tcpc_setup_dfp_mode(struct tcpc_port *port) +{ + enum typec_cc_polarity pol; + enum typec_cc_state state; + int ret; + + if (port == NULL) + return -EINVAL; + + if (tcpc_pd_sink_check_charging(port)) { + tcpc_log(port, "%s: Can't apply DFP mode when PD is charging\n", + __func__); + return -EPERM; + } + + tcpc_set_cc_to_source(port); + + ret = tcpc_send_command(port, TCPC_CMD_LOOK4CONNECTION); + if (ret) + return ret; + + /* At least wait tCcStatusDelay + tTCPCFilter + tCcTCPCSampleRate (max) = 200us + 500us + ?ms + * PTN5110 datasheet does not contain the sample rate value, according other productions, + * the sample rate is at ms level, about 2 ms -10ms. So wait 100ms should be enough. + */ + mdelay(100); + + ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_CC_STATUS, TCPC_ALERT_CC_STATUS, 100); + if (ret) { + tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_CC_STATUS bit failed, ret = %d\n", + __func__, ret); + return ret; + } + + ret = tcpc_get_cc_status(port, &pol, &state); + tcpc_clear_alert(port, TCPC_ALERT_CC_STATUS); + + if (!ret) { + /* If presenting as Rd/audio mode/open, return */ + if (state != TYPEC_STATE_SRC_RD_RA && state != TYPEC_STATE_SRC_RD) + return -EPERM; + + if (pol == TYPEC_POLARITY_CC1) + tcpc_debug_log(port, "polarity cc1\n"); + else + tcpc_debug_log(port, "polarity cc2\n"); + + if (port->ss_sel_func) + port->ss_sel_func(pol); + + ret = tcpc_set_plug_orientation(port, pol); + if (ret) + return ret; + + /* Enable source vbus default voltage */ + ret = tcpc_send_command(port, TCPC_CMD_SRC_VBUS_DEFAULT); + if (ret) + return ret; + + /* The max vbus on time is 200ms, we add margin 100ms */ + mdelay(300); + + } + + return 0; +} + +int tcpc_setup_ufp_mode(struct tcpc_port *port) +{ + enum typec_cc_polarity pol; + enum typec_cc_state state; + int ret; + + if (port == NULL) + return -EINVAL; + + /* Check if the PD charge is working. If not, need to configure CC role for UFP */ + if (!tcpc_pd_sink_check_charging(port)) { + + /* Disable the source vbus once it is enabled by DFP mode */ + tcpc_disable_src_vbus(port); + + tcpc_set_cc_to_sink(port); + + ret = tcpc_send_command(port, TCPC_CMD_LOOK4CONNECTION); + if (ret) + return ret; + + /* At least wait tCcStatusDelay + tTCPCFilter + tCcTCPCSampleRate (max) = 200us + 500us + ?ms + * PTN5110 datasheet does not contain the sample rate value, according other productions, + * the sample rate is at ms level, about 2 ms -10ms. So wait 100ms should be enough. + */ + mdelay(100); + + ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_CC_STATUS, TCPC_ALERT_CC_STATUS, 100); + if (ret) { + tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_CC_STATUS bit failed, ret = %d\n", + __func__, ret); + return ret; + } + + ret = tcpc_get_cc_status(port, &pol, &state); + tcpc_clear_alert(port, TCPC_ALERT_CC_STATUS); + + } else { + ret = tcpc_get_cc_status(port, &pol, &state); + } + + if (!ret) { + /* If presenting not as sink, then return */ + if (state != TYPEC_STATE_SNK_DEFAULT && state != TYPEC_STATE_SNK_POWER15 && + state != TYPEC_STATE_SNK_POWER30) + return -EPERM; + + if (pol == TYPEC_POLARITY_CC1) + tcpc_debug_log(port, "polarity cc1\n"); + else + tcpc_debug_log(port, "polarity cc2\n"); + + if (port->ss_sel_func) + port->ss_sel_func(pol); + + ret = tcpc_set_plug_orientation(port, pol); + if (ret) + return ret; + } + + return 0; +} + +int tcpc_disable_src_vbus(struct tcpc_port *port) +{ + int ret; + + if (port == NULL) + return -EINVAL; + + /* Disable VBUS*/ + ret = tcpc_send_command(port, TCPC_CMD_DISABLE_SRC_VBUS); + if (ret) + return ret; + + /* The max vbus off time is 0.5ms, we add margin 0.5 ms */ + mdelay(1); + + return 0; +} + +int tcpc_disable_sink_vbus(struct tcpc_port *port) +{ + int ret; + + if (port == NULL) + return -EINVAL; + + /* Disable SINK VBUS*/ + ret = tcpc_send_command(port, TCPC_CMD_DISABLE_SINK_VBUS); + if (ret) + return ret; + + /* The max vbus off time is 0.5ms, we add margin 0.5 ms */ + mdelay(1); + + return 0; +} + + +static int tcpc_pd_receive_message(struct tcpc_port *port, struct pd_message *msg) +{ + int ret; + uint8_t cnt; + uint16_t val; + + if (port == NULL) + return -EINVAL; + + /* Generally the max tSenderResponse is 30ms, max tTypeCSendSourceCap is 200ms, we set the timeout to 500ms */ + ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_RX_STATUS, TCPC_ALERT_RX_STATUS, 500); + if (ret) { + tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_RX_STATUS bit failed, ret = %d\n", + __func__, ret); + return ret; + } + + cnt = 0; + ret = dm_i2c_read(port->i2c_dev, TCPC_RX_BYTE_CNT, (uint8_t *)&cnt, 1); + if (ret) + return -EIO; + + if (cnt > 0) { + ret = dm_i2c_read(port->i2c_dev, TCPC_RX_BUF_FRAME_TYPE, (uint8_t *)msg, cnt); + if (ret) + return -EIO; + + /* Clear RX status alert bit */ + val = TCPC_ALERT_RX_STATUS; + ret = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&val, 2); + if (ret) + return -EIO; + } + + return cnt; +} + +static int tcpc_pd_transmit_message(struct tcpc_port *port, struct pd_message *msg_p, uint8_t bytes) +{ + int ret; + uint8_t valb; + uint16_t val; + + if (port == NULL) + return -EINVAL; + + if (msg_p == NULL || bytes <= 0) + return -EINVAL; + + ret = dm_i2c_write(port->i2c_dev, TCPC_TX_BYTE_CNT, (const uint8_t *)&bytes, 1); + if (ret) + return -EIO; + + ret = dm_i2c_write(port->i2c_dev, TCPC_TX_HDR, (const uint8_t *)&(msg_p->header), bytes); + if (ret) + return -EIO; + + valb = (3 << TCPC_TRANSMIT_RETRY_SHIFT) | (TCPC_TX_SOP << TCPC_TRANSMIT_TYPE_SHIFT); + ret = dm_i2c_write(port->i2c_dev, TCPC_TRANSMIT, (const uint8_t *)&valb, 1); + if (ret) + return -EIO; + + /* Max tReceive is 1.1ms, we set to 5ms timeout */ + ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_TX_SUCCESS, TCPC_ALERT_TX_SUCCESS, 5); + if (ret) { + if (ret == -ETIME) { + ret = dm_i2c_read(port->i2c_dev, TCPC_ALERT, (uint8_t *)&val, 2); + if (ret) + return -EIO; + + if (val & TCPC_ALERT_TX_FAILED) + tcpc_log(port, "%s: PD TX FAILED, ALERT = 0x%x\n", __func__, val); + + if (val & TCPC_ALERT_TX_DISCARDED) + tcpc_log(port, "%s: PD TX DISCARDED, ALERT = 0x%x\n", __func__, val); + + } else { + tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_TX_SUCCESS bit failed, ret = %d\n", + __func__, ret); + } + } else { + port->tx_msg_id = (port->tx_msg_id + 1) & PD_HEADER_ID_MASK; + } + + /* Clear ALERT status */ + val &= (TCPC_ALERT_TX_FAILED | TCPC_ALERT_TX_DISCARDED | TCPC_ALERT_TX_SUCCESS); + ret = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&val, 2); + if (ret) + return -EIO; + + return ret; +} + +static void tcpc_log_source_caps(struct tcpc_port *port, uint32_t *caps, unsigned int capcount) +{ + int i; + + for (i = 0; i < capcount; i++) { + u32 pdo = caps[i]; + enum pd_pdo_type type = pdo_type(pdo); + + tcpc_log(port, "PDO %d: type %d, ", + i, type); + + switch (type) { + case PDO_TYPE_FIXED: + tcpc_log(port, "%u mV, %u mA [%s%s%s%s%s%s]\n", + pdo_fixed_voltage(pdo), + pdo_max_current(pdo), + (pdo & PDO_FIXED_DUAL_ROLE) ? + "R" : "", + (pdo & PDO_FIXED_SUSPEND) ? + "S" : "", + (pdo & PDO_FIXED_HIGHER_CAP) ? + "H" : "", + (pdo & PDO_FIXED_USB_COMM) ? + "U" : "", + (pdo & PDO_FIXED_DATA_SWAP) ? + "D" : "", + (pdo & PDO_FIXED_EXTPOWER) ? + "E" : ""); + break; + case PDO_TYPE_VAR: + tcpc_log(port, "%u-%u mV, %u mA\n", + pdo_min_voltage(pdo), + pdo_max_voltage(pdo), + pdo_max_current(pdo)); + break; + case PDO_TYPE_BATT: + tcpc_log(port, "%u-%u mV, %u mW\n", + pdo_min_voltage(pdo), + pdo_max_voltage(pdo), + pdo_max_power(pdo)); + break; + default: + tcpc_log(port, "undefined\n"); + break; + } + } +} + +static int tcpc_pd_select_pdo(uint32_t *caps, uint32_t capcount, uint32_t max_snk_mv, uint32_t max_snk_ma) +{ + unsigned int i, max_mw = 0, max_mv = 0; + int ret = -EINVAL; + + /* + * Select the source PDO providing the most power while staying within + * the board's voltage limits. Prefer PDO providing exp + */ + for (i = 0; i < capcount; i++) { + u32 pdo = caps[i]; + enum pd_pdo_type type = pdo_type(pdo); + unsigned int mv, ma, mw; + + if (type == PDO_TYPE_FIXED) + mv = pdo_fixed_voltage(pdo); + else + mv = pdo_min_voltage(pdo); + + if (type == PDO_TYPE_BATT) { + mw = pdo_max_power(pdo); + } else { + ma = min(pdo_max_current(pdo), + max_snk_ma); + mw = ma * mv / 1000; + } + + /* Perfer higher voltages if available */ + if ((mw > max_mw || (mw == max_mw && mv > max_mv)) && + mv <= max_snk_mv) { + ret = i; + max_mw = mw; + max_mv = mv; + } + } + + return ret; +} + +static int tcpc_pd_build_request(struct tcpc_port *port, + uint32_t *caps, + uint32_t capcount, + uint32_t max_snk_mv, + uint32_t max_snk_ma, + uint32_t max_snk_mw, + uint32_t operating_snk_mw, + uint32_t *rdo) +{ + unsigned int mv, ma, mw, flags; + unsigned int max_ma, max_mw; + enum pd_pdo_type type; + int index; + u32 pdo; + + index = tcpc_pd_select_pdo(caps, capcount, max_snk_mv, max_snk_ma); + if (index < 0) + return -EINVAL; + + pdo = caps[index]; + type = pdo_type(pdo); + + if (type == PDO_TYPE_FIXED) + mv = pdo_fixed_voltage(pdo); + else + mv = pdo_min_voltage(pdo); + + /* Select maximum available current within the board's power limit */ + if (type == PDO_TYPE_BATT) { + mw = pdo_max_power(pdo); + ma = 1000 * min(mw, max_snk_mw) / mv; + } else { + ma = min(pdo_max_current(pdo), + 1000 * max_snk_mw / mv); + } + ma = min(ma, max_snk_ma); + + /* XXX: Any other flags need to be set? */ + flags = 0; + + /* Set mismatch bit if offered power is less than operating power */ + mw = ma * mv / 1000; + max_ma = ma; + max_mw = mw; + if (mw < operating_snk_mw) { + flags |= RDO_CAP_MISMATCH; + max_mw = operating_snk_mw; + max_ma = max_mw * 1000 / mv; + } + + if (type == PDO_TYPE_BATT) { + *rdo = RDO_BATT(index + 1, mw, max_mw, flags); + + tcpc_log(port, "Requesting PDO %d: %u mV, %u mW%s\n", + index, mv, mw, + flags & RDO_CAP_MISMATCH ? " [mismatch]" : ""); + } else { + *rdo = RDO_FIXED(index + 1, ma, max_ma, flags); + + tcpc_log(port, "Requesting PDO %d: %u mV, %u mA%s\n", + index, mv, ma, + flags & RDO_CAP_MISMATCH ? " [mismatch]" : ""); + } + + return 0; +} + +static void tcpc_pd_sink_process(struct tcpc_port *port) +{ + int ret; + uint8_t msgtype; + uint32_t objcnt; + struct pd_message msg; + enum pd_sink_state pd_state = WAIT_SOURCE_CAP; + + while (tcpc_pd_receive_message(port, &msg) > 0) { + + msgtype = pd_header_type(msg.header); + objcnt = pd_header_cnt_le(msg.header); + + tcpc_debug_log(port, "get msg, type %d, cnt %d\n", msgtype, objcnt); + + switch (pd_state) { + case WAIT_SOURCE_CAP: + case SINK_READY: + if (msgtype != PD_DATA_SOURCE_CAP) + continue; + + uint32_t *caps = (uint32_t *)&msg.payload; + uint32_t rdo = 0; + + tcpc_log_source_caps(port, caps, objcnt); + + tcpc_pd_build_request(port, caps, objcnt, + port->cfg.max_snk_mv, port->cfg.max_snk_ma, + port->cfg.max_snk_mw, port->cfg.op_snk_mv, + &rdo); + + memset(&msg, 0, sizeof(msg)); + msg.header = PD_HEADER(PD_DATA_REQUEST, 0, 0, port->tx_msg_id, 1); /* power sink, data device, id 0, len 1 */ + msg.payload[0] = rdo; + + ret = tcpc_pd_transmit_message(port, &msg, 6); + if (ret) + tcpc_log(port, "send request failed\n"); + else + pd_state = WAIT_SOURCE_ACCEPT; + + break; + case WAIT_SOURCE_ACCEPT: + if (objcnt > 0) /* Should be ctrl message */ + continue; + + if (msgtype == PD_CTRL_ACCEPT) { + pd_state = WAIT_SOURCE_READY; + tcpc_log(port, "Source accept request\n"); + } else if (msgtype == PD_CTRL_REJECT) { + tcpc_log(port, "Source reject request\n"); + return; + } + + break; + case WAIT_SOURCE_READY: + if (objcnt > 0) /* Should be ctrl message */ + continue; + + if (msgtype == PD_CTRL_PS_RDY) { + tcpc_log(port, "PD source ready!\n"); + pd_state = SINK_READY; + } + + break; + default: + tcpc_log(port, "unexpect status: %u\n", pd_state); + break; + } + } +} + +bool tcpc_pd_sink_check_charging(struct tcpc_port *port) +{ + uint8_t valb; + int err; + enum typec_cc_polarity pol; + enum typec_cc_state state; + + if (port == NULL) + return false; + + /* Check the CC status, must be sink */ + err = tcpc_get_cc_status(port, &pol, &state); + if (err || (state != TYPEC_STATE_SNK_POWER15 + && state != TYPEC_STATE_SNK_POWER30 + && state != TYPEC_STATE_SNK_DEFAULT)) { + tcpc_debug_log(port, "TCPC wrong state for PD charging, err = %d, CC = 0x%x\n", + err, state); + return false; + } + + /* Check the VBUS PRES and SINK VBUS for dead battery */ + err = dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1); + if (err) { + tcpc_debug_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return false; + } + + if (!(valb & TCPC_POWER_STATUS_VBUS_PRES)) { + tcpc_debug_log(port, "VBUS NOT PRES \n"); + return false; + } + + if (!(valb & TCPC_POWER_STATUS_SINKING_VBUS)) { + tcpc_debug_log(port, "SINK VBUS is not enabled for dead battery\n"); + return false; + } + + return true; +} + +static int tcpc_pd_sink_disable(struct tcpc_port *port) +{ + uint8_t valb; + int err; + + if (port == NULL) + return -EINVAL; + + port->pd_state = UNATTACH; + + /* Check the VBUS PRES and SINK VBUS for dead battery */ + err = dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + if ((valb & TCPC_POWER_STATUS_VBUS_PRES) && (valb & TCPC_POWER_STATUS_SINKING_VBUS)) { + dm_i2c_read(port->i2c_dev, TCPC_POWER_CTRL, (uint8_t *)&valb, 1); + valb &= ~TCPC_POWER_CTRL_AUTO_DISCH_DISCO; /* disable AutoDischargeDisconnect */ + dm_i2c_write(port->i2c_dev, TCPC_POWER_CTRL, (const uint8_t *)&valb, 1); + + tcpc_disable_sink_vbus(port); + } + + if (port->cfg.switch_setup_func) + port->cfg.switch_setup_func(port); + + return 0; +} + +static int tcpc_pd_sink_init(struct tcpc_port *port) +{ + uint8_t valb; + uint16_t val; + int err; + enum typec_cc_polarity pol; + enum typec_cc_state state; + + if (port == NULL) + return -EINVAL; + + port->pd_state = UNATTACH; + + /* Check the VBUS PRES and SINK VBUS for dead battery */ + err = dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + if (!(valb & TCPC_POWER_STATUS_VBUS_PRES)) { + tcpc_debug_log(port, "VBUS NOT PRES \n"); + return -EPERM; + } + + if (!(valb & TCPC_POWER_STATUS_SINKING_VBUS)) { + tcpc_debug_log(port, "SINK VBUS is not enabled for dead battery\n"); + return -EPERM; + } + + err = dm_i2c_read(port->i2c_dev, TCPC_ALERT, (uint8_t *)&val, 2); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + if (!(val & TCPC_ALERT_CC_STATUS)) { + tcpc_debug_log(port, "CC STATUS not detected for dead battery\n"); + return -EPERM; + } + + err = tcpc_get_cc_status(port, &pol, &state); + if (err || (state != TYPEC_STATE_SNK_POWER15 + && state != TYPEC_STATE_SNK_POWER30 + && state != TYPEC_STATE_SNK_DEFAULT)) { + tcpc_log(port, "TCPC wrong state for dead battery, err = %d, CC = 0x%x\n", + err, state); + return -EPERM; + } else + port->pd_state = ATTACHED; + + dm_i2c_read(port->i2c_dev, TCPC_POWER_CTRL, (uint8_t *)&valb, 1); + valb &= ~TCPC_POWER_CTRL_AUTO_DISCH_DISCO; /* disable AutoDischargeDisconnect */ + dm_i2c_write(port->i2c_dev, TCPC_POWER_CTRL, (const uint8_t *)&valb, 1); + + if (port->cfg.switch_setup_func) + port->cfg.switch_setup_func(port); + + /* As sink role */ + valb = 0x00; + err = dm_i2c_write(port->i2c_dev, TCPC_MSG_HDR_INFO, (const uint8_t *)&valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + /* Enable rx */ + valb = TCPC_RX_DETECT_SOP | TCPC_RX_DETECT_HARD_RESET; + err = dm_i2c_write(port->i2c_dev, TCPC_RX_DETECT, (const uint8_t *)&valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + tcpc_pd_sink_process(port); + + return 0; +} + +int tcpc_init(struct tcpc_port *port, struct tcpc_port_config config, ss_mux_sel ss_sel_func) +{ + int ret; + uint8_t valb; + uint16_t vid, pid; + struct udevice *bus; + struct udevice *i2c_dev = NULL; + + memset(port, 0, sizeof(struct tcpc_port)); + + if (port == NULL) + return -EINVAL; + + port->cfg = config; + port->tx_msg_id = 0; + port->ss_sel_func = ss_sel_func; + port->log_p = (char *)&(port->logbuffer); + port->log_size = TCPC_LOG_BUFFER_SIZE; + port->log_print = port->log_p; + memset(&(port->logbuffer), 0, TCPC_LOG_BUFFER_SIZE); + + ret = uclass_get_device_by_seq(UCLASS_I2C, port->cfg.i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, port->cfg.addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, config.addr); + return -ENODEV; + } + + port->i2c_dev = i2c_dev; + + /* Check the Initialization Status bit in 1s */ + ret = tcpc_polling_reg(port, TCPC_POWER_STATUS, 1, TCPC_POWER_STATUS_UNINIT, 0, 1000); + if (ret) { + tcpc_log(port, "%s: Polling TCPC POWER STATUS Initialization Status bit failed, ret = %d\n", + __func__, ret); + return ret; + } + + dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1); + tcpc_debug_log("POWER STATUS: 0x%x\n", valb); + + /* Clear AllRegistersResetToDefault */ + valb = 0x80; + ret = dm_i2c_write(port->i2c_dev, TCPC_FAULT_STATUS, (const uint8_t *)&valb, 1); + if (ret) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Read Vendor ID and Product ID */ + ret = dm_i2c_read(port->i2c_dev, TCPC_VENDOR_ID, (uint8_t *)&vid, 2); + if (ret) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + + ret = dm_i2c_read(port->i2c_dev, TCPC_PRODUCT_ID, (uint8_t *)&pid, 2); + if (ret) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + + tcpc_log(port, "TCPC: Vendor ID [0x%x], Product ID [0x%x], Addr [I2C%u 0x%x]\n", + vid, pid, port->cfg.i2c_bus, port->cfg.addr); + + if (!port->cfg.disable_pd) { + if (port->cfg.port_type == TYPEC_PORT_UFP + || port->cfg.port_type == TYPEC_PORT_DRP) + tcpc_pd_sink_init(port); + } else { + tcpc_pd_sink_disable(port); + } + + tcpc_clear_alert(port, 0xffff); + + tcpc_print_log(port); + + return 0; +} diff --git a/board/freescale/common/tcpc.h b/board/freescale/common/tcpc.h new file mode 100644 index 00000000000..ff749518a8b --- /dev/null +++ b/board/freescale/common/tcpc.h @@ -0,0 +1,469 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TCPCI_H +#define __TCPCI_H + +#include + +#define TCPC_VENDOR_ID 0x0 +#define TCPC_PRODUCT_ID 0x2 + +#define TCPC_ALERT 0x10 +#define TCPC_ALERT_VBUS_DISCNCT BIT(11) +#define TCPC_ALERT_RX_BUF_OVF BIT(10) +#define TCPC_ALERT_FAULT BIT(9) +#define TCPC_ALERT_V_ALARM_LO BIT(8) +#define TCPC_ALERT_V_ALARM_HI BIT(7) +#define TCPC_ALERT_TX_SUCCESS BIT(6) +#define TCPC_ALERT_TX_DISCARDED BIT(5) +#define TCPC_ALERT_TX_FAILED BIT(4) +#define TCPC_ALERT_RX_HARD_RST BIT(3) +#define TCPC_ALERT_RX_STATUS BIT(2) +#define TCPC_ALERT_POWER_STATUS BIT(1) +#define TCPC_ALERT_CC_STATUS BIT(0) + +#define TCPC_TCPC_CTRL 0x19 +#define TCPC_TCPC_CTRL_BIST_MODE BIT(1) +#define TCPC_TCPC_CTRL_ORIENTATION BIT(0) + +#define TCPC_ROLE_CTRL 0x1a +#define TCPC_ROLE_CTRL_DRP BIT(6) +#define TCPC_ROLE_CTRL_RP_VAL_SHIFT 4 +#define TCPC_ROLE_CTRL_RP_VAL_MASK 0x3 +#define TCPC_ROLE_CTRL_RP_VAL_DEF 0x0 +#define TCPC_ROLE_CTRL_RP_VAL_1_5 0x1 +#define TCPC_ROLE_CTRL_RP_VAL_3_0 0x2 +#define TCPC_ROLE_CTRL_CC2_SHIFT 2 +#define TCPC_ROLE_CTRL_CC2_MASK 0x3 +#define TCPC_ROLE_CTRL_CC1_SHIFT 0 +#define TCPC_ROLE_CTRL_CC1_MASK 0x3 +#define TCPC_ROLE_CTRL_CC_RA 0x0 +#define TCPC_ROLE_CTRL_CC_RP 0x1 +#define TCPC_ROLE_CTRL_CC_RD 0x2 +#define TCPC_ROLE_CTRL_CC_OPEN 0x3 + +#define TCPC_POWER_CTRL 0x1c +#define TCPC_POWER_CTRL_EN_VCONN BIT(0) +#define TCPC_POWER_CTRL_VCONN_POWER BIT(1) +#define TCPC_POWER_CTRL_FORCE_DISCH BIT(2) +#define TCPC_POWER_CTRL_EN_BLEED_CH BIT(3) +#define TCPC_POWER_CTRL_AUTO_DISCH_DISCO BIT(4) +#define TCPC_POWER_CTRL_DIS_V_ALARMS BIT(5) +#define TCPC_POWER_CTRL_VBUS_V_MONITOR BIT(6) + +#define TCPC_CC_STATUS 0x1d +#define TCPC_CC_STATUS_LOOK4CONN BIT(5) +#define TCPC_CC_STATUS_TERM BIT(4) +#define TCPC_CC_STATUS_CC2_SHIFT 2 +#define TCPC_CC_STATUS_CC2_MASK 0x3 +#define TCPC_CC_STATUS_CC1_SHIFT 0 +#define TCPC_CC_STATUS_CC1_MASK 0x3 + +#define TCPC_POWER_STATUS 0x1e +#define TCPC_POWER_STATUS_UNINIT BIT(6) +#define TCPC_POWER_STATUS_VBUS_DET BIT(3) +#define TCPC_POWER_STATUS_VBUS_PRES BIT(2) +#define TCPC_POWER_STATUS_SINKING_VBUS BIT(0) + +#define TCPC_FAULT_STATUS 0x1f + +#define TCPC_COMMAND 0x23 +#define TCPC_CMD_WAKE_I2C 0x11 +#define TCPC_CMD_DISABLE_VBUS_DETECT 0x22 +#define TCPC_CMD_ENABLE_VBUS_DETECT 0x33 +#define TCPC_CMD_DISABLE_SINK_VBUS 0x44 +#define TCPC_CMD_SINK_VBUS 0x55 +#define TCPC_CMD_DISABLE_SRC_VBUS 0x66 +#define TCPC_CMD_SRC_VBUS_DEFAULT 0x77 +#define TCPC_CMD_SRC_VBUS_HIGH 0x88 +#define TCPC_CMD_LOOK4CONNECTION 0x99 +#define TCPC_CMD_RXONEMORE 0xAA +#define TCPC_CMD_I2C_IDLE 0xFF + +#define TCPC_DEV_CAP_1 0x24 +#define TCPC_DEV_CAP_2 0x26 +#define TCPC_STD_INPUT_CAP 0x28 +#define TCPC_STD_OUTPUT_CAP 0x29 + +#define TCPC_MSG_HDR_INFO 0x2e +#define TCPC_MSG_HDR_INFO_DATA_ROLE BIT(3) +#define TCPC_MSG_HDR_INFO_PWR_ROLE BIT(0) +#define TCPC_MSG_HDR_INFO_REV_SHIFT 1 +#define TCPC_MSG_HDR_INFO_REV_MASK 0x3 + +#define TCPC_RX_DETECT 0x2f +#define TCPC_RX_DETECT_HARD_RESET BIT(5) +#define TCPC_RX_DETECT_SOP BIT(0) + +#define TCPC_RX_BYTE_CNT 0x30 +#define TCPC_RX_BUF_FRAME_TYPE 0x31 +#define TCPC_RX_HDR 0x32 +#define TCPC_RX_DATA 0x34 /* through 0x4f */ + +#define TCPC_TRANSMIT 0x50 +#define TCPC_TRANSMIT_RETRY_SHIFT 4 +#define TCPC_TRANSMIT_RETRY_MASK 0x3 +#define TCPC_TRANSMIT_TYPE_SHIFT 0 +#define TCPC_TRANSMIT_TYPE_MASK 0x7 + +#define TCPC_TX_BYTE_CNT 0x51 +#define TCPC_TX_HDR 0x52 +#define TCPC_TX_DATA 0x54 /* through 0x6f */ + +#define TCPC_VBUS_VOLTAGE 0x70 +#define TCPC_VBUS_VOL_MASK 0x3ff +#define TCPC_VBUS_VOL_SCALE_FACTOR_MASK 0xc00 +#define TCPC_VBUS_VOL_SCALE_FACTOR_SHIFT 10 +#define TCPC_VBUS_VOL_MV_UNIT 25 + +#define TCPC_VBUS_SINK_DISCONNECT_THRESH 0x72 +#define TCPC_VBUS_STOP_DISCHARGE_THRESH 0x74 +#define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 +#define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 + +enum typec_role { + TYPEC_SINK, + TYPEC_SOURCE, + TYPEC_ROLE_UNKNOWN, +}; + +enum typec_data_role { + TYPEC_DEVICE, + TYPEC_HOST, +}; + +enum typec_cc_polarity { + TYPEC_POLARITY_CC1, + TYPEC_POLARITY_CC2, +}; + +enum typec_cc_state { + TYPEC_STATE_OPEN, + TYPEC_STATE_SRC_BOTH_RA, + TYPEC_STATE_SRC_RD_RA, + TYPEC_STATE_SRC_RD, + TYPEC_STATE_SRC_RESERVED, + TYPEC_STATE_SNK_DEFAULT, + TYPEC_STATE_SNK_POWER15, + TYPEC_STATE_SNK_POWER30, +}; + + +/* USB PD Messages */ +enum pd_ctrl_msg_type { + /* 0 Reserved */ + PD_CTRL_GOOD_CRC = 1, + PD_CTRL_GOTO_MIN = 2, + PD_CTRL_ACCEPT = 3, + PD_CTRL_REJECT = 4, + PD_CTRL_PING = 5, + PD_CTRL_PS_RDY = 6, + PD_CTRL_GET_SOURCE_CAP = 7, + PD_CTRL_GET_SINK_CAP = 8, + PD_CTRL_DR_SWAP = 9, + PD_CTRL_PR_SWAP = 10, + PD_CTRL_VCONN_SWAP = 11, + PD_CTRL_WAIT = 12, + PD_CTRL_SOFT_RESET = 13, + /* 14-15 Reserved */ +}; + +enum pd_data_msg_type { + /* 0 Reserved */ + PD_DATA_SOURCE_CAP = 1, + PD_DATA_REQUEST = 2, + PD_DATA_BIST = 3, + PD_DATA_SINK_CAP = 4, + /* 5-14 Reserved */ + PD_DATA_VENDOR_DEF = 15, +}; + +enum tcpc_transmit_type { + TCPC_TX_SOP = 0, + TCPC_TX_SOP_PRIME = 1, + TCPC_TX_SOP_PRIME_PRIME = 2, + TCPC_TX_SOP_DEBUG_PRIME = 3, + TCPC_TX_SOP_DEBUG_PRIME_PRIME = 4, + TCPC_TX_HARD_RESET = 5, + TCPC_TX_CABLE_RESET = 6, + TCPC_TX_BIST_MODE_2 = 7 +}; + +enum pd_sink_state{ + UNATTACH = 0, + ATTACHED, + WAIT_SOURCE_CAP, + WAIT_SOURCE_ACCEPT, + WAIT_SOURCE_READY, + SINK_READY, +}; + + +#define PD_REV10 0x0 +#define PD_REV20 0x1 + +#define PD_HEADER_CNT_SHIFT 12 +#define PD_HEADER_CNT_MASK 0x7 +#define PD_HEADER_ID_SHIFT 9 +#define PD_HEADER_ID_MASK 0x7 +#define PD_HEADER_PWR_ROLE BIT(8) +#define PD_HEADER_REV_SHIFT 6 +#define PD_HEADER_REV_MASK 0x3 +#define PD_HEADER_DATA_ROLE BIT(5) +#define PD_HEADER_TYPE_SHIFT 0 +#define PD_HEADER_TYPE_MASK 0xf + +#define PD_HEADER(type, pwr, data, id, cnt) \ + ((((type) & PD_HEADER_TYPE_MASK) << PD_HEADER_TYPE_SHIFT) | \ + ((pwr) == TYPEC_SOURCE ? PD_HEADER_PWR_ROLE : 0) | \ + ((data) == TYPEC_HOST ? PD_HEADER_DATA_ROLE : 0) | \ + (PD_REV20 << PD_HEADER_REV_SHIFT) | \ + (((id) & PD_HEADER_ID_MASK) << PD_HEADER_ID_SHIFT) | \ + (((cnt) & PD_HEADER_CNT_MASK) << PD_HEADER_CNT_SHIFT)) + + +static inline unsigned int pd_header_cnt(uint16_t header) +{ + return (header >> PD_HEADER_CNT_SHIFT) & PD_HEADER_CNT_MASK; +} + +static inline unsigned int pd_header_cnt_le(__le16 header) +{ + return pd_header_cnt(le16_to_cpu(header)); +} + +static inline unsigned int pd_header_type(uint16_t header) +{ + return (header >> PD_HEADER_TYPE_SHIFT) & PD_HEADER_TYPE_MASK; +} + +static inline unsigned int pd_header_type_le(__le16 header) +{ + return pd_header_type(le16_to_cpu(header)); +} + +#define PD_MAX_PAYLOAD 7 + +struct pd_message { + uint8_t frametype; + uint16_t header; + uint32_t payload[PD_MAX_PAYLOAD]; +} __packed; + +enum pd_pdo_type { + PDO_TYPE_FIXED = 0, + PDO_TYPE_BATT = 1, + PDO_TYPE_VAR = 2, +}; + + +#define PDO_TYPE_SHIFT 30 +#define PDO_TYPE_MASK 0x3 + +#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) + +#define PDO_VOLT_MASK 0x3ff +#define PDO_CURR_MASK 0x3ff +#define PDO_PWR_MASK 0x3ff + +#define PDO_FIXED_DUAL_ROLE BIT(29) /* Power role swap supported */ +#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported (Source) */ +#define PDO_FIXED_HIGHER_CAP BIT(28) /* Requires more than vSafe5V (Sink) */ +#define PDO_FIXED_EXTPOWER BIT(27) /* Externally powered */ +#define PDO_FIXED_USB_COMM BIT(26) /* USB communications capable */ +#define PDO_FIXED_DATA_SWAP BIT(25) /* Data role swap supported */ +#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) +#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) + +#define PDO_FIXED(mv, ma, flags) \ + (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ + PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) + +#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ + +#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) +#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) +#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) + +#define PDO_BATT(min_mv, max_mv, max_mw) \ + (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ + PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) + +#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) +#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) +#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) + +#define PDO_VAR(min_mv, max_mv, max_ma) \ + (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ + PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) + +static inline enum pd_pdo_type pdo_type(uint32_t pdo) +{ + return (pdo >> PDO_TYPE_SHIFT) & PDO_TYPE_MASK; +} + +static inline unsigned int pdo_fixed_voltage(uint32_t pdo) +{ + return ((pdo >> PDO_FIXED_VOLT_SHIFT) & PDO_VOLT_MASK) * 50; +} + +static inline unsigned int pdo_min_voltage(uint32_t pdo) +{ + return ((pdo >> PDO_VAR_MIN_VOLT_SHIFT) & PDO_VOLT_MASK) * 50; +} + +static inline unsigned int pdo_max_voltage(uint32_t pdo) +{ + return ((pdo >> PDO_VAR_MAX_VOLT_SHIFT) & PDO_VOLT_MASK) * 50; +} + +static inline unsigned int pdo_max_current(uint32_t pdo) +{ + return ((pdo >> PDO_VAR_MAX_CURR_SHIFT) & PDO_CURR_MASK) * 10; +} + +static inline unsigned int pdo_max_power(uint32_t pdo) +{ + return ((pdo >> PDO_BATT_MAX_PWR_SHIFT) & PDO_PWR_MASK) * 250; +} + +/* RDO: Request Data Object */ +#define RDO_OBJ_POS_SHIFT 28 +#define RDO_OBJ_POS_MASK 0x7 +#define RDO_GIVE_BACK BIT(27) /* Supports reduced operating current */ +#define RDO_CAP_MISMATCH BIT(26) /* Not satisfied by source caps */ +#define RDO_USB_COMM BIT(25) /* USB communications capable */ +#define RDO_NO_SUSPEND BIT(24) /* USB Suspend not supported */ + +#define RDO_PWR_MASK 0x3ff +#define RDO_CURR_MASK 0x3ff + +#define RDO_FIXED_OP_CURR_SHIFT 10 +#define RDO_FIXED_MAX_CURR_SHIFT 0 + +#define RDO_OBJ(idx) (((idx) & RDO_OBJ_POS_MASK) << RDO_OBJ_POS_SHIFT) + +#define PDO_FIXED_OP_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_OP_CURR_SHIFT) +#define PDO_FIXED_MAX_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_MAX_CURR_SHIFT) + +#define RDO_FIXED(idx, op_ma, max_ma, flags) \ + (RDO_OBJ(idx) | (flags) | \ + PDO_FIXED_OP_CURR(op_ma) | PDO_FIXED_MAX_CURR(max_ma)) + +#define RDO_BATT_OP_PWR_SHIFT 10 /* 250mW units */ +#define RDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ + +#define RDO_BATT_OP_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_OP_PWR_SHIFT) +#define RDO_BATT_MAX_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_MAX_PWR_SHIFT) + +#define RDO_BATT(idx, op_mw, max_mw, flags) \ + (RDO_OBJ(idx) | (flags) | \ + RDO_BATT_OP_PWR(op_mw) | RDO_BATT_MAX_PWR(max_mw)) + +static inline unsigned int rdo_index(u32 rdo) +{ + return (rdo >> RDO_OBJ_POS_SHIFT) & RDO_OBJ_POS_MASK; +} + +static inline unsigned int rdo_op_current(u32 rdo) +{ + return ((rdo >> RDO_FIXED_OP_CURR_SHIFT) & RDO_CURR_MASK) * 10; +} + +static inline unsigned int rdo_max_current(u32 rdo) +{ + return ((rdo >> RDO_FIXED_MAX_CURR_SHIFT) & + RDO_CURR_MASK) * 10; +} + +static inline unsigned int rdo_op_power(u32 rdo) +{ + return ((rdo >> RDO_BATT_OP_PWR_SHIFT) & RDO_PWR_MASK) * 250; +} + +static inline unsigned int rdo_max_power(u32 rdo) +{ + return ((rdo >> RDO_BATT_MAX_PWR_SHIFT) & RDO_PWR_MASK) * 250; +} + +#define TCPC_LOG_BUFFER_SIZE 1024 + +struct tcpc_port; + +typedef void (*ss_mux_sel)(enum typec_cc_polarity pol); +typedef int (*ext_pd_switch_setup)(struct tcpc_port *port_p); + +enum tcpc_port_type { + TYPEC_PORT_DFP, + TYPEC_PORT_UFP, + TYPEC_PORT_DRP, +}; + +struct tcpc_port_config { + uint8_t i2c_bus; + uint8_t addr; + enum tcpc_port_type port_type; + uint32_t max_snk_mv; + uint32_t max_snk_ma; + uint32_t max_snk_mw; + uint32_t op_snk_mv; + bool disable_pd; + ext_pd_switch_setup switch_setup_func; +}; + +struct tcpc_port { + struct tcpc_port_config cfg; + struct udevice *i2c_dev; + ss_mux_sel ss_sel_func; + enum pd_sink_state pd_state; + uint32_t tx_msg_id; + uint32_t log_size; + char logbuffer[TCPC_LOG_BUFFER_SIZE]; + char *log_p; + char *log_print; +}; + +int tcpc_set_cc_to_source(struct tcpc_port *port); +int tcpc_set_cc_to_sink(struct tcpc_port *port); +int tcpc_set_plug_orientation(struct tcpc_port *port, enum typec_cc_polarity polarity); +int tcpc_get_cc_status(struct tcpc_port *port, enum typec_cc_polarity *polarity, enum typec_cc_state *state); +int tcpc_clear_alert(struct tcpc_port *port, uint16_t clear_mask); +int tcpc_send_command(struct tcpc_port *port, uint8_t command); +int tcpc_polling_reg(struct tcpc_port *port, uint8_t reg, + uint8_t reg_width, uint16_t mask, uint16_t value, ulong timeout_ms); +int tcpc_setup_dfp_mode(struct tcpc_port *port); +int tcpc_setup_ufp_mode(struct tcpc_port *port); +int tcpc_disable_src_vbus(struct tcpc_port *port); +int tcpc_init(struct tcpc_port *port, struct tcpc_port_config config, ss_mux_sel ss_sel_func); +bool tcpc_pd_sink_check_charging(struct tcpc_port *port); +void tcpc_print_log(struct tcpc_port *port); + +#ifdef CONFIG_SPL_BUILD +int tcpc_setup_ufp_mode(struct tcpc_port *port) +{ + return 0; +} +int tcpc_setup_dfp_mode(struct tcpc_port *port) +{ + return 0; +} + +int tcpc_disable_src_vbus(struct tcpc_port *port) +{ + return 0; +} +#endif +#endif /* __TCPCI_H */ diff --git a/board/freescale/imx8mm_evk/Kconfig b/board/freescale/imx8mm_evk/Kconfig new file mode 100644 index 00000000000..88949d7bab9 --- /dev/null +++ b/board/freescale/imx8mm_evk/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8MM_EVK || TARGET_IMX8MM_DDR4_EVK + +config SYS_BOARD + default "imx8mm_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mm_evk" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile new file mode 100644 index 00000000000..f6e5510b281 --- /dev/null +++ b/board/freescale/imx8mm_evk/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mm_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o +endif diff --git a/board/freescale/imx8mm_evk/ddr4_timing.c b/board/freescale/imx8mm_evk/ddr4_timing.c new file mode 100644 index 00000000000..3d784ae8cb1 --- /dev/null +++ b/board/freescale/imx8mm_evk/ddr4_timing.c @@ -0,0 +1,1482 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +struct dram_cfg_param ddr4_ddrc_cfg[] = { + /* Start to config, default 2400mbps */ + { DDRC_MSTR(0), 0x81040010 }, + { DDRC_PWRCTL(0), 0x000000aa }, + { DDRC_PWRTMG(0), 0x00221306 }, + { DDRC_RFSHCTL0(0), 0x00c0a070 }, + { DDRC_RFSHCTL1(0), 0x00010008 }, + { DDRC_RFSHCTL3(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x004980f4 }, + { DDRC_CRCPARCTL0(0), 0x00000000 }, + { DDRC_CRCPARCTL1(0), 0x00001010 }, + { DDRC_INIT0(0), 0xc0030002 }, + { DDRC_INIT1(0), 0x00020009 }, + { DDRC_INIT2(0), 0x0000350f }, + { DDRC_INIT3(0), (0xa34 << 16) | 0x105 }, + { DDRC_INIT4(0), (0x1028 << 16) | 0x200 }, + { DDRC_INIT5(0), 0x001103cb }, + { DDRC_INIT6(0), (0x200 << 16) | 0x200 }, + { DDRC_INIT7(0), 0x814 }, + { DDRC_DIMMCTL(0), 0x00000032 }, + { DDRC_RANKCTL(0), 0x00000fc7 }, + { DDRC_DRAMTMG0(0), 0x14132813 }, + { DDRC_DRAMTMG1(0), 0x0004051b }, + { DDRC_DRAMTMG2(0), 0x0808030f }, + { DDRC_DRAMTMG3(0), 0x0000400c }, + { DDRC_DRAMTMG4(0), 0x08030409 }, + { DDRC_DRAMTMG5(0), 0x0e090504 }, + { DDRC_DRAMTMG6(0), 0x05030000 }, + { DDRC_DRAMTMG7(0), 0x0000090e }, + { DDRC_DRAMTMG8(0), 0x0606700c }, + { DDRC_DRAMTMG9(0), 0x0002040c }, + { DDRC_DRAMTMG10(0), 0x000f0c07 }, + { DDRC_DRAMTMG11(0), 0x1809011d }, + { DDRC_DRAMTMG12(0), 0x0000000d }, + { DDRC_DRAMTMG13(0), 0x2b000000 }, + { DDRC_DRAMTMG14(0), 0x000000a4 }, + { DDRC_DRAMTMG15(0), 0x00000000 }, + { DDRC_DRAMTMG17(0), 0x00250078 }, + { DDRC_ZQCTL0(0), 0x51000040 }, + { DDRC_ZQCTL1(0), 0x00000070 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + { DDRC_DFITMG0(0), 0x038b820b }, + { DDRC_DFITMG1(0), 0x02020103 }, + { DDRC_DFILPCFG0(0), 0x07f04011 }, + { DDRC_DFILPCFG1(0), 0x000000b0 }, + { DDRC_DFIUPD0(0), 0xe0400018 }, + { DDRC_DFIUPD1(0), 0x0048005a }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000001 }, + { DDRC_DFITMG2(0), 0x00000b0b }, + { DDRC_DFITMG3(0), 0x00000001 }, + { DDRC_DBICTL(0), 0x00000000 }, + { DDRC_DFIPHYMSTR(0), 0x00000000 }, + + /* MT40A512M16 addr map */ + { DDRC_ADDRMAP0(0), 0x0000001F }, + { DDRC_ADDRMAP1(0), 0x003F0909 }, + { DDRC_ADDRMAP2(0), 0x01010100 }, + { DDRC_ADDRMAP3(0), 0x01010101 }, + { DDRC_ADDRMAP4(0), 0x00001f1f }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x07070707 }, + { DDRC_ADDRMAP7(0), 0x00000f0f }, + { DDRC_ADDRMAP8(0), 0x00003F01 }, + { DDRC_ADDRMAP9(0), 0x0a020b06 }, + { DDRC_ADDRMAP10(0), 0x0a0a0a0a }, + { DDRC_ADDRMAP11(0), 0x00000000 }, + + { DDRC_ODTCFG(0), 0x07000600 }, + { DDRC_ODTMAP(0), 0x0001 }, + + /* P1 400mts */ + { DDRC_FREQ1_RFSHCTL0(0), 0x0021a0c0 }, + { DDRC_FREQ1_RFSHTMG(0), 0x0018001a }, + { DDRC_FREQ1_INIT3(0), (0x204 << 16) | 0x104 }, + { DDRC_FREQ1_INIT4(0), (0x1000 << 16) }, + { DDRC_FREQ1_INIT6(0), (0x200 << 16) | 0x200 }, + { DDRC_FREQ1_INIT7(0), 0x14 }, + { DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0604 }, /* t_ras_max=9*7.8us, t_ras_min=35ns */ + { DDRC_FREQ1_DRAMTMG1(0), 0x00030314 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0505040a }, + { DDRC_FREQ1_DRAMTMG3(0), 0x0000400c }, + { DDRC_FREQ1_DRAMTMG4(0), 0x06040307 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x090d0202 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a070008 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x00000d09 }, + { DDRC_FREQ1_DRAMTMG8(0), 0x08084b09 }, + { DDRC_FREQ1_DRAMTMG9(0), 0x00020308 }, + { DDRC_FREQ1_DRAMTMG10(0), 0x000f0d06 }, + { DDRC_FREQ1_DRAMTMG11(0), 0x12060111 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x00000008 }, + { DDRC_FREQ1_DRAMTMG13(0), 0x21000000 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x00c6007d }, + { DDRC_FREQ1_ZQCTL0(0), 0x51000040 }, + { DDRC_FREQ1_DFITMG0(0), 0x03858204 }, + { DDRC_FREQ1_DFITMG1(0), 0x00020103 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000504 }, + { DDRC_FREQ1_DFITMG3(0), 0x00000001 }, + { DDRC_FREQ1_ODTCFG(0), 0x07000601 }, + + /* p2 100mts */ + { DDRC_FREQ2_RFSHCTL0(0), 0x0021a0c0 }, + { DDRC_FREQ2_RFSHTMG(0), 0x0006000e }, /* tREFI=7.8us */ + { DDRC_FREQ2_INIT3(0), (0x204 << 16) | 0x104 }, + { DDRC_FREQ2_INIT4(0), (0x1000 << 16) }, + { DDRC_FREQ2_INIT6(0), (0x200 << 16) | 0x200 }, + { DDRC_FREQ2_INIT7(0), 0x14 }, + { DDRC_FREQ2_DRAMTMG0(0), 0x0c0e0101 }, /* t_ras_max=9*7.8us, t_ras_min=35ns */ + { DDRC_FREQ2_DRAMTMG1(0), 0x00030314 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0505040a }, + { DDRC_FREQ2_DRAMTMG3(0), 0x0000400c }, + { DDRC_FREQ2_DRAMTMG4(0), 0x06040307 }, /* tRP=6 --> 7 */ + { DDRC_FREQ2_DRAMTMG5(0), 0x090d0202 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a070008 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x00000d09 }, + { DDRC_FREQ2_DRAMTMG8(0), 0x08084b09 }, + { DDRC_FREQ2_DRAMTMG9(0), 0x00020308 }, + { DDRC_FREQ2_DRAMTMG10(0), 0x000f0d06 }, + { DDRC_FREQ2_DRAMTMG11(0), 0x12060111 }, + { DDRC_FREQ2_DRAMTMG12(0), 0x00000008 }, + { DDRC_FREQ2_DRAMTMG13(0), 0x21000000 }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000000 }, + { DDRC_FREQ2_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x00c6007d }, + { DDRC_FREQ2_ZQCTL0(0), 0x51000040 }, + { DDRC_FREQ2_DFITMG0(0), 0x03858204 }, + { DDRC_FREQ2_DFITMG1(0), 0x00020103 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000504 }, + { DDRC_FREQ2_DFITMG3(0), 0x00000001 }, + { DDRC_FREQ2_ODTCFG(0), 0x07000601 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr4_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */ + { 0x1015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */ + { 0x1105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */ + { 0x1115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */ + { 0x1205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */ + { 0x1215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */ + { 0x1305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */ + { 0x1315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */ + + { 0x11005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 */ + { 0x11015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 */ + { 0x11105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 */ + { 0x11115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 */ + { 0x11205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 */ + { 0x11215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 */ + { 0x11305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 */ + { 0x11315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 */ + + { 0x21005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 */ + { 0x21015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 */ + { 0x21105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 */ + { 0x21115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 */ + { 0x21205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 */ + { 0x21215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 */ + { 0x21305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 */ + { 0x21315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 */ + + { 0x55, 0x355 }, /* DWC_DDRPHYA_ANIB0_ATxSlewRate */ + { 0x1055, 0x355 }, /* DWC_DDRPHYA_ANIB1_ATxSlewRate */ + { 0x2055, 0x355 }, /* DWC_DDRPHYA_ANIB2_ATxSlewRate */ + { 0x3055, 0x355 }, /* DWC_DDRPHYA_ANIB3_ATxSlewRate */ + { 0x4055, 0x55 }, /* DWC_DDRPHYA_ANIB4_ATxSlewRate */ + { 0x5055, 0x55 }, /* DWC_DDRPHYA_ANIB5_ATxSlewRate */ + { 0x6055, 0x355 }, /* DWC_DDRPHYA_ANIB6_ATxSlewRate */ + { 0x7055, 0x355 }, /* DWC_DDRPHYA_ANIB7_ATxSlewRate */ + { 0x8055, 0x355 }, /* DWC_DDRPHYA_ANIB8_ATxSlewRate */ + { 0x9055, 0x355 }, /* DWC_DDRPHYA_ANIB9_ATxSlewRate */ + + { 0x200c5, 0xa }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */ + { 0x1200c5, 0x7 }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p1 */ + { 0x2200c5, 0x7 }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p2 */ + + { 0x2002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */ + { 0x12002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 */ + { 0x22002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 */ + + { 0x20024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */ + { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + + { 0x120024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 */ + { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + + { 0x220024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 */ + { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + + { 0x20056, 0x6 },/* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */ + { 0x120056, 0xa }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 */ + { 0x220056, 0xa }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 */ + + { 0x1004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */ + { 0x1014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */ + { 0x1104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */ + { 0x1114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */ + { 0x1204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */ + { 0x1214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */ + { 0x1304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */ + { 0x1314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */ + + { 0x11004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 */ + { 0x11014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 */ + { 0x11104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 */ + { 0x11114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 */ + { 0x11204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 */ + { 0x11214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 */ + { 0x11304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 */ + { 0x11314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 */ + + { 0x21004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 */ + { 0x21014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 */ + { 0x21104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 */ + { 0x21114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 */ + { 0x21204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 */ + { 0x21214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 */ + { 0x21304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 */ + { 0x21314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 */ + + { 0x10049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */ + { 0x10149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */ + { 0x11049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */ + { 0x11149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */ + { 0x12049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */ + { 0x12149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */ + { 0x13049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */ + { 0x13149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */ + + { 0x110049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 */ + { 0x110149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 */ + { 0x111049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 */ + { 0x111149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 */ + { 0x112049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 */ + { 0x112149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 */ + { 0x113049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 */ + { 0x113149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 */ + + { 0x210049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 */ + { 0x210149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 */ + { 0x211049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 */ + { 0x211149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 */ + { 0x212049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 */ + { 0x212149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 */ + { 0x213049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 */ + { 0x213149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 */ + + { 0x43, 0x63 }, /* DWC_DDRPHYA_ANIB0_ATxImpedance */ + { 0x1043, 0x63 }, /* DWC_DDRPHYA_ANIB1_ATxImpedance */ + { 0x2043, 0x63 }, /* DWC_DDRPHYA_ANIB2_ATxImpedance */ + { 0x3043, 0x63 }, /* DWC_DDRPHYA_ANIB3_ATxImpedance */ + { 0x4043, 0x63 }, /* DWC_DDRPHYA_ANIB4_ATxImpedance */ + { 0x5043, 0x63 }, /* DWC_DDRPHYA_ANIB5_ATxImpedance */ + { 0x6043, 0x63 }, /* DWC_DDRPHYA_ANIB6_ATxImpedance */ + { 0x7043, 0x63 }, /* DWC_DDRPHYA_ANIB7_ATxImpedance */ + { 0x8043, 0x63 }, /* DWC_DDRPHYA_ANIB8_ATxImpedance */ + { 0x9043, 0x63 }, /* DWC_DDRPHYA_ANIB9_ATxImpedance */ + + { 0x20018, 0x5 }, /* DWC_DDRPHYA_MASTER0_DfiMode */ + { 0x20075, 0x2 }, /* DWC_DDRPHYA_MASTER0_DfiCAMode */ + { 0x20050, 0x0 }, /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */ + { 0x20008, 0x258 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */ + { 0x120008, 0x64 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 */ + { 0x220008, 0x19 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 */ + { 0x20088, 0x9 }, /* DWC_DDRPHYA_MASTER0_CalRate */ + + { 0x200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */ + { 0x10043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */ + { 0x10143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */ + { 0x11043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */ + { 0x11143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */ + { 0x12043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */ + { 0x12143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */ + { 0x13043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */ + { 0x13143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */ + + { 0x1200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 */ + { 0x110043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 */ + { 0x110143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 */ + { 0x111043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 */ + { 0x111143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 */ + { 0x112043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 */ + { 0x112143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 */ + { 0x113043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 */ + { 0x113143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 */ + + { 0x2200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 */ + { 0x210043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 */ + { 0x210143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 */ + { 0x211043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 */ + { 0x211143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 */ + { 0x212043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 */ + { 0x212143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 */ + { 0x213043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 */ + { 0x213143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 */ + + { 0x2005b, 0x7529 }, /* DWC_DDRPHYA_MASTER0_MemAlertControl */ + { 0x2005c, 0x0 }, /* DWC_DDRPHYA_MASTER0_MemAlertControl2 */ + { 0x200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */ + { 0x1200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 */ + { 0x2200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 */ + { 0x20019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */ + { 0x120019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p1 */ + { 0x220019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p2 */ + + { 0x200f0, 0x5665 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */ + { 0x200f1, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */ + { 0x200f2, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */ + { 0x200f3, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */ + { 0x200f4, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */ + { 0x200f5, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */ + { 0x200f6, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */ + { 0x200f7, 0xf000 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */ + { 0x20025, 0x0 }, /* DWC_DDRPHYA_MASTER0_MasterX4Config */ + { 0x2002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */ + { 0x12002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p1 */ + { 0x22002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p2 */ + { 0x200c7, 0x21 }, /* DWC_DDRPHYA_MASTER0_PllCtrl1_p0 */ + { 0x200ca, 0x24 }, /* DWC_DDRPHYA_MASTER0_PllTestMode_p0 */ +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr4_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr4_fsp0_cfg[] = { + { 0x20060, 0x2 }, + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x0 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x54009, 0x0 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x1 }, + { 0x5402f, 0xa34 }, + { 0x54030, 0x105 }, + { 0x54031, 0x1028 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x200 }, + { 0x54035, 0x814 }, + { 0x54036, 0x101 }, + { 0x54037, 0x0 }, + { 0x54038, 0x0 }, + { 0x54039, 0x0 }, + { 0x5403a, 0x0 }, + { 0x5403b, 0x0 }, + { 0x5403c, 0x0 }, + { 0x5403d, 0x0 }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x0 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x54009, 0x0 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x204 }, + { 0x54030, 0x104 }, + { 0x54031, 0x1000 }, + { 0x54032, 0x0 }, + { 0x54033, 0x200 }, + { 0x54034, 0x200 }, + { 0x54035, 0x14 }, + { 0x54036, 0x101 }, + { 0x54037, 0x0 }, + { 0x54038, 0x0 }, + { 0x54039, 0x0 }, + { 0x5403a, 0x0 }, + { 0x5403b, 0x0 }, + { 0x5403c, 0x0 }, + { 0x5403d, 0x0 }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x0 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x54009, 0x0 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x204 }, + { 0x54030, 0x104 }, + { 0x54031, 0x1000 }, + { 0x54032, 0x0 }, + { 0x54033, 0x200 }, + { 0x54034, 0x200 }, + { 0x54035, 0x14 }, + { 0x54036, 0x101 }, + { 0x54037, 0x0 }, + { 0x54038, 0x0 }, + { 0x54039, 0x0 }, + { 0x5403a, 0x0 }, + { 0x5403b, 0x0 }, + { 0x5403c, 0x0 }, + { 0x5403d, 0x0 }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, + +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x0 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x54009, 0x0 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x1 }, + { 0x5402f, 0xa34 }, + { 0x54030, 0x105 }, + { 0x54031, 0x1028 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x200 }, + { 0x54035, 0x814 }, + { 0x54036, 0x101 }, + { 0x54037, 0x0 }, + { 0x54038, 0x0 }, + { 0x54039, 0x0 }, + { 0x5403a, 0x0 }, + { 0x5403b, 0x0 }, + { 0x5403c, 0x0 }, + { 0x5403d, 0x0 }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr4_phy_pie[] = { + { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + { 0x90000, 0x10 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */ + { 0x90001, 0x400 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */ + { 0x90002, 0x10e }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */ + { 0x90003, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */ + { 0x90004, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */ + { 0x90005, 0x8 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */ + { 0x90029, 0xb }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */ + { 0x9002a, 0x480 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */ + { 0x9002b, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */ + { 0x9002c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */ + { 0x9002d, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */ + { 0x9002e, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */ + { 0x9002f, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */ + { 0x90030, 0x478 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */ + { 0x90031, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */ + { 0x90032, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */ + { 0x90033, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */ + { 0x90034, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */ + { 0x90035, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */ + { 0x90036, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */ + { 0x90037, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */ + { 0x90038, 0x44 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */ + { 0x90039, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */ + { 0x9003a, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */ + { 0x9003b, 0x14f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */ + { 0x9003c, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */ + { 0x9003d, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */ + { 0x9003e, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */ + { 0x9003f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */ + { 0x90040, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */ + { 0x90041, 0x4f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */ + { 0x90042, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */ + { 0x90043, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */ + { 0x90044, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */ + { 0x90045, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */ + { 0x90046, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */ + { 0x90047, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */ + { 0x90048, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */ + { 0x90049, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */ + { 0x9004a, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */ + { 0x9004b, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */ + { 0x9004c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */ + { 0x9004d, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */ + { 0x9004e, 0x45a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */ + { 0x9004f, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */ + { 0x90050, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */ + { 0x90051, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */ + { 0x90052, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */ + { 0x90053, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */ + { 0x90054, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */ + { 0x90055, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */ + { 0x90056, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */ + { 0x90057, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */ + { 0x90058, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */ + { 0x90059, 0x40c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */ + { 0x9005a, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */ + { 0x9005b, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */ + { 0x9005c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */ + { 0x9005d, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */ + { 0x9005e, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */ + { 0x9005f, 0x4040 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */ + { 0x90060, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */ + { 0x90061, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */ + { 0x90062, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */ + { 0x90063, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */ + { 0x90064, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */ + { 0x90065, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */ + { 0x90066, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */ + { 0x90067, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */ + { 0x90068, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */ + { 0x90069, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */ + { 0x9006a, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */ + { 0x9006b, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */ + { 0x9006c, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */ + { 0x9006d, 0x78 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */ + { 0x9006e, 0x549 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */ + { 0x9006f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */ + { 0x90070, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */ + { 0x90071, 0xd49 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */ + { 0x90072, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */ + { 0x90073, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */ + { 0x90074, 0x94a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */ + { 0x90075, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */ + { 0x90076, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */ + { 0x90077, 0x441 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */ + { 0x90078, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */ + { 0x90079, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */ + { 0x9007a, 0x42 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */ + { 0x9007b, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */ + { 0x9007c, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */ + { 0x9007d, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */ + { 0x9007e, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */ + { 0x9007f, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */ + { 0x90080, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */ + { 0x90081, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */ + { 0x90082, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */ + { 0x90083, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */ + { 0x90084, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */ + { 0x90085, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */ + { 0x90086, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */ + { 0x90087, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */ + { 0x90088, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */ + { 0x90089, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */ + { 0x9008a, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */ + { 0x9008b, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */ + { 0x9008c, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */ + { 0x9008d, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */ + { 0x9008e, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */ + { 0x9008f, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */ + { 0x90090, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */ + { 0x90091, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */ + { 0x90092, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */ + { 0x90093, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */ + { 0x90094, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */ + { 0x90095, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */ + { 0x90096, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */ + { 0x90097, 0x58 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */ + { 0x90098, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */ + { 0x90099, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */ + { 0x9009a, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */ + { 0x9009b, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */ + { 0x9009c, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */ + { 0x9009d, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */ + { 0x9009e, 0x7 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */ + { 0x9009f, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */ + { 0x900a0, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */ + { 0x900a1, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */ + { 0x900a2, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */ + { 0x900a3, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */ + { 0x900a4, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */ + { 0x900a5, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */ + { 0x900a6, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */ + { 0x900a7, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */ + { 0x900a8, 0x8138 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */ + { 0x900a9, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */ + { 0x900aa, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */ + { 0x900ab, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */ + { 0x900ac, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */ + { 0x900ad, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */ + { 0x900ae, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */ + { 0x900af, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */ + { 0x900b0, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */ + { 0x900b1, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */ + { 0x900b2, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */ + { 0x900b3, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */ + { 0x900b4, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */ + { 0x900b5, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */ + { 0x900b6, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */ + { 0x900b7, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */ + { 0x900b8, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */ + { 0x900b9, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */ + { 0x900ba, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */ + { 0x900bb, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */ + { 0x900bc, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */ + { 0x900bd, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */ + { 0x900be, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */ + { 0x900bf, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */ + { 0x900c0, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */ + { 0x900c1, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */ + { 0x900c2, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */ + { 0x900c3, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */ + { 0x900c4, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */ + { 0x900c5, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */ + { 0x900c6, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */ + { 0x900c7, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */ + { 0x900c8, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */ + { 0x900c9, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */ + { 0x900ca, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */ + { 0x900cb, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */ + { 0x900cc, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */ + { 0x900cd, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */ + { 0x90006, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */ + { 0x90007, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */ + { 0x90008, 0x8 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */ + { 0x90009, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */ + { 0x9000a, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */ + { 0x9000b, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */ + { 0xd00e7, 0x400 }, /* DWC_DDRPHYA_APBONLY0_SequencerOverride */ + { 0x90017, 0x0 }, /* DWC_DDRPHYA_INITENG0_StartVector0b0 */ + { 0x90026, 0x2c }, /* DWC_DDRPHYA_INITENG0_StartVector0b15 */ + { 0x2000b, 0x4b }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */ + { 0x2000c, 0x96 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */ + { 0x2000d, 0x5dc }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */ + { 0x2000e, 0x2c }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */ + { 0x12000b, 0xc }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */ + { 0x12000c, 0x19 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */ + { 0x12000d, 0xfa }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */ + { 0x12000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */ + { 0x22000b, 0x3 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */ + { 0x22000c, 0x6 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */ + { 0x22000d, 0x3e }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */ + { 0x22000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */ + { 0x9000c, 0x0 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */ + { 0x9000d, 0x173 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */ + { 0x9000e, 0x60 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */ + { 0x9000f, 0x6110 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */ + { 0x90010, 0x2152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */ + { 0x90011, 0xdfbd }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */ + { 0x90012, 0xffff }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */ + { 0x90013, 0x6152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */ + { 0xc0080, 0x0 }, /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +}; + +struct dram_fsp_msg ddr4_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_2d_cfg), + }, +}; + +/* ddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr4_ddrc_cfg), + .ddrphy_cfg = ddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr4_ddrphy_cfg), + .fsp_msg = ddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr4_dram_fsp_msg), + .ddrphy_trained_csr = ddr4_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr4_ddrphy_trained_csr), + .ddrphy_pie = ddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr4_phy_pie), +}; diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c new file mode 100644 index 00000000000..a1b7e08c99b --- /dev/null +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -0,0 +1,735 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_FSPI +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) +static iomux_v3_cfg_t const qspi_pads[] = { + IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL | PAD_CTL_PE | PAD_CTL_PUE), + IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); + + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +#define SPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) +static iomux_v3_cfg_t const ecspi1_pads[] = { + IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const ecspi2_pads[] = { + IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + gpio_request(IMX_GPIO_NR(5, 9), "ECSPI1 CS"); + gpio_request(IMX_GPIO_NR(5, 13), "ECSPI2 CS"); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + if (bus == 0) + return IMX_GPIO_NR(5, 9); + else + return IMX_GPIO_NR(5, 13); +} +#endif + +#ifdef CONFIG_NAND_MXS +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS) +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE) +static iomux_v3_cfg_t const gpmi_pads[] = { + IMX8MM_PAD_NAND_ALE_RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), + IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); +} +#endif + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); /* SPL will call the board_early_init_f */ +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + /* TODO */ + return 0; +} +#endif + +int dram_init(void) +{ + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; + else + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +#define FEC_RST_PAD IMX_GPIO_NR(4, 22) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(FEC_RST_PAD, "fec1_rst"); + gpio_direction_output(FEC_RST_PAD, 0); + udelay(500); + gpio_direction_output(FEC_RST_PAD, 1); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port port2; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + return 0; +} + +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(1, 0x72); + } else if (port == &port2) { + debug("Setup pd switch on port 2\n"); + return setup_pd_switch(1, 0x73); + } else + return -EINVAL; +} + +struct tcpc_port_config port1_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +struct tcpc_port_config port2_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x52, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +static int setup_typec(void) +{ + int ret; + + debug("tcpc_init port 2\n"); + ret = tcpc_init(&port2, port2_config, NULL); + if (ret) { + printf("%s: tcpc port2 init failed, err=%d\n", + __func__, ret); + } else if (tcpc_pd_sink_check_charging(&port2)) { + /* Disable PD for USB1, since USB2 has priority */ + port1_config.disable_pd = true; + printf("Power supply on USB2\n"); + } + + debug("tcpc_init port 1\n"); + ret = tcpc_init(&port1, port1_config, NULL); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } else { + if (!port1_config.disable_pd) + printf("Power supply on USB1\n"); + return ret; + } + + return ret; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + struct tcpc_port *port_ptr; + + debug("board_usb_init %d, type %d\n", index, init); + + if (index == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + imx8m_usb_power(index, true); + + if (init == USB_INIT_HOST) + tcpc_setup_dfp_mode(port_ptr); + else + tcpc_setup_ufp_mode(port_ptr); + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + debug("board_usb_cleanup %d, type %d\n", index, init); + + if (init == USB_INIT_HOST) { + if (index == 0) + ret = tcpc_disable_src_vbus(&port1); + else + ret = tcpc_disable_src_vbus(&port2); + } + + imx8m_usb_power(index, false); + return ret; +} + +int board_ehci_usb_phy_mode(struct udevice *dev) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + struct tcpc_port *port_ptr; + + if (dev->seq == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + tcpc_setup_ufp_mode(port_ptr); + + ret = tcpc_get_cc_status(port_ptr, &pol, &state); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; +} + +#endif + +int board_init(void) +{ +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_FSL_FSPI + board_qspi_init(); +#endif + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno + 1; +} + +#ifdef CONFIG_VIDEO_MXS + +#define ADV7535_MAIN 0x3d +#define ADV7535_DSI_CEC 0x3c + +static const struct sec_mipi_dsim_plat_data imx8mm_mipi_dsim_plat_data = { + .version = 0x1060200, + .max_data_lanes = 4, + .max_data_rate = 1500000000ULL, + .reg_base = MIPI_DSI_BASE_ADDR, + .gpr_base = CSI_BASE_ADDR + 0x8000, +}; + +static int adv7535_i2c_reg_write(struct udevice *dev, uint addr, uint mask, uint data) +{ + uint8_t valb; + int err; + + if (mask != 0xff) { + err = dm_i2c_read(dev, addr, &valb, 1); + if (err) + return err; + + valb &= ~mask; + valb |= data; + } else { + valb = data; + } + + err = dm_i2c_write(dev, addr, &valb, 1); + return err; +} + +static int adv7535_i2c_reg_read(struct udevice *dev, uint8_t addr, uint8_t *data) +{ + uint8_t valb; + int err; + + err = dm_i2c_read(dev, addr, &valb, 1); + if (err) + return err; + + *data = (int)valb; + return 0; +} + +static void adv7535_init(void) +{ + struct udevice *bus, *main_dev, *cec_dev; + int i2c_bus = 1; + int ret; + uint8_t val; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: No bus %d\n", __func__, i2c_bus); + return; + } + + ret = dm_i2c_probe(bus, ADV7535_MAIN, 0, &main_dev); + if (ret) { + printf("%s: Can't find device id=0x%x, on bus %d\n", + __func__, ADV7535_MAIN, i2c_bus); + return; + } + + ret = dm_i2c_probe(bus, ADV7535_DSI_CEC, 0, &cec_dev); + if (ret) { + printf("%s: Can't find device id=0x%x, on bus %d\n", + __func__, ADV7535_MAIN, i2c_bus); + return; + } + + adv7535_i2c_reg_read(main_dev, 0x00, &val); + debug("Chip revision: 0x%x (expected: 0x14)\n", val); + adv7535_i2c_reg_read(cec_dev, 0x00, &val); + debug("Chip ID MSB: 0x%x (expected: 0x75)\n", val); + adv7535_i2c_reg_read(cec_dev, 0x01, &val); + debug("Chip ID LSB: 0x%x (expected: 0x33)\n", val); + + /* Power */ + adv7535_i2c_reg_write(main_dev, 0x41, 0xff, 0x10); + /* Initialisation (Fixed) Registers */ + adv7535_i2c_reg_write(main_dev, 0x16, 0xff, 0x20); + adv7535_i2c_reg_write(main_dev, 0x9A, 0xff, 0xE0); + adv7535_i2c_reg_write(main_dev, 0xBA, 0xff, 0x70); + adv7535_i2c_reg_write(main_dev, 0xDE, 0xff, 0x82); + adv7535_i2c_reg_write(main_dev, 0xE4, 0xff, 0x40); + adv7535_i2c_reg_write(main_dev, 0xE5, 0xff, 0x80); + adv7535_i2c_reg_write(cec_dev, 0x15, 0xff, 0xD0); + adv7535_i2c_reg_write(cec_dev, 0x17, 0xff, 0xD0); + adv7535_i2c_reg_write(cec_dev, 0x24, 0xff, 0x20); + adv7535_i2c_reg_write(cec_dev, 0x57, 0xff, 0x11); + /* 4 x DSI Lanes */ + adv7535_i2c_reg_write(cec_dev, 0x1C, 0xff, 0x40); + + /* DSI Pixel Clock Divider */ + adv7535_i2c_reg_write(cec_dev, 0x16, 0xff, 0x18); + + /* Enable Internal Timing Generator */ + adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB); + /* 1920 x 1080p 60Hz */ + adv7535_i2c_reg_write(cec_dev, 0x28, 0xff, 0x89); /* total width */ + adv7535_i2c_reg_write(cec_dev, 0x29, 0xff, 0x80); /* total width */ + adv7535_i2c_reg_write(cec_dev, 0x2A, 0xff, 0x02); /* hsync */ + adv7535_i2c_reg_write(cec_dev, 0x2B, 0xff, 0xC0); /* hsync */ + adv7535_i2c_reg_write(cec_dev, 0x2C, 0xff, 0x05); /* hfp */ + adv7535_i2c_reg_write(cec_dev, 0x2D, 0xff, 0x80); /* hfp */ + adv7535_i2c_reg_write(cec_dev, 0x2E, 0xff, 0x09); /* hbp */ + adv7535_i2c_reg_write(cec_dev, 0x2F, 0xff, 0x40); /* hbp */ + + adv7535_i2c_reg_write(cec_dev, 0x30, 0xff, 0x46); /* total height */ + adv7535_i2c_reg_write(cec_dev, 0x31, 0xff, 0x50); /* total height */ + adv7535_i2c_reg_write(cec_dev, 0x32, 0xff, 0x00); /* vsync */ + adv7535_i2c_reg_write(cec_dev, 0x33, 0xff, 0x50); /* vsync */ + adv7535_i2c_reg_write(cec_dev, 0x34, 0xff, 0x00); /* vfp */ + adv7535_i2c_reg_write(cec_dev, 0x35, 0xff, 0x40); /* vfp */ + adv7535_i2c_reg_write(cec_dev, 0x36, 0xff, 0x02); /* vbp */ + adv7535_i2c_reg_write(cec_dev, 0x37, 0xff, 0x40); /* vbp */ + + /* Reset Internal Timing Generator */ + adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB); + adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0x8B); + adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB); + + /* HDMI Output */ + adv7535_i2c_reg_write(main_dev, 0xAF, 0xff, 0x16); + /* AVI Infoframe - RGB - 16-9 Aspect Ratio */ + adv7535_i2c_reg_write(main_dev, 0x55, 0xff, 0x02); + adv7535_i2c_reg_write(main_dev, 0x56, 0xff, 0x0); + + /* GC Packet Enable */ + adv7535_i2c_reg_write(main_dev, 0x40, 0xff, 0x0); + /* GC Colour Depth - 24 Bit */ + adv7535_i2c_reg_write(main_dev, 0x4C, 0xff, 0x0); + /* Down Dither Output Colour Depth - 8 Bit (default) */ + adv7535_i2c_reg_write(main_dev, 0x49, 0xff, 0x00); + + /* set low refresh 1080p30 */ + adv7535_i2c_reg_write(main_dev, 0x4A, 0xff, 0x80); /*should be 0x80 for 1080p60 and 0x8c for 1080p30*/ + + /* HDMI Output Enable */ + adv7535_i2c_reg_write(cec_dev, 0xbe, 0xff, 0x3c); + adv7535_i2c_reg_write(cec_dev, 0x03, 0xff, 0x89); +} + +#define DISPLAY_MIX_SFT_RSTN_CSR 0x00 +#define DISPLAY_MIX_CLK_EN_CSR 0x04 + + /* 'DISP_MIX_SFT_RSTN_CSR' bit fields */ +#define BUS_RSTN_BLK_SYNC_SFT_EN BIT(6) + + /* 'DISP_MIX_CLK_EN_CSR' bit fields */ +#define LCDIF_PIXEL_CLK_SFT_EN BIT(7) +#define LCDIF_APB_CLK_SFT_EN BIT(6) + +void disp_mix_bus_rstn_reset(ulong gpr_base, bool reset) +{ + if (!reset) + /* release reset */ + setbits_le32(gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, BUS_RSTN_BLK_SYNC_SFT_EN); + else + /* hold reset */ + clrbits_le32(gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, BUS_RSTN_BLK_SYNC_SFT_EN); +} + +void disp_mix_lcdif_clks_enable(ulong gpr_base, bool enable) +{ + if (enable) + /* enable lcdif clks */ + setbits_le32(gpr_base + DISPLAY_MIX_CLK_EN_CSR, LCDIF_PIXEL_CLK_SFT_EN | LCDIF_APB_CLK_SFT_EN); + else + /* disable lcdif clks */ + clrbits_le32(gpr_base + DISPLAY_MIX_CLK_EN_CSR, LCDIF_PIXEL_CLK_SFT_EN | LCDIF_APB_CLK_SFT_EN); +} + +struct mipi_dsi_client_dev adv7535_dev = { + .channel = 0, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE, + .name = "ADV7535", +}; + +struct mipi_dsi_client_dev rm67191_dev = { + .channel = 0, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE, +}; + +#define FSL_SIP_GPC 0xC2000000 +#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x3 +#define DISPMIX 9 +#define MIPI 10 + +void do_enable_mipi2hdmi(struct display_info_t const *dev) +{ + gpio_request(IMX_GPIO_NR(1, 8), "DSI EN"); + gpio_direction_output(IMX_GPIO_NR(1, 8), 1); + + /* ADV7353 initialization */ + adv7535_init(); + + /* enable the dispmix & mipi phy power domain */ + call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0); + call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0); + + /* Put lcdif out of reset */ + disp_mix_bus_rstn_reset(imx8mm_mipi_dsim_plat_data.gpr_base, false); + disp_mix_lcdif_clks_enable(imx8mm_mipi_dsim_plat_data.gpr_base, true); + + /* Setup mipi dsim */ + sec_mipi_dsim_setup(&imx8mm_mipi_dsim_plat_data); + imx_mipi_dsi_bridge_attach(&adv7535_dev); /* attach adv7535 device */ +} + +void do_enable_mipi_led(struct display_info_t const *dev) +{ + gpio_request(IMX_GPIO_NR(1, 8), "DSI EN"); + gpio_direction_output(IMX_GPIO_NR(1, 8), 0); + mdelay(100); + gpio_direction_output(IMX_GPIO_NR(1, 8), 1); + + /* enable the dispmix & mipi phy power domain */ + call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0); + call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0); + + /* Put lcdif out of reset */ + disp_mix_bus_rstn_reset(imx8mm_mipi_dsim_plat_data.gpr_base, false); + disp_mix_lcdif_clks_enable(imx8mm_mipi_dsim_plat_data.gpr_base, true); + + /* Setup mipi dsim */ + sec_mipi_dsim_setup(&imx8mm_mipi_dsim_plat_data); + + rm67191_init(); + rm67191_dev.name = displays[1].mode.name; + imx_mipi_dsi_bridge_attach(&rm67191_dev); /* attach rm67191 device */ +} + +void board_quiesce_devices(void) +{ + gpio_request(IMX_GPIO_NR(1, 8), "DSI EN"); + gpio_direction_output(IMX_GPIO_NR(1, 8), 0); +} + +struct display_info_t const displays[] = {{ + .bus = LCDIF_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_mipi2hdmi, + .mode = { + .name = "MIPI2HDMI", + .refresh = 60, + .xres = 1920, + .yres = 1080, + .pixclock = 6734, /* 148500000 */ + .left_margin = 148, + .right_margin = 88, + .upper_margin = 36, + .lower_margin = 4, + .hsync_len = 44, + .vsync_len = 5, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + +} }, { + .bus = LCDIF_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_mipi_led, + .mode = { + .name = "RM67191_OLED", + .refresh = 60, + .xres = 1080, + .yres = 1920, + .pixclock = 7575, /* 132000000 */ + .left_margin = 34, + .right_margin = 20, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 2, + .vsync_len = 2, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c new file mode 100644 index 00000000000..fe8c540f9a8 --- /dev/null +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c @@ -0,0 +1,1855 @@ +/* + * Copyright 2018-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /* Initialize DDRC registers */ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + + /* performance setting */ + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + + /* P1: 400mts */ + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + + /* p2: 100mts */ + { 0x3d403020, 0x21 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + + /* default boot point */ + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x120024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x220024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x200c7, 0x21 }, + { 0x1200c7, 0x21 }, + { 0x2200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, + { 0x2200ca, 0x24 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c new file mode 100644 index 00000000000..10f00a50d20 --- /dev/null +++ b/board/freescale/imx8mm_evk/spl.c @@ -0,0 +1,255 @@ +/* + * Copyright 2018-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC, + .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC, + .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +/* + * The evk board uses DAT3 to detect CD card plugin, + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. + */ +static iomux_v3_cfg_t const usdhc2_cd_pad = + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); + +static iomux_v3_cfg_t const usdhc2_dat3_pad = + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | + MUX_PAD_CTRL(USDHC_PAD_CTRL); + + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 1}, + {USDHC3_BASE_ADDR, 0, 1}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 1: + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + imx_iomux_v3_setup_pad(usdhc2_cd_pad); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_direction_input(USDHC2_CD_GPIO); + + /* + * Since it is the DAT3 pin, this pin is pulled to + * low voltage if no card + */ + ret = gpio_get_value(USDHC2_CD_GPIO); + + imx_iomux_v3_setup_pad(usdhc2_dat3_pad); + return ret; + } + + return 1; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_bd71837_init(I2C_PMIC); + if (ret) + printf("power init failed"); + + p = pmic_get("BD71837"); + pmic_probe(p); + + + /* decrease RESET key long push time from the default 10s to 10ms */ + pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0); + + /* unlock the PMIC regs */ + pmic_reg_write(p, BD71837_REGLOCK, 0x1); + + /* increase VDD_SOC to typical value 0.85v before first DRAM access */ + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); + + /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ + pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83); + +#ifndef CONFIG_IMX8M_LPDDR4 + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28); +#endif + + /* lock the PMIC regs */ + pmic_reg_write(p, BD71837_REGLOCK, 0x11); + + return 0; +} +#endif + +void spl_board_init(void) +{ +#ifndef CONFIG_SPL_USB_SDP_SUPPORT + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } +#endif + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8mm_val/Kconfig b/board/freescale/imx8mm_val/Kconfig new file mode 100644 index 00000000000..2364cc431ad --- /dev/null +++ b/board/freescale/imx8mm_val/Kconfig @@ -0,0 +1,14 @@ + if TARGET_IMX8MM_DDR4_VAL || TARGET_IMX8MM_DDR3L_VAL + +config SYS_BOARD + default "imx8mm_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mm_val" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8mm_val/Makefile b/board/freescale/imx8mm_val/Makefile new file mode 100644 index 00000000000..4911989fcb5 --- /dev/null +++ b/board/freescale/imx8mm_val/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mm_val.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += ddr/ +endif diff --git a/board/freescale/imx8mm_val/ddr/Makefile b/board/freescale/imx8mm_val/ddr/Makefile new file mode 100644 index 00000000000..d0a9f5a5fa0 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += helper.o +obj-y += wait_ddrphy_training_complete.o +obj-$(CONFIG_TARGET_IMX8MM_DDR4_VAL) += ddr4/ +obj-$(CONFIG_TARGET_IMX8MM_DDR3L_VAL) += ddr3l/ +endif diff --git a/board/freescale/imx8mm_val/ddr/ddr.h b/board/freescale/imx8mm_val/ddr/ddr.h new file mode 100644 index 00000000000..b0e8ab5c7eb --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr.h @@ -0,0 +1,59 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * Common file for ddr code + */ + +#ifndef __M845S_DDR_H_ +#define __M845S_DDR_H_ + +#ifdef DDR_DEBUG +#define ddr_dbg(fmt, ...) printf("DDR: debug:" fmt "\n", ##__VA_ARGS__) +#else +#define ddr_dbg(fmt, ...) +#endif + +/******************************************************************* + Desc: user data type + + *******************************************************************/ +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; +/******************************************************************* + Desc: prototype + + *******************************************************************/ +void ddr_init(void); +void ddr_load_train_code(enum fw_type type); +void wait_ddrphy_training_complete(void); +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(unsigned int pstate); +void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void); +void dwc_ddrphy_phyinit_userCustom_customPostTrain(void); +void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(void); +void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void); +void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void); +void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned int run_2D); +void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void); + +/******************************************************************* + Desc: definition + + *******************************************************************/ +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline uint32_t reg32_read(unsigned long addr) +{ + return readl(addr); +} + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} +#endif diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/Makefile b/board/freescale/imx8mm_val/ddr/ddr3l/Makefile new file mode 100644 index 00000000000..dac4d506783 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr3l/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += ddr3_phyinit_task.o +obj-y += ddr3_phyinit_train_sw_ffc_fw09.o +obj-y += ddr3_sw_fast_freq_chg_fw09.o +obj-y += restore_1d2d_trained_csr_ddr3_p012.o +obj-y += save_1d2d_trained_csr_ddr3_p012.o +endif diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/anamix_common.h b/board/freescale/imx8mm_val/ddr/ddr3l/anamix_common.h new file mode 100644 index 00000000000..9f1ddd35538 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr3l/anamix_common.h @@ -0,0 +1,88 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ANAMIX_COMMON_TMP_H +#define ANAMIX_COMMON_TMP_H + +/*ANAMIX Address Definition*/ +#define ANAMIX_PLL_BASE_ADDR 0x30360000 +#define ANAMIX_OSC_BASE_ADDR 0x30270000 +#define ANAMIX_TSN_BASE_ADDR 0x30260000 + +/* PLL TOP REG */ +#define AUDIO_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x00) +#define AUDIO_PLL1_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x04) +#define AUDIO_PLL1_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x08) +#define AUDIO_PLL1_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x0c) +#define AUDIO_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x10) +#define AUDIO_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x14) +#define AUDIO_PLL2_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x18) +#define AUDIO_PLL2_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x1c) +#define AUDIO_PLL2_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x20) +#define AUDIO_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x24) +#define VIDEO_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x28) +#define VIDEO_PLL1_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x2c) +#define VIDEO_PLL1_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x30) +#define VIDEO_PLL1_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x34) +#define VIDEO_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x38) +#define VIDEO_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x3c) +#define VIDEO_PLL2_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x40) +#define VIDEO_PLL2_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x44) +#define VIDEO_PLL2_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x48) +#define VIDEO_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x4c) +#define DRAM_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x50) +#define DRAM_PLL_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x54) +#define DRAM_PLL_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x58) +#define DRAM_PLL_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x5c) +#define DRAM_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60) +#define GPU_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64) +#define GPU_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68) +#define GPU_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x6c) +#define GPU_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x70) +#define VPU_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x74) +#define VPU_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x78) +#define VPU_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x7c) +#define VPU_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x80) +#define ARM_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x84) +#define ARM_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x88) +#define ARM_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x8c) +#define ARM_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x90) +#define SYS_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x94) +#define SYS_PLL1_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x98) +#define SYS_PLL1_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x9c) +#define SYS_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x100) +#define SYS_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x104) +#define SYS_PLL2_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x108) +#define SYS_PLL2_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x10c) +#define SYS_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x110) +#define SYS_PLL3_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x114) +#define SYS_PLL3_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x118) +#define SYS_PLL3_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x11c) +#define SYS_PLL3_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x120) +#define ANAMIX_MISC_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x124) +#define ANAMIX_CLK_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x128) + +/* TMP SNSR REG */ +#define TER_ADDR (ANAMIX_TSN_BASE_ADDR + 0x00) +#define TSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x04) +#define TIER_ADDR (ANAMIX_TSN_BASE_ADDR + 0x08) +#define TIDR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x0c) +#define TMHTITR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x10) +#define TMHTATR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x14) +#define TMHTACTR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x18) +#define TSCR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x1c) +#define TRITSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x20) +#define TRATSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x24) +#define TASR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x28) +#define TTMC_ADDR (ANAMIX_TSN_BASE_ADDR + 0x2c) + +/* OSC */ +#define SYS_OSCNML_CTL0_ADDR (ANAMIX_OSC_BASE_ADDR + 0x00) +#define SYS_OSCNML_CTL1_ADDR (ANAMIX_OSC_BASE_ADDR + 0x04) +#define HDMI_OSCNML_CTL0_ADDR (ANAMIX_OSC_BASE_ADDR + 0x8000) +#define HDMI_OSCNML_CTL1_ADDR (ANAMIX_OSC_BASE_ADDR + 0x8004) + +#endif diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_define.h b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_define.h new file mode 100644 index 00000000000..6f26ef8039d --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_define.h @@ -0,0 +1,43 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef DDR3_DEFINE_H +#define DDR3_DEFINE_H + +#include "../ddr.h" + +#define RUN_ON_SILICON + +#ifdef DDR3_1600MTS_SWFFC_RET + #define DDR3_SW_FFC +#endif + +#define SAVE_DDRPHY_TRAIN_ADDR 0x180000 +#define DDR_CSD1_BASE_ADDR 0x40000000 +#define DDR_CSD2_BASE_ADDR 0x80000000 + +#define ANAMIX_PLL_BASE_ADDR 0x30360000 +#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60) +#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64) +#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68) +#define GPC_PU_PWRHSK 0x303A01FC +#define GPC_TOP_CONFIG_OFFSET 0x0000 +#define AIPS1_ARB_BASE_ADDR 0x30000000 +#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR +#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x200000) +#define CCM_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x180000) +#define CCM_SRC_CTRL_OFFSET (CCM_IPS_BASE_ADDR + 0x800) +#define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * n) + +#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data) +#define dwc_ddrphy_apb_rd(addr) (reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))) +#define reg32clrbit(addr, bitpos) reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1 << (bitpos))))) + +void restore_1d2d_trained_csr_ddr3_p012(unsigned int addr); +void save_1d2d_trained_csr_ddr3_p012(unsigned int addr); +void ddr3_phyinit_train_sw_ffc(unsigned int after_retention); + +#endif diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_task.c b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_task.c new file mode 100644 index 00000000000..fb1bfe41624 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_task.c @@ -0,0 +1,73 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "ddr3_define.h" + +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk (unsigned int pstate) { + if (pstate == 0) { + ddr_dbg("C: 1 ...\n"); + dram_pll_init(DRAM_PLL_OUT_400M); + } else if (pstate == 1) { + ddr_dbg("C: 2 ...\n"); + dram_pll_init(DRAM_PLL_OUT_266M); + } else if (pstate == 2) { + ddr_dbg("C: 3 ...\n"); + dram_pll_init(DRAM_PLL_OUT_167M); + } else { + printf("C: no freq match\n"); + } +} + +void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void) +{ + wait_ddrphy_training_complete(); +} +void dwc_ddrphy_phyinit_userCustom_overrideUserInput (void) {} +void dwc_ddrphy_phyinit_userCustom_A_bringupPower (void) {} +void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy (void) {} +void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned int Train2D) {} +void dwc_ddrphy_phyinit_userCustom_customPostTrain(void) {} +void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void) {} + +void ddr3_mr_write(unsigned int mr, unsigned int data, unsigned int read, unsigned int rank) +{ + unsigned int tmp, mr_mirror, data_mirror; + + /* 1. Poll MRSTAT.mr_wr_busy until it is 0. This checks that there is no outstanding MR transaction. No */ + /* writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1. */ + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + + /* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and (for MRWs) */ + /* MRCTRL1.mr_data to define the MR transaction. */ + /* (A3, A4), (A5, A6), (A7, A8), (BA0, BA1),*/ + tmp = reg32_read(DDRC_DIMMCTL(0)); + if ((tmp & 0x2) && (rank == 0x2)) { + mr_mirror = (mr & 0x4) | ((mr & 0x1) << 1) | ((mr & 0x2) >> 1);/* BA0, BA1 swap */ + data_mirror = (data & 0xfe07) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | ((data & 0x20) << 1) | ((data & 0x40) >> 1) | ((data & 0x80) << 1) | ((data & 0x100) >> 1); + } else { + mr_mirror = mr; + data_mirror = data; + } + + reg32_write(DDRC_MRCTRL0(0), read | (mr_mirror << 12) | (rank << 4)); + reg32_write(DDRC_MRCTRL1(0), data_mirror); + + /* 3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1. This bit is self-clearing, and triggers */ + /* the MR transaction. The uMCTL2 then asserts the MRSTAT.mr_wr_busy while it performs the MR */ + /* transaction to SDRAM, and no further accesses can be initiated until it is deasserted. */ + reg32setbit(DDRC_MRCTRL0(0), 31); + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp); + +} diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_train_sw_ffc_fw09.c b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_train_sw_ffc_fw09.c new file mode 100644 index 00000000000..c809c434b64 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_train_sw_ffc_fw09.c @@ -0,0 +1,1157 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "../ddr.h" +#include "ddr3_define.h" + +void ddr3_phyinit_train_sw_ffc(unsigned int after_retention) +{ + /* [dwc_ddrphy_phyinit_main] Start of dwc_ddrphy_phyinit_main() */ + /* [dwc_ddrphy_phyinit_sequence] Start of dwc_ddrphy_phyinit_sequence() */ + /* [dwc_ddrphy_phyinit_initStruct] Start of dwc_ddrphy_phyinit_initStruct() */ + /* [dwc_ddrphy_phyinit_initStruct] End of dwc_ddrphy_phyinit_initStruct() */ + /* [dwc_ddrphy_phyinit_setDefault] Start of dwc_ddrphy_phyinit_setDefault() */ + /* [dwc_ddrphy_phyinit_setDefault] End of dwc_ddrphy_phyinit_setDefault() */ + + + /* ############################################################## */ + /* */ + /* dwc_ddrphy_phyinit_userCustom_overrideUserInput is a user-editable function. */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + + dwc_ddrphy_phyinit_userCustom_overrideUserInput (); + /* */ + /* [dwc_ddrphy_phyinit_userCustom_overrideUserInput] End of dwc_ddrphy_phyinit_userCustom_overrideUserInput() */ + + + /* ############################################################## */ + /* */ + /* Step (A) : Bring up VDD, VDDQ, and VAA */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + + + dwc_ddrphy_phyinit_userCustom_A_bringupPower (); + + /* [dwc_ddrphy_phyinit_userCustom_A_bringupPower] End of dwc_ddrphy_phyinit_userCustom_A_bringupPower() */ + /* [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] Start of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* Step (B) Start Clocks and Reset the PHY */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy (); + + /* [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] End of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() */ + /* */ + + /* ############################################################## */ + /* */ + /* Step (C) Initialize PHY Configuration */ + /* */ + /* Load the required PHY configuration registers for the appropriate mode and memory configuration */ + /* */ + /* ############################################################## */ + /* */ + + /* [phyinit_C_initPhyConfig] Start of dwc_ddrphy_phyinit_C_initPhyConfig() */ + /* */ + /* ############################################################## */ + /* TxPreDrvMode[2] = 0 */ + /* ############################################################## */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxSlewRate::TxPreDrvMode to 0x3 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxSlewRate::TxPreP to 0xf */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxSlewRate::TxPreN to 0xc */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x1005f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1015f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1105f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1115f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1205f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1215f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1305f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1315f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxSlewRate::TxPreDrvMode to 0x3 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxSlewRate::TxPreP to 0xf */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxSlewRate::TxPreN to 0xc */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x11005f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 */ + dwc_ddrphy_apb_wr(0x11015f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 */ + dwc_ddrphy_apb_wr(0x11105f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 */ + dwc_ddrphy_apb_wr(0x11115f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 */ + dwc_ddrphy_apb_wr(0x11205f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 */ + dwc_ddrphy_apb_wr(0x11215f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 */ + dwc_ddrphy_apb_wr(0x11305f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 */ + dwc_ddrphy_apb_wr(0x11315f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxSlewRate::TxPreDrvMode to 0x3 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxSlewRate::TxPreP to 0xf */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxSlewRate::TxPreN to 0xc */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x21005f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 */ + dwc_ddrphy_apb_wr(0x21015f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 */ + dwc_ddrphy_apb_wr(0x21105f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 */ + dwc_ddrphy_apb_wr(0x21115f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 */ + dwc_ddrphy_apb_wr(0x21205f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 */ + dwc_ddrphy_apb_wr(0x21215f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 */ + dwc_ddrphy_apb_wr(0x21305f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 */ + dwc_ddrphy_apb_wr(0x21315f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=0 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=0 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=0 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x55, 0x365); /* DWC_DDRPHYA_ANIB0_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=1 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=1 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=1 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x1055, 0x365); /* DWC_DDRPHYA_ANIB1_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=2 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=2 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=2 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x2055, 0x365); /* DWC_DDRPHYA_ANIB2_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=3 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=3 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=3 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x3055, 0x365); /* DWC_DDRPHYA_ANIB3_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x0, ANIB=4 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=4 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=4 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x4055, 0x65); /* DWC_DDRPHYA_ANIB4_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x0, ANIB=5 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=5 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=5 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x5055, 0x65); /* DWC_DDRPHYA_ANIB5_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=6 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=6 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=6 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x6055, 0x365); /* DWC_DDRPHYA_ANIB6_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=7 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=7 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=7 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x7055, 0x365); /* DWC_DDRPHYA_ANIB7_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=8 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=8 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=8 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x8055, 0x365); /* DWC_DDRPHYA_ANIB8_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=9 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=9 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=9 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x9055, 0x365); /* DWC_DDRPHYA_ANIB9_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x200c5, 0xb); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming PllCtrl2 to b based on DfiClk frequency = 400. */ + dwc_ddrphy_apb_wr(0x1200c5, 0x7); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming PllCtrl2 to 7 based on DfiClk frequency = 133. */ + dwc_ddrphy_apb_wr(0x2200c5, 0x7); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming PllCtrl2 to 7 based on DfiClk frequency = 83. */ + /* */ + /* ############################################################## */ + /* */ + /* Program ARdPtrInitVal based on Frequency and PLL Bypass inputs */ + /* The values programmed here assume ideal properties of DfiClk */ + /* and Pclk including: */ + /* - DfiClk skew */ + /* - DfiClk jitter */ + /* - DfiClk PVT variations */ + /* - Pclk skew */ + /* - Pclk jitter */ + /* */ + /* PLL Bypassed mode: */ + /* For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 2-6 */ + /* For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6 */ + /* */ + /* PLL Enabled mode: */ + /* For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6 */ + /* For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-6 */ + /* */ + /* ############################################################## */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming ARdPtrInitVal to 0x1 */ + dwc_ddrphy_apb_wr(0x2002e, 0x1); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming ARdPtrInitVal to 0x1 */ + dwc_ddrphy_apb_wr(0x12002e, 0x1); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming ARdPtrInitVal to 0x1 */ + dwc_ddrphy_apb_wr(0x22002e, 0x1); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl to 0x8 */ + dwc_ddrphy_apb_wr(0x20024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DbyteDllModeCntrl to 0x0 */ + dwc_ddrphy_apb_wr(0x2003a, 0x0); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl to 0x8 */ + dwc_ddrphy_apb_wr(0x120024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DbyteDllModeCntrl to 0x0 */ + dwc_ddrphy_apb_wr(0x2003a, 0x0); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl to 0x8 */ + dwc_ddrphy_apb_wr(0x220024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DbyteDllModeCntrl to 0x0 */ + dwc_ddrphy_apb_wr(0x2003a, 0x0); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming ProcOdtTimeCtl to 0xa */ + dwc_ddrphy_apb_wr(0x20056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming ProcOdtTimeCtl to 0xa */ + dwc_ddrphy_apb_wr(0x120056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming ProcOdtTimeCtl to 0xa */ + dwc_ddrphy_apb_wr(0x220056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxOdtDrvStren::ODTStrenP to 0x18 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxOdtDrvStren::ODTStrenN to 0x18 */ + dwc_ddrphy_apb_wr(0x1004d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1014d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1104d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1114d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1204d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1214d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1304d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1314d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxOdtDrvStren::ODTStrenP to 0x18 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxOdtDrvStren::ODTStrenN to 0x18 */ + dwc_ddrphy_apb_wr(0x11004d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 */ + dwc_ddrphy_apb_wr(0x11014d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 */ + dwc_ddrphy_apb_wr(0x11104d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 */ + dwc_ddrphy_apb_wr(0x11114d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 */ + dwc_ddrphy_apb_wr(0x11204d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 */ + dwc_ddrphy_apb_wr(0x11214d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 */ + dwc_ddrphy_apb_wr(0x11304d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 */ + dwc_ddrphy_apb_wr(0x11314d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxOdtDrvStren::ODTStrenP to 0x18 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxOdtDrvStren::ODTStrenN to 0x18 */ + dwc_ddrphy_apb_wr(0x21004d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 */ + dwc_ddrphy_apb_wr(0x21014d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 */ + dwc_ddrphy_apb_wr(0x21104d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 */ + dwc_ddrphy_apb_wr(0x21114d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 */ + dwc_ddrphy_apb_wr(0x21204d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 */ + dwc_ddrphy_apb_wr(0x21214d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 */ + dwc_ddrphy_apb_wr(0x21304d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 */ + dwc_ddrphy_apb_wr(0x21314d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */ + dwc_ddrphy_apb_wr(0x10049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x10149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x11049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x11149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x12049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x12149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x13049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x13149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */ + dwc_ddrphy_apb_wr(0x110049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 */ + dwc_ddrphy_apb_wr(0x110149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 */ + dwc_ddrphy_apb_wr(0x111049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 */ + dwc_ddrphy_apb_wr(0x111149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 */ + dwc_ddrphy_apb_wr(0x112049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 */ + dwc_ddrphy_apb_wr(0x112149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 */ + dwc_ddrphy_apb_wr(0x113049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 */ + dwc_ddrphy_apb_wr(0x113149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */ + dwc_ddrphy_apb_wr(0x210049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 */ + dwc_ddrphy_apb_wr(0x210149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 */ + dwc_ddrphy_apb_wr(0x211049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 */ + dwc_ddrphy_apb_wr(0x211149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 */ + dwc_ddrphy_apb_wr(0x212049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 */ + dwc_ddrphy_apb_wr(0x212149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 */ + dwc_ddrphy_apb_wr(0x213049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 */ + dwc_ddrphy_apb_wr(0x213149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 */ + /* [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenP to 0x3 */ + /* [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenN to 0x3 */ + dwc_ddrphy_apb_wr(0x43, 0x63); /* DWC_DDRPHYA_ANIB0_ATxImpedance */ + dwc_ddrphy_apb_wr(0x1043, 0x63); /* DWC_DDRPHYA_ANIB1_ATxImpedance */ + dwc_ddrphy_apb_wr(0x2043, 0x63); /* DWC_DDRPHYA_ANIB2_ATxImpedance */ + dwc_ddrphy_apb_wr(0x3043, 0x63); /* DWC_DDRPHYA_ANIB3_ATxImpedance */ + dwc_ddrphy_apb_wr(0x4043, 0x63); /* DWC_DDRPHYA_ANIB4_ATxImpedance */ + dwc_ddrphy_apb_wr(0x5043, 0x63); /* DWC_DDRPHYA_ANIB5_ATxImpedance */ + dwc_ddrphy_apb_wr(0x6043, 0x63); /* DWC_DDRPHYA_ANIB6_ATxImpedance */ + dwc_ddrphy_apb_wr(0x7043, 0x63); /* DWC_DDRPHYA_ANIB7_ATxImpedance */ + dwc_ddrphy_apb_wr(0x8043, 0x63); /* DWC_DDRPHYA_ANIB8_ATxImpedance */ + dwc_ddrphy_apb_wr(0x9043, 0x63); /* DWC_DDRPHYA_ANIB9_ATxImpedance */ + /* [phyinit_C_initPhyConfig] Programming DfiMode to 0x5 */ + dwc_ddrphy_apb_wr(0x20018, 0x5); /* DWC_DDRPHYA_MASTER0_DfiMode */ + /* [phyinit_C_initPhyConfig] Programming DfiCAMode to 0x0 */ + dwc_ddrphy_apb_wr(0x20075, 0x0); /* DWC_DDRPHYA_MASTER0_DfiCAMode */ + /* [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPd50 to 0x0 */ + /* [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPu50 to 0x0 */ + dwc_ddrphy_apb_wr(0x20050, 0x0); /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x190 */ + dwc_ddrphy_apb_wr(0x20008, 0x190); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x85 */ + dwc_ddrphy_apb_wr(0x120008, 0x85); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x53 */ + dwc_ddrphy_apb_wr(0x220008, 0x53); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 */ + /* [phyinit_C_initPhyConfig] Programming CalRate::CalInterval to 0x9 */ + /* [phyinit_C_initPhyConfig] Programming CalRate::CalOnce to 0x0 */ + dwc_ddrphy_apb_wr(0x20088, 0x9); /* DWC_DDRPHYA_MASTER0_CalRate */ + /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f */ + /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0xf8 */ + dwc_ddrphy_apb_wr(0x200b2, 0xf8); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl to 0x581 */ + dwc_ddrphy_apb_wr(0x10043, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x10143, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x11043, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x11143, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x12043, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x12143, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x13043, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x13143, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f */ + /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal to 0xf8 */ + dwc_ddrphy_apb_wr(0x1200b2, 0xf8); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Programming DqDqsRcvCntrl to 0x581 */ + dwc_ddrphy_apb_wr(0x110043, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 */ + dwc_ddrphy_apb_wr(0x110143, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 */ + dwc_ddrphy_apb_wr(0x111043, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 */ + dwc_ddrphy_apb_wr(0x111143, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 */ + dwc_ddrphy_apb_wr(0x112043, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 */ + dwc_ddrphy_apb_wr(0x112143, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 */ + dwc_ddrphy_apb_wr(0x113043, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 */ + dwc_ddrphy_apb_wr(0x113143, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f */ + /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal to 0xf8 */ + dwc_ddrphy_apb_wr(0x2200b2, 0xf8); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Programming DqDqsRcvCntrl to 0x581 */ + dwc_ddrphy_apb_wr(0x210043, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 */ + dwc_ddrphy_apb_wr(0x210143, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 */ + dwc_ddrphy_apb_wr(0x211043, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 */ + dwc_ddrphy_apb_wr(0x211143, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 */ + dwc_ddrphy_apb_wr(0x212043, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 */ + dwc_ddrphy_apb_wr(0x212143, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 */ + dwc_ddrphy_apb_wr(0x213043, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 */ + dwc_ddrphy_apb_wr(0x213143, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DfiFreqRatio_p0 to 0x1 */ + dwc_ddrphy_apb_wr(0x200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DfiFreqRatio_p1 to 0x1 */ + dwc_ddrphy_apb_wr(0x1200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DfiFreqRatio_p2 to 0x1 */ + dwc_ddrphy_apb_wr(0x2200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TristateModeCA::DisDynAdrTri_p0 to 0x1 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TristateModeCA::DDR2TMode_p0 to 0x0 */ + dwc_ddrphy_apb_wr(0x20019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TristateModeCA::DisDynAdrTri_p1 to 0x1 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TristateModeCA::DDR2TMode_p1 to 0x0 */ + dwc_ddrphy_apb_wr(0x120019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TristateModeCA::DisDynAdrTri_p2 to 0x1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TristateModeCA::DDR2TMode_p2 to 0x0 */ + dwc_ddrphy_apb_wr(0x220019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p2 */ + /* [phyinit_C_initPhyConfig] Programming DfiFreqXlat* */ + dwc_ddrphy_apb_wr(0x200f0, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */ + dwc_ddrphy_apb_wr(0x200f1, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */ + dwc_ddrphy_apb_wr(0x200f2, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */ + dwc_ddrphy_apb_wr(0x200f3, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */ + dwc_ddrphy_apb_wr(0x200f4, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */ + dwc_ddrphy_apb_wr(0x200f5, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */ + dwc_ddrphy_apb_wr(0x200f6, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */ + dwc_ddrphy_apb_wr(0x200f7, 0xf000); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */ + /* [phyinit_C_initPhyConfig] Programming MasterX4Config::X4TG to 0x0 */ + dwc_ddrphy_apb_wr(0x20025, 0x0); /* DWC_DDRPHYA_MASTER0_MasterX4Config */ + /* [phyinit_C_initPhyConfig] End of dwc_ddrphy_phyinit_C_initPhyConfig() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* dwc_ddrphy_phyihunit_userCustom_customPreTrain is a user-editable function. */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* [phyinit_userCustom_customPreTrain] Start of dwc_ddrphy_phyinit_userCustom_customPreTrain() */ + /* [phyinit_userCustom_customPreTrain] End of dwc_ddrphy_phyinit_userCustom_customPreTrain() */ + /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=0) */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (D) Load the 1D IMEM image */ + /* */ + /* This function loads the training firmware IMEM image into the SRAM. */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Programming MemResetL to 0x2 */ + if (!after_retention) { + dwc_ddrphy_apb_wr(0x20060, 0x2); + + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr3/ddr3_pmu_train_imem.incv */ + + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x50000 size 0x4000 */ + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x4000 */ + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + /* This allows the firmware unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] End of dwc_ddrphy_phyinit_D_loadIMEM() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* Step (E) Set the PHY input clocks to the desired frequency for pstate 0 */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0); + + /* */ + /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */ + /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=0) */ + + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* for test on silicon, load 1D dmem/imem here */ + #ifdef CONFIG_SPL_VSI_FW_LOADING + load_train_1d_code(); + #else + ddr_load_train_code(FW_1D_IMAGE); + #endif + ddr_dbg("start 1d train\n"); + + + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr3/ddr3_pmu_train_dmem.incv */ + + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */ + #ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x54000, 0x0); + #else + dwc_ddrphy_apb_wr(0x54000, 0x600); + #endif + dwc_ddrphy_apb_wr(0x54001, 0x0); + dwc_ddrphy_apb_wr(0x54002, 0x0); + dwc_ddrphy_apb_wr(0x54003, 0x640); + dwc_ddrphy_apb_wr(0x54004, 0x2); + dwc_ddrphy_apb_wr(0x54005, 0x0); + dwc_ddrphy_apb_wr(0x54006, 0x140); + dwc_ddrphy_apb_wr(0x54007, 0x2000); + #ifdef DDR_ONE_RANK + dwc_ddrphy_apb_wr(0x54008, 0x101); + dwc_ddrphy_apb_wr(0x54009, 0x0); + #else + dwc_ddrphy_apb_wr(0x54008, 0x303); + dwc_ddrphy_apb_wr(0x54009, 0x200); + #endif + dwc_ddrphy_apb_wr(0x5400a, 0x0); + #ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x5400b, 0x31f); + #else + dwc_ddrphy_apb_wr(0x5400b, 0x1); + #endif + dwc_ddrphy_apb_wr(0x5400c, 0xc8); + dwc_ddrphy_apb_wr(0x5400d, 0x0); + dwc_ddrphy_apb_wr(0x5400e, 0x0); + dwc_ddrphy_apb_wr(0x5400f, 0x0); + dwc_ddrphy_apb_wr(0x54010, 0x0); + dwc_ddrphy_apb_wr(0x54011, 0x0); + dwc_ddrphy_apb_wr(0x54012, 0x1); + dwc_ddrphy_apb_wr(0x5402f, 0xd70); + dwc_ddrphy_apb_wr(0x54030, 0x4); + dwc_ddrphy_apb_wr(0x54031, 0x18); + dwc_ddrphy_apb_wr(0x5403a, 0x1221); + dwc_ddrphy_apb_wr(0x5403b, 0x4884); + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */ + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + /* This allows the firmware unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (G) Execute the Training Firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */ + /* ResetToMicro fields to 1 (all other fields should be zero). */ + /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */ + dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */ + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */ + dwc_ddrphy_phyinit_userCustom_G_waitFwDone (); + + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */ + /* 4. Halt the microcontroller." */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (H) Read the Message Block results */ + /* */ + /* The procedure is as follows: */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* */ + /* 2. Read the Firmware Message Block to obtain the results from the training. */ + /* This can be accomplished by issuing APB read commands to the DMEM addresses. */ + /* Example: */ + /* if (Train2D) */ + /* { */ + /* _read_2d_message_block_outputs_ */ + /* } */ + /* else */ + /* { */ + /* _read_1d_message_block_outputs_ */ + /* } */ + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0); + + /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */ + /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* 4. If training is required at another frequency, repeat the operations starting at step (E). */ + /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* Step (E) Set the PHY input clocks to the desired frequency for pstate 1 */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + #ifdef DDR3_SW_FFC + dwc_ddrphy_phyinit_userCustom_E_setDfiClk (1); + + /* */ + /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */ + /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=1, Train2D=0) */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr3/ddr3_pmu_train_dmem.incv */ + + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */ + #ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x54000, 0x0); + #else + dwc_ddrphy_apb_wr(0x54000, 0x600); + #endif + dwc_ddrphy_apb_wr(0x54001, 0x0); + dwc_ddrphy_apb_wr(0x54002, 0x1); + dwc_ddrphy_apb_wr(0x54003, 0x214); + dwc_ddrphy_apb_wr(0x54004, 0x2); + dwc_ddrphy_apb_wr(0x54005, 0x0); + dwc_ddrphy_apb_wr(0x54006, 0x140); + dwc_ddrphy_apb_wr(0x54007, 0x2000); + #ifdef DDR_ONE_RANK + dwc_ddrphy_apb_wr(0x54008, 0x101); + dwc_ddrphy_apb_wr(0x54009, 0x0); + #else + dwc_ddrphy_apb_wr(0x54008, 0x303); + dwc_ddrphy_apb_wr(0x54009, 0x200); + #endif + dwc_ddrphy_apb_wr(0x5400a, 0x0); + #ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x5400b, 0x21f); + #else + dwc_ddrphy_apb_wr(0x5400b, 0x1); + #endif + dwc_ddrphy_apb_wr(0x5400c, 0xc8); + dwc_ddrphy_apb_wr(0x5400d, 0x0); + dwc_ddrphy_apb_wr(0x5400e, 0x0); + dwc_ddrphy_apb_wr(0x5400f, 0x0); + dwc_ddrphy_apb_wr(0x54010, 0x0); + dwc_ddrphy_apb_wr(0x54011, 0x0); + dwc_ddrphy_apb_wr(0x54012, 0x1); + dwc_ddrphy_apb_wr(0x5402f, 0x930); + dwc_ddrphy_apb_wr(0x54030, 0x4); + dwc_ddrphy_apb_wr(0x54031, 0x8); + dwc_ddrphy_apb_wr(0x5403a, 0x1221); + dwc_ddrphy_apb_wr(0x5403b, 0x4884); + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */ + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + /* This allows the firmware unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (G) Execute the Training Firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */ + /* ResetToMicro fields to 1 (all other fields should be zero). */ + /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */ + dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */ + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */ + dwc_ddrphy_phyinit_userCustom_G_waitFwDone (); + + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */ + /* 4. Halt the microcontroller." */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (H) Read the Message Block results */ + /* */ + /* The procedure is as follows: */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* */ + /* 2. Read the Firmware Message Block to obtain the results from the training. */ + /* This can be accomplished by issuing APB read commands to the DMEM addresses. */ + /* Example: */ + /* if (Train2D) */ + /* { */ + /* _read_2d_message_block_outputs_ */ + /* } */ + /* else */ + /* { */ + /* _read_1d_message_block_outputs_ */ + /* } */ + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0); + + /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */ + /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* 4. If training is required at another frequency, repeat the operations starting at step (E). */ + /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* Step (E) Set the PHY input clocks to the desired frequency for pstate 2 */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + dwc_ddrphy_phyinit_userCustom_E_setDfiClk (2); + + /* */ + /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */ + /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=2, Train2D=0) */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr3/ddr3_pmu_train_dmem.incv */ + + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */ + #ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x54000, 0x0); + #else + dwc_ddrphy_apb_wr(0x54000, 0x600); + #endif + dwc_ddrphy_apb_wr(0x54001, 0x0); + dwc_ddrphy_apb_wr(0x54002, 0x2); + dwc_ddrphy_apb_wr(0x54003, 0x14c); + dwc_ddrphy_apb_wr(0x54004, 0x2); + dwc_ddrphy_apb_wr(0x54005, 0x0); + dwc_ddrphy_apb_wr(0x54006, 0x140); + dwc_ddrphy_apb_wr(0x54007, 0x2000); + #ifdef DDR_ONE_RANK + dwc_ddrphy_apb_wr(0x54008, 0x101); + dwc_ddrphy_apb_wr(0x54009, 0x0); + #else + dwc_ddrphy_apb_wr(0x54008, 0x303); + dwc_ddrphy_apb_wr(0x54009, 0x200); + #endif + dwc_ddrphy_apb_wr(0x5400a, 0x0); + #ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x5400b, 0x21f); + #else + dwc_ddrphy_apb_wr(0x5400b, 0x1); + #endif + dwc_ddrphy_apb_wr(0x5400c, 0xc8); + dwc_ddrphy_apb_wr(0x5400d, 0x0); + dwc_ddrphy_apb_wr(0x5400e, 0x0); + dwc_ddrphy_apb_wr(0x5400f, 0x0); + dwc_ddrphy_apb_wr(0x54010, 0x0); + dwc_ddrphy_apb_wr(0x54011, 0x0); + dwc_ddrphy_apb_wr(0x54012, 0x1); + dwc_ddrphy_apb_wr(0x5402f, 0x520); + dwc_ddrphy_apb_wr(0x54030, 0x4); + dwc_ddrphy_apb_wr(0x54031, 0x0); + dwc_ddrphy_apb_wr(0x5403a, 0x1221); + dwc_ddrphy_apb_wr(0x5403b, 0x4884); + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */ + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + /* This allows the firmware unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (G) Execute the Training Firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */ + /* ResetToMicro fields to 1 (all other fields should be zero). */ + /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */ + dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */ + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */ + dwc_ddrphy_phyinit_userCustom_G_waitFwDone (); + + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */ + /* 4. Halt the microcontroller." */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (H) Read the Message Block results */ + /* */ + /* The procedure is as follows: */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* */ + /* 2. Read the Firmware Message Block to obtain the results from the training. */ + /* This can be accomplished by issuing APB read commands to the DMEM addresses. */ + /* Example: */ + /* if (Train2D) */ + /* { */ + /* _read_2d_message_block_outputs_ */ + /* } */ + /* else */ + /* { */ + /* _read_1d_message_block_outputs_ */ + /* } */ + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0); + + /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */ + /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* 4. If training is required at another frequency, repeat the operations starting at step (E). */ + /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */ + /* [phyinit_I_loadPIEImage] Start of dwc_ddrphy_phyinit_I_loadPIEImage() */ + #endif /* DDR3_SW_FFC */ + ddr_dbg("1D training done!!!!\n"); + } /* !after_retention */else {/* after_retention */ + /* restore_1d2d_trained_csr_ddr3_p0(SAVE_DDRPHY_TRAIN_ADDR); */ + restore_1d2d_trained_csr_ddr3_p012(SAVE_DDRPHY_TRAIN_ADDR); + } /* after_retention */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (I) Load PHY Init Engine Image */ + /* */ + /* Load the PHY Initialization Engine memory with the provided initialization sequence. */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [phyinit_I_loadPIEImage] Programming PIE Production Code */ + dwc_ddrphy_apb_wr(0x90000, 0x10); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90001, 0x400); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90002, 0x10e); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90003, 0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x90004, 0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x90005, 0x8); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x90029, 0xb); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x9002a, 0x480); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x9002b, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x9002c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9002d, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9002e, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x9002f, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */ + dwc_ddrphy_apb_wr(0x90030, 0x478); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */ + dwc_ddrphy_apb_wr(0x90031, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */ + dwc_ddrphy_apb_wr(0x90032, 0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */ + dwc_ddrphy_apb_wr(0x90033, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */ + dwc_ddrphy_apb_wr(0x90034, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */ + dwc_ddrphy_apb_wr(0x90035, 0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */ + dwc_ddrphy_apb_wr(0x90036, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */ + dwc_ddrphy_apb_wr(0x90037, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */ + dwc_ddrphy_apb_wr(0x90038, 0x44); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */ + dwc_ddrphy_apb_wr(0x90039, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */ + dwc_ddrphy_apb_wr(0x9003a, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */ + dwc_ddrphy_apb_wr(0x9003b, 0x14f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */ + dwc_ddrphy_apb_wr(0x9003c, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */ + dwc_ddrphy_apb_wr(0x9003d, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */ + dwc_ddrphy_apb_wr(0x9003e, 0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */ + dwc_ddrphy_apb_wr(0x9003f, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */ + dwc_ddrphy_apb_wr(0x90040, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */ + dwc_ddrphy_apb_wr(0x90041, 0x4f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */ + dwc_ddrphy_apb_wr(0x90042, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */ + dwc_ddrphy_apb_wr(0x90043, 0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */ + dwc_ddrphy_apb_wr(0x90044, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */ + dwc_ddrphy_apb_wr(0x90045, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */ + dwc_ddrphy_apb_wr(0x90046, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */ + dwc_ddrphy_apb_wr(0x90047, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */ + dwc_ddrphy_apb_wr(0x90048, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */ + dwc_ddrphy_apb_wr(0x90049, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */ + dwc_ddrphy_apb_wr(0x9004a, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */ + dwc_ddrphy_apb_wr(0x9004b, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */ + dwc_ddrphy_apb_wr(0x9004c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */ + dwc_ddrphy_apb_wr(0x9004d, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */ + dwc_ddrphy_apb_wr(0x9004e, 0x45a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */ + dwc_ddrphy_apb_wr(0x9004f, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */ + dwc_ddrphy_apb_wr(0x90050, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */ + dwc_ddrphy_apb_wr(0x90051, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */ + dwc_ddrphy_apb_wr(0x90052, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */ + dwc_ddrphy_apb_wr(0x90053, 0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */ + dwc_ddrphy_apb_wr(0x90054, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */ + dwc_ddrphy_apb_wr(0x90055, 0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */ + dwc_ddrphy_apb_wr(0x90056, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */ + dwc_ddrphy_apb_wr(0x90057, 0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */ + dwc_ddrphy_apb_wr(0x90058, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */ + dwc_ddrphy_apb_wr(0x90059, 0x40c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */ + dwc_ddrphy_apb_wr(0x9005a, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */ + dwc_ddrphy_apb_wr(0x9005b, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */ + dwc_ddrphy_apb_wr(0x9005c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */ + dwc_ddrphy_apb_wr(0x9005d, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */ + dwc_ddrphy_apb_wr(0x9005e, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */ + dwc_ddrphy_apb_wr(0x9005f, 0x4040); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */ + dwc_ddrphy_apb_wr(0x90060, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */ + dwc_ddrphy_apb_wr(0x90061, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */ + dwc_ddrphy_apb_wr(0x90062, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */ + dwc_ddrphy_apb_wr(0x90063, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */ + dwc_ddrphy_apb_wr(0x90064, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */ + dwc_ddrphy_apb_wr(0x90065, 0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */ + dwc_ddrphy_apb_wr(0x90066, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */ + dwc_ddrphy_apb_wr(0x90067, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */ + dwc_ddrphy_apb_wr(0x90068, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */ + dwc_ddrphy_apb_wr(0x90069, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */ + dwc_ddrphy_apb_wr(0x9006a, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */ + dwc_ddrphy_apb_wr(0x9006b, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */ + dwc_ddrphy_apb_wr(0x9006c, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */ + dwc_ddrphy_apb_wr(0x9006d, 0x78); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */ + dwc_ddrphy_apb_wr(0x9006e, 0x549); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */ + dwc_ddrphy_apb_wr(0x9006f, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */ + dwc_ddrphy_apb_wr(0x90070, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */ + dwc_ddrphy_apb_wr(0x90071, 0xd49); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */ + dwc_ddrphy_apb_wr(0x90072, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */ + dwc_ddrphy_apb_wr(0x90073, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */ + dwc_ddrphy_apb_wr(0x90074, 0x94a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */ + dwc_ddrphy_apb_wr(0x90075, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */ + dwc_ddrphy_apb_wr(0x90076, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */ + dwc_ddrphy_apb_wr(0x90077, 0x441); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */ + dwc_ddrphy_apb_wr(0x90078, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */ + dwc_ddrphy_apb_wr(0x90079, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */ + dwc_ddrphy_apb_wr(0x9007a, 0x42); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */ + dwc_ddrphy_apb_wr(0x9007b, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */ + dwc_ddrphy_apb_wr(0x9007c, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */ + dwc_ddrphy_apb_wr(0x9007d, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */ + dwc_ddrphy_apb_wr(0x9007e, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */ + dwc_ddrphy_apb_wr(0x9007f, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */ + dwc_ddrphy_apb_wr(0x90080, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */ + dwc_ddrphy_apb_wr(0x90081, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */ + dwc_ddrphy_apb_wr(0x90082, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */ + dwc_ddrphy_apb_wr(0x90083, 0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */ + dwc_ddrphy_apb_wr(0x90084, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */ + dwc_ddrphy_apb_wr(0x90085, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */ + dwc_ddrphy_apb_wr(0x90086, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */ + dwc_ddrphy_apb_wr(0x90087, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */ + dwc_ddrphy_apb_wr(0x90088, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */ + dwc_ddrphy_apb_wr(0x90089, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */ + dwc_ddrphy_apb_wr(0x9008a, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */ + dwc_ddrphy_apb_wr(0x9008b, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */ + dwc_ddrphy_apb_wr(0x9008c, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */ + dwc_ddrphy_apb_wr(0x9008d, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */ + dwc_ddrphy_apb_wr(0x9008e, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */ + dwc_ddrphy_apb_wr(0x9008f, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */ + dwc_ddrphy_apb_wr(0x90090, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */ + dwc_ddrphy_apb_wr(0x90091, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */ + dwc_ddrphy_apb_wr(0x90092, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */ + dwc_ddrphy_apb_wr(0x90093, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */ + dwc_ddrphy_apb_wr(0x90094, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */ + dwc_ddrphy_apb_wr(0x90095, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */ + dwc_ddrphy_apb_wr(0x90096, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */ + dwc_ddrphy_apb_wr(0x90097, 0x58); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */ + dwc_ddrphy_apb_wr(0x90098, 0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */ + dwc_ddrphy_apb_wr(0x90099, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */ + dwc_ddrphy_apb_wr(0x9009a, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */ + dwc_ddrphy_apb_wr(0x9009b, 0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */ + dwc_ddrphy_apb_wr(0x9009c, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */ + dwc_ddrphy_apb_wr(0x9009d, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */ + dwc_ddrphy_apb_wr(0x9009e, 0x7); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */ + dwc_ddrphy_apb_wr(0x9009f, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */ + dwc_ddrphy_apb_wr(0x900a0, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */ + dwc_ddrphy_apb_wr(0x900a1, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */ + dwc_ddrphy_apb_wr(0x900a2, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */ + dwc_ddrphy_apb_wr(0x900a3, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */ + dwc_ddrphy_apb_wr(0x900a4, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */ + dwc_ddrphy_apb_wr(0x900a5, 0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */ + dwc_ddrphy_apb_wr(0x900a6, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */ + dwc_ddrphy_apb_wr(0x900a7, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */ + dwc_ddrphy_apb_wr(0x900a8, 0x8138); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */ + dwc_ddrphy_apb_wr(0x900a9, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */ + dwc_ddrphy_apb_wr(0x900aa, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */ + dwc_ddrphy_apb_wr(0x900ab, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */ + dwc_ddrphy_apb_wr(0x900ac, 0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */ + dwc_ddrphy_apb_wr(0x900ad, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */ + dwc_ddrphy_apb_wr(0x900ae, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */ + dwc_ddrphy_apb_wr(0x900af, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */ + dwc_ddrphy_apb_wr(0x900b0, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */ + dwc_ddrphy_apb_wr(0x900b1, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */ + dwc_ddrphy_apb_wr(0x900b2, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */ + dwc_ddrphy_apb_wr(0x900b3, 0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */ + dwc_ddrphy_apb_wr(0x900b4, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */ + dwc_ddrphy_apb_wr(0x900b5, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */ + dwc_ddrphy_apb_wr(0x900b6, 0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */ + dwc_ddrphy_apb_wr(0x900b7, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */ + dwc_ddrphy_apb_wr(0x900b8, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */ + dwc_ddrphy_apb_wr(0x900b9, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */ + dwc_ddrphy_apb_wr(0x900ba, 0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */ + dwc_ddrphy_apb_wr(0x900bb, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */ + dwc_ddrphy_apb_wr(0x900bc, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */ + dwc_ddrphy_apb_wr(0x900bd, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */ + dwc_ddrphy_apb_wr(0x900be, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */ + dwc_ddrphy_apb_wr(0x900bf, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */ + dwc_ddrphy_apb_wr(0x900c0, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */ + dwc_ddrphy_apb_wr(0x900c1, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */ + dwc_ddrphy_apb_wr(0x900c2, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */ + dwc_ddrphy_apb_wr(0x900c3, 0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */ + dwc_ddrphy_apb_wr(0x900c4, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */ + dwc_ddrphy_apb_wr(0x900c5, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */ + dwc_ddrphy_apb_wr(0x900c6, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */ + dwc_ddrphy_apb_wr(0x900c7, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */ + dwc_ddrphy_apb_wr(0x900c8, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */ + dwc_ddrphy_apb_wr(0x900c9, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */ + dwc_ddrphy_apb_wr(0x900ca, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */ + dwc_ddrphy_apb_wr(0x900cb, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */ + dwc_ddrphy_apb_wr(0x900cc, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */ + dwc_ddrphy_apb_wr(0x900cd, 0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */ + dwc_ddrphy_apb_wr(0x90006, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90007, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90008, 0x8); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90009, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9000a, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9000b, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0xd00e7, 0x400); /* DWC_DDRPHYA_APBONLY0_SequencerOverride */ + dwc_ddrphy_apb_wr(0x90017, 0x0); /* DWC_DDRPHYA_INITENG0_StartVector0b0 */ + dwc_ddrphy_apb_wr(0x90026, 0x2c); /* DWC_DDRPHYA_INITENG0_StartVector0b15 */ + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=800MHz, Programming Seq0BDLY0 to 0x32 */ + dwc_ddrphy_apb_wr(0x2000b, 0x32); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */ + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=800MHz, Programming Seq0BDLY1 to 0x64 */ + dwc_ddrphy_apb_wr(0x2000c, 0x64); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */ + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=800MHz, Programming Seq0BDLY2 to 0x3e8 */ + dwc_ddrphy_apb_wr(0x2000d, 0x3e8); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */ + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=800MHz, Programming Seq0BDLY3 to 0x2c */ + dwc_ddrphy_apb_wr(0x2000e, 0x2c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */ + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=266MHz, Programming Seq0BDLY0 to 0x10 */ + dwc_ddrphy_apb_wr(0x12000b, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */ + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=266MHz, Programming Seq0BDLY1 to 0x21 */ + dwc_ddrphy_apb_wr(0x12000c, 0x21); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */ + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=266MHz, Programming Seq0BDLY2 to 0x14c */ + dwc_ddrphy_apb_wr(0x12000d, 0x14c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */ + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=266MHz, Programming Seq0BDLY3 to 0x10 */ + dwc_ddrphy_apb_wr(0x12000e, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */ + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=166MHz, Programming Seq0BDLY0 to 0xa */ + dwc_ddrphy_apb_wr(0x22000b, 0xa); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */ + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=166MHz, Programming Seq0BDLY1 to 0x14 */ + dwc_ddrphy_apb_wr(0x22000c, 0x14); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */ + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=166MHz, Programming Seq0BDLY2 to 0xcf */ + dwc_ddrphy_apb_wr(0x22000d, 0xcf); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */ + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=166MHz, Programming Seq0BDLY3 to 0x10 */ + dwc_ddrphy_apb_wr(0x22000e, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */ + dwc_ddrphy_apb_wr(0x9000c, 0x0); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */ + dwc_ddrphy_apb_wr(0x9000d, 0x173); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */ + dwc_ddrphy_apb_wr(0x9000e, 0x60); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */ + dwc_ddrphy_apb_wr(0x9000f, 0x6110); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */ + dwc_ddrphy_apb_wr(0x90010, 0x2152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */ + dwc_ddrphy_apb_wr(0x90011, 0xdfbd); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */ + dwc_ddrphy_apb_wr(0x90012, 0xffff); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */ + dwc_ddrphy_apb_wr(0x90013, 0x6152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */ + /* Disabling Ucclk (PMU) and Hclk (training hardware) */ + dwc_ddrphy_apb_wr(0xc0080, 0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + /* Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [phyinit_I_loadPIEImage] End of dwc_ddrphy_phyinit_I_loadPIEImage() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* dwc_ddrphy_phyinit_userCustom_customPostTrain is a user-editable function. */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + dwc_ddrphy_phyinit_userCustom_customPostTrain (); + + /* [dwc_ddrphy_phyinit_userCustom_customPostTrain] End of dwc_ddrphy_phyinit_userCustom_customPostTrain() */ + /* [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] Start of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (J) Initialize the PHY to Mission Mode through DFI Initialization */ + /* */ + /* Initialize the PHY to mission mode as follows: */ + /* */ + /* 1. Set the PHY input clocks to the desired frequency. */ + /* 2. Initialize the PHY to mission mode by performing DFI Initialization. */ + /* Please see the DFI specification for more information. See the DFI frequency bus encoding in section . */ + /* Note: The PHY training firmware initializes the DRAM state. if skip */ + /* training is used, the DRAM state is not initialized. */ + /* */ + /* ############################################################## */ + /* */ + dwc_ddrphy_phyinit_userCustom_J_enterMissionMode (); + + /* */ + /* [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] End of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() */ + /* [dwc_ddrphy_phyinit_sequence] End of dwc_ddrphy_phyinit_sequence() */ + /* [dwc_ddrphy_phyinit_main] End of dwc_ddrphy_phyinit_main() */ + + /* ---------------------------------------------------------------------- */ + /* save 1d2d training CSR */ + /* ---------------------------------------------------------------------- */ + if (!after_retention) { + save_1d2d_trained_csr_ddr3_p012(SAVE_DDRPHY_TRAIN_ADDR); + } +} diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_sw_fast_freq_chg_fw09.c b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_sw_fast_freq_chg_fw09.c new file mode 100644 index 00000000000..e3875f5a366 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_sw_fast_freq_chg_fw09.c @@ -0,0 +1,277 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "anamix_common.h" +#include "ddr3_define.h" + +void umctl2_cfg(void) +{ +#ifdef DDR_ONE_RANK + reg32_write(DDRC_MSTR(0), 0x81040001); +#else + reg32_write(DDRC_MSTR(0), 0x83040001); +#endif + + reg32_write(DDRC_PWRCTL(0), 0x000000a8); + reg32_write(DDRC_PWRTMG(0), 0x00532203); + + reg32_write(DDRC_RFSHCTL0(0), 0x00203020); + reg32_write(DDRC_RFSHCTL1(0), 0x0001000d); + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + reg32_write(DDRC_RFSHTMG(0), 0x0061008c); + reg32_write(DDRC_CRCPARCTL0(0), 0x00000000); + reg32_write(DDRC_CRCPARCTL1(0), 0x00000000); + reg32_write(DDRC_INIT0(0), 0xc0030002); + reg32_write(DDRC_INIT1(0), 0x0001000b); + reg32_write(DDRC_INIT2(0), 0x00006303); + reg32_write(DDRC_INIT3(0), 0x0d700004);/* MR1, MR0 */ + reg32_write(DDRC_INIT4(0), 0x00180000);/* MR2 */ + reg32_write(DDRC_INIT5(0), 0x00090071); + reg32_write(DDRC_INIT6(0), 0x00000000); + reg32_write(DDRC_INIT7(0), 0x00000000); + reg32_write(DDRC_DIMMCTL(0), 0x00000032); /* [1] dimm_addr_mirr_en, it will effect the MRS if use umctl2 to initi dram. */ + reg32_write(DDRC_RANKCTL(0), 0x00000ee5); + reg32_write(DDRC_DRAMTMG0(0), 0x0c101a0e); + reg32_write(DDRC_DRAMTMG1(0), 0x000a0314); + reg32_write(DDRC_DRAMTMG2(0), 0x04060509); + reg32_write(DDRC_DRAMTMG3(0), 0x00002006); + reg32_write(DDRC_DRAMTMG4(0), 0x06020306); + reg32_write(DDRC_DRAMTMG5(0), 0x0b060202); + reg32_write(DDRC_DRAMTMG6(0), 0x060a0009); + reg32_write(DDRC_DRAMTMG7(0), 0x0000060b); + reg32_write(DDRC_DRAMTMG8(0), 0x01017c0a); + reg32_write(DDRC_DRAMTMG9(0), 0x4000000e); + reg32_write(DDRC_DRAMTMG10(0), 0x00070803); + reg32_write(DDRC_DRAMTMG11(0), 0x0101000b); + reg32_write(DDRC_DRAMTMG12(0), 0x00000000); + reg32_write(DDRC_DRAMTMG13(0), 0x5d000000); + reg32_write(DDRC_DRAMTMG14(0), 0x00000b39); + reg32_write(DDRC_DRAMTMG15(0), 0x80000000); + reg32_write(DDRC_DRAMTMG17(0), 0x00f1006a); + reg32_write(DDRC_ZQCTL0(0), 0x50800020); + reg32_write(DDRC_ZQCTL1(0), 0x00000070); + reg32_write(DDRC_ZQCTL2(0), 0x00000000); + reg32_write(DDRC_DFITMG0(0), 0x03868203); + reg32_write(DDRC_DFITMG1(0), 0x00020103); + reg32_write(DDRC_DFILPCFG0(0), 0x07713021); + reg32_write(DDRC_DFILPCFG1(0), 0x00000010); + reg32_write(DDRC_DFIUPD0(0), 0xe0400018); + reg32_write(DDRC_DFIUPD1(0), 0x0005003c); + reg32_write(DDRC_DFIUPD2(0), 0x80000000); + reg32_write(DDRC_DFIMISC(0), 0x00000011); + reg32_write(DDRC_DFITMG2(0), 0x00000603); + reg32_write(DDRC_DFITMG3(0), 0x00000001); + reg32_write(DDRC_DBICTL(0), 0x00000001); + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000); + + /* My test mapping in this test case, for 8Gb,(two 4Gb, x16 DDR3) (col addr:10 bits row addr: 15 bits bank addr: 3bits 2 ranks) */ + /* MEMC_BURST_LENGTH = 8 */ + /* ----------------------------------------------------------------------------------------------------------------------------------- */ + /* AXI add: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (MEM_DATWIDTH=64) */ + /* AXI add: 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (MEM_DATWIDTH=32) *** */ + /* AXI add: 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (MEM_DATWIDTH=16) */ + /* ----------------------------------------------------------------------------------------------------------------------------------- */ + /* HIF add: 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - */ + /* ----------------------------------------------------------------------------------------------------------------------------------- */ + /* **** for Full DQ bus width (X32) **** */ + /* cs r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 b2 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 */ + /* Int base 6 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 4 3 2 9 8 7 6 5 4 3 2 - */ + /* p Value 22 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 0 0 0 0 0 0 0 0 - */ + /* ----------------------------------------------------------------------------------------------------------------------------------- */ + + reg32_write(DDRC_ADDRMAP0(0), 0x00000016); /* [4:0] cs-bit0: 6+22=28; [12:8] cs-bit1: 7+0 */ + reg32_write(DDRC_ADDRMAP1(0), 0x00080808); /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+8 */ + reg32_write(DDRC_ADDRMAP2(0), 0x00000000); /* [3:0] col-b2: 2; [11:8] col-b3: 3; [19:16] col-b4: 4 ; [27:24] col-b5: 5 */ + reg32_write(DDRC_ADDRMAP3(0), 0x00000000); /* [3:0] col-b6: 6; [11:8] col-b7: 7; [19:16] col-b8: 8 ; [27:24] col-b9: 9 */ + reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */ + reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6; [11:8] row-b1: 7; [19:16] row-b2_b10 ; [27:24] row-b11: 17 */ + reg32_write(DDRC_ADDRMAP6(0), 0x0f070707); /* [3:0] row-b12:18; [11:8] row-b13: 19; [19:16] row-b14:20 */ + reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f); + reg32_write(DDRC_ADDRMAP8(0), 0x00000000); /* [5:0] bg-b0; [13:8]bg-b1 */ + reg32_write(DDRC_ADDRMAP9(0), 0x0a020b06); /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP10(0), 0x0a0a0a0a);/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP11(0), 0x00000000); + + + reg32_write(DDRC_ODTCFG(0), 0x041d0f5c); + reg32_write(DDRC_ODTMAP(0), 0x00000201); + reg32_write(DDRC_SCHED(0), 0x7ab50b07); + reg32_write(DDRC_SCHED1(0), 0x00000022); + reg32_write(DDRC_PERFHPR1(0), 0x7b00665e); + reg32_write(DDRC_PERFLPR1(0), 0x2b00c4e1); + reg32_write(DDRC_PERFWR1(0), 0xb700c9fe); + reg32_write(DDRC_DBG0(0), 0x00000017); + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_DBGCMD(0), 0x00000000); + reg32_write(DDRC_SWCTL(0), 0x00000001); + reg32_write(DDRC_POISONCFG(0), 0x00010000); + reg32_write(DDRC_PCCFG(0), 0x00000100); + reg32_write(DDRC_PCFGR_0(0), 0x00003051); + reg32_write(DDRC_PCFGW_0(0), 0x000061d2); + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + reg32_write(DDRC_PCFGQOS0_0(0), 0x02100b04); + reg32_write(DDRC_PCFGQOS1_0(0), 0x003f0353); + reg32_write(DDRC_PCFGWQOS0_0(0), 0x00000002); + reg32_write(DDRC_PCFGWQOS1_0(0), 0x000005fd); +} + +void umctl2_freq1_cfg(void) +{ + reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x00d19034); + reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x0040805e); + reg32_write(DDRC_FREQ1_INIT3(0), 0x09300004); + reg32_write(DDRC_FREQ1_INIT4(0), 0x00080000); + reg32_write(DDRC_FREQ1_INIT6(0), 0x00000000); + reg32_write(DDRC_FREQ1_INIT7(0), 0x00000000); + reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x090e110a); + reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x0007020e); + reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x03040407); + reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x00002006); + reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x04020304); /* tRP=6 --> 7 */ + reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x09030202); + reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0c020000); + reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x00000309); + reg32_write(DDRC_FREQ1_DRAMTMG8(0), 0x01010a06); + reg32_write(DDRC_FREQ1_DRAMTMG9(0), 0x00000003); + reg32_write(DDRC_FREQ1_DRAMTMG10(0), 0x00090906); + reg32_write(DDRC_FREQ1_DRAMTMG11(0), 0x01010011); + reg32_write(DDRC_FREQ1_DRAMTMG12(0), 0x00000000); + reg32_write(DDRC_FREQ1_DRAMTMG13(0), 0x40000000); + reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x000000f3); + reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x80000000); + reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x001a0046); + reg32_write(DDRC_FREQ1_ZQCTL0(0), 0x50800020); + reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03828201); + reg32_write(DDRC_FREQ1_DFITMG1(0), 0x00020103); + reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000201); + reg32_write(DDRC_FREQ1_DFITMG3(0), 0x00000001); + reg32_write(DDRC_FREQ1_ODTCFG(0), 0x0a1a0768); + +} + +void umctl2_freq2_cfg(void) +{ + reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x00208014); + reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x00308046); + reg32_write(DDRC_FREQ2_INIT3(0), 0x05200004); + reg32_write(DDRC_FREQ2_INIT4(0), 0x00000000); + reg32_write(DDRC_FREQ2_INIT6(0), 0x00000000); + reg32_write(DDRC_FREQ2_INIT7(0), 0x00000000); + reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x070a0c07); + reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x0005020b); + reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x03030407); + reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x00002006); + reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x03020204); + reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x04070302); + reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x07080000); + reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x00000704); + reg32_write(DDRC_FREQ2_DRAMTMG8(0), 0x02026804); + reg32_write(DDRC_FREQ2_DRAMTMG9(0), 0x40000006); + reg32_write(DDRC_FREQ2_DRAMTMG10(0), 0x000c0b08); + reg32_write(DDRC_FREQ2_DRAMTMG11(0), 0x01010015); + reg32_write(DDRC_FREQ2_DRAMTMG12(0), 0x00000000); + reg32_write(DDRC_FREQ2_DRAMTMG13(0), 0x51000000); + reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x000002a0); + reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000); + reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x008c0039); + reg32_write(DDRC_FREQ2_ZQCTL0(0), 0x50800020); + reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03818200); + reg32_write(DDRC_FREQ2_DFITMG1(0), 0x00020103); + reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000100); + reg32_write(DDRC_FREQ2_DFITMG3(0), 0x00000001); + reg32_write(DDRC_FREQ2_ODTCFG(0), 0x04050800); + +} + +void ddr3_pub_train(void) +{ + volatile unsigned int tmp_t; + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); /* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, [4]src_system_rst_b! */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); /* deassert [4]src_system_rst_b! */ + + /* change the clock source of dram_apb_clk_root */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); /* to source 4 --800MHz/4 */ + + dram_pll_init(DRAM_PLL_OUT_400M); + ddr_dbg("C: dram pll init finished\n"); + + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5);/* PU_PGC_SW_PUP_REQ */ + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */ + + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + + while (0 != (0x3 & reg32_read(DDRC_STAT(0)))) + ; + + ddr_dbg("C: cfg umctl2 regs ...\n"); + umctl2_cfg(); +#ifdef DDR3_SW_FFC + umctl2_freq1_cfg(); + umctl2_freq2_cfg(); +#endif + + reg32_write(DDRC_RFSHCTL3(0), 0x00000011); + /* RESET: DEASSERTED */ + /* RESET: +#include +#include +#include +#include +#include "../ddr.h" +#include "ddr3_define.h" + +static const unsigned int restore_csr[] = { + 0x200b2, + 0x1200b2, + 0x2200b2, + 0x200cb, +#ifdef RUN_ON_SILICON + 0x10043, + 0x110043, + 0x210043, + 0x10143, + 0x110143, + 0x210143, + 0x11043, + 0x111043, + 0x211043, + 0x11143, + 0x111143, + 0x211143, + 0x12043, + 0x112043, + 0x212043, + 0x12143, + 0x112143, + 0x212143, + 0x13043, + 0x113043, + 0x213043, + 0x13143, + 0x113143, + 0x213143, + 0x80, + 0x100080, + 0x200080, + 0x1080, + 0x101080, + 0x201080, + 0x2080, + 0x102080, + 0x202080, + 0x3080, + 0x103080, + 0x203080, + 0x4080, + 0x104080, + 0x204080, + 0x5080, + 0x105080, + 0x205080, + 0x6080, + 0x106080, + 0x206080, + 0x7080, + 0x107080, + 0x207080, + 0x8080, + 0x108080, + 0x208080, + 0x9080, + 0x109080, + 0x209080, + 0x10080, + 0x110080, + 0x210080, + 0x10180, + 0x110180, + 0x210180, + 0x10081, + 0x110081, + 0x210081, + 0x10181, + 0x110181, + 0x210181, + 0x10082, + 0x110082, + 0x210082, + 0x10182, + 0x110182, + 0x210182, + 0x10083, + 0x110083, + 0x210083, + 0x10183, + 0x110183, + 0x210183, + 0x11080, + 0x111080, + 0x211080, + 0x11180, + 0x111180, + 0x211180, + 0x11081, + 0x111081, + 0x211081, + 0x11181, + 0x111181, + 0x211181, + 0x11082, + 0x111082, + 0x211082, + 0x11182, + 0x111182, + 0x211182, + 0x11083, + 0x111083, + 0x211083, + 0x11183, + 0x111183, + 0x211183, + 0x12080, + 0x112080, + 0x212080, + 0x12180, + 0x112180, + 0x212180, + 0x12081, + 0x112081, + 0x212081, + 0x12181, + 0x112181, + 0x212181, + 0x12082, + 0x112082, + 0x212082, + 0x12182, + 0x112182, + 0x212182, + 0x12083, + 0x112083, + 0x212083, + 0x12183, + 0x112183, + 0x212183, + 0x13080, + 0x113080, + 0x213080, + 0x13180, + 0x113180, + 0x213180, + 0x13081, + 0x113081, + 0x213081, + 0x13181, + 0x113181, + 0x213181, + 0x13082, + 0x113082, + 0x213082, + 0x13182, + 0x113182, + 0x213182, + 0x13083, + 0x113083, + 0x213083, + 0x13183, + 0x113183, + 0x213183, + 0x100d0, + 0x1100d0, + 0x2100d0, + 0x101d0, + 0x1101d0, + 0x2101d0, + 0x100d1, + 0x1100d1, + 0x2100d1, + 0x101d1, + 0x1101d1, + 0x2101d1, + 0x100d2, + 0x1100d2, + 0x2100d2, + 0x101d2, + 0x1101d2, + 0x2101d2, + 0x100d3, + 0x1100d3, + 0x2100d3, + 0x101d3, + 0x1101d3, + 0x2101d3, + 0x110d0, + 0x1110d0, + 0x2110d0, + 0x111d0, + 0x1111d0, + 0x2111d0, + 0x110d1, + 0x1110d1, + 0x2110d1, + 0x111d1, + 0x1111d1, + 0x2111d1, + 0x110d2, + 0x1110d2, + 0x2110d2, + 0x111d2, + 0x1111d2, + 0x2111d2, + 0x110d3, + 0x1110d3, + 0x2110d3, + 0x111d3, + 0x1111d3, + 0x2111d3, + 0x120d0, + 0x1120d0, + 0x2120d0, + 0x121d0, + 0x1121d0, + 0x2121d0, + 0x120d1, + 0x1120d1, + 0x2120d1, + 0x121d1, + 0x1121d1, + 0x2121d1, + 0x120d2, + 0x1120d2, + 0x2120d2, + 0x121d2, + 0x1121d2, + 0x2121d2, + 0x120d3, + 0x1120d3, + 0x2120d3, + 0x121d3, + 0x1121d3, + 0x2121d3, + 0x130d0, + 0x1130d0, + 0x2130d0, + 0x131d0, + 0x1131d0, + 0x2131d0, + 0x130d1, + 0x1130d1, + 0x2130d1, + 0x131d1, + 0x1131d1, + 0x2131d1, + 0x130d2, + 0x1130d2, + 0x2130d2, + 0x131d2, + 0x1131d2, + 0x2131d2, + 0x130d3, + 0x1130d3, + 0x2130d3, + 0x131d3, + 0x1131d3, + 0x2131d3, + 0x10068, + 0x10168, + 0x10268, + 0x10368, + 0x10468, + 0x10568, + 0x10668, + 0x10768, + 0x10868, + 0x10069, + 0x10169, + 0x10269, + 0x10369, + 0x10469, + 0x10569, + 0x10669, + 0x10769, + 0x10869, + 0x1006a, + 0x1016a, + 0x1026a, + 0x1036a, + 0x1046a, + 0x1056a, + 0x1066a, + 0x1076a, + 0x1086a, + 0x1006b, + 0x1016b, + 0x1026b, + 0x1036b, + 0x1046b, + 0x1056b, + 0x1066b, + 0x1076b, + 0x1086b, + 0x11068, + 0x11168, + 0x11268, + 0x11368, + 0x11468, + 0x11568, + 0x11668, + 0x11768, + 0x11868, + 0x11069, + 0x11169, + 0x11269, + 0x11369, + 0x11469, + 0x11569, + 0x11669, + 0x11769, + 0x11869, + 0x1106a, + 0x1116a, + 0x1126a, + 0x1136a, + 0x1146a, + 0x1156a, + 0x1166a, + 0x1176a, + 0x1186a, + 0x1106b, + 0x1116b, + 0x1126b, + 0x1136b, + 0x1146b, + 0x1156b, + 0x1166b, + 0x1176b, + 0x1186b, + 0x12068, + 0x12168, + 0x12268, + 0x12368, + 0x12468, + 0x12568, + 0x12668, + 0x12768, + 0x12868, + 0x12069, + 0x12169, + 0x12269, + 0x12369, + 0x12469, + 0x12569, + 0x12669, + 0x12769, + 0x12869, + 0x1206a, + 0x1216a, + 0x1226a, + 0x1236a, + 0x1246a, + 0x1256a, + 0x1266a, + 0x1276a, + 0x1286a, + 0x1206b, + 0x1216b, + 0x1226b, + 0x1236b, + 0x1246b, + 0x1256b, + 0x1266b, + 0x1276b, + 0x1286b, + 0x13068, + 0x13168, + 0x13268, + 0x13368, + 0x13468, + 0x13568, + 0x13668, + 0x13768, + 0x13868, + 0x13069, + 0x13169, + 0x13269, + 0x13369, + 0x13469, + 0x13569, + 0x13669, + 0x13769, + 0x13869, + 0x1306a, + 0x1316a, + 0x1326a, + 0x1336a, + 0x1346a, + 0x1356a, + 0x1366a, + 0x1376a, + 0x1386a, + 0x1306b, + 0x1316b, + 0x1326b, + 0x1336b, + 0x1346b, + 0x1356b, + 0x1366b, + 0x1376b, + 0x1386b, + 0x1008c, + 0x11008c, + 0x21008c, + 0x1018c, + 0x11018c, + 0x21018c, + 0x1008d, + 0x11008d, + 0x21008d, + 0x1018d, + 0x11018d, + 0x21018d, + 0x1008e, + 0x11008e, + 0x21008e, + 0x1018e, + 0x11018e, + 0x21018e, + 0x1008f, + 0x11008f, + 0x21008f, + 0x1018f, + 0x11018f, + 0x21018f, + 0x1108c, + 0x11108c, + 0x21108c, + 0x1118c, + 0x11118c, + 0x21118c, + 0x1108d, + 0x11108d, + 0x21108d, + 0x1118d, + 0x11118d, + 0x21118d, + 0x1108e, + 0x11108e, + 0x21108e, + 0x1118e, + 0x11118e, + 0x21118e, + 0x1108f, + 0x11108f, + 0x21108f, + 0x1118f, + 0x11118f, + 0x21118f, + 0x1208c, + 0x11208c, + 0x21208c, + 0x1218c, + 0x11218c, + 0x21218c, + 0x1208d, + 0x11208d, + 0x21208d, + 0x1218d, + 0x11218d, + 0x21218d, + 0x1208e, + 0x11208e, + 0x21208e, + 0x1218e, + 0x11218e, + 0x21218e, + 0x1208f, + 0x11208f, + 0x21208f, + 0x1218f, + 0x11218f, + 0x21218f, + 0x1308c, + 0x11308c, + 0x21308c, + 0x1318c, + 0x11318c, + 0x21318c, + 0x1308d, + 0x11308d, + 0x21308d, + 0x1318d, + 0x11318d, + 0x21318d, + 0x1308e, + 0x11308e, + 0x21308e, + 0x1318e, + 0x11318e, + 0x21318e, + 0x1308f, + 0x11308f, + 0x21308f, + 0x1318f, + 0x11318f, + 0x21318f, + 0x100c0, + 0x1100c0, + 0x2100c0, + 0x101c0, + 0x1101c0, + 0x2101c0, + 0x102c0, + 0x1102c0, + 0x2102c0, + 0x103c0, + 0x1103c0, + 0x2103c0, + 0x104c0, + 0x1104c0, + 0x2104c0, + 0x105c0, + 0x1105c0, + 0x2105c0, + 0x106c0, + 0x1106c0, + 0x2106c0, + 0x107c0, + 0x1107c0, + 0x2107c0, + 0x108c0, + 0x1108c0, + 0x2108c0, + 0x100c1, + 0x1100c1, + 0x2100c1, + 0x101c1, + 0x1101c1, + 0x2101c1, + 0x102c1, + 0x1102c1, + 0x2102c1, + 0x103c1, + 0x1103c1, + 0x2103c1, + 0x104c1, + 0x1104c1, + 0x2104c1, + 0x105c1, + 0x1105c1, + 0x2105c1, + 0x106c1, + 0x1106c1, + 0x2106c1, + 0x107c1, + 0x1107c1, + 0x2107c1, + 0x108c1, + 0x1108c1, + 0x2108c1, + 0x100c2, + 0x1100c2, + 0x2100c2, + 0x101c2, + 0x1101c2, + 0x2101c2, + 0x102c2, + 0x1102c2, + 0x2102c2, + 0x103c2, + 0x1103c2, + 0x2103c2, + 0x104c2, + 0x1104c2, + 0x2104c2, + 0x105c2, + 0x1105c2, + 0x2105c2, + 0x106c2, + 0x1106c2, + 0x2106c2, + 0x107c2, + 0x1107c2, + 0x2107c2, + 0x108c2, + 0x1108c2, + 0x2108c2, + 0x100c3, + 0x1100c3, + 0x2100c3, + 0x101c3, + 0x1101c3, + 0x2101c3, + 0x102c3, + 0x1102c3, + 0x2102c3, + 0x103c3, + 0x1103c3, + 0x2103c3, + 0x104c3, + 0x1104c3, + 0x2104c3, + 0x105c3, + 0x1105c3, + 0x2105c3, + 0x106c3, + 0x1106c3, + 0x2106c3, + 0x107c3, + 0x1107c3, + 0x2107c3, + 0x108c3, + 0x1108c3, + 0x2108c3, + 0x110c0, + 0x1110c0, + 0x2110c0, + 0x111c0, + 0x1111c0, + 0x2111c0, + 0x112c0, + 0x1112c0, + 0x2112c0, + 0x113c0, + 0x1113c0, + 0x2113c0, + 0x114c0, + 0x1114c0, + 0x2114c0, + 0x115c0, + 0x1115c0, + 0x2115c0, + 0x116c0, + 0x1116c0, + 0x2116c0, + 0x117c0, + 0x1117c0, + 0x2117c0, + 0x118c0, + 0x1118c0, + 0x2118c0, + 0x110c1, + 0x1110c1, + 0x2110c1, + 0x111c1, + 0x1111c1, + 0x2111c1, + 0x112c1, + 0x1112c1, + 0x2112c1, + 0x113c1, + 0x1113c1, + 0x2113c1, + 0x114c1, + 0x1114c1, + 0x2114c1, + 0x115c1, + 0x1115c1, + 0x2115c1, + 0x116c1, + 0x1116c1, + 0x2116c1, + 0x117c1, + 0x1117c1, + 0x2117c1, + 0x118c1, + 0x1118c1, + 0x2118c1, + 0x110c2, + 0x1110c2, + 0x2110c2, + 0x111c2, + 0x1111c2, + 0x2111c2, + 0x112c2, + 0x1112c2, + 0x2112c2, + 0x113c2, + 0x1113c2, + 0x2113c2, + 0x114c2, + 0x1114c2, + 0x2114c2, + 0x115c2, + 0x1115c2, + 0x2115c2, + 0x116c2, + 0x1116c2, + 0x2116c2, + 0x117c2, + 0x1117c2, + 0x2117c2, + 0x118c2, + 0x1118c2, + 0x2118c2, + 0x110c3, + 0x1110c3, + 0x2110c3, + 0x111c3, + 0x1111c3, + 0x2111c3, + 0x112c3, + 0x1112c3, + 0x2112c3, + 0x113c3, + 0x1113c3, + 0x2113c3, + 0x114c3, + 0x1114c3, + 0x2114c3, + 0x115c3, + 0x1115c3, + 0x2115c3, + 0x116c3, + 0x1116c3, + 0x2116c3, + 0x117c3, + 0x1117c3, + 0x2117c3, + 0x118c3, + 0x1118c3, + 0x2118c3, + 0x120c0, + 0x1120c0, + 0x2120c0, + 0x121c0, + 0x1121c0, + 0x2121c0, + 0x122c0, + 0x1122c0, + 0x2122c0, + 0x123c0, + 0x1123c0, + 0x2123c0, + 0x124c0, + 0x1124c0, + 0x2124c0, + 0x125c0, + 0x1125c0, + 0x2125c0, + 0x126c0, + 0x1126c0, + 0x2126c0, + 0x127c0, + 0x1127c0, + 0x2127c0, + 0x128c0, + 0x1128c0, + 0x2128c0, + 0x120c1, + 0x1120c1, + 0x2120c1, + 0x121c1, + 0x1121c1, + 0x2121c1, + 0x122c1, + 0x1122c1, + 0x2122c1, + 0x123c1, + 0x1123c1, + 0x2123c1, + 0x124c1, + 0x1124c1, + 0x2124c1, + 0x125c1, + 0x1125c1, + 0x2125c1, + 0x126c1, + 0x1126c1, + 0x2126c1, + 0x127c1, + 0x1127c1, + 0x2127c1, + 0x128c1, + 0x1128c1, + 0x2128c1, + 0x120c2, + 0x1120c2, + 0x2120c2, + 0x121c2, + 0x1121c2, + 0x2121c2, + 0x122c2, + 0x1122c2, + 0x2122c2, + 0x123c2, + 0x1123c2, + 0x2123c2, + 0x124c2, + 0x1124c2, + 0x2124c2, + 0x125c2, + 0x1125c2, + 0x2125c2, + 0x126c2, + 0x1126c2, + 0x2126c2, + 0x127c2, + 0x1127c2, + 0x2127c2, + 0x128c2, + 0x1128c2, + 0x2128c2, + 0x120c3, + 0x1120c3, + 0x2120c3, + 0x121c3, + 0x1121c3, + 0x2121c3, + 0x122c3, + 0x1122c3, + 0x2122c3, + 0x123c3, + 0x1123c3, + 0x2123c3, + 0x124c3, + 0x1124c3, + 0x2124c3, + 0x125c3, + 0x1125c3, + 0x2125c3, + 0x126c3, + 0x1126c3, + 0x2126c3, + 0x127c3, + 0x1127c3, + 0x2127c3, + 0x128c3, + 0x1128c3, + 0x2128c3, + 0x130c0, + 0x1130c0, + 0x2130c0, + 0x131c0, + 0x1131c0, + 0x2131c0, + 0x132c0, + 0x1132c0, + 0x2132c0, + 0x133c0, + 0x1133c0, + 0x2133c0, + 0x134c0, + 0x1134c0, + 0x2134c0, + 0x135c0, + 0x1135c0, + 0x2135c0, + 0x136c0, + 0x1136c0, + 0x2136c0, + 0x137c0, + 0x1137c0, + 0x2137c0, + 0x138c0, + 0x1138c0, + 0x2138c0, + 0x130c1, + 0x1130c1, + 0x2130c1, + 0x131c1, + 0x1131c1, + 0x2131c1, + 0x132c1, + 0x1132c1, + 0x2132c1, + 0x133c1, + 0x1133c1, + 0x2133c1, + 0x134c1, + 0x1134c1, + 0x2134c1, + 0x135c1, + 0x1135c1, + 0x2135c1, + 0x136c1, + 0x1136c1, + 0x2136c1, + 0x137c1, + 0x1137c1, + 0x2137c1, + 0x138c1, + 0x1138c1, + 0x2138c1, + 0x130c2, + 0x1130c2, + 0x2130c2, + 0x131c2, + 0x1131c2, + 0x2131c2, + 0x132c2, + 0x1132c2, + 0x2132c2, + 0x133c2, + 0x1133c2, + 0x2133c2, + 0x134c2, + 0x1134c2, + 0x2134c2, + 0x135c2, + 0x1135c2, + 0x2135c2, + 0x136c2, + 0x1136c2, + 0x2136c2, + 0x137c2, + 0x1137c2, + 0x2137c2, + 0x138c2, + 0x1138c2, + 0x2138c2, + 0x130c3, + 0x1130c3, + 0x2130c3, + 0x131c3, + 0x1131c3, + 0x2131c3, + 0x132c3, + 0x1132c3, + 0x2132c3, + 0x133c3, + 0x1133c3, + 0x2133c3, + 0x134c3, + 0x1134c3, + 0x2134c3, + 0x135c3, + 0x1135c3, + 0x2135c3, + 0x136c3, + 0x1136c3, + 0x2136c3, + 0x137c3, + 0x1137c3, + 0x2137c3, + 0x138c3, + 0x1138c3, + 0x2138c3, + 0x10020, + 0x110020, + 0x210020, + 0x11020, + 0x111020, + 0x211020, + 0x12020, + 0x112020, + 0x212020, + 0x13020, + 0x113020, +#endif + 0x213020, + 0x2007d, + 0x12007d, + 0x22007d, + 0 +}; + +void restore_1d2d_trained_csr_ddr3_p012(unsigned int addr) +{ + unsigned int i; + + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + for (i = 0; restore_csr[i] != 0; i++) { + dwc_ddrphy_apb_wr(restore_csr[i], reg32_read(addr + (i << 2))); + } + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + + ddr_dbg("restore 1d2d training registers done \n"); +} diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/save_1d2d_trained_csr_ddr3_p012.c b/board/freescale/imx8mm_val/ddr/ddr3l/save_1d2d_trained_csr_ddr3_p012.c new file mode 100644 index 00000000000..4ea62bbc2bd --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr3l/save_1d2d_trained_csr_ddr3_p012.c @@ -0,0 +1,971 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "../ddr.h" +#include "ddr3_define.h" + +static const unsigned int save_csr[] = { + 0x200b2, + 0x1200b2, + 0x2200b2, + 0x200cb, +#ifdef RUN_ON_SILICON + 0x10043, + 0x110043, + 0x210043, + 0x10143, + 0x110143, + 0x210143, + 0x11043, + 0x111043, + 0x211043, + 0x11143, + 0x111143, + 0x211143, + 0x12043, + 0x112043, + 0x212043, + 0x12143, + 0x112143, + 0x212143, + 0x13043, + 0x113043, + 0x213043, + 0x13143, + 0x113143, + 0x213143, + 0x80, + 0x100080, + 0x200080, + 0x1080, + 0x101080, + 0x201080, + 0x2080, + 0x102080, + 0x202080, + 0x3080, + 0x103080, + 0x203080, + 0x4080, + 0x104080, + 0x204080, + 0x5080, + 0x105080, + 0x205080, + 0x6080, + 0x106080, + 0x206080, + 0x7080, + 0x107080, + 0x207080, + 0x8080, + 0x108080, + 0x208080, + 0x9080, + 0x109080, + 0x209080, + 0x10080, + 0x110080, + 0x210080, + 0x10180, + 0x110180, + 0x210180, + 0x10081, + 0x110081, + 0x210081, + 0x10181, + 0x110181, + 0x210181, + 0x10082, + 0x110082, + 0x210082, + 0x10182, + 0x110182, + 0x210182, + 0x10083, + 0x110083, + 0x210083, + 0x10183, + 0x110183, + 0x210183, + 0x11080, + 0x111080, + 0x211080, + 0x11180, + 0x111180, + 0x211180, + 0x11081, + 0x111081, + 0x211081, + 0x11181, + 0x111181, + 0x211181, + 0x11082, + 0x111082, + 0x211082, + 0x11182, + 0x111182, + 0x211182, + 0x11083, + 0x111083, + 0x211083, + 0x11183, + 0x111183, + 0x211183, + 0x12080, + 0x112080, + 0x212080, + 0x12180, + 0x112180, + 0x212180, + 0x12081, + 0x112081, + 0x212081, + 0x12181, + 0x112181, + 0x212181, + 0x12082, + 0x112082, + 0x212082, + 0x12182, + 0x112182, + 0x212182, + 0x12083, + 0x112083, + 0x212083, + 0x12183, + 0x112183, + 0x212183, + 0x13080, + 0x113080, + 0x213080, + 0x13180, + 0x113180, + 0x213180, + 0x13081, + 0x113081, + 0x213081, + 0x13181, + 0x113181, + 0x213181, + 0x13082, + 0x113082, + 0x213082, + 0x13182, + 0x113182, + 0x213182, + 0x13083, + 0x113083, + 0x213083, + 0x13183, + 0x113183, + 0x213183, + 0x100d0, + 0x1100d0, + 0x2100d0, + 0x101d0, + 0x1101d0, + 0x2101d0, + 0x100d1, + 0x1100d1, + 0x2100d1, + 0x101d1, + 0x1101d1, + 0x2101d1, + 0x100d2, + 0x1100d2, + 0x2100d2, + 0x101d2, + 0x1101d2, + 0x2101d2, + 0x100d3, + 0x1100d3, + 0x2100d3, + 0x101d3, + 0x1101d3, + 0x2101d3, + 0x110d0, + 0x1110d0, + 0x2110d0, + 0x111d0, + 0x1111d0, + 0x2111d0, + 0x110d1, + 0x1110d1, + 0x2110d1, + 0x111d1, + 0x1111d1, + 0x2111d1, + 0x110d2, + 0x1110d2, + 0x2110d2, + 0x111d2, + 0x1111d2, + 0x2111d2, + 0x110d3, + 0x1110d3, + 0x2110d3, + 0x111d3, + 0x1111d3, + 0x2111d3, + 0x120d0, + 0x1120d0, + 0x2120d0, + 0x121d0, + 0x1121d0, + 0x2121d0, + 0x120d1, + 0x1120d1, + 0x2120d1, + 0x121d1, + 0x1121d1, + 0x2121d1, + 0x120d2, + 0x1120d2, + 0x2120d2, + 0x121d2, + 0x1121d2, + 0x2121d2, + 0x120d3, + 0x1120d3, + 0x2120d3, + 0x121d3, + 0x1121d3, + 0x2121d3, + 0x130d0, + 0x1130d0, + 0x2130d0, + 0x131d0, + 0x1131d0, + 0x2131d0, + 0x130d1, + 0x1130d1, + 0x2130d1, + 0x131d1, + 0x1131d1, + 0x2131d1, + 0x130d2, + 0x1130d2, + 0x2130d2, + 0x131d2, + 0x1131d2, + 0x2131d2, + 0x130d3, + 0x1130d3, + 0x2130d3, + 0x131d3, + 0x1131d3, + 0x2131d3, + 0x10068, + 0x10168, + 0x10268, + 0x10368, + 0x10468, + 0x10568, + 0x10668, + 0x10768, + 0x10868, + 0x10069, + 0x10169, + 0x10269, + 0x10369, + 0x10469, + 0x10569, + 0x10669, + 0x10769, + 0x10869, + 0x1006a, + 0x1016a, + 0x1026a, + 0x1036a, + 0x1046a, + 0x1056a, + 0x1066a, + 0x1076a, + 0x1086a, + 0x1006b, + 0x1016b, + 0x1026b, + 0x1036b, + 0x1046b, + 0x1056b, + 0x1066b, + 0x1076b, + 0x1086b, + 0x11068, + 0x11168, + 0x11268, + 0x11368, + 0x11468, + 0x11568, + 0x11668, + 0x11768, + 0x11868, + 0x11069, + 0x11169, + 0x11269, + 0x11369, + 0x11469, + 0x11569, + 0x11669, + 0x11769, + 0x11869, + 0x1106a, + 0x1116a, + 0x1126a, + 0x1136a, + 0x1146a, + 0x1156a, + 0x1166a, + 0x1176a, + 0x1186a, + 0x1106b, + 0x1116b, + 0x1126b, + 0x1136b, + 0x1146b, + 0x1156b, + 0x1166b, + 0x1176b, + 0x1186b, + 0x12068, + 0x12168, + 0x12268, + 0x12368, + 0x12468, + 0x12568, + 0x12668, + 0x12768, + 0x12868, + 0x12069, + 0x12169, + 0x12269, + 0x12369, + 0x12469, + 0x12569, + 0x12669, + 0x12769, + 0x12869, + 0x1206a, + 0x1216a, + 0x1226a, + 0x1236a, + 0x1246a, + 0x1256a, + 0x1266a, + 0x1276a, + 0x1286a, + 0x1206b, + 0x1216b, + 0x1226b, + 0x1236b, + 0x1246b, + 0x1256b, + 0x1266b, + 0x1276b, + 0x1286b, + 0x13068, + 0x13168, + 0x13268, + 0x13368, + 0x13468, + 0x13568, + 0x13668, + 0x13768, + 0x13868, + 0x13069, + 0x13169, + 0x13269, + 0x13369, + 0x13469, + 0x13569, + 0x13669, + 0x13769, + 0x13869, + 0x1306a, + 0x1316a, + 0x1326a, + 0x1336a, + 0x1346a, + 0x1356a, + 0x1366a, + 0x1376a, + 0x1386a, + 0x1306b, + 0x1316b, + 0x1326b, + 0x1336b, + 0x1346b, + 0x1356b, + 0x1366b, + 0x1376b, + 0x1386b, + 0x1008c, + 0x11008c, + 0x21008c, + 0x1018c, + 0x11018c, + 0x21018c, + 0x1008d, + 0x11008d, + 0x21008d, + 0x1018d, + 0x11018d, + 0x21018d, + 0x1008e, + 0x11008e, + 0x21008e, + 0x1018e, + 0x11018e, + 0x21018e, + 0x1008f, + 0x11008f, + 0x21008f, + 0x1018f, + 0x11018f, + 0x21018f, + 0x1108c, + 0x11108c, + 0x21108c, + 0x1118c, + 0x11118c, + 0x21118c, + 0x1108d, + 0x11108d, + 0x21108d, + 0x1118d, + 0x11118d, + 0x21118d, + 0x1108e, + 0x11108e, + 0x21108e, + 0x1118e, + 0x11118e, + 0x21118e, + 0x1108f, + 0x11108f, + 0x21108f, + 0x1118f, + 0x11118f, + 0x21118f, + 0x1208c, + 0x11208c, + 0x21208c, + 0x1218c, + 0x11218c, + 0x21218c, + 0x1208d, + 0x11208d, + 0x21208d, + 0x1218d, + 0x11218d, + 0x21218d, + 0x1208e, + 0x11208e, + 0x21208e, + 0x1218e, + 0x11218e, + 0x21218e, + 0x1208f, + 0x11208f, + 0x21208f, + 0x1218f, + 0x11218f, + 0x21218f, + 0x1308c, + 0x11308c, + 0x21308c, + 0x1318c, + 0x11318c, + 0x21318c, + 0x1308d, + 0x11308d, + 0x21308d, + 0x1318d, + 0x11318d, + 0x21318d, + 0x1308e, + 0x11308e, + 0x21308e, + 0x1318e, + 0x11318e, + 0x21318e, + 0x1308f, + 0x11308f, + 0x21308f, + 0x1318f, + 0x11318f, + 0x21318f, + 0x100c0, + 0x1100c0, + 0x2100c0, + 0x101c0, + 0x1101c0, + 0x2101c0, + 0x102c0, + 0x1102c0, + 0x2102c0, + 0x103c0, + 0x1103c0, + 0x2103c0, + 0x104c0, + 0x1104c0, + 0x2104c0, + 0x105c0, + 0x1105c0, + 0x2105c0, + 0x106c0, + 0x1106c0, + 0x2106c0, + 0x107c0, + 0x1107c0, + 0x2107c0, + 0x108c0, + 0x1108c0, + 0x2108c0, + 0x100c1, + 0x1100c1, + 0x2100c1, + 0x101c1, + 0x1101c1, + 0x2101c1, + 0x102c1, + 0x1102c1, + 0x2102c1, + 0x103c1, + 0x1103c1, + 0x2103c1, + 0x104c1, + 0x1104c1, + 0x2104c1, + 0x105c1, + 0x1105c1, + 0x2105c1, + 0x106c1, + 0x1106c1, + 0x2106c1, + 0x107c1, + 0x1107c1, + 0x2107c1, + 0x108c1, + 0x1108c1, + 0x2108c1, + 0x100c2, + 0x1100c2, + 0x2100c2, + 0x101c2, + 0x1101c2, + 0x2101c2, + 0x102c2, + 0x1102c2, + 0x2102c2, + 0x103c2, + 0x1103c2, + 0x2103c2, + 0x104c2, + 0x1104c2, + 0x2104c2, + 0x105c2, + 0x1105c2, + 0x2105c2, + 0x106c2, + 0x1106c2, + 0x2106c2, + 0x107c2, + 0x1107c2, + 0x2107c2, + 0x108c2, + 0x1108c2, + 0x2108c2, + 0x100c3, + 0x1100c3, + 0x2100c3, + 0x101c3, + 0x1101c3, + 0x2101c3, + 0x102c3, + 0x1102c3, + 0x2102c3, + 0x103c3, + 0x1103c3, + 0x2103c3, + 0x104c3, + 0x1104c3, + 0x2104c3, + 0x105c3, + 0x1105c3, + 0x2105c3, + 0x106c3, + 0x1106c3, + 0x2106c3, + 0x107c3, + 0x1107c3, + 0x2107c3, + 0x108c3, + 0x1108c3, + 0x2108c3, + 0x110c0, + 0x1110c0, + 0x2110c0, + 0x111c0, + 0x1111c0, + 0x2111c0, + 0x112c0, + 0x1112c0, + 0x2112c0, + 0x113c0, + 0x1113c0, + 0x2113c0, + 0x114c0, + 0x1114c0, + 0x2114c0, + 0x115c0, + 0x1115c0, + 0x2115c0, + 0x116c0, + 0x1116c0, + 0x2116c0, + 0x117c0, + 0x1117c0, + 0x2117c0, + 0x118c0, + 0x1118c0, + 0x2118c0, + 0x110c1, + 0x1110c1, + 0x2110c1, + 0x111c1, + 0x1111c1, + 0x2111c1, + 0x112c1, + 0x1112c1, + 0x2112c1, + 0x113c1, + 0x1113c1, + 0x2113c1, + 0x114c1, + 0x1114c1, + 0x2114c1, + 0x115c1, + 0x1115c1, + 0x2115c1, + 0x116c1, + 0x1116c1, + 0x2116c1, + 0x117c1, + 0x1117c1, + 0x2117c1, + 0x118c1, + 0x1118c1, + 0x2118c1, + 0x110c2, + 0x1110c2, + 0x2110c2, + 0x111c2, + 0x1111c2, + 0x2111c2, + 0x112c2, + 0x1112c2, + 0x2112c2, + 0x113c2, + 0x1113c2, + 0x2113c2, + 0x114c2, + 0x1114c2, + 0x2114c2, + 0x115c2, + 0x1115c2, + 0x2115c2, + 0x116c2, + 0x1116c2, + 0x2116c2, + 0x117c2, + 0x1117c2, + 0x2117c2, + 0x118c2, + 0x1118c2, + 0x2118c2, + 0x110c3, + 0x1110c3, + 0x2110c3, + 0x111c3, + 0x1111c3, + 0x2111c3, + 0x112c3, + 0x1112c3, + 0x2112c3, + 0x113c3, + 0x1113c3, + 0x2113c3, + 0x114c3, + 0x1114c3, + 0x2114c3, + 0x115c3, + 0x1115c3, + 0x2115c3, + 0x116c3, + 0x1116c3, + 0x2116c3, + 0x117c3, + 0x1117c3, + 0x2117c3, + 0x118c3, + 0x1118c3, + 0x2118c3, + 0x120c0, + 0x1120c0, + 0x2120c0, + 0x121c0, + 0x1121c0, + 0x2121c0, + 0x122c0, + 0x1122c0, + 0x2122c0, + 0x123c0, + 0x1123c0, + 0x2123c0, + 0x124c0, + 0x1124c0, + 0x2124c0, + 0x125c0, + 0x1125c0, + 0x2125c0, + 0x126c0, + 0x1126c0, + 0x2126c0, + 0x127c0, + 0x1127c0, + 0x2127c0, + 0x128c0, + 0x1128c0, + 0x2128c0, + 0x120c1, + 0x1120c1, + 0x2120c1, + 0x121c1, + 0x1121c1, + 0x2121c1, + 0x122c1, + 0x1122c1, + 0x2122c1, + 0x123c1, + 0x1123c1, + 0x2123c1, + 0x124c1, + 0x1124c1, + 0x2124c1, + 0x125c1, + 0x1125c1, + 0x2125c1, + 0x126c1, + 0x1126c1, + 0x2126c1, + 0x127c1, + 0x1127c1, + 0x2127c1, + 0x128c1, + 0x1128c1, + 0x2128c1, + 0x120c2, + 0x1120c2, + 0x2120c2, + 0x121c2, + 0x1121c2, + 0x2121c2, + 0x122c2, + 0x1122c2, + 0x2122c2, + 0x123c2, + 0x1123c2, + 0x2123c2, + 0x124c2, + 0x1124c2, + 0x2124c2, + 0x125c2, + 0x1125c2, + 0x2125c2, + 0x126c2, + 0x1126c2, + 0x2126c2, + 0x127c2, + 0x1127c2, + 0x2127c2, + 0x128c2, + 0x1128c2, + 0x2128c2, + 0x120c3, + 0x1120c3, + 0x2120c3, + 0x121c3, + 0x1121c3, + 0x2121c3, + 0x122c3, + 0x1122c3, + 0x2122c3, + 0x123c3, + 0x1123c3, + 0x2123c3, + 0x124c3, + 0x1124c3, + 0x2124c3, + 0x125c3, + 0x1125c3, + 0x2125c3, + 0x126c3, + 0x1126c3, + 0x2126c3, + 0x127c3, + 0x1127c3, + 0x2127c3, + 0x128c3, + 0x1128c3, + 0x2128c3, + 0x130c0, + 0x1130c0, + 0x2130c0, + 0x131c0, + 0x1131c0, + 0x2131c0, + 0x132c0, + 0x1132c0, + 0x2132c0, + 0x133c0, + 0x1133c0, + 0x2133c0, + 0x134c0, + 0x1134c0, + 0x2134c0, + 0x135c0, + 0x1135c0, + 0x2135c0, + 0x136c0, + 0x1136c0, + 0x2136c0, + 0x137c0, + 0x1137c0, + 0x2137c0, + 0x138c0, + 0x1138c0, + 0x2138c0, + 0x130c1, + 0x1130c1, + 0x2130c1, + 0x131c1, + 0x1131c1, + 0x2131c1, + 0x132c1, + 0x1132c1, + 0x2132c1, + 0x133c1, + 0x1133c1, + 0x2133c1, + 0x134c1, + 0x1134c1, + 0x2134c1, + 0x135c1, + 0x1135c1, + 0x2135c1, + 0x136c1, + 0x1136c1, + 0x2136c1, + 0x137c1, + 0x1137c1, + 0x2137c1, + 0x138c1, + 0x1138c1, + 0x2138c1, + 0x130c2, + 0x1130c2, + 0x2130c2, + 0x131c2, + 0x1131c2, + 0x2131c2, + 0x132c2, + 0x1132c2, + 0x2132c2, + 0x133c2, + 0x1133c2, + 0x2133c2, + 0x134c2, + 0x1134c2, + 0x2134c2, + 0x135c2, + 0x1135c2, + 0x2135c2, + 0x136c2, + 0x1136c2, + 0x2136c2, + 0x137c2, + 0x1137c2, + 0x2137c2, + 0x138c2, + 0x1138c2, + 0x2138c2, + 0x130c3, + 0x1130c3, + 0x2130c3, + 0x131c3, + 0x1131c3, + 0x2131c3, + 0x132c3, + 0x1132c3, + 0x2132c3, + 0x133c3, + 0x1133c3, + 0x2133c3, + 0x134c3, + 0x1134c3, + 0x2134c3, + 0x135c3, + 0x1135c3, + 0x2135c3, + 0x136c3, + 0x1136c3, + 0x2136c3, + 0x137c3, + 0x1137c3, + 0x2137c3, + 0x138c3, + 0x1138c3, + 0x2138c3, + 0x10020, + 0x110020, + 0x210020, + 0x11020, + 0x111020, + 0x211020, + 0x12020, + 0x112020, + 0x212020, + 0x13020, + 0x113020, +#endif + 0x213020, + 0x2007d, + 0x12007d, + 0x22007d, + 0 +}; + +void save_1d2d_trained_csr_ddr3_p012(unsigned int addr) +{ + unsigned int i; + + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xc0080, 0x3); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + for (i = 0; save_csr[i] != 0; i++) { + reg32_write(addr + (i << 2), dwc_ddrphy_apb_rd(save_csr[i])); + } + dwc_ddrphy_apb_wr(0xc0080, 0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + + ddr_dbg("save 1d2d training registers done \n"); +} diff --git a/board/freescale/imx8mm_val/ddr/ddr4/Makefile b/board/freescale/imx8mm_val/ddr/ddr4/Makefile new file mode 100644 index 00000000000..c4265d5ed4a --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr4/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += ddr4_phyinit_task.o +obj-y += ddr4_phyinit_2400_400_100_2r_fw09.o +obj-y += ddr4_swffc_fw09.o +obj-y += save_1d2d_trained_csr_ddr4_p012.o +obj-y += restore_1d2d_trained_csr_ddr4_p012.o +endif diff --git a/board/freescale/imx8mm_val/ddr/ddr4/anamix_common.h b/board/freescale/imx8mm_val/ddr/ddr4/anamix_common.h new file mode 100644 index 00000000000..9f1ddd35538 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr4/anamix_common.h @@ -0,0 +1,88 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ANAMIX_COMMON_TMP_H +#define ANAMIX_COMMON_TMP_H + +/*ANAMIX Address Definition*/ +#define ANAMIX_PLL_BASE_ADDR 0x30360000 +#define ANAMIX_OSC_BASE_ADDR 0x30270000 +#define ANAMIX_TSN_BASE_ADDR 0x30260000 + +/* PLL TOP REG */ +#define AUDIO_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x00) +#define AUDIO_PLL1_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x04) +#define AUDIO_PLL1_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x08) +#define AUDIO_PLL1_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x0c) +#define AUDIO_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x10) +#define AUDIO_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x14) +#define AUDIO_PLL2_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x18) +#define AUDIO_PLL2_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x1c) +#define AUDIO_PLL2_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x20) +#define AUDIO_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x24) +#define VIDEO_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x28) +#define VIDEO_PLL1_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x2c) +#define VIDEO_PLL1_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x30) +#define VIDEO_PLL1_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x34) +#define VIDEO_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x38) +#define VIDEO_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x3c) +#define VIDEO_PLL2_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x40) +#define VIDEO_PLL2_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x44) +#define VIDEO_PLL2_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x48) +#define VIDEO_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x4c) +#define DRAM_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x50) +#define DRAM_PLL_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x54) +#define DRAM_PLL_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x58) +#define DRAM_PLL_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x5c) +#define DRAM_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60) +#define GPU_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64) +#define GPU_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68) +#define GPU_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x6c) +#define GPU_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x70) +#define VPU_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x74) +#define VPU_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x78) +#define VPU_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x7c) +#define VPU_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x80) +#define ARM_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x84) +#define ARM_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x88) +#define ARM_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x8c) +#define ARM_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x90) +#define SYS_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x94) +#define SYS_PLL1_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x98) +#define SYS_PLL1_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x9c) +#define SYS_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x100) +#define SYS_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x104) +#define SYS_PLL2_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x108) +#define SYS_PLL2_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x10c) +#define SYS_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x110) +#define SYS_PLL3_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x114) +#define SYS_PLL3_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x118) +#define SYS_PLL3_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x11c) +#define SYS_PLL3_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x120) +#define ANAMIX_MISC_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x124) +#define ANAMIX_CLK_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x128) + +/* TMP SNSR REG */ +#define TER_ADDR (ANAMIX_TSN_BASE_ADDR + 0x00) +#define TSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x04) +#define TIER_ADDR (ANAMIX_TSN_BASE_ADDR + 0x08) +#define TIDR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x0c) +#define TMHTITR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x10) +#define TMHTATR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x14) +#define TMHTACTR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x18) +#define TSCR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x1c) +#define TRITSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x20) +#define TRATSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x24) +#define TASR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x28) +#define TTMC_ADDR (ANAMIX_TSN_BASE_ADDR + 0x2c) + +/* OSC */ +#define SYS_OSCNML_CTL0_ADDR (ANAMIX_OSC_BASE_ADDR + 0x00) +#define SYS_OSCNML_CTL1_ADDR (ANAMIX_OSC_BASE_ADDR + 0x04) +#define HDMI_OSCNML_CTL0_ADDR (ANAMIX_OSC_BASE_ADDR + 0x8000) +#define HDMI_OSCNML_CTL1_ADDR (ANAMIX_OSC_BASE_ADDR + 0x8004) + +#endif diff --git a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_define.h b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_define.h new file mode 100644 index 00000000000..af1b0e9ba00 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_define.h @@ -0,0 +1,133 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR4_CONFIG_H__ +#define __DDR4_CONFIG_H__ + +#include "../ddr.h" + +#define RUN_ON_SILICON +#define DDR4_SW_FFC +#define ENABLE_RETENTION + +#define DRAM_VREF 0x1f + +#define SAVE_DDRPHY_TRAIN_ADDR 0x184000 + +/* choose p2 state data rate, define just one of below macro */ +#define PLLBYPASS_400MBPS + +/* //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// */ +/* for DDR4 */ +/* Note:DQ SI RON=40ohm, RTT=48ohm */ +/* CA SI RON=40ohm, RTT=65ohm */ +/* //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// */ +/* for DDR RTT NOM/PARK */ +#define DDR4_ODT_DIS 0 +#define DDR4_ODT_60 1 +#define DDR4_ODT_120 2 +#define DDR4_ODT_40 3 +#define DDR4_ODT_240 4 +#define DDR4_ODT_48 5 +#define DDR4_ODT_80 6 +#define DDR4_ODT_34 7 + +/* for DDR RON */ +#define DDR4_RON_34 0 +#define DDR4_RON_48 1 +#define DDR4_RON_40 2 +#define DDR4_RON_RES 3 + +/* for DDR RTT write */ +#define DDR4_RTT_WR_DIS 0 +#define DDR4_RTT_WR_120 1 +#define DDR4_RTT_WR_240 2 +#define DDR4_RTT_WR_HZ 3 +#define DDR4_RTT_WR_80 4 + +/* for DDR4 PHY data RON */ +#define DDR4_PHY_DATA_RON_34 0xeba +#define DDR4_PHY_DATA_RON_40 0xe38 +#define DDR4_PHY_DATA_RON_48 ((0x1a << 6) | 0x1a) +#define DDR4_PHY_DATA_RON_60 ((0x18 << 6) | 0x18) +#define DDR4_PHY_DATA_RON_80 ((0x0a << 6) | 0x0a) +#define DDR4_PHY_DATA_RON_120 ((0x08 << 6) | 0x08) +#define DDR4_PHY_DATA_RON_240 ((0x02<<6)|0x02) + +/* for DDR4 PHY data RTT */ +#define DDR4_PHY_DATA_RTT_34 0x3a +#define DDR4_PHY_DATA_RTT_40 0x38 +#define DDR4_PHY_DATA_RTT_48 0x1a +#define DDR4_PHY_DATA_RTT_60 0x18 +#define DDR4_PHY_DATA_RTT_80 0x0a +#define DDR4_PHY_DATA_RTT_120 0x08 +#define DDR4_PHY_DATA_RTT_240 0x02 + +/* for DDR4 PHY address RON */ +#define DDR4_PHY_ADDR_RON_30 ((0x07 << 5) | 0x07) +#define DDR4_PHY_ADDR_RON_40 0x63 +#define DDR4_PHY_ADDR_RON_60 ((0x01 << 5) | 0x01) +#define DDR4_PHY_ADDR_RON_120 ((0x00 << 5) | 0x00) + +#define DDR4_PHY_ADDR_RON DDR4_PHY_ADDR_RON_40 + +/* read DDR4 */ +#ifdef DDR_ONE_RANK +#define DDR4_RON DDR4_RON_34 +#define DDR4_PHY_DATA_RTT DDR4_PHY_DATA_RTT_48 +#define DDR4_PHYREF_VALUE 91 +#else +#define DDR4_RON DDR4_RON_40 +#define DDR4_PHY_DATA_RTT DDR4_PHY_DATA_RTT_48 +#define DDR4_PHYREF_VALUE 93 +#endif + +/* write DDR4 */ +#ifdef DDR_ONE_RANK +/* one lank */ +#define DDR4_PHY_DATA_RON DDR4_PHY_DATA_RON_34 +#define DDR4_RTT_NOM DDR4_ODT_60 +#define DDR4_RTT_WR DDR4_RTT_WR_DIS +#define DDR4_RTT_PARK DDR4_ODT_DIS +#define DDR4_MR6_VALUE 0x0d +#else +/* two lank */ +#define DDR4_PHY_DATA_RON DDR4_PHY_DATA_RON_40 +#define DDR4_RTT_NOM DDR4_ODT_60 +#define DDR4_RTT_WR DDR4_RTT_WR_DIS +#define DDR4_RTT_PARK DDR4_ODT_DIS +#define DDR4_MR6_VALUE 0x10 +#endif + +/* voltage:delay */ +#define DDR4_2D_WEIGHT (31 << 8 | 127) + +#define ANAMIX_PLL_BASE_ADDR 0x30360000 +#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60) +#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64) +#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68) +#define GPC_PU_PWRHSK 0x303A01FC +#define GPC_TOP_CONFIG_OFFSET 0x0000 +#define AIPS1_ARB_BASE_ADDR 0x30000000 +#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR +#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x200000) +#define CCM_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x180000) +#define CCM_SRC_CTRL_OFFSET (CCM_IPS_BASE_ADDR + 0x800) +#define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * n) + + +#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data) +#define dwc_ddrphy_apb_rd(addr) (reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))) +#define reg32clrbit(addr, bitpos) reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1 << (bitpos))))) +#define DDR_CSD1_BASE_ADDR 0x40000000 +#define DDR_CSD2_BASE_ADDR 0x80000000 + +void restore_1d2d_trained_csr_ddr4_p012(unsigned int addr); +void save_1d2d_trained_csr_ddr4_p012(unsigned int addr); +void ddr4_mr_write(unsigned int mr, unsigned int data, unsigned int read, unsigned int rank); +void ddr4_phyinit_train_sw_ffc(unsigned int Train2D); + +#endif diff --git a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_2400_400_100_2r_fw09.c b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_2400_400_100_2r_fw09.c new file mode 100644 index 00000000000..eed33ea6632 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_2400_400_100_2r_fw09.c @@ -0,0 +1,1420 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "ddr4_define.h" + +extern unsigned int after_retention; +extern unsigned int mr_value[3][7]; + +void ddr4_phyinit_train_sw_ffc(unsigned int Train2D) +{ + /* [dwc_ddrphy_phyinit_main] Start of dwc_ddrphy_phyinit_main() */ + /* [dwc_ddrphy_phyinit_sequence] Start of dwc_ddrphy_phyinit_sequence() */ + /* [dwc_ddrphy_phyinit_initStruct] Start of dwc_ddrphy_phyinit_initStruct() */ + /* [dwc_ddrphy_phyinit_initStruct] End of dwc_ddrphy_phyinit_initStruct() */ + /* [dwc_ddrphy_phyinit_setDefault] Start of dwc_ddrphy_phyinit_setDefault() */ + /* [dwc_ddrphy_phyinit_setDefault] End of dwc_ddrphy_phyinit_setDefault() */ + + + /* ############################################################## */ + /* */ + /* dwc_ddrphy_phyinit_userCustom_overrideUserInput is a user-editable function. */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + + dwc_ddrphy_phyinit_userCustom_overrideUserInput (); + /* */ + /* [dwc_ddrphy_phyinit_userCustom_overrideUserInput] End of dwc_ddrphy_phyinit_userCustom_overrideUserInput() */ + + + /* ############################################################## */ + /* */ + /* Step (A) : Bring up VDD, VDDQ, and VAA */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + + + dwc_ddrphy_phyinit_userCustom_A_bringupPower (); + + /* [dwc_ddrphy_phyinit_userCustom_A_bringupPower] End of dwc_ddrphy_phyinit_userCustom_A_bringupPower() */ + /* [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] Start of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* Step (B) Start Clocks and Reset the PHY */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy (); + + /* [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] End of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() */ + /* */ + + /* ############################################################## */ + /* */ + /* Step (C) Initialize PHY Configuration */ + /* */ + /* Load the required PHY configuration registers for the appropriate mode and memory configuration */ + /* */ + /* ############################################################## */ + /* */ + + /* [phyinit_C_initPhyConfig] Start of dwc_ddrphy_phyinit_C_initPhyConfig() */ + /* */ + /* ############################################################## */ + /* TxPreDrvMode[2] = 0 */ + /* ############################################################## */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxSlewRate::TxPreDrvMode to 0x2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxSlewRate::TxPreP to 0xd */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxSlewRate::TxPreN to 0xf */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x1005f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1015f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1105f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1115f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1205f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1215f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1305f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1315f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxSlewRate::TxPreDrvMode to 0x2 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxSlewRate::TxPreP to 0xd */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxSlewRate::TxPreN to 0xf */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x11005f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 */ + dwc_ddrphy_apb_wr(0x11015f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 */ + dwc_ddrphy_apb_wr(0x11105f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 */ + dwc_ddrphy_apb_wr(0x11115f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 */ + dwc_ddrphy_apb_wr(0x11205f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 */ + dwc_ddrphy_apb_wr(0x11215f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 */ + dwc_ddrphy_apb_wr(0x11305f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 */ + dwc_ddrphy_apb_wr(0x11315f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxSlewRate::TxPreDrvMode to 0x2 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxSlewRate::TxPreP to 0xd */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxSlewRate::TxPreN to 0xf */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x21005f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 */ + dwc_ddrphy_apb_wr(0x21015f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 */ + dwc_ddrphy_apb_wr(0x21105f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 */ + dwc_ddrphy_apb_wr(0x21115f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 */ + dwc_ddrphy_apb_wr(0x21205f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 */ + dwc_ddrphy_apb_wr(0x21215f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 */ + dwc_ddrphy_apb_wr(0x21305f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 */ + dwc_ddrphy_apb_wr(0x21315f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=0 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=0 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=0 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x55, 0x355); /* DWC_DDRPHYA_ANIB0_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=1 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=1 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=1 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x1055, 0x355); /* DWC_DDRPHYA_ANIB1_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=2 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=2 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=2 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x2055, 0x355); /* DWC_DDRPHYA_ANIB2_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=3 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=3 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=3 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x3055, 0x355); /* DWC_DDRPHYA_ANIB3_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x0, ANIB=4 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=4 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=4 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x4055, 0x55); /* DWC_DDRPHYA_ANIB4_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x0, ANIB=5 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=5 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=5 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x5055, 0x55); /* DWC_DDRPHYA_ANIB5_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=6 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=6 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=6 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x6055, 0x355); /* DWC_DDRPHYA_ANIB6_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=7 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=7 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=7 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x7055, 0x355); /* DWC_DDRPHYA_ANIB7_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=8 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=8 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=8 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x8055, 0x355); /* DWC_DDRPHYA_ANIB8_ATxSlewRate */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=9 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=9 */ + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=9 */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */ + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */ + + dwc_ddrphy_apb_wr(0x9055, 0x355); /* DWC_DDRPHYA_ANIB9_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x200c5, 0xa); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming PllCtrl2 to a based on DfiClk frequency = 600. */ + dwc_ddrphy_apb_wr(0x1200c5, 0x7); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming PllCtrl2 to 7 based on DfiClk frequency = 100. */ + dwc_ddrphy_apb_wr(0x2200c5, 0x7); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming PllCtrl2 to 7 based on DfiClk frequency = 25. */ + /* */ + /* ############################################################## */ + /* */ + /* Program ARdPtrInitVal based on Frequency and PLL Bypass inputs */ + /* The values programmed here assume ideal properties of DfiClk */ + /* and Pclk including: */ + /* - DfiClk skew */ + /* - DfiClk jitter */ + /* - DfiClk PVT variations */ + /* - Pclk skew */ + /* - Pclk jitter */ + /* */ + /* PLL Bypassed mode: */ + /* For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 2-6 */ + /* For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6 */ + /* */ + /* PLL Enabled mode: */ + /* For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6 */ + /* For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-6 */ + /* */ + /* ############################################################## */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming ARdPtrInitVal to 0x2 */ + dwc_ddrphy_apb_wr(0x2002e, 0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming ARdPtrInitVal to 0x2 */ + dwc_ddrphy_apb_wr(0x12002e, 0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming ARdPtrInitVal to 0x2 */ + dwc_ddrphy_apb_wr(0x22002e, 0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl to 0x8 */ + dwc_ddrphy_apb_wr(0x20024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DbyteDllModeCntrl to 0x2 */ + dwc_ddrphy_apb_wr(0x2003a, 0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl to 0x8 */ + dwc_ddrphy_apb_wr(0x120024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DbyteDllModeCntrl to 0x2 */ + dwc_ddrphy_apb_wr(0x2003a, 0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl to 0x8 */ + dwc_ddrphy_apb_wr(0x220024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DbyteDllModeCntrl to 0x2 */ + dwc_ddrphy_apb_wr(0x2003a, 0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming ProcOdtTimeCtl to 0x6 */ + dwc_ddrphy_apb_wr(0x20056, 0x6); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming ProcOdtTimeCtl to 0xa */ + dwc_ddrphy_apb_wr(0x120056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming ProcOdtTimeCtl to 0xa */ + dwc_ddrphy_apb_wr(0x220056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxOdtDrvStren::ODTStrenP to 0x1a */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxOdtDrvStren::ODTStrenN to 0x0 */ + dwc_ddrphy_apb_wr(0x1004d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1014d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1104d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1114d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1204d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1214d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1304d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1314d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxOdtDrvStren::ODTStrenP to 0x1a */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxOdtDrvStren::ODTStrenN to 0x0 */ + dwc_ddrphy_apb_wr(0x11004d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 */ + dwc_ddrphy_apb_wr(0x11014d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 */ + dwc_ddrphy_apb_wr(0x11104d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 */ + dwc_ddrphy_apb_wr(0x11114d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 */ + dwc_ddrphy_apb_wr(0x11204d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 */ + dwc_ddrphy_apb_wr(0x11214d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 */ + dwc_ddrphy_apb_wr(0x11304d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 */ + dwc_ddrphy_apb_wr(0x11314d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxOdtDrvStren::ODTStrenP to 0x1a */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxOdtDrvStren::ODTStrenN to 0x0 */ + dwc_ddrphy_apb_wr(0x21004d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 */ + dwc_ddrphy_apb_wr(0x21014d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 */ + dwc_ddrphy_apb_wr(0x21104d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 */ + dwc_ddrphy_apb_wr(0x21114d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 */ + dwc_ddrphy_apb_wr(0x21204d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 */ + dwc_ddrphy_apb_wr(0x21214d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 */ + dwc_ddrphy_apb_wr(0x21304d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 */ + dwc_ddrphy_apb_wr(0x21314d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */ + dwc_ddrphy_apb_wr(0x10049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x10149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x11049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x11149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x12049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x12149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x13049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x13149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */ + dwc_ddrphy_apb_wr(0x110049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 */ + dwc_ddrphy_apb_wr(0x110149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 */ + dwc_ddrphy_apb_wr(0x111049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 */ + dwc_ddrphy_apb_wr(0x111149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 */ + dwc_ddrphy_apb_wr(0x112049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 */ + dwc_ddrphy_apb_wr(0x112149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 */ + dwc_ddrphy_apb_wr(0x113049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 */ + dwc_ddrphy_apb_wr(0x113149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */ + dwc_ddrphy_apb_wr(0x210049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 */ + dwc_ddrphy_apb_wr(0x210149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 */ + dwc_ddrphy_apb_wr(0x211049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 */ + dwc_ddrphy_apb_wr(0x211149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 */ + dwc_ddrphy_apb_wr(0x212049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 */ + dwc_ddrphy_apb_wr(0x212149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 */ + dwc_ddrphy_apb_wr(0x213049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 */ + dwc_ddrphy_apb_wr(0x213149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 */ + /* [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenP to 0x3 */ + /* [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenN to 0x3 */ + dwc_ddrphy_apb_wr(0x43, 0x63); /* DWC_DDRPHYA_ANIB0_ATxImpedance */ + dwc_ddrphy_apb_wr(0x1043, 0x63); /* DWC_DDRPHYA_ANIB1_ATxImpedance */ + dwc_ddrphy_apb_wr(0x2043, 0x63); /* DWC_DDRPHYA_ANIB2_ATxImpedance */ + dwc_ddrphy_apb_wr(0x3043, 0x63); /* DWC_DDRPHYA_ANIB3_ATxImpedance */ + dwc_ddrphy_apb_wr(0x4043, 0x63); /* DWC_DDRPHYA_ANIB4_ATxImpedance */ + dwc_ddrphy_apb_wr(0x5043, 0x63); /* DWC_DDRPHYA_ANIB5_ATxImpedance */ + dwc_ddrphy_apb_wr(0x6043, 0x63); /* DWC_DDRPHYA_ANIB6_ATxImpedance */ + dwc_ddrphy_apb_wr(0x7043, 0x63); /* DWC_DDRPHYA_ANIB7_ATxImpedance */ + dwc_ddrphy_apb_wr(0x8043, 0x63); /* DWC_DDRPHYA_ANIB8_ATxImpedance */ + dwc_ddrphy_apb_wr(0x9043, 0x63); /* DWC_DDRPHYA_ANIB9_ATxImpedance */ + /* [phyinit_C_initPhyConfig] Programming DfiMode to 0x5 */ + dwc_ddrphy_apb_wr(0x20018, 0x5); /* DWC_DDRPHYA_MASTER0_DfiMode */ + /* [phyinit_C_initPhyConfig] Programming DfiCAMode to 0x2 */ + dwc_ddrphy_apb_wr(0x20075, 0x2); /* DWC_DDRPHYA_MASTER0_DfiCAMode */ + /* [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPd50 to 0x0 */ + /* [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPu50 to 0x0 */ + dwc_ddrphy_apb_wr(0x20050, 0x0); /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x258 */ + dwc_ddrphy_apb_wr(0x20008, 0x258); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x64 */ + dwc_ddrphy_apb_wr(0x120008, 0x64); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x19 */ + dwc_ddrphy_apb_wr(0x220008, 0x19); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 */ + /* [phyinit_C_initPhyConfig] Programming CalRate::CalInterval to 0x9 */ + /* [phyinit_C_initPhyConfig] Programming CalRate::CalOnce to 0x0 */ + dwc_ddrphy_apb_wr(0x20088, 0x9); /* DWC_DDRPHYA_MASTER0_CalRate */ + /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x4d */ + /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0x268 */ + dwc_ddrphy_apb_wr(0x200b2, 0x268); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x3 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl to 0x5b1 */ + dwc_ddrphy_apb_wr(0x10043, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x10143, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x11043, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x11143, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x12043, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x12143, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x13043, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x13143, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal::GlobalVrefInDAC to 0x4d */ + /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal to 0x268 */ + dwc_ddrphy_apb_wr(0x1200b2, 0x268); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x3 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Programming DqDqsRcvCntrl to 0x5b1 */ + dwc_ddrphy_apb_wr(0x110043, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 */ + dwc_ddrphy_apb_wr(0x110143, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 */ + dwc_ddrphy_apb_wr(0x111043, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 */ + dwc_ddrphy_apb_wr(0x111143, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 */ + dwc_ddrphy_apb_wr(0x112043, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 */ + dwc_ddrphy_apb_wr(0x112143, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 */ + dwc_ddrphy_apb_wr(0x113043, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 */ + dwc_ddrphy_apb_wr(0x113143, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal::GlobalVrefInDAC to 0x4d */ + /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal to 0x268 */ + dwc_ddrphy_apb_wr(0x2200b2, 0x268); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x3 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Programming DqDqsRcvCntrl to 0x5b1 */ + dwc_ddrphy_apb_wr(0x210043, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 */ + dwc_ddrphy_apb_wr(0x210143, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 */ + dwc_ddrphy_apb_wr(0x211043, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 */ + dwc_ddrphy_apb_wr(0x211143, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 */ + dwc_ddrphy_apb_wr(0x212043, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 */ + dwc_ddrphy_apb_wr(0x212143, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 */ + dwc_ddrphy_apb_wr(0x213043, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 */ + dwc_ddrphy_apb_wr(0x213143, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 */ + /* [phyinit_C_initPhyConfig] Programming MemAlertControl::MALERTVrefLevel to 0x29 */ + /* [phyinit_C_initPhyConfig] Programming MemAlertControl::MALERTPuStren to 0x5 */ + /* [phyinit_C_initPhyConfig] Programming MemAlertControl to 0x7529 */ + /* [phyinit_C_initPhyConfig] Programming MemAlertControl2::MALERTSyncBypass to 0x0 */ + dwc_ddrphy_apb_wr(0x2005b, 0x7529); /* DWC_DDRPHYA_MASTER0_MemAlertControl */ + dwc_ddrphy_apb_wr(0x2005c, 0x0); /* DWC_DDRPHYA_MASTER0_MemAlertControl2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DfiFreqRatio_p0 to 0x1 */ + dwc_ddrphy_apb_wr(0x200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DfiFreqRatio_p1 to 0x1 */ + dwc_ddrphy_apb_wr(0x1200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DfiFreqRatio_p2 to 0x1 */ + dwc_ddrphy_apb_wr(0x2200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TristateModeCA::DisDynAdrTri_p0 to 0x1 */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TristateModeCA::DDR2TMode_p0 to 0x0 */ + dwc_ddrphy_apb_wr(0x20019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TristateModeCA::DisDynAdrTri_p1 to 0x1 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TristateModeCA::DDR2TMode_p1 to 0x0 */ + dwc_ddrphy_apb_wr(0x120019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TristateModeCA::DisDynAdrTri_p2 to 0x1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TristateModeCA::DDR2TMode_p2 to 0x0 */ + dwc_ddrphy_apb_wr(0x220019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p2 */ + /* [phyinit_C_initPhyConfig] Programming DfiFreqXlat* */ + dwc_ddrphy_apb_wr(0x200f0, 0x5665); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */ + dwc_ddrphy_apb_wr(0x200f1, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */ + dwc_ddrphy_apb_wr(0x200f2, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */ + dwc_ddrphy_apb_wr(0x200f3, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */ + dwc_ddrphy_apb_wr(0x200f4, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */ + dwc_ddrphy_apb_wr(0x200f5, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */ + dwc_ddrphy_apb_wr(0x200f6, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */ + dwc_ddrphy_apb_wr(0x200f7, 0xf000); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */ + /* [phyinit_C_initPhyConfig] Programming MasterX4Config::X4TG to 0x0 */ + dwc_ddrphy_apb_wr(0x20025, 0x0); /* DWC_DDRPHYA_MASTER0_MasterX4Config */ + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0 */ + dwc_ddrphy_apb_wr(0x2002d, 0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */ + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0 */ + dwc_ddrphy_apb_wr(0x12002d, 0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p1 */ + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0 */ + dwc_ddrphy_apb_wr(0x22002d, 0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p2 */ + /* [phyinit_C_initPhyConfig] End of dwc_ddrphy_phyinit_C_initPhyConfig() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* dwc_ddrphy_phyihunit_userCustom_customPreTrain is a user-editable function. */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + ddr_dbg("add 845S pll setting in phyinit\n"); + /* [phyinit_userCustom_customPreTrain] Start of dwc_ddrphy_phyinit_userCustom_customPreTrain() */ + dwc_ddrphy_apb_wr(0x200c7, 0x21); /* DWC_DDRPHYA_MASTER0_PllCtrl1_p0 */ + dwc_ddrphy_apb_wr(0x200ca, 0x24); /* DWC_DDRPHYA_MASTER0_PllTestMode_p0 */ + /* [phyinit_userCustom_customPreTrain] End of dwc_ddrphy_phyinit_userCustom_customPreTrain() */ + /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=0) */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (D) Load the 1D IMEM image */ + /* */ + /* This function loads the training firmware IMEM image into the SRAM. */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Programming MemResetL to 0x2 */ + if (!after_retention) { + dwc_ddrphy_apb_wr(0x20060, 0x2); + + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_imem.incv */ + + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x50000 size 0x4000 */ + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x4000 */ + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + /* This allows the firmware unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] End of dwc_ddrphy_phyinit_D_loadIMEM() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* Step (E) Set the PHY input clocks to the desired frequency for pstate 0 */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0); */ + + /* */ + /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */ + /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=0) */ + + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* for test on silicon, load 1D dmem/imem here */ +#ifdef CONFIG_SPL_VSI_FW_LOADING + load_train_1d_code(); +#else + ddr_load_train_code(FW_1D_IMAGE); +#endif + ddr_dbg("start 1d train\n"); + + /* */ + /* ############################################################## */ + /* */ + /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_dmem.incv */ + + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */ +#ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x54000, 0x0); +#else + dwc_ddrphy_apb_wr(0x54000, 0x600); +#endif + dwc_ddrphy_apb_wr(0x54001, 0x0); + dwc_ddrphy_apb_wr(0x54002, 0x0); + dwc_ddrphy_apb_wr(0x54003, 0x960); + dwc_ddrphy_apb_wr(0x54004, 0x2); + dwc_ddrphy_apb_wr(0x54005, 0x0); + dwc_ddrphy_apb_wr(0x54006, 0x25e); + dwc_ddrphy_apb_wr(0x54007, 0x2000); +#ifdef DDR_ONE_RANK + dwc_ddrphy_apb_wr(0x54008, 0x101); + dwc_ddrphy_apb_wr(0x54009, 0x0); +#else + dwc_ddrphy_apb_wr(0x54008, 0x303); + dwc_ddrphy_apb_wr(0x54009, 0x200);/* no addr mirror, 0x200 addr mirror */ +#endif + dwc_ddrphy_apb_wr(0x5400a, 0x0); +#ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x5400b, 0x31f); +#else + dwc_ddrphy_apb_wr(0x5400b, 0x1); +#endif + dwc_ddrphy_apb_wr(0x5400c, 0xc8); + dwc_ddrphy_apb_wr(0x5400d, 0x0); + dwc_ddrphy_apb_wr(0x5400e, 0x0); + dwc_ddrphy_apb_wr(0x5400f, 0x0); + dwc_ddrphy_apb_wr(0x54010, 0x0); + dwc_ddrphy_apb_wr(0x54011, 0x0); + dwc_ddrphy_apb_wr(0x54012, 0x1); + dwc_ddrphy_apb_wr(0x5402f, mr_value[0][0]); + dwc_ddrphy_apb_wr(0x54030, mr_value[0][1]); + dwc_ddrphy_apb_wr(0x54031, mr_value[0][2]); + dwc_ddrphy_apb_wr(0x54032, mr_value[0][3]); + dwc_ddrphy_apb_wr(0x54033, mr_value[0][4]); + dwc_ddrphy_apb_wr(0x54034, mr_value[0][5]); + dwc_ddrphy_apb_wr(0x54035, mr_value[0][6]); + +#ifdef DDR_ONE_RANK + dwc_ddrphy_apb_wr(0x54036, 0x101); +#else + dwc_ddrphy_apb_wr(0x54036, 0x103); +#endif + dwc_ddrphy_apb_wr(0x54037, 0x0); + dwc_ddrphy_apb_wr(0x54038, 0x0); + dwc_ddrphy_apb_wr(0x54039, 0x0); + dwc_ddrphy_apb_wr(0x5403a, 0x0); + dwc_ddrphy_apb_wr(0x5403b, 0x0); + dwc_ddrphy_apb_wr(0x5403c, 0x0); + dwc_ddrphy_apb_wr(0x5403d, 0x0); + dwc_ddrphy_apb_wr(0x5403e, 0x0); + dwc_ddrphy_apb_wr(0x5403f, 0x1221); + dwc_ddrphy_apb_wr(0x541fc, 0x100); + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */ + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + /* This allows the firmware unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (G) Execute the Training Firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */ + /* ResetToMicro fields to 1 (all other fields should be zero). */ + /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */ + dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */ + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. */ + /* Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */ + dwc_ddrphy_phyinit_userCustom_G_waitFwDone (); + + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */ + /* 4. Halt the microcontroller." */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (H) Read the Message Block results */ + /* */ + /* The procedure is as follows: */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* */ + /* 2. Read the Firmware Message Block to obtain the results from the training. */ + /* This can be accomplished by issuing APB read commands to the DMEM addresses. */ + /* Example: */ + /* if (Train2D) */ + /* { */ + /* _read_2d_message_block_outputs_ */ + /* } */ + /* else */ + /* { */ + /* _read_1d_message_block_outputs_ */ + /* } */ + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0); + + /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */ + /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* 4. If training is required at another frequency, repeat the operations starting at step (E). */ + /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* Step (E) Set the PHY input clocks to the desired frequency for pstate 1 */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ +#ifdef DDR4_SW_FFC + dwc_ddrphy_phyinit_userCustom_E_setDfiClk (1); + + /* */ + /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */ + /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=1, Train2D=0) */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_dmem.incv */ + + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */ +#ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x54000, 0x0); +#else + dwc_ddrphy_apb_wr(0x54000, 0x600); +#endif + dwc_ddrphy_apb_wr(0x54001, 0x0); + dwc_ddrphy_apb_wr(0x54002, 0x101); + dwc_ddrphy_apb_wr(0x54003, 0x190); + dwc_ddrphy_apb_wr(0x54004, 0x2); + dwc_ddrphy_apb_wr(0x54005, 0x0); + dwc_ddrphy_apb_wr(0x54006, 0x25e); + dwc_ddrphy_apb_wr(0x54007, 0x2000); +#ifdef DDR_ONE_RANK + dwc_ddrphy_apb_wr(0x54008, 0x101); + dwc_ddrphy_apb_wr(0x54009, 0x0); +#else + dwc_ddrphy_apb_wr(0x54008, 0x303); + dwc_ddrphy_apb_wr(0x54009, 0x200); +#endif + dwc_ddrphy_apb_wr(0x5400a, 0x0); +#ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x5400b, 0x21f); +#else + dwc_ddrphy_apb_wr(0x5400b, 0x5); +#endif + dwc_ddrphy_apb_wr(0x5400c, 0xc8); + dwc_ddrphy_apb_wr(0x5400d, 0x0); + dwc_ddrphy_apb_wr(0x5400e, 0x0); + dwc_ddrphy_apb_wr(0x5400f, 0x0); + dwc_ddrphy_apb_wr(0x54010, 0x0); + dwc_ddrphy_apb_wr(0x54011, 0x0); + dwc_ddrphy_apb_wr(0x54012, 0x1); + dwc_ddrphy_apb_wr(0x5402f, mr_value[1][0]); + dwc_ddrphy_apb_wr(0x54030, mr_value[1][1]); + dwc_ddrphy_apb_wr(0x54031, mr_value[1][2]); + dwc_ddrphy_apb_wr(0x54032, mr_value[1][3]); + dwc_ddrphy_apb_wr(0x54033, mr_value[1][4]); + dwc_ddrphy_apb_wr(0x54034, mr_value[1][5]); + dwc_ddrphy_apb_wr(0x54035, mr_value[1][6]); + +#ifdef DDR_ONE_RANK + dwc_ddrphy_apb_wr(0x54036, 0x101); +#else + dwc_ddrphy_apb_wr(0x54036, 0x103); +#endif + dwc_ddrphy_apb_wr(0x54037, 0x0); + dwc_ddrphy_apb_wr(0x54038, 0x0); + dwc_ddrphy_apb_wr(0x54039, 0x0); + dwc_ddrphy_apb_wr(0x5403a, 0x0); + dwc_ddrphy_apb_wr(0x5403b, 0x0); + dwc_ddrphy_apb_wr(0x5403c, 0x0); + dwc_ddrphy_apb_wr(0x5403d, 0x0); + dwc_ddrphy_apb_wr(0x5403e, 0x0); + dwc_ddrphy_apb_wr(0x5403f, 0x1221); + dwc_ddrphy_apb_wr(0x541fc, 0x100); + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */ + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + /* This allows the firmware unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (G) Execute the Training Firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */ + /* ResetToMicro fields to 1 (all other fields should be zero). */ + /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */ + dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */ + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */ + dwc_ddrphy_phyinit_userCustom_G_waitFwDone (); + + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */ + /* 4. Halt the microcontroller." */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (H) Read the Message Block results */ + /* */ + /* The procedure is as follows: */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* */ + /* 2. Read the Firmware Message Block to obtain the results from the training. */ + /* This can be accomplished by issuing APB read commands to the DMEM addresses. */ + /* Example: */ + /* if (Train2D) */ + /* { */ + /* _read_2d_message_block_outputs_ */ + /* } */ + /* else */ + /* { */ + /* _read_1d_message_block_outputs_ */ + /* } */ + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0); + + /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */ + /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* 4. If training is required at another frequency, repeat the operations starting at step (E). */ + /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* Step (E) Set the PHY input clocks to the desired frequency for pstate 2 */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + dwc_ddrphy_phyinit_userCustom_E_setDfiClk (2); + + /* */ + /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */ + /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=2, Train2D=0) */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_dmem.incv */ + + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */ +#ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x54000, 0x0); +#else + dwc_ddrphy_apb_wr(0x54000, 0x600); +#endif + dwc_ddrphy_apb_wr(0x54001, 0x0); + dwc_ddrphy_apb_wr(0x54002, 0x102); + dwc_ddrphy_apb_wr(0x54003, 0x64); + dwc_ddrphy_apb_wr(0x54004, 0x2); + dwc_ddrphy_apb_wr(0x54005, 0x0); + dwc_ddrphy_apb_wr(0x54006, 0x25e); + dwc_ddrphy_apb_wr(0x54007, 0x2000); +#ifdef DDR_ONE_RANK + dwc_ddrphy_apb_wr(0x54008, 0x101); + dwc_ddrphy_apb_wr(0x54009, 0x0); +#else + dwc_ddrphy_apb_wr(0x54008, 0x303); + dwc_ddrphy_apb_wr(0x54009, 0x200); +#endif + dwc_ddrphy_apb_wr(0x5400a, 0x0); +#ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x5400b, 0x21f); +#else + dwc_ddrphy_apb_wr(0x5400b, 0x5); +#endif + dwc_ddrphy_apb_wr(0x5400c, 0xc8); + dwc_ddrphy_apb_wr(0x5400d, 0x0); + dwc_ddrphy_apb_wr(0x5400e, 0x0); + dwc_ddrphy_apb_wr(0x5400f, 0x0); + dwc_ddrphy_apb_wr(0x54010, 0x0); + dwc_ddrphy_apb_wr(0x54011, 0x0); + dwc_ddrphy_apb_wr(0x54012, 0x1); + dwc_ddrphy_apb_wr(0x5402f, mr_value[2][0]); + dwc_ddrphy_apb_wr(0x54030, mr_value[2][1]); + dwc_ddrphy_apb_wr(0x54031, mr_value[2][2]); + dwc_ddrphy_apb_wr(0x54032, mr_value[2][3]); + dwc_ddrphy_apb_wr(0x54033, mr_value[2][4]); + dwc_ddrphy_apb_wr(0x54034, mr_value[2][5]); + dwc_ddrphy_apb_wr(0x54035, mr_value[2][6]); + +#ifdef DDR_ONE_RANK + dwc_ddrphy_apb_wr(0x54036, 0x101); +#else + dwc_ddrphy_apb_wr(0x54036, 0x103); +#endif + dwc_ddrphy_apb_wr(0x54037, 0x0); + dwc_ddrphy_apb_wr(0x54038, 0x0); + dwc_ddrphy_apb_wr(0x54039, 0x0); + dwc_ddrphy_apb_wr(0x5403a, 0x0); + dwc_ddrphy_apb_wr(0x5403b, 0x0); + dwc_ddrphy_apb_wr(0x5403c, 0x0); + dwc_ddrphy_apb_wr(0x5403d, 0x0); + dwc_ddrphy_apb_wr(0x5403e, 0x0); + dwc_ddrphy_apb_wr(0x5403f, 0x1221); + dwc_ddrphy_apb_wr(0x541fc, 0x100); + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */ + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + /* This allows the firmware unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (G) Execute the Training Firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */ + /* ResetToMicro fields to 1 (all other fields should be zero). */ + /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */ + dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */ + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */ + dwc_ddrphy_phyinit_userCustom_G_waitFwDone (); + + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */ + /* 4. Halt the microcontroller." */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (H) Read the Message Block results */ + /* */ + /* The procedure is as follows: */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* */ + /* 2. Read the Firmware Message Block to obtain the results from the training. */ + /* This can be accomplished by issuing APB read commands to the DMEM addresses. */ + /* Example: */ + /* if (Train2D) */ + /* { */ + /* _read_2d_message_block_outputs_ */ + /* } */ + /* else */ + /* { */ + /* _read_1d_message_block_outputs_ */ + /* } */ + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0); + + /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */ + /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* 4. If training is required at another frequency, repeat the operations starting at step (E). */ + /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* Step (E) Set the PHY input clocks to the desired frequency for pstate 0 */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0); +#endif /* DDR4_SW_FFC */ + + /* */ + /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */ + /* [dwc_ddrphy_phyinit_D_loadIMEM, 2D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=1) */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (D) Load the 2D IMEM image */ + /* */ + /* This function loads the training firmware IMEM image into the SRAM. */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4_2d/ddr4_2d_pmu_train_imem.incv */ + + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x50000 size 0x4000 */ + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x4000 */ + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + /* This allows the firmware unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_D_loadIMEM, 2D] End of dwc_ddrphy_phyinit_D_loadIMEM() */ + /* [phyinit_F_loadDMEM, 2D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=1) */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (F) Load the 2D DMEM image and write the 2D Message Block parameters for the training firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4_2d/ddr4_2d_pmu_train_dmem.incv */ + + ddr_dbg("C: 1D training done!!! \n"); + + if (Train2D) { + /* for test on silicon, load 2D dmem/imem here */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +#ifdef CONFIG_SPL_VSI_FW_LOADING + load_train_2d_code(); +#else + ddr_load_train_code(FW_2D_IMAGE); +#endif + ddr_dbg("start 2d train\n"); + + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x2d6 */ +#ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x54000, 0x0); +#else + dwc_ddrphy_apb_wr(0x54000, 0x600); +#endif + dwc_ddrphy_apb_wr(0x54001, 0x0); + dwc_ddrphy_apb_wr(0x54002, 0x0); + dwc_ddrphy_apb_wr(0x54003, 0x960); + dwc_ddrphy_apb_wr(0x54004, 0x2); + dwc_ddrphy_apb_wr(0x54005, 0x0); + dwc_ddrphy_apb_wr(0x54006, 0x25e); + dwc_ddrphy_apb_wr(0x54007, 0x2000); +#ifdef DDR_ONE_RANK + dwc_ddrphy_apb_wr(0x54008, 0x101); + dwc_ddrphy_apb_wr(0x54009, 0x0); +#else + dwc_ddrphy_apb_wr(0x54008, 0x303); + dwc_ddrphy_apb_wr(0x54009, 0x200); +#endif + dwc_ddrphy_apb_wr(0x5400a, 0x0); +#ifdef RUN_ON_SILICON + dwc_ddrphy_apb_wr(0x5400b, 0x61); +#else + dwc_ddrphy_apb_wr(0x5400b, 0x1); +#endif + dwc_ddrphy_apb_wr(0x5400c, 0xc8); + dwc_ddrphy_apb_wr(0x5400d, 0x100); + dwc_ddrphy_apb_wr(0x5400e, 0x1f7f); + dwc_ddrphy_apb_wr(0x5400f, 0x0); + dwc_ddrphy_apb_wr(0x54010, 0x0); + dwc_ddrphy_apb_wr(0x54011, 0x0); + dwc_ddrphy_apb_wr(0x54012, 0x1); + dwc_ddrphy_apb_wr(0x5402f, mr_value[0][0]); + dwc_ddrphy_apb_wr(0x54030, mr_value[0][1]); + dwc_ddrphy_apb_wr(0x54031, mr_value[0][2]); + dwc_ddrphy_apb_wr(0x54032, mr_value[0][3]); + dwc_ddrphy_apb_wr(0x54033, mr_value[0][4]); + dwc_ddrphy_apb_wr(0x54034, mr_value[0][5]); + dwc_ddrphy_apb_wr(0x54035, mr_value[0][6]); +#ifdef DDR_ONE_RANK + dwc_ddrphy_apb_wr(0x54036, 0x101); +#else + dwc_ddrphy_apb_wr(0x54036, 0x103); +#endif + dwc_ddrphy_apb_wr(0x54037, 0x0); + dwc_ddrphy_apb_wr(0x54038, 0x0); + dwc_ddrphy_apb_wr(0x54039, 0x0); + dwc_ddrphy_apb_wr(0x5403a, 0x0); + dwc_ddrphy_apb_wr(0x5403b, 0x0); + dwc_ddrphy_apb_wr(0x5403c, 0x0); + dwc_ddrphy_apb_wr(0x5403d, 0x0); + dwc_ddrphy_apb_wr(0x5403e, 0x0); + dwc_ddrphy_apb_wr(0x5403f, 0x1221); + dwc_ddrphy_apb_wr(0x541fc, 0x100); + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x2d6 */ + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + /* This allows the firmware unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [phyinit_F_loadDMEM, 2D] End of dwc_ddrphy_phyinit_F_loadDMEM() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (G) Execute the Training Firmware */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */ + /* ResetToMicro fields to 1 (all other fields should be zero). */ + /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */ + dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* */ + /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */ + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */ + dwc_ddrphy_phyinit_userCustom_G_waitFwDone (); + + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */ + /* 4. Halt the microcontroller." */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (H) Read the Message Block results */ + /* */ + /* The procedure is as follows: */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* */ + /* 2. Read the Firmware Message Block to obtain the results from the training. */ + /* This can be accomplished by issuing APB read commands to the DMEM addresses. */ + /* Example: */ + /* if (Train2D) */ + /* { */ + /* _read_2d_message_block_outputs_ */ + /* } */ + /* else */ + /* { */ + /* _read_1d_message_block_outputs_ */ + /* } */ + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (1); + + /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */ + /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* 4. If training is required at another frequency, repeat the operations starting at step (E). */ + /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */ + /* [phyinit_I_loadPIEImage] Start of dwc_ddrphy_phyinit_I_loadPIEImage() */ + ddr_dbg("2D training done!!!!\n"); + + } /* Train2D */ + } /* !after_retention */ +#ifdef ENABLE_RETENTION + else { /* after_retention */ + restore_1d2d_trained_csr_ddr4_p012(SAVE_DDRPHY_TRAIN_ADDR); + } /* after_retention */ +#endif + + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (I) Load PHY Init Engine Image */ + /* */ + /* Load the PHY Initialization Engine memory with the provided initialization sequence. */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* */ + /* Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */ + /* This allows the memory controller unrestricted access to the configuration CSRs. */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [phyinit_I_loadPIEImage] Programming PIE Production Code */ + dwc_ddrphy_apb_wr(0x90000, 0x10); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90001, 0x400); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90002, 0x10e); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90003, 0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x90004, 0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x90005, 0x8); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x90029, 0xb); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x9002a, 0x480); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x9002b, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x9002c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9002d, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9002e, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x9002f, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */ + dwc_ddrphy_apb_wr(0x90030, 0x478); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */ + dwc_ddrphy_apb_wr(0x90031, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */ + dwc_ddrphy_apb_wr(0x90032, 0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */ + dwc_ddrphy_apb_wr(0x90033, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */ + dwc_ddrphy_apb_wr(0x90034, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */ + dwc_ddrphy_apb_wr(0x90035, 0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */ + dwc_ddrphy_apb_wr(0x90036, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */ + dwc_ddrphy_apb_wr(0x90037, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */ + dwc_ddrphy_apb_wr(0x90038, 0x44); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */ + dwc_ddrphy_apb_wr(0x90039, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */ + dwc_ddrphy_apb_wr(0x9003a, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */ + dwc_ddrphy_apb_wr(0x9003b, 0x14f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */ + dwc_ddrphy_apb_wr(0x9003c, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */ + dwc_ddrphy_apb_wr(0x9003d, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */ + dwc_ddrphy_apb_wr(0x9003e, 0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */ + dwc_ddrphy_apb_wr(0x9003f, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */ + dwc_ddrphy_apb_wr(0x90040, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */ + dwc_ddrphy_apb_wr(0x90041, 0x4f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */ + dwc_ddrphy_apb_wr(0x90042, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */ + dwc_ddrphy_apb_wr(0x90043, 0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */ + dwc_ddrphy_apb_wr(0x90044, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */ + dwc_ddrphy_apb_wr(0x90045, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */ + dwc_ddrphy_apb_wr(0x90046, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */ + dwc_ddrphy_apb_wr(0x90047, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */ + dwc_ddrphy_apb_wr(0x90048, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */ + dwc_ddrphy_apb_wr(0x90049, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */ + dwc_ddrphy_apb_wr(0x9004a, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */ + dwc_ddrphy_apb_wr(0x9004b, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */ + dwc_ddrphy_apb_wr(0x9004c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */ + dwc_ddrphy_apb_wr(0x9004d, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */ + dwc_ddrphy_apb_wr(0x9004e, 0x45a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */ + dwc_ddrphy_apb_wr(0x9004f, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */ + dwc_ddrphy_apb_wr(0x90050, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */ + dwc_ddrphy_apb_wr(0x90051, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */ + dwc_ddrphy_apb_wr(0x90052, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */ + dwc_ddrphy_apb_wr(0x90053, 0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */ + dwc_ddrphy_apb_wr(0x90054, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */ + dwc_ddrphy_apb_wr(0x90055, 0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */ + dwc_ddrphy_apb_wr(0x90056, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */ + dwc_ddrphy_apb_wr(0x90057, 0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */ + dwc_ddrphy_apb_wr(0x90058, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */ + dwc_ddrphy_apb_wr(0x90059, 0x40c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */ + dwc_ddrphy_apb_wr(0x9005a, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */ + dwc_ddrphy_apb_wr(0x9005b, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */ + dwc_ddrphy_apb_wr(0x9005c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */ + dwc_ddrphy_apb_wr(0x9005d, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */ + dwc_ddrphy_apb_wr(0x9005e, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */ + dwc_ddrphy_apb_wr(0x9005f, 0x4040); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */ + dwc_ddrphy_apb_wr(0x90060, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */ + dwc_ddrphy_apb_wr(0x90061, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */ + dwc_ddrphy_apb_wr(0x90062, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */ + dwc_ddrphy_apb_wr(0x90063, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */ + dwc_ddrphy_apb_wr(0x90064, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */ + dwc_ddrphy_apb_wr(0x90065, 0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */ + dwc_ddrphy_apb_wr(0x90066, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */ + dwc_ddrphy_apb_wr(0x90067, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */ + dwc_ddrphy_apb_wr(0x90068, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */ + dwc_ddrphy_apb_wr(0x90069, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */ + dwc_ddrphy_apb_wr(0x9006a, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */ + dwc_ddrphy_apb_wr(0x9006b, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */ + dwc_ddrphy_apb_wr(0x9006c, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */ + dwc_ddrphy_apb_wr(0x9006d, 0x78); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */ + dwc_ddrphy_apb_wr(0x9006e, 0x549); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */ + dwc_ddrphy_apb_wr(0x9006f, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */ + dwc_ddrphy_apb_wr(0x90070, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */ + dwc_ddrphy_apb_wr(0x90071, 0xd49); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */ + dwc_ddrphy_apb_wr(0x90072, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */ + dwc_ddrphy_apb_wr(0x90073, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */ + dwc_ddrphy_apb_wr(0x90074, 0x94a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */ + dwc_ddrphy_apb_wr(0x90075, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */ + dwc_ddrphy_apb_wr(0x90076, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */ + dwc_ddrphy_apb_wr(0x90077, 0x441); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */ + dwc_ddrphy_apb_wr(0x90078, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */ + dwc_ddrphy_apb_wr(0x90079, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */ + dwc_ddrphy_apb_wr(0x9007a, 0x42); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */ + dwc_ddrphy_apb_wr(0x9007b, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */ + dwc_ddrphy_apb_wr(0x9007c, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */ + dwc_ddrphy_apb_wr(0x9007d, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */ + dwc_ddrphy_apb_wr(0x9007e, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */ + dwc_ddrphy_apb_wr(0x9007f, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */ + dwc_ddrphy_apb_wr(0x90080, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */ + dwc_ddrphy_apb_wr(0x90081, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */ + dwc_ddrphy_apb_wr(0x90082, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */ + dwc_ddrphy_apb_wr(0x90083, 0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */ + dwc_ddrphy_apb_wr(0x90084, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */ + dwc_ddrphy_apb_wr(0x90085, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */ + dwc_ddrphy_apb_wr(0x90086, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */ + dwc_ddrphy_apb_wr(0x90087, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */ + dwc_ddrphy_apb_wr(0x90088, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */ + dwc_ddrphy_apb_wr(0x90089, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */ + dwc_ddrphy_apb_wr(0x9008a, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */ + dwc_ddrphy_apb_wr(0x9008b, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */ + dwc_ddrphy_apb_wr(0x9008c, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */ + dwc_ddrphy_apb_wr(0x9008d, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */ + dwc_ddrphy_apb_wr(0x9008e, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */ + dwc_ddrphy_apb_wr(0x9008f, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */ + dwc_ddrphy_apb_wr(0x90090, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */ + dwc_ddrphy_apb_wr(0x90091, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */ + dwc_ddrphy_apb_wr(0x90092, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */ + dwc_ddrphy_apb_wr(0x90093, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */ + dwc_ddrphy_apb_wr(0x90094, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */ + dwc_ddrphy_apb_wr(0x90095, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */ + dwc_ddrphy_apb_wr(0x90096, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */ + dwc_ddrphy_apb_wr(0x90097, 0x58); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */ + dwc_ddrphy_apb_wr(0x90098, 0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */ + dwc_ddrphy_apb_wr(0x90099, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */ + dwc_ddrphy_apb_wr(0x9009a, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */ + dwc_ddrphy_apb_wr(0x9009b, 0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */ + dwc_ddrphy_apb_wr(0x9009c, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */ + dwc_ddrphy_apb_wr(0x9009d, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */ + dwc_ddrphy_apb_wr(0x9009e, 0x7); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */ + dwc_ddrphy_apb_wr(0x9009f, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */ + dwc_ddrphy_apb_wr(0x900a0, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */ + dwc_ddrphy_apb_wr(0x900a1, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */ + dwc_ddrphy_apb_wr(0x900a2, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */ + dwc_ddrphy_apb_wr(0x900a3, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */ + dwc_ddrphy_apb_wr(0x900a4, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */ + dwc_ddrphy_apb_wr(0x900a5, 0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */ + dwc_ddrphy_apb_wr(0x900a6, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */ + dwc_ddrphy_apb_wr(0x900a7, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */ + dwc_ddrphy_apb_wr(0x900a8, 0x8138); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */ + dwc_ddrphy_apb_wr(0x900a9, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */ + dwc_ddrphy_apb_wr(0x900aa, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */ + dwc_ddrphy_apb_wr(0x900ab, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */ + dwc_ddrphy_apb_wr(0x900ac, 0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */ + dwc_ddrphy_apb_wr(0x900ad, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */ + dwc_ddrphy_apb_wr(0x900ae, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */ + dwc_ddrphy_apb_wr(0x900af, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */ + dwc_ddrphy_apb_wr(0x900b0, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */ + dwc_ddrphy_apb_wr(0x900b1, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */ + dwc_ddrphy_apb_wr(0x900b2, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */ + dwc_ddrphy_apb_wr(0x900b3, 0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */ + dwc_ddrphy_apb_wr(0x900b4, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */ + dwc_ddrphy_apb_wr(0x900b5, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */ + dwc_ddrphy_apb_wr(0x900b6, 0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */ + dwc_ddrphy_apb_wr(0x900b7, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */ + dwc_ddrphy_apb_wr(0x900b8, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */ + dwc_ddrphy_apb_wr(0x900b9, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */ + dwc_ddrphy_apb_wr(0x900ba, 0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */ + dwc_ddrphy_apb_wr(0x900bb, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */ + dwc_ddrphy_apb_wr(0x900bc, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */ + dwc_ddrphy_apb_wr(0x900bd, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */ + dwc_ddrphy_apb_wr(0x900be, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */ + dwc_ddrphy_apb_wr(0x900bf, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */ + dwc_ddrphy_apb_wr(0x900c0, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */ + dwc_ddrphy_apb_wr(0x900c1, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */ + dwc_ddrphy_apb_wr(0x900c2, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */ + dwc_ddrphy_apb_wr(0x900c3, 0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */ + dwc_ddrphy_apb_wr(0x900c4, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */ + dwc_ddrphy_apb_wr(0x900c5, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */ + dwc_ddrphy_apb_wr(0x900c6, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */ + dwc_ddrphy_apb_wr(0x900c7, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */ + dwc_ddrphy_apb_wr(0x900c8, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */ + dwc_ddrphy_apb_wr(0x900c9, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */ + dwc_ddrphy_apb_wr(0x900ca, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */ + dwc_ddrphy_apb_wr(0x900cb, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */ + dwc_ddrphy_apb_wr(0x900cc, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */ + dwc_ddrphy_apb_wr(0x900cd, 0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */ + dwc_ddrphy_apb_wr(0x90006, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90007, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90008, 0x8); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90009, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9000a, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9000b, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0xd00e7, 0x400); /* DWC_DDRPHYA_APBONLY0_SequencerOverride */ + dwc_ddrphy_apb_wr(0x90017, 0x0); /* DWC_DDRPHYA_INITENG0_StartVector0b0 */ + dwc_ddrphy_apb_wr(0x90026, 0x2c); /* DWC_DDRPHYA_INITENG0_StartVector0b15 */ + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY0 to 0x4b */ + dwc_ddrphy_apb_wr(0x2000b, 0x4b); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */ + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY1 to 0x96 */ + dwc_ddrphy_apb_wr(0x2000c, 0x96); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */ + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY2 to 0x5dc */ + dwc_ddrphy_apb_wr(0x2000d, 0x5dc); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */ + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY3 to 0x2c */ + dwc_ddrphy_apb_wr(0x2000e, 0x2c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */ + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY0 to 0xc */ + dwc_ddrphy_apb_wr(0x12000b, 0xc); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */ + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY1 to 0x19 */ + dwc_ddrphy_apb_wr(0x12000c, 0x19); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */ + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY2 to 0xfa */ + dwc_ddrphy_apb_wr(0x12000d, 0xfa); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */ + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY3 to 0x10 */ + dwc_ddrphy_apb_wr(0x12000e, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */ + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY0 to 0x3 */ + dwc_ddrphy_apb_wr(0x22000b, 0x3); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */ + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY1 to 0x6 */ + dwc_ddrphy_apb_wr(0x22000c, 0x6); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */ + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY2 to 0x3e */ + dwc_ddrphy_apb_wr(0x22000d, 0x3e); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */ + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY3 to 0x10 */ + dwc_ddrphy_apb_wr(0x22000e, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */ + dwc_ddrphy_apb_wr(0x9000c, 0x0); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */ + dwc_ddrphy_apb_wr(0x9000d, 0x173); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */ + dwc_ddrphy_apb_wr(0x9000e, 0x60); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */ + dwc_ddrphy_apb_wr(0x9000f, 0x6110); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */ + dwc_ddrphy_apb_wr(0x90010, 0x2152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */ + dwc_ddrphy_apb_wr(0x90011, 0xdfbd); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */ + dwc_ddrphy_apb_wr(0x90012, 0xffff); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */ + dwc_ddrphy_apb_wr(0x90013, 0x6152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */ + /* Disabling Ucclk (PMU) and Hclk (training hardware) */ + dwc_ddrphy_apb_wr(0xc0080, 0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + /* Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + /* [phyinit_I_loadPIEImage] End of dwc_ddrphy_phyinit_I_loadPIEImage() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* dwc_ddrphy_phyinit_userCustom_customPostTrain is a user-editable function. */ + /* */ + /* See PhyInit App Note for detailed description and function usage */ + /* */ + /* ############################################################## */ + /* */ + dwc_ddrphy_phyinit_userCustom_customPostTrain (); + + /* [dwc_ddrphy_phyinit_userCustom_customPostTrain] End of dwc_ddrphy_phyinit_userCustom_customPostTrain() */ + /* [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] Start of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() */ + /* */ + /* */ + /* ############################################################## */ + /* */ + /* (J) Initialize the PHY to Mission Mode through DFI Initialization */ + /* */ + /* Initialize the PHY to mission mode as follows: */ + /* */ + /* 1. Set the PHY input clocks to the desired frequency. */ + /* 2. Initialize the PHY to mission mode by performing DFI Initialization. */ + /* Please see the DFI specification for more information. See the DFI frequency bus encoding in section . */ + /* Note: The PHY training firmware initializes the DRAM state. if skip */ + /* training is used, the DRAM state is not initialized. */ + /* */ + /* ############################################################## */ + /* */ + dwc_ddrphy_phyinit_userCustom_J_enterMissionMode (); + + /* */ + /* [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] End of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() */ + /* [dwc_ddrphy_phyinit_sequence] End of dwc_ddrphy_phyinit_sequence() */ + /* [dwc_ddrphy_phyinit_main] End of dwc_ddrphy_phyinit_main() */ + + /* ---------------------------------------------------------------------- */ + /* save 1d2d training CSR */ + /* ---------------------------------------------------------------------- */ +#ifdef ENABLE_RETENTION + if (!after_retention) { + save_1d2d_trained_csr_ddr4_p012(SAVE_DDRPHY_TRAIN_ADDR); + } +#endif +} diff --git a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_task.c b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_task.c new file mode 100644 index 00000000000..af7dab0812c --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_task.c @@ -0,0 +1,79 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "ddr4_define.h" + +extern unsigned int mr_value[3][7]; +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk (unsigned int pstate) { + if (pstate == 1) { + ddr_dbg("C: pstate1 ...\n"); +#ifdef PLLBYPASS_250MBPS + dram_enable_bypass(DRAM_BYPASSCLK_250M); +#endif +#ifdef PLLBYPASS_400MBPS + dram_enable_bypass(DRAM_BYPASSCLK_400M); +#endif + } else if (pstate == 2) { + ddr_dbg("C: pstate2 ...\n"); + dram_enable_bypass(DRAM_BYPASSCLK_100M); + } else { + ddr_dbg("C: pstate0 ...\n"); + dram_pll_init(DRAM_PLL_OUT_600M); + dram_disable_bypass(); + } +} + +void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void) +{ + wait_ddrphy_training_complete(); +} +void dwc_ddrphy_phyinit_userCustom_overrideUserInput (void) {} +void dwc_ddrphy_phyinit_userCustom_A_bringupPower (void) {} +void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy (void) {} +void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned int Train2D) {} +void dwc_ddrphy_phyinit_userCustom_customPostTrain(void) {} +void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void) {} + +void ddr4_mr_write(unsigned int mr, unsigned int data, unsigned int read, unsigned int rank) +{ + unsigned int tmp, mr_mirror, data_mirror; + + /* 1. Poll MRSTAT.mr_wr_busy until it is 0. This checks that there is no outstanding MR transaction. No */ + /* writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1. */ + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + + /* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and (for MRWs) */ + /* MRCTRL1.mr_data to define the MR transaction. */ + /* (A3, A4), (A5, A6), (A7, A8), (BA0, BA1), (A11, A13), */ + tmp = reg32_read(DDRC_DIMMCTL(0)); + if ((tmp & 0x2) && (rank == 0x2)) { + mr_mirror = (mr & 0x4) | ((mr & 0x1) << 1) | ((mr & 0x2) >> 1);/* BA0, BA1 swap */ + data_mirror = (data & 0x1607) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | ((data & 0x20) << 1) | + ((data & 0x40) >> 1) | ((data & 0x80) << 1) | ((data & 0x100) >> 1) | ((data & 0x800) << 2) | ((data & 0x2000) >> 2) ; + } else { + mr_mirror = mr; + data_mirror = data; + } + + reg32_write(DDRC_MRCTRL0(0), read | (mr_mirror << 12) | (rank << 4)); + reg32_write(DDRC_MRCTRL1(0), data_mirror); + + /* 3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1. This bit is self-clearing, and triggers */ + /* the MR transaction. The uMCTL2 then asserts the MRSTAT.mr_wr_busy while it performs the MR */ + /* transaction to SDRAM, and no further accesses can be initiated until it is deasserted. */ + reg32setbit(DDRC_MRCTRL0(0), 31); + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp); + +} diff --git a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_swffc_fw09.c b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_swffc_fw09.c new file mode 100644 index 00000000000..b8a05b9b2ef --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_swffc_fw09.c @@ -0,0 +1,599 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "anamix_common.h" +#include "ddr4_define.h" + +unsigned int mr_value[3][7] = { + {0xa34, 0x105, 0x1028, 0x240, 0x200, 0x200, 0x814}, /* pstate0 MR */ + {0x204, 0x104, 0x1000, 0x040, 0x200, 0x200, 0x014}, /* pstate1 MR */ + {0x204, 0x104, 0x1000, 0x040, 0x200, 0x200, 0x014} }; /* pstate2 MR */ + +static unsigned int cur_pstate; +unsigned int after_retention = 0; + +void ddr4_dll_change(unsigned int pstate); +void ddr4_dll_no_change(unsigned int pstate); + +void umctl2_cfg(void) +{ +#ifdef DDR_ONE_RANK + reg32_write(DDRC_MSTR(0), 0x81040010); +#else + reg32_write(DDRC_MSTR(0), 0x83040010); +#endif + + reg32_write(DDRC_PWRCTL(0), 0x000000aa); + reg32_write(DDRC_PWRTMG(0), 0x00221306); + + reg32_write(DDRC_RFSHCTL0(0), 0x00c0a070); + reg32_write(DDRC_RFSHCTL1(0), 0x00010008); + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); + reg32_write(DDRC_RFSHTMG(0), 0x004980f4); + reg32_write(DDRC_CRCPARCTL0(0), 0x00000000); + reg32_write(DDRC_CRCPARCTL1(0), 0x00001010); + reg32_write(DDRC_INIT0(0), 0xc0030002); + reg32_write(DDRC_INIT1(0), 0x00020009); + reg32_write(DDRC_INIT2(0), 0x0000350f); + reg32_write(DDRC_INIT3(0), (mr_value[0][0]<<16) | (mr_value[0][1])); + reg32_write(DDRC_INIT4(0), (mr_value[0][2]<<16) | (mr_value[0][3])); + reg32_write(DDRC_INIT5(0), 0x001103cb); + reg32_write(DDRC_INIT6(0), (mr_value[0][4]<<16) | (mr_value[0][5])); + reg32_write(DDRC_INIT7(0), mr_value[0][6]); + reg32_write(DDRC_DIMMCTL(0), 0x00000032); + reg32_write(DDRC_RANKCTL(0), 0x00000fc7); + reg32_write(DDRC_DRAMTMG0(0), 0x14132813); + reg32_write(DDRC_DRAMTMG1(0), 0x0004051b); + reg32_write(DDRC_DRAMTMG2(0), 0x0808030f); + reg32_write(DDRC_DRAMTMG3(0), 0x0000400c); + reg32_write(DDRC_DRAMTMG4(0), 0x08030409); + reg32_write(DDRC_DRAMTMG5(0), 0x0e090504); + reg32_write(DDRC_DRAMTMG6(0), 0x05030000); + reg32_write(DDRC_DRAMTMG7(0), 0x0000090e); + reg32_write(DDRC_DRAMTMG8(0), 0x0606700c); + reg32_write(DDRC_DRAMTMG9(0), 0x0002040c); + reg32_write(DDRC_DRAMTMG10(0), 0x000f0c07); + reg32_write(DDRC_DRAMTMG11(0), 0x1809011d); + reg32_write(DDRC_DRAMTMG12(0), 0x0000000d); + reg32_write(DDRC_DRAMTMG13(0), 0x2b000000); + reg32_write(DDRC_DRAMTMG14(0), 0x000000a4); + reg32_write(DDRC_DRAMTMG15(0), 0x00000000); + reg32_write(DDRC_DRAMTMG17(0), 0x00250078); + reg32_write(DDRC_ZQCTL0(0), 0x51000040); + reg32_write(DDRC_ZQCTL1(0), 0x00000070); + reg32_write(DDRC_ZQCTL2(0), 0x00000000); + reg32_write(DDRC_DFITMG0(0), 0x038b820b); + reg32_write(DDRC_DFITMG1(0), 0x02020103); + reg32_write(DDRC_DFILPCFG0(0), 0x07f04011); /* [8]dfi_lp_en_sr = 0 */ + reg32_write(DDRC_DFILPCFG1(0), 0x000000b0); + reg32_write(DDRC_DFIUPD0(0), 0xe0400018); + reg32_write(DDRC_DFIUPD1(0), 0x0048005a); + reg32_write(DDRC_DFIUPD2(0), 0x80000000); + reg32_write(DDRC_DFIMISC(0), 0x00000001); + reg32_write(DDRC_DFITMG2(0), 0x00000b0b); + reg32_write(DDRC_DFITMG3(0), 0x00000001); + reg32_write(DDRC_DBICTL(0), 0x00000000); + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000); + +#ifdef DDR_ONE_RANK + reg32_write(DDRC_ADDRMAP0(0), 0x0000001F); +#else + reg32_write(DDRC_ADDRMAP0(0), 0x00000017); /* [4:0]cs0: 6+23 */ +#endif + reg32_write(DDRC_ADDRMAP1(0), 0x003F0909); /* [5:0] bank b0: 2+9; [13:8] b1: P3+9 ; [21:16] b2: 4+, unused */ + reg32_write(DDRC_ADDRMAP2(0), 0x01010100); /* [3:0] col-b2: 2; [11:8] col-b3: 3+1; [19:16] col-b4: 4+1 ; [27:24] col-b5: 5+1 */ + reg32_write(DDRC_ADDRMAP3(0), 0x01010101); /* [3:0] col-b6: 6+1; [11:8] col-b7: 7+1; [19:16] col-b8: 8+1 ; [27:24] col-b9: 9+1 */ + reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */ + reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6+7; [11:8] row-b1: 7+7; [19:16] row-b2_b10: 8~16+7; [27:24] row-b11: 17+7 */ + reg32_write(DDRC_ADDRMAP6(0), 0x07070707); /* [3:0] row-b12:18+7; [11:8] row-b13: 19+7; [19:16] row-b14:20+7; [27:24] row-b15: 21+7 */ + reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f); /* col-b10, col-b11 not used */ + reg32_write(DDRC_ADDRMAP8(0), 0x00003F01); /* [5:0] bg-b0: 2+1; [13:8]bg-b1:3+, unused */ + reg32_write(DDRC_ADDRMAP9(0), 0x0a020b06); /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP10(0), 0x0a0a0a0a);/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP11(0), 0x00000000); + + /* FREQ0: BL8, CL=16, CWL=16, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1, so wr_odt_hold=5+1+1=7 */ + /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */ + reg32_write(DDRC_ODTCFG(0), 0x07000600); +#ifdef DDR_ONE_RANK + reg32_write(DDRC_ODTMAP(0), 0x0001); +#else + reg32_write(DDRC_ODTMAP(0), 0x0201);/* disable ODT0x00001120); */ +#endif + reg32_write(DDRC_SCHED(0), 0x317d1a07); + reg32_write(DDRC_SCHED1(0), 0x0000000f); + reg32_write(DDRC_PERFHPR1(0), 0x2a001b76); + reg32_write(DDRC_PERFLPR1(0), 0x7300b473); + reg32_write(DDRC_PERFWR1(0), 0x30000e06); + reg32_write(DDRC_DBG0(0), 0x00000014); + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_DBGCMD(0), 0x00000000); + reg32_write(DDRC_SWCTL(0), 0x00000001); + reg32_write(DDRC_POISONCFG(0), 0x00000010); + reg32_write(DDRC_PCCFG(0), 0x00000100);/* bl_exp_mode=1 */ + reg32_write(DDRC_PCFGR_0(0), 0x00013193); + reg32_write(DDRC_PCFGW_0(0), 0x00006096); + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + reg32_write(DDRC_PCFGQOS0_0(0), 0x02000c00); + reg32_write(DDRC_PCFGQOS1_0(0), 0x003c00db); + reg32_write(DDRC_PCFGWQOS0_0(0), 0x00100009); + reg32_write(DDRC_PCFGWQOS1_0(0), 0x00000002); + +} + +void umctl2_freq1_cfg(void) +{ + reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0021a0c0); +#ifdef PLLBYPASS_250MBPS + reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x000f0011);/* tREFI=7.8us */ +#endif +#ifdef PLLBYPASS_400MBPS + reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x0018001a);/* tREFI=7.8us */ +#endif + + reg32_write(DDRC_FREQ1_INIT3(0), (mr_value[1][0]<<16) | (mr_value[1][1])); + reg32_write(DDRC_FREQ1_INIT4(0), (mr_value[1][2]<<16) | (mr_value[1][3])); + reg32_write(DDRC_FREQ1_INIT6(0), (mr_value[1][4]<<16) | (mr_value[1][5])); + reg32_write(DDRC_FREQ1_INIT7(0), mr_value[1][6]); +#ifdef PLLBYPASS_250MBPS + reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0403);/* t_ras_max=9*7.8us, t_ras_min=35ns */ +#endif +#ifdef PLLBYPASS_400MBPS + reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0604);/* t_ras_max=9*7.8us, t_ras_min=35ns */ +#endif + reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030314); + reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0505040a); + reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x0000400c); + reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x06040307); /* tRP=6 --> 7 */ + reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x090d0202); + reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a070008); + reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x00000d09); + reg32_write(DDRC_FREQ1_DRAMTMG8(0), 0x08084b09); + reg32_write(DDRC_FREQ1_DRAMTMG9(0), 0x00020308); + reg32_write(DDRC_FREQ1_DRAMTMG10(0), 0x000f0d06); + reg32_write(DDRC_FREQ1_DRAMTMG11(0), 0x12060111); + reg32_write(DDRC_FREQ1_DRAMTMG12(0), 0x00000008); + reg32_write(DDRC_FREQ1_DRAMTMG13(0), 0x21000000); + reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000000); + reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000); + reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x00c6007d); + reg32_write(DDRC_FREQ1_ZQCTL0(0), 0x51000040); + reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03858204); + reg32_write(DDRC_FREQ1_DFITMG1(0), 0x00020103); + reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000504); + reg32_write(DDRC_FREQ1_DFITMG3(0), 0x00000001); + /* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */ + /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */ + reg32_write(DDRC_FREQ1_ODTCFG(0), 0x07000601); +} + +void umctl2_freq2_cfg(void) +{ + reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0021a0c0); + reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0006000e);/* tREFI=7.8us */ + reg32_write(DDRC_FREQ2_INIT3(0), (mr_value[2][0]<<16) | (mr_value[2][1])); + reg32_write(DDRC_FREQ2_INIT4(0), (mr_value[2][2]<<16) | (mr_value[2][3])); + reg32_write(DDRC_FREQ2_INIT6(0), (mr_value[2][4]<<16) | (mr_value[2][5])); + reg32_write(DDRC_FREQ2_INIT7(0), mr_value[2][6]); + reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0c0e0101);/* t_ras_max=9*7.8us, t_ras_min=35ns */ + reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030314); + reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0505040a); + reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x0000400c); + reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x06040307); /* tRP=6 --> 7 */ + reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x090d0202); + reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a070008); + reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x00000d09); + reg32_write(DDRC_FREQ2_DRAMTMG8(0), 0x08084b09); + reg32_write(DDRC_FREQ2_DRAMTMG9(0), 0x00020308); + reg32_write(DDRC_FREQ2_DRAMTMG10(0), 0x000f0d06); + reg32_write(DDRC_FREQ2_DRAMTMG11(0), 0x12060111); + reg32_write(DDRC_FREQ2_DRAMTMG12(0), 0x00000008); + reg32_write(DDRC_FREQ2_DRAMTMG13(0), 0x21000000); + reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000000); + reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000); + reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x00c6007d); + reg32_write(DDRC_FREQ2_ZQCTL0(0), 0x51000040); + reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03858204); + reg32_write(DDRC_FREQ2_DFITMG1(0), 0x00020103); + reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000504); + reg32_write(DDRC_FREQ2_DFITMG3(0), 0x00000001); + /* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */ + /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */ + reg32_write(DDRC_FREQ2_ODTCFG(0), 0x07000601); +} + + +void ddr4_pub_train(void) +{ + volatile unsigned int tmp_t; + after_retention = 0; + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); /* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, [4]src_system_rst_b! */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); /* deassert [4]src_system_rst_b! */ + + /* change the clock source of dram_apb_clk_root */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); /* to source 4 --800MHz/4 */ + + /* DDR_PLL_CONFIG_600MHz(); */ + dram_pll_init(DRAM_PLL_OUT_600M); + ddr_dbg("C: dram pll init finished\n"); + + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5);/* PU_PGC_SW_PUP_REQ */ + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */ + + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + + while (0 != (0x7 & reg32_read(DDRC_STAT(0)))) + ; + + ddr_dbg("C: cfg umctl2 regs ...\n"); + umctl2_cfg(); +#ifdef DDR4_SW_FFC + umctl2_freq1_cfg(); + umctl2_freq2_cfg(); +#endif + + reg32_write(DDRC_RFSHCTL3(0), 0x00000011); + /* RESET: DEASSERTED */ + /* RESET: 0; i--) + ; + ddr_dbg("C: waiting for 2*tREFI (2*7.8us)\n"); + + /* 14. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0. */ + reg32clrbit(DDRC_PWRCTL(0), 5); + do { + tmp = 0x3f & (reg32_read((DDRC_STAT(0)))); + ddr_dbg("C: waiting for exit Self Refresh\n"); + } while (tmp == 0x23); +} + +void ddr4_dll_change(unsigned int pstate) +{ + volatile unsigned int tmp; + enum DLL_STATE { NO_CHANGE = 0, ON2OFF = 1, OFF2ON = 2} dll_sw; /* 0-no change, 1-on2off, 2-off2on.; */ + + if (pstate != 0 && cur_pstate == 0) { + dll_sw = ON2OFF; + ddr_dbg("dll ON2OFF\n"); + } else if (pstate == 0 && cur_pstate != 0) { + dll_sw = OFF2ON; + ddr_dbg("dll OFF2ON\n"); + } else { + dll_sw = NO_CHANGE; + } + + /* the the following software programming sequence to switch from DLL-on to DLL-off, or reverse: */ + reg32_write(DDRC_SWCTL(0), 0x0000); + + /* 1. Set the DBG1.dis_hif = 1. This prevents further reads/writes being received on the HIF. */ + reg32setbit(DDRC_DBG1(0), 1); + /* 2. Set ZQCTL0.dis_auto_zq=1, to disable automatic generation of ZQCS/MPC(ZQ calibration) */ + /* commands */ + if (pstate == 1) + reg32setbit(DDRC_FREQ1_ZQCTL0(0), 31); + else if (pstate == 2) + reg32setbit(DDRC_FREQ2_ZQCTL0(0), 31); + else + reg32setbit(DDRC_ZQCTL0(0), 31); + + /* 3. Set RFSHCTL3.dis_auto_refresh=1, to disable automatic refreshes */ + reg32setbit(DDRC_RFSHCTL3(0), 0); + /* 4. Ensure all commands have been flushed from the uMCTL2 by polling */ + /* DBGCAM.wr_data_pipeline_empty, DBGCAM.rd_data_pipeline_empty1, */ + /* DBGCAM.dbg_wr_q_depth, DBGCAM.dbg_lpr_q_depth, DBGCAM.dbg_rd_q_empty, */ + /* DBGCAM.dbg_wr_q_empty. */ + do { + tmp = 0x06000000 & reg32_read(DDRC_DBGCAM(0)); + } while (tmp != 0x06000000); + reg32_write(DDRC_PCTRL_0(0), 0x00000000); + /* 5. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to disable RTT_NOM: */ + /* a. DDR3: Write 0 to MR1[9], MR1[6] and MR1[2] */ + /* b. DDR4: Write 0 to MR1[10:8] */ + if (mr_value[pstate][1] & 0x700) { + ddr4_mr_write(1, mr_value[pstate][1] & 0xF8FF, 0, 0x1); +#ifndef DDR_ONE_RANK + ddr4_mr_write(1, mr_value[pstate][1] & 0xF8FF, 0, 0x2); +#endif + } + /* 6. For DDR4 only: Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to write 0 to */ + /* MR5[8:6] to disable RTT_PARK */ + if (mr_value[pstate][5] & 0x1C0) { + ddr4_mr_write(5, mr_value[pstate][5] & 0xFE3F, 0, 0x1); +#ifndef DDR_ONE_RANK + ddr4_mr_write(5, mr_value[pstate][5] & 0xFE3F, 0, 0x2); +#endif + } + + if (dll_sw == ON2OFF) { + /* 7. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to write 0 to MR2[11:9], to */ + /* disable RTT_WR (and therefore disable dynamic ODT). This applies for both DDR3 and DDR4. */ + if (mr_value[pstate][2] & 0xE00) { + ddr4_mr_write(2, mr_value[pstate][2] & 0xF1FF, 0, 0x1); +#ifndef DDR_ONE_RANK + ddr4_mr_write(2, mr_value[pstate][2] & 0xF1FF, 0, 0x2); +#endif + } + /* 8. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to disable the DLL. The */ + /* timing of this MRS is automatically handled by the uMCTL2. */ + /* a. DDR3: Write 1 to MR1[0] */ + /* b. DDR4: Write 0 to MR1[0] */ + ddr4_mr_write(1, mr_value[pstate][1] & 0xFFFE, 0, 0x1); +#ifndef DDR_ONE_RANK + ddr4_mr_write(1, mr_value[pstate][1] & 0xFFFE, 0, 0x2); +#endif + } + + /* 9. Put the SDRAM into self-refresh mode by setting PWRCTL.selfref_sw = 1, and polling */ + /* STAT.operating_mode to ensure the DDRC has entered self-refresh. */ + reg32setbit(DDRC_PWRCTL(0), 5); + /* 10. Wait until STAT.operating_mode[1:0]==11 indicating that the DWC_ddr_umctl2 core is in selfrefresh mode. Ensure transition to self-refresh was due to software by checking that */ + /* STAT.selfref_type[1:0]=2`b10. */ + do { + tmp = 0x3f & (reg32_read((DDRC_STAT(0)))); + ddr_dbg("C: wait DRAM in Self Refresh\n"); + } while (tmp != 0x23); + + /* 11. Set the MSTR.dll_off_mode = 1 or 0. */ + if (dll_sw == ON2OFF) + reg32setbit(DDRC_MSTR(0), 15); + + if (dll_sw == OFF2ON) + reg32clrbit(DDRC_MSTR(0), 15); + + sw_pstate(pstate); + + /* DRAM dll enable */ + if (dll_sw == OFF2ON) { + ddr4_mr_write(1, mr_value[pstate][1] | 0x1, 0, 0x1); +#ifndef DDR_ONE_RANK + ddr4_mr_write(1, mr_value[pstate][1] | 0x1, 0, 0x2); +#endif + /* DRAM dll reset, self-clear */ + ddr4_mr_write(0, mr_value[pstate][0] | 0x100, 0, 0x1); +#ifndef DDR_ONE_RANK + ddr4_mr_write(0, mr_value[pstate][0] | 0x100, 0, 0x2); +#endif + } + + dram_all_mr_cfg(pstate); + + /* 16. Re-enable automatic generation of ZQCS/MPC(ZQ calibration) commands, by setting */ + /* ZQCTL0.dis_auto_zq=0 if they were previously disabled */ + if (pstate == 1) + reg32clrbit(DDRC_FREQ1_ZQCTL0(0), 31); + else if (pstate == 2) + reg32clrbit(DDRC_FREQ2_ZQCTL0(0), 31); + else + reg32clrbit(DDRC_ZQCTL0(0), 31); + + /* 17. Re-enable automatic refreshes (RFSHCTL3.dis_auto_refresh = 0) if they have been previously */ + /* disabled. */ + reg32clrbit(DDRC_RFSHCTL3(0), 0); + /* 18. Restore ZQCTL0.dis_srx_zqcl */ + /* 19. Write DBG1.dis_hif = 0 to re-enable reads and writes. */ + reg32clrbit(DDRC_DBG1(0), 1); + + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + /* 27. Write 1 to SBRCTL.scrub_en. Enable SBR if desired, only required if SBR instantiated. */ + + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */ + reg32_write(DDRC_SWCTL(0), 0x0001); + + /* wait SWSTAT.sw_done_ack to 1 */ + do { + tmp = 0x1 & reg32_read(DDRC_SWSTAT(0)); + } while (!tmp); +} + +void ddr4_dll_no_change(unsigned int pstate) +{ + volatile unsigned int tmp; + /* ------------------------------------------------------------------------------------- */ + /* change to pstate1 */ + /* ------------------------------------------------------------------------------------- */ + /* 1. Program one of UMCTL2_REGS_FREQ1/2/3, whichever you prefer, timing register-set with the */ + /* timing settings required for the alternative clock frequency. */ + /* set SWCTL.sw_done to disable quasi-dynamic register programming outside reset. */ + reg32_write(DDRC_SWCTL(0), 0x0000); + + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */ + /* wait SWSTAT.sw_done_ack to 1 */ + + /* 2. Write 0 to PCTRL_n.port_en. This blocks AXI port(s) from taking any transaction (blocks traffic on */ + /* AXI ports). */ + reg32_write(DDRC_PCTRL_0(0), 0x00000000); + /* 3. Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. Wait until all AXI ports are idle (the */ + /* uMCTL2 core has to be idle). */ + do { + tmp = reg32_read(DDRC_PSTAT(0)); + } while (tmp & 0x10001); + + /* 4. Write 0 to SBRCTL.scrub_en. Disable SBR, required only if SBR instantiated. */ + /* 5. Poll SBRSTAT.scrub_busy=0. Indicates that there are no outstanding SBR read commands (required */ + /* only if SBR instantiated). */ + /* 6. Set DERATEEN.derate_enable = 0, if DERATEEN.derate_eanble = 1 and the read latency (RL) value */ + /* needs to change after the frequency change (LPDDR2/3/4 only). */ + /* 7. Set DBG1.dis_hif=1 so that no new commands will be accepted by the uMCTL2. */ + reg32setbit(DDRC_DBG1(0), 1); + /* 8. Poll DBGCAM.dbg_wr_q_empty and DBGCAM.dbg_rd_q_empty to ensure that write and read data */ + /* buffers are empty. */ + do { + tmp = 0x06000000 & reg32_read(DDRC_DBGCAM(0)); + } while (tmp != 0x06000000); + /* 9. For DDR4, update MR6 with the new tDLLK value via the Mode Register Write signals */ + /* (MRCTRL0.mr_x/MRCTRL1.mr_x). */ + /* 10. Set DFILPCFG0.dfi_lp_en_sr = 0, if DFILPCFG0.dfi_lp_en_sr = 1, and wait until DFISTAT.dfi_lp_ack */ + /* = 0. */ + /* 11. If DFI PHY Master interface is active in uMCTL2 (DFIPHYMSTR.phymstr_en == 1'b1) then disable it */ + /* by programming DFIPHYMSTR.phymstr_en = 1'b0. */ + /* 12. Wait until STAT.operating_mode[1:0]!=11 indicating that the DWC_ddr_umctl2 controller is not in */ + /* self-refresh mode. */ + tmp = 0x3 & (reg32_read((DDRC_STAT(0)))); + if (tmp == 0x3) { + ddr_dbg("C: Error DRAM should not in Self Refresh\n"); + ddr_dbg("vt_error\n"); + } + /* 13. Assert PWRCTL.selfref_sw for the DWC_ddr_umctl2 core to enter the self-refresh mode. */ + reg32setbit(DDRC_PWRCTL(0), 5); + /* 14. Wait until STAT.operating_mode[1:0]==11 indicating that the DWC_ddr_umctl2 core is in selfrefresh mode. Ensure transition to self-refresh was due to software by checking that STAT.selfref_type[1:0]=2'b10. */ + do { + tmp = 0x3f & (reg32_read((DDRC_STAT(0)))); + ddr_dbg("C: DRAM in Self Refresh\n"); + } while (tmp != 0x23); + + sw_pstate(pstate); + dram_all_mr_cfg(pstate); + + + /* 23. Enable HIF commands by setting DBG1.dis_hif=0. */ + reg32clrbit(DDRC_DBG1(0), 1); + /* 24. Reset DERATEEN.derate_enable = 1 if DERATEEN.derate_enable has been set to 0 in step 6. */ + /* 25. If DFI PHY Master interface was active in uMCTL2 (DFIPHYMSTR.phymstr_en == 1'b1) before the */ + /* step 11 then enable it back by programming DFIPHYMSTR.phymstr_en = 1'b1. */ + /* 26. Write 1 to PCTRL_n.port_en. AXI port(s) are no longer blocked from taking transactions (Re-enable */ + /* traffic on AXI ports). */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + /* 27. Write 1 to SBRCTL.scrub_en. Enable SBR if desired, only required if SBR instantiated. */ + + + + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */ + reg32_write(DDRC_SWCTL(0), 0x0001); + + /* wait SWSTAT.sw_done_ack to 1 */ + do { + tmp = 0x1 & reg32_read(DDRC_SWSTAT(0)); + } while (!tmp); + + +} + +void ddr_init(void) +{ + /* initialize DDR4-2400 (umctl2@800MHz) */ + ddr4_pub_train(); +} diff --git a/board/freescale/imx8mm_val/ddr/ddr4/restore_1d2d_trained_csr_ddr4_p012.c b/board/freescale/imx8mm_val/ddr/ddr4/restore_1d2d_trained_csr_ddr4_p012.c new file mode 100644 index 00000000000..c060c447654 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr4/restore_1d2d_trained_csr_ddr4_p012.c @@ -0,0 +1,1042 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "ddr4_define.h" + +#ifdef ENABLE_RETENTION +static const unsigned int restore_csr[] = { + 0x200b2, + 0x1200b2, + 0x2200b2, + 0x200cb, +#ifdef RUN_ON_SILICON + 0x10043, + 0x110043, + 0x210043, + 0x10143, + 0x110143, + 0x210143, + 0x11043, + 0x111043, + 0x211043, + 0x11143, + 0x111143, + 0x211143, + 0x12043, + 0x112043, + 0x212043, + 0x12143, + 0x112143, + 0x212143, + 0x13043, + 0x113043, + 0x213043, + 0x13143, + 0x113143, + 0x213143, + 0x80, + 0x100080, + 0x200080, + 0x1080, + 0x101080, + 0x201080, + 0x2080, + 0x102080, + 0x202080, + 0x3080, + 0x103080, + 0x203080, + 0x4080, + 0x104080, + 0x204080, + 0x5080, + 0x105080, + 0x205080, + 0x6080, + 0x106080, + 0x206080, + 0x7080, + 0x107080, + 0x207080, + 0x8080, + 0x108080, + 0x208080, + 0x9080, + 0x109080, + 0x209080, + 0x10080, + 0x110080, + 0x210080, + 0x10180, + 0x110180, + 0x210180, + 0x10081, + 0x110081, + 0x210081, + 0x10181, + 0x110181, + 0x210181, + 0x10082, + 0x110082, + 0x210082, + 0x10182, + 0x110182, + 0x210182, + 0x10083, + 0x110083, + 0x210083, + 0x10183, + 0x110183, + 0x210183, + 0x11080, + 0x111080, + 0x211080, + 0x11180, + 0x111180, + 0x211180, + 0x11081, + 0x111081, + 0x211081, + 0x11181, + 0x111181, + 0x211181, + 0x11082, + 0x111082, + 0x211082, + 0x11182, + 0x111182, + 0x211182, + 0x11083, + 0x111083, + 0x211083, + 0x11183, + 0x111183, + 0x211183, + 0x12080, + 0x112080, + 0x212080, + 0x12180, + 0x112180, + 0x212180, + 0x12081, + 0x112081, + 0x212081, + 0x12181, + 0x112181, + 0x212181, + 0x12082, + 0x112082, + 0x212082, + 0x12182, + 0x112182, + 0x212182, + 0x12083, + 0x112083, + 0x212083, + 0x12183, + 0x112183, + 0x212183, + 0x13080, + 0x113080, + 0x213080, + 0x13180, + 0x113180, + 0x213180, + 0x13081, + 0x113081, + 0x213081, + 0x13181, + 0x113181, + 0x213181, + 0x13082, + 0x113082, + 0x213082, + 0x13182, + 0x113182, + 0x213182, + 0x13083, + 0x113083, + 0x213083, + 0x13183, + 0x113183, + 0x213183, + 0x100d0, + 0x1100d0, + 0x2100d0, + 0x101d0, + 0x1101d0, + 0x2101d0, + 0x100d1, + 0x1100d1, + 0x2100d1, + 0x101d1, + 0x1101d1, + 0x2101d1, + 0x100d2, + 0x1100d2, + 0x2100d2, + 0x101d2, + 0x1101d2, + 0x2101d2, + 0x100d3, + 0x1100d3, + 0x2100d3, + 0x101d3, + 0x1101d3, + 0x2101d3, + 0x110d0, + 0x1110d0, + 0x2110d0, + 0x111d0, + 0x1111d0, + 0x2111d0, + 0x110d1, + 0x1110d1, + 0x2110d1, + 0x111d1, + 0x1111d1, + 0x2111d1, + 0x110d2, + 0x1110d2, + 0x2110d2, + 0x111d2, + 0x1111d2, + 0x2111d2, + 0x110d3, + 0x1110d3, + 0x2110d3, + 0x111d3, + 0x1111d3, + 0x2111d3, + 0x120d0, + 0x1120d0, + 0x2120d0, + 0x121d0, + 0x1121d0, + 0x2121d0, + 0x120d1, + 0x1120d1, + 0x2120d1, + 0x121d1, + 0x1121d1, + 0x2121d1, + 0x120d2, + 0x1120d2, + 0x2120d2, + 0x121d2, + 0x1121d2, + 0x2121d2, + 0x120d3, + 0x1120d3, + 0x2120d3, + 0x121d3, + 0x1121d3, + 0x2121d3, + 0x130d0, + 0x1130d0, + 0x2130d0, + 0x131d0, + 0x1131d0, + 0x2131d0, + 0x130d1, + 0x1130d1, + 0x2130d1, + 0x131d1, + 0x1131d1, + 0x2131d1, + 0x130d2, + 0x1130d2, + 0x2130d2, + 0x131d2, + 0x1131d2, + 0x2131d2, + 0x130d3, + 0x1130d3, + 0x2130d3, + 0x131d3, + 0x1131d3, + 0x2131d3, + 0x10068, + 0x10168, + 0x10268, + 0x10368, + 0x10468, + 0x10568, + 0x10668, + 0x10768, + 0x10868, + 0x10069, + 0x10169, + 0x10269, + 0x10369, + 0x10469, + 0x10569, + 0x10669, + 0x10769, + 0x10869, + 0x1006a, + 0x1016a, + 0x1026a, + 0x1036a, + 0x1046a, + 0x1056a, + 0x1066a, + 0x1076a, + 0x1086a, + 0x1006b, + 0x1016b, + 0x1026b, + 0x1036b, + 0x1046b, + 0x1056b, + 0x1066b, + 0x1076b, + 0x1086b, + 0x11068, + 0x11168, + 0x11268, + 0x11368, + 0x11468, + 0x11568, + 0x11668, + 0x11768, + 0x11868, + 0x11069, + 0x11169, + 0x11269, + 0x11369, + 0x11469, + 0x11569, + 0x11669, + 0x11769, + 0x11869, + 0x1106a, + 0x1116a, + 0x1126a, + 0x1136a, + 0x1146a, + 0x1156a, + 0x1166a, + 0x1176a, + 0x1186a, + 0x1106b, + 0x1116b, + 0x1126b, + 0x1136b, + 0x1146b, + 0x1156b, + 0x1166b, + 0x1176b, + 0x1186b, + 0x12068, + 0x12168, + 0x12268, + 0x12368, + 0x12468, + 0x12568, + 0x12668, + 0x12768, + 0x12868, + 0x12069, + 0x12169, + 0x12269, + 0x12369, + 0x12469, + 0x12569, + 0x12669, + 0x12769, + 0x12869, + 0x1206a, + 0x1216a, + 0x1226a, + 0x1236a, + 0x1246a, + 0x1256a, + 0x1266a, + 0x1276a, + 0x1286a, + 0x1206b, + 0x1216b, + 0x1226b, + 0x1236b, + 0x1246b, + 0x1256b, + 0x1266b, + 0x1276b, + 0x1286b, + 0x13068, + 0x13168, + 0x13268, + 0x13368, + 0x13468, + 0x13568, + 0x13668, + 0x13768, + 0x13868, + 0x13069, + 0x13169, + 0x13269, + 0x13369, + 0x13469, + 0x13569, + 0x13669, + 0x13769, + 0x13869, + 0x1306a, + 0x1316a, + 0x1326a, + 0x1336a, + 0x1346a, + 0x1356a, + 0x1366a, + 0x1376a, + 0x1386a, + 0x1306b, + 0x1316b, + 0x1326b, + 0x1336b, + 0x1346b, + 0x1356b, + 0x1366b, + 0x1376b, + 0x1386b, + 0x1008c, + 0x11008c, + 0x21008c, + 0x1018c, + 0x11018c, + 0x21018c, + 0x1008d, + 0x11008d, + 0x21008d, + 0x1018d, + 0x11018d, + 0x21018d, + 0x1008e, + 0x11008e, + 0x21008e, + 0x1018e, + 0x11018e, + 0x21018e, + 0x1008f, + 0x11008f, + 0x21008f, + 0x1018f, + 0x11018f, + 0x21018f, + 0x1108c, + 0x11108c, + 0x21108c, + 0x1118c, + 0x11118c, + 0x21118c, + 0x1108d, + 0x11108d, + 0x21108d, + 0x1118d, + 0x11118d, + 0x21118d, + 0x1108e, + 0x11108e, + 0x21108e, + 0x1118e, + 0x11118e, + 0x21118e, + 0x1108f, + 0x11108f, + 0x21108f, + 0x1118f, + 0x11118f, + 0x21118f, + 0x1208c, + 0x11208c, + 0x21208c, + 0x1218c, + 0x11218c, + 0x21218c, + 0x1208d, + 0x11208d, + 0x21208d, + 0x1218d, + 0x11218d, + 0x21218d, + 0x1208e, + 0x11208e, + 0x21208e, + 0x1218e, + 0x11218e, + 0x21218e, + 0x1208f, + 0x11208f, + 0x21208f, + 0x1218f, + 0x11218f, + 0x21218f, + 0x1308c, + 0x11308c, + 0x21308c, + 0x1318c, + 0x11318c, + 0x21318c, + 0x1308d, + 0x11308d, + 0x21308d, + 0x1318d, + 0x11318d, + 0x21318d, + 0x1308e, + 0x11308e, + 0x21308e, + 0x1318e, + 0x11318e, + 0x21318e, + 0x1308f, + 0x11308f, + 0x21308f, + 0x1318f, + 0x11318f, + 0x21318f, + 0x100c0, + 0x1100c0, + 0x2100c0, + 0x101c0, + 0x1101c0, + 0x2101c0, + 0x102c0, + 0x1102c0, + 0x2102c0, + 0x103c0, + 0x1103c0, + 0x2103c0, + 0x104c0, + 0x1104c0, + 0x2104c0, + 0x105c0, + 0x1105c0, + 0x2105c0, + 0x106c0, + 0x1106c0, + 0x2106c0, + 0x107c0, + 0x1107c0, + 0x2107c0, + 0x108c0, + 0x1108c0, + 0x2108c0, + 0x100c1, + 0x1100c1, + 0x2100c1, + 0x101c1, + 0x1101c1, + 0x2101c1, + 0x102c1, + 0x1102c1, + 0x2102c1, + 0x103c1, + 0x1103c1, + 0x2103c1, + 0x104c1, + 0x1104c1, + 0x2104c1, + 0x105c1, + 0x1105c1, + 0x2105c1, + 0x106c1, + 0x1106c1, + 0x2106c1, + 0x107c1, + 0x1107c1, + 0x2107c1, + 0x108c1, + 0x1108c1, + 0x2108c1, + 0x100c2, + 0x1100c2, + 0x2100c2, + 0x101c2, + 0x1101c2, + 0x2101c2, + 0x102c2, + 0x1102c2, + 0x2102c2, + 0x103c2, + 0x1103c2, + 0x2103c2, + 0x104c2, + 0x1104c2, + 0x2104c2, + 0x105c2, + 0x1105c2, + 0x2105c2, + 0x106c2, + 0x1106c2, + 0x2106c2, + 0x107c2, + 0x1107c2, + 0x2107c2, + 0x108c2, + 0x1108c2, + 0x2108c2, + 0x100c3, + 0x1100c3, + 0x2100c3, + 0x101c3, + 0x1101c3, + 0x2101c3, + 0x102c3, + 0x1102c3, + 0x2102c3, + 0x103c3, + 0x1103c3, + 0x2103c3, + 0x104c3, + 0x1104c3, + 0x2104c3, + 0x105c3, + 0x1105c3, + 0x2105c3, + 0x106c3, + 0x1106c3, + 0x2106c3, + 0x107c3, + 0x1107c3, + 0x2107c3, + 0x108c3, + 0x1108c3, + 0x2108c3, + 0x110c0, + 0x1110c0, + 0x2110c0, + 0x111c0, + 0x1111c0, + 0x2111c0, + 0x112c0, + 0x1112c0, + 0x2112c0, + 0x113c0, + 0x1113c0, + 0x2113c0, + 0x114c0, + 0x1114c0, + 0x2114c0, + 0x115c0, + 0x1115c0, + 0x2115c0, + 0x116c0, + 0x1116c0, + 0x2116c0, + 0x117c0, + 0x1117c0, + 0x2117c0, + 0x118c0, + 0x1118c0, + 0x2118c0, + 0x110c1, + 0x1110c1, + 0x2110c1, + 0x111c1, + 0x1111c1, + 0x2111c1, + 0x112c1, + 0x1112c1, + 0x2112c1, + 0x113c1, + 0x1113c1, + 0x2113c1, + 0x114c1, + 0x1114c1, + 0x2114c1, + 0x115c1, + 0x1115c1, + 0x2115c1, + 0x116c1, + 0x1116c1, + 0x2116c1, + 0x117c1, + 0x1117c1, + 0x2117c1, + 0x118c1, + 0x1118c1, + 0x2118c1, + 0x110c2, + 0x1110c2, + 0x2110c2, + 0x111c2, + 0x1111c2, + 0x2111c2, + 0x112c2, + 0x1112c2, + 0x2112c2, + 0x113c2, + 0x1113c2, + 0x2113c2, + 0x114c2, + 0x1114c2, + 0x2114c2, + 0x115c2, + 0x1115c2, + 0x2115c2, + 0x116c2, + 0x1116c2, + 0x2116c2, + 0x117c2, + 0x1117c2, + 0x2117c2, + 0x118c2, + 0x1118c2, + 0x2118c2, + 0x110c3, + 0x1110c3, + 0x2110c3, + 0x111c3, + 0x1111c3, + 0x2111c3, + 0x112c3, + 0x1112c3, + 0x2112c3, + 0x113c3, + 0x1113c3, + 0x2113c3, + 0x114c3, + 0x1114c3, + 0x2114c3, + 0x115c3, + 0x1115c3, + 0x2115c3, + 0x116c3, + 0x1116c3, + 0x2116c3, + 0x117c3, + 0x1117c3, + 0x2117c3, + 0x118c3, + 0x1118c3, + 0x2118c3, + 0x120c0, + 0x1120c0, + 0x2120c0, + 0x121c0, + 0x1121c0, + 0x2121c0, + 0x122c0, + 0x1122c0, + 0x2122c0, + 0x123c0, + 0x1123c0, + 0x2123c0, + 0x124c0, + 0x1124c0, + 0x2124c0, + 0x125c0, + 0x1125c0, + 0x2125c0, + 0x126c0, + 0x1126c0, + 0x2126c0, + 0x127c0, + 0x1127c0, + 0x2127c0, + 0x128c0, + 0x1128c0, + 0x2128c0, + 0x120c1, + 0x1120c1, + 0x2120c1, + 0x121c1, + 0x1121c1, + 0x2121c1, + 0x122c1, + 0x1122c1, + 0x2122c1, + 0x123c1, + 0x1123c1, + 0x2123c1, + 0x124c1, + 0x1124c1, + 0x2124c1, + 0x125c1, + 0x1125c1, + 0x2125c1, + 0x126c1, + 0x1126c1, + 0x2126c1, + 0x127c1, + 0x1127c1, + 0x2127c1, + 0x128c1, + 0x1128c1, + 0x2128c1, + 0x120c2, + 0x1120c2, + 0x2120c2, + 0x121c2, + 0x1121c2, + 0x2121c2, + 0x122c2, + 0x1122c2, + 0x2122c2, + 0x123c2, + 0x1123c2, + 0x2123c2, + 0x124c2, + 0x1124c2, + 0x2124c2, + 0x125c2, + 0x1125c2, + 0x2125c2, + 0x126c2, + 0x1126c2, + 0x2126c2, + 0x127c2, + 0x1127c2, + 0x2127c2, + 0x128c2, + 0x1128c2, + 0x2128c2, + 0x120c3, + 0x1120c3, + 0x2120c3, + 0x121c3, + 0x1121c3, + 0x2121c3, + 0x122c3, + 0x1122c3, + 0x2122c3, + 0x123c3, + 0x1123c3, + 0x2123c3, + 0x124c3, + 0x1124c3, + 0x2124c3, + 0x125c3, + 0x1125c3, + 0x2125c3, + 0x126c3, + 0x1126c3, + 0x2126c3, + 0x127c3, + 0x1127c3, + 0x2127c3, + 0x128c3, + 0x1128c3, + 0x2128c3, + 0x130c0, + 0x1130c0, + 0x2130c0, + 0x131c0, + 0x1131c0, + 0x2131c0, + 0x132c0, + 0x1132c0, + 0x2132c0, + 0x133c0, + 0x1133c0, + 0x2133c0, + 0x134c0, + 0x1134c0, + 0x2134c0, + 0x135c0, + 0x1135c0, + 0x2135c0, + 0x136c0, + 0x1136c0, + 0x2136c0, + 0x137c0, + 0x1137c0, + 0x2137c0, + 0x138c0, + 0x1138c0, + 0x2138c0, + 0x130c1, + 0x1130c1, + 0x2130c1, + 0x131c1, + 0x1131c1, + 0x2131c1, + 0x132c1, + 0x1132c1, + 0x2132c1, + 0x133c1, + 0x1133c1, + 0x2133c1, + 0x134c1, + 0x1134c1, + 0x2134c1, + 0x135c1, + 0x1135c1, + 0x2135c1, + 0x136c1, + 0x1136c1, + 0x2136c1, + 0x137c1, + 0x1137c1, + 0x2137c1, + 0x138c1, + 0x1138c1, + 0x2138c1, + 0x130c2, + 0x1130c2, + 0x2130c2, + 0x131c2, + 0x1131c2, + 0x2131c2, + 0x132c2, + 0x1132c2, + 0x2132c2, + 0x133c2, + 0x1133c2, + 0x2133c2, + 0x134c2, + 0x1134c2, + 0x2134c2, + 0x135c2, + 0x1135c2, + 0x2135c2, + 0x136c2, + 0x1136c2, + 0x2136c2, + 0x137c2, + 0x1137c2, + 0x2137c2, + 0x138c2, + 0x1138c2, + 0x2138c2, + 0x130c3, + 0x1130c3, + 0x2130c3, + 0x131c3, + 0x1131c3, + 0x2131c3, + 0x132c3, + 0x1132c3, + 0x2132c3, + 0x133c3, + 0x1133c3, + 0x2133c3, + 0x134c3, + 0x1134c3, + 0x2134c3, + 0x135c3, + 0x1135c3, + 0x2135c3, + 0x136c3, + 0x1136c3, + 0x2136c3, + 0x137c3, + 0x1137c3, + 0x2137c3, + 0x138c3, + 0x1138c3, + 0x2138c3, + 0x10020, + 0x110020, + 0x210020, + 0x11020, + 0x111020, + 0x211020, + 0x12020, + 0x112020, + 0x212020, + 0x13020, + 0x113020, + 0x213020, + 0x2007d, + 0x12007d, + 0x22007d, + 0x10040, + 0x10140, + 0x10240, + 0x10340, + 0x10440, + 0x10540, + 0x10640, + 0x10740, + 0x10840, + 0x10030, + 0x10130, + 0x10230, + 0x10330, + 0x10430, + 0x10530, + 0x10630, + 0x10730, + 0x10830, + 0x11040, + 0x11140, + 0x11240, + 0x11340, + 0x11440, + 0x11540, + 0x11640, + 0x11740, + 0x11840, + 0x11030, + 0x11130, + 0x11230, + 0x11330, + 0x11430, + 0x11530, + 0x11630, + 0x11730, + 0x11830, + 0x12040, + 0x12140, + 0x12240, + 0x12340, + 0x12440, + 0x12540, + 0x12640, + 0x12740, + 0x12840, + 0x12030, + 0x12130, + 0x12230, + 0x12330, + 0x12430, + 0x12530, + 0x12630, + 0x12730, + 0x12830, + 0x13040, + 0x13140, + 0x13240, + 0x13340, + 0x13440, + 0x13540, + 0x13640, + 0x13740, + 0x13840, + 0x13030, + 0x13130, + 0x13230, + 0x13330, + 0x13430, + 0x13530, + 0x13630, + 0x13730, + 0x13830, +#endif + 0 +}; + +void restore_1d2d_trained_csr_ddr4_p012(unsigned int addr) +{ + unsigned int i; + + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + for (i = 0; restore_csr[i] != 0; i++) { + dwc_ddrphy_apb_wr(restore_csr[i], reg32_read(addr + (i << 2))); + } + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + + ddr_dbg("restore 1d2d training registers done \n"); +} +#endif diff --git a/board/freescale/imx8mm_val/ddr/ddr4/save_1d2d_trained_csr_ddr4_p012.c b/board/freescale/imx8mm_val/ddr/ddr4/save_1d2d_trained_csr_ddr4_p012.c new file mode 100644 index 00000000000..179fabe36e0 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/ddr4/save_1d2d_trained_csr_ddr4_p012.c @@ -0,0 +1,1044 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "ddr4_define.h" + +#ifdef ENABLE_RETENTION +static const unsigned int save_csr[] = { + 0x200b2, + 0x1200b2, + 0x2200b2, + 0x200cb, +#ifdef RUN_ON_SILICON + 0x10043, + 0x110043, + 0x210043, + 0x10143, + 0x110143, + 0x210143, + 0x11043, + 0x111043, + 0x211043, + 0x11143, + 0x111143, + 0x211143, + 0x12043, + 0x112043, + 0x212043, + 0x12143, + 0x112143, + 0x212143, + 0x13043, + 0x113043, + 0x213043, + 0x13143, + 0x113143, + 0x213143, + 0x80, + 0x100080, + 0x200080, + 0x1080, + 0x101080, + 0x201080, + 0x2080, + 0x102080, + 0x202080, + 0x3080, + 0x103080, + 0x203080, + 0x4080, + 0x104080, + 0x204080, + 0x5080, + 0x105080, + 0x205080, + 0x6080, + 0x106080, + 0x206080, + 0x7080, + 0x107080, + 0x207080, + 0x8080, + 0x108080, + 0x208080, + 0x9080, + 0x109080, + 0x209080, + 0x10080, + 0x110080, + 0x210080, + 0x10180, + 0x110180, + 0x210180, + 0x10081, + 0x110081, + 0x210081, + 0x10181, + 0x110181, + 0x210181, + 0x10082, + 0x110082, + 0x210082, + 0x10182, + 0x110182, + 0x210182, + 0x10083, + 0x110083, + 0x210083, + 0x10183, + 0x110183, + 0x210183, + 0x11080, + 0x111080, + 0x211080, + 0x11180, + 0x111180, + 0x211180, + 0x11081, + 0x111081, + 0x211081, + 0x11181, + 0x111181, + 0x211181, + 0x11082, + 0x111082, + 0x211082, + 0x11182, + 0x111182, + 0x211182, + 0x11083, + 0x111083, + 0x211083, + 0x11183, + 0x111183, + 0x211183, + 0x12080, + 0x112080, + 0x212080, + 0x12180, + 0x112180, + 0x212180, + 0x12081, + 0x112081, + 0x212081, + 0x12181, + 0x112181, + 0x212181, + 0x12082, + 0x112082, + 0x212082, + 0x12182, + 0x112182, + 0x212182, + 0x12083, + 0x112083, + 0x212083, + 0x12183, + 0x112183, + 0x212183, + 0x13080, + 0x113080, + 0x213080, + 0x13180, + 0x113180, + 0x213180, + 0x13081, + 0x113081, + 0x213081, + 0x13181, + 0x113181, + 0x213181, + 0x13082, + 0x113082, + 0x213082, + 0x13182, + 0x113182, + 0x213182, + 0x13083, + 0x113083, + 0x213083, + 0x13183, + 0x113183, + 0x213183, + 0x100d0, + 0x1100d0, + 0x2100d0, + 0x101d0, + 0x1101d0, + 0x2101d0, + 0x100d1, + 0x1100d1, + 0x2100d1, + 0x101d1, + 0x1101d1, + 0x2101d1, + 0x100d2, + 0x1100d2, + 0x2100d2, + 0x101d2, + 0x1101d2, + 0x2101d2, + 0x100d3, + 0x1100d3, + 0x2100d3, + 0x101d3, + 0x1101d3, + 0x2101d3, + 0x110d0, + 0x1110d0, + 0x2110d0, + 0x111d0, + 0x1111d0, + 0x2111d0, + 0x110d1, + 0x1110d1, + 0x2110d1, + 0x111d1, + 0x1111d1, + 0x2111d1, + 0x110d2, + 0x1110d2, + 0x2110d2, + 0x111d2, + 0x1111d2, + 0x2111d2, + 0x110d3, + 0x1110d3, + 0x2110d3, + 0x111d3, + 0x1111d3, + 0x2111d3, + 0x120d0, + 0x1120d0, + 0x2120d0, + 0x121d0, + 0x1121d0, + 0x2121d0, + 0x120d1, + 0x1120d1, + 0x2120d1, + 0x121d1, + 0x1121d1, + 0x2121d1, + 0x120d2, + 0x1120d2, + 0x2120d2, + 0x121d2, + 0x1121d2, + 0x2121d2, + 0x120d3, + 0x1120d3, + 0x2120d3, + 0x121d3, + 0x1121d3, + 0x2121d3, + 0x130d0, + 0x1130d0, + 0x2130d0, + 0x131d0, + 0x1131d0, + 0x2131d0, + 0x130d1, + 0x1130d1, + 0x2130d1, + 0x131d1, + 0x1131d1, + 0x2131d1, + 0x130d2, + 0x1130d2, + 0x2130d2, + 0x131d2, + 0x1131d2, + 0x2131d2, + 0x130d3, + 0x1130d3, + 0x2130d3, + 0x131d3, + 0x1131d3, + 0x2131d3, + 0x10068, + 0x10168, + 0x10268, + 0x10368, + 0x10468, + 0x10568, + 0x10668, + 0x10768, + 0x10868, + 0x10069, + 0x10169, + 0x10269, + 0x10369, + 0x10469, + 0x10569, + 0x10669, + 0x10769, + 0x10869, + 0x1006a, + 0x1016a, + 0x1026a, + 0x1036a, + 0x1046a, + 0x1056a, + 0x1066a, + 0x1076a, + 0x1086a, + 0x1006b, + 0x1016b, + 0x1026b, + 0x1036b, + 0x1046b, + 0x1056b, + 0x1066b, + 0x1076b, + 0x1086b, + 0x11068, + 0x11168, + 0x11268, + 0x11368, + 0x11468, + 0x11568, + 0x11668, + 0x11768, + 0x11868, + 0x11069, + 0x11169, + 0x11269, + 0x11369, + 0x11469, + 0x11569, + 0x11669, + 0x11769, + 0x11869, + 0x1106a, + 0x1116a, + 0x1126a, + 0x1136a, + 0x1146a, + 0x1156a, + 0x1166a, + 0x1176a, + 0x1186a, + 0x1106b, + 0x1116b, + 0x1126b, + 0x1136b, + 0x1146b, + 0x1156b, + 0x1166b, + 0x1176b, + 0x1186b, + 0x12068, + 0x12168, + 0x12268, + 0x12368, + 0x12468, + 0x12568, + 0x12668, + 0x12768, + 0x12868, + 0x12069, + 0x12169, + 0x12269, + 0x12369, + 0x12469, + 0x12569, + 0x12669, + 0x12769, + 0x12869, + 0x1206a, + 0x1216a, + 0x1226a, + 0x1236a, + 0x1246a, + 0x1256a, + 0x1266a, + 0x1276a, + 0x1286a, + 0x1206b, + 0x1216b, + 0x1226b, + 0x1236b, + 0x1246b, + 0x1256b, + 0x1266b, + 0x1276b, + 0x1286b, + 0x13068, + 0x13168, + 0x13268, + 0x13368, + 0x13468, + 0x13568, + 0x13668, + 0x13768, + 0x13868, + 0x13069, + 0x13169, + 0x13269, + 0x13369, + 0x13469, + 0x13569, + 0x13669, + 0x13769, + 0x13869, + 0x1306a, + 0x1316a, + 0x1326a, + 0x1336a, + 0x1346a, + 0x1356a, + 0x1366a, + 0x1376a, + 0x1386a, + 0x1306b, + 0x1316b, + 0x1326b, + 0x1336b, + 0x1346b, + 0x1356b, + 0x1366b, + 0x1376b, + 0x1386b, + 0x1008c, + 0x11008c, + 0x21008c, + 0x1018c, + 0x11018c, + 0x21018c, + 0x1008d, + 0x11008d, + 0x21008d, + 0x1018d, + 0x11018d, + 0x21018d, + 0x1008e, + 0x11008e, + 0x21008e, + 0x1018e, + 0x11018e, + 0x21018e, + 0x1008f, + 0x11008f, + 0x21008f, + 0x1018f, + 0x11018f, + 0x21018f, + 0x1108c, + 0x11108c, + 0x21108c, + 0x1118c, + 0x11118c, + 0x21118c, + 0x1108d, + 0x11108d, + 0x21108d, + 0x1118d, + 0x11118d, + 0x21118d, + 0x1108e, + 0x11108e, + 0x21108e, + 0x1118e, + 0x11118e, + 0x21118e, + 0x1108f, + 0x11108f, + 0x21108f, + 0x1118f, + 0x11118f, + 0x21118f, + 0x1208c, + 0x11208c, + 0x21208c, + 0x1218c, + 0x11218c, + 0x21218c, + 0x1208d, + 0x11208d, + 0x21208d, + 0x1218d, + 0x11218d, + 0x21218d, + 0x1208e, + 0x11208e, + 0x21208e, + 0x1218e, + 0x11218e, + 0x21218e, + 0x1208f, + 0x11208f, + 0x21208f, + 0x1218f, + 0x11218f, + 0x21218f, + 0x1308c, + 0x11308c, + 0x21308c, + 0x1318c, + 0x11318c, + 0x21318c, + 0x1308d, + 0x11308d, + 0x21308d, + 0x1318d, + 0x11318d, + 0x21318d, + 0x1308e, + 0x11308e, + 0x21308e, + 0x1318e, + 0x11318e, + 0x21318e, + 0x1308f, + 0x11308f, + 0x21308f, + 0x1318f, + 0x11318f, + 0x21318f, + 0x100c0, + 0x1100c0, + 0x2100c0, + 0x101c0, + 0x1101c0, + 0x2101c0, + 0x102c0, + 0x1102c0, + 0x2102c0, + 0x103c0, + 0x1103c0, + 0x2103c0, + 0x104c0, + 0x1104c0, + 0x2104c0, + 0x105c0, + 0x1105c0, + 0x2105c0, + 0x106c0, + 0x1106c0, + 0x2106c0, + 0x107c0, + 0x1107c0, + 0x2107c0, + 0x108c0, + 0x1108c0, + 0x2108c0, + 0x100c1, + 0x1100c1, + 0x2100c1, + 0x101c1, + 0x1101c1, + 0x2101c1, + 0x102c1, + 0x1102c1, + 0x2102c1, + 0x103c1, + 0x1103c1, + 0x2103c1, + 0x104c1, + 0x1104c1, + 0x2104c1, + 0x105c1, + 0x1105c1, + 0x2105c1, + 0x106c1, + 0x1106c1, + 0x2106c1, + 0x107c1, + 0x1107c1, + 0x2107c1, + 0x108c1, + 0x1108c1, + 0x2108c1, + 0x100c2, + 0x1100c2, + 0x2100c2, + 0x101c2, + 0x1101c2, + 0x2101c2, + 0x102c2, + 0x1102c2, + 0x2102c2, + 0x103c2, + 0x1103c2, + 0x2103c2, + 0x104c2, + 0x1104c2, + 0x2104c2, + 0x105c2, + 0x1105c2, + 0x2105c2, + 0x106c2, + 0x1106c2, + 0x2106c2, + 0x107c2, + 0x1107c2, + 0x2107c2, + 0x108c2, + 0x1108c2, + 0x2108c2, + 0x100c3, + 0x1100c3, + 0x2100c3, + 0x101c3, + 0x1101c3, + 0x2101c3, + 0x102c3, + 0x1102c3, + 0x2102c3, + 0x103c3, + 0x1103c3, + 0x2103c3, + 0x104c3, + 0x1104c3, + 0x2104c3, + 0x105c3, + 0x1105c3, + 0x2105c3, + 0x106c3, + 0x1106c3, + 0x2106c3, + 0x107c3, + 0x1107c3, + 0x2107c3, + 0x108c3, + 0x1108c3, + 0x2108c3, + 0x110c0, + 0x1110c0, + 0x2110c0, + 0x111c0, + 0x1111c0, + 0x2111c0, + 0x112c0, + 0x1112c0, + 0x2112c0, + 0x113c0, + 0x1113c0, + 0x2113c0, + 0x114c0, + 0x1114c0, + 0x2114c0, + 0x115c0, + 0x1115c0, + 0x2115c0, + 0x116c0, + 0x1116c0, + 0x2116c0, + 0x117c0, + 0x1117c0, + 0x2117c0, + 0x118c0, + 0x1118c0, + 0x2118c0, + 0x110c1, + 0x1110c1, + 0x2110c1, + 0x111c1, + 0x1111c1, + 0x2111c1, + 0x112c1, + 0x1112c1, + 0x2112c1, + 0x113c1, + 0x1113c1, + 0x2113c1, + 0x114c1, + 0x1114c1, + 0x2114c1, + 0x115c1, + 0x1115c1, + 0x2115c1, + 0x116c1, + 0x1116c1, + 0x2116c1, + 0x117c1, + 0x1117c1, + 0x2117c1, + 0x118c1, + 0x1118c1, + 0x2118c1, + 0x110c2, + 0x1110c2, + 0x2110c2, + 0x111c2, + 0x1111c2, + 0x2111c2, + 0x112c2, + 0x1112c2, + 0x2112c2, + 0x113c2, + 0x1113c2, + 0x2113c2, + 0x114c2, + 0x1114c2, + 0x2114c2, + 0x115c2, + 0x1115c2, + 0x2115c2, + 0x116c2, + 0x1116c2, + 0x2116c2, + 0x117c2, + 0x1117c2, + 0x2117c2, + 0x118c2, + 0x1118c2, + 0x2118c2, + 0x110c3, + 0x1110c3, + 0x2110c3, + 0x111c3, + 0x1111c3, + 0x2111c3, + 0x112c3, + 0x1112c3, + 0x2112c3, + 0x113c3, + 0x1113c3, + 0x2113c3, + 0x114c3, + 0x1114c3, + 0x2114c3, + 0x115c3, + 0x1115c3, + 0x2115c3, + 0x116c3, + 0x1116c3, + 0x2116c3, + 0x117c3, + 0x1117c3, + 0x2117c3, + 0x118c3, + 0x1118c3, + 0x2118c3, + 0x120c0, + 0x1120c0, + 0x2120c0, + 0x121c0, + 0x1121c0, + 0x2121c0, + 0x122c0, + 0x1122c0, + 0x2122c0, + 0x123c0, + 0x1123c0, + 0x2123c0, + 0x124c0, + 0x1124c0, + 0x2124c0, + 0x125c0, + 0x1125c0, + 0x2125c0, + 0x126c0, + 0x1126c0, + 0x2126c0, + 0x127c0, + 0x1127c0, + 0x2127c0, + 0x128c0, + 0x1128c0, + 0x2128c0, + 0x120c1, + 0x1120c1, + 0x2120c1, + 0x121c1, + 0x1121c1, + 0x2121c1, + 0x122c1, + 0x1122c1, + 0x2122c1, + 0x123c1, + 0x1123c1, + 0x2123c1, + 0x124c1, + 0x1124c1, + 0x2124c1, + 0x125c1, + 0x1125c1, + 0x2125c1, + 0x126c1, + 0x1126c1, + 0x2126c1, + 0x127c1, + 0x1127c1, + 0x2127c1, + 0x128c1, + 0x1128c1, + 0x2128c1, + 0x120c2, + 0x1120c2, + 0x2120c2, + 0x121c2, + 0x1121c2, + 0x2121c2, + 0x122c2, + 0x1122c2, + 0x2122c2, + 0x123c2, + 0x1123c2, + 0x2123c2, + 0x124c2, + 0x1124c2, + 0x2124c2, + 0x125c2, + 0x1125c2, + 0x2125c2, + 0x126c2, + 0x1126c2, + 0x2126c2, + 0x127c2, + 0x1127c2, + 0x2127c2, + 0x128c2, + 0x1128c2, + 0x2128c2, + 0x120c3, + 0x1120c3, + 0x2120c3, + 0x121c3, + 0x1121c3, + 0x2121c3, + 0x122c3, + 0x1122c3, + 0x2122c3, + 0x123c3, + 0x1123c3, + 0x2123c3, + 0x124c3, + 0x1124c3, + 0x2124c3, + 0x125c3, + 0x1125c3, + 0x2125c3, + 0x126c3, + 0x1126c3, + 0x2126c3, + 0x127c3, + 0x1127c3, + 0x2127c3, + 0x128c3, + 0x1128c3, + 0x2128c3, + 0x130c0, + 0x1130c0, + 0x2130c0, + 0x131c0, + 0x1131c0, + 0x2131c0, + 0x132c0, + 0x1132c0, + 0x2132c0, + 0x133c0, + 0x1133c0, + 0x2133c0, + 0x134c0, + 0x1134c0, + 0x2134c0, + 0x135c0, + 0x1135c0, + 0x2135c0, + 0x136c0, + 0x1136c0, + 0x2136c0, + 0x137c0, + 0x1137c0, + 0x2137c0, + 0x138c0, + 0x1138c0, + 0x2138c0, + 0x130c1, + 0x1130c1, + 0x2130c1, + 0x131c1, + 0x1131c1, + 0x2131c1, + 0x132c1, + 0x1132c1, + 0x2132c1, + 0x133c1, + 0x1133c1, + 0x2133c1, + 0x134c1, + 0x1134c1, + 0x2134c1, + 0x135c1, + 0x1135c1, + 0x2135c1, + 0x136c1, + 0x1136c1, + 0x2136c1, + 0x137c1, + 0x1137c1, + 0x2137c1, + 0x138c1, + 0x1138c1, + 0x2138c1, + 0x130c2, + 0x1130c2, + 0x2130c2, + 0x131c2, + 0x1131c2, + 0x2131c2, + 0x132c2, + 0x1132c2, + 0x2132c2, + 0x133c2, + 0x1133c2, + 0x2133c2, + 0x134c2, + 0x1134c2, + 0x2134c2, + 0x135c2, + 0x1135c2, + 0x2135c2, + 0x136c2, + 0x1136c2, + 0x2136c2, + 0x137c2, + 0x1137c2, + 0x2137c2, + 0x138c2, + 0x1138c2, + 0x2138c2, + 0x130c3, + 0x1130c3, + 0x2130c3, + 0x131c3, + 0x1131c3, + 0x2131c3, + 0x132c3, + 0x1132c3, + 0x2132c3, + 0x133c3, + 0x1133c3, + 0x2133c3, + 0x134c3, + 0x1134c3, + 0x2134c3, + 0x135c3, + 0x1135c3, + 0x2135c3, + 0x136c3, + 0x1136c3, + 0x2136c3, + 0x137c3, + 0x1137c3, + 0x2137c3, + 0x138c3, + 0x1138c3, + 0x2138c3, + 0x10020, + 0x110020, + 0x210020, + 0x11020, + 0x111020, + 0x211020, + 0x12020, + 0x112020, + 0x212020, + 0x13020, + 0x113020, + 0x213020, + 0x2007d, + 0x12007d, + 0x22007d, + 0x10040, + 0x10140, + 0x10240, + 0x10340, + 0x10440, + 0x10540, + 0x10640, + 0x10740, + 0x10840, + 0x10030, + 0x10130, + 0x10230, + 0x10330, + 0x10430, + 0x10530, + 0x10630, + 0x10730, + 0x10830, + 0x11040, + 0x11140, + 0x11240, + 0x11340, + 0x11440, + 0x11540, + 0x11640, + 0x11740, + 0x11840, + 0x11030, + 0x11130, + 0x11230, + 0x11330, + 0x11430, + 0x11530, + 0x11630, + 0x11730, + 0x11830, + 0x12040, + 0x12140, + 0x12240, + 0x12340, + 0x12440, + 0x12540, + 0x12640, + 0x12740, + 0x12840, + 0x12030, + 0x12130, + 0x12230, + 0x12330, + 0x12430, + 0x12530, + 0x12630, + 0x12730, + 0x12830, + 0x13040, + 0x13140, + 0x13240, + 0x13340, + 0x13440, + 0x13540, + 0x13640, + 0x13740, + 0x13840, + 0x13030, + 0x13130, + 0x13230, + 0x13330, + 0x13430, + 0x13530, + 0x13630, + 0x13730, + 0x13830, +#endif + 0 +}; + +void save_1d2d_trained_csr_ddr4_p012(unsigned int addr) +{ + unsigned int i; + + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xc0080, 0x3); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + for (i = 0; save_csr[i] != 0; i++) { + reg32_write(addr + (i << 2), dwc_ddrphy_apb_rd(save_csr[i])); + } + dwc_ddrphy_apb_wr(0xc0080, 0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + + ddr_dbg("save 1d2d training registers done \n"); +} +#endif diff --git a/board/freescale/imx8mm_val/ddr/helper.c b/board/freescale/imx8mm_val/ddr/helper.c new file mode 100644 index 00000000000..564f582f144 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/helper.c @@ -0,0 +1,102 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define IMEM_LEN 32768 +#define DMEM_LEN 16384 +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +/* We need PHY iMEM PHY is 32KB padded */ +void ddr_load_train_code(enum fw_type type) +{ + u32 tmp32, i; + u32 error = 0; + unsigned long pr_to32, pr_from32; + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; + unsigned long imem_start = (unsigned long)&_end + fw_offset; + unsigned long dmem_start = imem_start + IMEM_LEN; + + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN; ) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN;) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + printf("check ddr4_pmu_train_imem code\n"); + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN;) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + + if (tmp32 != readl(pr_from32)) { + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + if (error) + printf("check ddr4_pmu_train_imem code fail=%d\n", error); + else + printf("check ddr4_pmu_train_imem code pass\n"); + + printf("check ddr4_pmu_train_dmem code\n"); + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN;) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + if (tmp32 != readl(pr_from32)) { + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + + if (error) + printf("check ddr4_pmu_train_dmem code fail=%d", error); + else + printf("check ddr4_pmu_train_dmem code pass\n"); +} diff --git a/board/freescale/imx8mm_val/ddr/wait_ddrphy_training_complete.c b/board/freescale/imx8mm_val/ddr/wait_ddrphy_training_complete.c new file mode 100644 index 00000000000..e0da1be32f9 --- /dev/null +++ b/board/freescale/imx8mm_val/ddr/wait_ddrphy_training_complete.c @@ -0,0 +1,102 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include "ddr.h" + +static inline void poll_pmu_message_ready(void) +{ + unsigned int reg; + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + } while (reg & 0x1); +} + +static inline void ack_pmu_message_recieve(void) +{ + unsigned int reg; + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031, 0x0); + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + } while (!(reg & 0x1)); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031, 0x1); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032); + + ack_pmu_message_recieve(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032); + + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034); + + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_recieve(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + ddr_dbg("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + ddr_dbg(" PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)) { + arg = get_stream_message(); + ddr_dbg(" arg[%d] = 0x%08x\n", i, arg); + i++; + } + + ddr_dbg("\n"); +} + +void wait_ddrphy_training_complete(void) +{ + unsigned int mail; + while (1) { + mail = get_mail(); + decode_major_message(mail); + if (mail == 0x08) { + decode_streaming_message(); + } else if (mail == 0x07) { + printf("Training PASS\n"); + break; + } else if (mail == 0xff) { + printf("Training FAILED\n"); + break; + } + } +} diff --git a/board/freescale/imx8mm_val/imx8mm_val.c b/board/freescale/imx8mm_val/imx8mm_val.c new file mode 100644 index 00000000000..db0ae07e06a --- /dev/null +++ b/board/freescale/imx8mm_val/imx8mm_val.c @@ -0,0 +1,447 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; +#endif + +#ifdef CONFIG_FSL_FSPI +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) +static iomux_v3_cfg_t const qspi_pads[] = { + IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL | PAD_CTL_PE | PAD_CTL_PUE), + IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); + + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +#define SPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) +static iomux_v3_cfg_t const ecspi1_pads[] = { + IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(5, 9), "ECSPI1 CS"); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return IMX_GPIO_NR(5, 9); +} +#endif + +#ifdef CONFIG_NAND_MXS +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS) +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE) +static iomux_v3_cfg_t const gpmi_pads[] = { + IMX8MM_PAD_NAND_ALE_RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), + IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); +} +#endif + +int board_early_init_f(void) +{ +#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); +#endif + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); /* SPL will call the board_early_init_f */ +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + /* TODO */ + return 0; +} +#endif + +int dram_init(void) +{ + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; + else + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL +#define FEC_RST_PAD IMX_GPIO_NR(4, 22) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(FEC_RST_PAD, "fec1_rst"); + gpio_direction_output(FEC_RST_PAD, 0); + udelay(500); + gpio_direction_output(FEC_RST_PAD, 1); +} +#endif + +static int setup_fec(void) +{ +#ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + /* + * GPR1 bit 13: + * 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also; + * 0:enet1 rmii clock comes from external phy or osc + */ + + setbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT); + return set_clk_enet(ENET_50MHZ); +#else + + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); + return set_clk_enet(ENET_125MHZ); +#endif +} + +int board_phy_config(struct phy_device *phydev) +{ +#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +#endif + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port port2; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + return 0; +} + +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(1, 0x72); + } else if (port == &port2) { + debug("Setup pd switch on port 2\n"); + return setup_pd_switch(1, 0x73); + } else + return -EINVAL; +} + +struct tcpc_port_config port1_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +struct tcpc_port_config port2_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x52, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +static int setup_typec(void) +{ + int ret; + + debug("tcpc_init port 2\n"); + ret = tcpc_init(&port2, port2_config, NULL); + if (ret) { + printf("%s: tcpc port2 init failed, err=%d\n", + __func__, ret); + } else if (tcpc_pd_sink_check_charging(&port2)) { + /* Disable PD for USB1, since USB2 has priority */ + port1_config.disable_pd = true; + printf("Power supply on USB2\n"); + } + + debug("tcpc_init port 1\n"); + ret = tcpc_init(&port1, port1_config, NULL); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } else { + if (!port1_config.disable_pd) + printf("Power supply on USB1\n"); + return ret; + } + + return ret; +} +#endif + +#ifdef CONFIG_USB_EHCI_HCD +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; +#ifdef CONFIG_USB_TCPC + struct tcpc_port *port_ptr; +#endif + + debug("board_usb_init %d, type %d\n", index, init); + + imx8m_usb_power(index, true); + +#ifdef CONFIG_USB_TCPC + if (index == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + if (init == USB_INIT_HOST) + tcpc_setup_dfp_mode(port_ptr); + else + tcpc_setup_ufp_mode(port_ptr); +#endif + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + debug("board_usb_cleanup %d, type %d\n", index, init); + +#ifdef CONFIG_USB_TCPC + if (init == USB_INIT_HOST) { + if (index == 0) + ret = tcpc_disable_src_vbus(&port1); + else + ret = tcpc_disable_src_vbus(&port2); + } +#endif + + imx8m_usb_power(index, false); + return ret; +} + +#ifdef CONFIG_USB_TCPC +int board_ehci_usb_phy_mode(struct udevice *dev) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + struct tcpc_port *port_ptr; + + if (dev->seq == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + tcpc_setup_ufp_mode(port_ptr); + + ret = tcpc_get_cc_status(port_ptr, &pol, &state); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; +} +#endif +#endif + +int board_init(void) +{ +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_FSL_FSPI + board_qspi_init(); +#endif + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno + 1; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} diff --git a/board/freescale/imx8mm_val/spl.c b/board/freescale/imx8mm_val/spl.c new file mode 100644 index 00000000000..99144049ea2 --- /dev/null +++ b/board/freescale/imx8mm_val/spl.c @@ -0,0 +1,249 @@ +/* + * Copyright 2018-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr/ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + /* ddr train */ + ddr_init(); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC, + .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC, + .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +/* + * The evk board uses DAT3 to detect CD card plugin, + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. + */ +static iomux_v3_cfg_t const usdhc2_cd_pad = + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); + +static iomux_v3_cfg_t const usdhc2_dat3_pad = + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | + MUX_PAD_CTRL(USDHC_PAD_CTRL); + + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 1}, + {USDHC3_BASE_ADDR, 0, 1}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 1: + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + imx_iomux_v3_setup_pad(usdhc2_cd_pad); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_direction_input(USDHC2_CD_GPIO); + + /* + * Since it is the DAT3 pin, this pin is pulled to + * low voltage if no card + */ + ret = gpio_get_value(USDHC2_CD_GPIO); + + imx_iomux_v3_setup_pad(usdhc2_dat3_pad); + return ret; + } + + return 1; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_bd71837_init(I2C_PMIC); + if (ret) + printf("power init failed"); + + p = pmic_get("BD71837"); + pmic_probe(p); + + + /* decrease RESET key long push time from the default 10s to 10ms */ + pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0); + + /* unlock the PMIC regs */ + pmic_reg_write(p, BD71837_REGLOCK, 0x1); + + /* increase VDD_SOC to typical value 0.85v before first DRAM access */ + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); + + /* increase VDD_DRAM to 0.9v for 3Ghz DDR */ + pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2); + +#ifdef CONFIG_TARGET_IMX8MM_DDR4_VAL + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28); +#elif defined(CONFIG_TARGET_IMX8MM_DDR3L_VAL) + /* increase NVCC_DRAM_1V35 to 1.35v for DDR3L */ + pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x37); +#endif + + /* lock the PMIC regs */ + pmic_reg_write(p, BD71837_REGLOCK, 0x11); + + return 0; +} +#endif + +void spl_board_init(void) +{ + enable_tzc380(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + /* DDR initialization */ + spl_dram_init(); + +#ifndef CONFIG_SPL_USB_SDP_SUPPORT + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } +#endif + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8mq_aiy/Kconfig b/board/freescale/imx8mq_aiy/Kconfig new file mode 100644 index 00000000000..7d907362732 --- /dev/null +++ b/board/freescale/imx8mq_aiy/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8MQ_AIY + +config SYS_BOARD + default "imx8mq_aiy" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mq_aiy" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8mq_aiy/Makefile b/board/freescale/imx8mq_aiy/Makefile new file mode 100644 index 00000000000..90b0ffefc72 --- /dev/null +++ b/board/freescale/imx8mq_aiy/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2016 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8m_aiy.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += ddr/lpddr4_timing_micron_3g.o +obj-$(CONFIG_IMX8M_LPDDR4) += ddr/lpddr4_timing_1g.o +endif diff --git a/board/freescale/imx8mq_aiy/ddr/lpddr4_timing_1g.c b/board/freescale/imx8mq_aiy/ddr/lpddr4_timing_1g.c new file mode 100755 index 00000000000..fb7dea73681 --- /dev/null +++ b/board/freescale/imx8mq_aiy/ddr/lpddr4_timing_1g.c @@ -0,0 +1,1734 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304,0x1}, + {0x3d400030,0x1}, + {0x3d400000,0xa1080020}, + {0x3d400028,0x0}, + {0x3d400020,0x203}, + {0x3d400024,0x3e800}, + {0x3d400064,0x610090}, + {0x3d4000d0,0xc003061c}, + {0x3d4000d4,0x9e0000}, + {0x3d4000dc,0xd4002d}, + {0x3d4000e0,0x310008}, + {0x3d4000e8,0x66004a}, + {0x3d4000ec,0x16004a}, + {0x3d400100,0x1a201b22}, + {0x3d400104,0x60633}, + {0x3d40010c,0xc0c000}, + {0x3d400110,0xf04080f}, + {0x3d400114,0x2040c0c}, + {0x3d400118,0x1010007}, + {0x3d40011c,0x401}, + {0x3d400130,0x20600}, + {0x3d400134,0xc100002}, + {0x3d400138,0x96}, + {0x3d400144,0xa00050}, + {0x3d400180,0xc3200018}, + {0x3d400184,0x28061a8}, + {0x3d400188,0x0}, + {0x3d400190,0x497820a}, + {0x3d400194,0x80303}, + {0x3d4001a0,0xe0400018}, + {0x3d4001a4,0xdf00e4}, + {0x3d4001a8,0x80000000}, + {0x3d4001b0,0x11}, + {0x3d4001b4,0x170a}, + {0x3d4001c0,0x1}, + {0x3d4001c4,0x1}, + {0x3d4000f4,0x639}, + {0x3d400108,0x70e1617}, + {0x3d400200,0x1f}, + {0x3d40020c,0x0}, + {0x3d400210,0x1f1f}, + {0x3d400204,0x80808}, + {0x3d400214,0x7070707}, + {0x3d400218,0xf070707}, + {0x3d402020,0x1}, + {0x3d402024,0xd0c0}, + {0x3d402050,0x20d040}, + {0x3d402064,0x14001f}, + {0x3d4020dc,0x940009}, + {0x3d4020e0,0x310000}, + {0x3d4020e8,0x66004a}, + {0x3d4020ec,0x16004a}, + {0x3d402100,0xb070508}, + {0x3d402104,0x3040b}, + {0x3d402108,0x305090c}, + {0x3d40210c,0x505000}, + {0x3d402110,0x4040204}, + {0x3d402114,0x2030303}, + {0x3d402118,0x1010004}, + {0x3d40211c,0x301}, + {0x3d402130,0x20300}, + {0x3d402134,0xa100002}, + {0x3d402138,0x20}, + {0x3d402144,0x220011}, + {0x3d402180,0xc0a70006}, + {0x3d402190,0x3858202}, + {0x3d402194,0x80303}, + {0x3d4021b4,0x502}, + {0x3d400244,0x0}, + {0x3d400250,0x29001505}, + {0x3d400254,0x2c}, + {0x3d40025c,0x5900575b}, + {0x3d400264,0x90000096}, + {0x3d40026c,0x1000012c}, + {0x3d400300,0x16}, + {0x3d400304,0x0}, + {0x3d40030c,0x0}, + {0x3d400320,0x1}, + {0x3d40036c,0x11}, + {0x3d400400,0x111}, + {0x3d400404,0x10f3}, + {0x3d400408,0x72ff}, + {0x3d400490,0x1}, + {0x3d400494,0xe00}, + {0x3d400498,0x62ffff}, + {0x3d40049c,0xe00}, + {0x3d4004a0,0xffff}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0,0x0}, + {0x100a1,0x1}, + {0x100a2,0x2}, + {0x100a3,0x3}, + {0x100a4,0x4}, + {0x100a5,0x5}, + {0x100a6,0x6}, + {0x100a7,0x7}, + {0x110a0,0x0}, + {0x110a1,0x1}, + {0x110a2,0x2}, + {0x110a3,0x3}, + {0x110a4,0x4}, + {0x110a5,0x5}, + {0x110a6,0x6}, + {0x110a7,0x7}, + {0x120a0,0x0}, + {0x120a1,0x1}, + {0x120a2,0x2}, + {0x120a3,0x3}, + {0x120a4,0x4}, + {0x120a5,0x5}, + {0x120a6,0x6}, + {0x120a7,0x7}, + {0x130a0,0x0}, + {0x130a1,0x1}, + {0x130a2,0x2}, + {0x130a3,0x3}, + {0x130a4,0x4}, + {0x130a5,0x5}, + {0x130a6,0x6}, + {0x130a7,0x7}, + {0x20110,0x2}, + {0x20111,0x3}, + {0x20112,0x4}, + {0x20113,0x5}, + {0x20114,0x0}, + {0x20115,0x1}, + {0x1005f,0x1ff}, + {0x1015f,0x1ff}, + {0x1105f,0x1ff}, + {0x1115f,0x1ff}, + {0x1205f,0x1ff}, + {0x1215f,0x1ff}, + {0x1305f,0x1ff}, + {0x1315f,0x1ff}, + {0x11005f,0x1ff}, + {0x11015f,0x1ff}, + {0x11105f,0x1ff}, + {0x11115f,0x1ff}, + {0x11205f,0x1ff}, + {0x11215f,0x1ff}, + {0x11305f,0x1ff}, + {0x11315f,0x1ff}, + {0x55,0x1ff}, + {0x1055,0x1ff}, + {0x2055,0x1ff}, + {0x3055,0x1ff}, + {0x4055,0x1ff}, + {0x5055,0x1ff}, + {0x6055,0x1ff}, + {0x7055,0x1ff}, + {0x8055,0x1ff}, + {0x9055,0x1ff}, + {0x200c5,0x19}, + {0x1200c5,0x7}, + {0x2002e,0x2}, + {0x12002e,0x1}, + {0x90204,0x0}, + {0x190204,0x0}, + {0x20024,0x1ab}, + {0x2003a,0x0}, + {0x120024,0x1ab}, + {0x2003a,0x0}, + {0x20056,0x3}, + {0x120056,0xa}, + {0x1004d,0xe00}, + {0x1014d,0xe00}, + {0x1104d,0xe00}, + {0x1114d,0xe00}, + {0x1204d,0xe00}, + {0x1214d,0xe00}, + {0x1304d,0xe00}, + {0x1314d,0xe00}, + {0x11004d,0xe00}, + {0x11014d,0xe00}, + {0x11104d,0xe00}, + {0x11114d,0xe00}, + {0x11204d,0xe00}, + {0x11214d,0xe00}, + {0x11304d,0xe00}, + {0x11314d,0xe00}, + {0x10049,0xeba}, + {0x10149,0xeba}, + {0x11049,0xeba}, + {0x11149,0xeba}, + {0x12049,0xeba}, + {0x12149,0xeba}, + {0x13049,0xeba}, + {0x13149,0xeba}, + {0x110049,0xeba}, + {0x110149,0xeba}, + {0x111049,0xeba}, + {0x111149,0xeba}, + {0x112049,0xeba}, + {0x112149,0xeba}, + {0x113049,0xeba}, + {0x113149,0xeba}, + {0x43,0xe7}, + {0x1043,0xe7}, + {0x2043,0xe7}, + {0x3043,0xe7}, + {0x4043,0xe7}, + {0x5043,0xe7}, + {0x6043,0xe7}, + {0x7043,0xe7}, + {0x8043,0xe7}, + {0x9043,0xe7}, + {0x20018,0x3}, + {0x20075,0x4}, + {0x20050,0x0}, + {0x20008,0x320}, + {0x120008,0xa7}, + {0x20088,0x9}, + {0x200b2,0xdc}, + {0x10043,0x5a1}, + {0x10143,0x5a1}, + {0x11043,0x5a1}, + {0x11143,0x5a1}, + {0x12043,0x5a1}, + {0x12143,0x5a1}, + {0x13043,0x5a1}, + {0x13143,0x5a1}, + {0x1200b2,0xdc}, + {0x110043,0x5a1}, + {0x110143,0x5a1}, + {0x111043,0x5a1}, + {0x111143,0x5a1}, + {0x112043,0x5a1}, + {0x112143,0x5a1}, + {0x113043,0x5a1}, + {0x113143,0x5a1}, + {0x200fa,0x1}, + {0x1200fa,0x1}, + {0x20019,0x1}, + {0x120019,0x1}, + {0x200f0,0x0}, + {0x200f1,0x0}, + {0x200f2,0x4444}, + {0x200f3,0x8888}, + {0x200f4,0x5555}, + {0x200f5,0x0}, + {0x200f6,0x0}, + {0x200f7,0xf000}, + {0x20025,0x0}, + {0x2002d,0x0}, + {0x12002d,0x0}, + {0x200c7,0x80}, + {0x1200c7,0x80}, + {0x200ca,0x106}, + {0x1200ca,0x106}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xc80}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x131f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x1}, + {0x54003,0x29c}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x994}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x994}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0x9400}, + {0x54033,0x3109}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0x9400}, + {0x54039,0x3109}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xc80}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x61}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400f,0x100}, + {0x54010,0x1f7f}, + {0x54012,0x110}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000,0x10}, + {0x90001,0x400}, + {0x90002,0x10e}, + {0x90003,0x0}, + {0x90004,0x0}, + {0x90005,0x8}, + {0x90029,0xb}, + {0x9002a,0x480}, + {0x9002b,0x109}, + {0x9002c,0x8}, + {0x9002d,0x448}, + {0x9002e,0x139}, + {0x9002f,0x8}, + {0x90030,0x478}, + {0x90031,0x109}, + {0x90032,0x0}, + {0x90033,0xe8}, + {0x90034,0x109}, + {0x90035,0x2}, + {0x90036,0x10}, + {0x90037,0x139}, + {0x90038,0xf}, + {0x90039,0x7c0}, + {0x9003a,0x139}, + {0x9003b,0x44}, + {0x9003c,0x630}, + {0x9003d,0x159}, + {0x9003e,0x14f}, + {0x9003f,0x630}, + {0x90040,0x159}, + {0x90041,0x47}, + {0x90042,0x630}, + {0x90043,0x149}, + {0x90044,0x4f}, + {0x90045,0x630}, + {0x90046,0x179}, + {0x90047,0x8}, + {0x90048,0xe0}, + {0x90049,0x109}, + {0x9004a,0x0}, + {0x9004b,0x7c8}, + {0x9004c,0x109}, + {0x9004d,0x0}, + {0x9004e,0x1}, + {0x9004f,0x8}, + {0x90050,0x0}, + {0x90051,0x45a}, + {0x90052,0x9}, + {0x90053,0x0}, + {0x90054,0x448}, + {0x90055,0x109}, + {0x90056,0x40}, + {0x90057,0x630}, + {0x90058,0x179}, + {0x90059,0x1}, + {0x9005a,0x618}, + {0x9005b,0x109}, + {0x9005c,0x40c0}, + {0x9005d,0x630}, + {0x9005e,0x149}, + {0x9005f,0x8}, + {0x90060,0x4}, + {0x90061,0x48}, + {0x90062,0x4040}, + {0x90063,0x630}, + {0x90064,0x149}, + {0x90065,0x0}, + {0x90066,0x4}, + {0x90067,0x48}, + {0x90068,0x40}, + {0x90069,0x630}, + {0x9006a,0x149}, + {0x9006b,0x10}, + {0x9006c,0x4}, + {0x9006d,0x18}, + {0x9006e,0x0}, + {0x9006f,0x4}, + {0x90070,0x78}, + {0x90071,0x549}, + {0x90072,0x630}, + {0x90073,0x159}, + {0x90074,0xd49}, + {0x90075,0x630}, + {0x90076,0x159}, + {0x90077,0x94a}, + {0x90078,0x630}, + {0x90079,0x159}, + {0x9007a,0x441}, + {0x9007b,0x630}, + {0x9007c,0x149}, + {0x9007d,0x42}, + {0x9007e,0x630}, + {0x9007f,0x149}, + {0x90080,0x1}, + {0x90081,0x630}, + {0x90082,0x149}, + {0x90083,0x0}, + {0x90084,0xe0}, + {0x90085,0x109}, + {0x90086,0xa}, + {0x90087,0x10}, + {0x90088,0x109}, + {0x90089,0x9}, + {0x9008a,0x3c0}, + {0x9008b,0x149}, + {0x9008c,0x9}, + {0x9008d,0x3c0}, + {0x9008e,0x159}, + {0x9008f,0x18}, + {0x90090,0x10}, + {0x90091,0x109}, + {0x90092,0x0}, + {0x90093,0x3c0}, + {0x90094,0x109}, + {0x90095,0x18}, + {0x90096,0x4}, + {0x90097,0x48}, + {0x90098,0x18}, + {0x90099,0x4}, + {0x9009a,0x58}, + {0x9009b,0xa}, + {0x9009c,0x10}, + {0x9009d,0x109}, + {0x9009e,0x2}, + {0x9009f,0x10}, + {0x900a0,0x109}, + {0x900a1,0x5}, + {0x900a2,0x7c0}, + {0x900a3,0x109}, + {0x900a4,0x10}, + {0x900a5,0x10}, + {0x900a6,0x109}, + {0x40000,0x811}, + {0x40020,0x880}, + {0x40040,0x0}, + {0x40060,0x0}, + {0x40001,0x4008}, + {0x40021,0x83}, + {0x40041,0x4f}, + {0x40061,0x0}, + {0x40002,0x4040}, + {0x40022,0x83}, + {0x40042,0x51}, + {0x40062,0x0}, + {0x40003,0x811}, + {0x40023,0x880}, + {0x40043,0x0}, + {0x40063,0x0}, + {0x40004,0x720}, + {0x40024,0xf}, + {0x40044,0x1740}, + {0x40064,0x0}, + {0x40005,0x16}, + {0x40025,0x83}, + {0x40045,0x4b}, + {0x40065,0x0}, + {0x40006,0x716}, + {0x40026,0xf}, + {0x40046,0x2001}, + {0x40066,0x0}, + {0x40007,0x716}, + {0x40027,0xf}, + {0x40047,0x2800}, + {0x40067,0x0}, + {0x40008,0x716}, + {0x40028,0xf}, + {0x40048,0xf00}, + {0x40068,0x0}, + {0x40009,0x720}, + {0x40029,0xf}, + {0x40049,0x1400}, + {0x40069,0x0}, + {0x4000a,0xe08}, + {0x4002a,0xc15}, + {0x4004a,0x0}, + {0x4006a,0x0}, + {0x4000b,0x623}, + {0x4002b,0x15}, + {0x4004b,0x0}, + {0x4006b,0x0}, + {0x4000c,0x4028}, + {0x4002c,0x80}, + {0x4004c,0x0}, + {0x4006c,0x0}, + {0x4000d,0xe08}, + {0x4002d,0xc1a}, + {0x4004d,0x0}, + {0x4006d,0x0}, + {0x4000e,0x623}, + {0x4002e,0x1a}, + {0x4004e,0x0}, + {0x4006e,0x0}, + {0x4000f,0x4040}, + {0x4002f,0x80}, + {0x4004f,0x0}, + {0x4006f,0x0}, + {0x40010,0x2604}, + {0x40030,0x15}, + {0x40050,0x0}, + {0x40070,0x0}, + {0x40011,0x708}, + {0x40031,0x5}, + {0x40051,0x0}, + {0x40071,0x2002}, + {0x40012,0x8}, + {0x40032,0x80}, + {0x40052,0x0}, + {0x40072,0x0}, + {0x40013,0x2604}, + {0x40033,0x1a}, + {0x40053,0x0}, + {0x40073,0x0}, + {0x40014,0x708}, + {0x40034,0xa}, + {0x40054,0x0}, + {0x40074,0x2002}, + {0x40015,0x4040}, + {0x40035,0x80}, + {0x40055,0x0}, + {0x40075,0x0}, + {0x40016,0x60a}, + {0x40036,0x15}, + {0x40056,0x1200}, + {0x40076,0x0}, + {0x40017,0x61a}, + {0x40037,0x15}, + {0x40057,0x1300}, + {0x40077,0x0}, + {0x40018,0x60a}, + {0x40038,0x1a}, + {0x40058,0x1200}, + {0x40078,0x0}, + {0x40019,0x642}, + {0x40039,0x1a}, + {0x40059,0x1300}, + {0x40079,0x0}, + {0x4001a,0x4808}, + {0x4003a,0x880}, + {0x4005a,0x0}, + {0x4007a,0x0}, + {0x900a7,0x0}, + {0x900a8,0x790}, + {0x900a9,0x11a}, + {0x900aa,0x8}, + {0x900ab,0x7aa}, + {0x900ac,0x2a}, + {0x900ad,0x10}, + {0x900ae,0x7b2}, + {0x900af,0x2a}, + {0x900b0,0x0}, + {0x900b1,0x7c8}, + {0x900b2,0x109}, + {0x900b3,0x10}, + {0x900b4,0x2a8}, + {0x900b5,0x129}, + {0x900b6,0x8}, + {0x900b7,0x370}, + {0x900b8,0x129}, + {0x900b9,0xa}, + {0x900ba,0x3c8}, + {0x900bb,0x1a9}, + {0x900bc,0xc}, + {0x900bd,0x408}, + {0x900be,0x199}, + {0x900bf,0x14}, + {0x900c0,0x790}, + {0x900c1,0x11a}, + {0x900c2,0x8}, + {0x900c3,0x4}, + {0x900c4,0x18}, + {0x900c5,0xe}, + {0x900c6,0x408}, + {0x900c7,0x199}, + {0x900c8,0x8}, + {0x900c9,0x8568}, + {0x900ca,0x108}, + {0x900cb,0x18}, + {0x900cc,0x790}, + {0x900cd,0x16a}, + {0x900ce,0x8}, + {0x900cf,0x1d8}, + {0x900d0,0x169}, + {0x900d1,0x10}, + {0x900d2,0x8558}, + {0x900d3,0x168}, + {0x900d4,0x70}, + {0x900d5,0x788}, + {0x900d6,0x16a}, + {0x900d7,0x1ff8}, + {0x900d8,0x85a8}, + {0x900d9,0x1e8}, + {0x900da,0x50}, + {0x900db,0x798}, + {0x900dc,0x16a}, + {0x900dd,0x60}, + {0x900de,0x7a0}, + {0x900df,0x16a}, + {0x900e0,0x8}, + {0x900e1,0x8310}, + {0x900e2,0x168}, + {0x900e3,0x8}, + {0x900e4,0xa310}, + {0x900e5,0x168}, + {0x900e6,0xa}, + {0x900e7,0x408}, + {0x900e8,0x169}, + {0x900e9,0x6e}, + {0x900ea,0x0}, + {0x900eb,0x68}, + {0x900ec,0x0}, + {0x900ed,0x408}, + {0x900ee,0x169}, + {0x900ef,0x0}, + {0x900f0,0x8310}, + {0x900f1,0x168}, + {0x900f2,0x0}, + {0x900f3,0xa310}, + {0x900f4,0x168}, + {0x900f5,0x1ff8}, + {0x900f6,0x85a8}, + {0x900f7,0x1e8}, + {0x900f8,0x68}, + {0x900f9,0x798}, + {0x900fa,0x16a}, + {0x900fb,0x78}, + {0x900fc,0x7a0}, + {0x900fd,0x16a}, + {0x900fe,0x68}, + {0x900ff,0x790}, + {0x90100,0x16a}, + {0x90101,0x8}, + {0x90102,0x8b10}, + {0x90103,0x168}, + {0x90104,0x8}, + {0x90105,0xab10}, + {0x90106,0x168}, + {0x90107,0xa}, + {0x90108,0x408}, + {0x90109,0x169}, + {0x9010a,0x58}, + {0x9010b,0x0}, + {0x9010c,0x68}, + {0x9010d,0x0}, + {0x9010e,0x408}, + {0x9010f,0x169}, + {0x90110,0x0}, + {0x90111,0x8b10}, + {0x90112,0x168}, + {0x90113,0x0}, + {0x90114,0xab10}, + {0x90115,0x168}, + {0x90116,0x0}, + {0x90117,0x1d8}, + {0x90118,0x169}, + {0x90119,0x80}, + {0x9011a,0x790}, + {0x9011b,0x16a}, + {0x9011c,0x18}, + {0x9011d,0x7aa}, + {0x9011e,0x6a}, + {0x9011f,0xa}, + {0x90120,0x0}, + {0x90121,0x1e9}, + {0x90122,0x8}, + {0x90123,0x8080}, + {0x90124,0x108}, + {0x90125,0xf}, + {0x90126,0x408}, + {0x90127,0x169}, + {0x90128,0xc}, + {0x90129,0x0}, + {0x9012a,0x68}, + {0x9012b,0x9}, + {0x9012c,0x0}, + {0x9012d,0x1a9}, + {0x9012e,0x0}, + {0x9012f,0x408}, + {0x90130,0x169}, + {0x90131,0x0}, + {0x90132,0x8080}, + {0x90133,0x108}, + {0x90134,0x8}, + {0x90135,0x7aa}, + {0x90136,0x6a}, + {0x90137,0x0}, + {0x90138,0x8568}, + {0x90139,0x108}, + {0x9013a,0xb7}, + {0x9013b,0x790}, + {0x9013c,0x16a}, + {0x9013d,0x1f}, + {0x9013e,0x0}, + {0x9013f,0x68}, + {0x90140,0x8}, + {0x90141,0x8558}, + {0x90142,0x168}, + {0x90143,0xf}, + {0x90144,0x408}, + {0x90145,0x169}, + {0x90146,0xc}, + {0x90147,0x0}, + {0x90148,0x68}, + {0x90149,0x0}, + {0x9014a,0x408}, + {0x9014b,0x169}, + {0x9014c,0x0}, + {0x9014d,0x8558}, + {0x9014e,0x168}, + {0x9014f,0x8}, + {0x90150,0x3c8}, + {0x90151,0x1a9}, + {0x90152,0x3}, + {0x90153,0x370}, + {0x90154,0x129}, + {0x90155,0x20}, + {0x90156,0x2aa}, + {0x90157,0x9}, + {0x90158,0x0}, + {0x90159,0x400}, + {0x9015a,0x10e}, + {0x9015b,0x8}, + {0x9015c,0xe8}, + {0x9015d,0x109}, + {0x9015e,0x0}, + {0x9015f,0x8140}, + {0x90160,0x10c}, + {0x90161,0x10}, + {0x90162,0x8138}, + {0x90163,0x10c}, + {0x90164,0x8}, + {0x90165,0x7c8}, + {0x90166,0x101}, + {0x90167,0x8}, + {0x90168,0x0}, + {0x90169,0x8}, + {0x9016a,0x8}, + {0x9016b,0x448}, + {0x9016c,0x109}, + {0x9016d,0xf}, + {0x9016e,0x7c0}, + {0x9016f,0x109}, + {0x90170,0x0}, + {0x90171,0xe8}, + {0x90172,0x109}, + {0x90173,0x47}, + {0x90174,0x630}, + {0x90175,0x109}, + {0x90176,0x8}, + {0x90177,0x618}, + {0x90178,0x109}, + {0x90179,0x8}, + {0x9017a,0xe0}, + {0x9017b,0x109}, + {0x9017c,0x0}, + {0x9017d,0x7c8}, + {0x9017e,0x109}, + {0x9017f,0x8}, + {0x90180,0x8140}, + {0x90181,0x10c}, + {0x90182,0x0}, + {0x90183,0x1}, + {0x90184,0x8}, + {0x90185,0x8}, + {0x90186,0x4}, + {0x90187,0x8}, + {0x90188,0x8}, + {0x90189,0x7c8}, + {0x9018a,0x101}, + {0x90006,0x0}, + {0x90007,0x0}, + {0x90008,0x8}, + {0x90009,0x0}, + {0x9000a,0x0}, + {0x9000b,0x0}, + {0xd00e7,0x400}, + {0x90017,0x0}, + {0x9001f,0x2a}, + {0x90026,0x6a}, + {0x400d0,0x0}, + {0x400d1,0x101}, + {0x400d2,0x105}, + {0x400d3,0x107}, + {0x400d4,0x10f}, + {0x400d5,0x202}, + {0x400d6,0x20a}, + {0x400d7,0x20b}, + {0x2003a,0x2}, + {0x2000b,0x64}, + {0x2000c,0xc8}, + {0x2000d,0x7d0}, + {0x2000e,0x2c}, + {0x12000b,0x14}, + {0x12000c,0x29}, + {0x12000d,0x1a1}, + {0x12000e,0x10}, + {0x9000c,0x0}, + {0x9000d,0x173}, + {0x9000e,0x60}, + {0x9000f,0x6110}, + {0x90010,0x2152}, + {0x90011,0xdfbd}, + {0x90012,0x60}, + {0x90013,0x6152}, + {0x20010,0x5a}, + {0x20011,0x3}, + {0x120010,0x5a}, + {0x120011,0x3}, + {0x40080,0xe0}, + {0x40081,0x12}, + {0x40082,0xe0}, + {0x40083,0x12}, + {0x40084,0xe0}, + {0x40085,0x12}, + {0x140080,0xe0}, + {0x140081,0x12}, + {0x140082,0xe0}, + {0x140083,0x12}, + {0x140084,0xe0}, + {0x140085,0x12}, + {0x400fd,0xf}, + {0x10011,0x1}, + {0x10012,0x1}, + {0x10013,0x180}, + {0x10018,0x1}, + {0x10002,0x6209}, + {0x100b2,0x1}, + {0x101b4,0x1}, + {0x102b4,0x1}, + {0x103b4,0x1}, + {0x104b4,0x1}, + {0x105b4,0x1}, + {0x106b4,0x1}, + {0x107b4,0x1}, + {0x108b4,0x1}, + {0x11011,0x1}, + {0x11012,0x1}, + {0x11013,0x180}, + {0x11018,0x1}, + {0x11002,0x6209}, + {0x110b2,0x1}, + {0x111b4,0x1}, + {0x112b4,0x1}, + {0x113b4,0x1}, + {0x114b4,0x1}, + {0x115b4,0x1}, + {0x116b4,0x1}, + {0x117b4,0x1}, + {0x118b4,0x1}, + {0x12011,0x1}, + {0x12012,0x1}, + {0x12013,0x180}, + {0x12018,0x1}, + {0x12002,0x6209}, + {0x120b2,0x1}, + {0x121b4,0x1}, + {0x122b4,0x1}, + {0x123b4,0x1}, + {0x124b4,0x1}, + {0x125b4,0x1}, + {0x126b4,0x1}, + {0x127b4,0x1}, + {0x128b4,0x1}, + {0x13011,0x1}, + {0x13012,0x1}, + {0x13013,0x180}, + {0x13018,0x1}, + {0x13002,0x6209}, + {0x130b2,0x1}, + {0x131b4,0x1}, + {0x132b4,0x1}, + {0x133b4,0x1}, + {0x134b4,0x1}, + {0x135b4,0x1}, + {0x136b4,0x1}, + {0x137b4,0x1}, + {0x138b4,0x1}, + {0x2003a,0x2}, + {0xc0080,0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1g = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 667, }, +}; + diff --git a/board/freescale/imx8mq_aiy/ddr/lpddr4_timing_micron_3g.c b/board/freescale/imx8mq_aiy/ddr/lpddr4_timing_micron_3g.c new file mode 100755 index 00000000000..e9a995975f6 --- /dev/null +++ b/board/freescale/imx8mq_aiy/ddr/lpddr4_timing_micron_3g.c @@ -0,0 +1,1734 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304,0x1}, + {0x3d400030,0x1}, + {0x3d400000,0xa3080020}, + {0x3d400028,0x0}, + {0x3d400020,0x203}, + {0x3d400024,0x3e800}, + {0x3d400064,0x6100e0}, + {0x3d4000d0,0xc003061c}, + {0x3d4000d4,0x9e0000}, + {0x3d4000dc,0xd4002d}, + {0x3d4000e0,0x310008}, + {0x3d4000e8,0x66004a}, + {0x3d4000ec,0x16004a}, + {0x3d400100,0x1a201b22}, + {0x3d400104,0x60633}, + {0x3d40010c,0xc0c000}, + {0x3d400110,0xf04080f}, + {0x3d400114,0x2040c0c}, + {0x3d400118,0x1010007}, + {0x3d40011c,0x401}, + {0x3d400130,0x20600}, + {0x3d400134,0xc100002}, + {0x3d400138,0xe6}, + {0x3d400144,0xa00050}, + {0x3d400180,0xc3200018}, + {0x3d400184,0x28061a8}, + {0x3d400188,0x0}, + {0x3d400190,0x497820a}, + {0x3d400194,0x80303}, + {0x3d4001a0,0xe0400018}, + {0x3d4001a4,0xdf00e4}, + {0x3d4001a8,0x80000000}, + {0x3d4001b0,0x11}, + {0x3d4001b4,0x170a}, + {0x3d4001c0,0x1}, + {0x3d4001c4,0x1}, + {0x3d4000f4,0x639}, + {0x3d400108,0x70e1617}, + {0x3d400200,0x15}, + {0x3d40020c,0x0}, + {0x3d400210,0x1f1f}, + {0x3d400204,0x80808}, + {0x3d400214,0x7070707}, + {0x3d400218,0x48080707}, + {0x3d402020,0x1}, + {0x3d402024,0xd0c0}, + {0x3d402050,0x20d040}, + {0x3d402064,0x14002f}, + {0x3d4020dc,0x940009}, + {0x3d4020e0,0x310000}, + {0x3d4020e8,0x66004a}, + {0x3d4020ec,0x16004a}, + {0x3d402100,0xb070508}, + {0x3d402104,0x3040b}, + {0x3d402108,0x305090c}, + {0x3d40210c,0x505000}, + {0x3d402110,0x4040204}, + {0x3d402114,0x2030303}, + {0x3d402118,0x1010004}, + {0x3d40211c,0x301}, + {0x3d402130,0x20300}, + {0x3d402134,0xa100002}, + {0x3d402138,0x31}, + {0x3d402144,0x220011}, + {0x3d402180,0xc0a70006}, + {0x3d402190,0x3858202}, + {0x3d402194,0x80303}, + {0x3d4021b4,0x502}, + {0x3d400244,0x0}, + {0x3d400250,0x29001505}, + {0x3d400254,0x2c}, + {0x3d40025c,0x5900575b}, + {0x3d400264,0x90000096}, + {0x3d40026c,0x1000012c}, + {0x3d400300,0x16}, + {0x3d400304,0x0}, + {0x3d40030c,0x0}, + {0x3d400320,0x1}, + {0x3d40036c,0x11}, + {0x3d400400,0x111}, + {0x3d400404,0x10f3}, + {0x3d400408,0x72ff}, + {0x3d400490,0x1}, + {0x3d400494,0xe00}, + {0x3d400498,0x62ffff}, + {0x3d40049c,0xe00}, + {0x3d4004a0,0xffff}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0,0x0}, + {0x100a1,0x1}, + {0x100a2,0x2}, + {0x100a3,0x3}, + {0x100a4,0x4}, + {0x100a5,0x5}, + {0x100a6,0x6}, + {0x100a7,0x7}, + {0x110a0,0x0}, + {0x110a1,0x1}, + {0x110a2,0x2}, + {0x110a3,0x3}, + {0x110a4,0x4}, + {0x110a5,0x5}, + {0x110a6,0x6}, + {0x110a7,0x7}, + {0x120a0,0x0}, + {0x120a1,0x1}, + {0x120a2,0x2}, + {0x120a3,0x3}, + {0x120a4,0x4}, + {0x120a5,0x5}, + {0x120a6,0x6}, + {0x120a7,0x7}, + {0x130a0,0x0}, + {0x130a1,0x1}, + {0x130a2,0x2}, + {0x130a3,0x3}, + {0x130a4,0x4}, + {0x130a5,0x5}, + {0x130a6,0x6}, + {0x130a7,0x7}, + {0x20110,0x2}, + {0x20111,0x3}, + {0x20112,0x4}, + {0x20113,0x5}, + {0x20114,0x0}, + {0x20115,0x1}, + {0x1005f,0x1ff}, + {0x1015f,0x1ff}, + {0x1105f,0x1ff}, + {0x1115f,0x1ff}, + {0x1205f,0x1ff}, + {0x1215f,0x1ff}, + {0x1305f,0x1ff}, + {0x1315f,0x1ff}, + {0x11005f,0x1ff}, + {0x11015f,0x1ff}, + {0x11105f,0x1ff}, + {0x11115f,0x1ff}, + {0x11205f,0x1ff}, + {0x11215f,0x1ff}, + {0x11305f,0x1ff}, + {0x11315f,0x1ff}, + {0x55,0x1ff}, + {0x1055,0x1ff}, + {0x2055,0x1ff}, + {0x3055,0x1ff}, + {0x4055,0x1ff}, + {0x5055,0x1ff}, + {0x6055,0x1ff}, + {0x7055,0x1ff}, + {0x8055,0x1ff}, + {0x9055,0x1ff}, + {0x200c5,0x19}, + {0x1200c5,0x7}, + {0x2002e,0x2}, + {0x12002e,0x1}, + {0x90204,0x0}, + {0x190204,0x0}, + {0x20024,0x1ab}, + {0x2003a,0x0}, + {0x120024,0x1ab}, + {0x2003a,0x0}, + {0x20056,0x3}, + {0x120056,0xa}, + {0x1004d,0xe00}, + {0x1014d,0xe00}, + {0x1104d,0xe00}, + {0x1114d,0xe00}, + {0x1204d,0xe00}, + {0x1214d,0xe00}, + {0x1304d,0xe00}, + {0x1314d,0xe00}, + {0x11004d,0xe00}, + {0x11014d,0xe00}, + {0x11104d,0xe00}, + {0x11114d,0xe00}, + {0x11204d,0xe00}, + {0x11214d,0xe00}, + {0x11304d,0xe00}, + {0x11314d,0xe00}, + {0x10049,0xeba}, + {0x10149,0xeba}, + {0x11049,0xeba}, + {0x11149,0xeba}, + {0x12049,0xeba}, + {0x12149,0xeba}, + {0x13049,0xeba}, + {0x13149,0xeba}, + {0x110049,0xeba}, + {0x110149,0xeba}, + {0x111049,0xeba}, + {0x111149,0xeba}, + {0x112049,0xeba}, + {0x112149,0xeba}, + {0x113049,0xeba}, + {0x113149,0xeba}, + {0x43,0x63}, + {0x1043,0x63}, + {0x2043,0x63}, + {0x3043,0x63}, + {0x4043,0x63}, + {0x5043,0x63}, + {0x6043,0x63}, + {0x7043,0x63}, + {0x8043,0x63}, + {0x9043,0x63}, + {0x20018,0x3}, + {0x20075,0x4}, + {0x20050,0x0}, + {0x20008,0x320}, + {0x120008,0xa7}, + {0x20088,0x9}, + {0x200b2,0xdc}, + {0x10043,0x5a1}, + {0x10143,0x5a1}, + {0x11043,0x5a1}, + {0x11143,0x5a1}, + {0x12043,0x5a1}, + {0x12143,0x5a1}, + {0x13043,0x5a1}, + {0x13143,0x5a1}, + {0x1200b2,0xdc}, + {0x110043,0x5a1}, + {0x110143,0x5a1}, + {0x111043,0x5a1}, + {0x111143,0x5a1}, + {0x112043,0x5a1}, + {0x112143,0x5a1}, + {0x113043,0x5a1}, + {0x113143,0x5a1}, + {0x200fa,0x1}, + {0x1200fa,0x1}, + {0x20019,0x1}, + {0x120019,0x1}, + {0x200f0,0x0}, + {0x200f1,0x0}, + {0x200f2,0x4444}, + {0x200f3,0x8888}, + {0x200f4,0x5555}, + {0x200f5,0x0}, + {0x200f6,0x0}, + {0x200f7,0xf000}, + {0x20025,0x0}, + {0x2002d,0x0}, + {0x12002d,0x0}, + {0x200c7,0x80}, + {0x1200c7,0x80}, + {0x200ca,0x106}, + {0x1200ca,0x106}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xc80}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x131f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x310}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x1}, + {0x54003,0x29c}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x310}, + {0x54019,0x994}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x994}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0x9400}, + {0x54033,0x3109}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0x9400}, + {0x54039,0x3109}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xc80}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x61}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400f,0x100}, + {0x54010,0x1f7f}, + {0x54012,0x310}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000,0x10}, + {0x90001,0x400}, + {0x90002,0x10e}, + {0x90003,0x0}, + {0x90004,0x0}, + {0x90005,0x8}, + {0x90029,0xb}, + {0x9002a,0x480}, + {0x9002b,0x109}, + {0x9002c,0x8}, + {0x9002d,0x448}, + {0x9002e,0x139}, + {0x9002f,0x8}, + {0x90030,0x478}, + {0x90031,0x109}, + {0x90032,0x0}, + {0x90033,0xe8}, + {0x90034,0x109}, + {0x90035,0x2}, + {0x90036,0x10}, + {0x90037,0x139}, + {0x90038,0xf}, + {0x90039,0x7c0}, + {0x9003a,0x139}, + {0x9003b,0x44}, + {0x9003c,0x630}, + {0x9003d,0x159}, + {0x9003e,0x14f}, + {0x9003f,0x630}, + {0x90040,0x159}, + {0x90041,0x47}, + {0x90042,0x630}, + {0x90043,0x149}, + {0x90044,0x4f}, + {0x90045,0x630}, + {0x90046,0x179}, + {0x90047,0x8}, + {0x90048,0xe0}, + {0x90049,0x109}, + {0x9004a,0x0}, + {0x9004b,0x7c8}, + {0x9004c,0x109}, + {0x9004d,0x0}, + {0x9004e,0x1}, + {0x9004f,0x8}, + {0x90050,0x0}, + {0x90051,0x45a}, + {0x90052,0x9}, + {0x90053,0x0}, + {0x90054,0x448}, + {0x90055,0x109}, + {0x90056,0x40}, + {0x90057,0x630}, + {0x90058,0x179}, + {0x90059,0x1}, + {0x9005a,0x618}, + {0x9005b,0x109}, + {0x9005c,0x40c0}, + {0x9005d,0x630}, + {0x9005e,0x149}, + {0x9005f,0x8}, + {0x90060,0x4}, + {0x90061,0x48}, + {0x90062,0x4040}, + {0x90063,0x630}, + {0x90064,0x149}, + {0x90065,0x0}, + {0x90066,0x4}, + {0x90067,0x48}, + {0x90068,0x40}, + {0x90069,0x630}, + {0x9006a,0x149}, + {0x9006b,0x10}, + {0x9006c,0x4}, + {0x9006d,0x18}, + {0x9006e,0x0}, + {0x9006f,0x4}, + {0x90070,0x78}, + {0x90071,0x549}, + {0x90072,0x630}, + {0x90073,0x159}, + {0x90074,0xd49}, + {0x90075,0x630}, + {0x90076,0x159}, + {0x90077,0x94a}, + {0x90078,0x630}, + {0x90079,0x159}, + {0x9007a,0x441}, + {0x9007b,0x630}, + {0x9007c,0x149}, + {0x9007d,0x42}, + {0x9007e,0x630}, + {0x9007f,0x149}, + {0x90080,0x1}, + {0x90081,0x630}, + {0x90082,0x149}, + {0x90083,0x0}, + {0x90084,0xe0}, + {0x90085,0x109}, + {0x90086,0xa}, + {0x90087,0x10}, + {0x90088,0x109}, + {0x90089,0x9}, + {0x9008a,0x3c0}, + {0x9008b,0x149}, + {0x9008c,0x9}, + {0x9008d,0x3c0}, + {0x9008e,0x159}, + {0x9008f,0x18}, + {0x90090,0x10}, + {0x90091,0x109}, + {0x90092,0x0}, + {0x90093,0x3c0}, + {0x90094,0x109}, + {0x90095,0x18}, + {0x90096,0x4}, + {0x90097,0x48}, + {0x90098,0x18}, + {0x90099,0x4}, + {0x9009a,0x58}, + {0x9009b,0xa}, + {0x9009c,0x10}, + {0x9009d,0x109}, + {0x9009e,0x2}, + {0x9009f,0x10}, + {0x900a0,0x109}, + {0x900a1,0x5}, + {0x900a2,0x7c0}, + {0x900a3,0x109}, + {0x900a4,0x10}, + {0x900a5,0x10}, + {0x900a6,0x109}, + {0x40000,0x811}, + {0x40020,0x880}, + {0x40040,0x0}, + {0x40060,0x0}, + {0x40001,0x4008}, + {0x40021,0x83}, + {0x40041,0x4f}, + {0x40061,0x0}, + {0x40002,0x4040}, + {0x40022,0x83}, + {0x40042,0x51}, + {0x40062,0x0}, + {0x40003,0x811}, + {0x40023,0x880}, + {0x40043,0x0}, + {0x40063,0x0}, + {0x40004,0x720}, + {0x40024,0xf}, + {0x40044,0x1740}, + {0x40064,0x0}, + {0x40005,0x16}, + {0x40025,0x83}, + {0x40045,0x4b}, + {0x40065,0x0}, + {0x40006,0x716}, + {0x40026,0xf}, + {0x40046,0x2001}, + {0x40066,0x0}, + {0x40007,0x716}, + {0x40027,0xf}, + {0x40047,0x2800}, + {0x40067,0x0}, + {0x40008,0x716}, + {0x40028,0xf}, + {0x40048,0xf00}, + {0x40068,0x0}, + {0x40009,0x720}, + {0x40029,0xf}, + {0x40049,0x1400}, + {0x40069,0x0}, + {0x4000a,0xe08}, + {0x4002a,0xc15}, + {0x4004a,0x0}, + {0x4006a,0x0}, + {0x4000b,0x623}, + {0x4002b,0x15}, + {0x4004b,0x0}, + {0x4006b,0x0}, + {0x4000c,0x4028}, + {0x4002c,0x80}, + {0x4004c,0x0}, + {0x4006c,0x0}, + {0x4000d,0xe08}, + {0x4002d,0xc1a}, + {0x4004d,0x0}, + {0x4006d,0x0}, + {0x4000e,0x623}, + {0x4002e,0x1a}, + {0x4004e,0x0}, + {0x4006e,0x0}, + {0x4000f,0x4040}, + {0x4002f,0x80}, + {0x4004f,0x0}, + {0x4006f,0x0}, + {0x40010,0x2604}, + {0x40030,0x15}, + {0x40050,0x0}, + {0x40070,0x0}, + {0x40011,0x708}, + {0x40031,0x5}, + {0x40051,0x0}, + {0x40071,0x2002}, + {0x40012,0x8}, + {0x40032,0x80}, + {0x40052,0x0}, + {0x40072,0x0}, + {0x40013,0x2604}, + {0x40033,0x1a}, + {0x40053,0x0}, + {0x40073,0x0}, + {0x40014,0x708}, + {0x40034,0xa}, + {0x40054,0x0}, + {0x40074,0x2002}, + {0x40015,0x4040}, + {0x40035,0x80}, + {0x40055,0x0}, + {0x40075,0x0}, + {0x40016,0x60a}, + {0x40036,0x15}, + {0x40056,0x1200}, + {0x40076,0x0}, + {0x40017,0x61a}, + {0x40037,0x15}, + {0x40057,0x1300}, + {0x40077,0x0}, + {0x40018,0x60a}, + {0x40038,0x1a}, + {0x40058,0x1200}, + {0x40078,0x0}, + {0x40019,0x642}, + {0x40039,0x1a}, + {0x40059,0x1300}, + {0x40079,0x0}, + {0x4001a,0x4808}, + {0x4003a,0x880}, + {0x4005a,0x0}, + {0x4007a,0x0}, + {0x900a7,0x0}, + {0x900a8,0x790}, + {0x900a9,0x11a}, + {0x900aa,0x8}, + {0x900ab,0x7aa}, + {0x900ac,0x2a}, + {0x900ad,0x10}, + {0x900ae,0x7b2}, + {0x900af,0x2a}, + {0x900b0,0x0}, + {0x900b1,0x7c8}, + {0x900b2,0x109}, + {0x900b3,0x10}, + {0x900b4,0x2a8}, + {0x900b5,0x129}, + {0x900b6,0x8}, + {0x900b7,0x370}, + {0x900b8,0x129}, + {0x900b9,0xa}, + {0x900ba,0x3c8}, + {0x900bb,0x1a9}, + {0x900bc,0xc}, + {0x900bd,0x408}, + {0x900be,0x199}, + {0x900bf,0x14}, + {0x900c0,0x790}, + {0x900c1,0x11a}, + {0x900c2,0x8}, + {0x900c3,0x4}, + {0x900c4,0x18}, + {0x900c5,0xe}, + {0x900c6,0x408}, + {0x900c7,0x199}, + {0x900c8,0x8}, + {0x900c9,0x8568}, + {0x900ca,0x108}, + {0x900cb,0x18}, + {0x900cc,0x790}, + {0x900cd,0x16a}, + {0x900ce,0x8}, + {0x900cf,0x1d8}, + {0x900d0,0x169}, + {0x900d1,0x10}, + {0x900d2,0x8558}, + {0x900d3,0x168}, + {0x900d4,0x70}, + {0x900d5,0x788}, + {0x900d6,0x16a}, + {0x900d7,0x1ff8}, + {0x900d8,0x85a8}, + {0x900d9,0x1e8}, + {0x900da,0x50}, + {0x900db,0x798}, + {0x900dc,0x16a}, + {0x900dd,0x60}, + {0x900de,0x7a0}, + {0x900df,0x16a}, + {0x900e0,0x8}, + {0x900e1,0x8310}, + {0x900e2,0x168}, + {0x900e3,0x8}, + {0x900e4,0xa310}, + {0x900e5,0x168}, + {0x900e6,0xa}, + {0x900e7,0x408}, + {0x900e8,0x169}, + {0x900e9,0x6e}, + {0x900ea,0x0}, + {0x900eb,0x68}, + {0x900ec,0x0}, + {0x900ed,0x408}, + {0x900ee,0x169}, + {0x900ef,0x0}, + {0x900f0,0x8310}, + {0x900f1,0x168}, + {0x900f2,0x0}, + {0x900f3,0xa310}, + {0x900f4,0x168}, + {0x900f5,0x1ff8}, + {0x900f6,0x85a8}, + {0x900f7,0x1e8}, + {0x900f8,0x68}, + {0x900f9,0x798}, + {0x900fa,0x16a}, + {0x900fb,0x78}, + {0x900fc,0x7a0}, + {0x900fd,0x16a}, + {0x900fe,0x68}, + {0x900ff,0x790}, + {0x90100,0x16a}, + {0x90101,0x8}, + {0x90102,0x8b10}, + {0x90103,0x168}, + {0x90104,0x8}, + {0x90105,0xab10}, + {0x90106,0x168}, + {0x90107,0xa}, + {0x90108,0x408}, + {0x90109,0x169}, + {0x9010a,0x58}, + {0x9010b,0x0}, + {0x9010c,0x68}, + {0x9010d,0x0}, + {0x9010e,0x408}, + {0x9010f,0x169}, + {0x90110,0x0}, + {0x90111,0x8b10}, + {0x90112,0x168}, + {0x90113,0x0}, + {0x90114,0xab10}, + {0x90115,0x168}, + {0x90116,0x0}, + {0x90117,0x1d8}, + {0x90118,0x169}, + {0x90119,0x80}, + {0x9011a,0x790}, + {0x9011b,0x16a}, + {0x9011c,0x18}, + {0x9011d,0x7aa}, + {0x9011e,0x6a}, + {0x9011f,0xa}, + {0x90120,0x0}, + {0x90121,0x1e9}, + {0x90122,0x8}, + {0x90123,0x8080}, + {0x90124,0x108}, + {0x90125,0xf}, + {0x90126,0x408}, + {0x90127,0x169}, + {0x90128,0xc}, + {0x90129,0x0}, + {0x9012a,0x68}, + {0x9012b,0x9}, + {0x9012c,0x0}, + {0x9012d,0x1a9}, + {0x9012e,0x0}, + {0x9012f,0x408}, + {0x90130,0x169}, + {0x90131,0x0}, + {0x90132,0x8080}, + {0x90133,0x108}, + {0x90134,0x8}, + {0x90135,0x7aa}, + {0x90136,0x6a}, + {0x90137,0x0}, + {0x90138,0x8568}, + {0x90139,0x108}, + {0x9013a,0xb7}, + {0x9013b,0x790}, + {0x9013c,0x16a}, + {0x9013d,0x1f}, + {0x9013e,0x0}, + {0x9013f,0x68}, + {0x90140,0x8}, + {0x90141,0x8558}, + {0x90142,0x168}, + {0x90143,0xf}, + {0x90144,0x408}, + {0x90145,0x169}, + {0x90146,0xc}, + {0x90147,0x0}, + {0x90148,0x68}, + {0x90149,0x0}, + {0x9014a,0x408}, + {0x9014b,0x169}, + {0x9014c,0x0}, + {0x9014d,0x8558}, + {0x9014e,0x168}, + {0x9014f,0x8}, + {0x90150,0x3c8}, + {0x90151,0x1a9}, + {0x90152,0x3}, + {0x90153,0x370}, + {0x90154,0x129}, + {0x90155,0x20}, + {0x90156,0x2aa}, + {0x90157,0x9}, + {0x90158,0x0}, + {0x90159,0x400}, + {0x9015a,0x10e}, + {0x9015b,0x8}, + {0x9015c,0xe8}, + {0x9015d,0x109}, + {0x9015e,0x0}, + {0x9015f,0x8140}, + {0x90160,0x10c}, + {0x90161,0x10}, + {0x90162,0x8138}, + {0x90163,0x10c}, + {0x90164,0x8}, + {0x90165,0x7c8}, + {0x90166,0x101}, + {0x90167,0x8}, + {0x90168,0x0}, + {0x90169,0x8}, + {0x9016a,0x8}, + {0x9016b,0x448}, + {0x9016c,0x109}, + {0x9016d,0xf}, + {0x9016e,0x7c0}, + {0x9016f,0x109}, + {0x90170,0x0}, + {0x90171,0xe8}, + {0x90172,0x109}, + {0x90173,0x47}, + {0x90174,0x630}, + {0x90175,0x109}, + {0x90176,0x8}, + {0x90177,0x618}, + {0x90178,0x109}, + {0x90179,0x8}, + {0x9017a,0xe0}, + {0x9017b,0x109}, + {0x9017c,0x0}, + {0x9017d,0x7c8}, + {0x9017e,0x109}, + {0x9017f,0x8}, + {0x90180,0x8140}, + {0x90181,0x10c}, + {0x90182,0x0}, + {0x90183,0x1}, + {0x90184,0x8}, + {0x90185,0x8}, + {0x90186,0x4}, + {0x90187,0x8}, + {0x90188,0x8}, + {0x90189,0x7c8}, + {0x9018a,0x101}, + {0x90006,0x0}, + {0x90007,0x0}, + {0x90008,0x8}, + {0x90009,0x0}, + {0x9000a,0x0}, + {0x9000b,0x0}, + {0xd00e7,0x400}, + {0x90017,0x0}, + {0x9001f,0x2a}, + {0x90026,0x6a}, + {0x400d0,0x0}, + {0x400d1,0x101}, + {0x400d2,0x105}, + {0x400d3,0x107}, + {0x400d4,0x10f}, + {0x400d5,0x202}, + {0x400d6,0x20a}, + {0x400d7,0x20b}, + {0x2003a,0x2}, + {0x2000b,0x64}, + {0x2000c,0xc8}, + {0x2000d,0x7d0}, + {0x2000e,0x2c}, + {0x12000b,0x14}, + {0x12000c,0x29}, + {0x12000d,0x1a1}, + {0x12000e,0x10}, + {0x9000c,0x0}, + {0x9000d,0x173}, + {0x9000e,0x60}, + {0x9000f,0x6110}, + {0x90010,0x2152}, + {0x90011,0xdfbd}, + {0x90012,0x60}, + {0x90013,0x6152}, + {0x20010,0x5a}, + {0x20011,0x3}, + {0x120010,0x5a}, + {0x120011,0x3}, + {0x40080,0xe0}, + {0x40081,0x12}, + {0x40082,0xe0}, + {0x40083,0x12}, + {0x40084,0xe0}, + {0x40085,0x12}, + {0x140080,0xe0}, + {0x140081,0x12}, + {0x140082,0xe0}, + {0x140083,0x12}, + {0x140084,0xe0}, + {0x140085,0x12}, + {0x400fd,0xf}, + {0x10011,0x1}, + {0x10012,0x1}, + {0x10013,0x180}, + {0x10018,0x1}, + {0x10002,0x6209}, + {0x100b2,0x1}, + {0x101b4,0x1}, + {0x102b4,0x1}, + {0x103b4,0x1}, + {0x104b4,0x1}, + {0x105b4,0x1}, + {0x106b4,0x1}, + {0x107b4,0x1}, + {0x108b4,0x1}, + {0x11011,0x1}, + {0x11012,0x1}, + {0x11013,0x180}, + {0x11018,0x1}, + {0x11002,0x6209}, + {0x110b2,0x1}, + {0x111b4,0x1}, + {0x112b4,0x1}, + {0x113b4,0x1}, + {0x114b4,0x1}, + {0x115b4,0x1}, + {0x116b4,0x1}, + {0x117b4,0x1}, + {0x118b4,0x1}, + {0x12011,0x1}, + {0x12012,0x1}, + {0x12013,0x180}, + {0x12018,0x1}, + {0x12002,0x6209}, + {0x120b2,0x1}, + {0x121b4,0x1}, + {0x122b4,0x1}, + {0x123b4,0x1}, + {0x124b4,0x1}, + {0x125b4,0x1}, + {0x126b4,0x1}, + {0x127b4,0x1}, + {0x128b4,0x1}, + {0x13011,0x1}, + {0x13012,0x1}, + {0x13013,0x180}, + {0x13018,0x1}, + {0x13002,0x6209}, + {0x130b2,0x1}, + {0x131b4,0x1}, + {0x132b4,0x1}, + {0x133b4,0x1}, + {0x134b4,0x1}, + {0x135b4,0x1}, + {0x136b4,0x1}, + {0x137b4,0x1}, + {0x138b4,0x1}, + {0x2003a,0x2}, + {0xc0080,0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_micron_3g = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 667, }, +}; + diff --git a/board/freescale/imx8mq_aiy/imx8m_aiy.c b/board/freescale/imx8mq_aiy/imx8m_aiy.c new file mode 100644 index 00000000000..7b8427b2078 --- /dev/null +++ b/board/freescale/imx8mq_aiy/imx8m_aiy.c @@ -0,0 +1,440 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_QSPI +static iomux_v3_cfg_t const qspi_pads[] = { + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); + + set_clk_qspi(); + + return 0; +} +#endif + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + /* TODO */ + return 0; +} +#endif + +/* layout of baseboard id */ +#define IMX8MQ_GPIO3_IO24 IMX_GPIO_NR(3, 24) //board_id[2]:2 +#define IMX8MQ_GPIO3_IO22 IMX_GPIO_NR(3, 22) //board_id[2]:1 +#define IMX8MQ_GPIO3_IO19 IMX_GPIO_NR(3, 19) //board_id[2]:0 + +/* GPIO port description */ +static unsigned long imx8m_gpio_ports[] = { + [0] = GPIO1_BASE_ADDR, + [1] = GPIO2_BASE_ADDR, + [2] = GPIO3_BASE_ADDR, + [3] = GPIO4_BASE_ADDR, + [4] = GPIO5_BASE_ADDR, +}; + +/* use legacy gpio operations before device model is ready. */ +static int gpio_direction_input_legacy(unsigned int gpio) +{ + unsigned int port; + struct gpio_regs *regs; + u32 l; + + port = gpio/32; + + gpio &= 0x1f; + + regs = (struct gpio_regs *)imx8m_gpio_ports[port]; + + l = readl(®s->gpio_dir); + /* set direction as input. */ + l &= ~(1 << gpio); + writel(l, ®s->gpio_dir); + + return 0; +} + +static int gpio_get_value_legacy(unsigned gpio) +{ + unsigned int port; + struct gpio_regs *regs; + u32 val; + + port = gpio/32; + + gpio &= 0x1f; + + regs = (struct gpio_regs *)imx8m_gpio_ports[port]; + + val = (readl(®s->gpio_dr) >> gpio) & 0x01; + + return val; +} + +int get_imx8m_baseboard_id(void) +{ + int i = 0, value = 0; + int baseboard_id; + int pin[3]; + + /* initialize the pin array */ + pin[0] = IMX8MQ_GPIO3_IO19; + pin[1] = IMX8MQ_GPIO3_IO22; + pin[2] = IMX8MQ_GPIO3_IO24; + + /* Set gpio direction as input and get the input value */ + baseboard_id = 0; + for (i = 0; i < 3; i++) { + gpio_direction_input_legacy(pin[i]); + if ((value = gpio_get_value_legacy(pin[i])) < 0) { + printf("Error! Read gpio port: %d failed!\n", pin[i]); + return -1; + } else + baseboard_id |= ((value & 0x01) << i); + } + + return baseboard_id; +} +#ifdef CONFIG_IMX_TRUSTY_OS +int get_tee_load(ulong *load) +{ + int board_id; + + board_id = get_imx8m_baseboard_id(); + /* load TEE to the last 32M of DDR */ + if ((board_id == AIY_MICRON_1G) || + (board_id == AIY_HYNIX_1G)) { + /* for 1G DDR board */ + *load = (ulong)TEE_LOAD_ADDR_1G; + } else { + /* for 3G DDR board */ + *load = (ulong)TEE_LOAD_ADDR_3G; + } + + return 0; +} +#endif + +int dram_init(void) +{ + int baseboard_id; + uint32_t ddr_size = 0; + /* different boards have different DDR type, distinguish the DDR + * type by board id. + */ + baseboard_id = get_imx8m_baseboard_id(); + if ((baseboard_id == AIY_MICRON_1G) || + (baseboard_id == AIY_HYNIX_1G)) { + /* 1G DDR size */ + ddr_size = 0x40000000; + } else{ + /* Default to use 3G DDR size */ + ddr_size = 0xc0000000; + } + + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = ddr_size - rom_pointer[1]; + else + gd->ram_size = ddr_size; + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +#define FEC_RST_PAD IMX_GPIO_NR(1, 9) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(1, 9), 1); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); + return set_clk_enet(ENET_125MHZ); +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_USB_DWC3 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +#define PTN5150A_BUS 2 +#define PTN5150A_ADDR 0x3D +#define PTN5150A_CONTROL 0x2 +#define PTN5150A_CONTROL_PORT_MASK 0x6 + +static struct dwc3_device dwc3_device_data = { +#ifdef CONFIG_SPL_BUILD + .maximum_speed = USB_SPEED_HIGH, +#else + .maximum_speed = USB_SPEED_SUPER, +#endif + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .power_down_scale = 2, +}; + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); +} + +#ifndef CONFIG_SPL_BUILD +static void configure_cc_switch() { + uint8_t value; + int ret; + struct udevice *bus, *dev; + + ret = uclass_get_device_by_seq(UCLASS_I2C, PTN5150A_BUS, &bus); + if (ret) { + printf("%s: No bus %d\n", __func__, PTN5150A_BUS); + return; + } + + ret = dm_i2c_probe(bus, PTN5150A_ADDR, 0, &dev); + if (ret) { + printf("%s: Can't find device id=0x%x, on bus %d\n", + __func__, PTN5150A_ADDR, PTN5150A_BUS); + return; + } + + if (dm_i2c_read(dev, PTN5150A_CONTROL, &value, 1)) { + printf("Unable to configure USB switch"); + return; + } + + value &= ~PTN5150A_CONTROL_PORT_MASK; + if (dm_i2c_write(dev, PTN5150A_CONTROL, &value, 1)) { + printf("Unable to configure USB switch"); + return; + } + printf("Configured USB Switch for UFP\n"); +} +#endif +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) +int board_usb_init(int index, enum usb_init_type init) +{ + imx8m_usb_power(index, true); + +#ifndef CONFIG_SPL_BUILD + /* Explicitly set USB switch to UFP (device) to ensure proper + *fastboot operation on type-C ports. */ + configure_cc_switch(); +#endif + + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_nxp_usb_phy_init(&dwc3_device_data); + return dwc3_uboot_init(&dwc3_device_data); + } + + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_uboot_exit(index); + } + + imx8m_usb_power(index, false); + + return 0; +} +#endif + +int board_init(void) +{ + board_qspi_init(); + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) + init_usb_clk(); +#endif + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "Phanbell"); + env_set("board_rev", "iMX8MQ"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + int baseboard_id; + baseboard_id = get_imx8m_baseboard_id(); + if ((baseboard_id == AIY_MICRON_1G) || + (baseboard_id == AIY_HYNIX_1G)) { + /* 1G DDR size */ + env_set("bootargs_ram_capacity", "cma=296M galcore.contiguousSize=33554432"); + } else { + /* 3G DDR size */ + env_set("bootargs_ram_capacity", "cma=384M"); + } + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/freescale/imx8mq_aiy/spl.c b/board/freescale/imx8mq_aiy/spl.c new file mode 100644 index 00000000000..712c764edfb --- /dev/null +++ b/board/freescale/imx8mq_aiy/spl.c @@ -0,0 +1,261 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern struct dram_timing_info dram_timing_micron_3g; +extern struct dram_timing_info dram_timing_1g; +extern int get_imx8m_baseboard_id(void); + +void spl_dram_init(void) +{ + int board_id = get_imx8m_baseboard_id(); + + /* ddr init */ + if ((board_id == AIY_MICRON_1G) || (board_id == AIY_HYNIX_1G)) + ddr_init(&dram_timing_1g); + else + ddr_init(&dram_timing_micron_3g); + +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_bd71837_init(I2C_PMIC); + if (ret) + printf("power init failed"); + + p = pmic_get("BD71837"); + pmic_probe(p); + + /* Unlock reg */ + pmic_reg_write(p, BD71837_REGLOCK, 0x1); + + /* Set BUCK5 output for DRAM to 1.0V */ + /* 0.70,0.80,0.90,1.00, 1.05,1.10,1.20,1.35 */ + pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x3); + + /* Set BUCK3 output for VDD_GPU_0V9 to 0.90V */ + /* 0.7-1.3 (10mVstep) */ + pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14); + + /* Set BUCK4 output for VDD_VPU_0V9 to 0.90V */ + /* 0.7-1.3 (10mVstep) */ + pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14); + + /* Set BUCK2 output for VDD_ARM_0V9 to 0.90V */ + /* 0.7-1.3 (10mVstep) */ + pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x14); + + /* Set BUCK1 output for VDD_SOC_0V9 to 0.90V */ + /* 0.7-1.3 (10mVstep) */ + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x14); + + /* lock the PMIC regs */ + pmic_reg_write(p, BD71837_REGLOCK, 0x11); + + return 0; +} +#endif + +void spl_board_init(void) +{ +#ifndef CONFIG_SPL_USB_SDP_SUPPORT + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } +#endif + init_usb_clk(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(0); /* Init UART0 clock */ + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8mq_arm2/Kconfig b/board/freescale/imx8mq_arm2/Kconfig new file mode 100644 index 00000000000..41757ccd324 --- /dev/null +++ b/board/freescale/imx8mq_arm2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8MQ_DDR3L_ARM2 || TARGET_IMX8MQ_DDR4_ARM2 + +config SYS_BOARD + default "imx8mq_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mq_arm2" + +endif diff --git a/board/freescale/imx8mq_arm2/Makefile b/board/freescale/imx8mq_arm2/Makefile new file mode 100644 index 00000000000..e977342e942 --- /dev/null +++ b/board/freescale/imx8mq_arm2/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2017 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mq_arm2.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += ddr/helper.o +ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 +obj-y += ddr/ddr3l/ddr_init.o ddr/ddr3l/ddrphy_train.o +else +obj-y += ddr/ddr4/ddr_init.o ddr/ddr4/ddrphy_train.o +endif +endif diff --git a/board/freescale/imx8mq_arm2/ddr/ddr.h b/board/freescale/imx8mq_arm2/ddr/ddr.h new file mode 100644 index 00000000000..4f3b65afe3c --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/ddr.h @@ -0,0 +1,49 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef SRC_DDRC_RCR_ADDR +#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000 +#endif +#ifndef DDR_CSD1_BASE_ADDR +#define DDR_CSD1_BASE_ADDR 0x40000000 +#endif + +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +void ddr_init(void); +void ddr_load_train_code(enum fw_type type); +void wait_ddrphy_training_complete(void); +void ddr3_phyinit_train_1600mts(void); +void ddr4_phyinit_train_2400mts(void); + +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline uint32_t reg32_read(unsigned long addr) +{ + return readl(addr); +} +/* +static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val) +{ + writel(val, addr); +} +*/ + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} + +static inline void reg32clrbit(unsigned long addr, u32 bit) +{ + clrbits_le32(addr, (1 << bit)); +} diff --git a/board/freescale/imx8mq_arm2/ddr/ddr3l/ddr_init.c b/board/freescale/imx8mq_arm2/ddr/ddr3l/ddr_init.c new file mode 100644 index 00000000000..8471a77bbaa --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/ddr3l/ddr_init.c @@ -0,0 +1,188 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "../ddr.h" + +#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG +#define ddr_printf(args...) printf(args) +#else +#define ddr_printf(args...) +#endif + +#include "../wait_ddrphy_training_complete.c" + +volatile unsigned int tmp; +void umctl2_cfg(void){ + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + do{ + tmp = 0x7 & (reg32_read(DDRC_STAT(0))); + } while (tmp);/* wait init state */ + + reg32_write(DDRC_MSTR(0), 0x83040001);/* two rank */ + + reg32_write(DDRC_MRCTRL0(0), 0x40004030); + reg32_write(DDRC_MRCTRL1(0), 0x0001c68e); + reg32_write(DDRC_MRCTRL2(0), 0x921b7e95); + reg32_write(DDRC_DERATEEN(0), 0x00000506); + reg32_write(DDRC_DERATEINT(0), 0x9a4fbdf1); + reg32_write(DDRC_MSTR2(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x000000a8); + reg32_write(DDRC_PWRTMG(0), 0x00532203); + reg32_write(DDRC_HWLPCTL(0), 0x0b6d0000); + reg32_write(DDRC_HWFFCCTL(0), 0x00000030); + reg32_write(DDRC_RFSHCTL0(0), 0x00203020); + reg32_write(DDRC_RFSHCTL1(0), 0x0001000d); + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + reg32_write(DDRC_RFSHTMG(0), 0x0061008c); + reg32_write(DDRC_CRCPARCTL0(0), 0x00000000); + reg32_write(DDRC_CRCPARCTL1(0), 0x00000000); + reg32_write(DDRC_INIT0(0), 0xc0030002); + reg32_write(DDRC_INIT1(0), 0x0001000b); + reg32_write(DDRC_INIT2(0), 0x00006303); + reg32_write(DDRC_INIT3(0), 0x0d700044);/* MR1, MR0 */ + reg32_write(DDRC_INIT4(0), 0x00180000);/* MR2 */ + reg32_write(DDRC_INIT5(0), 0x00090071); + reg32_write(DDRC_INIT6(0), 0x00000000); + reg32_write(DDRC_INIT7(0), 0x00000000); + reg32_write(DDRC_DIMMCTL(0), 0x00000032); + reg32_write(DDRC_RANKCTL(0), 0x00000ee5); + reg32_write(DDRC_DRAMTMG0(0), 0x0c101a0e); + reg32_write(DDRC_DRAMTMG1(0), 0x000a0314); + reg32_write(DDRC_DRAMTMG2(0), 0x04060509); + reg32_write(DDRC_DRAMTMG3(0), 0x00002006); + reg32_write(DDRC_DRAMTMG4(0), 0x06020306); + reg32_write(DDRC_DRAMTMG5(0), 0x0b060202); + reg32_write(DDRC_DRAMTMG6(0), 0x060a0009); + reg32_write(DDRC_DRAMTMG7(0), 0x0000060b); + reg32_write(DDRC_DRAMTMG8(0), 0x01017c0a); + reg32_write(DDRC_DRAMTMG9(0), 0x4000000e); + reg32_write(DDRC_DRAMTMG10(0), 0x00070803); + reg32_write(DDRC_DRAMTMG11(0), 0x0101000b); + reg32_write(DDRC_DRAMTMG12(0), 0x00000000); + reg32_write(DDRC_DRAMTMG13(0), 0x5d000000); + reg32_write(DDRC_DRAMTMG14(0), 0x00000b39); + reg32_write(DDRC_DRAMTMG15(0), 0x80000000); + reg32_write(DDRC_DRAMTMG17(0), 0x00f1006a); + reg32_write(DDRC_ZQCTL0(0), 0x50800020); + reg32_write(DDRC_ZQCTL1(0), 0x00000070); + reg32_write(DDRC_ZQCTL2(0), 0x00000000); + reg32_write(DDRC_DFITMG0(0), 0x03868203); + reg32_write(DDRC_DFITMG1(0), 0x00020103); + reg32_write(DDRC_DFILPCFG0(0), 0x07713121); + reg32_write(DDRC_DFILPCFG1(0), 0x00000010); + reg32_write(DDRC_DFIUPD0(0), 0xe0400018); + reg32_write(DDRC_DFIUPD1(0), 0x0005003c); + reg32_write(DDRC_DFIUPD2(0), 0x00000000); + reg32_write(DDRC_DFIMISC(0), 0x00000011); + reg32_write(DDRC_DFITMG2(0), 0x00000603); + reg32_write(DDRC_DFITMG3(0), 0x00000001); + reg32_write(DDRC_DBICTL(0), 0x00000001); + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000); + + reg32_write(DDRC_ADDRMAP0(0), 0x00000016); /* [4:0] cs-bit0: 6+22=28; [12:8] cs-bit1: 7+0 */ + reg32_write(DDRC_ADDRMAP1(0), 0x00080808); /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+8 */ + reg32_write(DDRC_ADDRMAP2(0), 0x00000000); /* [3:0] col-b2: 2; [11:8] col-b3: 3; [19:16] col-b4: 4 ; [27:24] col-b5: 5 */ + reg32_write(DDRC_ADDRMAP3(0), 0x00000000); /* [3:0] col-b6: 6; [11:8] col-b7: 7; [19:16] col-b8: 8 ; [27:24] col-b9: 9 */ + reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */ + reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6; [11:8] row-b1: 7; [19:16] row-b2_b10 ; [27:24] row-b11: 17 */ + reg32_write(DDRC_ADDRMAP6(0), 0x0f070707); /* [3:0] row-b12:18; [11:8] row-b13: 19; [19:16] row-b14:20 */ + reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f); + reg32_write(DDRC_ADDRMAP8(0), 0x00000000); /* [5:0] bg-b0; [13:8]bg-b1 */ + reg32_write(DDRC_ADDRMAP9(0), 0x0a020b06); /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP10(0), 0x0a0a0a0a);/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP11(0), 0x00000000); + + + reg32_write(DDRC_ODTCFG(0), 0x041d0f5c); + reg32_write(DDRC_ODTMAP(0), 0x00000201); + reg32_write(DDRC_SCHED(0), 0x7ab50b07); + reg32_write(DDRC_SCHED1(0), 0x00000022); + reg32_write(DDRC_PERFHPR1(0), 0x7b00665e); + reg32_write(DDRC_PERFLPR1(0), 0x2b00c4e1); + reg32_write(DDRC_PERFWR1(0), 0xb700c9fe); + reg32_write(DDRC_DBG0(0), 0x00000017); + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_DBGCMD(0), 0x00000000); + reg32_write(DDRC_SWCTL(0), 0x00000001); + reg32_write(DDRC_POISONCFG(0), 0x00010000); + reg32_write(DDRC_PCCFG(0), 0x00000100); + reg32_write(DDRC_PCFGR_0(0), 0x00003051); + reg32_write(DDRC_PCFGW_0(0), 0x000061d2); + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + reg32_write(DDRC_PCFGQOS0_0(0), 0x02100b04); + reg32_write(DDRC_PCFGQOS1_0(0), 0x003f0353); + reg32_write(DDRC_PCFGWQOS0_0(0), 0x00000002); + reg32_write(DDRC_PCFGWQOS1_0(0), 0x000005fd); +} + +void ddr_init(void) +{ + /* change the clock source of dram_apb_clk_root */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16)); + + /* disable the clock gating */ + reg32_write(0x303A00EC,0x0000ffff); + reg32setbit(0x303A00F8,5); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + + dram_pll_init(DRAM_PLL_OUT_400M); + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /* Configure uMCTL2's registers */ + umctl2_cfg(); + + reg32setbit(DDRC_RFSHCTL3(0),0); /* dis_auto_refresh */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + ddr_load_train_code(FW_1D_IMAGE); + + reg32_write(DDRC_DBG1(0), 0x00000000); /* ('b00000000_00000000_00000000_00000000) ('d0) */ + reg32setbit(DDRC_PWRCTL(0),5); /* selfref_sw=1, self-refresh */ + reg32clrbit(DDRC_SWCTL(0), 0); /* sw_done=0, enable quasi-dynamic programming */ + reg32_write(DDRC_DFIMISC(0), 0x00000000); + + /* Configure DDR3L PHY's registers */ + ddr3_phyinit_train_1600mts(); + + do { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0x00020097); + } while (tmp != 0); + + reg32setbit(DDRC_DFIMISC(0),5);/* dfi_init_start=1 */ + do{ + tmp = 0x1 & (reg32_read(DDRC_DFISTAT(0))); + } while (!tmp);/* wait DFISTAT.dfi_init_complete to 1 */ + + reg32clrbit(DDRC_DFIMISC(0),5);/* dfi_init_start=0 */ + reg32setbit(DDRC_DFIMISC(0),0);/* dfi_init_complete_en=1 */ + + reg32clrbit(DDRC_PWRCTL(0),5);/* selfref_sw=0, exit self-refresh */ + + reg32setbit(DDRC_SWCTL(0), 0);/* sw_done=1, disable quasi-dynamic programming */ + + /* wait SWSTAT.sw_done_ack to 1 */ + do{ + tmp = 0x1 & (reg32_read(DDRC_SWSTAT(0))); + } while (!tmp); + + /* wait STAT to normal state */ + do{ + tmp = 0x7 & (reg32_read(DDRC_STAT(0))); + } while (tmp != 0x1); + + reg32_write(DDRC_PCTRL_0(0), 0x00000001); /* enable port 0 */ + + reg32clrbit(DDRC_RFSHCTL3(0), 0); /* auto-refresh enable */ + +} diff --git a/board/freescale/imx8mq_arm2/ddr/ddr3l/ddrphy_train.c b/board/freescale/imx8mq_arm2/ddr/ddr3l/ddrphy_train.c new file mode 100644 index 00000000000..c0e80ede538 --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/ddr3l/ddrphy_train.c @@ -0,0 +1,355 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "../ddr.h" + +#define DDR3_MR1_RTT120_RON40 ((0L << 9) | (1L << 6) | (0L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=010:120ohm;Ron:M[5,1]=00:40ohm */ +#define DDR3_MR1_RTT120_RON34 ((0L << 9) | (1L << 6) | (0L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=010:120ohm;Ron:M[5,1]=01:34ohm */ +#define DDR3_MR1_RTT60_RON40 ((0L << 9) | (0L << 6) | (1L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=001:60ohm;Ron:M[5,1]=00:40ohm */ +#define DDR3_MR1_RTT60_RON34 ((0L << 9) | (0L << 6) | (1L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=001:60ohm;Ron:M[5,1]=01:34ohm */ +#define DDR3_MR1_RTT40_RON34 ((0L << 9) | (1L << 6) | (1L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=011:40ohm;Ron:M[5,1]=01:34ohm */ +#define DDR3_MR1_RTT_DIS_RON40 ((0L << 9) | (0L << 6) | (0L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=000:disable;Ron:M[5,1]=00:40ohm */ + +#define DDR3_PHY_RON40 40 /* 40ohm */ +#define DDR3_PHY_RON34 34 /* 34ohm */ + +#define DDR3_PHY_RTT120 120 /* 120ohm */ +#define DDR3_PHY_RTT60 60 /* 60ohm */ +#define DDR3_PHY_RTT40 40 /* 40ohm */ +#define DDR3_PHY_RTT48 48 /* 48ohm */ + +#define DDR3_RTT_WR_DIS 0UL +#define DDR3_RTT_WR_60 1UL +#define DDR3_RTT_WR_120 2UL + +#define DDR3_MR1_VAL DDR3_MR1_RTT120_RON40 +#define DDR3_MR2_RTT_WR_VAL DDR3_RTT_WR_DIS + +#define DDR3_PHY_RON DDR3_PHY_RON40 +#define DDR3_PHY_RTT DDR3_PHY_RTT120 + + +#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr), data) +#define dwc_ddrphy_apb_rd(addr) (reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr))) + +void ddr3_phyinit_train_1600mts(void){ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x1005f,0x3ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1015f,0x3ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1105f,0x3ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1115f,0x3ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1205f,0x3ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1215f,0x3ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1305f,0x3ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1315f,0x3ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */ + + dwc_ddrphy_apb_wr(0x55,0x3ff); /* DWC_DDRPHYA_ANIB0_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x1055,0x3ff); /* DWC_DDRPHYA_ANIB1_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x2055,0x3ff); /* DWC_DDRPHYA_ANIB2_ATxSlewRat */ + dwc_ddrphy_apb_wr(0x3055,0x3ff); /* DWC_DDRPHYA_ANIB3_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x4055,0xff); /* DWC_DDRPHYA_ANIB4_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x5055,0xff); /* DWC_DDRPHYA_ANIB5_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x6055,0x3ff); /* DWC_DDRPHYA_ANIB6_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x7055,0x3ff); /* DWC_DDRPHYA_ANIB7_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x8055,0x3ff); /* DWC_DDRPHYA_ANIB8_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x9055,0x3ff); /* DWC_DDRPHYA_ANIB9_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x200c5,0xb); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */ + dwc_ddrphy_apb_wr(0x2002e,0x1); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */ + + dwc_ddrphy_apb_wr(0x20024,0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */ + dwc_ddrphy_apb_wr(0x2003a,0x0); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + dwc_ddrphy_apb_wr(0x20056,0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */ + dwc_ddrphy_apb_wr(0x1004d,0x208); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1014d,0x208); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1104d,0x208); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1114d,0x208); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1204d,0x208); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1214d,0x208); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1304d,0x208); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1314d,0x208); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x10049,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x10149,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x11049,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x11149,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x12049,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x12149,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x13049,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x13149,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x43,0x63); /* DWC_DDRPHYA_ANIB0_ATxImpedance */ + dwc_ddrphy_apb_wr(0x1043,0x63); /* DWC_DDRPHYA_ANIB1_ATxImpedance */ + dwc_ddrphy_apb_wr(0x2043,0x63); /* DWC_DDRPHYA_ANIB2_ATxImpedance */ + dwc_ddrphy_apb_wr(0x3043,0x63); /* DWC_DDRPHYA_ANIB3_ATxImpedance */ + dwc_ddrphy_apb_wr(0x4043,0x63); /* DWC_DDRPHYA_ANIB4_ATxImpedance */ + dwc_ddrphy_apb_wr(0x5043,0x63); /* DWC_DDRPHYA_ANIB5_ATxImpedance */ + dwc_ddrphy_apb_wr(0x6043,0x63); /* DWC_DDRPHYA_ANIB6_ATxImpedance */ + dwc_ddrphy_apb_wr(0x7043,0x63); /* DWC_DDRPHYA_ANIB7_ATxImpedance */ + dwc_ddrphy_apb_wr(0x8043,0x63); /* DWC_DDRPHYA_ANIB8_ATxImpedance */ + dwc_ddrphy_apb_wr(0x9043,0x63); /* DWC_DDRPHYA_ANIB9_ATxImpedance */ + dwc_ddrphy_apb_wr(0x20018,0x5); /* DWC_DDRPHYA_MASTER0_DfiMode */ + dwc_ddrphy_apb_wr(0x20075,0x0); /* DWC_DDRPHYA_MASTER0_DfiCAMode */ + dwc_ddrphy_apb_wr(0x20050,0x0); /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */ + dwc_ddrphy_apb_wr(0x20008,0x190); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */ + dwc_ddrphy_apb_wr(0x20088,0x9); /* DWC_DDRPHYA_MASTER0_CalRate */ + dwc_ddrphy_apb_wr(0x200b2,0xf8); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */ + dwc_ddrphy_apb_wr(0x10043,0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x10143,0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x11043,0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x11143,0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x12043,0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x12143,0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x13043,0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x13143,0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x200fa,0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */ + dwc_ddrphy_apb_wr(0x20019,0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */ + dwc_ddrphy_apb_wr(0x200f0,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */ + dwc_ddrphy_apb_wr(0x200f1,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */ + dwc_ddrphy_apb_wr(0x200f2,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */ + dwc_ddrphy_apb_wr(0x200f3,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */ + dwc_ddrphy_apb_wr(0x200f4,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */ + dwc_ddrphy_apb_wr(0x200f5,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */ + dwc_ddrphy_apb_wr(0x200f6,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */ + dwc_ddrphy_apb_wr(0x200f7,0xf000); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */ + dwc_ddrphy_apb_wr(0x2000b,0x33); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */ + dwc_ddrphy_apb_wr(0x2000c,0x65); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */ + dwc_ddrphy_apb_wr(0x2000d,0x3e9); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */ + dwc_ddrphy_apb_wr(0x2000e,0x2c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */ + dwc_ddrphy_apb_wr(0x20025,0x0); /* DWC_DDRPHYA_MASTER0_MasterX4Config */ + dwc_ddrphy_apb_wr(0x2002d,0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */ + + dwc_ddrphy_apb_wr(0x20060,0x2); /* DWC_DDRPHYA_MASTER0_MemResetL */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x54000,0x0); + dwc_ddrphy_apb_wr(0x54001,0x0); + dwc_ddrphy_apb_wr(0x54002,0x0); + dwc_ddrphy_apb_wr(0x54003,0x640); + dwc_ddrphy_apb_wr(0x54004,0x2); + dwc_ddrphy_apb_wr(0x54005,((DDR3_PHY_RON << 8) | (DDR3_PHY_RTT << 0))); + dwc_ddrphy_apb_wr(0x54006,0x13b); + dwc_ddrphy_apb_wr(0x54007,0x2000); + + dwc_ddrphy_apb_wr(0x54008,0x303); /* two ranks */ + + dwc_ddrphy_apb_wr(0x54009,0x200); + dwc_ddrphy_apb_wr(0x5400a,0x0); + dwc_ddrphy_apb_wr(0x5400b,0x31f); + dwc_ddrphy_apb_wr(0x5400c,0xc8); + + dwc_ddrphy_apb_wr(0x54012,0x1); + dwc_ddrphy_apb_wr(0x5402f,0xd70); /* MR0 */ + dwc_ddrphy_apb_wr(0x54030,DDR3_MR1_VAL); /* MR1=6:Ron=34ohm/Rtt(NOM)=60ohm */ + dwc_ddrphy_apb_wr(0x54031,(0x18 | (DDR3_MR2_RTT_WR_VAL << 9))); /*MR2 */ + dwc_ddrphy_apb_wr(0x5403a,0x1221); + dwc_ddrphy_apb_wr(0x5403b,0x4884); + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099,0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + + wait_ddrphy_training_complete(); + + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x90000,0x10); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90001,0x400); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90002,0x10e); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90003,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x90004,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x90005,0x8); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x90029,0xb); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x9002a,0x480); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x9002b,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x9002c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9002d,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9002e,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x9002f,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */ + dwc_ddrphy_apb_wr(0x90030,0x478); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */ + dwc_ddrphy_apb_wr(0x90031,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */ + dwc_ddrphy_apb_wr(0x90032,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */ + dwc_ddrphy_apb_wr(0x90033,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */ + dwc_ddrphy_apb_wr(0x90034,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */ + dwc_ddrphy_apb_wr(0x90035,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */ + dwc_ddrphy_apb_wr(0x90036,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */ + dwc_ddrphy_apb_wr(0x90037,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */ + dwc_ddrphy_apb_wr(0x90038,0x44); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */ + dwc_ddrphy_apb_wr(0x90039,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */ + dwc_ddrphy_apb_wr(0x9003a,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */ + dwc_ddrphy_apb_wr(0x9003b,0x14f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */ + dwc_ddrphy_apb_wr(0x9003c,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */ + dwc_ddrphy_apb_wr(0x9003d,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */ + dwc_ddrphy_apb_wr(0x9003e,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */ + dwc_ddrphy_apb_wr(0x9003f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */ + dwc_ddrphy_apb_wr(0x90040,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */ + dwc_ddrphy_apb_wr(0x90041,0x4f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */ + dwc_ddrphy_apb_wr(0x90042,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */ + dwc_ddrphy_apb_wr(0x90043,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */ + dwc_ddrphy_apb_wr(0x90044,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */ + dwc_ddrphy_apb_wr(0x90045,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */ + dwc_ddrphy_apb_wr(0x90046,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */ + dwc_ddrphy_apb_wr(0x90047,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */ + dwc_ddrphy_apb_wr(0x90048,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */ + dwc_ddrphy_apb_wr(0x90049,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */ + dwc_ddrphy_apb_wr(0x9004a,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */ + dwc_ddrphy_apb_wr(0x9004b,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */ + dwc_ddrphy_apb_wr(0x9004c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */ + dwc_ddrphy_apb_wr(0x9004d,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */ + dwc_ddrphy_apb_wr(0x9004e,0x45a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */ + dwc_ddrphy_apb_wr(0x9004f,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */ + dwc_ddrphy_apb_wr(0x90050,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */ + dwc_ddrphy_apb_wr(0x90051,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */ + dwc_ddrphy_apb_wr(0x90052,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */ + dwc_ddrphy_apb_wr(0x90053,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */ + dwc_ddrphy_apb_wr(0x90054,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */ + dwc_ddrphy_apb_wr(0x90055,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */ + dwc_ddrphy_apb_wr(0x90056,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */ + dwc_ddrphy_apb_wr(0x90057,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */ + dwc_ddrphy_apb_wr(0x90058,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */ + dwc_ddrphy_apb_wr(0x90059,0x40c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */ + dwc_ddrphy_apb_wr(0x9005a,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */ + dwc_ddrphy_apb_wr(0x9005b,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */ + dwc_ddrphy_apb_wr(0x9005c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */ + dwc_ddrphy_apb_wr(0x9005d,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */ + dwc_ddrphy_apb_wr(0x9005e,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */ + dwc_ddrphy_apb_wr(0x9005f,0x4040); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */ + dwc_ddrphy_apb_wr(0x90060,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */ + dwc_ddrphy_apb_wr(0x90061,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */ + dwc_ddrphy_apb_wr(0x90062,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */ + dwc_ddrphy_apb_wr(0x90063,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */ + dwc_ddrphy_apb_wr(0x90064,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */ + dwc_ddrphy_apb_wr(0x90065,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */ + dwc_ddrphy_apb_wr(0x90066,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */ + dwc_ddrphy_apb_wr(0x90067,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */ + dwc_ddrphy_apb_wr(0x90068,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */ + dwc_ddrphy_apb_wr(0x90069,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */ + dwc_ddrphy_apb_wr(0x9006a,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */ + dwc_ddrphy_apb_wr(0x9006b,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */ + dwc_ddrphy_apb_wr(0x9006c,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */ + dwc_ddrphy_apb_wr(0x9006d,0x78); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */ + dwc_ddrphy_apb_wr(0x9006e,0x549); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */ + dwc_ddrphy_apb_wr(0x9006f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */ + dwc_ddrphy_apb_wr(0x90070,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */ + dwc_ddrphy_apb_wr(0x90071,0xd49); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */ + dwc_ddrphy_apb_wr(0x90072,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */ + dwc_ddrphy_apb_wr(0x90073,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */ + dwc_ddrphy_apb_wr(0x90074,0x94a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */ + dwc_ddrphy_apb_wr(0x90075,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */ + dwc_ddrphy_apb_wr(0x90076,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */ + dwc_ddrphy_apb_wr(0x90077,0x441); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */ + dwc_ddrphy_apb_wr(0x90078,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */ + dwc_ddrphy_apb_wr(0x90079,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */ + dwc_ddrphy_apb_wr(0x9007a,0x42); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */ + dwc_ddrphy_apb_wr(0x9007b,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */ + dwc_ddrphy_apb_wr(0x9007c,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */ + dwc_ddrphy_apb_wr(0x9007d,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */ + dwc_ddrphy_apb_wr(0x9007e,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */ + dwc_ddrphy_apb_wr(0x9007f,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */ + dwc_ddrphy_apb_wr(0x90080,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */ + dwc_ddrphy_apb_wr(0x90081,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */ + dwc_ddrphy_apb_wr(0x90082,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */ + dwc_ddrphy_apb_wr(0x90083,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */ + dwc_ddrphy_apb_wr(0x90084,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */ + dwc_ddrphy_apb_wr(0x90085,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */ + dwc_ddrphy_apb_wr(0x90086,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */ + dwc_ddrphy_apb_wr(0x90087,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */ + dwc_ddrphy_apb_wr(0x90088,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */ + dwc_ddrphy_apb_wr(0x90089,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */ + dwc_ddrphy_apb_wr(0x9008a,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */ + dwc_ddrphy_apb_wr(0x9008b,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */ + dwc_ddrphy_apb_wr(0x9008c,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */ + dwc_ddrphy_apb_wr(0x9008d,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */ + dwc_ddrphy_apb_wr(0x9008e,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */ + dwc_ddrphy_apb_wr(0x9008f,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */ + dwc_ddrphy_apb_wr(0x90090,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */ + dwc_ddrphy_apb_wr(0x90091,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */ + dwc_ddrphy_apb_wr(0x90092,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */ + dwc_ddrphy_apb_wr(0x90093,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */ + dwc_ddrphy_apb_wr(0x90094,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */ + dwc_ddrphy_apb_wr(0x90095,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */ + dwc_ddrphy_apb_wr(0x90096,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */ + dwc_ddrphy_apb_wr(0x90097,0x58); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */ + dwc_ddrphy_apb_wr(0x90098,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */ + dwc_ddrphy_apb_wr(0x90099,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */ + dwc_ddrphy_apb_wr(0x9009a,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */ + dwc_ddrphy_apb_wr(0x9009b,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */ + dwc_ddrphy_apb_wr(0x9009c,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */ + dwc_ddrphy_apb_wr(0x9009d,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */ + dwc_ddrphy_apb_wr(0x9009e,0x7); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */ + dwc_ddrphy_apb_wr(0x9009f,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */ + dwc_ddrphy_apb_wr(0x900a0,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */ + dwc_ddrphy_apb_wr(0x900a1,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */ + dwc_ddrphy_apb_wr(0x900a2,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */ + dwc_ddrphy_apb_wr(0x900a3,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */ + dwc_ddrphy_apb_wr(0x900a4,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */ + dwc_ddrphy_apb_wr(0x900a5,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */ + dwc_ddrphy_apb_wr(0x900a6,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */ + dwc_ddrphy_apb_wr(0x900a7,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */ + dwc_ddrphy_apb_wr(0x900a8,0x8138); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */ + dwc_ddrphy_apb_wr(0x900a9,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */ + dwc_ddrphy_apb_wr(0x900aa,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */ + dwc_ddrphy_apb_wr(0x900ab,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */ + dwc_ddrphy_apb_wr(0x900ac,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */ + dwc_ddrphy_apb_wr(0x900ad,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */ + dwc_ddrphy_apb_wr(0x900ae,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */ + dwc_ddrphy_apb_wr(0x900af,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */ + dwc_ddrphy_apb_wr(0x900b0,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */ + dwc_ddrphy_apb_wr(0x900b1,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */ + dwc_ddrphy_apb_wr(0x900b2,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */ + dwc_ddrphy_apb_wr(0x900b3,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */ + dwc_ddrphy_apb_wr(0x900b4,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */ + dwc_ddrphy_apb_wr(0x900b5,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */ + dwc_ddrphy_apb_wr(0x900b6,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */ + dwc_ddrphy_apb_wr(0x900b7,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */ + dwc_ddrphy_apb_wr(0x900b8,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */ + dwc_ddrphy_apb_wr(0x900b9,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */ + dwc_ddrphy_apb_wr(0x900ba,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */ + dwc_ddrphy_apb_wr(0x900bb,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */ + dwc_ddrphy_apb_wr(0x900bc,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */ + dwc_ddrphy_apb_wr(0x900bd,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */ + dwc_ddrphy_apb_wr(0x900be,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */ + dwc_ddrphy_apb_wr(0x900bf,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */ + dwc_ddrphy_apb_wr(0x900c0,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */ + dwc_ddrphy_apb_wr(0x900c1,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */ + dwc_ddrphy_apb_wr(0x900c2,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */ + dwc_ddrphy_apb_wr(0x900c3,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */ + dwc_ddrphy_apb_wr(0x900c4,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */ + dwc_ddrphy_apb_wr(0x900c5,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */ + dwc_ddrphy_apb_wr(0x900c6,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */ + dwc_ddrphy_apb_wr(0x900c7,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */ + dwc_ddrphy_apb_wr(0x900c8,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */ + dwc_ddrphy_apb_wr(0x900c9,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */ + dwc_ddrphy_apb_wr(0x900ca,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */ + dwc_ddrphy_apb_wr(0x900cb,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */ + dwc_ddrphy_apb_wr(0x900cc,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */ + dwc_ddrphy_apb_wr(0x900cd,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */ + dwc_ddrphy_apb_wr(0x90006,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90007,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90008,0x8); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90009,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9000a,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9000b,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0xd00e7,0x400); /* DWC_DDRPHYA_APBONLY0_SequencerOverride */ + dwc_ddrphy_apb_wr(0x90017,0x0); /* DWC_DDRPHYA_INITENG0_StartVector0b0 */ + dwc_ddrphy_apb_wr(0x90026,0x2c); /* DWC_DDRPHYA_INITENG0_StartVector0b15 */ + dwc_ddrphy_apb_wr(0x9000c,0x0); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */ + dwc_ddrphy_apb_wr(0x9000d,0x173); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */ + dwc_ddrphy_apb_wr(0x9000e,0x60); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */ + dwc_ddrphy_apb_wr(0x9000f,0x6110); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */ + dwc_ddrphy_apb_wr(0x90010,0x2152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */ + dwc_ddrphy_apb_wr(0x90011,0xdfbd); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */ + dwc_ddrphy_apb_wr(0x90012,0xffff); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */ + dwc_ddrphy_apb_wr(0x90013,0x6152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */ + dwc_ddrphy_apb_wr(0xc0080,0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +} diff --git a/board/freescale/imx8mq_arm2/ddr/ddr4/ddr_init.c b/board/freescale/imx8mq_arm2/ddr/ddr4/ddr_init.c new file mode 100644 index 00000000000..e4f410ecaf5 --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/ddr4/ddr_init.c @@ -0,0 +1,226 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "../ddr.h" + +#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG +#define ddr_printf(args...) printf(args) +#else +#define ddr_printf(args...) +#endif + +#include "../wait_ddrphy_training_complete.c" + +volatile unsigned int tmp, tmp_t; +void umctl2_cfg(void){ + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + tmp = reg32_read(DDRC_STAT(0)); + while (tmp_t == 0x00000001){ + tmp = reg32_read(DDRC_STAT(0)); + tmp_t = tmp && 0x00000001; + } + + reg32_write(DDRC_MSTR(0), 0x83040010); /* Two ranks */ + + reg32_write(DDRC_MRCTRL0(0), 0x40007030); + reg32_write(DDRC_MRCTRL1(0), 0x000170df); + reg32_write(DDRC_MRCTRL2(0), 0x97d37be3); + reg32_write(DDRC_DERATEEN(0), 0x00000302); + reg32_write(DDRC_DERATEINT(0), 0xbc808cc7); + reg32_write(DDRC_MSTR2(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x000001ae); + reg32_write(DDRC_PWRTMG(0), 0x000d2800); + reg32_write(DDRC_HWLPCTL(0), 0x000c0000); + reg32_write(DDRC_HWFFCCTL(0), 0x00000010); + reg32_write(DDRC_RFSHCTL0(0), 0x007090b0); + reg32_write(DDRC_RFSHCTL1(0), 0x00420019); + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); + reg32_write(DDRC_RFSHTMG(0), 0x0049009d); + reg32_write(DDRC_CRCPARCTL0(0), 0x00000000); + reg32_write(DDRC_CRCPARCTL1(0), 0x00001011); + reg32_write(DDRC_INIT0(0), 0xc0030002); + reg32_write(DDRC_INIT1(0), 0x00030006); + reg32_write(DDRC_INIT2(0), 0x00000305); + reg32_write(DDRC_INIT3(0), 0x0a300001); + reg32_write(DDRC_INIT4(0), 0x10180240); + reg32_write(DDRC_INIT5(0), 0x0011008a); + reg32_write(DDRC_INIT6(0), 0x0a000042); + reg32_write(DDRC_INIT7(0), 0x00000800); + reg32_write(DDRC_DIMMCTL(0), 0x00000032); /* [1] dimm_addr_mirr_en, it will effect the MRS if use umctl2 to initi dram. */ + reg32_write(DDRC_RANKCTL(0), 0x00000530); + reg32_write(DDRC_DRAMTMG0(0), 0x14132813); + reg32_write(DDRC_DRAMTMG1(0), 0x0007051b); + reg32_write(DDRC_DRAMTMG2(0), 0x090a050f); + reg32_write(DDRC_DRAMTMG3(0), 0x0000f00f); + reg32_write(DDRC_DRAMTMG4(0), 0x08030409); + reg32_write(DDRC_DRAMTMG5(0), 0x0c0d0504); + reg32_write(DDRC_DRAMTMG6(0), 0x00000003); + reg32_write(DDRC_DRAMTMG7(0), 0x00000d0c); + reg32_write(DDRC_DRAMTMG8(0), 0x05051f09); + reg32_write(DDRC_DRAMTMG9(0), 0x0002040c); + reg32_write(DDRC_DRAMTMG10(0), 0x000e0d0b); + reg32_write(DDRC_DRAMTMG11(0), 0x1409011e); + reg32_write(DDRC_DRAMTMG12(0), 0x0000000d); + reg32_write(DDRC_DRAMTMG13(0), 0x09000000); + reg32_write(DDRC_DRAMTMG14(0), 0x00000371); + reg32_write(DDRC_DRAMTMG15(0), 0x80000000); + reg32_write(DDRC_DRAMTMG17(0), 0x0076006e); + reg32_write(DDRC_ZQCTL0(0), 0x51000040); + reg32_write(DDRC_ZQCTL1(0), 0x00000070); + reg32_write(DDRC_ZQCTL2(0), 0x00000000); + reg32_write(DDRC_DFITMG0(0), 0x038f820c); + reg32_write(DDRC_DFITMG1(0), 0x00020103); + reg32_write(DDRC_DFILPCFG0(0), 0x07e1b011); + reg32_write(DDRC_DFILPCFG1(0), 0x00000030); + reg32_write(DDRC_DFIUPD0(0), 0xe0400018); + reg32_write(DDRC_DFIUPD1(0), 0x004e00c3); + reg32_write(DDRC_DFIUPD2(0), 0x00000000); + reg32_write(DDRC_DFIMISC(0), 0x00000001); + reg32_write(DDRC_DFITMG2(0), 0x00000f0c); + reg32_write(DDRC_DFITMG3(0), 0x00000001); + reg32_write(DDRC_DBICTL(0), 0x00000000); + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000); + + reg32_write(DDRC_ADDRMAP0(0), 0x00001F17); /* [4:0]cs0: 6+23 */ + reg32_write(DDRC_ADDRMAP1(0), 0x003F0808); /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+, unused */ + reg32_write(DDRC_ADDRMAP2(0), 0x00000000); /* [3:0] col-b2: 2; [11:8] col-b3: 3+0; [19:16] col-b4: 4+0 ; [27:24] col-b5: 5+0 */ + reg32_write(DDRC_ADDRMAP3(0), 0x00000000); /* [3:0] col-b6: 6+0; [11:8] col-b7: 7+0; [19:16] col-b8: 8+0 ; [27:24] col-b9: 9+0 */ + reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */ + reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6+7; [11:8] row-b1: 7+7; [19:16] row-b2_b10: 8~16+7; [27:24] row-b11: 17+7 */ + reg32_write(DDRC_ADDRMAP6(0), 0x07070707); /* [3:0] row-b12:18+7; [11:8] row-b13: 19+7; [19:16] row-b14:20+7 */ + reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f); /* col-b10, col-b11 not used */ + reg32_write(DDRC_ADDRMAP8(0), 0x00003F0A); /* [5:0] bg-b0: 2+10; [13:8]bg-b1:3+, unused */ + reg32_write(DDRC_ADDRMAP9(0), 0x00000000); /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP10(0), 0x00000000);/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP11(0), 0x00000000); + + + reg32_write(DDRC_ODTCFG(0), 0x05170558); + reg32_write(DDRC_ODTMAP(0), 0x00002113); + reg32_write(DDRC_SCHED(0), 0x0d6f0705); + reg32_write(DDRC_SCHED1(0), 0x00000000); + reg32_write(DDRC_PERFHPR1(0), 0xe500558b); + reg32_write(DDRC_PERFLPR1(0), 0x75001fea); + reg32_write(DDRC_PERFWR1(0), 0x880026c7); + reg32_write(DDRC_DBG0(0), 0x00000011); + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_DBGCMD(0), 0x00000000); + reg32_write(DDRC_SWCTL(0), 0x00000001); + reg32_write(DDRC_POISONCFG(0), 0x00100011); + reg32_write(DDRC_PCCFG(0), 0x00000100); + reg32_write(DDRC_PCFGR_0(0), 0x00015313); + reg32_write(DDRC_PCFGW_0(0), 0x000050dc); + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + reg32_write(DDRC_PCFGQOS0_0(0), 0x01100200); + reg32_write(DDRC_PCFGQOS1_0(0), 0x01ba023a); + reg32_write(DDRC_PCFGWQOS0_0(0), 0x00110000); + reg32_write(DDRC_PCFGWQOS1_0(0), 0x0000001e); +} + +void ddr_init(void) +{ + /* change the clock source of dram_apb_clk_root */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16)); + + /* disable the clock gating */ + reg32_write(0x303A00EC,0x0000ffff); + reg32setbit(0x303A00F8,5); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + + dram_pll_init(DRAM_PLL_OUT_600M); + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /* Configure uMCTL2's registers */ + umctl2_cfg(); + + tmp = reg32_read(DDRC_RFSHCTL3(0)); + reg32_write(DDRC_RFSHCTL3(0), 0x00000011); + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + ddr_load_train_code(FW_1D_IMAGE); + + reg32_write(DDRC_DBG1(0), 0x00000000); + tmp = reg32_read(DDRC_PWRCTL(0)); + reg32_write(DDRC_PWRCTL(0), 0x000001ae); + tmp = reg32_read(DDRC_PWRCTL(0)); + reg32_write(DDRC_PWRCTL(0), 0x000001ac); + reg32_write(DDRC_SWCTL(0), 0x00000000); + tmp = reg32_read(DDRC_CRCPARSTAT(0)); + + reg32_write(DDRC_DFIMISC(0), 0x00000000); + reg32_write(DDRC_DFIMISC(0), 0x00000000); + + tmp = reg32_read(DDRC_DBICTL(0)); + tmp = reg32_read(DDRC_MSTR(0)); + tmp = reg32_read(DDRC_INIT3(0)); + tmp = reg32_read(DDRC_INIT4(0)); + tmp = reg32_read(DDRC_INIT6(0)); + tmp = reg32_read(DDRC_INIT7(0)); + tmp = reg32_read(DDRC_INIT0(0)); + + ddr4_phyinit_train_2400mts(); + + do { + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*0x00020097); + } while (tmp_t != 0); + + + reg32_write(DDRC_DFIMISC(0), 0x00000020); + + /* wait DFISTAT.dfi_init_complete to 1 */ + tmp_t = 0; + while(tmp_t == 0){ + tmp = reg32_read(DDRC_DFISTAT(0)); + tmp_t = tmp & 0x01; + } + + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000000); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x0000018c); + + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset .*/ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* wait SWSTAT.sw_done_ack to 1 */ + tmp_t = 0; + while(tmp_t==0){ + tmp = reg32_read(DDRC_SWSTAT(0)); + tmp_t = tmp & 0x01; + } + + /* wait STAT to normal state */ + tmp_t = 0; + while(tmp_t==0){ + tmp = reg32_read(DDRC_STAT(0)); + tmp_t = tmp & 0x01; + } + + tmp = reg32_read(DDRC_CRCPARSTAT(0)); + + reg32_write(DDRC_PWRCTL(0), 0x0000018c); + + reg32_write(DDRC_DERATEEN(0), 0x00000302); + + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); /* dis_auto-refresh is set to 0 */ + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0xd0000), 0); + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54030)); + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54035)); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0xd0000), 1); +} diff --git a/board/freescale/imx8mq_arm2/ddr/ddr4/ddrphy_train.c b/board/freescale/imx8mq_arm2/ddr/ddr4/ddrphy_train.c new file mode 100644 index 00000000000..99bd751e461 --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/ddr4/ddrphy_train.c @@ -0,0 +1,1366 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "../ddr.h" + +#define DDR_RON 2 +#define PHY_RTT 48 +#define PHYREF_VALUE 0x3b + +#define PHY_RON 40 +#define DDR_RTT 5 +#define MR6_VALUE 0x1f + + +#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr), data) +#define dwc_ddrphy_apb_rd(addr) (reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr))) + +void ddr4_phyinit_train_2400mts(){ + dwc_ddrphy_apb_wr(0x1005f,0x2ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1015f,0x2ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1105f,0x2ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1115f,0x2ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1205f,0x2ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1215f,0x2ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1305f,0x2ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1315f,0x2ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */ + + dwc_ddrphy_apb_wr(0x55,0x3ff); /* DWC_DDRPHYA_ANIB0_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x1055,0x3ff); /* DWC_DDRPHYA_ANIB1_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x2055,0x3ff); /* DWC_DDRPHYA_ANIB2_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x3055,0x3ff); /* DWC_DDRPHYA_ANIB3_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x4055,0xff); /* DWC_DDRPHYA_ANIB4_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x5055,0xff); /* DWC_DDRPHYA_ANIB5_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x6055,0x3ff); /* DWC_DDRPHYA_ANIB6_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x7055,0x3ff); /* DWC_DDRPHYA_ANIB7_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x8055,0x3ff); /* DWC_DDRPHYA_ANIB8_ATxSlewRate */ + + dwc_ddrphy_apb_wr(0x9055,0x3ff); /* DWC_DDRPHYA_ANIB9_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x200c5,0xa); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */ + dwc_ddrphy_apb_wr(0x2002e,0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */ + dwc_ddrphy_apb_wr(0x20024,0x9); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */ + dwc_ddrphy_apb_wr(0x2003a,0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + dwc_ddrphy_apb_wr(0x20056,0x2); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */ + dwc_ddrphy_apb_wr(0x1004d,0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1014d,0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1104d,0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1114d,0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1204d,0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1214d,0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1304d,0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1314d,0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x10049,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x10149,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x11049,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x11149,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x12049,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x12149,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x13049,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x13149,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x43,0x3ff); /* DWC_DDRPHYA_ANIB0_ATxImpedance */ + dwc_ddrphy_apb_wr(0x1043,0x3ff); /* DWC_DDRPHYA_ANIB1_ATxImpedance */ + dwc_ddrphy_apb_wr(0x2043,0x3ff); /* DWC_DDRPHYA_ANIB2_ATxImpedance */ + dwc_ddrphy_apb_wr(0x3043,0x3ff); /* DWC_DDRPHYA_ANIB3_ATxImpedance */ + dwc_ddrphy_apb_wr(0x4043,0x3ff); /* DWC_DDRPHYA_ANIB4_ATxImpedance */ + dwc_ddrphy_apb_wr(0x5043,0x3ff); /* DWC_DDRPHYA_ANIB5_ATxImpedance */ + dwc_ddrphy_apb_wr(0x6043,0x3ff); /* DWC_DDRPHYA_ANIB6_ATxImpedance */ + dwc_ddrphy_apb_wr(0x7043,0x3ff); /* DWC_DDRPHYA_ANIB7_ATxImpedance */ + dwc_ddrphy_apb_wr(0x8043,0x3ff); /* DWC_DDRPHYA_ANIB8_ATxImpedance */ + dwc_ddrphy_apb_wr(0x9043,0x3ff); /* DWC_DDRPHYA_ANIB9_ATxImpedance */ + dwc_ddrphy_apb_wr(0x20018,0x5); /* DWC_DDRPHYA_MASTER0_DfiMode */ + dwc_ddrphy_apb_wr(0x20075,0x2); /* DWC_DDRPHYA_MASTER0_DfiCAMode */ + dwc_ddrphy_apb_wr(0x20050,0x0); /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */ + dwc_ddrphy_apb_wr(0x20008,0x258); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */ + dwc_ddrphy_apb_wr(0x20088,0x9); /* DWC_DDRPHYA_MASTER0_CalRate */ + dwc_ddrphy_apb_wr(0x200b2,0x288); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */ + dwc_ddrphy_apb_wr(0x10043,0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x10143,0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x11043,0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x11143,0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x12043,0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x12143,0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x13043,0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x13143,0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x200fa,0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */ + dwc_ddrphy_apb_wr(0x20019,0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */ + dwc_ddrphy_apb_wr(0x200f0,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */ + dwc_ddrphy_apb_wr(0x200f1,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */ + dwc_ddrphy_apb_wr(0x200f2,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */ + dwc_ddrphy_apb_wr(0x200f3,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */ + dwc_ddrphy_apb_wr(0x200f4,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */ + dwc_ddrphy_apb_wr(0x200f5,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */ + dwc_ddrphy_apb_wr(0x200f6,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */ + dwc_ddrphy_apb_wr(0x200f7,0xf000); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */ + dwc_ddrphy_apb_wr(0x2000b,0x4c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */ + dwc_ddrphy_apb_wr(0x2000c,0x97); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */ + dwc_ddrphy_apb_wr(0x2000d,0x5dd); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */ + dwc_ddrphy_apb_wr(0x2000e,0x2c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */ + dwc_ddrphy_apb_wr(0x20025,0x0); /* DWC_DDRPHYA_MASTER0_MasterX4Config */ + dwc_ddrphy_apb_wr(0x2002d,0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */ + dwc_ddrphy_apb_wr(0x20060,0x2); /* DWC_DDRPHYA_MASTER0_MemResetL */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x54000,0x80);/* should be 0x80 in silicon */ + dwc_ddrphy_apb_wr(0x54001,0x0); + dwc_ddrphy_apb_wr(0x54002,0x0); + dwc_ddrphy_apb_wr(0x54003,0x960); + dwc_ddrphy_apb_wr(0x54004,0x2); + + dwc_ddrphy_apb_wr(0x54005,((PHY_RON<<8)|(PHY_RTT<<0))/*0x2830*/); + dwc_ddrphy_apb_wr(0x54006,(0x200|PHYREF_VALUE)/*0x23b*/); + dwc_ddrphy_apb_wr(0x54007,0x2000); + + dwc_ddrphy_apb_wr(0x54008,0x303); /* Two ranks */ + + dwc_ddrphy_apb_wr(0x54009,0x200);/* no addr mirror, 0x200 addr mirror */ + dwc_ddrphy_apb_wr(0x5400a,0x0); + dwc_ddrphy_apb_wr(0x5400b,0x31f);/* should be 0x31f in silicon */ + + dwc_ddrphy_apb_wr(0x5400c,0xc8); /* 0xc8 indicates stage completion messages showed */ + + dwc_ddrphy_apb_wr(0x5400d,0x0); + dwc_ddrphy_apb_wr(0x5400e,0x0); + dwc_ddrphy_apb_wr(0x5400f,0x0); + dwc_ddrphy_apb_wr(0x54010,0x0); + dwc_ddrphy_apb_wr(0x54011,0x0); + dwc_ddrphy_apb_wr(0x54012,0x1); + dwc_ddrphy_apb_wr(0x54013,0x0); + dwc_ddrphy_apb_wr(0x54014,0x0); + dwc_ddrphy_apb_wr(0x54015,0x0); + dwc_ddrphy_apb_wr(0x54016,0x0); + dwc_ddrphy_apb_wr(0x54017,0x0); + dwc_ddrphy_apb_wr(0x54018,0x0); + dwc_ddrphy_apb_wr(0x54019,0x0); + dwc_ddrphy_apb_wr(0x5401a,0x0); + dwc_ddrphy_apb_wr(0x5401b,0x0); + dwc_ddrphy_apb_wr(0x5401c,0x0); + dwc_ddrphy_apb_wr(0x5401d,0x0); + dwc_ddrphy_apb_wr(0x5401e,0x0); + dwc_ddrphy_apb_wr(0x5401f,0x0); + dwc_ddrphy_apb_wr(0x54020,0x0); + dwc_ddrphy_apb_wr(0x54021,0x0); + dwc_ddrphy_apb_wr(0x54022,0x0); + dwc_ddrphy_apb_wr(0x54023,0x0); + dwc_ddrphy_apb_wr(0x54024,0x0); + dwc_ddrphy_apb_wr(0x54025,0x0); + dwc_ddrphy_apb_wr(0x54026,0x0); + dwc_ddrphy_apb_wr(0x54027,0x0); + dwc_ddrphy_apb_wr(0x54028,0x0); + dwc_ddrphy_apb_wr(0x54029,0x0); + dwc_ddrphy_apb_wr(0x5402a,0x0); + dwc_ddrphy_apb_wr(0x5402b,0x0); + dwc_ddrphy_apb_wr(0x5402c,0x0); + dwc_ddrphy_apb_wr(0x5402d,0x0); + dwc_ddrphy_apb_wr(0x5402e,0x0); + + dwc_ddrphy_apb_wr(0x5402f,0xa30);/* MR0 */ + dwc_ddrphy_apb_wr(0x54030, ((DDR_RTT<<8)|(DDR_RON<<1)|0x1)/*0x1*/);/* MR1 */ + dwc_ddrphy_apb_wr(0x54031,0x1018);/* MR2 */ + dwc_ddrphy_apb_wr(0x54032,0x240);/* MR3 */ + dwc_ddrphy_apb_wr(0x54033,0xa00);/* MR4 */ + dwc_ddrphy_apb_wr(0x54034,0x42);/* MR5 */ + dwc_ddrphy_apb_wr(0x54035,(0x800|MR6_VALUE)/*0x800*/);/* MR6 */ + + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54030)); + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54035)); + + dwc_ddrphy_apb_wr(0x54036,0x103); + dwc_ddrphy_apb_wr(0x54037,0x0); + dwc_ddrphy_apb_wr(0x54038,0x0); + dwc_ddrphy_apb_wr(0x54039,0x0); + dwc_ddrphy_apb_wr(0x5403a,0x0); + dwc_ddrphy_apb_wr(0x5403b,0x0); + dwc_ddrphy_apb_wr(0x5403c,0x0); + dwc_ddrphy_apb_wr(0x5403d,0x0); + dwc_ddrphy_apb_wr(0x5403e,0x0); + dwc_ddrphy_apb_wr(0x5403f,0x1221); + dwc_ddrphy_apb_wr(0x54040,0x0); + dwc_ddrphy_apb_wr(0x54041,0x0); + dwc_ddrphy_apb_wr(0x54042,0x0); + dwc_ddrphy_apb_wr(0x54043,0x0); + dwc_ddrphy_apb_wr(0x54044,0x0); + dwc_ddrphy_apb_wr(0x54045,0x0); + dwc_ddrphy_apb_wr(0x54046,0x0); + dwc_ddrphy_apb_wr(0x54047,0x0); + dwc_ddrphy_apb_wr(0x54048,0x0); + dwc_ddrphy_apb_wr(0x54049,0x0); + dwc_ddrphy_apb_wr(0x5404a,0x0); + dwc_ddrphy_apb_wr(0x5404b,0x0); + dwc_ddrphy_apb_wr(0x5404c,0x0); + dwc_ddrphy_apb_wr(0x5404d,0x0); + dwc_ddrphy_apb_wr(0x5404e,0x0); + dwc_ddrphy_apb_wr(0x5404f,0x0); + dwc_ddrphy_apb_wr(0x54050,0x0); + dwc_ddrphy_apb_wr(0x54051,0x0); + dwc_ddrphy_apb_wr(0x54052,0x0); + dwc_ddrphy_apb_wr(0x54053,0x0); + dwc_ddrphy_apb_wr(0x54054,0x0); + dwc_ddrphy_apb_wr(0x54055,0x0); + dwc_ddrphy_apb_wr(0x54056,0x0); + dwc_ddrphy_apb_wr(0x54057,0x0); + dwc_ddrphy_apb_wr(0x54058,0x0); + dwc_ddrphy_apb_wr(0x54059,0x0); + dwc_ddrphy_apb_wr(0x5405a,0x0); + dwc_ddrphy_apb_wr(0x5405b,0x0); + dwc_ddrphy_apb_wr(0x5405c,0x0); + dwc_ddrphy_apb_wr(0x5405d,0x0); + dwc_ddrphy_apb_wr(0x5405e,0x0); + dwc_ddrphy_apb_wr(0x5405f,0x0); + dwc_ddrphy_apb_wr(0x54060,0x0); + dwc_ddrphy_apb_wr(0x54061,0x0); + dwc_ddrphy_apb_wr(0x54062,0x0); + dwc_ddrphy_apb_wr(0x54063,0x0); + dwc_ddrphy_apb_wr(0x54064,0x0); + dwc_ddrphy_apb_wr(0x54065,0x0); + dwc_ddrphy_apb_wr(0x54066,0x0); + dwc_ddrphy_apb_wr(0x54067,0x0); + dwc_ddrphy_apb_wr(0x54068,0x0); + dwc_ddrphy_apb_wr(0x54069,0x0); + dwc_ddrphy_apb_wr(0x5406a,0x0); + dwc_ddrphy_apb_wr(0x5406b,0x0); + dwc_ddrphy_apb_wr(0x5406c,0x0); + dwc_ddrphy_apb_wr(0x5406d,0x0); + dwc_ddrphy_apb_wr(0x5406e,0x0); + dwc_ddrphy_apb_wr(0x5406f,0x0); + dwc_ddrphy_apb_wr(0x54070,0x0); + dwc_ddrphy_apb_wr(0x54071,0x0); + dwc_ddrphy_apb_wr(0x54072,0x0); + dwc_ddrphy_apb_wr(0x54073,0x0); + dwc_ddrphy_apb_wr(0x54074,0x0); + dwc_ddrphy_apb_wr(0x54075,0x0); + dwc_ddrphy_apb_wr(0x54076,0x0); + dwc_ddrphy_apb_wr(0x54077,0x0); + dwc_ddrphy_apb_wr(0x54078,0x0); + dwc_ddrphy_apb_wr(0x54079,0x0); + dwc_ddrphy_apb_wr(0x5407a,0x0); + dwc_ddrphy_apb_wr(0x5407b,0x0); + dwc_ddrphy_apb_wr(0x5407c,0x0); + dwc_ddrphy_apb_wr(0x5407d,0x0); + dwc_ddrphy_apb_wr(0x5407e,0x0); + dwc_ddrphy_apb_wr(0x5407f,0x0); + dwc_ddrphy_apb_wr(0x54080,0x0); + dwc_ddrphy_apb_wr(0x54081,0x0); + dwc_ddrphy_apb_wr(0x54082,0x0); + dwc_ddrphy_apb_wr(0x54083,0x0); + dwc_ddrphy_apb_wr(0x54084,0x0); + dwc_ddrphy_apb_wr(0x54085,0x0); + dwc_ddrphy_apb_wr(0x54086,0x0); + dwc_ddrphy_apb_wr(0x54087,0x0); + dwc_ddrphy_apb_wr(0x54088,0x0); + dwc_ddrphy_apb_wr(0x54089,0x0); + dwc_ddrphy_apb_wr(0x5408a,0x0); + dwc_ddrphy_apb_wr(0x5408b,0x0); + dwc_ddrphy_apb_wr(0x5408c,0x0); + dwc_ddrphy_apb_wr(0x5408d,0x0); + dwc_ddrphy_apb_wr(0x5408e,0x0); + dwc_ddrphy_apb_wr(0x5408f,0x0); + dwc_ddrphy_apb_wr(0x54090,0x0); + dwc_ddrphy_apb_wr(0x54091,0x0); + dwc_ddrphy_apb_wr(0x54092,0x0); + dwc_ddrphy_apb_wr(0x54093,0x0); + dwc_ddrphy_apb_wr(0x54094,0x0); + dwc_ddrphy_apb_wr(0x54095,0x0); + dwc_ddrphy_apb_wr(0x54096,0x0); + dwc_ddrphy_apb_wr(0x54097,0x0); + dwc_ddrphy_apb_wr(0x54098,0x0); + dwc_ddrphy_apb_wr(0x54099,0x0); + dwc_ddrphy_apb_wr(0x5409a,0x0); + dwc_ddrphy_apb_wr(0x5409b,0x0); + dwc_ddrphy_apb_wr(0x5409c,0x0); + dwc_ddrphy_apb_wr(0x5409d,0x0); + dwc_ddrphy_apb_wr(0x5409e,0x0); + dwc_ddrphy_apb_wr(0x5409f,0x0); + dwc_ddrphy_apb_wr(0x540a0,0x0); + dwc_ddrphy_apb_wr(0x540a1,0x0); + dwc_ddrphy_apb_wr(0x540a2,0x0); + dwc_ddrphy_apb_wr(0x540a3,0x0); + dwc_ddrphy_apb_wr(0x540a4,0x0); + dwc_ddrphy_apb_wr(0x540a5,0x0); + dwc_ddrphy_apb_wr(0x540a6,0x0); + dwc_ddrphy_apb_wr(0x540a7,0x0); + dwc_ddrphy_apb_wr(0x540a8,0x0); + dwc_ddrphy_apb_wr(0x540a9,0x0); + dwc_ddrphy_apb_wr(0x540aa,0x0); + dwc_ddrphy_apb_wr(0x540ab,0x0); + dwc_ddrphy_apb_wr(0x540ac,0x0); + dwc_ddrphy_apb_wr(0x540ad,0x0); + dwc_ddrphy_apb_wr(0x540ae,0x0); + dwc_ddrphy_apb_wr(0x540af,0x0); + dwc_ddrphy_apb_wr(0x540b0,0x0); + dwc_ddrphy_apb_wr(0x540b1,0x0); + dwc_ddrphy_apb_wr(0x540b2,0x0); + dwc_ddrphy_apb_wr(0x540b3,0x0); + dwc_ddrphy_apb_wr(0x540b4,0x0); + dwc_ddrphy_apb_wr(0x540b5,0x0); + dwc_ddrphy_apb_wr(0x540b6,0x0); + dwc_ddrphy_apb_wr(0x540b7,0x0); + dwc_ddrphy_apb_wr(0x540b8,0x0); + dwc_ddrphy_apb_wr(0x540b9,0x0); + dwc_ddrphy_apb_wr(0x540ba,0x0); + dwc_ddrphy_apb_wr(0x540bb,0x0); + dwc_ddrphy_apb_wr(0x540bc,0x0); + dwc_ddrphy_apb_wr(0x540bd,0x0); + dwc_ddrphy_apb_wr(0x540be,0x0); + dwc_ddrphy_apb_wr(0x540bf,0x0); + dwc_ddrphy_apb_wr(0x540c0,0x0); + dwc_ddrphy_apb_wr(0x540c1,0x0); + dwc_ddrphy_apb_wr(0x540c2,0x0); + dwc_ddrphy_apb_wr(0x540c3,0x0); + dwc_ddrphy_apb_wr(0x540c4,0x0); + dwc_ddrphy_apb_wr(0x540c5,0x0); + dwc_ddrphy_apb_wr(0x540c6,0x0); + dwc_ddrphy_apb_wr(0x540c7,0x0); + dwc_ddrphy_apb_wr(0x540c8,0x0); + dwc_ddrphy_apb_wr(0x540c9,0x0); + dwc_ddrphy_apb_wr(0x540ca,0x0); + dwc_ddrphy_apb_wr(0x540cb,0x0); + dwc_ddrphy_apb_wr(0x540cc,0x0); + dwc_ddrphy_apb_wr(0x540cd,0x0); + dwc_ddrphy_apb_wr(0x540ce,0x0); + dwc_ddrphy_apb_wr(0x540cf,0x0); + dwc_ddrphy_apb_wr(0x540d0,0x0); + dwc_ddrphy_apb_wr(0x540d1,0x0); + dwc_ddrphy_apb_wr(0x540d2,0x0); + dwc_ddrphy_apb_wr(0x540d3,0x0); + dwc_ddrphy_apb_wr(0x540d4,0x0); + dwc_ddrphy_apb_wr(0x540d5,0x0); + dwc_ddrphy_apb_wr(0x540d6,0x0); + dwc_ddrphy_apb_wr(0x540d7,0x0); + dwc_ddrphy_apb_wr(0x540d8,0x0); + dwc_ddrphy_apb_wr(0x540d9,0x0); + dwc_ddrphy_apb_wr(0x540da,0x0); + dwc_ddrphy_apb_wr(0x540db,0x0); + dwc_ddrphy_apb_wr(0x540dc,0x0); + dwc_ddrphy_apb_wr(0x540dd,0x0); + dwc_ddrphy_apb_wr(0x540de,0x0); + dwc_ddrphy_apb_wr(0x540df,0x0); + dwc_ddrphy_apb_wr(0x540e0,0x0); + dwc_ddrphy_apb_wr(0x540e1,0x0); + dwc_ddrphy_apb_wr(0x540e2,0x0); + dwc_ddrphy_apb_wr(0x540e3,0x0); + dwc_ddrphy_apb_wr(0x540e4,0x0); + dwc_ddrphy_apb_wr(0x540e5,0x0); + dwc_ddrphy_apb_wr(0x540e6,0x0); + dwc_ddrphy_apb_wr(0x540e7,0x0); + dwc_ddrphy_apb_wr(0x540e8,0x0); + dwc_ddrphy_apb_wr(0x540e9,0x0); + dwc_ddrphy_apb_wr(0x540ea,0x0); + dwc_ddrphy_apb_wr(0x540eb,0x0); + dwc_ddrphy_apb_wr(0x540ec,0x0); + dwc_ddrphy_apb_wr(0x540ed,0x0); + dwc_ddrphy_apb_wr(0x540ee,0x0); + dwc_ddrphy_apb_wr(0x540ef,0x0); + dwc_ddrphy_apb_wr(0x540f0,0x0); + dwc_ddrphy_apb_wr(0x540f1,0x0); + dwc_ddrphy_apb_wr(0x540f2,0x0); + dwc_ddrphy_apb_wr(0x540f3,0x0); + dwc_ddrphy_apb_wr(0x540f4,0x0); + dwc_ddrphy_apb_wr(0x540f5,0x0); + dwc_ddrphy_apb_wr(0x540f6,0x0); + dwc_ddrphy_apb_wr(0x540f7,0x0); + dwc_ddrphy_apb_wr(0x540f8,0x0); + dwc_ddrphy_apb_wr(0x540f9,0x0); + dwc_ddrphy_apb_wr(0x540fa,0x0); + dwc_ddrphy_apb_wr(0x540fb,0x0); + dwc_ddrphy_apb_wr(0x540fc,0x0); + dwc_ddrphy_apb_wr(0x540fd,0x0); + dwc_ddrphy_apb_wr(0x540fe,0x0); + dwc_ddrphy_apb_wr(0x540ff,0x0); + dwc_ddrphy_apb_wr(0x54100,0x0); + dwc_ddrphy_apb_wr(0x54101,0x0); + dwc_ddrphy_apb_wr(0x54102,0x0); + dwc_ddrphy_apb_wr(0x54103,0x0); + dwc_ddrphy_apb_wr(0x54104,0x0); + dwc_ddrphy_apb_wr(0x54105,0x0); + dwc_ddrphy_apb_wr(0x54106,0x0); + dwc_ddrphy_apb_wr(0x54107,0x0); + dwc_ddrphy_apb_wr(0x54108,0x0); + dwc_ddrphy_apb_wr(0x54109,0x0); + dwc_ddrphy_apb_wr(0x5410a,0x0); + dwc_ddrphy_apb_wr(0x5410b,0x0); + dwc_ddrphy_apb_wr(0x5410c,0x0); + dwc_ddrphy_apb_wr(0x5410d,0x0); + dwc_ddrphy_apb_wr(0x5410e,0x0); + dwc_ddrphy_apb_wr(0x5410f,0x0); + dwc_ddrphy_apb_wr(0x54110,0x0); + dwc_ddrphy_apb_wr(0x54111,0x0); + dwc_ddrphy_apb_wr(0x54112,0x0); + dwc_ddrphy_apb_wr(0x54113,0x0); + dwc_ddrphy_apb_wr(0x54114,0x0); + dwc_ddrphy_apb_wr(0x54115,0x0); + dwc_ddrphy_apb_wr(0x54116,0x0); + dwc_ddrphy_apb_wr(0x54117,0x0); + dwc_ddrphy_apb_wr(0x54118,0x0); + dwc_ddrphy_apb_wr(0x54119,0x0); + dwc_ddrphy_apb_wr(0x5411a,0x0); + dwc_ddrphy_apb_wr(0x5411b,0x0); + dwc_ddrphy_apb_wr(0x5411c,0x0); + dwc_ddrphy_apb_wr(0x5411d,0x0); + dwc_ddrphy_apb_wr(0x5411e,0x0); + dwc_ddrphy_apb_wr(0x5411f,0x0); + dwc_ddrphy_apb_wr(0x54120,0x0); + dwc_ddrphy_apb_wr(0x54121,0x0); + dwc_ddrphy_apb_wr(0x54122,0x0); + dwc_ddrphy_apb_wr(0x54123,0x0); + dwc_ddrphy_apb_wr(0x54124,0x0); + dwc_ddrphy_apb_wr(0x54125,0x0); + dwc_ddrphy_apb_wr(0x54126,0x0); + dwc_ddrphy_apb_wr(0x54127,0x0); + dwc_ddrphy_apb_wr(0x54128,0x0); + dwc_ddrphy_apb_wr(0x54129,0x0); + dwc_ddrphy_apb_wr(0x5412a,0x0); + dwc_ddrphy_apb_wr(0x5412b,0x0); + dwc_ddrphy_apb_wr(0x5412c,0x0); + dwc_ddrphy_apb_wr(0x5412d,0x0); + dwc_ddrphy_apb_wr(0x5412e,0x0); + dwc_ddrphy_apb_wr(0x5412f,0x0); + dwc_ddrphy_apb_wr(0x54130,0x0); + dwc_ddrphy_apb_wr(0x54131,0x0); + dwc_ddrphy_apb_wr(0x54132,0x0); + dwc_ddrphy_apb_wr(0x54133,0x0); + dwc_ddrphy_apb_wr(0x54134,0x0); + dwc_ddrphy_apb_wr(0x54135,0x0); + dwc_ddrphy_apb_wr(0x54136,0x0); + dwc_ddrphy_apb_wr(0x54137,0x0); + dwc_ddrphy_apb_wr(0x54138,0x0); + dwc_ddrphy_apb_wr(0x54139,0x0); + dwc_ddrphy_apb_wr(0x5413a,0x0); + dwc_ddrphy_apb_wr(0x5413b,0x0); + dwc_ddrphy_apb_wr(0x5413c,0x0); + dwc_ddrphy_apb_wr(0x5413d,0x0); + dwc_ddrphy_apb_wr(0x5413e,0x0); + dwc_ddrphy_apb_wr(0x5413f,0x0); + dwc_ddrphy_apb_wr(0x54140,0x0); + dwc_ddrphy_apb_wr(0x54141,0x0); + dwc_ddrphy_apb_wr(0x54142,0x0); + dwc_ddrphy_apb_wr(0x54143,0x0); + dwc_ddrphy_apb_wr(0x54144,0x0); + dwc_ddrphy_apb_wr(0x54145,0x0); + dwc_ddrphy_apb_wr(0x54146,0x0); + dwc_ddrphy_apb_wr(0x54147,0x0); + dwc_ddrphy_apb_wr(0x54148,0x0); + dwc_ddrphy_apb_wr(0x54149,0x0); + dwc_ddrphy_apb_wr(0x5414a,0x0); + dwc_ddrphy_apb_wr(0x5414b,0x0); + dwc_ddrphy_apb_wr(0x5414c,0x0); + dwc_ddrphy_apb_wr(0x5414d,0x0); + dwc_ddrphy_apb_wr(0x5414e,0x0); + dwc_ddrphy_apb_wr(0x5414f,0x0); + dwc_ddrphy_apb_wr(0x54150,0x0); + dwc_ddrphy_apb_wr(0x54151,0x0); + dwc_ddrphy_apb_wr(0x54152,0x0); + dwc_ddrphy_apb_wr(0x54153,0x0); + dwc_ddrphy_apb_wr(0x54154,0x0); + dwc_ddrphy_apb_wr(0x54155,0x0); + dwc_ddrphy_apb_wr(0x54156,0x0); + dwc_ddrphy_apb_wr(0x54157,0x0); + dwc_ddrphy_apb_wr(0x54158,0x0); + dwc_ddrphy_apb_wr(0x54159,0x0); + dwc_ddrphy_apb_wr(0x5415a,0x0); + dwc_ddrphy_apb_wr(0x5415b,0x0); + dwc_ddrphy_apb_wr(0x5415c,0x0); + dwc_ddrphy_apb_wr(0x5415d,0x0); + dwc_ddrphy_apb_wr(0x5415e,0x0); + dwc_ddrphy_apb_wr(0x5415f,0x0); + dwc_ddrphy_apb_wr(0x54160,0x0); + dwc_ddrphy_apb_wr(0x54161,0x0); + dwc_ddrphy_apb_wr(0x54162,0x0); + dwc_ddrphy_apb_wr(0x54163,0x0); + dwc_ddrphy_apb_wr(0x54164,0x0); + dwc_ddrphy_apb_wr(0x54165,0x0); + dwc_ddrphy_apb_wr(0x54166,0x0); + dwc_ddrphy_apb_wr(0x54167,0x0); + dwc_ddrphy_apb_wr(0x54168,0x0); + dwc_ddrphy_apb_wr(0x54169,0x0); + dwc_ddrphy_apb_wr(0x5416a,0x0); + dwc_ddrphy_apb_wr(0x5416b,0x0); + dwc_ddrphy_apb_wr(0x5416c,0x0); + dwc_ddrphy_apb_wr(0x5416d,0x0); + dwc_ddrphy_apb_wr(0x5416e,0x0); + dwc_ddrphy_apb_wr(0x5416f,0x0); + dwc_ddrphy_apb_wr(0x54170,0x0); + dwc_ddrphy_apb_wr(0x54171,0x0); + dwc_ddrphy_apb_wr(0x54172,0x0); + dwc_ddrphy_apb_wr(0x54173,0x0); + dwc_ddrphy_apb_wr(0x54174,0x0); + dwc_ddrphy_apb_wr(0x54175,0x0); + dwc_ddrphy_apb_wr(0x54176,0x0); + dwc_ddrphy_apb_wr(0x54177,0x0); + dwc_ddrphy_apb_wr(0x54178,0x0); + dwc_ddrphy_apb_wr(0x54179,0x0); + dwc_ddrphy_apb_wr(0x5417a,0x0); + dwc_ddrphy_apb_wr(0x5417b,0x0); + dwc_ddrphy_apb_wr(0x5417c,0x0); + dwc_ddrphy_apb_wr(0x5417d,0x0); + dwc_ddrphy_apb_wr(0x5417e,0x0); + dwc_ddrphy_apb_wr(0x5417f,0x0); + dwc_ddrphy_apb_wr(0x54180,0x0); + dwc_ddrphy_apb_wr(0x54181,0x0); + dwc_ddrphy_apb_wr(0x54182,0x0); + dwc_ddrphy_apb_wr(0x54183,0x0); + dwc_ddrphy_apb_wr(0x54184,0x0); + dwc_ddrphy_apb_wr(0x54185,0x0); + dwc_ddrphy_apb_wr(0x54186,0x0); + dwc_ddrphy_apb_wr(0x54187,0x0); + dwc_ddrphy_apb_wr(0x54188,0x0); + dwc_ddrphy_apb_wr(0x54189,0x0); + dwc_ddrphy_apb_wr(0x5418a,0x0); + dwc_ddrphy_apb_wr(0x5418b,0x0); + dwc_ddrphy_apb_wr(0x5418c,0x0); + dwc_ddrphy_apb_wr(0x5418d,0x0); + dwc_ddrphy_apb_wr(0x5418e,0x0); + dwc_ddrphy_apb_wr(0x5418f,0x0); + dwc_ddrphy_apb_wr(0x54190,0x0); + dwc_ddrphy_apb_wr(0x54191,0x0); + dwc_ddrphy_apb_wr(0x54192,0x0); + dwc_ddrphy_apb_wr(0x54193,0x0); + dwc_ddrphy_apb_wr(0x54194,0x0); + dwc_ddrphy_apb_wr(0x54195,0x0); + dwc_ddrphy_apb_wr(0x54196,0x0); + dwc_ddrphy_apb_wr(0x54197,0x0); + dwc_ddrphy_apb_wr(0x54198,0x0); + dwc_ddrphy_apb_wr(0x54199,0x0); + dwc_ddrphy_apb_wr(0x5419a,0x0); + dwc_ddrphy_apb_wr(0x5419b,0x0); + dwc_ddrphy_apb_wr(0x5419c,0x0); + dwc_ddrphy_apb_wr(0x5419d,0x0); + dwc_ddrphy_apb_wr(0x5419e,0x0); + dwc_ddrphy_apb_wr(0x5419f,0x0); + dwc_ddrphy_apb_wr(0x541a0,0x0); + dwc_ddrphy_apb_wr(0x541a1,0x0); + dwc_ddrphy_apb_wr(0x541a2,0x0); + dwc_ddrphy_apb_wr(0x541a3,0x0); + dwc_ddrphy_apb_wr(0x541a4,0x0); + dwc_ddrphy_apb_wr(0x541a5,0x0); + dwc_ddrphy_apb_wr(0x541a6,0x0); + dwc_ddrphy_apb_wr(0x541a7,0x0); + dwc_ddrphy_apb_wr(0x541a8,0x0); + dwc_ddrphy_apb_wr(0x541a9,0x0); + dwc_ddrphy_apb_wr(0x541aa,0x0); + dwc_ddrphy_apb_wr(0x541ab,0x0); + dwc_ddrphy_apb_wr(0x541ac,0x0); + dwc_ddrphy_apb_wr(0x541ad,0x0); + dwc_ddrphy_apb_wr(0x541ae,0x0); + dwc_ddrphy_apb_wr(0x541af,0x0); + dwc_ddrphy_apb_wr(0x541b0,0x0); + dwc_ddrphy_apb_wr(0x541b1,0x0); + dwc_ddrphy_apb_wr(0x541b2,0x0); + dwc_ddrphy_apb_wr(0x541b3,0x0); + dwc_ddrphy_apb_wr(0x541b4,0x0); + dwc_ddrphy_apb_wr(0x541b5,0x0); + dwc_ddrphy_apb_wr(0x541b6,0x0); + dwc_ddrphy_apb_wr(0x541b7,0x0); + dwc_ddrphy_apb_wr(0x541b8,0x0); + dwc_ddrphy_apb_wr(0x541b9,0x0); + dwc_ddrphy_apb_wr(0x541ba,0x0); + dwc_ddrphy_apb_wr(0x541bb,0x0); + dwc_ddrphy_apb_wr(0x541bc,0x0); + dwc_ddrphy_apb_wr(0x541bd,0x0); + dwc_ddrphy_apb_wr(0x541be,0x0); + dwc_ddrphy_apb_wr(0x541bf,0x0); + dwc_ddrphy_apb_wr(0x541c0,0x0); + dwc_ddrphy_apb_wr(0x541c1,0x0); + dwc_ddrphy_apb_wr(0x541c2,0x0); + dwc_ddrphy_apb_wr(0x541c3,0x0); + dwc_ddrphy_apb_wr(0x541c4,0x0); + dwc_ddrphy_apb_wr(0x541c5,0x0); + dwc_ddrphy_apb_wr(0x541c6,0x0); + dwc_ddrphy_apb_wr(0x541c7,0x0); + dwc_ddrphy_apb_wr(0x541c8,0x0); + dwc_ddrphy_apb_wr(0x541c9,0x0); + dwc_ddrphy_apb_wr(0x541ca,0x0); + dwc_ddrphy_apb_wr(0x541cb,0x0); + dwc_ddrphy_apb_wr(0x541cc,0x0); + dwc_ddrphy_apb_wr(0x541cd,0x0); + dwc_ddrphy_apb_wr(0x541ce,0x0); + dwc_ddrphy_apb_wr(0x541cf,0x0); + dwc_ddrphy_apb_wr(0x541d0,0x0); + dwc_ddrphy_apb_wr(0x541d1,0x0); + dwc_ddrphy_apb_wr(0x541d2,0x0); + dwc_ddrphy_apb_wr(0x541d3,0x0); + dwc_ddrphy_apb_wr(0x541d4,0x0); + dwc_ddrphy_apb_wr(0x541d5,0x0); + dwc_ddrphy_apb_wr(0x541d6,0x0); + dwc_ddrphy_apb_wr(0x541d7,0x0); + dwc_ddrphy_apb_wr(0x541d8,0x0); + dwc_ddrphy_apb_wr(0x541d9,0x0); + dwc_ddrphy_apb_wr(0x541da,0x0); + dwc_ddrphy_apb_wr(0x541db,0x0); + dwc_ddrphy_apb_wr(0x541dc,0x0); + dwc_ddrphy_apb_wr(0x541dd,0x0); + dwc_ddrphy_apb_wr(0x541de,0x0); + dwc_ddrphy_apb_wr(0x541df,0x0); + dwc_ddrphy_apb_wr(0x541e0,0x0); + dwc_ddrphy_apb_wr(0x541e1,0x0); + dwc_ddrphy_apb_wr(0x541e2,0x0); + dwc_ddrphy_apb_wr(0x541e3,0x0); + dwc_ddrphy_apb_wr(0x541e4,0x0); + dwc_ddrphy_apb_wr(0x541e5,0x0); + dwc_ddrphy_apb_wr(0x541e6,0x0); + dwc_ddrphy_apb_wr(0x541e7,0x0); + dwc_ddrphy_apb_wr(0x541e8,0x0); + dwc_ddrphy_apb_wr(0x541e9,0x0); + dwc_ddrphy_apb_wr(0x541ea,0x0); + dwc_ddrphy_apb_wr(0x541eb,0x0); + dwc_ddrphy_apb_wr(0x541ec,0x0); + dwc_ddrphy_apb_wr(0x541ed,0x0); + dwc_ddrphy_apb_wr(0x541ee,0x0); + dwc_ddrphy_apb_wr(0x541ef,0x0); + dwc_ddrphy_apb_wr(0x541f0,0x0); + dwc_ddrphy_apb_wr(0x541f1,0x0); + dwc_ddrphy_apb_wr(0x541f2,0x0); + dwc_ddrphy_apb_wr(0x541f3,0x0); + dwc_ddrphy_apb_wr(0x541f4,0x0); + dwc_ddrphy_apb_wr(0x541f5,0x0); + dwc_ddrphy_apb_wr(0x541f6,0x0); + dwc_ddrphy_apb_wr(0x541f7,0x0); + dwc_ddrphy_apb_wr(0x541f8,0x0); + dwc_ddrphy_apb_wr(0x541f9,0x0); + dwc_ddrphy_apb_wr(0x541fa,0x0); + dwc_ddrphy_apb_wr(0x541fb,0x0); + dwc_ddrphy_apb_wr(0x541fc,0x100); + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099,0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + + wait_ddrphy_training_complete(); + + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + + ddr_load_train_code(FW_2D_IMAGE); + + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x54000,0x80);/* should be 0x80 in silicon */ + dwc_ddrphy_apb_wr(0x54001,0x0); + dwc_ddrphy_apb_wr(0x54002,0x0); + dwc_ddrphy_apb_wr(0x54003,0x960); + dwc_ddrphy_apb_wr(0x54004,0x2); + + dwc_ddrphy_apb_wr(0x54005,((PHY_RON<<8)|(PHY_RTT<<0))/*0x2830*/); + dwc_ddrphy_apb_wr(0x54006,(0x200|PHYREF_VALUE)/*0x23b*/); + dwc_ddrphy_apb_wr(0x54007,0x2000); + + dwc_ddrphy_apb_wr(0x54008,0x303); + + dwc_ddrphy_apb_wr(0x54009,0x200); + dwc_ddrphy_apb_wr(0x5400a,0x0); + dwc_ddrphy_apb_wr(0x5400b,0x61);/* should be 0x61 in silicon */ + + dwc_ddrphy_apb_wr(0x5400c,0xc8); /* 0xc8 indicates stage completion messages showed */ + + dwc_ddrphy_apb_wr(0x5400d,0x0); + dwc_ddrphy_apb_wr(0x5400e,0x8020); + dwc_ddrphy_apb_wr(0x5400f,0x0); + dwc_ddrphy_apb_wr(0x54010,0x0); + dwc_ddrphy_apb_wr(0x54011,0x0); + dwc_ddrphy_apb_wr(0x54012,0x1); + dwc_ddrphy_apb_wr(0x54013,0x0); + dwc_ddrphy_apb_wr(0x54014,0x0); + dwc_ddrphy_apb_wr(0x54015,0x0); + dwc_ddrphy_apb_wr(0x54016,0x0); + dwc_ddrphy_apb_wr(0x54017,0x0); + dwc_ddrphy_apb_wr(0x54018,0x0); + dwc_ddrphy_apb_wr(0x54019,0x0); + dwc_ddrphy_apb_wr(0x5401a,0x0); + dwc_ddrphy_apb_wr(0x5401b,0x0); + dwc_ddrphy_apb_wr(0x5401c,0x0); + dwc_ddrphy_apb_wr(0x5401d,0x0); + dwc_ddrphy_apb_wr(0x5401e,0x0); + dwc_ddrphy_apb_wr(0x5401f,0x0); + dwc_ddrphy_apb_wr(0x54020,0x0); + dwc_ddrphy_apb_wr(0x54021,0x0); + dwc_ddrphy_apb_wr(0x54022,0x0); + dwc_ddrphy_apb_wr(0x54023,0x0); + dwc_ddrphy_apb_wr(0x54024,0x0); + dwc_ddrphy_apb_wr(0x54025,0x0); + dwc_ddrphy_apb_wr(0x54026,0x0); + dwc_ddrphy_apb_wr(0x54027,0x0); + dwc_ddrphy_apb_wr(0x54028,0x0); + dwc_ddrphy_apb_wr(0x54029,0x0); + dwc_ddrphy_apb_wr(0x5402a,0x0); + dwc_ddrphy_apb_wr(0x5402b,0x0); + dwc_ddrphy_apb_wr(0x5402c,0x0); + dwc_ddrphy_apb_wr(0x5402d,0x0); + dwc_ddrphy_apb_wr(0x5402e,0x0); + + dwc_ddrphy_apb_wr(0x5402f,0xa30);/* MR0 */ + dwc_ddrphy_apb_wr(0x54030, ((DDR_RTT<<8)|(DDR_RON<<1)|0x1)/*0x1*/);/* MR1 */ + dwc_ddrphy_apb_wr(0x54031,0x1018);/* MR2 */ + dwc_ddrphy_apb_wr(0x54032,0x240);/* MR3 */ + dwc_ddrphy_apb_wr(0x54033,0xa00);/* MR4 */ + dwc_ddrphy_apb_wr(0x54034,0x42);/* MR5 */ + dwc_ddrphy_apb_wr(0x54035,(0x800|MR6_VALUE)/*0x800*/);/* MR6 */ + + dwc_ddrphy_apb_wr(0x54036,0x103); + dwc_ddrphy_apb_wr(0x54037,0x0); + dwc_ddrphy_apb_wr(0x54038,0x0); + dwc_ddrphy_apb_wr(0x54039,0x0); + dwc_ddrphy_apb_wr(0x5403a,0x0); + dwc_ddrphy_apb_wr(0x5403b,0x0); + dwc_ddrphy_apb_wr(0x5403c,0x0); + dwc_ddrphy_apb_wr(0x5403d,0x0); + dwc_ddrphy_apb_wr(0x5403e,0x0); + dwc_ddrphy_apb_wr(0x5403f,0x1221); + dwc_ddrphy_apb_wr(0x54040,0x0); + dwc_ddrphy_apb_wr(0x54041,0x0); + dwc_ddrphy_apb_wr(0x54042,0x0); + dwc_ddrphy_apb_wr(0x54043,0x0); + dwc_ddrphy_apb_wr(0x54044,0x0); + dwc_ddrphy_apb_wr(0x54045,0x0); + dwc_ddrphy_apb_wr(0x54046,0x0); + dwc_ddrphy_apb_wr(0x54047,0x0); + dwc_ddrphy_apb_wr(0x54048,0x0); + dwc_ddrphy_apb_wr(0x54049,0x0); + dwc_ddrphy_apb_wr(0x5404a,0x0); + dwc_ddrphy_apb_wr(0x5404b,0x0); + dwc_ddrphy_apb_wr(0x5404c,0x0); + dwc_ddrphy_apb_wr(0x5404d,0x0); + dwc_ddrphy_apb_wr(0x5404e,0x0); + dwc_ddrphy_apb_wr(0x5404f,0x0); + dwc_ddrphy_apb_wr(0x54050,0x0); + dwc_ddrphy_apb_wr(0x54051,0x0); + dwc_ddrphy_apb_wr(0x54052,0x0); + dwc_ddrphy_apb_wr(0x54053,0x0); + dwc_ddrphy_apb_wr(0x54054,0x0); + dwc_ddrphy_apb_wr(0x54055,0x0); + dwc_ddrphy_apb_wr(0x54056,0x0); + dwc_ddrphy_apb_wr(0x54057,0x0); + dwc_ddrphy_apb_wr(0x54058,0x0); + dwc_ddrphy_apb_wr(0x54059,0x0); + dwc_ddrphy_apb_wr(0x5405a,0x0); + dwc_ddrphy_apb_wr(0x5405b,0x0); + dwc_ddrphy_apb_wr(0x5405c,0x0); + dwc_ddrphy_apb_wr(0x5405d,0x0); + dwc_ddrphy_apb_wr(0x5405e,0x0); + dwc_ddrphy_apb_wr(0x5405f,0x0); + dwc_ddrphy_apb_wr(0x54060,0x0); + dwc_ddrphy_apb_wr(0x54061,0x0); + dwc_ddrphy_apb_wr(0x54062,0x0); + dwc_ddrphy_apb_wr(0x54063,0x0); + dwc_ddrphy_apb_wr(0x54064,0x0); + dwc_ddrphy_apb_wr(0x54065,0x0); + dwc_ddrphy_apb_wr(0x54066,0x0); + dwc_ddrphy_apb_wr(0x54067,0x0); + dwc_ddrphy_apb_wr(0x54068,0x0); + dwc_ddrphy_apb_wr(0x54069,0x0); + dwc_ddrphy_apb_wr(0x5406a,0x0); + dwc_ddrphy_apb_wr(0x5406b,0x0); + dwc_ddrphy_apb_wr(0x5406c,0x0); + dwc_ddrphy_apb_wr(0x5406d,0x0); + dwc_ddrphy_apb_wr(0x5406e,0x0); + dwc_ddrphy_apb_wr(0x5406f,0x0); + dwc_ddrphy_apb_wr(0x54070,0x0); + dwc_ddrphy_apb_wr(0x54071,0x0); + dwc_ddrphy_apb_wr(0x54072,0x0); + dwc_ddrphy_apb_wr(0x54073,0x0); + dwc_ddrphy_apb_wr(0x54074,0x0); + dwc_ddrphy_apb_wr(0x54075,0x0); + dwc_ddrphy_apb_wr(0x54076,0x0); + dwc_ddrphy_apb_wr(0x54077,0x0); + dwc_ddrphy_apb_wr(0x54078,0x0); + dwc_ddrphy_apb_wr(0x54079,0x0); + dwc_ddrphy_apb_wr(0x5407a,0x0); + dwc_ddrphy_apb_wr(0x5407b,0x0); + dwc_ddrphy_apb_wr(0x5407c,0x0); + dwc_ddrphy_apb_wr(0x5407d,0x0); + dwc_ddrphy_apb_wr(0x5407e,0x0); + dwc_ddrphy_apb_wr(0x5407f,0x0); + dwc_ddrphy_apb_wr(0x54080,0x0); + dwc_ddrphy_apb_wr(0x54081,0x0); + dwc_ddrphy_apb_wr(0x54082,0x0); + dwc_ddrphy_apb_wr(0x54083,0x0); + dwc_ddrphy_apb_wr(0x54084,0x0); + dwc_ddrphy_apb_wr(0x54085,0x0); + dwc_ddrphy_apb_wr(0x54086,0x0); + dwc_ddrphy_apb_wr(0x54087,0x0); + dwc_ddrphy_apb_wr(0x54088,0x0); + dwc_ddrphy_apb_wr(0x54089,0x0); + dwc_ddrphy_apb_wr(0x5408a,0x0); + dwc_ddrphy_apb_wr(0x5408b,0x0); + dwc_ddrphy_apb_wr(0x5408c,0x0); + dwc_ddrphy_apb_wr(0x5408d,0x0); + dwc_ddrphy_apb_wr(0x5408e,0x0); + dwc_ddrphy_apb_wr(0x5408f,0x0); + dwc_ddrphy_apb_wr(0x54090,0x0); + dwc_ddrphy_apb_wr(0x54091,0x0); + dwc_ddrphy_apb_wr(0x54092,0x0); + dwc_ddrphy_apb_wr(0x54093,0x0); + dwc_ddrphy_apb_wr(0x54094,0x0); + dwc_ddrphy_apb_wr(0x54095,0x0); + dwc_ddrphy_apb_wr(0x54096,0x0); + dwc_ddrphy_apb_wr(0x54097,0x0); + dwc_ddrphy_apb_wr(0x54098,0x0); + dwc_ddrphy_apb_wr(0x54099,0x0); + dwc_ddrphy_apb_wr(0x5409a,0x0); + dwc_ddrphy_apb_wr(0x5409b,0x0); + dwc_ddrphy_apb_wr(0x5409c,0x0); + dwc_ddrphy_apb_wr(0x5409d,0x0); + dwc_ddrphy_apb_wr(0x5409e,0x0); + dwc_ddrphy_apb_wr(0x5409f,0x0); + dwc_ddrphy_apb_wr(0x540a0,0x0); + dwc_ddrphy_apb_wr(0x540a1,0x0); + dwc_ddrphy_apb_wr(0x540a2,0x0); + dwc_ddrphy_apb_wr(0x540a3,0x0); + dwc_ddrphy_apb_wr(0x540a4,0x0); + dwc_ddrphy_apb_wr(0x540a5,0x0); + dwc_ddrphy_apb_wr(0x540a6,0x0); + dwc_ddrphy_apb_wr(0x540a7,0x0); + dwc_ddrphy_apb_wr(0x540a8,0x0); + dwc_ddrphy_apb_wr(0x540a9,0x0); + dwc_ddrphy_apb_wr(0x540aa,0x0); + dwc_ddrphy_apb_wr(0x540ab,0x0); + dwc_ddrphy_apb_wr(0x540ac,0x0); + dwc_ddrphy_apb_wr(0x540ad,0x0); + dwc_ddrphy_apb_wr(0x540ae,0x0); + dwc_ddrphy_apb_wr(0x540af,0x0); + dwc_ddrphy_apb_wr(0x540b0,0x0); + dwc_ddrphy_apb_wr(0x540b1,0x0); + dwc_ddrphy_apb_wr(0x540b2,0x0); + dwc_ddrphy_apb_wr(0x540b3,0x0); + dwc_ddrphy_apb_wr(0x540b4,0x0); + dwc_ddrphy_apb_wr(0x540b5,0x0); + dwc_ddrphy_apb_wr(0x540b6,0x0); + dwc_ddrphy_apb_wr(0x540b7,0x0); + dwc_ddrphy_apb_wr(0x540b8,0x0); + dwc_ddrphy_apb_wr(0x540b9,0x0); + dwc_ddrphy_apb_wr(0x540ba,0x0); + dwc_ddrphy_apb_wr(0x540bb,0x0); + dwc_ddrphy_apb_wr(0x540bc,0x0); + dwc_ddrphy_apb_wr(0x540bd,0x0); + dwc_ddrphy_apb_wr(0x540be,0x0); + dwc_ddrphy_apb_wr(0x540bf,0x0); + dwc_ddrphy_apb_wr(0x540c0,0x0); + dwc_ddrphy_apb_wr(0x540c1,0x0); + dwc_ddrphy_apb_wr(0x540c2,0x0); + dwc_ddrphy_apb_wr(0x540c3,0x0); + dwc_ddrphy_apb_wr(0x540c4,0x0); + dwc_ddrphy_apb_wr(0x540c5,0x0); + dwc_ddrphy_apb_wr(0x540c6,0x0); + dwc_ddrphy_apb_wr(0x540c7,0x0); + dwc_ddrphy_apb_wr(0x540c8,0x0); + dwc_ddrphy_apb_wr(0x540c9,0x0); + dwc_ddrphy_apb_wr(0x540ca,0x0); + dwc_ddrphy_apb_wr(0x540cb,0x0); + dwc_ddrphy_apb_wr(0x540cc,0x0); + dwc_ddrphy_apb_wr(0x540cd,0x0); + dwc_ddrphy_apb_wr(0x540ce,0x0); + dwc_ddrphy_apb_wr(0x540cf,0x0); + dwc_ddrphy_apb_wr(0x540d0,0x0); + dwc_ddrphy_apb_wr(0x540d1,0x0); + dwc_ddrphy_apb_wr(0x540d2,0x0); + dwc_ddrphy_apb_wr(0x540d3,0x0); + dwc_ddrphy_apb_wr(0x540d4,0x0); + dwc_ddrphy_apb_wr(0x540d5,0x0); + dwc_ddrphy_apb_wr(0x540d6,0x0); + dwc_ddrphy_apb_wr(0x540d7,0x0); + dwc_ddrphy_apb_wr(0x540d8,0x0); + dwc_ddrphy_apb_wr(0x540d9,0x0); + dwc_ddrphy_apb_wr(0x540da,0x0); + dwc_ddrphy_apb_wr(0x540db,0x0); + dwc_ddrphy_apb_wr(0x540dc,0x0); + dwc_ddrphy_apb_wr(0x540dd,0x0); + dwc_ddrphy_apb_wr(0x540de,0x0); + dwc_ddrphy_apb_wr(0x540df,0x0); + dwc_ddrphy_apb_wr(0x540e0,0x0); + dwc_ddrphy_apb_wr(0x540e1,0x0); + dwc_ddrphy_apb_wr(0x540e2,0x0); + dwc_ddrphy_apb_wr(0x540e3,0x0); + dwc_ddrphy_apb_wr(0x540e4,0x0); + dwc_ddrphy_apb_wr(0x540e5,0x0); + dwc_ddrphy_apb_wr(0x540e6,0x0); + dwc_ddrphy_apb_wr(0x540e7,0x0); + dwc_ddrphy_apb_wr(0x540e8,0x0); + dwc_ddrphy_apb_wr(0x540e9,0x0); + dwc_ddrphy_apb_wr(0x540ea,0x0); + dwc_ddrphy_apb_wr(0x540eb,0x0); + dwc_ddrphy_apb_wr(0x540ec,0x0); + dwc_ddrphy_apb_wr(0x540ed,0x0); + dwc_ddrphy_apb_wr(0x540ee,0x0); + dwc_ddrphy_apb_wr(0x540ef,0x0); + dwc_ddrphy_apb_wr(0x540f0,0x0); + dwc_ddrphy_apb_wr(0x540f1,0x0); + dwc_ddrphy_apb_wr(0x540f2,0x0); + dwc_ddrphy_apb_wr(0x540f3,0x0); + dwc_ddrphy_apb_wr(0x540f4,0x0); + dwc_ddrphy_apb_wr(0x540f5,0x0); + dwc_ddrphy_apb_wr(0x540f6,0x0); + dwc_ddrphy_apb_wr(0x540f7,0x0); + dwc_ddrphy_apb_wr(0x540f8,0x0); + dwc_ddrphy_apb_wr(0x540f9,0x0); + dwc_ddrphy_apb_wr(0x540fa,0x0); + dwc_ddrphy_apb_wr(0x540fb,0x0); + dwc_ddrphy_apb_wr(0x540fc,0x0); + dwc_ddrphy_apb_wr(0x540fd,0x0); + dwc_ddrphy_apb_wr(0x540fe,0x0); + dwc_ddrphy_apb_wr(0x540ff,0x0); + dwc_ddrphy_apb_wr(0x54100,0x0); + dwc_ddrphy_apb_wr(0x54101,0x0); + dwc_ddrphy_apb_wr(0x54102,0x0); + dwc_ddrphy_apb_wr(0x54103,0x0); + dwc_ddrphy_apb_wr(0x54104,0x0); + dwc_ddrphy_apb_wr(0x54105,0x0); + dwc_ddrphy_apb_wr(0x54106,0x0); + dwc_ddrphy_apb_wr(0x54107,0x0); + dwc_ddrphy_apb_wr(0x54108,0x0); + dwc_ddrphy_apb_wr(0x54109,0x0); + dwc_ddrphy_apb_wr(0x5410a,0x0); + dwc_ddrphy_apb_wr(0x5410b,0x0); + dwc_ddrphy_apb_wr(0x5410c,0x0); + dwc_ddrphy_apb_wr(0x5410d,0x0); + dwc_ddrphy_apb_wr(0x5410e,0x0); + dwc_ddrphy_apb_wr(0x5410f,0x0); + dwc_ddrphy_apb_wr(0x54110,0x0); + dwc_ddrphy_apb_wr(0x54111,0x0); + dwc_ddrphy_apb_wr(0x54112,0x0); + dwc_ddrphy_apb_wr(0x54113,0x0); + dwc_ddrphy_apb_wr(0x54114,0x0); + dwc_ddrphy_apb_wr(0x54115,0x0); + dwc_ddrphy_apb_wr(0x54116,0x0); + dwc_ddrphy_apb_wr(0x54117,0x0); + dwc_ddrphy_apb_wr(0x54118,0x0); + dwc_ddrphy_apb_wr(0x54119,0x0); + dwc_ddrphy_apb_wr(0x5411a,0x0); + dwc_ddrphy_apb_wr(0x5411b,0x0); + dwc_ddrphy_apb_wr(0x5411c,0x0); + dwc_ddrphy_apb_wr(0x5411d,0x0); + dwc_ddrphy_apb_wr(0x5411e,0x0); + dwc_ddrphy_apb_wr(0x5411f,0x0); + dwc_ddrphy_apb_wr(0x54120,0x0); + dwc_ddrphy_apb_wr(0x54121,0x0); + dwc_ddrphy_apb_wr(0x54122,0x0); + dwc_ddrphy_apb_wr(0x54123,0x0); + dwc_ddrphy_apb_wr(0x54124,0x0); + dwc_ddrphy_apb_wr(0x54125,0x0); + dwc_ddrphy_apb_wr(0x54126,0x0); + dwc_ddrphy_apb_wr(0x54127,0x0); + dwc_ddrphy_apb_wr(0x54128,0x0); + dwc_ddrphy_apb_wr(0x54129,0x0); + dwc_ddrphy_apb_wr(0x5412a,0x0); + dwc_ddrphy_apb_wr(0x5412b,0x0); + dwc_ddrphy_apb_wr(0x5412c,0x0); + dwc_ddrphy_apb_wr(0x5412d,0x0); + dwc_ddrphy_apb_wr(0x5412e,0x0); + dwc_ddrphy_apb_wr(0x5412f,0x0); + dwc_ddrphy_apb_wr(0x54130,0x0); + dwc_ddrphy_apb_wr(0x54131,0x0); + dwc_ddrphy_apb_wr(0x54132,0x0); + dwc_ddrphy_apb_wr(0x54133,0x0); + dwc_ddrphy_apb_wr(0x54134,0x0); + dwc_ddrphy_apb_wr(0x54135,0x0); + dwc_ddrphy_apb_wr(0x54136,0x0); + dwc_ddrphy_apb_wr(0x54137,0x0); + dwc_ddrphy_apb_wr(0x54138,0x0); + dwc_ddrphy_apb_wr(0x54139,0x0); + dwc_ddrphy_apb_wr(0x5413a,0x0); + dwc_ddrphy_apb_wr(0x5413b,0x0); + dwc_ddrphy_apb_wr(0x5413c,0x0); + dwc_ddrphy_apb_wr(0x5413d,0x0); + dwc_ddrphy_apb_wr(0x5413e,0x0); + dwc_ddrphy_apb_wr(0x5413f,0x0); + dwc_ddrphy_apb_wr(0x54140,0x0); + dwc_ddrphy_apb_wr(0x54141,0x0); + dwc_ddrphy_apb_wr(0x54142,0x0); + dwc_ddrphy_apb_wr(0x54143,0x0); + dwc_ddrphy_apb_wr(0x54144,0x0); + dwc_ddrphy_apb_wr(0x54145,0x0); + dwc_ddrphy_apb_wr(0x54146,0x0); + dwc_ddrphy_apb_wr(0x54147,0x0); + dwc_ddrphy_apb_wr(0x54148,0x0); + dwc_ddrphy_apb_wr(0x54149,0x0); + dwc_ddrphy_apb_wr(0x5414a,0x0); + dwc_ddrphy_apb_wr(0x5414b,0x0); + dwc_ddrphy_apb_wr(0x5414c,0x0); + dwc_ddrphy_apb_wr(0x5414d,0x0); + dwc_ddrphy_apb_wr(0x5414e,0x0); + dwc_ddrphy_apb_wr(0x5414f,0x0); + dwc_ddrphy_apb_wr(0x54150,0x0); + dwc_ddrphy_apb_wr(0x54151,0x0); + dwc_ddrphy_apb_wr(0x54152,0x0); + dwc_ddrphy_apb_wr(0x54153,0x0); + dwc_ddrphy_apb_wr(0x54154,0x0); + dwc_ddrphy_apb_wr(0x54155,0x0); + dwc_ddrphy_apb_wr(0x54156,0x0); + dwc_ddrphy_apb_wr(0x54157,0x0); + dwc_ddrphy_apb_wr(0x54158,0x0); + dwc_ddrphy_apb_wr(0x54159,0x0); + dwc_ddrphy_apb_wr(0x5415a,0x0); + dwc_ddrphy_apb_wr(0x5415b,0x0); + dwc_ddrphy_apb_wr(0x5415c,0x0); + dwc_ddrphy_apb_wr(0x5415d,0x0); + dwc_ddrphy_apb_wr(0x5415e,0x0); + dwc_ddrphy_apb_wr(0x5415f,0x0); + dwc_ddrphy_apb_wr(0x54160,0x0); + dwc_ddrphy_apb_wr(0x54161,0x0); + dwc_ddrphy_apb_wr(0x54162,0x0); + dwc_ddrphy_apb_wr(0x54163,0x0); + dwc_ddrphy_apb_wr(0x54164,0x0); + dwc_ddrphy_apb_wr(0x54165,0x0); + dwc_ddrphy_apb_wr(0x54166,0x0); + dwc_ddrphy_apb_wr(0x54167,0x0); + dwc_ddrphy_apb_wr(0x54168,0x0); + dwc_ddrphy_apb_wr(0x54169,0x0); + dwc_ddrphy_apb_wr(0x5416a,0x0); + dwc_ddrphy_apb_wr(0x5416b,0x0); + dwc_ddrphy_apb_wr(0x5416c,0x0); + dwc_ddrphy_apb_wr(0x5416d,0x0); + dwc_ddrphy_apb_wr(0x5416e,0x0); + dwc_ddrphy_apb_wr(0x5416f,0x0); + dwc_ddrphy_apb_wr(0x54170,0x0); + dwc_ddrphy_apb_wr(0x54171,0x0); + dwc_ddrphy_apb_wr(0x54172,0x0); + dwc_ddrphy_apb_wr(0x54173,0x0); + dwc_ddrphy_apb_wr(0x54174,0x0); + dwc_ddrphy_apb_wr(0x54175,0x0); + dwc_ddrphy_apb_wr(0x54176,0x0); + dwc_ddrphy_apb_wr(0x54177,0x0); + dwc_ddrphy_apb_wr(0x54178,0x0); + dwc_ddrphy_apb_wr(0x54179,0x0); + dwc_ddrphy_apb_wr(0x5417a,0x0); + dwc_ddrphy_apb_wr(0x5417b,0x0); + dwc_ddrphy_apb_wr(0x5417c,0x0); + dwc_ddrphy_apb_wr(0x5417d,0x0); + dwc_ddrphy_apb_wr(0x5417e,0x0); + dwc_ddrphy_apb_wr(0x5417f,0x0); + dwc_ddrphy_apb_wr(0x54180,0x0); + dwc_ddrphy_apb_wr(0x54181,0x0); + dwc_ddrphy_apb_wr(0x54182,0x0); + dwc_ddrphy_apb_wr(0x54183,0x0); + dwc_ddrphy_apb_wr(0x54184,0x0); + dwc_ddrphy_apb_wr(0x54185,0x0); + dwc_ddrphy_apb_wr(0x54186,0x0); + dwc_ddrphy_apb_wr(0x54187,0x0); + dwc_ddrphy_apb_wr(0x54188,0x0); + dwc_ddrphy_apb_wr(0x54189,0x0); + dwc_ddrphy_apb_wr(0x5418a,0x0); + dwc_ddrphy_apb_wr(0x5418b,0x0); + dwc_ddrphy_apb_wr(0x5418c,0x0); + dwc_ddrphy_apb_wr(0x5418d,0x0); + dwc_ddrphy_apb_wr(0x5418e,0x0); + dwc_ddrphy_apb_wr(0x5418f,0x0); + dwc_ddrphy_apb_wr(0x54190,0x0); + dwc_ddrphy_apb_wr(0x54191,0x0); + dwc_ddrphy_apb_wr(0x54192,0x0); + dwc_ddrphy_apb_wr(0x54193,0x0); + dwc_ddrphy_apb_wr(0x54194,0x0); + dwc_ddrphy_apb_wr(0x54195,0x0); + dwc_ddrphy_apb_wr(0x54196,0x0); + dwc_ddrphy_apb_wr(0x54197,0x0); + dwc_ddrphy_apb_wr(0x54198,0x0); + dwc_ddrphy_apb_wr(0x54199,0x0); + dwc_ddrphy_apb_wr(0x5419a,0x0); + dwc_ddrphy_apb_wr(0x5419b,0x0); + dwc_ddrphy_apb_wr(0x5419c,0x0); + dwc_ddrphy_apb_wr(0x5419d,0x0); + dwc_ddrphy_apb_wr(0x5419e,0x0); + dwc_ddrphy_apb_wr(0x5419f,0x0); + dwc_ddrphy_apb_wr(0x541a0,0x0); + dwc_ddrphy_apb_wr(0x541a1,0x0); + dwc_ddrphy_apb_wr(0x541a2,0x0); + dwc_ddrphy_apb_wr(0x541a3,0x0); + dwc_ddrphy_apb_wr(0x541a4,0x0); + dwc_ddrphy_apb_wr(0x541a5,0x0); + dwc_ddrphy_apb_wr(0x541a6,0x0); + dwc_ddrphy_apb_wr(0x541a7,0x0); + dwc_ddrphy_apb_wr(0x541a8,0x0); + dwc_ddrphy_apb_wr(0x541a9,0x0); + dwc_ddrphy_apb_wr(0x541aa,0x0); + dwc_ddrphy_apb_wr(0x541ab,0x0); + dwc_ddrphy_apb_wr(0x541ac,0x0); + dwc_ddrphy_apb_wr(0x541ad,0x0); + dwc_ddrphy_apb_wr(0x541ae,0x0); + dwc_ddrphy_apb_wr(0x541af,0x0); + dwc_ddrphy_apb_wr(0x541b0,0x0); + dwc_ddrphy_apb_wr(0x541b1,0x0); + dwc_ddrphy_apb_wr(0x541b2,0x0); + dwc_ddrphy_apb_wr(0x541b3,0x0); + dwc_ddrphy_apb_wr(0x541b4,0x0); + dwc_ddrphy_apb_wr(0x541b5,0x0); + dwc_ddrphy_apb_wr(0x541b6,0x0); + dwc_ddrphy_apb_wr(0x541b7,0x0); + dwc_ddrphy_apb_wr(0x541b8,0x0); + dwc_ddrphy_apb_wr(0x541b9,0x0); + dwc_ddrphy_apb_wr(0x541ba,0x0); + dwc_ddrphy_apb_wr(0x541bb,0x0); + dwc_ddrphy_apb_wr(0x541bc,0x0); + dwc_ddrphy_apb_wr(0x541bd,0x0); + dwc_ddrphy_apb_wr(0x541be,0x0); + dwc_ddrphy_apb_wr(0x541bf,0x0); + dwc_ddrphy_apb_wr(0x541c0,0x0); + dwc_ddrphy_apb_wr(0x541c1,0x0); + dwc_ddrphy_apb_wr(0x541c2,0x0); + dwc_ddrphy_apb_wr(0x541c3,0x0); + dwc_ddrphy_apb_wr(0x541c4,0x0); + dwc_ddrphy_apb_wr(0x541c5,0x0); + dwc_ddrphy_apb_wr(0x541c6,0x0); + dwc_ddrphy_apb_wr(0x541c7,0x0); + dwc_ddrphy_apb_wr(0x541c8,0x0); + dwc_ddrphy_apb_wr(0x541c9,0x0); + dwc_ddrphy_apb_wr(0x541ca,0x0); + dwc_ddrphy_apb_wr(0x541cb,0x0); + dwc_ddrphy_apb_wr(0x541cc,0x0); + dwc_ddrphy_apb_wr(0x541cd,0x0); + dwc_ddrphy_apb_wr(0x541ce,0x0); + dwc_ddrphy_apb_wr(0x541cf,0x0); + dwc_ddrphy_apb_wr(0x541d0,0x0); + dwc_ddrphy_apb_wr(0x541d1,0x0); + dwc_ddrphy_apb_wr(0x541d2,0x0); + dwc_ddrphy_apb_wr(0x541d3,0x0); + dwc_ddrphy_apb_wr(0x541d4,0x0); + dwc_ddrphy_apb_wr(0x541d5,0x0); + dwc_ddrphy_apb_wr(0x541d6,0x0); + dwc_ddrphy_apb_wr(0x541d7,0x0); + dwc_ddrphy_apb_wr(0x541d8,0x0); + dwc_ddrphy_apb_wr(0x541d9,0x0); + dwc_ddrphy_apb_wr(0x541da,0x0); + dwc_ddrphy_apb_wr(0x541db,0x0); + dwc_ddrphy_apb_wr(0x541dc,0x0); + dwc_ddrphy_apb_wr(0x541dd,0x0); + dwc_ddrphy_apb_wr(0x541de,0x0); + dwc_ddrphy_apb_wr(0x541df,0x0); + dwc_ddrphy_apb_wr(0x541e0,0x0); + dwc_ddrphy_apb_wr(0x541e1,0x0); + dwc_ddrphy_apb_wr(0x541e2,0x0); + dwc_ddrphy_apb_wr(0x541e3,0x0); + dwc_ddrphy_apb_wr(0x541e4,0x0); + dwc_ddrphy_apb_wr(0x541e5,0x0); + dwc_ddrphy_apb_wr(0x541e6,0x0); + dwc_ddrphy_apb_wr(0x541e7,0x0); + dwc_ddrphy_apb_wr(0x541e8,0x0); + dwc_ddrphy_apb_wr(0x541e9,0x0); + dwc_ddrphy_apb_wr(0x541ea,0x0); + dwc_ddrphy_apb_wr(0x541eb,0x0); + dwc_ddrphy_apb_wr(0x541ec,0x0); + dwc_ddrphy_apb_wr(0x541ed,0x0); + dwc_ddrphy_apb_wr(0x541ee,0x0); + dwc_ddrphy_apb_wr(0x541ef,0x0); + dwc_ddrphy_apb_wr(0x541f0,0x0); + dwc_ddrphy_apb_wr(0x541f1,0x0); + dwc_ddrphy_apb_wr(0x541f2,0x0); + dwc_ddrphy_apb_wr(0x541f3,0x0); + dwc_ddrphy_apb_wr(0x541f4,0x0); + dwc_ddrphy_apb_wr(0x541f5,0x0); + dwc_ddrphy_apb_wr(0x541f6,0x0); + dwc_ddrphy_apb_wr(0x541f7,0x0); + dwc_ddrphy_apb_wr(0x541f8,0x0); + dwc_ddrphy_apb_wr(0x541f9,0x0); + dwc_ddrphy_apb_wr(0x541fa,0x0); + dwc_ddrphy_apb_wr(0x541fb,0x0); + dwc_ddrphy_apb_wr(0x541fc,0x100); + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099,0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + + wait_ddrphy_training_complete(); + + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x90000,0x10); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90001,0x400); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90002,0x10e); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90003,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x90004,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x90005,0x8); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x90029,0xb); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x9002a,0x480); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x9002b,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x9002c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9002d,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9002e,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x9002f,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */ + dwc_ddrphy_apb_wr(0x90030,0x478); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */ + dwc_ddrphy_apb_wr(0x90031,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */ + dwc_ddrphy_apb_wr(0x90032,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */ + dwc_ddrphy_apb_wr(0x90033,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */ + dwc_ddrphy_apb_wr(0x90034,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */ + dwc_ddrphy_apb_wr(0x90035,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */ + dwc_ddrphy_apb_wr(0x90036,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */ + dwc_ddrphy_apb_wr(0x90037,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */ + dwc_ddrphy_apb_wr(0x90038,0x44); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */ + dwc_ddrphy_apb_wr(0x90039,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */ + dwc_ddrphy_apb_wr(0x9003a,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */ + dwc_ddrphy_apb_wr(0x9003b,0x14f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */ + dwc_ddrphy_apb_wr(0x9003c,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */ + dwc_ddrphy_apb_wr(0x9003d,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */ + dwc_ddrphy_apb_wr(0x9003e,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */ + dwc_ddrphy_apb_wr(0x9003f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */ + dwc_ddrphy_apb_wr(0x90040,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */ + dwc_ddrphy_apb_wr(0x90041,0x4f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */ + dwc_ddrphy_apb_wr(0x90042,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */ + dwc_ddrphy_apb_wr(0x90043,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */ + dwc_ddrphy_apb_wr(0x90044,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */ + dwc_ddrphy_apb_wr(0x90045,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */ + dwc_ddrphy_apb_wr(0x90046,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */ + dwc_ddrphy_apb_wr(0x90047,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */ + dwc_ddrphy_apb_wr(0x90048,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */ + dwc_ddrphy_apb_wr(0x90049,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */ + dwc_ddrphy_apb_wr(0x9004a,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */ + dwc_ddrphy_apb_wr(0x9004b,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */ + dwc_ddrphy_apb_wr(0x9004c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */ + dwc_ddrphy_apb_wr(0x9004d,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */ + dwc_ddrphy_apb_wr(0x9004e,0x45a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */ + dwc_ddrphy_apb_wr(0x9004f,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */ + dwc_ddrphy_apb_wr(0x90050,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */ + dwc_ddrphy_apb_wr(0x90051,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */ + dwc_ddrphy_apb_wr(0x90052,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */ + dwc_ddrphy_apb_wr(0x90053,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */ + dwc_ddrphy_apb_wr(0x90054,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */ + dwc_ddrphy_apb_wr(0x90055,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */ + dwc_ddrphy_apb_wr(0x90056,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */ + dwc_ddrphy_apb_wr(0x90057,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */ + dwc_ddrphy_apb_wr(0x90058,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */ + dwc_ddrphy_apb_wr(0x90059,0x40c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */ + dwc_ddrphy_apb_wr(0x9005a,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */ + dwc_ddrphy_apb_wr(0x9005b,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */ + dwc_ddrphy_apb_wr(0x9005c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */ + dwc_ddrphy_apb_wr(0x9005d,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */ + dwc_ddrphy_apb_wr(0x9005e,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */ + dwc_ddrphy_apb_wr(0x9005f,0x4040); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */ + dwc_ddrphy_apb_wr(0x90060,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */ + dwc_ddrphy_apb_wr(0x90061,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */ + dwc_ddrphy_apb_wr(0x90062,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */ + dwc_ddrphy_apb_wr(0x90063,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */ + dwc_ddrphy_apb_wr(0x90064,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */ + dwc_ddrphy_apb_wr(0x90065,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */ + dwc_ddrphy_apb_wr(0x90066,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */ + dwc_ddrphy_apb_wr(0x90067,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */ + dwc_ddrphy_apb_wr(0x90068,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */ + dwc_ddrphy_apb_wr(0x90069,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */ + dwc_ddrphy_apb_wr(0x9006a,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */ + dwc_ddrphy_apb_wr(0x9006b,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */ + dwc_ddrphy_apb_wr(0x9006c,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */ + dwc_ddrphy_apb_wr(0x9006d,0x78); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */ + dwc_ddrphy_apb_wr(0x9006e,0x549); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */ + dwc_ddrphy_apb_wr(0x9006f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */ + dwc_ddrphy_apb_wr(0x90070,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */ + dwc_ddrphy_apb_wr(0x90071,0xd49); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */ + dwc_ddrphy_apb_wr(0x90072,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */ + dwc_ddrphy_apb_wr(0x90073,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */ + dwc_ddrphy_apb_wr(0x90074,0x94a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */ + dwc_ddrphy_apb_wr(0x90075,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */ + dwc_ddrphy_apb_wr(0x90076,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */ + dwc_ddrphy_apb_wr(0x90077,0x441); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */ + dwc_ddrphy_apb_wr(0x90078,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */ + dwc_ddrphy_apb_wr(0x90079,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */ + dwc_ddrphy_apb_wr(0x9007a,0x42); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */ + dwc_ddrphy_apb_wr(0x9007b,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */ + dwc_ddrphy_apb_wr(0x9007c,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */ + dwc_ddrphy_apb_wr(0x9007d,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */ + dwc_ddrphy_apb_wr(0x9007e,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */ + dwc_ddrphy_apb_wr(0x9007f,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */ + dwc_ddrphy_apb_wr(0x90080,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */ + dwc_ddrphy_apb_wr(0x90081,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */ + dwc_ddrphy_apb_wr(0x90082,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */ + dwc_ddrphy_apb_wr(0x90083,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */ + dwc_ddrphy_apb_wr(0x90084,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */ + dwc_ddrphy_apb_wr(0x90085,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */ + dwc_ddrphy_apb_wr(0x90086,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */ + dwc_ddrphy_apb_wr(0x90087,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */ + dwc_ddrphy_apb_wr(0x90088,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */ + dwc_ddrphy_apb_wr(0x90089,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */ + dwc_ddrphy_apb_wr(0x9008a,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */ + dwc_ddrphy_apb_wr(0x9008b,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */ + dwc_ddrphy_apb_wr(0x9008c,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */ + dwc_ddrphy_apb_wr(0x9008d,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */ + dwc_ddrphy_apb_wr(0x9008e,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */ + dwc_ddrphy_apb_wr(0x9008f,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */ + dwc_ddrphy_apb_wr(0x90090,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */ + dwc_ddrphy_apb_wr(0x90091,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */ + dwc_ddrphy_apb_wr(0x90092,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */ + dwc_ddrphy_apb_wr(0x90093,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */ + dwc_ddrphy_apb_wr(0x90094,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */ + dwc_ddrphy_apb_wr(0x90095,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */ + dwc_ddrphy_apb_wr(0x90096,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */ + dwc_ddrphy_apb_wr(0x90097,0x58); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */ + dwc_ddrphy_apb_wr(0x90098,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */ + dwc_ddrphy_apb_wr(0x90099,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */ + dwc_ddrphy_apb_wr(0x9009a,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */ + dwc_ddrphy_apb_wr(0x9009b,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */ + dwc_ddrphy_apb_wr(0x9009c,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */ + dwc_ddrphy_apb_wr(0x9009d,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */ + dwc_ddrphy_apb_wr(0x9009e,0x7); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */ + dwc_ddrphy_apb_wr(0x9009f,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */ + dwc_ddrphy_apb_wr(0x900a0,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */ + dwc_ddrphy_apb_wr(0x900a1,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */ + dwc_ddrphy_apb_wr(0x900a2,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */ + dwc_ddrphy_apb_wr(0x900a3,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */ + dwc_ddrphy_apb_wr(0x900a4,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */ + dwc_ddrphy_apb_wr(0x900a5,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */ + dwc_ddrphy_apb_wr(0x900a6,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */ + dwc_ddrphy_apb_wr(0x900a7,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */ + dwc_ddrphy_apb_wr(0x900a8,0x8138); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */ + dwc_ddrphy_apb_wr(0x900a9,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */ + dwc_ddrphy_apb_wr(0x900aa,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */ + dwc_ddrphy_apb_wr(0x900ab,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */ + dwc_ddrphy_apb_wr(0x900ac,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */ + dwc_ddrphy_apb_wr(0x900ad,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */ + dwc_ddrphy_apb_wr(0x900ae,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */ + dwc_ddrphy_apb_wr(0x900af,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */ + dwc_ddrphy_apb_wr(0x900b0,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */ + dwc_ddrphy_apb_wr(0x900b1,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */ + dwc_ddrphy_apb_wr(0x900b2,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */ + dwc_ddrphy_apb_wr(0x900b3,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */ + dwc_ddrphy_apb_wr(0x900b4,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */ + dwc_ddrphy_apb_wr(0x900b5,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */ + dwc_ddrphy_apb_wr(0x900b6,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */ + dwc_ddrphy_apb_wr(0x900b7,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */ + dwc_ddrphy_apb_wr(0x900b8,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */ + dwc_ddrphy_apb_wr(0x900b9,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */ + dwc_ddrphy_apb_wr(0x900ba,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */ + dwc_ddrphy_apb_wr(0x900bb,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */ + dwc_ddrphy_apb_wr(0x900bc,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */ + dwc_ddrphy_apb_wr(0x900bd,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */ + dwc_ddrphy_apb_wr(0x900be,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */ + dwc_ddrphy_apb_wr(0x900bf,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */ + dwc_ddrphy_apb_wr(0x900c0,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */ + dwc_ddrphy_apb_wr(0x900c1,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */ + dwc_ddrphy_apb_wr(0x900c2,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */ + dwc_ddrphy_apb_wr(0x900c3,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */ + dwc_ddrphy_apb_wr(0x900c4,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */ + dwc_ddrphy_apb_wr(0x900c5,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */ + dwc_ddrphy_apb_wr(0x900c6,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */ + dwc_ddrphy_apb_wr(0x900c7,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */ + dwc_ddrphy_apb_wr(0x900c8,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */ + dwc_ddrphy_apb_wr(0x900c9,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */ + dwc_ddrphy_apb_wr(0x900ca,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */ + dwc_ddrphy_apb_wr(0x900cb,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */ + dwc_ddrphy_apb_wr(0x900cc,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */ + dwc_ddrphy_apb_wr(0x900cd,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */ + dwc_ddrphy_apb_wr(0x90006,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90007,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90008,0x8); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90009,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9000a,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9000b,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0xd00e7,0x400); /* DWC_DDRPHYA_APBONLY0_SequencerOverride */ + dwc_ddrphy_apb_wr(0x90017,0x0); /* DWC_DDRPHYA_INITENG0_StartVector0b0 */ + dwc_ddrphy_apb_wr(0x90026,0x2c); /* DWC_DDRPHYA_INITENG0_StartVector0b15 */ + dwc_ddrphy_apb_wr(0x9000c,0x0); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */ + dwc_ddrphy_apb_wr(0x9000d,0x173); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */ + dwc_ddrphy_apb_wr(0x9000e,0x60); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */ + dwc_ddrphy_apb_wr(0x9000f,0x6110); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */ + dwc_ddrphy_apb_wr(0x90010,0x2152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */ + dwc_ddrphy_apb_wr(0x90011,0xdfbd); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */ + dwc_ddrphy_apb_wr(0x90012,0xffff); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */ + dwc_ddrphy_apb_wr(0x90013,0x6152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */ + dwc_ddrphy_apb_wr(0xc0080,0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +} diff --git a/board/freescale/imx8mq_arm2/ddr/helper.c b/board/freescale/imx8mq_arm2/ddr/helper.c new file mode 100644 index 00000000000..b9a9bd24635 --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/helper.c @@ -0,0 +1,104 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define IMEM_LEN 32768 +#define DMEM_LEN 16384 +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +/* We need PHY iMEM PHY is 32KB padded */ +void ddr_load_train_code(enum fw_type type) +{ + u32 tmp32, i; + u32 error = 0; + unsigned long pr_to32, pr_from32; + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; + unsigned long imem_start = (unsigned long)&_end + fw_offset; + unsigned long dmem_start = imem_start + IMEM_LEN; + + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for(i = 0x0; i < IMEM_LEN; ){ + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for(i = 0x0; i < DMEM_LEN;){ + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + printf("check ddr_imem code\n"); + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for(i = 0x0; i < IMEM_LEN;){ + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + + if(tmp32 != readl(pr_from32)){ + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + if(error){ + printf("check ddr_imem code fail=%d\n",error); + }else{ + printf("check ddr_imem code pass\n"); + } + + printf("check ddr_dmem code\n"); + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for(i = 0x0; i < DMEM_LEN;){ + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + if(tmp32 != readl(pr_from32)){ + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + + if(error){ + printf("check ddr_dmem code fail=%d",error); + }else{ + printf("check ddr_dmem code pass\n"); + } +} diff --git a/board/freescale/imx8mq_arm2/ddr/wait_ddrphy_training_complete.c b/board/freescale/imx8mq_arm2/ddr/wait_ddrphy_training_complete.c new file mode 100644 index 00000000000..0b42e58bd1d --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/wait_ddrphy_training_complete.c @@ -0,0 +1,96 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +static inline void poll_pmu_message_ready(void) +{ + unsigned int reg; + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + } while (reg & 0x1); +} + +static inline void ack_pmu_message_recieve(void) +{ + unsigned int reg; + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0); + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + } while (!(reg & 0x1)); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032); + + ack_pmu_message_recieve(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032); + + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034); + + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_recieve(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + ddr_printf("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + ddr_printf(" PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)){ + arg = get_stream_message(); + ddr_printf(" arg[%d] = 0x%08x\n", i, arg); + i++; + } + + ddr_printf("\n"); +} + +void wait_ddrphy_training_complete(void) +{ + unsigned int mail; + while (1) { + mail = get_mail(); + decode_major_message(mail); + if (mail == 0x08) { + decode_streaming_message(); + } else if (mail == 0x07) { + printf("Training PASS\n"); + break; + } else if (mail == 0xff) { + printf("Training FAILED\n"); + break; + } + } +} diff --git a/board/freescale/imx8mq_arm2/imx8mq_arm2.c b/board/freescale/imx8mq_arm2/imx8mq_arm2.c new file mode 100644 index 00000000000..a6e07b30104 --- /dev/null +++ b/board/freescale/imx8mq_arm2/imx8mq_arm2.c @@ -0,0 +1,339 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) + +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS) +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE) + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_QSPI +static iomux_v3_cfg_t const qspi_pads[] = { + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); + + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), + IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + init_nand_clk(); +} +#endif + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); /* SPL will call the board_early_init_f */ +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + /* TODO */ + return 0; +} +#endif + +int dram_init(void) +{ + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; + else + gd->ram_size = PHYS_SDRAM_SIZE; + +#if CONFIG_NR_DRAM_BANKS > 1 + gd->ram_size += PHYS_SDRAM_2_SIZE; +#endif + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + if (rom_pointer[1]) + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE -rom_pointer[1]; + else + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#endif + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +#ifndef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 +#define FEC_RST_PAD IMX_GPIO_NR(1, 9) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(1, 9), 1); +} +#endif + +static int setup_fec(void) +{ +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + /* + * GPR1 bit 13: + * 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also; + * 0:enet1 rmii clock comes from external phy or osc + */ + + setbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT); + return set_clk_enet(ENET_50MHZ); +#else + setup_iomux_fec(); + + return set_clk_enet(ENET_125MHZ); +#endif +} + + +int board_phy_config(struct phy_device *phydev) +{ +#ifndef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 + + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +#endif + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_USB_DWC3 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +static struct dwc3_device dwc3_device_data = { +#ifdef CONFIG_SPL_BUILD + .maximum_speed = USB_SPEED_HIGH, +#else + .maximum_speed = USB_SPEED_SUPER, +#endif + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .power_down_scale = 2, +}; + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); +} + +int board_usb_init(int index, enum usb_init_type init) +{ + dwc3_nxp_usb_phy_init(&dwc3_device_data); + return dwc3_uboot_init(&dwc3_device_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + dwc3_uboot_exit(index); + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 + env_set("board_name", "DDR3L-ARM2"); +#else + env_set("board_name", "DDR4-ARM2"); +#endif + env_set("board_rev", "iMX8MQ"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +phys_size_t get_effective_memsize(void) +{ + if (rom_pointer[1]) + return (PHYS_SDRAM_SIZE - rom_pointer[1]); + else + return PHYS_SDRAM_SIZE; +} diff --git a/board/freescale/imx8mq_arm2/spl.c b/board/freescale/imx8mq_arm2/spl.c new file mode 100644 index 00000000000..acf35be9a72 --- /dev/null +++ b/board/freescale/imx8mq_arm2/spl.c @@ -0,0 +1,257 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include +#include +#include +#include +#include "ddr/ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + /* ddr init */ + ddr_init(); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 + ret = !gpio_get_value(USDHC2_CD_GPIO); +#else + ret = gpio_get_value(USDHC2_CD_GPIO); +#endif + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return -ENODEV; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return -ENODEV; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + pmic_reg_read(p, PFUZE100_SW1ABVOL, ®); + if ((reg & 0x3f) != 0x1c) { + reg &= ~0x3f; + reg |= 0x1c; + pmic_reg_write(p, PFUZE100_SW1ABVOL, reg); + } + + pmic_reg_read(p, PFUZE100_SW1CVOL, ®); + if ((reg & 0x3f) != 0x1c) { + reg &= ~0x3f; + reg |= 0x1c; + pmic_reg_write(p, PFUZE100_SW1CVOL, reg); + } + + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} +#endif + +void spl_board_init(void) +{ +#ifndef CONFIG_SPL_USB_SDP_SUPPORT + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } +#endif + + init_usb_clk(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(0); /* Init UART0 clock */ + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* Adjust pmic voltage VDD_DRAM to 1.0V for DRAM RUN >= 2400MHZ */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8mq_evk/Kconfig b/board/freescale/imx8mq_evk/Kconfig new file mode 100644 index 00000000000..3f3bddf324d --- /dev/null +++ b/board/freescale/imx8mq_evk/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8MQ_EVK + +config SYS_BOARD + default "imx8mq_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mq_evk" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8mq_evk/Makefile b/board/freescale/imx8mq_evk/Makefile new file mode 100644 index 00000000000..9ca20e09b42 --- /dev/null +++ b/board/freescale/imx8mq_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2016 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mq_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o +endif diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c new file mode 100644 index 00000000000..1d2b912b3cb --- /dev/null +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -0,0 +1,394 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" +#include "../common/pfuze.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_QSPI +static iomux_v3_cfg_t const qspi_pads[] = { + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); + + set_clk_qspi(); + + return 0; +} +#endif + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + /* TODO */ + return 0; +} +#endif + +int dram_init(void) +{ + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; + else + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +#define FEC_RST_PAD IMX_GPIO_NR(1, 9) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(1, 9), 1); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); + return set_clk_enet(ENET_125MHZ); +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_USB_DWC3 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +static struct dwc3_device dwc3_device_data = { +#ifdef CONFIG_SPL_BUILD + .maximum_speed = USB_SPEED_HIGH, +#else + .maximum_speed = USB_SPEED_SUPER, +#endif + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .power_down_scale = 2, +}; + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); +} +#endif + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port; +struct tcpc_port_config port_config = { + .i2c_bus = 0, + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 20000, + .max_snk_ma = 3000, + .max_snk_mw = 15000, + .op_snk_mv = 9000, +}; + +#define USB_TYPEC_SEL IMX_GPIO_NR(3, 15) + +static iomux_v3_cfg_t ss_mux_gpio[] = { + IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void ss_mux_select(enum typec_cc_polarity pol) +{ + if (pol == TYPEC_POLARITY_CC1) + gpio_direction_output(USB_TYPEC_SEL, 1); + else + gpio_direction_output(USB_TYPEC_SEL, 0); +} + +static int setup_typec(void) +{ + int ret; + + imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); + gpio_request(USB_TYPEC_SEL, "typec_sel"); + + ret = tcpc_init(&port, port_config, &ss_mux_select); + if (ret) { + printf("%s: tcpc init failed, err=%d\n", + __func__, ret); + } + + return ret; +} +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + imx8m_usb_power(index, true); + + if (index == 0 && init == USB_INIT_DEVICE) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_ufp_mode(&port); +#endif + dwc3_nxp_usb_phy_init(&dwc3_device_data); + return dwc3_uboot_init(&dwc3_device_data); + } else if (index == 0 && init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_dfp_mode(&port); +#endif + return ret; + } + + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_uboot_exit(index); + } else if (index == 0 && init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_disable_src_vbus(&port); +#endif + } + + imx8m_usb_power(index, false); + + return ret; +} +#endif + +int board_init(void) +{ + board_qspi_init(); + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) + init_usb_clk(); +#endif + +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "EVK"); + env_set("board_rev", "iMX8MQ"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +#if defined(CONFIG_VIDEO_IMXDCSS) + +struct display_info_t const displays[] = {{ + .bus = 0, /* Unused */ + .addr = 0, /* Unused */ + .pixfmt = GDF_32BIT_X888RGB, + .detect = NULL, + .enable = NULL, +#ifndef CONFIG_VIDEO_IMXDCSS_1080P + .mode = { + .name = "HDMI", /* 720P60 */ + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 13468, /* 74250 kHz */ + .left_margin = 110, + .right_margin = 220, + .upper_margin = 5, + .lower_margin = 20, + .hsync_len = 40, + .vsync_len = 5, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED + } +#else + .mode = { + .name = "HDMI", /* 1080P60 */ + .refresh = 60, + .xres = 1920, + .yres = 1080, + .pixclock = 6734, /* 148500 kHz */ + .left_margin = 148, + .right_margin = 88, + .upper_margin = 36, + .lower_margin = 4, + .hsync_len = 44, + .vsync_len = 5, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED + } +#endif +} }; +size_t display_count = ARRAY_SIZE(displays); + +#endif /* CONFIG_VIDEO_IMXDCSS */ + +/* return hard code board id for imx8m_ref */ +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) +int get_imx8m_baseboard_id(void) +{ + return IMX8M_REF_3G; +} +#endif diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c new file mode 100644 index 00000000000..c73be15ab5d --- /dev/null +++ b/board/freescale/imx8mq_evk/lpddr4_timing.c @@ -0,0 +1,2084 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include + +#define LPDDR4_HDT_CTL_2D 0xC8 /* stage completion */ +#define LPDDR4_HDT_CTL_3200_1D 0xC8 /* stage completion */ +#define LPDDR4_HDT_CTL_400_1D 0xC8 /* stage completion */ +#define LPDDR4_HDT_CTL_100_1D 0xC8 /* stage completion */ + +// 400/100 training seq +#define LPDDR4_TRAIN_SEQ_100 0x121f +#define LPDDR4_TRAIN_SEQ_400 0x121f + +//2D share & weight +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 +#define LPDDR4_CATRAIN_3200_1d 0 +#define LPDDR4_CATRAIN_400 0 +#define LPDDR4_CATRAIN_100 0 +#define LPDDR4_CATRAIN_3200_2d 0 + +#define WR_POST_EXT_3200 /* recommened to define */ + +/* for LPDDR4 Rtt */ +#define LPDDR4_RTT40 6 +#define LPDDR4_RTT48 5 +#define LPDDR4_RTT60 4 +#define LPDDR4_RTT80 3 +#define LPDDR4_RTT120 2 +#define LPDDR4_RTT240 1 +#define LPDDR4_RTT_DIS 0 + +/* for LPDDR4 Ron */ +#define LPDDR4_RON34 7 +#define LPDDR4_RON40 6 +#define LPDDR4_RON48 5 +#define LPDDR4_RON60 4 +#define LPDDR4_RON80 3 + +#define LPDDR4_PHY_ADDR_RON60 0x1 +#define LPDDR4_PHY_ADDR_RON40 0x3 +#define LPDDR4_PHY_ADDR_RON30 0x7 +#define LPDDR4_PHY_ADDR_RON24 0xf +#define LPDDR4_PHY_ADDR_RON20 0x1f + +/* for read channel */ +#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */ +#define LPDDR4_PHY_RTT 30 +#define LPDDR4_PHY_VREF_VALUE 17 + +/* for write channel */ +#define LPDDR4_PHY_RON 30 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 +#define LPDDR4_RTT_DQ LPDDR4_RTT40 /* MR11[2:0] */ +#define LPDDR4_RTT_CA LPDDR4_RTT40 /* MR11[6:4] */ +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 /* MR11[6:4] */ +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 /* LPDDR4_RTT_DIS */ +#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd)) /* MR12 */ +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd)) /* MR14 */ +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd)) /* MR14 */ +#define LPDDR4_MR22_RANK0 ((0 << 5) | (1 << 4) | (0 << 3) | (LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */ +#define LPDDR4_MR22_RANK1 ((0 << 5) | (1 << 4) | (0 << 3) | (LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */ +#define LPDDR4_MR3_PU_CAL 1 /* MR3[0] */ + +struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, + + /* Frequency 1: 400mbps */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, + { DDRC_FREQ1_INIT3(0), 0x00840000 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + + /* Frequency 2: 100mbps */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + { DDRC_FREQ2_INIT6(0), 0x0066004a }, + { DDRC_FREQ2_INIT7(0), 0x0006004a }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, + { 0x20111, 0x03 }, + { 0x20112, 0x04 }, + { 0x20113, 0x05 }, + { 0x20114, 0x00 }, + { 0x20115, 0x01 }, + + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + +#ifdef WR_POST_EXT_3200 + { 0x20024, 0xeb }, +#else + { 0x20024, 0xab }, +#endif + { 0x2003a, 0x0 }, + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + + { 0x200c7, 0x80 }, + { 0x1200c7, 0x80 }, + { 0x2200c7, 0x80 }, + { 0x200ca, 0x106 }, + { 0x1200ca, 0x106 }, + { 0x2200ca, 0x106 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */ + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },//MR3/MR2 +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },//MR3/MR2 +#endif + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8)/*0x4600*/ },//MR11/MR4 + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },//self:0x284d//MR13/MR12 + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ },//MR16/MR14 + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ }, + { 0x54038, 0xd400 },//MR1 +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },//MR3/MR2 +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },//MR3/MR2 +#endif + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8)/*0x4600*/ },//MR11/MR4 + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },//self:0x284d//MR13/MR12 + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ },//MR16/MR14 + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },//{ 0x5403d,0x500 }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_400 }, + { 0x54009, LPDDR4_HDT_CTL_400_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_400 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },//MR4/MR3 + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |(LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ)/*0x4d46*/ },//MR12/MR11 + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ },//self:0x4d28//MR14/MR13 + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },//MR4/MR3 + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ)/*0x4d46*/ },//MR12/MR11 + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ },//self:0x4d28//MR14/MR13 + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_100 }, + { 0x54009, LPDDR4_HDT_CTL_100_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_100 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1 ) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + + { 0x54032, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c new file mode 100644 index 00000000000..027fa235843 --- /dev/null +++ b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c @@ -0,0 +1,1965 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include + +#define LPDDR4_HDT_CTL_2D 0xC8 /* stage completion */ +#define LPDDR4_HDT_CTL_3200_1D 0xC8 /* stage completion */ +#define LPDDR4_HDT_CTL_400_1D 0xC8 /* stage completion */ +#define LPDDR4_HDT_CTL_100_1D 0xC8 /* stage completion */ + +/* 2D share & weight */ +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 +#define LPDDR4_CATRAIN_3200_1d 0 +#define LPDDR4_CATRAIN_400 0 +#define LPDDR4_CATRAIN_100 0 +#define LPDDR4_CATRAIN_3200_2d 0 + +#define WR_POST_EXT_3200 /* recommened to define */ + +/* lpddr4 phy training config */ +/* for LPDDR4 Rtt */ +#define LPDDR4_RTT40 6 +#define LPDDR4_RTT48 5 +#define LPDDR4_RTT60 4 +#define LPDDR4_RTT80 3 +#define LPDDR4_RTT120 2 +#define LPDDR4_RTT240 1 +#define LPDDR4_RTT_DIS 0 + +/* for LPDDR4 Ron */ +#define LPDDR4_RON34 7 +#define LPDDR4_RON40 6 +#define LPDDR4_RON48 5 +#define LPDDR4_RON60 4 +#define LPDDR4_RON80 3 + +#define LPDDR4_PHY_ADDR_RON60 0x1 +#define LPDDR4_PHY_ADDR_RON40 0x3 +#define LPDDR4_PHY_ADDR_RON30 0x7 +#define LPDDR4_PHY_ADDR_RON24 0xf +#define LPDDR4_PHY_ADDR_RON20 0x1f + +/* for read channel */ +#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */ +#define LPDDR4_PHY_RTT 30 +#define LPDDR4_PHY_VREF_VALUE 17 + +/* for write channel */ +#define LPDDR4_PHY_RON 30 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 +#define LPDDR4_RTT_DQ LPDDR4_RTT40 /* MR11[2:0] */ +#define LPDDR4_RTT_CA LPDDR4_RTT40 /* MR11[6:4] */ +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 /* MR11[6:4] */ +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 /* LPDDR4_RTT_DIS//MR11[6:4] */ +#define LPDDR4_VREF_VALUE_CA ((1<<6)|(0xd)) /*((0<<6)|(0xe)) MR12 */ +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1<<6)|(0xd)) /* MR14 */ +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1<<6)|(0xd)) /* MR14 */ +#define LPDDR4_MR22_RANK0 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */ +#define LPDDR4_MR22_RANK1 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */ +#define LPDDR4_MR3_PU_CAL 1 /* MR3[0] */ + +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + /* dis_dq=1, indicates no reads or writes are issued to SDRAM */ + { DDRC_DBG1(0), 0x00000001 }, + /* selfref_en=1, SDRAM enter self-refresh state */ + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 /* recommened to define */ + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + + /* need be refined by ddrphy trained value */ + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + /* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */ + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + /* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */ + { DDRC_ADDRMAP5(0), 0x07070707 }, + /* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */ + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* 667mts frequency setting */ + { DDRC_FREQ1_DERATEEN(0), 0x0000000 }, + { DDRC_FREQ1_DERATEINT(0), 0x0800000 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x014001E }, + { DDRC_FREQ1_INIT3(0), 0x0140009 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 }, + { DDRC_FREQ1_DRAMTMG1(0), 0x003040A }, + { DDRC_FREQ1_DRAMTMG2(0), 0x305080C }, + { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 }, + { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 }, + { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 }, + { DDRC_FREQ1_DFITMG0(0), 0x3858202 }, + { DDRC_FREQ1_DFITMG1(0), 0x0000404 }, + { DDRC_FREQ1_DFITMG2(0), 0x0000502 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, + { DDRC_FREQ1_DERATEEN(0), 0x00000202 }, + { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 }, + { DDRC_FREQ1_RFSHTMG(0), 0x00610090 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, /* MapCAB0toDFI */ + { 0x20111, 0x03 }, /* MapCAB1toDFI */ + { 0x20112, 0x04 }, /* MapCAB2toDFI */ + { 0x20113, 0x05 }, /* MapCAB3toDFI */ + { 0x20114, 0x00 }, /* MapCAB4toDFI */ + { 0x20115, 0x01 }, /* MapCAB5toDFI */ + + /* Initialize PHY Configuration */ + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xe3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0xa3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0xa3 }, + { 0x2003a, 0x2 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0xa7 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x600 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5655 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON<<8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x29c }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x914 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x914 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x1400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, 0x600 }, + { 0x54038, 0x1400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54024, 0x5 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0xd }, + { 0x900a5, 0x7c0 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x4 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x70 }, + { 0x900db, 0x788 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x1ff8 }, + { 0x900de, 0x85a8 }, + { 0x900df, 0x1e8 }, + { 0x900e0, 0x50 }, + { 0x900e1, 0x798 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x60 }, + { 0x900e4, 0x7a0 }, + { 0x900e5, 0x16a }, + { 0x900e6, 0x8 }, + { 0x900e7, 0x8310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0x8 }, + { 0x900ea, 0xa310 }, + { 0x900eb, 0x168 }, + { 0x900ec, 0xa }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x6e }, + { 0x900f0, 0x0 }, + { 0x900f1, 0x68 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x408 }, + { 0x900f4, 0x169 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0x8310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x0 }, + { 0x900f9, 0xa310 }, + { 0x900fa, 0x168 }, + { 0x900fb, 0x1ff8 }, + { 0x900fc, 0x85a8 }, + { 0x900fd, 0x1e8 }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x798 }, + { 0x90100, 0x16a }, + { 0x90101, 0x78 }, + { 0x90102, 0x7a0 }, + { 0x90103, 0x16a }, + { 0x90104, 0x68 }, + { 0x90105, 0x790 }, + { 0x90106, 0x16a }, + { 0x90107, 0x8 }, + { 0x90108, 0x8b10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0x8 }, + { 0x9010b, 0xab10 }, + { 0x9010c, 0x168 }, + { 0x9010d, 0xa }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x58 }, + { 0x90111, 0x0 }, + { 0x90112, 0x68 }, + { 0x90113, 0x0 }, + { 0x90114, 0x408 }, + { 0x90115, 0x169 }, + { 0x90116, 0x0 }, + { 0x90117, 0x8b10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0xab10 }, + { 0x9011b, 0x168 }, + { 0x9011c, 0x0 }, + { 0x9011d, 0x1d8 }, + { 0x9011e, 0x169 }, + { 0x9011f, 0x80 }, + { 0x90120, 0x790 }, + { 0x90121, 0x16a }, + { 0x90122, 0x18 }, + { 0x90123, 0x7aa }, + { 0x90124, 0x6a }, + { 0x90125, 0xa }, + { 0x90126, 0x0 }, + { 0x90127, 0x1e9 }, + { 0x90128, 0x8 }, + { 0x90129, 0x8080 }, + { 0x9012a, 0x108 }, + { 0x9012b, 0xf }, + { 0x9012c, 0x408 }, + { 0x9012d, 0x169 }, + { 0x9012e, 0xc }, + { 0x9012f, 0x0 }, + { 0x90130, 0x68 }, + { 0x90131, 0x9 }, + { 0x90132, 0x0 }, + { 0x90133, 0x1a9 }, + { 0x90134, 0x0 }, + { 0x90135, 0x408 }, + { 0x90136, 0x169 }, + { 0x90137, 0x0 }, + { 0x90138, 0x8080 }, + { 0x90139, 0x108 }, + { 0x9013a, 0x8 }, + { 0x9013b, 0x7aa }, + { 0x9013c, 0x6a }, + { 0x9013d, 0x0 }, + { 0x9013e, 0x8568 }, + { 0x9013f, 0x108 }, + { 0x90140, 0xb7 }, + { 0x90141, 0x790 }, + { 0x90142, 0x16a }, + { 0x90143, 0x1f }, + { 0x90144, 0x0 }, + { 0x90145, 0x68 }, + { 0x90146, 0x8 }, + { 0x90147, 0x8558 }, + { 0x90148, 0x168 }, + { 0x90149, 0xf }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0xc }, + { 0x9014d, 0x0 }, + { 0x9014e, 0x68 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x408 }, + { 0x90151, 0x169 }, + { 0x90152, 0x0 }, + { 0x90153, 0x8558 }, + { 0x90154, 0x168 }, + { 0x90155, 0x8 }, + { 0x90156, 0x3c8 }, + { 0x90157, 0x1a9 }, + { 0x90158, 0x3 }, + { 0x90159, 0x370 }, + { 0x9015a, 0x129 }, + { 0x9015b, 0x20 }, + { 0x9015c, 0x2aa }, + { 0x9015d, 0x9 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x400 }, + { 0x90160, 0x10e }, + { 0x90161, 0x8 }, + { 0x90162, 0xe8 }, + { 0x90163, 0x109 }, + { 0x90164, 0x0 }, + { 0x90165, 0x8140 }, + { 0x90166, 0x10c }, + { 0x90167, 0x10 }, + { 0x90168, 0x8138 }, + { 0x90169, 0x10c }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x7c8 }, + { 0x9016c, 0x101 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x0 }, + { 0x9016f, 0x8 }, + { 0x90170, 0x8 }, + { 0x90171, 0x448 }, + { 0x90172, 0x109 }, + { 0x90173, 0xf }, + { 0x90174, 0x7c0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0xe8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x47 }, + { 0x9017a, 0x630 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x618 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0xe0 }, + { 0x90181, 0x109 }, + { 0x90182, 0x0 }, + { 0x90183, 0x7c8 }, + { 0x90184, 0x109 }, + { 0x90185, 0x8 }, + { 0x90186, 0x8140 }, + { 0x90187, 0x10c }, + { 0x90188, 0x0 }, + { 0x90189, 0x1 }, + { 0x9018a, 0x8 }, + { 0x9018b, 0x8 }, + { 0x9018c, 0x4 }, + { 0x9018d, 0x8 }, + { 0x9018e, 0x8 }, + { 0x9018f, 0x7c8 }, + { 0x90190, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x6c }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, + { 0x12000c, 0x29 }, + { 0x12000d, 0x1a1 }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing_b0 = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + /* + * this table must be initialized if DDRPHY bypass mode is + * not used: all fsp drate > 666MTS. + */ + .fsp_table = { 3200, 667, }, +}; diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c new file mode 100644 index 00000000000..841329f6a52 --- /dev/null +++ b/board/freescale/imx8mq_evk/spl.c @@ -0,0 +1,255 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern struct dram_timing_info dram_timing_b0; + +void spl_dram_init(void) +{ + /* ddr init */ + if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1) + ddr_init(&dram_timing); + else + ddr_init(&dram_timing_b0); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return -ENODEV; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return -ENODEV; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + if ((reg & 0x3f) != 0x18) { + reg &= ~0x3f; + reg |= 0x18; + pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + } + + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + + /* set SW3A standby mode to off */ + pmic_reg_read(p, PFUZE100_SW3AMODE, ®); + reg &= ~0xf; + reg |= APS_OFF; + pmic_reg_write(p, PFUZE100_SW3AMODE, reg); + + return 0; +} +#endif + +void spl_board_init(void) +{ +#ifndef CONFIG_SPL_USB_SDP_SUPPORT + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } +#endif + + init_usb_clk(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(0); /* Init UART0 clock */ + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8mq_phanbell/Kconfig b/board/freescale/imx8mq_phanbell/Kconfig new file mode 100644 index 00000000000..442d982e5f5 --- /dev/null +++ b/board/freescale/imx8mq_phanbell/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8MQ_PHANBELL + +config SYS_BOARD + default "imx8mq_phanbell" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mq_phanbell" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8mq_phanbell/Makefile b/board/freescale/imx8mq_phanbell/Makefile new file mode 100644 index 00000000000..fc4b9f8ef0a --- /dev/null +++ b/board/freescale/imx8mq_phanbell/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2016 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8m_phanbell.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o +endif diff --git a/board/freescale/imx8mq_phanbell/ddr/ddr.h b/board/freescale/imx8mq_phanbell/ddr/ddr.h new file mode 100644 index 00000000000..9acb29c7a5f --- /dev/null +++ b/board/freescale/imx8mq_phanbell/ddr/ddr.h @@ -0,0 +1,34 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +void ddr_init(void); +void ddr_load_train_code(enum fw_type type); +void lpddr4_800M_cfg_phy(void); + +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline uint32_t reg32_read(unsigned long addr) +{ + return readl(addr); +} + +static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} diff --git a/board/freescale/imx8mq_phanbell/ddr/ddr_init.c b/board/freescale/imx8mq_phanbell/ddr/ddr_init.c new file mode 100755 index 00000000000..46d3557cb55 --- /dev/null +++ b/board/freescale/imx8mq_phanbell/ddr/ddr_init.c @@ -0,0 +1,474 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "ddr.h" + +#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG +#define ddr_printf(args...) printf(args) +#else +#define ddr_printf(args...) +#endif + +#include "wait_ddrphy_training_complete.c" +#ifndef SRC_DDRC_RCR_ADDR +#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000 +#endif +#ifndef DDR_CSD1_BASE_ADDR +#define DDR_CSD1_BASE_ADDR 0x40000000 +#endif +#define SILICON_TRAIN + +volatile unsigned int tmp, tmp_t, i; +void lpddr4_800MHz_cfg_umctl2(void) +{ + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000304, 0x00000001); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000030, 0x00000001); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000000, 0x83080020); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000064, 0x006180e0); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d0, 0xc003061B); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d4, 0x009D0000); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d8, 0x0000fe05); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000dc, 0x00d4002d); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e0, 0x00310008); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e4, 0x00040009); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e8, 0x0046004d); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000ec, 0x0005004d); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000f4, 0x00000979); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000100, 0x1a203522); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000104, 0x00060630); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000108, 0x070e1214); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000010c, 0x00b0c006); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000110, 0x0f04080f); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000114, 0x0d0d0c0c); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000118, 0x01010007); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000011c, 0x0000060a); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000120, 0x01010101); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000124, 0x40000008); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000128, 0x00050d01); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000012c, 0x01010008); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000130, 0x00020000); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000134, 0x18100002); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000138, 0x00000dc2); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000013c, 0x80000000); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000144, 0x00a00050); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000180, 0x53200018); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000184, 0x02800070); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000188, 0x00000000); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000190, 0x0397820a); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00002190, 0x0397820a); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00003190, 0x0397820a); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000194, 0x00020103); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a0, 0xe0400018); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a4, 0x00df00e4); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a8, 0x00000000); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b0, 0x00000011); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b4, 0x0000170a); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c0, 0x00000001); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c4, 0x00000000); + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ + dwc_ddrphy_apb_wr(DDRC_ADDRMAP0(0), 0x00000015); + dwc_ddrphy_apb_wr(DDRC_ADDRMAP4(0), 0x00001F1F); + /* bank interleave */ + dwc_ddrphy_apb_wr(DDRC_ADDRMAP1(0), 0x00080808); + dwc_ddrphy_apb_wr(DDRC_ADDRMAP5(0), 0x07070707); + dwc_ddrphy_apb_wr(DDRC_ADDRMAP6(0), 0x08080707); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000240, 0x020f0c54); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000244, 0x00000000); + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000490, 0x00000001); + + /* performance setting */ + dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908); + dwc_ddrphy_apb_wr(DDRC_ODTMAP(0), 0x00000000); + dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505); + dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c); + dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b); + dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x00000009); + dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574); + dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016); + dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000); + dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000); + dwc_ddrphy_apb_wr(DDRC_SWCTL(0), 0x00000001); + dwc_ddrphy_apb_wr(DDRC_POISONCFG(0), 0x00000011); + dwc_ddrphy_apb_wr(DDRC_PCCFG(0), 0x00000111); + dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3); + dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff); + dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001); + dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x01110d00); + dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x00620790); + dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00100001); + dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000041f); + dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202); + dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5); + dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040); + dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090); +} + +void lpddr4_100MHz_cfg_umctl2(void) +{ + reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c); + reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030410); + reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0305090c); + reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x00505006); + reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x05040305); + reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504); + reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a060004); + reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000090e); + reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000032); + reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000); + reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0036001b); + reg32_write(DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1); + reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0020d040); + reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03818200); + reg32_write(DDRC_FREQ1_ODTCFG(0), 0x0a1a096c); + reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000000); + reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x00038014); + reg32_write(DDRC_FREQ1_INIT3(0), 0x00840000); + reg32_write(DDRC_FREQ1_INIT6(0), 0x0000004d); + reg32_write(DDRC_FREQ1_INIT7(0), 0x0000004d); + reg32_write(DDRC_FREQ1_INIT4(0), 0x00310000); +} + +void lpddr4_25MHz_cfg_umctl2(void) +{ + reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c); + reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030410); + reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0305090c); + reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x00505006); + reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x05040305); + reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504); + reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a060004); + reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x0000090e); + reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000032); + reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000); + reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x0036001b); + reg32_write(DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1); + reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0020d040); + reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03818200); + reg32_write(DDRC_FREQ2_ODTCFG(0), 0x0a1a096c); + reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000000); + reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0003800c); + reg32_write(DDRC_FREQ2_INIT3(0), 0x00840000); + reg32_write(DDRC_FREQ2_INIT6(0), 0x0000004d); + reg32_write(DDRC_FREQ2_INIT7(0), 0x0000004d); + reg32_write(DDRC_FREQ2_INIT4(0), 0x00310000); +} + +int get_imx8m_baseboard_id(void); +void ddr_cfg_phy(void); +void ddr_init(void) +{ + int board_id = 0; + + board_id = get_imx8m_baseboard_id(); + if ((board_id == ENTERPRISE_MICRON_1G) || + (board_id == ENTERPRISE_HYNIX_1G)) { + /** Initialize DDR clock and DDRC registers **/ + reg32_write(0x3038a088,0x7070000); + reg32_write(0x3038a084,0x4030000); + reg32_write(0x303a00ec,0xffff); + tmp=reg32_read(0x303a00f8); + tmp |= 0x20; + reg32_write(0x303a00f8,tmp); + reg32_write(0x30391000,0x8f000000); + reg32_write(0x30391004,0x8f000000); + reg32_write(0x30360068,0xece580); + tmp=reg32_read(0x30360060); + tmp &= ~0x80; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp |= 0x200; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x20; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x10; + reg32_write(0x30360060,tmp); + do{ + tmp=reg32_read(0x30360060); + if(tmp&0x80000000) break; + }while(1); + reg32_write(0x30391000,0x8f000006); + reg32_write(0x3d400304,0x1); + reg32_write(0x3d400030,0x1); + reg32_write(0x3d400000,0xa1080020); + reg32_write(0x3d400028,0x0); + reg32_write(0x3d400020,0x203); + reg32_write(0x3d400024,0x186a000); + reg32_write(0x3d400064,0x610090); + reg32_write(0x3d4000d0,0xc003061c); + reg32_write(0x3d4000d4,0x9e0000); + reg32_write(0x3d4000dc,0xd4002d); + reg32_write(0x3d4000e0,0x310008); + reg32_write(0x3d4000e8,0x66004a); + reg32_write(0x3d4000ec,0x16004a); + reg32_write(0x3d400100,0x1a201b22); + reg32_write(0x3d400104,0x60633); + reg32_write(0x3d40010c,0xc0c000); + reg32_write(0x3d400110,0xf04080f); + reg32_write(0x3d400114,0x2040c0c); + reg32_write(0x3d400118,0x1010007); + reg32_write(0x3d40011c,0x401); + reg32_write(0x3d400130,0x20600); + reg32_write(0x3d400134,0xc100002); + reg32_write(0x3d400138,0x96); + reg32_write(0x3d400144,0xa00050); + reg32_write(0x3d400180,0x3200018); + reg32_write(0x3d400184,0x28061a8); + reg32_write(0x3d400188,0x0); + reg32_write(0x3d400190,0x497820a); + reg32_write(0x3d400194,0x80303); + reg32_write(0x3d4001a0,0xe0400018); + reg32_write(0x3d4001a4,0xdf00e4); + reg32_write(0x3d4001a8,0x80000000); + reg32_write(0x3d4001b0,0x11); + reg32_write(0x3d4001b4,0x170a); + reg32_write(0x3d4001c0,0x1); + reg32_write(0x3d4001c4,0x1); + reg32_write(0x3d4000f4,0x639); + reg32_write(0x3d400108,0x70e1214); + reg32_write(0x3d400200,0x1f); + reg32_write(0x3d40020c,0x0); + reg32_write(0x3d400210,0x1f1f); + reg32_write(0x3d400204,0x80808); + reg32_write(0x3d400214,0x7070707); + reg32_write(0x3d400218,0xf070707); + reg32_write(0x3d402020,0x1); + reg32_write(0x3d402024,0x518b00); + reg32_write(0x3d402050,0x20d040); + reg32_write(0x3d402064,0x14001f); + reg32_write(0x3d4020dc,0x940009); + reg32_write(0x3d4020e0,0x310000); + reg32_write(0x3d4020e8,0x66004a); + reg32_write(0x3d4020ec,0x16004a); + reg32_write(0x3d402100,0xb070508); + reg32_write(0x3d402104,0x3040b); + reg32_write(0x3d402108,0x305090c); + reg32_write(0x3d40210c,0x505000); + reg32_write(0x3d402110,0x4040204); + reg32_write(0x3d402114,0x2030303); + reg32_write(0x3d402118,0x1010004); + reg32_write(0x3d40211c,0x301); + reg32_write(0x3d402130,0x20300); + reg32_write(0x3d402134,0xa100002); + reg32_write(0x3d402138,0x20); + reg32_write(0x3d402144,0x220011); + reg32_write(0x3d402180,0xa70006); + reg32_write(0x3d402190,0x3858202); + reg32_write(0x3d402194,0x80303); + reg32_write(0x3d4021b4,0x502); + reg32_write(0x3d400244,0x0); + reg32_write(0x3d400250,0x29001505); + reg32_write(0x3d400254,0x2c); + reg32_write(0x3d40025c,0x5900575b); + reg32_write(0x3d400264,0x9); + reg32_write(0x3d40026c,0x2005574); + reg32_write(0x3d400300,0x16); + reg32_write(0x3d400304,0x0); + reg32_write(0x3d40030c,0x0); + reg32_write(0x3d400320,0x1); + reg32_write(0x3d40036c,0x11); + reg32_write(0x3d400400,0x111); + reg32_write(0x3d400404,0x10f3); + reg32_write(0x3d400408,0x72ff); + reg32_write(0x3d400490,0x1); + reg32_write(0x3d400494,0x1110d00); + reg32_write(0x3d400498,0x620790); + reg32_write(0x3d40049c,0x100001); + reg32_write(0x3d4004a0,0x41f); + reg32_write(0x30391000,0x8f000004); + reg32_write(0x30391000,0x8f000000); + reg32_write(0x3d400030,0xa8); + do{ + tmp=reg32_read(0x3d400004); + if(tmp&0x223) break; + }while(1); + reg32_write(0x3d400320,0x0); + reg32_write(0x3d000000,0x1); + reg32_write(0x3d4001b0,0x10); + reg32_write(0x3c040280,0x0); + reg32_write(0x3c040284,0x1); + reg32_write(0x3c040288,0x2); + reg32_write(0x3c04028c,0x3); + reg32_write(0x3c040290,0x4); + reg32_write(0x3c040294,0x5); + reg32_write(0x3c040298,0x6); + reg32_write(0x3c04029c,0x7); + reg32_write(0x3c044280,0x0); + reg32_write(0x3c044284,0x1); + reg32_write(0x3c044288,0x2); + reg32_write(0x3c04428c,0x3); + reg32_write(0x3c044290,0x4); + reg32_write(0x3c044294,0x5); + reg32_write(0x3c044298,0x6); + reg32_write(0x3c04429c,0x7); + reg32_write(0x3c048280,0x0); + reg32_write(0x3c048284,0x1); + reg32_write(0x3c048288,0x2); + reg32_write(0x3c04828c,0x3); + reg32_write(0x3c048290,0x4); + reg32_write(0x3c048294,0x5); + reg32_write(0x3c048298,0x6); + reg32_write(0x3c04829c,0x7); + reg32_write(0x3c04c280,0x0); + reg32_write(0x3c04c284,0x1); + reg32_write(0x3c04c288,0x2); + reg32_write(0x3c04c28c,0x3); + reg32_write(0x3c04c290,0x4); + reg32_write(0x3c04c294,0x5); + reg32_write(0x3c04c298,0x6); + reg32_write(0x3c04c29c,0x7); + + /* Configure DDR PHY's registers */ + ddr_cfg_phy(); + + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + reg32_write(DDRC_SWCTL(0), 0x0000); + /* + * ------------------- 9 ------------------- + * Set DFIMISC.dfi_init_start to 1 + * ----------------------------------------- + */ + reg32_write(DDRC_DFIMISC(0), 0x00000030); + reg32_write(DDRC_SWCTL(0), 0x0001); + + /* wait DFISTAT.dfi_init_complete to 1 */ + tmp_t = 0; + while(tmp_t==0){ + tmp = reg32_read(DDRC_DFISTAT(0)); + tmp_t = tmp & 0x01; + tmp = reg32_read(DDRC_MRSTAT(0)); + } + + reg32_write(DDRC_SWCTL(0), 0x0000); + + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000010); + reg32_write(DDRC_DFIMISC(0), 0x00000011); + reg32_write(DDRC_PWRCTL(0), 0x00000088); + + tmp = reg32_read(DDRC_CRCPARSTAT(0)); + /* + * set SWCTL.sw_done to enable quasi-dynamic register + * programming outside reset. + */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* wait SWSTAT.sw_done_ack to 1 */ + while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0) + ; + + /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ + while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1) + ; + + reg32_write(DDRC_PWRCTL(0), 0x00000088); + /* reg32_write(DDRC_PWRCTL(0), 0x018a); */ + tmp = reg32_read(DDRC_CRCPARSTAT(0)); + + /* enable port 0 */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + /* enable DDR auto-refresh mode */ + tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; + reg32_write(DDRC_RFSHCTL3(0), tmp); + } else { + /* Default use 3G DDR */ + /* change the clock source of dram_apb_clk_root */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16)); + + /* disable the clock gating */ + reg32_write(0x303A00EC,0x0000ffff); + reg32setbit(0x303A00F8,5); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + + dram_pll_init(SSCG_PLL_OUT_800M); + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /* Configure uMCTL2's registers */ + lpddr4_800MHz_cfg_umctl2(); + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + reg32_write(DDRC_DBG1(0), 0x00000000); + tmp = reg32_read(DDRC_PWRCTL(0)); + reg32_write(DDRC_PWRCTL(0), 0x000000a8); + /* reg32_write(DDRC_PWRCTL(0), 0x0000018a); */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + reg32_write(DDRC_DDR_SS_GPR0, 0x01); + reg32_write(DDRC_DFIMISC(0), 0x00000010); + + /* Configure LPDDR4 PHY's registers */ + lpddr4_800M_cfg_phy(); + + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + reg32_write(DDRC_SWCTL(0), 0x0000); + /* + * ------------------- 9 ------------------- + * Set DFIMISC.dfi_init_start to 1 + * ----------------------------------------- + */ + reg32_write(DDRC_DFIMISC(0), 0x00000030); + reg32_write(DDRC_SWCTL(0), 0x0001); + + /* wait DFISTAT.dfi_init_complete to 1 */ + tmp_t = 0; + while(tmp_t==0){ + tmp = reg32_read(DDRC_DFISTAT(0)); + tmp_t = tmp & 0x01; + tmp = reg32_read(DDRC_MRSTAT(0)); + } + + reg32_write(DDRC_SWCTL(0), 0x0000); + + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000010); + reg32_write(DDRC_DFIMISC(0), 0x00000011); + reg32_write(DDRC_PWRCTL(0), 0x00000088); + + tmp = reg32_read(DDRC_CRCPARSTAT(0)); + /* + * set SWCTL.sw_done to enable quasi-dynamic register + * programming outside reset. + */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* wait SWSTAT.sw_done_ack to 1 */ + while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0) + ; + + /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ + while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1) + ; + + reg32_write(DDRC_PWRCTL(0), 0x00000088); + /* reg32_write(DDRC_PWRCTL(0), 0x018a); */ + tmp = reg32_read(DDRC_CRCPARSTAT(0)); + + /* enable port 0 */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + tmp = reg32_read(DDRC_CRCPARSTAT(0)); + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + + reg32_write(DDRC_SWCTL(0), 0x0); + lpddr4_100MHz_cfg_umctl2(); + lpddr4_25MHz_cfg_umctl2(); + reg32_write(DDRC_SWCTL(0), 0x1); + + /* wait SWSTAT.sw_done_ack to 1 */ + while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0) + ; + + reg32_write(DDRC_SWCTL(0), 0x0); + } +} diff --git a/board/freescale/imx8mq_phanbell/ddr/ddrphy_train.c b/board/freescale/imx8mq_phanbell/ddr/ddrphy_train.c new file mode 100755 index 00000000000..3e020709812 --- /dev/null +++ b/board/freescale/imx8mq_phanbell/ddr/ddrphy_train.c @@ -0,0 +1,2075 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "ddr.h" + +extern void wait_ddrphy_training_complete(void); +void ddr_cfg_phy(void) { + unsigned int tmp, tmp_t; + + //Init DDRPHY register... + reg32_write(0x3c080440,0x2); + reg32_write(0x3c080444,0x3); + reg32_write(0x3c080448,0x4); + reg32_write(0x3c08044c,0x5); + reg32_write(0x3c080450,0x0); + reg32_write(0x3c080454,0x1); + reg32_write(0x3c04017c,0x1ff); + reg32_write(0x3c04057c,0x1ff); + reg32_write(0x3c04417c,0x1ff); + reg32_write(0x3c04457c,0x1ff); + reg32_write(0x3c04817c,0x1ff); + reg32_write(0x3c04857c,0x1ff); + reg32_write(0x3c04c17c,0x1ff); + reg32_write(0x3c04c57c,0x1ff); + reg32_write(0x3c44017c,0x1ff); + reg32_write(0x3c44057c,0x1ff); + reg32_write(0x3c44417c,0x1ff); + reg32_write(0x3c44457c,0x1ff); + reg32_write(0x3c44817c,0x1ff); + reg32_write(0x3c44857c,0x1ff); + reg32_write(0x3c44c17c,0x1ff); + reg32_write(0x3c44c57c,0x1ff); + reg32_write(0x3c000154,0x1ff); + reg32_write(0x3c004154,0x1ff); + reg32_write(0x3c008154,0x1ff); + reg32_write(0x3c00c154,0x1ff); + reg32_write(0x3c010154,0x1ff); + reg32_write(0x3c014154,0x1ff); + reg32_write(0x3c018154,0x1ff); + reg32_write(0x3c01c154,0x1ff); + reg32_write(0x3c020154,0x1ff); + reg32_write(0x3c024154,0x1ff); + reg32_write(0x3c080314,0x19); + reg32_write(0x3c480314,0x7); + reg32_write(0x3c0800b8,0x2); + reg32_write(0x3c4800b8,0x1); + reg32_write(0x3c240810,0x0); + reg32_write(0x3c640810,0x0); + reg32_write(0x3c080090,0xab); + reg32_write(0x3c0800e8,0x0); + reg32_write(0x3c480090,0xab); + reg32_write(0x3c0800e8,0x0); + reg32_write(0x3c080158,0x3); + reg32_write(0x3c480158,0xa); + reg32_write(0x3c040134,0xe00); + reg32_write(0x3c040534,0xe00); + reg32_write(0x3c044134,0xe00); + reg32_write(0x3c044534,0xe00); + reg32_write(0x3c048134,0xe00); + reg32_write(0x3c048534,0xe00); + reg32_write(0x3c04c134,0xe00); + reg32_write(0x3c04c534,0xe00); + reg32_write(0x3c440134,0xe00); + reg32_write(0x3c440534,0xe00); + reg32_write(0x3c444134,0xe00); + reg32_write(0x3c444534,0xe00); + reg32_write(0x3c448134,0xe00); + reg32_write(0x3c448534,0xe00); + reg32_write(0x3c44c134,0xe00); + reg32_write(0x3c44c534,0xe00); + reg32_write(0x3c040124,0xfbe); + reg32_write(0x3c040524,0xfbe); + reg32_write(0x3c044124,0xfbe); + reg32_write(0x3c044524,0xfbe); + reg32_write(0x3c048124,0xfbe); + reg32_write(0x3c048524,0xfbe); + reg32_write(0x3c04c124,0xfbe); + reg32_write(0x3c04c524,0xfbe); + reg32_write(0x3c440124,0xfbe); + reg32_write(0x3c440524,0xfbe); + reg32_write(0x3c444124,0xfbe); + reg32_write(0x3c444524,0xfbe); + reg32_write(0x3c448124,0xfbe); + reg32_write(0x3c448524,0xfbe); + reg32_write(0x3c44c124,0xfbe); + reg32_write(0x3c44c524,0xfbe); + reg32_write(0x3c00010c,0x63); + reg32_write(0x3c00410c,0x63); + reg32_write(0x3c00810c,0x63); + reg32_write(0x3c00c10c,0x63); + reg32_write(0x3c01010c,0x63); + reg32_write(0x3c01410c,0x63); + reg32_write(0x3c01810c,0x63); + reg32_write(0x3c01c10c,0x63); + reg32_write(0x3c02010c,0x63); + reg32_write(0x3c02410c,0x63); + reg32_write(0x3c080060,0x3); + reg32_write(0x3c0801d4,0x4); + reg32_write(0x3c080140,0x0); + reg32_write(0x3c080020,0x320); + reg32_write(0x3c480020,0xa7); + reg32_write(0x3c080220,0x9); + reg32_write(0x3c0802c8,0xdc); + reg32_write(0x3c04010c,0x5a1); + reg32_write(0x3c04050c,0x5a1); + reg32_write(0x3c04410c,0x5a1); + reg32_write(0x3c04450c,0x5a1); + reg32_write(0x3c04810c,0x5a1); + reg32_write(0x3c04850c,0x5a1); + reg32_write(0x3c04c10c,0x5a1); + reg32_write(0x3c04c50c,0x5a1); + reg32_write(0x3c4802c8,0xdc); + reg32_write(0x3c44010c,0x5a1); + reg32_write(0x3c44050c,0x5a1); + reg32_write(0x3c44410c,0x5a1); + reg32_write(0x3c44450c,0x5a1); + reg32_write(0x3c44810c,0x5a1); + reg32_write(0x3c44850c,0x5a1); + reg32_write(0x3c44c10c,0x5a1); + reg32_write(0x3c44c50c,0x5a1); + reg32_write(0x3c0803e8,0x1); + reg32_write(0x3c4803e8,0x1); + reg32_write(0x3c080064,0x1); + reg32_write(0x3c480064,0x1); + reg32_write(0x3c0803c0,0x0); + reg32_write(0x3c0803c4,0x0); + reg32_write(0x3c0803c8,0x4444); + reg32_write(0x3c0803cc,0x8888); + reg32_write(0x3c0803d0,0x5555); + reg32_write(0x3c0803d4,0x0); + reg32_write(0x3c0803d8,0x0); + reg32_write(0x3c0803dc,0xf000); + reg32_write(0x3c080094,0x0); + reg32_write(0x3c0800b4,0x0); + reg32_write(0x3c4800b4,0x0); + reg32_write(0x3c080180,0x2); + + //enable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + //load the 1D training image + ddr_load_train_code(FW_1D_IMAGE); + + //configure DDRPHY-FW DMEM structure @clock0... + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + + //set the PHY input clock to the desired frequency for pstate 0 + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x131f); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x110); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); + + //disable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + //Reset MPU and run + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); + wait_ddrphy_training_complete(); + + //configure DDRPHY-FW DMEM structure @clock1... + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + + //set the PHY input clock to the desired frequency for pstate 1 + reg32_write(0x3038a088,0x7070000); + reg32_write(0x3038a084,0x4030000); + reg32_write(0x303a00ec,0xffff); + tmp=reg32_read(0x303a00f8); + tmp |= 0x20; + reg32_write(0x303a00f8,tmp); + reg32_write(0x30360068,0xf5a406); + tmp=reg32_read(0x30360060); + tmp &= ~0x80; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp |= 0x200; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x20; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x10; + reg32_write(0x30360060,tmp); + do{ + tmp=reg32_read(0x30360060); + if(tmp&0x80000000) break; + }while(1); + reg32_write(0x30389808,0x1000000); + + //enable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + + reg32_write(0x3c150008,0x1); + reg32_write(0x3c15000c,0x29c); + reg32_write(0x3c150020,0x121f); + reg32_write(0x3c150064,0x994); + reg32_write(0x3c150068,0x31); + reg32_write(0x3c15006c,0x4d46); + reg32_write(0x3c150070,0x4d08); + reg32_write(0x3c150074,0x0); + reg32_write(0x3c150078,0x15); + reg32_write(0x3c15007c,0x994); + reg32_write(0x3c150080,0x31); + reg32_write(0x3c150084,0x4d46); + reg32_write(0x3c150088,0x4d08); + reg32_write(0x3c15008c,0x0); + reg32_write(0x3c150090,0x15); + reg32_write(0x3c1500c8,0x9400); + reg32_write(0x3c1500cc,0x3109); + reg32_write(0x3c1500d0,0x4600); + reg32_write(0x3c1500d4,0x84d); + reg32_write(0x3c1500d8,0x4d); + reg32_write(0x3c1500dc,0x1500); + reg32_write(0x3c1500e0,0x9400); + reg32_write(0x3c1500e4,0x3109); + reg32_write(0x3c1500e8,0x4600); + reg32_write(0x3c1500ec,0x84d); + reg32_write(0x3c1500f0,0x4d); + reg32_write(0x3c1500f4,0x1500); + reg32_write(0x3c1500f8,0x0); + + //disable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + //Reset MPU and run + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); + wait_ddrphy_training_complete(); + + //set the PHY input clock to the desired frequency for pstate 0 + reg32_write(0x3038a088,0x7070000); + reg32_write(0x3038a084,0x4030000); + reg32_write(0x303a00ec,0xffff); + tmp=reg32_read(0x303a00f8); + tmp |= 0x20; + reg32_write(0x303a00f8,tmp); + reg32_write(0x30360068,0xece580); + tmp=reg32_read(0x30360060); + tmp &= ~0x80; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp |= 0x200; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x20; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x10; + reg32_write(0x30360060,tmp); + do{ + tmp=reg32_read(0x30360060); + if(tmp&0x80000000) break; + }while(1); + reg32_write(0x30389808,0x1000000); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + + + //enable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + //load the 2D training image + ddr_load_train_code(FW_2D_IMAGE); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x61); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x100); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x1f7f); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x110); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); + + //disable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + //Reset MPU and run + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); + wait_ddrphy_training_complete(); + + //Halt MPU + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + //enable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + + //Load firmware PIE image + reg32_write(0x3c240000,0x10); + reg32_write(0x3c240004,0x400); + reg32_write(0x3c240008,0x10e); + reg32_write(0x3c24000c,0x0); + reg32_write(0x3c240010,0x0); + reg32_write(0x3c240014,0x8); + reg32_write(0x3c2400a4,0xb); + reg32_write(0x3c2400a8,0x480); + reg32_write(0x3c2400ac,0x109); + reg32_write(0x3c2400b0,0x8); + reg32_write(0x3c2400b4,0x448); + reg32_write(0x3c2400b8,0x139); + reg32_write(0x3c2400bc,0x8); + reg32_write(0x3c2400c0,0x478); + reg32_write(0x3c2400c4,0x109); + reg32_write(0x3c2400c8,0x0); + reg32_write(0x3c2400cc,0xe8); + reg32_write(0x3c2400d0,0x109); + reg32_write(0x3c2400d4,0x2); + reg32_write(0x3c2400d8,0x10); + reg32_write(0x3c2400dc,0x139); + reg32_write(0x3c2400e0,0xf); + reg32_write(0x3c2400e4,0x7c0); + reg32_write(0x3c2400e8,0x139); + reg32_write(0x3c2400ec,0x44); + reg32_write(0x3c2400f0,0x630); + reg32_write(0x3c2400f4,0x159); + reg32_write(0x3c2400f8,0x14f); + reg32_write(0x3c2400fc,0x630); + reg32_write(0x3c240100,0x159); + reg32_write(0x3c240104,0x47); + reg32_write(0x3c240108,0x630); + reg32_write(0x3c24010c,0x149); + reg32_write(0x3c240110,0x4f); + reg32_write(0x3c240114,0x630); + reg32_write(0x3c240118,0x179); + reg32_write(0x3c24011c,0x8); + reg32_write(0x3c240120,0xe0); + reg32_write(0x3c240124,0x109); + reg32_write(0x3c240128,0x0); + reg32_write(0x3c24012c,0x7c8); + reg32_write(0x3c240130,0x109); + reg32_write(0x3c240134,0x0); + reg32_write(0x3c240138,0x1); + reg32_write(0x3c24013c,0x8); + reg32_write(0x3c240140,0x0); + reg32_write(0x3c240144,0x45a); + reg32_write(0x3c240148,0x9); + reg32_write(0x3c24014c,0x0); + reg32_write(0x3c240150,0x448); + reg32_write(0x3c240154,0x109); + reg32_write(0x3c240158,0x40); + reg32_write(0x3c24015c,0x630); + reg32_write(0x3c240160,0x179); + reg32_write(0x3c240164,0x1); + reg32_write(0x3c240168,0x618); + reg32_write(0x3c24016c,0x109); + reg32_write(0x3c240170,0x40c0); + reg32_write(0x3c240174,0x630); + reg32_write(0x3c240178,0x149); + reg32_write(0x3c24017c,0x8); + reg32_write(0x3c240180,0x4); + reg32_write(0x3c240184,0x48); + reg32_write(0x3c240188,0x4040); + reg32_write(0x3c24018c,0x630); + reg32_write(0x3c240190,0x149); + reg32_write(0x3c240194,0x0); + reg32_write(0x3c240198,0x4); + reg32_write(0x3c24019c,0x48); + reg32_write(0x3c2401a0,0x40); + reg32_write(0x3c2401a4,0x630); + reg32_write(0x3c2401a8,0x149); + reg32_write(0x3c2401ac,0x10); + reg32_write(0x3c2401b0,0x4); + reg32_write(0x3c2401b4,0x18); + reg32_write(0x3c2401b8,0x0); + reg32_write(0x3c2401bc,0x4); + reg32_write(0x3c2401c0,0x78); + reg32_write(0x3c2401c4,0x549); + reg32_write(0x3c2401c8,0x630); + reg32_write(0x3c2401cc,0x159); + reg32_write(0x3c2401d0,0xd49); + reg32_write(0x3c2401d4,0x630); + reg32_write(0x3c2401d8,0x159); + reg32_write(0x3c2401dc,0x94a); + reg32_write(0x3c2401e0,0x630); + reg32_write(0x3c2401e4,0x159); + reg32_write(0x3c2401e8,0x441); + reg32_write(0x3c2401ec,0x630); + reg32_write(0x3c2401f0,0x149); + reg32_write(0x3c2401f4,0x42); + reg32_write(0x3c2401f8,0x630); + reg32_write(0x3c2401fc,0x149); + reg32_write(0x3c240200,0x1); + reg32_write(0x3c240204,0x630); + reg32_write(0x3c240208,0x149); + reg32_write(0x3c24020c,0x0); + reg32_write(0x3c240210,0xe0); + reg32_write(0x3c240214,0x109); + reg32_write(0x3c240218,0xa); + reg32_write(0x3c24021c,0x10); + reg32_write(0x3c240220,0x109); + reg32_write(0x3c240224,0x9); + reg32_write(0x3c240228,0x3c0); + reg32_write(0x3c24022c,0x149); + reg32_write(0x3c240230,0x9); + reg32_write(0x3c240234,0x3c0); + reg32_write(0x3c240238,0x159); + reg32_write(0x3c24023c,0x18); + reg32_write(0x3c240240,0x10); + reg32_write(0x3c240244,0x109); + reg32_write(0x3c240248,0x0); + reg32_write(0x3c24024c,0x3c0); + reg32_write(0x3c240250,0x109); + reg32_write(0x3c240254,0x18); + reg32_write(0x3c240258,0x4); + reg32_write(0x3c24025c,0x48); + reg32_write(0x3c240260,0x18); + reg32_write(0x3c240264,0x4); + reg32_write(0x3c240268,0x58); + reg32_write(0x3c24026c,0xa); + reg32_write(0x3c240270,0x10); + reg32_write(0x3c240274,0x109); + reg32_write(0x3c240278,0x2); + reg32_write(0x3c24027c,0x10); + reg32_write(0x3c240280,0x109); + reg32_write(0x3c240284,0x5); + reg32_write(0x3c240288,0x7c0); + reg32_write(0x3c24028c,0x109); + reg32_write(0x3c240290,0x10); + reg32_write(0x3c240294,0x10); + reg32_write(0x3c240298,0x109); + reg32_write(0x3c100000,0x811); + reg32_write(0x3c100080,0x880); + reg32_write(0x3c100100,0x0); + reg32_write(0x3c100180,0x0); + reg32_write(0x3c100004,0x4008); + reg32_write(0x3c100084,0x83); + reg32_write(0x3c100104,0x4f); + reg32_write(0x3c100184,0x0); + reg32_write(0x3c100008,0x4040); + reg32_write(0x3c100088,0x83); + reg32_write(0x3c100108,0x51); + reg32_write(0x3c100188,0x0); + reg32_write(0x3c10000c,0x811); + reg32_write(0x3c10008c,0x880); + reg32_write(0x3c10010c,0x0); + reg32_write(0x3c10018c,0x0); + reg32_write(0x3c100010,0x720); + reg32_write(0x3c100090,0xf); + reg32_write(0x3c100110,0x1740); + reg32_write(0x3c100190,0x0); + reg32_write(0x3c100014,0x16); + reg32_write(0x3c100094,0x83); + reg32_write(0x3c100114,0x4b); + reg32_write(0x3c100194,0x0); + reg32_write(0x3c100018,0x716); + reg32_write(0x3c100098,0xf); + reg32_write(0x3c100118,0x2001); + reg32_write(0x3c100198,0x0); + reg32_write(0x3c10001c,0x716); + reg32_write(0x3c10009c,0xf); + reg32_write(0x3c10011c,0x2800); + reg32_write(0x3c10019c,0x0); + reg32_write(0x3c100020,0x716); + reg32_write(0x3c1000a0,0xf); + reg32_write(0x3c100120,0xf00); + reg32_write(0x3c1001a0,0x0); + reg32_write(0x3c100024,0x720); + reg32_write(0x3c1000a4,0xf); + reg32_write(0x3c100124,0x1400); + reg32_write(0x3c1001a4,0x0); + reg32_write(0x3c100028,0xe08); + reg32_write(0x3c1000a8,0xc15); + reg32_write(0x3c100128,0x0); + reg32_write(0x3c1001a8,0x0); + reg32_write(0x3c10002c,0x623); + reg32_write(0x3c1000ac,0x15); + reg32_write(0x3c10012c,0x0); + reg32_write(0x3c1001ac,0x0); + reg32_write(0x3c100030,0x4028); + reg32_write(0x3c1000b0,0x80); + reg32_write(0x3c100130,0x0); + reg32_write(0x3c1001b0,0x0); + reg32_write(0x3c100034,0xe08); + reg32_write(0x3c1000b4,0xc1a); + reg32_write(0x3c100134,0x0); + reg32_write(0x3c1001b4,0x0); + reg32_write(0x3c100038,0x623); + reg32_write(0x3c1000b8,0x1a); + reg32_write(0x3c100138,0x0); + reg32_write(0x3c1001b8,0x0); + reg32_write(0x3c10003c,0x4040); + reg32_write(0x3c1000bc,0x80); + reg32_write(0x3c10013c,0x0); + reg32_write(0x3c1001bc,0x0); + reg32_write(0x3c100040,0x2604); + reg32_write(0x3c1000c0,0x15); + reg32_write(0x3c100140,0x0); + reg32_write(0x3c1001c0,0x0); + reg32_write(0x3c100044,0x708); + reg32_write(0x3c1000c4,0x5); + reg32_write(0x3c100144,0x0); + reg32_write(0x3c1001c4,0x2002); + reg32_write(0x3c100048,0x8); + reg32_write(0x3c1000c8,0x80); + reg32_write(0x3c100148,0x0); + reg32_write(0x3c1001c8,0x0); + reg32_write(0x3c10004c,0x2604); + reg32_write(0x3c1000cc,0x1a); + reg32_write(0x3c10014c,0x0); + reg32_write(0x3c1001cc,0x0); + reg32_write(0x3c100050,0x708); + reg32_write(0x3c1000d0,0xa); + reg32_write(0x3c100150,0x0); + reg32_write(0x3c1001d0,0x2002); + reg32_write(0x3c100054,0x4040); + reg32_write(0x3c1000d4,0x80); + reg32_write(0x3c100154,0x0); + reg32_write(0x3c1001d4,0x0); + reg32_write(0x3c100058,0x60a); + reg32_write(0x3c1000d8,0x15); + reg32_write(0x3c100158,0x1200); + reg32_write(0x3c1001d8,0x0); + reg32_write(0x3c10005c,0x61a); + reg32_write(0x3c1000dc,0x15); + reg32_write(0x3c10015c,0x1300); + reg32_write(0x3c1001dc,0x0); + reg32_write(0x3c100060,0x60a); + reg32_write(0x3c1000e0,0x1a); + reg32_write(0x3c100160,0x1200); + reg32_write(0x3c1001e0,0x0); + reg32_write(0x3c100064,0x642); + reg32_write(0x3c1000e4,0x1a); + reg32_write(0x3c100164,0x1300); + reg32_write(0x3c1001e4,0x0); + reg32_write(0x3c100068,0x4808); + reg32_write(0x3c1000e8,0x880); + reg32_write(0x3c100168,0x0); + reg32_write(0x3c1001e8,0x0); + reg32_write(0x3c24029c,0x0); + reg32_write(0x3c2402a0,0x790); + reg32_write(0x3c2402a4,0x11a); + reg32_write(0x3c2402a8,0x8); + reg32_write(0x3c2402ac,0x7aa); + reg32_write(0x3c2402b0,0x2a); + reg32_write(0x3c2402b4,0x10); + reg32_write(0x3c2402b8,0x7b2); + reg32_write(0x3c2402bc,0x2a); + reg32_write(0x3c2402c0,0x0); + reg32_write(0x3c2402c4,0x7c8); + reg32_write(0x3c2402c8,0x109); + reg32_write(0x3c2402cc,0x10); + reg32_write(0x3c2402d0,0x2a8); + reg32_write(0x3c2402d4,0x129); + reg32_write(0x3c2402d8,0x8); + reg32_write(0x3c2402dc,0x370); + reg32_write(0x3c2402e0,0x129); + reg32_write(0x3c2402e4,0xa); + reg32_write(0x3c2402e8,0x3c8); + reg32_write(0x3c2402ec,0x1a9); + reg32_write(0x3c2402f0,0xc); + reg32_write(0x3c2402f4,0x408); + reg32_write(0x3c2402f8,0x199); + reg32_write(0x3c2402fc,0x14); + reg32_write(0x3c240300,0x790); + reg32_write(0x3c240304,0x11a); + reg32_write(0x3c240308,0x8); + reg32_write(0x3c24030c,0x4); + reg32_write(0x3c240310,0x18); + reg32_write(0x3c240314,0xe); + reg32_write(0x3c240318,0x408); + reg32_write(0x3c24031c,0x199); + reg32_write(0x3c240320,0x8); + reg32_write(0x3c240324,0x8568); + reg32_write(0x3c240328,0x108); + reg32_write(0x3c24032c,0x18); + reg32_write(0x3c240330,0x790); + reg32_write(0x3c240334,0x16a); + reg32_write(0x3c240338,0x8); + reg32_write(0x3c24033c,0x1d8); + reg32_write(0x3c240340,0x169); + reg32_write(0x3c240344,0x10); + reg32_write(0x3c240348,0x8558); + reg32_write(0x3c24034c,0x168); + reg32_write(0x3c240350,0x70); + reg32_write(0x3c240354,0x788); + reg32_write(0x3c240358,0x16a); + reg32_write(0x3c24035c,0x1ff8); + reg32_write(0x3c240360,0x85a8); + reg32_write(0x3c240364,0x1e8); + reg32_write(0x3c240368,0x50); + reg32_write(0x3c24036c,0x798); + reg32_write(0x3c240370,0x16a); + reg32_write(0x3c240374,0x60); + reg32_write(0x3c240378,0x7a0); + reg32_write(0x3c24037c,0x16a); + reg32_write(0x3c240380,0x8); + reg32_write(0x3c240384,0x8310); + reg32_write(0x3c240388,0x168); + reg32_write(0x3c24038c,0x8); + reg32_write(0x3c240390,0xa310); + reg32_write(0x3c240394,0x168); + reg32_write(0x3c240398,0xa); + reg32_write(0x3c24039c,0x408); + reg32_write(0x3c2403a0,0x169); + reg32_write(0x3c2403a4,0x6e); + reg32_write(0x3c2403a8,0x0); + reg32_write(0x3c2403ac,0x68); + reg32_write(0x3c2403b0,0x0); + reg32_write(0x3c2403b4,0x408); + reg32_write(0x3c2403b8,0x169); + reg32_write(0x3c2403bc,0x0); + reg32_write(0x3c2403c0,0x8310); + reg32_write(0x3c2403c4,0x168); + reg32_write(0x3c2403c8,0x0); + reg32_write(0x3c2403cc,0xa310); + reg32_write(0x3c2403d0,0x168); + reg32_write(0x3c2403d4,0x1ff8); + reg32_write(0x3c2403d8,0x85a8); + reg32_write(0x3c2403dc,0x1e8); + reg32_write(0x3c2403e0,0x68); + reg32_write(0x3c2403e4,0x798); + reg32_write(0x3c2403e8,0x16a); + reg32_write(0x3c2403ec,0x78); + reg32_write(0x3c2403f0,0x7a0); + reg32_write(0x3c2403f4,0x16a); + reg32_write(0x3c2403f8,0x68); + reg32_write(0x3c2403fc,0x790); + reg32_write(0x3c240400,0x16a); + reg32_write(0x3c240404,0x8); + reg32_write(0x3c240408,0x8b10); + reg32_write(0x3c24040c,0x168); + reg32_write(0x3c240410,0x8); + reg32_write(0x3c240414,0xab10); + reg32_write(0x3c240418,0x168); + reg32_write(0x3c24041c,0xa); + reg32_write(0x3c240420,0x408); + reg32_write(0x3c240424,0x169); + reg32_write(0x3c240428,0x58); + reg32_write(0x3c24042c,0x0); + reg32_write(0x3c240430,0x68); + reg32_write(0x3c240434,0x0); + reg32_write(0x3c240438,0x408); + reg32_write(0x3c24043c,0x169); + reg32_write(0x3c240440,0x0); + reg32_write(0x3c240444,0x8b10); + reg32_write(0x3c240448,0x168); + reg32_write(0x3c24044c,0x0); + reg32_write(0x3c240450,0xab10); + reg32_write(0x3c240454,0x168); + reg32_write(0x3c240458,0x0); + reg32_write(0x3c24045c,0x1d8); + reg32_write(0x3c240460,0x169); + reg32_write(0x3c240464,0x80); + reg32_write(0x3c240468,0x790); + reg32_write(0x3c24046c,0x16a); + reg32_write(0x3c240470,0x18); + reg32_write(0x3c240474,0x7aa); + reg32_write(0x3c240478,0x6a); + reg32_write(0x3c24047c,0xa); + reg32_write(0x3c240480,0x0); + reg32_write(0x3c240484,0x1e9); + reg32_write(0x3c240488,0x8); + reg32_write(0x3c24048c,0x8080); + reg32_write(0x3c240490,0x108); + reg32_write(0x3c240494,0xf); + reg32_write(0x3c240498,0x408); + reg32_write(0x3c24049c,0x169); + reg32_write(0x3c2404a0,0xc); + reg32_write(0x3c2404a4,0x0); + reg32_write(0x3c2404a8,0x68); + reg32_write(0x3c2404ac,0x9); + reg32_write(0x3c2404b0,0x0); + reg32_write(0x3c2404b4,0x1a9); + reg32_write(0x3c2404b8,0x0); + reg32_write(0x3c2404bc,0x408); + reg32_write(0x3c2404c0,0x169); + reg32_write(0x3c2404c4,0x0); + reg32_write(0x3c2404c8,0x8080); + reg32_write(0x3c2404cc,0x108); + reg32_write(0x3c2404d0,0x8); + reg32_write(0x3c2404d4,0x7aa); + reg32_write(0x3c2404d8,0x6a); + reg32_write(0x3c2404dc,0x0); + reg32_write(0x3c2404e0,0x8568); + reg32_write(0x3c2404e4,0x108); + reg32_write(0x3c2404e8,0xb7); + reg32_write(0x3c2404ec,0x790); + reg32_write(0x3c2404f0,0x16a); + reg32_write(0x3c2404f4,0x1f); + reg32_write(0x3c2404f8,0x0); + reg32_write(0x3c2404fc,0x68); + reg32_write(0x3c240500,0x8); + reg32_write(0x3c240504,0x8558); + reg32_write(0x3c240508,0x168); + reg32_write(0x3c24050c,0xf); + reg32_write(0x3c240510,0x408); + reg32_write(0x3c240514,0x169); + reg32_write(0x3c240518,0xc); + reg32_write(0x3c24051c,0x0); + reg32_write(0x3c240520,0x68); + reg32_write(0x3c240524,0x0); + reg32_write(0x3c240528,0x408); + reg32_write(0x3c24052c,0x169); + reg32_write(0x3c240530,0x0); + reg32_write(0x3c240534,0x8558); + reg32_write(0x3c240538,0x168); + reg32_write(0x3c24053c,0x8); + reg32_write(0x3c240540,0x3c8); + reg32_write(0x3c240544,0x1a9); + reg32_write(0x3c240548,0x3); + reg32_write(0x3c24054c,0x370); + reg32_write(0x3c240550,0x129); + reg32_write(0x3c240554,0x20); + reg32_write(0x3c240558,0x2aa); + reg32_write(0x3c24055c,0x9); + reg32_write(0x3c240560,0x0); + reg32_write(0x3c240564,0x400); + reg32_write(0x3c240568,0x10e); + reg32_write(0x3c24056c,0x8); + reg32_write(0x3c240570,0xe8); + reg32_write(0x3c240574,0x109); + reg32_write(0x3c240578,0x0); + reg32_write(0x3c24057c,0x8140); + reg32_write(0x3c240580,0x10c); + reg32_write(0x3c240584,0x10); + reg32_write(0x3c240588,0x8138); + reg32_write(0x3c24058c,0x10c); + reg32_write(0x3c240590,0x8); + reg32_write(0x3c240594,0x7c8); + reg32_write(0x3c240598,0x101); + reg32_write(0x3c24059c,0x8); + reg32_write(0x3c2405a0,0x0); + reg32_write(0x3c2405a4,0x8); + reg32_write(0x3c2405a8,0x8); + reg32_write(0x3c2405ac,0x448); + reg32_write(0x3c2405b0,0x109); + reg32_write(0x3c2405b4,0xf); + reg32_write(0x3c2405b8,0x7c0); + reg32_write(0x3c2405bc,0x109); + reg32_write(0x3c2405c0,0x0); + reg32_write(0x3c2405c4,0xe8); + reg32_write(0x3c2405c8,0x109); + reg32_write(0x3c2405cc,0x47); + reg32_write(0x3c2405d0,0x630); + reg32_write(0x3c2405d4,0x109); + reg32_write(0x3c2405d8,0x8); + reg32_write(0x3c2405dc,0x618); + reg32_write(0x3c2405e0,0x109); + reg32_write(0x3c2405e4,0x8); + reg32_write(0x3c2405e8,0xe0); + reg32_write(0x3c2405ec,0x109); + reg32_write(0x3c2405f0,0x0); + reg32_write(0x3c2405f4,0x7c8); + reg32_write(0x3c2405f8,0x109); + reg32_write(0x3c2405fc,0x8); + reg32_write(0x3c240600,0x8140); + reg32_write(0x3c240604,0x10c); + reg32_write(0x3c240608,0x0); + reg32_write(0x3c24060c,0x1); + reg32_write(0x3c240610,0x8); + reg32_write(0x3c240614,0x8); + reg32_write(0x3c240618,0x4); + reg32_write(0x3c24061c,0x8); + reg32_write(0x3c240620,0x8); + reg32_write(0x3c240624,0x7c8); + reg32_write(0x3c240628,0x101); + reg32_write(0x3c240018,0x0); + reg32_write(0x3c24001c,0x0); + reg32_write(0x3c240020,0x8); + reg32_write(0x3c240024,0x0); + reg32_write(0x3c240028,0x0); + reg32_write(0x3c24002c,0x0); + reg32_write(0x3c34039c,0x400); + reg32_write(0x3c24005c,0x0); + reg32_write(0x3c24007c,0x2a); + reg32_write(0x3c240098,0x6a); + reg32_write(0x3c100340,0x0); + reg32_write(0x3c100344,0x101); + reg32_write(0x3c100348,0x105); + reg32_write(0x3c10034c,0x107); + reg32_write(0x3c100350,0x10f); + reg32_write(0x3c100354,0x202); + reg32_write(0x3c100358,0x20a); + reg32_write(0x3c10035c,0x20b); + reg32_write(0x3c0800e8,0x2); + reg32_write(0x3c08002c,0x65); + reg32_write(0x3c080030,0xc9); + reg32_write(0x3c080034,0x7d1); + reg32_write(0x3c080038,0x2c); + reg32_write(0x3c48002c,0x65); + reg32_write(0x3c480030,0xc9); + reg32_write(0x3c480034,0x7d1); + reg32_write(0x3c480038,0x2c); + reg32_write(0x3c240030,0x0); + reg32_write(0x3c240034,0x173); + reg32_write(0x3c240038,0x60); + reg32_write(0x3c24003c,0x6110); + reg32_write(0x3c240040,0x2152); + reg32_write(0x3c240044,0xdfbd); + reg32_write(0x3c240048,0x60); + reg32_write(0x3c24004c,0x6152); + reg32_write(0x3c080040,0x5a); + reg32_write(0x3c080044,0x3); + reg32_write(0x3c480040,0x5a); + reg32_write(0x3c480044,0x3); + reg32_write(0x3c100200,0xe0); + reg32_write(0x3c100204,0x12); + reg32_write(0x3c100208,0xe0); + reg32_write(0x3c10020c,0x12); + reg32_write(0x3c100210,0xe0); + reg32_write(0x3c100214,0x12); + reg32_write(0x3c500200,0xe0); + reg32_write(0x3c500204,0x12); + reg32_write(0x3c500208,0xe0); + reg32_write(0x3c50020c,0x12); + reg32_write(0x3c500210,0xe0); + reg32_write(0x3c500214,0x12); + reg32_write(0x3c1003f4,0xf); + reg32_write(0x3c040044,0x1); + reg32_write(0x3c040048,0x1); + reg32_write(0x3c04004c,0x180); + reg32_write(0x3c040060,0x1); + reg32_write(0x3c040008,0x6209); + reg32_write(0x3c0402c8,0x1); + reg32_write(0x3c0406d0,0x1); + reg32_write(0x3c040ad0,0x1); + reg32_write(0x3c040ed0,0x1); + reg32_write(0x3c0412d0,0x1); + reg32_write(0x3c0416d0,0x1); + reg32_write(0x3c041ad0,0x1); + reg32_write(0x3c041ed0,0x1); + reg32_write(0x3c0422d0,0x1); + reg32_write(0x3c044044,0x1); + reg32_write(0x3c044048,0x1); + reg32_write(0x3c04404c,0x180); + reg32_write(0x3c044060,0x1); + reg32_write(0x3c044008,0x6209); + reg32_write(0x3c0442c8,0x1); + reg32_write(0x3c0446d0,0x1); + reg32_write(0x3c044ad0,0x1); + reg32_write(0x3c044ed0,0x1); + reg32_write(0x3c0452d0,0x1); + reg32_write(0x3c0456d0,0x1); + reg32_write(0x3c045ad0,0x1); + reg32_write(0x3c045ed0,0x1); + reg32_write(0x3c0462d0,0x1); + reg32_write(0x3c048044,0x1); + reg32_write(0x3c048048,0x1); + reg32_write(0x3c04804c,0x180); + reg32_write(0x3c048060,0x1); + reg32_write(0x3c048008,0x6209); + reg32_write(0x3c0482c8,0x1); + reg32_write(0x3c0486d0,0x1); + reg32_write(0x3c048ad0,0x1); + reg32_write(0x3c048ed0,0x1); + reg32_write(0x3c0492d0,0x1); + reg32_write(0x3c0496d0,0x1); + reg32_write(0x3c049ad0,0x1); + reg32_write(0x3c049ed0,0x1); + reg32_write(0x3c04a2d0,0x1); + reg32_write(0x3c04c044,0x1); + reg32_write(0x3c04c048,0x1); + reg32_write(0x3c04c04c,0x180); + reg32_write(0x3c04c060,0x1); + reg32_write(0x3c04c008,0x6209); + reg32_write(0x3c04c2c8,0x1); + reg32_write(0x3c04c6d0,0x1); + reg32_write(0x3c04cad0,0x1); + reg32_write(0x3c04ced0,0x1); + reg32_write(0x3c04d2d0,0x1); + reg32_write(0x3c04d6d0,0x1); + reg32_write(0x3c04dad0,0x1); + reg32_write(0x3c04ded0,0x1); + reg32_write(0x3c04e2d0,0x1); + reg32_write(0x3c0800e8,0x2); + reg32_write(0x3c300200,0x2); + //customer Post Train + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x0000006a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x00000001); + /* + * CalBusy.0 =1, indicates the calibrator is actively calibrating. + * Wait Calibrating done. + */ + tmp_t = 1; + while(tmp_t) { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097); + tmp_t = tmp & 0x01; + } + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0); + //disable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); +} + +void ddr_pll_bypass_100mts(void) { + /* change the clock source of dram_alt_clk_root to source 2 --100MHz */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0),(0x7<<24)|(0x7<<16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0),(0x2<<24)); + + /* change the clock source of dram_apb_clk_root to source 2 --40MHz */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x2<<24)|(0x1<<16)); + + /* disable the clock gating */ + reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8,5); /* PU_PGC_SW_PUP_REQ */ + + /* configure pll bypass mode */ + reg32_write(0x30389804, 1<<24); + + printf("PLL bypass to 100MTS setting done \n"); +} + +void ddr_pll_bypass_400mts(void) { + /* change the clock source of dram_alt_clk_root to source 2 --400MHz */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0),(0x7<<24)|(0x7<<16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0),(0x5<<24)); + + /* change the clock source of dram_apb_clk_root to source 2 --40MHz/2 */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x2<<24)|(0x1<<16)); + + /* disable the clock gating */ + reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8,5); /* PU_PGC_SW_PUP_REQ */ + + /* configure pll bypass mode */ + reg32_write(0x30389804, 1<<24); + + printf("PLL bypass to 400MTS setting done \n"); +} + + +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate) +{ + if (pstate == 2) + ddr_pll_bypass_100mts(); + else if (pstate == 1) + ddr_pll_bypass_400mts(); + else { + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4 << 24) | (0x3 << 16)); + reg32_write(0x30389808, 1 << 24); + } +} + +void lpddr4_800M_cfg_phy(void) { + unsigned int tmp, tmp_t; + + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20110, 0x02); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20111, 0x03); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20112, 0x04); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20113, 0x05); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20114, 0x00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20115, 0x01); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1005f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1015f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1105f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1115f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1205f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1215f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1305f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1315f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11005f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11015f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11105f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11115f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11205f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11215f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11305f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11315f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21005f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21015f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21105f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21115f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21205f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21215f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21305f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21315f, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x55, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1055, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2055, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3055, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4055, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5055, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6055, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7055, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8055, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9055, 0x1ff); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200c5, 0x19); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200c5, 0x7); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200c5, 0x7); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002e, 0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002e, 0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002e, 0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90204, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x190204, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x290204, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20024, 0xab); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120024, 0xab); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220024, 0xab); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20056, 0x3); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120056, 0xa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220056, 0xa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1004d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1014d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1104d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1114d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1204d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1214d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1304d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1314d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11004d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11014d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11104d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11114d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11204d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11214d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11304d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11314d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21004d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21014d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21104d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21114d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21204d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21214d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21304d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21314d, 0xe00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213049, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213149, 0xe38); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x43, 0x21); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1043, 0x21); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2043, 0x21); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3043, 0x21); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4043, 0x21); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5043, 0x21); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6043, 0x21); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7043, 0x21); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8043, 0x21); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9043, 0x21); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20018, 0x3); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20075, 0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20050, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20008, 0x320); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120008, 0x64); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220008, 0x19); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200b2, 0x19c); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200b2, 0x19c); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200b2, 0x19c); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213043, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213143, 0x5a1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200fa, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200fa, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200fa, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20019, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120019, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220019, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x660); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f1, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f2, 0x4444); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f3, 0x8888); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f4, 0x5555); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f5, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f6, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f7, 0xf000); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000b, 0x65); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000c, 0xc9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000d, 0x7d1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000e, 0x2c); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000b, 0xd); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000c, 0x1a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000d, 0xfb); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000e, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000b, 0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000c, 0x7); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000d, 0x3f); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000e, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20025, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002d, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002d, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002d, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20060, 0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + /* load the 1D training image */ + ddr_load_train_code(FW_1D_IMAGE); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + + /* set the PHY input clock to the desired frequency for pstate 2 */ + dwc_ddrphy_phyinit_userCustom_E_setDfiClk(2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x102); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x64); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); +extern void wait_ddrphy_training_complete(void); + wait_ddrphy_training_complete(); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + + /* set the PHY input clock to the desired frequency for pstate 1 */ + dwc_ddrphy_phyinit_userCustom_E_setDfiClk(1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x101); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x190); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x500); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); +extern void wait_ddrphy_training_complete(void); + wait_ddrphy_training_complete(); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + + /* set the PHY input clock to the desired frequency for pstate 0 */ + dwc_ddrphy_phyinit_userCustom_E_setDfiClk(0); + + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x131f); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0x5); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x312d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x84d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x312d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x84d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); +extern void wait_ddrphy_training_complete(void); +wait_ddrphy_training_complete(); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + /* load the 2D training image */ + ddr_load_train_code(FW_2D_IMAGE); + + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0); + + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x61); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x100); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x1f7f); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x084d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x084d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x500); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1); + /* Execute the Training Firmware */ + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x0); + /* wait for 2D training complete */ + extern void wait_ddrphy_training_complete(void); + wait_ddrphy_training_complete(); + + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1); + + /* (I) Load PHY Init Engine Image */ + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90000, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90001, 0x400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90002, 0x10e); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90003, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90004, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90005, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90029, 0xb); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002a, 0x480); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002b, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002c, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002d, 0x448); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002e, 0x139); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002f, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90030, 0x478); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90031, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90032, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90033, 0xe8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90034, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90035, 0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90036, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90037, 0x139); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90038, 0xf); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90039, 0x7c0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003a, 0x139); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003b, 0x44); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003c, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003d, 0x159); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003e, 0x14f); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003f, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90040, 0x159); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90041, 0x47); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90042, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90043, 0x149); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90044, 0x4f); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90045, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90046, 0x179); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90047, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90048, 0xe0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90049, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004a, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004b, 0x7c8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004c, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004d, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004e, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004f, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90050, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90051, 0x45a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90052, 0x9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90053, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90054, 0x448); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90055, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90056, 0x40); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90057, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90058, 0x179); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90059, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005a, 0x618); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005b, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005c, 0x40c0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005d, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005e, 0x149); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005f, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90060, 0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90061, 0x48); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90062, 0x4040); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90063, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90064, 0x149); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90065, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90066, 0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90067, 0x48); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90068, 0x40); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90069, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006a, 0x149); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006b, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006c, 0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006d, 0x18); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006e, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006f, 0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90070, 0x78); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90071, 0x549); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90072, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90073, 0x159); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90074, 0xd49); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90075, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90076, 0x159); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90077, 0x94a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90078, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90079, 0x159); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007a, 0x441); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007b, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007c, 0x149); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007d, 0x42); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007e, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007f, 0x149); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90080, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90081, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90082, 0x149); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90083, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90084, 0xe0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90085, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90086, 0xa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90087, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90088, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90089, 0x9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008a, 0x3c0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008b, 0x149); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008c, 0x9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008d, 0x3c0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008e, 0x159); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008f, 0x18); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90090, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90091, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90092, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90093, 0x3c0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90094, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90095, 0x18); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90096, 0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90097, 0x48); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90098, 0x18); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90099, 0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009a, 0x58); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009b, 0xa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009c, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009d, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009e, 0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009f, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a0, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a1, 0x5); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a2, 0x7c0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a3, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a4, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a5, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a6, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40000, 0x811); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40020, 0x880); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40040, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40060, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40001, 0x4016); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40021, 0x83); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40041, 0x4f); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40061, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40002, 0x4040); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40022, 0x83); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40042, 0x51); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40062, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40003, 0x811); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40023, 0x880); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40043, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40063, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40004, 0x720); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40024, 0xf); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40044, 0x1740); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40064, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40005, 0x16); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40025, 0x83); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40045, 0x4b); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40065, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40006, 0x716); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40026, 0xf); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40046, 0x2001); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40066, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40007, 0x716); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40027, 0xf); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40047, 0x2800); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40067, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40008, 0x716); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40028, 0xf); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40048, 0xf00); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40068, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40009, 0x720); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40029, 0xf); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40049, 0x1400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40069, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000a, 0xe08); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002a, 0xc15); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004a, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006a, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000b, 0x623); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002b, 0x15); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004b, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006b, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000c, 0x4004); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002c, 0x80); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004c, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006c, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000d, 0xe08); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002d, 0xc1a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004d, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006d, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000e, 0x623); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002e, 0x1a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004e, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006e, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000f, 0x4040); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002f, 0x80); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004f, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006f, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40010, 0x2604); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40030, 0x15); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40050, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40070, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40011, 0x708); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40031, 0x5); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40051, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40071, 0x2002); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40012, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40032, 0x80); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40052, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40072, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40013, 0x2604); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40033, 0x1a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40053, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40073, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40014, 0x708); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40034, 0xa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40054, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40074, 0x2002); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40015, 0x4040); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40035, 0x80); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40055, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40075, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40016, 0x60a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40036, 0x15); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40056, 0x1200); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40076, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40017, 0x61a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40037, 0x15); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40057, 0x1300); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40077, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40018, 0x60a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40038, 0x1a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40058, 0x1200); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40078, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40019, 0x642); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40039, 0x1a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40059, 0x1300); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40079, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4001a, 0x4808); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4003a, 0x880); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4005a, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4007a, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a7, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a8, 0x790); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a9, 0x11a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900aa, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ab, 0x7aa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ac, 0x2a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ad, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ae, 0x7b2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900af, 0x2a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b0, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b1, 0x7c8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b2, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b3, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b4, 0x2a8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b5, 0x129); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b6, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b7, 0x370); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b8, 0x129); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b9, 0xa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ba, 0x3c8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bb, 0x1a9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bc, 0xc); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bd, 0x408); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900be, 0x199); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bf, 0x14); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c0, 0x790); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c1, 0x11a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c2, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c3, 0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c4, 0x18); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c5, 0xc); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c6, 0x408); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c7, 0x199); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c8, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c9, 0x8568); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ca, 0x108); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cb, 0x18); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cc, 0x790); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cd, 0x16a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ce, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cf, 0x1d8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d0, 0x169); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d1, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d2, 0x8558); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d3, 0x168); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d4, 0x70); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d5, 0x788); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d6, 0x16a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d7, 0x1ff8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d8, 0x85a8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d9, 0x1e8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900da, 0x50); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900db, 0x798); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dc, 0x16a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dd, 0x60); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900de, 0x7a0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900df, 0x16a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e0, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e1, 0x8310); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e2, 0x168); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e3, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e4, 0xa310); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e5, 0x168); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e6, 0xa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e7, 0x408); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e8, 0x169); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e9, 0x6e); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ea, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900eb, 0x68); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ec, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ed, 0x408); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ee, 0x169); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ef, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f0, 0x8310); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f1, 0x168); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f2, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f3, 0xa310); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f4, 0x168); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f5, 0x1ff8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f6, 0x85a8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f7, 0x1e8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f8, 0x68); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f9, 0x798); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fa, 0x16a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fb, 0x78); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fc, 0x7a0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fd, 0x16a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fe, 0x68); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ff, 0x790); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90100, 0x16a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90101, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90102, 0x8b10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90103, 0x168); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90104, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90105, 0xab10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90106, 0x168); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90107, 0xa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90108, 0x408); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90109, 0x169); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010a, 0x58); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010b, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010c, 0x68); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010d, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010e, 0x408); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010f, 0x169); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90110, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90111, 0x8b10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90112, 0x168); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90113, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90114, 0xab10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90115, 0x168); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90116, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90117, 0x1d8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90118, 0x169); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90119, 0x80); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011a, 0x790); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011b, 0x16a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011c, 0x18); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011d, 0x7aa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011e, 0x6a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011f, 0xa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90120, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90121, 0x1e9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90122, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90123, 0x8080); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90124, 0x108); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90125, 0xf); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90126, 0x408); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90127, 0x169); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90128, 0xc); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90129, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012a, 0x68); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012b, 0x9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012c, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012d, 0x1a9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012e, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012f, 0x408); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90130, 0x169); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90131, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90132, 0x8080); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90133, 0x108); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90134, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90135, 0x7aa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90136, 0x6a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90137, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90138, 0x8568); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90139, 0x108); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013a, 0xb7); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013b, 0x790); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013c, 0x16a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013d, 0x1d); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013e, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013f, 0x68); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90140, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90141, 0x8558); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90142, 0x168); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90143, 0xf); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90144, 0x408); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90145, 0x169); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90146, 0xc); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90147, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90148, 0x68); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90149, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014a, 0x408); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014b, 0x169); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014c, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014d, 0x8558); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014e, 0x168); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014f, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90150, 0x3c8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90151, 0x1a9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90152, 0x3); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90153, 0x370); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90154, 0x129); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90155, 0x20); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90156, 0x2aa); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90157, 0x9); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90158, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90159, 0x400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015a, 0x10e); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015b, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015c, 0xe8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015d, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015e, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015f, 0x8140); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90160, 0x10c); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90161, 0x10); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90162, 0x8138); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90163, 0x10c); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90164, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90165, 0x7c8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90166, 0x101); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90167, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90168, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90169, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016a, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016b, 0x448); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016c, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016d, 0xf); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016e, 0x7c0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016f, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90170, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90171, 0xe8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90172, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90173, 0x47); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90174, 0x630); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90175, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90176, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90177, 0x618); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90178, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90179, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017a, 0xe0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017b, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017c, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017d, 0x7c8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017e, 0x109); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017f, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90180, 0x8140); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90181, 0x10c); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90182, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90183, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90184, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90185, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90186, 0x4); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90187, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90188, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90189, 0x7c8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018a, 0x101); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90006, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90007, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90008, 0x8); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90009, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000a, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000b, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd00e7, 0x400); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90017, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9001f, 0x2a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90026, 0x6a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d0, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d1, 0x101); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d2, 0x105); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d3, 0x107); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d4, 0x10f); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d5, 0x202); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d6, 0x20a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d7, 0x20b); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000c, 0x0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000d, 0x173); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000e, 0x60); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000f, 0x6110); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90010, 0x2152); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90011, 0xdfbd); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90012, 0x60); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90013, 0x6152); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20010, 0x5a); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20011, 0x3); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40080, 0xe0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40081, 0x12); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40082, 0xe0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40083, 0x12); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40084, 0xe0); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40085, 0x12); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400fd, 0xf); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10011, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10012, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10013, 0x180); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10018, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10002, 0x6209); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x100b2, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x101b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x102b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x103b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x104b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x105b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x106b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x107b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x108b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11011, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11012, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11013, 0x180); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11018, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11002, 0x6209); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110b2, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x114b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x115b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x116b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x117b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x118b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12011, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12012, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12013, 0x180); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12018, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002, 0x6209); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120b2, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x121b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x122b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x123b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x124b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x125b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x126b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x127b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x128b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13011, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13012, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13013, 0x180); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13018, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13002, 0x6209); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x130b2, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x131b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x132b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x133b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x134b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x135b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x136b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x137b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x138b4, 0x1); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xc0080, 0x2); + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x000d0000, 0x00000000); + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x0000006a); + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x00000001); + /* + * CalBusy.0 =1, indicates the calibrator is actively calibrating. + * Wait Calibrating done. + */ + tmp_t = 1; + while(tmp_t) { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097); + tmp_t = tmp & 0x01; + } + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0); +} diff --git a/board/freescale/imx8mq_phanbell/ddr/helper.c b/board/freescale/imx8mq_phanbell/ddr/helper.c new file mode 100644 index 00000000000..3cd44e8bfdf --- /dev/null +++ b/board/freescale/imx8mq_phanbell/ddr/helper.c @@ -0,0 +1,104 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define IMEM_LEN 32768//23400 //byte +#define DMEM_LEN 16384//1720 //byte +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +/* We need PHY iMEM PHY is 32KB padded */ +void ddr_load_train_code(enum fw_type type) +{ + u32 tmp32, i; + u32 error = 0; + unsigned long pr_to32, pr_from32; + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; + unsigned long imem_start = (unsigned long)&_end + fw_offset; + unsigned long dmem_start = imem_start + IMEM_LEN; + + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for(i = 0x0; i < IMEM_LEN; ){ + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for(i = 0x0; i < DMEM_LEN;){ + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + printf("check ddr4_pmu_train_imem code\n"); + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for(i = 0x0; i < IMEM_LEN;){ + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + + if(tmp32 != readl(pr_from32)){ + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + if(error){ + printf("check ddr4_pmu_train_imem code fail=%d\n",error); + }else{ + printf("check ddr4_pmu_train_imem code pass\n"); + } + + printf("check ddr4_pmu_train_dmem code\n"); + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for(i = 0x0; i < DMEM_LEN;){ + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + if(tmp32 != readl(pr_from32)){ + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + + if(error){ + printf("check ddr4_pmu_train_dmem code fail=%d",error); + }else{ + printf("check ddr4_pmu_train_dmem code pass\n"); + } +} diff --git a/board/freescale/imx8mq_phanbell/ddr/lpddr4_dvfs.h b/board/freescale/imx8mq_phanbell/ddr/lpddr4_dvfs.h new file mode 100644 index 00000000000..60d5dd4438f --- /dev/null +++ b/board/freescale/imx8mq_phanbell/ddr/lpddr4_dvfs.h @@ -0,0 +1,78 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LPDDR4_DVFS_H__ +#define __LPDDR4_DVFS_H__ +#include + +#define DFILP_SPT + +#define ANAMIX_PLL_BASE_ADDR 0x30360000 +#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60) +#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64) +#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68) + +#define LPDDR4_HDT_CTL_2D 0xC8 /* stage completion */ +#define LPDDR4_HDT_CTL_3200_1D 0xC8 /* stage completion */ +#define LPDDR4_HDT_CTL_400_1D 0xC8 /* stage completion */ +#define LPDDR4_HDT_CTL_100_1D 0xC8 /* stage completion */ + +/* 2D share & weight */ +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 +#define LPDDR4_CATRAIN_3200_1d 0 +#define LPDDR4_CATRAIN_400 0 +#define LPDDR4_CATRAIN_100 0 +#define LPDDR4_CATRAIN_3200_2d 0 + +#define WR_POST_EXT_3200 /* recommened to define */ + +/* lpddr4 phy training config */ +/* for LPDDR4 Rtt */ +#define LPDDR4_RTT40 6 +#define LPDDR4_RTT48 5 +#define LPDDR4_RTT60 4 +#define LPDDR4_RTT80 3 +#define LPDDR4_RTT120 2 +#define LPDDR4_RTT240 1 +#define LPDDR4_RTT_DIS 0 + +/* for LPDDR4 Ron */ +#define LPDDR4_RON34 7 +#define LPDDR4_RON40 6 +#define LPDDR4_RON48 5 +#define LPDDR4_RON60 4 +#define LPDDR4_RON80 3 + +#define LPDDR4_PHY_ADDR_RON60 0x1 +#define LPDDR4_PHY_ADDR_RON40 0x3 +#define LPDDR4_PHY_ADDR_RON30 0x7 +#define LPDDR4_PHY_ADDR_RON24 0xf +#define LPDDR4_PHY_ADDR_RON20 0x1f + +/* for read channel */ +#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */ +#define LPDDR4_PHY_RTT 30 +#define LPDDR4_PHY_VREF_VALUE 17 + +/* for write channel */ +#define LPDDR4_PHY_RON 30 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 +#define LPDDR4_RTT_DQ LPDDR4_RTT40 /* MR11[2:0] */ +#define LPDDR4_RTT_CA LPDDR4_RTT40 /* MR11[6:4] */ +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 /* MR11[6:4] */ +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 /* LPDDR4_RTT_DIS//MR11[6:4] */ +#define LPDDR4_VREF_VALUE_CA ((1<<6)|(0xd)) /*((0<<6)|(0xe)) MR12 */ +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1<<6)|(0xd)) /* MR14 */ +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1<<6)|(0xd)) /* MR14 */ +#define LPDDR4_MR22_RANK0 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */ +#define LPDDR4_MR22_RANK1 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */ +#define LPDDR4_MR3_PU_CAL 1 /* MR3[0] */ + +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 + +#endif /*__LPDDR4_DVFS_H__ */ diff --git a/board/freescale/imx8mq_phanbell/ddr/wait_ddrphy_training_complete.c b/board/freescale/imx8mq_phanbell/ddr/wait_ddrphy_training_complete.c new file mode 100644 index 00000000000..0b42e58bd1d --- /dev/null +++ b/board/freescale/imx8mq_phanbell/ddr/wait_ddrphy_training_complete.c @@ -0,0 +1,96 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +static inline void poll_pmu_message_ready(void) +{ + unsigned int reg; + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + } while (reg & 0x1); +} + +static inline void ack_pmu_message_recieve(void) +{ + unsigned int reg; + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0); + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + } while (!(reg & 0x1)); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032); + + ack_pmu_message_recieve(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032); + + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034); + + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_recieve(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + ddr_printf("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + ddr_printf(" PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)){ + arg = get_stream_message(); + ddr_printf(" arg[%d] = 0x%08x\n", i, arg); + i++; + } + + ddr_printf("\n"); +} + +void wait_ddrphy_training_complete(void) +{ + unsigned int mail; + while (1) { + mail = get_mail(); + decode_major_message(mail); + if (mail == 0x08) { + decode_streaming_message(); + } else if (mail == 0x07) { + printf("Training PASS\n"); + break; + } else if (mail == 0xff) { + printf("Training FAILED\n"); + break; + } + } +} diff --git a/board/freescale/imx8mq_phanbell/imx8m_phanbell.c b/board/freescale/imx8mq_phanbell/imx8m_phanbell.c new file mode 100644 index 00000000000..b3890083090 --- /dev/null +++ b/board/freescale/imx8mq_phanbell/imx8m_phanbell.c @@ -0,0 +1,399 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_QSPI +static iomux_v3_cfg_t const qspi_pads[] = { + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); + + set_clk_qspi(); + + return 0; +} +#endif + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + /* TODO */ + return 0; +} +#endif + +/* layout of baseboard id */ +#define IMX8MQ_GPIO3_IO25 IMX_GPIO_NR(3, 25) //board_id[6]:6 +#define IMX8MQ_GPIO3_IO19 IMX_GPIO_NR(3, 19) //board_id[6]:5 +#define IMX8MQ_GPIO3_IO20 IMX_GPIO_NR(3, 20) //board_id[6]:4 +#define IMX8MQ_GPIO3_IO24 IMX_GPIO_NR(3, 24) //board_id[6]:3 +#define IMX8MQ_GPIO3_IO23 IMX_GPIO_NR(3, 23) //board_id[6]:2 +#define IMX8MQ_GPIO3_IO22 IMX_GPIO_NR(3, 22) //board_id[6]:1 +#define IMX8MQ_GPIO3_IO21 IMX_GPIO_NR(3, 21) //board_id[6]:0 + +/* GPIO port description */ +static unsigned long imx8m_gpio_ports[] = { + [0] = GPIO1_BASE_ADDR, + [1] = GPIO2_BASE_ADDR, + [2] = GPIO3_BASE_ADDR, + [3] = GPIO4_BASE_ADDR, + [4] = GPIO5_BASE_ADDR, +}; + +/* use legacy gpio operations before device model is ready. */ +static int gpio_direction_input_legacy(unsigned int gpio) +{ + unsigned int port; + struct gpio_regs *regs; + u32 l; + + port = gpio/32; + + gpio &= 0x1f; + + regs = (struct gpio_regs *)imx8m_gpio_ports[port]; + + l = readl(®s->gpio_dir); + /* set direction as input. */ + l &= ~(1 << gpio); + writel(l, ®s->gpio_dir); + + return 0; +} + +static int gpio_get_value_legacy(unsigned gpio) +{ + unsigned int port; + struct gpio_regs *regs; + u32 val; + + port = gpio/32; + + gpio &= 0x1f; + + regs = (struct gpio_regs *)imx8m_gpio_ports[port]; + + val = (readl(®s->gpio_dr) >> gpio) & 0x01; + + return val; +} + +int get_imx8m_baseboard_id(void) +{ + int i = 0, value = 0; + int baseboard_id; + int pin[7]; + + /* initialize the pin array */ + pin[0] = IMX8MQ_GPIO3_IO21; + pin[1] = IMX8MQ_GPIO3_IO22; + pin[2] = IMX8MQ_GPIO3_IO23; + pin[3] = IMX8MQ_GPIO3_IO24; + pin[4] = IMX8MQ_GPIO3_IO20; + pin[5] = IMX8MQ_GPIO3_IO19; + pin[6] = IMX8MQ_GPIO3_IO25; + + /* Set gpio direction as input and get the input value */ + baseboard_id = 0; + for (i = 0; i < 7; i++) { + gpio_direction_input_legacy(pin[i]); + if ((value = gpio_get_value_legacy(pin[i])) < 0) { + printf("Error! Read gpio port: %d failed!\n", pin[i]); + return -1; + } + else + baseboard_id |= ((value & 0x01) << i); + } + + return baseboard_id; +} +#ifdef CONFIG_IMX_TRUSTY_OS +int get_tee_load(ulong *load) +{ + int board_id; + + board_id = get_imx8m_baseboard_id(); + /* load TEE to the last 32M of DDR */ + if ((board_id == ENTERPRISE_MICRON_1G) || + (board_id == ENTERPRISE_HYNIX_1G)) { + /* for 1G DDR board */ + *load = (ulong)TEE_LOAD_ADDR_1G; + } else { + /* for 3G DDR board */ + *load = (ulong)TEE_LOAD_ADDR_3G; + } + + return 0; +} +#endif + +int dram_init(void) +{ + int baseboard_id; + uint32_t ddr_size = 0; + /* different boards have different DDR type, distinguish the DDR + * type by board id. + */ + baseboard_id = get_imx8m_baseboard_id(); + if ((baseboard_id == ENTERPRISE_MICRON_1G) || + (baseboard_id == ENTERPRISE_HYNIX_1G)) { + /* 1G DDR size */ + ddr_size = 0x40000000; + } else{ + /* Default to use 3G DDR size */ + ddr_size = 0xc0000000; + } + + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = ddr_size - rom_pointer[1]; + else + gd->ram_size = ddr_size; + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +#define FEC_RST_PAD IMX_GPIO_NR(1, 9) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(1, 9), 1); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); + return set_clk_enet(ENET_125MHZ); +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_USB_DWC3 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_SUPER, + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .power_down_scale = 2, +}; + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); +} +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) +int board_usb_init(int index, enum usb_init_type init) +{ + imx8m_usb_power(index, true); + + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_nxp_usb_phy_init(&dwc3_device_data); + return dwc3_uboot_init(&dwc3_device_data); + } + + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_uboot_exit(index); + } + + imx8m_usb_power(index, false); + + return 0; +} +#endif + +int board_init(void) +{ + board_qspi_init(); + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) + init_usb_clk(); +#endif + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "Phanbell"); + env_set("board_rev", "iMX8MQ"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + int baseboard_id; + baseboard_id = get_imx8m_baseboard_id(); + if ((baseboard_id == ENTERPRISE_MICRON_1G) || + (baseboard_id == ENTERPRISE_HYNIX_1G)) { + /* 1G DDR size */ + env_set("bootargs_ram_capacity", "cma=296M galcore.contiguousSize=8388608"); + } else { + /* 3G DDR size */ + env_set("bootargs_ram_capacity", "cma=384M"); + } + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/freescale/imx8mq_phanbell/spl.c b/board/freescale/imx8mq_phanbell/spl.c new file mode 100644 index 00000000000..75ecb93b148 --- /dev/null +++ b/board/freescale/imx8mq_phanbell/spl.c @@ -0,0 +1,248 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr/ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + /* ddr init */ + ddr_init(); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_bd71837_init(I2C_PMIC); + if (ret) + printf("power init failed"); + + p = pmic_get("BD71837"); + pmic_probe(p); + + /* unlock the PMIC regs */ + pmic_reg_write(p, BD71837_REGLOCK, 0x1); + + /* Set BUCK2 output for ARM to 0.85v */ + pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x0f); + + /* Set BUCK3 output for GPU off */ + pmic_reg_write(p, BD71837_BUCK3_CTRL, 0x46); + + /* Set BUCK4 output for VPU off */ + pmic_reg_write(p, BD71837_BUCK4_CTRL, 0x46); + + /* Set BUCK5 output for DRAM to 0.9V */ + pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2); + + /* Set BUCK6 output for VDD_3V3 to 3.1V */ + pmic_reg_write(p, BD71837_BUCK6_VOLT, 0x1); + + /* Set BUCK7 output for VDD_1V8 to 1.695V */ + pmic_reg_write(p, BD71837_BUCK7_VOLT, 0x1); + + /* lock the PMIC regs */ + pmic_reg_write(p, BD71837_REGLOCK, 0x11); + return 0; +} +#endif + +void spl_board_init(void) +{ +#ifndef CONFIG_SPL_USB_SDP_SUPPORT + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } +#endif + init_usb_clk(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(0); /* Init UART0 clock */ + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8qm_arm2/Kconfig b/board/freescale/imx8qm_arm2/Kconfig new file mode 100644 index 00000000000..3e2ca251bc5 --- /dev/null +++ b/board/freescale/imx8qm_arm2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8QM_LPDDR4_ARM2 || TARGET_IMX8QM_DDR4_ARM2 + +config SYS_BOARD + default "imx8qm_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qm_arm2" + +endif diff --git a/board/freescale/imx8qm_arm2/Makefile b/board/freescale/imx8qm_arm2/Makefile new file mode 100644 index 00000000000..2b5fdd9b71e --- /dev/null +++ b/board/freescale/imx8qm_arm2/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_arm2.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/freescale/imx8qm_arm2/imx8qm_arm2.c b/board/freescale/imx8qm_arm2/imx8qm_arm2.c new file mode 100644 index 00000000000..911485e5dcc --- /dev/null +++ b/board/freescale/imx8qm_arm2/imx8qm_arm2.c @@ -0,0 +1,720 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pca953x.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_ipc_t ipcHndl = 0; + sc_err_t sciErr = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + /* Power up UART0, this is very early while power domain is not working */ + sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, 2, &rate); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Enable UART0 clock root */ + sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_0, 2, true, false); + if (sciErr != SC_ERR_NONE) + return 0; + + LPCG_AllClockOn(LPUART_0_LPCG); + + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12) + +#ifndef CONFIG_SPL_BUILD + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +#endif + {USDHC3_BASE_ADDR, 0, 4}, +}; + +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for WP */ + SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for CD, GPIO5 IO22 */ + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; +#endif +static iomux_cfg_t usdhc2_sd[] = { + SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux to GPIO4 IO12 */ +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + struct power_domain pd; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 + case 0: + if (!power_domain_lookup_name("conn_sdhc0", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + if (!power_domain_lookup_name("conn_sdhc1", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + case 2: +#else + case 0: +#endif + + if (!power_domain_lookup_name("conn_sdhc2", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); + init_clk_usdhc(2); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gpio_request(USDHC2_CD_GPIO, "sd2_cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 + ret = 1; /* eMMC */ +#else + ret = 0; /* eMMC not present on DDR4 board */ +#endif + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} +#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_FSL_ESDHC */ + + +#ifdef CONFIG_FEC_MXC +#include + +static iomux_cfg_t pad_enet1[] = { + SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + if (0 == CONFIG_FEC_ENET_DEV) + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); + else + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1)); +} + +static void enet_device_phy_reset(void) +{ + struct gpio_desc desc_enet0; + struct gpio_desc desc_enet1; + int ret; + + ret = dm_gpio_lookup_name("gpio@18_1", &desc_enet0); + if (ret) + return; + + ret = dm_gpio_request(&desc_enet0, "enet0_reset"); + if (ret) + return; + ret = dm_gpio_lookup_name("gpio@18_4", &desc_enet1); + if (ret) + return; + + ret = dm_gpio_request(&desc_enet1, "enet1_reset"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc_enet0, GPIOD_IS_OUT); + dm_gpio_set_value(&desc_enet0, 0); + udelay(50); + dm_gpio_set_value(&desc_enet0, 1); + + dm_gpio_set_dir_flags(&desc_enet1, GPIOD_IS_OUT); + dm_gpio_set_value(&desc_enet1, 0); + udelay(50); + dm_gpio_set_value(&desc_enet1, 1); + + /* The board has a long delay for this reset to become stable */ + mdelay(200); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + struct power_domain pd; + + printf("[%s] %d\n", __func__, __LINE__); + + if (CONFIG_FEC_ENET_DEV) { + if (!power_domain_lookup_name("conn_enet1", &pd)) + power_domain_on(&pd); + } else { + if (!power_domain_lookup_name("conn_enet0", &pd)) + power_domain_on(&pd); + } + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} + +int board_phy_config(struct phy_device *phydev) +{ +#ifdef CONFIG_FEC_ENABLE_MAX7322 + uint8_t value; + + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS); + + if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) { + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1)) + printf("MAX7322 write failed\n"); + } else { + printf("MAX7322 Not found\n"); + } + mdelay(1); +#endif + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +static int setup_fec(int ind) +{ + /* Reset ENET PHY */ + enet_device_phy_reset(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO + +#define LVDS_ENABLE IMX_GPIO_NR(1, 6) +#define MIPI_ENABLE IMX_GPIO_NR(1, 7) +#define DEBUG_LED IMX_GPIO_NR(2, 15) +#define IOEXP_RESET IMX_GPIO_NR(1, 12) + +static iomux_cfg_t board_gpios[] = { + SC_P_LVDS0_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_LVDS0_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_LVDS1_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_SPDIF0_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void board_gpio_init(void) +{ + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + gpio_request(DEBUG_LED, "debug_led"); + gpio_direction_output(DEBUG_LED, 1); + + /* enable i2c port expander assert reset line */ + gpio_request(IOEXP_RESET, "ioexp_rst"); + gpio_direction_output(IOEXP_RESET, 1); + + /* enable LVDS SAS boards */ + gpio_request(LVDS_ENABLE, "lvds_enable"); + gpio_direction_output(LVDS_ENABLE, 1); + + /* enable MIPI SAS boards */ + gpio_request(MIPI_ENABLE, "mipi_enable"); + gpio_direction_output(MIPI_ENABLE, 1); +} +#endif + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 + puts("Board: iMX8QM LPDDR4 ARM2\n"); +#else + puts("Board: iMX8QM DDR4 ARM2\n"); +#endif + + print_bootinfo(); + + /* Note: After reloc, ipcHndl will no longer be valid. If handle + * returned by sc_ipc_open matches SC_IPC_CH, use this + * macro (valid after reloc) for subsequent SCI calls. + */ + if (gd->arch.ipc_channel_handle != SC_IPC_CH) { + printf("\nSCI error! Invalid handle\n"); + } + + return 0; +} + +#ifdef CONFIG_FSL_HSIO + +#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT)) +static iomux_cfg_t board_pcie_pins[] = { + SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), + SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), + SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), +}; + +static void imx8qm_hsio_initialize(void) +{ + struct power_domain pd; + int ret; + + if (!power_domain_lookup_name("hsio_sata0", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_sata0 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("hsio_pcie0", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_pcie0 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("hsio_pcie1", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_pcie1 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("hsio_gpio", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_gpio Power up failed! (error = %d)\n", ret); + } + + LPCG_AllClockOn(HSIO_PCIE_X2_LPCG); + LPCG_AllClockOn(HSIO_PCIE_X1_LPCG); + LPCG_AllClockOn(HSIO_SATA_LPCG); + LPCG_AllClockOn(HSIO_PHY_X2_LPCG); + LPCG_AllClockOn(HSIO_PHY_X1_LPCG); + LPCG_AllClockOn(HSIO_PHY_X2_CRR0_LPCG); + LPCG_AllClockOn(HSIO_PHY_X1_CRR1_LPCG); + LPCG_AllClockOn(HSIO_PCIE_X2_CRR2_LPCG); + LPCG_AllClockOn(HSIO_PCIE_X1_CRR3_LPCG); + LPCG_AllClockOn(HSIO_SATA_CRR4_LPCG); + LPCG_AllClockOn(HSIO_MISC_LPCG); + LPCG_AllClockOn(HSIO_GPIO_LPCG); + + imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins)); + +} + +void pci_init_board(void) +{ + /* test the 1 lane mode of the PCIe A controller */ + mx8qm_pcie_init(); +} +#endif + +#ifdef CONFIG_USB_CDNS3_GADGET + +static struct cdns3_device cdns3_device_data = { + .none_core_base = 0x5B110000, + .xhci_base = 0x5B130000, + .dev_base = 0x5B140000, + .phy_base = 0x5B160000, + .otg_base = 0x5B120000, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 1, +}; + +int usb_gadget_handle_interrupts(void) +{ + cdns3_uboot_handle_interrupt(1); + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_DEVICE) { + struct power_domain pd; + int ret; + + /* Power on usb */ + if (!power_domain_lookup_name("conn_usb2", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_usb2 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("conn_usb2_phy", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_usb2_phy Power up failed! (error = %d)\n", ret); + } + + ret = cdns3_uboot_init(&cdns3_device_data); + printf("%d cdns3_uboot_initmode %d\n", index, ret); + } + } + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_DEVICE) { + struct power_domain pd; + int ret; + + cdns3_uboot_exit(1); + + /* Power off usb */ + if (!power_domain_lookup_name("conn_usb2", &pd)) { + ret = power_domain_off(&pd); + if (ret) + printf("conn_usb2 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("conn_usb2_phy", &pd)) { + ret = power_domain_off(&pd); + if (ret) + printf("conn_usb2_phy Power up failed! (error = %d)\n", ret); + } + } + } + return ret; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_FSL_HSIO + imx8qm_hsio_initialize(); +#ifdef CONFIG_SCSI_AHCI_PLAT + sata_init(); +#endif +#endif + return 0; +} + +void board_quiesce_devices() +{ + const char *power_on_devices[] = { + "dma_lpuart0", + }; + + power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + puts("SCI reboot request"); + sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD); + while (1) + putc('.'); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 + return devno; +#else + return devno - 2; +#endif +} + +int mmc_map_to_kernel_blk(int dev_no) +{ +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 + return dev_no; +#else + return dev_no + 2; +#endif +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "ARM2"); + env_set("board_rev", "iMX8QM"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +#if defined(CONFIG_VIDEO_IMXDPUV1) +static void enable_lvds(struct display_info_t const *dev) +{ + display_controller_setup((PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_soc_setup(dev->bus, (PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_configure(dev->bus); + lvds2hdmi_setup(6); +} + +struct display_info_t const displays[] = {{ + .bus = 0, /* LVDS0 */ + .addr = 0, /* Unused */ + .pixfmt = IMXDPUV1_PIX_FMT_BGRA32, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "IT6263", /* 720P60 */ + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 13468, /* 74250000 */ + .left_margin = 110, + .right_margin = 220, + .upper_margin = 5, + .lower_margin = 20, + .hsync_len = 40, + .vsync_len = 5, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +#endif /* CONFIG_VIDEO_IMXDPUV1 */ diff --git a/board/freescale/imx8qm_arm2/spl.c b/board/freescale/imx8qm_arm2/spl.c new file mode 100644 index 00000000000..cb25483c100 --- /dev/null +++ b/board/freescale/imx8qm_arm2/spl.c @@ -0,0 +1,243 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pca953x.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +#endif + {USDHC3_BASE_ADDR, 0, 4}, +}; + +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for WP */ + SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for CD, GPIO5 IO22 */ + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; +#endif +static iomux_cfg_t usdhc2_sd[] = { + SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux to GPIO4 IO12 */ +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 + case 0: + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_0, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_1, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_GPIO_5, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + case 2: +#else + case 0: +#endif + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_2, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_GPIO_4, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); + init_clk_usdhc(2); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gpio_request(USDHC2_CD_GPIO, "sd2_cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 + ret = 1; /* eMMC */ +#else + ret = 0; /* eMMC not present on DDR4 board */ +#endif + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC */ + +void spl_dram_init(void) +{ + /* do nothing for now */ +} + +void spl_board_init(void) +{ + /* DDR initialization */ + spl_dram_init(); + + puts("Normal Boot\n"); +} + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} + diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig new file mode 100644 index 00000000000..93d7d5f9c57 --- /dev/null +++ b/board/freescale/imx8qm_mek/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8QM_MEK + +config SYS_BOARD + default "imx8qm_mek" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qm_mek" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8qm_mek/Makefile b/board/freescale/imx8qm_mek/Makefile new file mode 100644 index 00000000000..ac9391d27d1 --- /dev/null +++ b/board/freescale/imx8qm_mek/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_mek.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif + diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c new file mode 100644 index 00000000000..b32e5223240 --- /dev/null +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -0,0 +1,628 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_ipc_t ipcHndl = 0; + sc_err_t sciErr = 0; + + /* When start u-boot in XEN VM, directly return */ + if (IS_ENABLED(CONFIG_XEN)) { + writel(0xF53535F5, (void __iomem *)0x80000000); + return 0; + } + + ipcHndl = gd->arch.ipc_channel_handle; + + /* Power up UART0, this is very early while power domain is not working */ + sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, 2, &rate); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Enable UART0 clock root */ + sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_0, 2, true, false); + if (sciErr != SC_ERR_NONE) + return 0; + + LPCG_AllClockOn(LPUART_0_LPCG); + + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_FEC_MXC +#include + +static iomux_cfg_t pad_enet1[] = { + SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + if (0 == CONFIG_FEC_ENET_DEV) + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); + else + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1)); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + struct power_domain pd; + + printf("[%s] %d\n", __func__, __LINE__); + + if (CONFIG_FEC_ENET_DEV) { + if (!power_domain_lookup_name("conn_enet1", &pd)) + power_domain_on(&pd); + } else { + if (!power_domain_lookup_name("conn_enet0", &pd)) + power_domain_on(&pd); + } + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO + +#define LVDS_ENABLE IMX_GPIO_NR(1, 6) +#define MIPI_ENABLE IMX_GPIO_NR(1, 7) + +#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20) +#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24) +#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23) + +static void board_gpio_init(void) +{ + /* Enable BB 3V3 */ + gpio_request(BB_GPIO_3V3_1, "bb_3v3_1"); + gpio_direction_output(BB_GPIO_3V3_1, 1); + gpio_request(BB_GPIO_3V3_2, "bb_3v3_2"); + gpio_direction_output(BB_GPIO_3V3_2, 1); + gpio_request(BB_GPIO_3V3_3, "bb_3v3_3"); + gpio_direction_output(BB_GPIO_3V3_3, 1); + + /* enable LVDS SAS boards */ + gpio_request(LVDS_ENABLE, "lvds_enable"); + gpio_direction_output(LVDS_ENABLE, 1); + + /* enable MIPI SAS boards */ + gpio_request(MIPI_ENABLE, "mipi_enable"); + gpio_direction_output(MIPI_ENABLE, 1); +} +#endif + +int checkboard(void) +{ + puts("Board: iMX8QM MEK\n"); + + print_bootinfo(); + + /* Note: After reloc, ipcHndl will no longer be valid. If handle + * returned by sc_ipc_open matches SC_IPC_CH, use this + * macro (valid after reloc) for subsequent SCI calls. + */ + if (gd->arch.ipc_channel_handle != SC_IPC_CH) { + printf("\nSCI error! Invalid handle\n"); + } + + return 0; +} + +#ifdef CONFIG_FSL_HSIO + +#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT)) +static iomux_cfg_t board_pcie_pins[] = { + SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), + SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), + SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), +}; + +static void imx8qm_hsio_initialize(void) +{ + struct power_domain pd; + int ret; + + if (!power_domain_lookup_name("hsio_sata0", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_sata0 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("hsio_pcie0", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_pcie0 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("hsio_pcie1", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_pcie1 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("hsio_gpio", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_gpio Power up failed! (error = %d)\n", ret); + } + + LPCG_AllClockOn(HSIO_PCIE_X2_LPCG); + LPCG_AllClockOn(HSIO_PCIE_X1_LPCG); + LPCG_AllClockOn(HSIO_SATA_LPCG); + LPCG_AllClockOn(HSIO_PHY_X2_LPCG); + LPCG_AllClockOn(HSIO_PHY_X1_LPCG); + LPCG_AllClockOn(HSIO_PHY_X2_CRR0_LPCG); + LPCG_AllClockOn(HSIO_PHY_X1_CRR1_LPCG); + LPCG_AllClockOn(HSIO_PCIE_X2_CRR2_LPCG); + LPCG_AllClockOn(HSIO_PCIE_X1_CRR3_LPCG); + LPCG_AllClockOn(HSIO_SATA_CRR4_LPCG); + LPCG_AllClockOn(HSIO_MISC_LPCG); + LPCG_AllClockOn(HSIO_GPIO_LPCG); + + imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins)); +} + +void pci_init_board(void) +{ + /* test the 1 lane mode of the PCIe A controller */ + mx8qm_pcie_init(); +} +#endif + +#ifdef CONFIG_USB + +#ifdef CONFIG_USB_TCPC +#define USB_TYPEC_SEL IMX_GPIO_NR(4, 6) +#define USB_TYPEC_EN IMX_GPIO_NR(4, 19) + +static iomux_cfg_t ss_mux_gpio[] = { + SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +struct tcpc_port port; +struct tcpc_port_config port_config = { + .i2c_bus = 0, + .addr = 0x51, + .port_type = TYPEC_PORT_DFP, +}; + +void ss_mux_select(enum typec_cc_polarity pol) +{ + if (pol == TYPEC_POLARITY_CC1) + gpio_direction_output(USB_TYPEC_SEL, 0); + else + gpio_direction_output(USB_TYPEC_SEL, 1); +} + +static void setup_typec(void) +{ + imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); + gpio_request(USB_TYPEC_SEL, "typec_sel"); + gpio_request(USB_TYPEC_EN, "typec_en"); + + gpio_direction_output(USB_TYPEC_EN, 1); + + tcpc_init(&port, port_config, &ss_mux_select); +} +#endif + +#ifdef CONFIG_USB_CDNS3_GADGET +static struct cdns3_device cdns3_device_data = { + .none_core_base = 0x5B110000, + .xhci_base = 0x5B130000, + .dev_base = 0x5B140000, + .phy_base = 0x5B160000, + .otg_base = 0x5B120000, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 1, +}; + +int usb_gadget_handle_interrupts(int index) +{ + cdns3_uboot_handle_interrupt(index); + return 0; +} +#endif + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_dfp_mode(&port); +#endif +#ifdef CONFIG_USB_CDNS3_GADGET + } else { +#ifdef CONFIG_SPL_BUILD + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + printf("conn_usb2 Power up failed! (error = %d)\n", ret); + + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2_PHY, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + printf("conn_usb2_phy Power up failed! (error = %d)\n", ret); +#else + struct power_domain pd; + int ret; + + /* Power on usb */ + if (!power_domain_lookup_name("conn_usb2", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_usb2 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("conn_usb2_phy", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_usb2_phy Power up failed! (error = %d)\n", ret); + } +#endif + +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_ufp_mode(&port); + printf("%d setufp mode %d\n", index, ret); +#endif + + ret = cdns3_uboot_init(&cdns3_device_data); + printf("%d cdns3_uboot_initmode %d\n", index, ret); +#endif + } + } + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_disable_src_vbus(&port); +#endif +#ifdef CONFIG_USB_CDNS3_GADGET + } else { + cdns3_uboot_exit(1); + +#ifdef CONFIG_SPL_BUILD + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2, SC_PM_PW_MODE_OFF); + if (ret != SC_ERR_NONE) + printf("conn_usb2 Power down failed! (error = %d)\n", ret); + + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2_PHY, SC_PM_PW_MODE_OFF); + if (ret != SC_ERR_NONE) + printf("conn_usb2_phy Power down failed! (error = %d)\n", ret); +#else + struct power_domain pd; + int ret; + + /* Power off usb */ + if (!power_domain_lookup_name("conn_usb2", &pd)) { + ret = power_domain_off(&pd); + if (ret) + printf("conn_usb2 Power down failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("conn_usb2_phy", &pd)) { + ret = power_domain_off(&pd); + if (ret) + printf("conn_usb2_phy Power down failed! (error = %d)\n", ret); + } +#endif +#endif + } + } + return ret; +} +#endif + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + +#ifdef CONFIG_FSL_HSIO + imx8qm_hsio_initialize(); +#ifdef CONFIG_SCSI_AHCI_PLAT + sata_init(); +#endif +#endif + +#if defined(CONFIG_USB_XHCI_IMX8) && defined(CONFIG_USB_TCPC) + setup_typec(); +#endif + + return 0; +} + +void board_quiesce_devices(void) +{ + const char *power_on_devices[] = { + "dma_lpuart0", + }; + + if (IS_ENABLED(CONFIG_XEN)) { + /* Clear magic number to let xen know uboot is over */ + writel(0x0, (void __iomem *)0x80000000); + return; + } + + power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + puts("SCI reboot request"); + sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD); + while (1) + putc('.'); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return dev_no; +} + +extern uint32_t _end_ofs; +int board_late_init(void) +{ + char *fdt_file; + bool m4_boot; + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "MEK"); + env_set("board_rev", "iMX8QM"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + fdt_file = env_get("fdt_file"); + m4_boot = check_m4_parts_boot(); + + if (fdt_file && !strcmp(fdt_file, "undefined")) { + if (m4_boot) + env_set("fdt_file", "fsl-imx8qm-mek-rpmsg.dtb"); + else + env_set("fdt_file", "fsl-imx8qm-mek.dtb"); + } + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + +#ifdef IMX_LOAD_HDMI_FIMRWARE + char *end_of_uboot; + char command[256]; + end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob)); + end_of_uboot += 9; + + /* load hdmitxfw.bin and hdmirxfw.bin*/ + memcpy((void *)IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot, + IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE); + + sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR); + run_command(command, 0); + + sprintf(command, "hdprx load 0x%x", + IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE); + run_command(command, 0); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +#if defined(CONFIG_VIDEO_IMXDPUV1) +static void enable_lvds(struct display_info_t const *dev) +{ + display_controller_setup((PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_soc_setup(dev->bus, (PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_configure(dev->bus); + lvds2hdmi_setup(6); +} + +struct display_info_t const displays[] = {{ + .bus = 0, /* LVDS0 */ + .addr = 0, /* Unused */ + .pixfmt = IMXDPUV1_PIX_FMT_BGRA32, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "IT6263", /* 720P60 */ + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 13468, /* 74250000 */ + .left_margin = 110, + .right_margin = 220, + .upper_margin = 5, + .lower_margin = 20, + .hsync_len = 40, + .vsync_len = 5, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +#endif /* CONFIG_VIDEO_IMXDPUV1 */ diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c new file mode 100644 index 00000000000..74366abe91f --- /dev/null +++ b/board/freescale/imx8qm_mek/spl.c @@ -0,0 +1,238 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pca953x.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for WP */ + SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for CD, GPIO5 IO22 */ + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_0, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_1, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_GPIO_5, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; /* eMMC */ + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC */ + +void spl_dram_init(void) +{ + /* do nothing for now */ +} + +void spl_board_init(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + if (sc_rm_is_resource_owned(ipcHndl, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) { + puts("Warning: failed to initialize FSPI0\n"); + } + } +#endif + + /* DDR initialization */ + spl_dram_init(); + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + if (sc_rm_is_resource_owned(ipcHndl, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) { + puts("Warning: failed to turn off FSPI0\n"); + } + } +#endif +} + + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} + diff --git a/board/freescale/imx8qxp_arm2/Kconfig b/board/freescale/imx8qxp_arm2/Kconfig new file mode 100644 index 00000000000..abfb895fec4 --- /dev/null +++ b/board/freescale/imx8qxp_arm2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8QXP_LPDDR4_ARM2 || TARGET_IMX8QXP_DDR3_ARM2 || TARGET_IMX8X_17X17_VAL + +config SYS_BOARD + default "imx8qxp_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qxp_arm2" + +endif diff --git a/board/freescale/imx8qxp_arm2/Makefile b/board/freescale/imx8qxp_arm2/Makefile new file mode 100644 index 00000000000..62348c6d59c --- /dev/null +++ b/board/freescale/imx8qxp_arm2/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2017-2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qxp_arm2.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c new file mode 100644 index 00000000000..3ccf20de992 --- /dev/null +++ b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c @@ -0,0 +1,732 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pca953x.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPMI_NAND_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \ + | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#ifdef CONFIG_NAND_MXS +static iomux_cfg_t gpmi_nand_pads[] = { + SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + + /* i.MX8QXP NAND use nand_re_dqs_pins */ + SC_P_USDHC1_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + +}; + +static void setup_iomux_gpmi_nand(void) +{ + imx8_iomux_setup_multiple_pads(gpmi_nand_pads, ARRAY_SIZE(gpmi_nand_pads)); +} + +static void imx8qxp_gpmi_nand_initialize(void) +{ + int ret; +#ifdef CONFIG_SPL_BUILD + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_DMA_4_CH0, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return; + + + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_NAND, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return; +#else + struct power_domain pd; + + if (!power_domain_lookup_name("conn_dma4_ch0", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_dma4_ch0 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("conn_nand", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_nand Power up failed! (error = %d)\n", ret); + } +#endif + + init_clk_gpmi_nand(); + setup_iomux_gpmi_nand(); + mxs_dma_init(); + +} +#endif + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_ipc_t ipcHndl = 0; + sc_err_t sciErr = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + /* Power up UART0 */ + sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, 2, &rate); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Enable UART0 clock root */ + sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_0, 2, true, false); + if (sciErr != SC_ERR_NONE) + return 0; + + LPCG_AllClockOn(LPUART_0_LPCG); + + setup_iomux_uart(); + +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_NAND_MXS + imx8qxp_gpmi_nand_initialize(); +#endif +#endif + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 22) + +#ifndef CONFIG_SPL_BUILD +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, +#ifndef CONFIG_TARGET_IMX8X_17X17_VAL + {USDHC2_BASE_ADDR, 0, 4}, +#endif +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for WP */ + SC_P_USDHC1_CD_B | MUX_MODE_ALT(4) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for CD, GPIO4 IO22 */ + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + struct power_domain pd; + +#ifdef CONFIG_NAND_MXS + return 0; +#endif + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + if (!power_domain_lookup_name("conn_sdhc0", &pd)) + power_domain_on(&pd); + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + if (!power_domain_lookup_name("conn_sdhc1", &pd)) + power_domain_on(&pd); + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; /* eMMC */ + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC */ +#endif /* CONFIG_SPL_BUILD */ + +#ifdef CONFIG_FEC_MXC +#include + +static iomux_cfg_t pad_enet1[] = { + SC_P_SPDIF0_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_SPDIF0_RX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX3_RX2 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX2_RX3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_SCKR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_SCKT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_FSR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + if (0 == CONFIG_FEC_ENET_DEV) + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); + else + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1)); +} + +static void enet_device_phy_reset(void) +{ + struct gpio_desc desc_enet0; + struct gpio_desc desc_enet1; + int ret; + + ret = dm_gpio_lookup_name("gpio@18_1", &desc_enet0); + if (ret) + return; + + ret = dm_gpio_request(&desc_enet0, "enet0_reset"); + if (ret) + return; + + ret = dm_gpio_lookup_name("gpio@18_4", &desc_enet1); + if (ret) + return; + + ret = dm_gpio_request(&desc_enet1, "enet1_reset"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc_enet0, GPIOD_IS_OUT); + dm_gpio_set_value(&desc_enet0, 0); + udelay(50); + dm_gpio_set_value(&desc_enet0, 1); + + dm_gpio_set_dir_flags(&desc_enet1, GPIOD_IS_OUT); + dm_gpio_set_value(&desc_enet1, 0); + udelay(50); + dm_gpio_set_value(&desc_enet1, 1); + + /* The board has a long delay for this reset to become stable */ + mdelay(200); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + struct power_domain pd; + + printf("[%s] %d\n", __func__, __LINE__); + + if (CONFIG_FEC_ENET_DEV) { + if (!power_domain_lookup_name("conn_enet1", &pd)) + power_domain_on(&pd); + } else { + if (!power_domain_lookup_name("conn_enet0", &pd)) + power_domain_on(&pd); + } + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} + +int board_phy_config(struct phy_device *phydev) +{ +#ifdef CONFIG_FEC_ENABLE_MAX7322 + uint8_t value; + + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS); + + if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) { + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1)) + printf("MAX7322 write failed\n"); + } else { + printf("MAX7322 Not found\n"); + } + mdelay(1); +#endif + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + + + +static int setup_fec(int ind) +{ + /* Reset ENET PHY */ + enet_device_phy_reset(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO + +#define DEBUG_LED IMX_GPIO_NR(3, 23) +#define IOEXP_RESET IMX_GPIO_NR(0, 19) +#define BB_PWR_EN IMX_GPIO_NR(5, 9) + +static iomux_cfg_t board_gpios[] = { + SC_P_QSPI0B_SS0_B | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_MCLK_IN0 | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void board_gpio_init(void) +{ + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + gpio_request(DEBUG_LED, "debug_led"); + gpio_direction_output(DEBUG_LED, 1); + + /* enable i2c port expander assert reset line */ + gpio_request(IOEXP_RESET, "ioexp_rst"); + gpio_direction_output(IOEXP_RESET, 1); + + /* Enable base board 1.8V power */ + gpio_request(BB_PWR_EN, "bb_pwr_en"); + gpio_direction_output(BB_PWR_EN, 1); +} +#endif + +int checkboard(void) +{ +#if defined(CONFIG_TARGET_IMX8QXP_DDR3_ARM2) + puts("Board: iMX8QXP DDR3 ARM2\n"); +#elif defined(CONFIG_TARGET_IMX8X_17X17_VAL) + puts("Board: iMX8X(QXP/DX) 17x17 Validation Board\n"); +#else + puts("Board: iMX8QXP LPDDR4 ARM2\n"); +#endif + + print_bootinfo(); + + /* Note: After reloc, ipcHndl will no longer be valid. If handle + * returned by sc_ipc_open matches SC_IPC_CH, use this + * macro (valid after reloc) for subsequent SCI calls. + */ + if (gd->arch.ipc_channel_handle != SC_IPC_CH) + printf("\nSCI error! Invalid handle\n"); + + return 0; +} + +#ifdef CONFIG_FSL_HSIO + +#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT)) +static iomux_cfg_t board_pcie_pins[] = { + SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), + SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), + SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), +}; + +static void imx8qxp_hsio_initialize(void) +{ + struct power_domain pd; + int ret; + + if (!power_domain_lookup_name("hsio_pcie1", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_pcie1 Power up failed! (error = %d)\n", ret); + } + if (!power_domain_lookup_name("hsio_gpio", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_gpio Power up failed! (error = %d)\n", ret); + } + + LPCG_AllClockOn(HSIO_PCIE_X1_LPCG); + LPCG_AllClockOn(HSIO_PHY_X1_LPCG); + LPCG_AllClockOn(HSIO_PHY_X1_CRR1_LPCG); + LPCG_AllClockOn(HSIO_PCIE_X1_CRR3_LPCG); + LPCG_AllClockOn(HSIO_MISC_LPCG); + LPCG_AllClockOn(HSIO_GPIO_LPCG); + + imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins)); +} + +void pci_init_board(void) +{ + imx8qxp_hsio_initialize(); + + /* test the 1 lane mode of the PCIe A controller */ + mx8qxp_pcie_init(); +} + +#endif + +#if defined(CONFIG_USB_CDNS3_GADGET) + +static struct cdns3_device cdns3_device_data = { + .none_core_base = 0x5B110000, + .xhci_base = 0x5B130000, + .dev_base = 0x5B140000, + .phy_base = 0x5B160000, + .otg_base = 0x5B120000, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 1, +}; + +int usb_gadget_handle_interrupts(void) +{ + cdns3_uboot_handle_interrupt(1); + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_DEVICE) { + struct power_domain pd; + int ret; + + /* Power on usb */ + if (!power_domain_lookup_name("conn_usb2", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_usb2 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("conn_usb2_phy", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_usb2_phy Power up failed! (error = %d)\n", ret); + } + + ret = cdns3_uboot_init(&cdns3_device_data); + printf("%d cdns3_uboot_initmode %d\n", index, ret); + } + } + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_DEVICE) { + struct power_domain pd; + int ret; + + cdns3_uboot_exit(1); + + /* Power off usb */ + if (!power_domain_lookup_name("conn_usb2", &pd)) { + ret = power_domain_off(&pd); + if (ret) + printf("conn_usb2 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("conn_usb2_phy", &pd)) { + ret = power_domain_off(&pd); + if (ret) + printf("conn_usb2_phy Power up failed! (error = %d)\n", ret); + } + } + } + return ret; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_NAND_MXS + imx8qxp_gpmi_nand_initialize(); +#endif + + return 0; +} + +void board_quiesce_devices() +{ + const char *power_on_devices[] = { + "dma_lpuart0", + + /* HIFI DSP boot */ + "audio_sai0", + "audio_ocram", + }; + + power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + puts("SCI reboot request"); + sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD); + while (1) + putc('.'); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "ARM2"); + env_set("board_rev", "iMX8QXP"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +#if defined(CONFIG_VIDEO_IMXDPUV1) +static void enable_lvds(struct display_info_t const *dev) +{ + display_controller_setup((PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_soc_setup(dev->bus, (PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_configure(dev->bus); + lvds2hdmi_setup(13); +} + +struct display_info_t const displays[] = {{ + .bus = 0, /* LVDS0 */ + .addr = 0, /* LVDS0 */ + .pixfmt = IMXDPUV1_PIX_FMT_BGRA32, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "IT6263", /* 720P60 */ + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 13468, /* 74250000 */ + .left_margin = 110, + .right_margin = 220, + .upper_margin = 5, + .lower_margin = 20, + .hsync_len = 40, + .vsync_len = 5, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +#endif /* CONFIG_VIDEO_IMXDPUV1 */ diff --git a/board/freescale/imx8qxp_arm2/spl.c b/board/freescale/imx8qxp_arm2/spl.c new file mode 100644 index 00000000000..e9cb7eb532f --- /dev/null +++ b/board/freescale/imx8qxp_arm2/spl.c @@ -0,0 +1,227 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pca953x.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPMI_NAND_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \ + | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 22) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, +#ifndef CONFIG_TARGET_IMX8X_17X17_VAL + {USDHC2_BASE_ADDR, 0, 4}, +#endif +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for WP */ + SC_P_USDHC1_CD_B | MUX_MODE_ALT(4) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for CD, GPIO4 IO22 */ + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +void spl_dram_init(void) +{ + /* do nothing for now */ +} + + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + sc_ipc_t ipcHndl = 0; + +#ifdef CONFIG_NAND_MXS + return 0; +#endif + ipcHndl = gd->arch.ipc_channel_handle; + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_0, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_1, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_GPIO_4, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; /* eMMC */ + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC */ + +void spl_board_init(void) +{ +#if defined(CONFIG_QSPI_BOOT) + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) { + puts("Warning: failed to initialize FSPI0\n"); + } +#endif + /* DDR initialization */ + spl_dram_init(); + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ +#if defined(CONFIG_QSPI_BOOT) + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) { + puts("Warning: failed to turn off FSPI0\n"); + } +#endif +} + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} + diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig new file mode 100644 index 00000000000..b67300d816c --- /dev/null +++ b/board/freescale/imx8qxp_mek/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8QXP_MEK + +config SYS_BOARD + default "imx8qxp_mek" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qxp_mek" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8qxp_mek/Makefile b/board/freescale/imx8qxp_mek/Makefile new file mode 100644 index 00000000000..987f97496f2 --- /dev/null +++ b/board/freescale/imx8qxp_mek/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qxp_mek.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c new file mode 100644 index 00000000000..89f99ea2867 --- /dev/null +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -0,0 +1,730 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pca953x.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_ipc_t ipcHndl = 0; + sc_err_t sciErr = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + /* Power up UART0 */ + sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, 2, &rate); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Enable UART0 clock root */ + sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_0, 2, true, false); + if (sciErr != SC_ERR_NONE) + return 0; + + LPCG_AllClockOn(LPUART_0_LPCG); + + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 22) + +#ifndef CONFIG_SPL_BUILD +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for WP */ + SC_P_USDHC1_CD_B | MUX_MODE_ALT(4) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for CD, GPIO4 IO22 */ + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + struct power_domain pd; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + if (!power_domain_lookup_name("conn_sdhc0", &pd)) + power_domain_on(&pd); + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + if (!power_domain_lookup_name("conn_sdhc1", &pd)) + power_domain_on(&pd); + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; /* eMMC */ + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_FSL_ESDHC */ + + +#ifdef CONFIG_FEC_MXC +#include + +static iomux_cfg_t pad_enet1[] = { + SC_P_SPDIF0_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_SPDIF0_RX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX3_RX2 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX2_RX3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_SCKR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_SCKT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_FSR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + if (0 == CONFIG_FEC_ENET_DEV) + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); + else + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1)); +} + +static void enet_device_phy_reset(void) +{ + struct gpio_desc desc; + int ret; + + /* The BB_PER_RST_B will reset the ENET1 PHY */ + if (0 == CONFIG_FEC_ENET_DEV) { + ret = dm_gpio_lookup_name("gpio@1a_4", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "enet0_reset"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + udelay(50); + dm_gpio_set_value(&desc, 1); + } + + /* The board has a long delay for this reset to become stable */ + mdelay(200); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + struct power_domain pd; + + printf("[%s] %d\n", __func__, __LINE__); + + if (CONFIG_FEC_ENET_DEV) { + if (!power_domain_lookup_name("conn_enet1", &pd)) + power_domain_on(&pd); + } else { + if (!power_domain_lookup_name("conn_enet0", &pd)) + power_domain_on(&pd); + } + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +static int setup_fec(int ind) +{ + /* Reset ENET PHY */ + enet_device_phy_reset(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO +static void board_gpio_init(void) +{ + int ret; + struct gpio_desc desc; + + ret = dm_gpio_lookup_name("gpio@1a_3", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "bb_per_rst_b"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + udelay(50); + dm_gpio_set_value(&desc, 1); +} +#endif + +int checkboard(void) +{ + puts("Board: iMX8QXP MEK\n"); + + print_bootinfo(); + + /* Note: After reloc, ipcHndl will no longer be valid. If handle + * returned by sc_ipc_open matches SC_IPC_CH, use this + * macro (valid after reloc) for subsequent SCI calls. + */ + if (gd->arch.ipc_channel_handle != SC_IPC_CH) + printf("\nSCI error! Invalid handle\n"); + + return 0; +} + +#ifdef CONFIG_FSL_HSIO + +#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT)) +static iomux_cfg_t board_pcie_pins[] = { + SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), + SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), + SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), +}; + +static void imx8qxp_hsio_initialize(void) +{ + struct power_domain pd; + int ret; + + if (!power_domain_lookup_name("hsio_pcie1", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_pcie1 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("hsio_gpio", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_gpio Power up failed! (error = %d)\n", ret); + } + + LPCG_AllClockOn(HSIO_PCIE_X1_LPCG); + LPCG_AllClockOn(HSIO_PHY_X1_LPCG); + LPCG_AllClockOn(HSIO_PHY_X1_CRR1_LPCG); + LPCG_AllClockOn(HSIO_PCIE_X1_CRR3_LPCG); + LPCG_AllClockOn(HSIO_MISC_LPCG); + LPCG_AllClockOn(HSIO_GPIO_LPCG); + + imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins)); +} + +void pci_init_board(void) +{ + imx8qxp_hsio_initialize(); + + /* test the 1 lane mode of the PCIe A controller */ + mx8qxp_pcie_init(); +} + +#endif + +#ifdef CONFIG_USB + +#ifdef CONFIG_USB_TCPC +#define USB_TYPEC_SEL IMX_GPIO_NR(5, 9) +static iomux_cfg_t ss_mux_gpio[] = { + SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +struct tcpc_port port; +struct tcpc_port_config port_config = { + .i2c_bus = 1, + .addr = 0x50, + .port_type = TYPEC_PORT_DFP, +}; + +void ss_mux_select(enum typec_cc_polarity pol) +{ + if (pol == TYPEC_POLARITY_CC1) + gpio_direction_output(USB_TYPEC_SEL, 0); + else + gpio_direction_output(USB_TYPEC_SEL, 1); +} + +static void setup_typec(void) +{ + int ret; + struct gpio_desc typec_en_desc; + + imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); + gpio_request(USB_TYPEC_SEL, "typec_sel"); + + ret = dm_gpio_lookup_name("gpio@1a_7", &typec_en_desc); + if (ret) { + printf("%s lookup gpio@1a_7 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&typec_en_desc, "typec_en"); + if (ret) { + printf("%s request typec_en failed ret = %d\n", __func__, ret); + return; + } + + /* Enable SS MUX */ + dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + tcpc_init(&port, port_config, &ss_mux_select); +} +#endif + +#ifdef CONFIG_USB_CDNS3_GADGET +static struct cdns3_device cdns3_device_data = { + .none_core_base = 0x5B110000, + .xhci_base = 0x5B130000, + .dev_base = 0x5B140000, + .phy_base = 0x5B160000, + .otg_base = 0x5B120000, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 1, +}; + +int usb_gadget_handle_interrupts(int index) +{ + cdns3_uboot_handle_interrupt(index); + return 0; +} +#endif + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_dfp_mode(&port); +#endif +#ifdef CONFIG_USB_CDNS3_GADGET + } else { +#ifdef CONFIG_SPL_BUILD + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + printf("conn_usb2 Power up failed! (error = %d)\n", ret); + + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2_PHY, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + printf("conn_usb2_phy Power up failed! (error = %d)\n", ret); +#else + struct power_domain pd; + int ret; + + /* Power on usb */ + if (!power_domain_lookup_name("conn_usb2", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_usb2 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("conn_usb2_phy", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_usb2_phy Power up failed! (error = %d)\n", ret); + } +#endif + +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_ufp_mode(&port); + printf("%d setufp mode %d\n", index, ret); +#endif + + ret = cdns3_uboot_init(&cdns3_device_data); + printf("%d cdns3_uboot_initmode %d\n", index, ret); +#endif + } + } + + return ret; + +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_disable_src_vbus(&port); +#endif +#ifdef CONFIG_USB_CDNS3_GADGET + } else { + cdns3_uboot_exit(1); + +#ifdef CONFIG_SPL_BUILD + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2, SC_PM_PW_MODE_OFF); + if (ret != SC_ERR_NONE) + printf("conn_usb2 Power down failed! (error = %d)\n", ret); + + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2_PHY, SC_PM_PW_MODE_OFF); + if (ret != SC_ERR_NONE) + printf("conn_usb2_phy Power down failed! (error = %d)\n", ret); +#else + struct power_domain pd; + int ret; + + /* Power off usb */ + if (!power_domain_lookup_name("conn_usb2", &pd)) { + ret = power_domain_off(&pd); + if (ret) + printf("conn_usb2 Power down failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("conn_usb2_phy", &pd)) { + ret = power_domain_off(&pd); + if (ret) + printf("conn_usb2_phy Power down failed! (error = %d)\n", ret); + } +#endif +#endif + } + } + + return ret; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC) + setup_typec(); +#endif + + return 0; +} + +void board_quiesce_devices() +{ + const char *power_on_devices[] = { + "dma_lpuart0", + + /* HIFI DSP boot */ + "audio_sai0", + "audio_ocram", + }; + + power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + puts("SCI reboot request"); + sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD); + while (1) + putc('.'); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + char *fdt_file; + bool m4_boot; + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "MEK"); + env_set("board_rev", "iMX8QXP"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + fdt_file = env_get("fdt_file"); + m4_boot = check_m4_parts_boot(); + + if (fdt_file && !strcmp(fdt_file, "undefined")) { + if (m4_boot) + env_set("fdt_file", "fsl-imx8qxp-mek-rpmsg.dtb"); + else + env_set("fdt_file", "fsl-imx8qxp-mek.dtb"); + } + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +#if defined(CONFIG_VIDEO_IMXDPUV1) +static void enable_lvds(struct display_info_t const *dev) +{ + struct gpio_desc desc; + int ret; + + /* MIPI_DSI0_EN on IOEXP 0x1a port 6, MIPI_DSI1_EN on IOEXP 0x1d port 7 */ + ret = dm_gpio_lookup_name("gpio@1a_6", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "lvds0_en"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + display_controller_setup((PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_soc_setup(dev->bus, (PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_configure(dev->bus); + lvds2hdmi_setup(13); +} + +struct display_info_t const displays[] = {{ + .bus = 0, /* LVDS0 */ + .addr = 0, /* LVDS0 */ + .pixfmt = IMXDPUV1_PIX_FMT_BGRA32, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "IT6263", /* 720P60 */ + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 13468, /* 74250000 */ + .left_margin = 110, + .right_margin = 220, + .upper_margin = 5, + .lower_margin = 20, + .hsync_len = 40, + .vsync_len = 5, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +#endif /* CONFIG_VIDEO_IMXDPUV1 */ diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c new file mode 100644 index 00000000000..a8c88299728 --- /dev/null +++ b/board/freescale/imx8qxp_mek/spl.c @@ -0,0 +1,234 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pca953x.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT)) + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 22) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for WP */ + SC_P_USDHC1_CD_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for CD, GPIO4 IO22 */ + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +void spl_dram_init(void) +{ + /* do nothing for now */ +} + +int board_mmc_init(bd_t *bis) +{ + + int i, ret; + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_0, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_1, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_GPIO_4, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; /* eMMC */ + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +#endif + +void spl_board_init(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + if (sc_rm_is_resource_owned(ipcHndl, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) { + puts("Warning: failed to initialize FSPI0\n"); + } + } +#endif + /* DDR initialization */ + spl_dram_init(); + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + sc_ipc_t ipcHndl = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + if (sc_rm_is_resource_owned(ipcHndl, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) { + puts("Warning: failed to turn off FSPI0\n"); + } + } +#endif +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} + diff --git a/board/freescale/multa-imx7d/Kconfig b/board/freescale/multa-imx7d/Kconfig new file mode 100644 index 00000000000..38beb240000 --- /dev/null +++ b/board/freescale/multa-imx7d/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MULTA_IMX7D + +config SYS_BOARD + default "multa-imx7d" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "multa-imx7d" + +endif diff --git a/board/freescale/multa-imx7d/MAINTAINERS b/board/freescale/multa-imx7d/MAINTAINERS new file mode 100644 index 00000000000..d98beceba2f --- /dev/null +++ b/board/freescale/multa-imx7d/MAINTAINERS @@ -0,0 +1,6 @@ +MULTA IMX7D BOARD +M: Fang Hui +S: Maintained +F: board/freescale/multa-imx7d +F: include/configs/multa-imx7d.h +F: configs/multa-imx7d_defconfig diff --git a/board/freescale/multa-imx7d/Makefile b/board/freescale/multa-imx7d/Makefile new file mode 100644 index 00000000000..8fc7c67e80e --- /dev/null +++ b/board/freescale/multa-imx7d/Makefile @@ -0,0 +1,6 @@ +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := multa-imx7d.o diff --git a/board/freescale/multa-imx7d/imximage.cfg b/board/freescale/multa-imx7d/imximage.cfg new file mode 100644 index 00000000000..ec1226d663d --- /dev/null +++ b/board/freescale/multa-imx7d/imximage.cfg @@ -0,0 +1,116 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/multa-imx7d/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000b24 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/multa-imx7d/multa-imx7d.c b/board/freescale/multa-imx7d/multa-imx7d.c new file mode 100644 index 00000000000..400e83683fe --- /dev/null +++ b/board/freescale/multa-imx7d/multa-imx7d.c @@ -0,0 +1,1013 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include +#include +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#include + +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ + +DECLARE_GLOBAL_DATA_PTR; + +#define PHY_NRESET_GPIO IMX_GPIO_NR(4, 22) + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) + +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) + +#define EPDC_PAD_CTRL 0x0 + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C4 */ +struct i2c_pads_info i2c_pad_info4 = { + .scl = { + .i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(7, 8), + }, + .sda = { + .i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(7, 9), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#define IOX_SDI IMX_GPIO_NR(1, 9) +#define IOX_STCP IMX_GPIO_NR(1, 12) +#define IOX_SHCP IMX_GPIO_NR(1, 13) + +static iomux_v3_cfg_t const iox_pads[] = { + /* IOX_SDI */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_STCP */ + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_SHCP */ + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* + * PCIE_DIS_B --> Q0 + * PCIE_RST_B --> Q1 + * HDMI_RST_B --> Q2 + * PERI_RST_B --> Q3 + * SENSOR_RST_B --> Q4 + * ENET_RST_B --> Q5 + * PERI_3V3_EN --> Q6 + * LCD_PWR_EN --> Q7 + */ +enum qn { + PCIE_DIS_B, + PCIE_RST_B, + HDMI_RST_B, + PERI_RST_B, + SENSOR_RST_B, + ENET_RST_B, + PERI_3V3_EN, + LCD_PWR_EN, +}; + +enum qn_func { + qn_reset, + qn_enable, + qn_disable, +}; + +enum qn_level { + qn_low = 0, + qn_high = 1, +}; + +static enum qn_level seq[3][2] = { + {0, 1}, {1, 1}, {0, 0} +}; + +static enum qn_func qn_output[8] = { + qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, + qn_disable +}; + +static void iox74lv_init(void) +{ + int i; + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); +}; + +void iox74lv_set(int index) +{ + int i; + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + + if (i == index) + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); + else + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); +}; + +#define BOARD_REV_C 0x300 +#define BOARD_REV_B 0x200 +#define BOARD_REV_A 0x100 + +static int mx7sabre_rev(void) +{ + /* + * Get Board ID information from OCOTP_GP1[15:8] + * i.MX7D SDB RevA: 0x41 + * i.MX7D SDB RevB: 0x42 + */ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[14]; + int reg = readl(&bank->fuse_regs[0]); + int ret; + + if (reg != 0) { + switch (reg >> 8 & 0x0F) { + case 0x3: + ret = BOARD_REV_C; + break; + case 0x02: + ret = BOARD_REV_B; + break; + case 0x01: + default: + ret = BOARD_REV_A; + break; + } + } else { + /* If the gp1 fuse is not burn, we have to use TO rev for the board rev */ + if (is_soc_rev(CHIP_REV_1_0)) + ret = BOARD_REV_A; + else if (is_soc_rev(CHIP_REV_1_1)) + ret = BOARD_REV_B; + else + ret = BOARD_REV_C; + } + + return ret; +} + +u32 get_board_rev(void) +{ + int rev = mx7sabre_rev(); + + return (get_cpu_rev() & ~(0xF << 8)) | rev; +} + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + /* NAND_USDHC_BUS_CLK is set in rom */ + set_clk_nand(); +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_EPDC_BDR1__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwm_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); + + /* Reset LCD */ + gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = ELCDIF1_IPS_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "TFT43AB", + .xres = 480, + .yres = 272, + .pixclock = 108695, + .left_margin = 8, + .right_margin = 4, + .upper_margin = 2, + .lower_margin = 4, + .hsync_len = 41, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) +#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_get_env_dev(int devno) +{ + if (devno == 2) + devno--; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + if (dev_no == 1) + dev_no++; + + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = 1; /* Assume uSDHC3 emmc is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc2 USDHC3 (eMMC) + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); + gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); + gpio_direction_output(USDHC3_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif + +iomux_v3_cfg_t const fec2_en_pads[] = { + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#ifdef CONFIG_FEC_MXC +/* Currently incompleted since on the demo client fec1 is not used */ +static const iomux_v3_cfg_t fec1_pads[] = { + MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, + MX7D_PAD_LCD_DATA15__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static const iomux_v3_cfg_t fec2_pads[] = { + MX7D_PAD_GPIO1_IO14__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_GPIO1_IO15__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + + MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, + + /* NRES_ETH pin */ + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + if (fec_id == 0) { + /* FEC1 */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), + (IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK)); + } else if (fec_id == 1) { + /* FEC2 */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), + (IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK)); + } else { + return -EINVAL; + } + + ret = set_clk_enet(ENET_50MHZ); + if (ret) { + printf("%s: set_clk_enet() failed\n", __func__); + return ret; + } + + return 0; +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* Reset the PHY */ + gpio_direction_output(PHY_NRESET_GPIO, 0); + mdelay(5); + gpio_set_value(PHY_NRESET_GPIO, 1); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_FSL_QSPI +static iomux_v3_cfg_t const quadspi_pads[] = { + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, + ARRAY_SIZE(quadspi_pads)); + + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX7D_PAD_EPDC_DATA00__GPIO2_IO0, + MX7D_PAD_EPDC_DATA01__GPIO2_IO1, + MX7D_PAD_EPDC_DATA02__GPIO2_IO2, + MX7D_PAD_EPDC_DATA03__GPIO2_IO3, + MX7D_PAD_EPDC_DATA04__GPIO2_IO4, + MX7D_PAD_EPDC_DATA05__GPIO2_IO5, + MX7D_PAD_EPDC_DATA06__GPIO2_IO6, + MX7D_PAD_EPDC_DATA07__GPIO2_IO7, + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16, + MX7D_PAD_EPDC_SDLE__GPIO2_IO17, + MX7D_PAD_EPDC_SDOE__GPIO2_IO18, + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19, + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20, + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21, + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24, + MX7D_PAD_EPDC_GDOE__GPIO2_IO25, + MX7D_PAD_EPDC_GDRL__GPIO2_IO26, + MX7D_PAD_EPDC_GDSP__GPIO2_IO27, + MX7D_PAD_EPDC_BDR0__GPIO2_IO28, + MX7D_PAD_EPDC_BDR1__GPIO2_IO29, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0); + + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + gpio_direction_input(IMX_GPIO_NR(2, 31)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_direction_output(IMX_GPIO_NR(4, 14), 1); + + /* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_direction_output(IMX_GPIO_NR(2, 23), 1); + + /* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_direction_output(IMX_GPIO_NR(2, 30), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + /*** epdc Maxim PMIC settings ***/ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 30), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 23), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 31))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 23), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 30), 0); +} +#endif + +#ifdef CONFIG_USB_EHCI_MX7 +static iomux_v3_cfg_t const usb_otg1_pads[] = { + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usb_otg2_pads[] = { + MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* On RevB board, the GPIO_IO07 is muxed for OTG2 PWR */ +iomux_v3_cfg_t const usb_otg2_revB_pads[] = { + MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, + ARRAY_SIZE(usb_otg1_pads)); + + if (mx7sabre_rev() >= BOARD_REV_B) + imx_iomux_v3_setup_multiple_pads(usb_otg2_revB_pads, + ARRAY_SIZE(usb_otg2_revB_pads)); + else + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, + ARRAY_SIZE(usb_otg2_pads)); +} + +extern int usb_phy_mode(int port); +int board_usb_phy_mode(int port) +{ + if (port == 0) + return usb_phy_mode(port); + else + return USB_INIT_HOST; +} + +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); +#endif + +#ifdef CONFIG_USB_EHCI_MX7 + setup_usb(); +#endif + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); + + iox74lv_init(); + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_MXC_EPDC + if (mx7sabre_rev() >= BOARD_REV_B) { + /* On RevB, GPIO1_IO04 is used for ENET2 EN, + * so set its output to high to isolate the ENET2 signals for EPDC + */ + imx_iomux_v3_setup_multiple_pads(fec2_en_pads, + ARRAY_SIZE(fec2_en_pads)); + gpio_direction_output(IMX_GPIO_NR(1, 4), 1); + } else { + qn_output[5] = qn_disable; + iox74lv_set(5); + } + setup_epdc(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, + /* TODO: Nand */ + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + i2c_set_bus_num(3); + + axp_init(); + /* Disable LDO0 and ALDO2 */ + axp_disable_ldo0(); + axp_set_power_output(0xFB); + mdelay(20); + + axp_set_ldo0(AXP152_LDO0_3V3, AXP152_LDO0_CURR_1500MA); + axp_set_aldo2(AXP152_ALDO_3V3); + + axp_set_dcdc3(1350); + axp_set_power_output(0xFF); + + return 0; +} +#endif + +int board_late_init(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + return 0; +} + +int checkboard(void) +{ + printf("Board: multa imx7d\n"); + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +/* Use S3 button for recovery key */ +#define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10) +iomux_v3_cfg_t const recovery_key_pads[] = { + (MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)), +}; + +int is_recovery_key_pressing(void) +{ + int button_pressed = 0; + + /* Check Recovery Combo Button press or not. */ + imx_iomux_v3_setup_multiple_pads(recovery_key_pads, + ARRAY_SIZE(recovery_key_pads)); + + gpio_direction_input(GPIO_VOL_DN_KEY); + + if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return button_pressed; +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/freescale/multa-imx7d/plugin.S b/board/freescale/multa-imx7d/plugin.S new file mode 100644 index 00000000000..d500d63615d --- /dev/null +++ b/board/freescale/multa-imx7d/plugin.S @@ -0,0 +1,227 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x18181818 + str r1, [r0, #0x7c] + ldr r1, =0x18181818 + str r1, [r0, #0x80] + ldr r1, =0x40401818 + str r1, [r0, #0x84] + ldr r1, =0x00000040 + str r1, [r0, #0x88] + ldr r1, =0x40404040 + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_ddr_freq_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne FREQ_DEFAULT_533 + + /* Change to 400Mhz for TO1.1 */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x70 + ldr r2, =0x00703021 + str r2, [r0, r1] + ldr r1, =0x90 + ldr r2, =0x0 + str r2, [r0, r1] + ldr r1, =0x70 + ldr r2, =0x00603021 + str r2, [r0, r1] + + ldr r3, =0x80000000 +wait_lock: + ldr r2, [r0, r1] + and r2, r3 + cmp r2, r3 + bne wait_lock + + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x9880 + ldr r2, =0x1 + str r2, [r0, r1] + +FREQ_DEFAULT_533: +.endm + +.macro imx7d_multa_ddr_setting + imx7d_ddr_freq_setting + + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x01040001 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00400046 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00020001 + str r1, [r0, #0xd0] + ldr r1, =0x00690000 + str r1, [r0, #0xd4] + ldr r1, =0x09300004 + str r1, [r0, #0xdc] + ldr r1, =0x04080000 + str r1, [r0, #0xe0] + ldr r1, =0x00100004 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x09081109 + str r1, [r0, #0x100] + ldr r1, =0x0007020d + str r1, [r0, #0x104] + ldr r1, =0x03040407 + str r1, [r0, #0x108] + ldr r1, =0x00002006 + str r1, [r0, #0x10c] + ldr r1, =0x04020205 + str r1, [r0, #0x110] + ldr r1, =0x03030202 + str r1, [r0, #0x114] + ldr r1, =0x00000803 + str r1, [r0, #0x120] + ldr r1, =0x00800020 + str r1, [r0, #0x180] + ldr r1, =0x02000100 + str r1, [r0, #0x184] + ldr r1, =0x02098204 + str r1, [r0, #0x190] + ldr r1, =0x00030303 + str r1, [r0, #0x194] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00080808 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 + str r1, [r0, #0x214] + ldr r1, =0x0f070707 + str r1, [r0, #0x218] + + ldr r1, =0x06000604 + str r1, [r0, #0x240] + ldr r1, =0x00000001 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17420f40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00060807 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + imx7d_ddrphy_latency_setting + ldr r1, =0x08080808 + str r1, [r0, #0x20] + ldr r1, =0x08080808 + str r1, [r0, #0x30] + ldr r1, =0x01000010 + str r1, [r0, #0x50] + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_multa_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6qarm2/Kconfig b/board/freescale/mx6qarm2/Kconfig index 8ab8b460f92..6d2c75151c0 100644 --- a/board/freescale/mx6qarm2/Kconfig +++ b/board/freescale/mx6qarm2/Kconfig @@ -1,4 +1,4 @@ -if TARGET_MX6QARM2 +if TARGET_MX6QARM2 || TARGET_MX6DLARM2 config SYS_BOARD default "mx6qarm2" @@ -9,4 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6qarm2" +config SYS_TEXT_BASE + default 0x17800000 + +config MX6DQ_POP_LPDDR2 + bool "Select this if it is a MX6Q POP LPDDR2 board" + endif diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index c85bde510e0..957156f08e9 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. * Jason Liu * * SPDX-License-Identifier: GPL-2.0+ @@ -10,6 +10,9 @@ * The syntax is taken as close as possible with the kwbimage */ +#define __ASSEMBLY__ +#include + /* image version */ IMAGE_VERSION 2 @@ -19,6 +22,15 @@ IMAGE_VERSION 2 */ BOOT_FROM sd +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + /* * Device Configuration Data (DCD) * @@ -30,8 +42,179 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ -#ifdef CONFIG_MX6DQ_LPDDR2 +#ifdef CONFIG_MX6DQ_POP_LPDDR2 + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* DCD */ +DATA 4 0x020e0798 0x00080000 +DATA 4 0x020e0758 0x00000000 + +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 + +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 + +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 + +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00003030 +DATA 4 0x020e05b0 0x00003030 +DATA 4 0x020e0524 0x00003030 +DATA 4 0x020e051c 0x00003030 +DATA 4 0x020e0518 0x00003030 +DATA 4 0x020e050c 0x00003030 +DATA 4 0x020e05b8 0x00003030 +DATA 4 0x020e05c0 0x00003030 + +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 + +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b401c 0x00008000 + +DATA 4 0x021b085c 0x1B5F0107 +DATA 4 0x021b485c 0x1B5F0107 + +DATA 4 0x021b0800 0xA1390003 + +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b4890 0x00400000 + +DATA 4 0x021b0848 0x3C3A3A44 +DATA 4 0x021b4848 0x3C3A3A44 + +DATA 4 0x021b0850 0x4238423A +DATA 4 0x021b4850 0x4238423A + +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b483c 0x20000000 +DATA 4 0x021b4840 0x00000000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b482c 0xf3333333 +DATA 4 0x021b4830 0xf3333333 +DATA 4 0x021b4834 0xf3333333 +DATA 4 0x021b4838 0xf3333333 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b000c 0x444961A5 +DATA 4 0x021b0010 0x00160E83 +DATA 4 0x021b0014 0x000000DD + +DATA 4 0x021b0018 0x0000174C +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x149F26D2 +DATA 4 0x021b0030 0x00000010 +DATA 4 0x021b0038 0x0021099B +DATA 4 0x021b0040 0x0000004F +DATA 4 0x021b0400 0x11420000 +DATA 4 0x021b0000 0x83110000 + +DATA 4 0x021b4004 0x00020036 +DATA 4 0x021b4008 0x00000000 +DATA 4 0x021b400c 0x444961A5 +DATA 4 0x021b4010 0x00160E83 +DATA 4 0x021b4014 0x000000DD + +DATA 4 0x021b4018 0x0000174C +DATA 4 0x021b401c 0x00008000 +DATA 4 0x021b402c 0x149F26D2 +DATA 4 0x021b4030 0x00000010 +DATA 4 0x021b4038 0x0021099B +DATA 4 0x021b4040 0x00000017 +DATA 4 0x021b4400 0x11420000 +DATA 4 0x021b4000 0x83110000 + +DATA 4 0x021b001c 0x003F8030 +DATA 4 0x021b001c 0xFF0A8030 +DATA 4 0x021b001c 0xC2018030 +DATA 4 0x021b001c 0x06028030 +DATA 4 0x021b001c 0x02038030 + +DATA 4 0x021b401c 0x003F8030 +DATA 4 0x021b401c 0xFF0A8030 +DATA 4 0x021b401c 0xC2018030 +DATA 4 0x021b401c 0x06028030 +DATA 4 0x021b401c 0x02038030 + +DATA 4 0x021b0800 0xA1390003 + +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b4020 0x00001800 + +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b4818 0x00000000 + +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b4004 0x00025576 + +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b4404 0x00011006 + +DATA 4 0x021b001c 0x00000000 +DATA 4 0x021b401c 0x00000000 + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F + +#elif defined(CONFIG_MX6DQ_LPDDR2) /* DCD */ +DATA 4 0x020C4018 0x21324 +DATA 4 0x020C4014 0x2018D00 +CHECK_BITS_CLR 4 0x020C4048 0x3F +DATA 4 0x020C4018 0x61324 +DATA 4 0x020C4014 0x18D00 +CHECK_BITS_CLR 4 0x020C4048 0x3F DATA 4 0x020C4018 0x60324 DATA 4 0x020E05a8 0x00003038 @@ -336,3 +519,4 @@ DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F #endif /* CONFIG_MX6DQ_LPDDR2 */ +#endif diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg index 1f5a0a57d5e..e94918cd10e 100644 --- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg +++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * Jason Liu * * SPDX-License-Identifier: GPL-2.0+ @@ -10,6 +10,9 @@ * The syntax is taken as close as possible with the kwbimage */ +#define __ASSEMBLY__ +#include + /* image version */ IMAGE_VERSION 2 @@ -19,6 +22,15 @@ IMAGE_VERSION 2 */ BOOT_FROM sd +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + /* * Device Configuration Data (DCD) * @@ -460,3 +472,4 @@ DATA 4 0x020e0010 0xF00000CF DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F #endif /* CONFIG_MX6DL_LPDDR2 */ +#endif diff --git a/board/freescale/mx6qarm2/mt128x64mx32.cfg b/board/freescale/mx6qarm2/mt128x64mx32.cfg new file mode 100644 index 00000000000..f630188850c --- /dev/null +++ b/board/freescale/mx6qarm2/mt128x64mx32.cfg @@ -0,0 +1,301 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_MX6DQ_POP_LPDDR2 +/* set ddr to 400Mhz */ +DATA 4 0x020C4018 0x21324 +DATA 4 0x020C4014 0x2018100 +CHECK_BITS_CLR 4 0x020C4048 0x3F +DATA 4 0x020C4018 0x61324 +DATA 4 0x020C4014 0x18900 +CHECK_BITS_CLR 4 0x020C4048 0x3F +DATA 4 0x020C4018 0x60324 + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff +// Switch PL301_FAST2 to DDR dual channel mapping +//DATA 4 0x00B00000 0x1 + +//============================================================================= +/// IOMUX +//============================================================================= +//DDR IO TYPE: +DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE +DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE + +//CLOCK: +DATA 4 0x020e0588 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 +DATA 4 0x020e0594 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 + +//Control: +DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS +DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS +DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET +DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS +DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 +DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 +DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS +DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS + +//Data Strobes: +DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL +DATA 4 0x020e05a8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 +DATA 4 0x020e05b0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 +DATA 4 0x020e0524 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 +DATA 4 0x020e051c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 +DATA 4 0x020e0518 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 +DATA 4 0x020e050c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 +DATA 4 0x020e05b8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 +DATA 4 0x020e05c0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 + +//Data: +DATA 4 0x020e0798 0x00080000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE +DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS +DATA 4 0x020e0788 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS +DATA 4 0x020e0794 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS +DATA 4 0x020e079c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS +DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS +DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS +DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS +DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS + +DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 +DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 +DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 +DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 +DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 +DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 +DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 +DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 + +//============================================================================= +// DDR Controller Registers +//============================================================================= +// Manufacturer: Micron - POP Package +// Device Part Number: MT42L128M64D2LL-25WT +// Clock Freq.: 400MHz +// Density per CS in Gb: 4 +// Chip Selects used: 1 +// Number of channels 2 +// Density per channel (Gb) 4 +// Total DRAM density (Gb) 8 +// Number of Banks: 8 +// Row address: 14 +// Column address: 10 +// Data bus width 32 +//============================================================================= + +// MMDC0_MDSCR, set the Configuration request bit during MMDC set up +DATA 4 0x021b001c 0x00008000 // Chan 0 +DATA 4 0x021b401c 0x00008000 // Chan 1 +// Adjust ZQ delay for MMDC clock frequency at 400MHz +DATA 4 0x021b085c 0x1b4700c7 //LPDDR2 ZQ params +DATA 4 0x021b485c 0x1b4700c7 //LPDDR2 ZQ params + +//============================================================================= +// Calibration setup. +// +//============================================================================= +DATA 4 0x021b0800 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable one time ZQ calibration +DATA 4 0x021b4800 0xa1380003 // DDR_PHY_P1_MPZQHWCTRL + +DATA 4 0x021b0890 0x00400000 //ca bus abs delay +DATA 4 0x021b4890 0x00400000 //ca bus abs delay + +//DATA 4 0x021b48bc0x00055555 // DDR_PHY_P1_MPWRCADL + +DATA 4 0x021b08b8 0x00000800 //frc_msr. +DATA 4 0x021b48b8 0x00000800 //frc_msr. + +// read delays, settings recommended by design to remain constant +DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3 +DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3 +DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3 +DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3 +DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3 +DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3 +DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3 +DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3 + +// write delays, settings recommended by design to remain constant +DATA 4 0x021b082c 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b0830 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b0834 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b0838 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b482c 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 +DATA 4 0x021b4830 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 +DATA 4 0x021b4834 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 +DATA 4 0x021b4838 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 + +DATA 4 0x021b0848 0x36383644 // MPRDDLCTL PHY0 +DATA 4 0x021b4848 0x3a383846 // MPRDDLCTL PHY1 + +DATA 4 0x021b0850 0x38343E34 // MPWRDLCTL PHY0 +DATA 4 0x021b4850 0x48384A44 // MPWRDLCTL PHY1 + +DATA 4 0x021b083c 0x20000000 //PHY0 dqs gating dis +DATA 4 0x021b0840 0x0 +DATA 4 0x021b483c 0x20000000 //PHY0 dqs gating dis +DATA 4 0x021b4840 0x0 + +//For i.mx6qd parts of versions C and later (v1.2, v1.3). +DATA 4 0x021b08c0 0x24921492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 +DATA 4 0x021b48c0 0x24921492 + +DATA 4 0x021b08b8 0x00000800 //frc_msr. +DATA 4 0x021b48b8 0x00000800 //frc_msr. +//============================================================================= +// Calibration setup end +//============================================================================= + +// Channel0 - starting address 0x80000000 +DATA 4 0x021b000c 0x33374133 // MMDC0_MDCFG0 +DATA 4 0x021b0004 0x00020024 // MMDC0_MDPDC +DATA 4 0x021b0010 0x00100A82 // MMDC0_MDCFG1 +DATA 4 0x021b0014 0x00000093 // MMDC0_MDCFG2 + +//MDMISC: RALAT kept to the high level of 5. +//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: +//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 +//b. Small performence improvment +DATA 4 0x021b0018 0x0000174C // MMDC0_MDMISC +DATA 4 0x021b002c 0x0F9F26D2 // MMDC0_MDRWD +DATA 4 0x021b0030 0x009F0E10 // MMDC0_MDOR +DATA 4 0x021b0038 0x001A0889 // MMDC0_MDCFG3LP +DATA 4 0x021b0008 0x00000000 // MMDC0_MDOTC +DATA 4 0x021b0040 0x0000004F // Chan0 CS0_END 2 channel with 2 Channel fixed mode +// DATA 4 0x021b0400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled +DATA 4 0x021b0000 0x83110000 // MMDC0_MDCTL + +// Channel1 - starting address 0x10000000 +// Note: the values for Chan1 should match those of Chan0 +DATA 4 0x021b400c 0x33374133 // MMDC1_MDCFG0 +DATA 4 0x021b4004 0x00020024 // MMDC1_MDPDC +DATA 4 0x021b4010 0x00100A82 // MMDC1_MDCFG1 +DATA 4 0x021b4014 0x00000093 // MMDC1_MDCFG2 +DATA 4 0x021b4018 0x0000174C // MMDC1_MDMISC +DATA 4 0x021b402c 0x0F9F26D2 // MMDC1_MDRWD +DATA 4 0x021b4030 0x009F0E10 // MMDC1_MDOR +DATA 4 0x021b4038 0x001A0889 // MMDC1_MDCFG3LP +DATA 4 0x021b4008 0x00000000 // MMDC1_MDOTC +DATA 4 0x021b4040 0x00000017 // Chan1 CS0_END +// DATA 4 0x021b4400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled +DATA 4 0x021b4000 0x83110000 // MMDC1_MDCTL + +// Precharge all commands per JEDEC +// The memory controller may optionally issue a Precharge-All command +// prior to the MRW Reset command. +// This is strongly recommended to ensure a robust DRAM initialization +DATA 4 0x021b001c 0x00008010 // precharge-all commnad CS0 - Chan 0 +DATA 4 0x021b401c 0x00008010 // precharge-all commnad CS0 - Chan 1 + +//============================================================================= +// LPDDR2 Mode Register Writes +//============================================================================= +// Channel 0 CS0 +DATA 4 0x021b001c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset) +DATA 4 0x021b001c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +DATA 4 0x021b001c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration +DATA 4 0x021b001c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration +DATA 4 0x021b001c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration +// Channel 0 CS1 +// Note, CS1 does not exist in this memory hence these writes are commented out +// They are only shown here for completeness +// If you use a memory where CS1 exists, simply uncomment these lines +//DATA 4 0x021b001c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset) +//DATA 4 0x021b001c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +//DATA 4 0x021b001c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration +//DATA 4 0x021b001c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration +//DATA 4 0x021b001c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration + +// For Channel 1 mode register writes - these should match channel 0 settings +// Channel 1 CS0 +DATA 4 0x021b401c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset) +DATA 4 0x021b401c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +DATA 4 0x021b401c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration +DATA 4 0x021b401c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration +DATA 4 0x021b401c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration +// Channel 1 CS1 +// Note, CS1 does not exist in this memory hence these writes are commented out +// They are only shown here for completeness +// If you use a memory where CS1 exists, simply uncomment these lines +//DATA 4 0x021b401c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset) +//DATA 4 0x021b401c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +//DATA 4 0x021b401c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration +//DATA 4 0x021b401c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration +//DATA 4 0x021b401c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration + +//////////#################################################// +//final DDR setup, before operation start: + +DATA 4 0x021b0020 0x00001800 // MMDC0_MDREF +DATA 4 0x021b4020 0x00001800 // MMDC1_MDREF, align with Chan 0 setting + +DATA 4 0x021b0818 0x0 // DDR_PHY_P0_MPODTCTRL +DATA 4 0x021b4818 0x0 // DDR_PHY_P1_MPODTCTRL + +DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr +DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P1_MPMUR0, frc_msr + +DATA 4 0x021b0004 0x00025564 // MMDC0_MDPDC now SDCTL power down enabled +DATA 4 0x021b4004 0x00025564 // MMDC1_MDPDC now SDCTL power down enabled, align with Chan 0 setting + +DATA 4 0x021b0404 0x00011006 //MMDC0_MAPSR ADOPT power down enabled +DATA 4 0x021b4404 0x00011006 //MMDC1_MAPSR ADOPT power down enabled, align with Chan 0 setting + +DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register +DATA 4 0x021b401c 0x00000000 // MMDC1_MDSCR, clear this register + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif +#endif diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 8cb5ac5940e..cd172c0e738 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -12,11 +12,20 @@ #include #include #include +#include #include #include #include #include #include +#include + +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -31,6 +40,10 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + int dram_init(void) { #if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \ @@ -43,11 +56,24 @@ int dram_init(void) return 0; } +#if defined(CONFIG_MX6DQ_POP_LPDDR2) +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_0; + gd->bd->bi_dram[0].size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + + return 0; +} +#endif + iomux_v3_cfg_t const uart4_pads[] = { MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#ifndef CONFIG_DM_MMC iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -59,7 +85,11 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#ifdef CONFIG_MX6DQ_POP_LPDDR2 + MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#else MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +#endif }; iomux_v3_cfg_t const usdhc4_pads[] = { @@ -74,6 +104,7 @@ iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +#endif iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -105,27 +136,24 @@ static void setup_iomux_enet(void) } #ifdef CONFIG_FSL_ESDHC +#ifndef CONFIG_DM_MMC struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR}, {USDHC4_BASE_ADDR}, }; -int board_mmc_get_env_dev(int devno) -{ - return devno - 2; -} - int board_mmc_getcd(struct mmc *mmc) { + int ret = 1; +#ifndef CONFIG_MX6DQ_POP_LPDDR2 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; if (cfg->esdhc_base == USDHC3_BASE_ADDR) { gpio_direction_input(IMX_GPIO_NR(6, 11)); ret = !gpio_get_value(IMX_GPIO_NR(6, 11)); } else /* Don't have the CD GPIO pin on board */ ret = 1; - +#endif return ret; } @@ -163,69 +191,70 @@ int board_mmc_init(bd_t *bis) } #endif +int board_mmc_get_env_dev(int devno) +{ + return devno - 2; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno + 2; +} +#endif + #define MII_MMD_ACCESS_CTRL_REG 0xd #define MII_MMD_ACCESS_ADDR_DATA_REG 0xe #define MII_DBG_PORT_REG 0x1d #define MII_DBG_PORT2_REG 0x1e -int fecmxc_mii_postcall(int phy) +static int ar8031_phy_fixup(struct phy_device *phydev) { unsigned short val; - /* - * Due to the i.MX6Q Armadillo2 board HW design,there is - * no 125Mhz clock input from SOC. In order to use RGMII, - * We need enable AR8031 ouput a 125MHz clk from CLK_25M - */ - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7); - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007); - miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val); + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_CTRL_REG, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_CTRL_REG, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_ADDR_DATA_REG); val &= 0xffe3; val |= 0x18; - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val); + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_ADDR_DATA_REG, val); - /* For the RGMII phy, we need enable tx clock delay */ - miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5); - miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val); + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_DBG_PORT_REG, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DBG_PORT2_REG); val |= 0x0100; - miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val); - - miiphy_write("FEC", phy, MII_BMCR, 0xa100); + phy_write(phydev, MDIO_DEVAD_NONE, MII_DBG_PORT2_REG, val); return 0; } -int board_eth_init(bd_t *bis) +int board_phy_config(struct phy_device *phydev) { - struct eth_device *dev; - int ret = cpu_eth_init(bis); + ar8031_phy_fixup(phydev); - if (ret) - return ret; + if (phydev->drv->config) + phydev->drv->config(phydev); - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXC: Unable to get FEC device entry\n"); - return -EINVAL; - } + return 0; +} - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXC: Unable to register FEC mii postcall\n"); - return ret; - } +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); - return 0; + return cpu_eth_init(bis); } #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) static iomux_v3_cfg_t const usb_otg_pads[] = { MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), }; static void setup_usb(void) @@ -255,11 +284,11 @@ int board_ehci_hcd_init(int port) return 0; } #endif +#endif int board_early_init_f(void) { setup_iomux_uart(); - setup_iomux_enet(); return 0; } @@ -270,7 +299,24 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB setup_usb(); +#else + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 1); +#endif +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); #endif return 0; @@ -286,3 +332,36 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_LDO_BYPASS_CHECK +/* no external pmic, always ldo_enable */ +void ldo_mode_set(int ldo_bypass) +{ + return; +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +void board_fastboot_setup(void) +{ + if (!getenv("fastboot_dev")) + setenv("fastboot_dev", "mmc0"); + if (!getenv("bootcmd")) + setenv("bootcmd", "boota mmc0"); +} + +#ifdef CONFIG_ANDROID_RECOVERY +int check_recovery_cmd_file(void) { + return 0; +} + +void board_recovery_setup(void) +{ + if (!getenv("bootcmd_android_recovery")) + setenv("bootcmd_android_recovery", "boota mmc0 recovery"); + + printf("setup env for recovery..\n"); + setenv("bootcmd", "run bootcmd_android_recovery"); +} +#endif +#endif diff --git a/board/freescale/mx6qarm2/plugin.S b/board/freescale/mx6qarm2/plugin.S new file mode 100644 index 00000000000..fe697598e36 --- /dev/null +++ b/board/freescale/mx6qarm2/plugin.S @@ -0,0 +1,1176 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +.macro imx6dlarm2_ddr_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00003000 + str r1, [r0, #0x590] + str r1, [r0, #0x598] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00003030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + + ldr r2, =0x00370037 + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x422f0220 + str r2, [r0, #0x83c] + ldr r2, =0x021f0219 + str r2, [r0, #0x840] + + ldr r2, =0x422f0220 + str r2, [r1, #0x83c] + ldr r2, =0x022d022f + str r2, [r1, #0x840] + + ldr r2, =0x47494b49 + str r2, [r0, #0x848] + ldr r2, =0x48484c47 + str r2, [r1, #0x848] + + ldr r2, =0x39382b2f + str r2, [r0, #0x850] + ldr r2, =0x2f35312c + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x00000800 + str r2, [r1, #0x8b8] + + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x40445323 + str r2, [r0, #0x00c] + ldr r2, =0xb66e8c63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00081740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x00440e21 + str r2, [r0, #0x030] + +#ifdef CONFIG_DDR_32BIT + ldr r2, =0x00000017 + str r2, [r0, #0x040] + ldr r2, =0xc3190000 + str r2, [r0, #0x000] +#else + ldr r2, =0x00000027 + str r2, [r0, #0x040] + ldr r2, =0xc31a0000 + str r2, [r0, #0x000] +#endif + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x0400803a + str r2, [r0, #0x01c] + + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x0000803b + str r2, [r0, #0x01c] + + ldr r2, =0x00428031 + str r2, [r0, #0x01c] + ldr r2, =0x00428039 + str r2, [r0, #0x01c] + + ldr r2, =0x07208030 + str r2, [r0, #0x01c] + ldr r2, =0x07208038 + str r2, [r0, #0x01c] + + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x04008048 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + + ldr r2, =0x00000007 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0x0002556d + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r1, #0x004] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dqarm2_ddr_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + ldr r1, =0x00000030 + str r1, [r0, #0x594] + + ldr r1, =0x00000030 + str r1, [r0, #0x56c] + ldr r1, =0x00000030 + str r1, [r0, #0x578] + ldr r1, =0x00000030 + str r1, [r0, #0x74c] + + ldr r1, =0x00000030 + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + ldr r1, =0x00000030 + str r1, [r0, #0x5a0] + ldr r1, =0x00000030 + str r1, [r0, #0x78c] + + ldr r1, =0x00000000 + str r1, [r0, #0x750] + + ldr r1, =0x00000038 + str r1, [r0, #0x5a8] + ldr r1, =0x00000038 + str r1, [r0, #0x5b0] + ldr r1, =0x00000038 + str r1, [r0, #0x524] + ldr r1, =0x00000038 + str r1, [r0, #0x51c] + ldr r1, =0x00000038 + str r1, [r0, #0x518] + ldr r1, =0x00000038 + str r1, [r0, #0x50c] + ldr r1, =0x00000038 + str r1, [r0, #0x5b8] + ldr r1, =0x00000038 + str r1, [r0, #0x5c0] + + ldr r1, =0x00000000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + ldr r1, =0x00000030 + str r1, [r0, #0x788] + ldr r1, =0x00000030 + str r1, [r0, #0x794] + ldr r1, =0x00000030 + str r1, [r0, #0x79c] + ldr r1, =0x00000030 + str r1, [r0, #0x7a0] + ldr r1, =0x00000030 + str r1, [r0, #0x7a4] + ldr r1, =0x00000030 + str r1, [r0, #0x7a8] + ldr r1, =0x00000030 + str r1, [r0, #0x748] + + ldr r1, =0x00000030 + str r1, [r0, #0x5ac] + ldr r1, =0x00000030 + str r1, [r0, #0x5b4] + ldr r1, =0x00000030 + str r1, [r0, #0x528] + ldr r1, =0x00000030 + str r1, [r0, #0x520] + ldr r1, =0x00000030 + str r1, [r0, #0x514] + ldr r1, =0x00000030 + str r1, [r0, #0x510] + ldr r1, =0x00000030 + str r1, [r0, #0x5bc] + ldr r1, =0x00000030 + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + ldr r2, =0x001F001F + str r2, [r0, #0x810] + + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00440044 + str r2, [r1, #0x80c] + ldr r2, =0x00440044 + str r2, [r1, #0x810] + + ldr r2, =0x4333033F + str r2, [r0, #0x83c] + ldr r2, =0x0339033E + str r2, [r0, #0x840] + ldr r2, =0x433F0343 + str r2, [r1, #0x83c] + ldr r2, =0x03490320 + str r2, [r1, #0x840] + + ldr r2, =0x42363838 + str r2, [r0, #0x848] + ldr r2, =0x3F343242 + str r2, [r1, #0x848] + + ldr r2, =0x37424844 + str r2, [r0, #0x850] + ldr r2, =0x48264731 + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + ldr r2, =0x33333333 + str r2, [r0, #0x820] + ldr r2, =0x33333333 + str r2, [r0, #0x824] + ldr r2, =0x33333333 + str r2, [r0, #0x828] + ldr r2, =0x33333333 + str r2, [r1, #0x81c] + ldr r2, =0x33333333 + str r2, [r1, #0x820] + ldr r2, =0x33333333 + str r2, [r1, #0x824] + ldr r2, =0x33333333 + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x00000800 + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x09444040 + str r2, [r0, #0x008] + ldr r2, =0x555A7975 + str r2, [r0, #0x00c] + ldr r2, =0xFF538F64 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00081740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x005a1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x11420000 + str r2, [r0, #0x400] + ldr r2, =0x11420000 + str r2, [r1, #0x400] + + ldr r2, =0xc31a0000 + str r2, [r0, #0x000] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x0408803a + str r2, [r0, #0x01c] + + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x0000803b + str r2, [r0, #0x01c] + + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x00048039 + str r2, [r0, #0x01c] + + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x09408038 + str r2, [r0, #0x01c] + + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x04008048 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dlarm2_lpddr2_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00003028 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + str r1, [r0, #0x4cc] + str r1, [r0, #0x4d0] + str r1, [r0, #0x4d4] + str r1, [r0, #0x4d8] + + ldr r1, =0x00000038 + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + str r1, [r0, #0x480] + str r1, [r0, #0x484] + str r1, [r0, #0x488] + str r1, [r0, #0x48c] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x494] + str r1, [r0, #0x4a4] + str r1, [r0, #0x4a8] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + ldr r1, =0x00000038 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x780] + str r1, [r0, #0x784] + str r1, [r0, #0x78c] + str r1, [r0, #0x748] + str r1, [r0, #0x74c] + str r1, [r0, #0x76c] + ldr r1, =0x00020000 + str r1, [r0, #0x750] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + ldr r1, =0x00020000 + str r1, [r0, #0x760] + ldr r1, =0x00080000 + str r1, [r0, #0x774] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + ldr r2, =0x1b5f01ff + str r2, [r0, #0x85c] + str r2, [r1, #0x85c] + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00400000 + str r2, [r0, #0x890] + str r2, [r1, #0x890] + ldr r2, =0x00055555 + str r2, [r1, #0x8bc] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x4b4b524f + str r2, [r0, #0x848] + ldr r2, =0x494f4c44 + str r2, [r1, #0x848] + + ldr r2, =0x3c3d303c + str r2, [r0, #0x850] + ldr r2, =0x3c343d38 + str r2, [r1, #0x850] + + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + str r2, [r1, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + str r2, [r1, #0x840] + + ldr r2, =0x00000a00 + str r2, [r0, #0x858] + str r2, [r1, #0x858] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x34386145 + str r2, [r0, #0xc] + ldr r2, =0x00020036 + str r2, [r0, #0x4] + ldr r2, =0x00100c83 + str r2, [r0, #0x10] + ldr r2, =0x000000Dc + str r2, [r0, #0x14] + ldr r2, =0x0000174C + str r2, [r0, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x2c] + ldr r2, =0x0000020e + str r2, [r0, #0x30] + ldr r2, =0x00190778 + str r2, [r0, #0x38] + ldr r2, =0x00000000 + str r2, [r0, #0x8] + + ldr r2, =0x0000005f + str r2, [r0, #0x40] + ldr r2, =0x0000000f + str r2, [r0, #0x404] + + ldr r2, =0xc3010000 + str r2, [r0, #0x0] + + ldr r2, =0x34386145 + str r2, [r1, #0xc] + + ldr r2, =0x00020036 + str r2, [r1, #0x4] + ldr r2, =0x00100c83 + str r2, [r1, #0x10] + ldr r2, =0x000000Dc + str r2, [r1, #0x14] + ldr r2, =0x0000174C + str r2, [r1, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r1, #0x2c] + ldr r2, =0x0000020e + str r2, [r1, #0x30] + ldr r2, =0x00190778 + str r2, [r1, #0x38] + ldr r2, =0x00000000 + str r2, [r1, #0x8] + + ldr r2, =0x0000003f + str r2, [r1, #0x40] + + ldr r2, =0xc3010000 + str r2, [r1, #0x0] + + ldr r2, =0x003f8030 + str r2, [r0, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x1c] + ldr r2, =0xa2018030 + str r2, [r0, #0x1c] + ldr r2, =0x06028030 + str r2, [r0, #0x1c] + ldr r2, =0x01038030 + str r2, [r0, #0x1c] + + ldr r2, =0x003f8030 + str r2, [r1, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r1, #0x1c] + ldr r2, =0xa2018030 + str r2, [r1, #0x1c] + ldr r2, =0x06028030 + str r2, [r1, #0x1c] + ldr r2, =0x01038030 + str r2, [r1, #0x1c] + + ldr r2, =0x00005800 + str r2, [r0, #0x20] + str r2, [r1, #0x20] + + ldr r2, =0x00000000 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00000000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + ldr r1, =0x007F007F + str r1, [r0, #0x18] + ldr r1, =0x007F007F + str r1, [r0, #0x1c] +.endm + +.macro imx6dqarm2_lpddr2_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x60324 + str r1, [r0, #0x18] + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00003038 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00000038 + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x57c] + str r1, [r0, #0x590] + str r1, [r0, #0x598] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + ldr r1, =0x00000038 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x74c] + ldr r1, =0x00020000 + str r1, [r0, #0x750] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + ldr r1, =0x00020000 + str r1, [r0, #0x774] + ldr r1, =0x00000038 + str r1, [r0, #0x78c] + ldr r1, =0x00080000 + str r1, [r0, #0x798] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + ldr r2, =0x1b5f01ff + str r2, [r0, #0x85c] + str r2, [r1, #0x85c] + ldr r2, =0xa1390000 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + ldr r2, =0x00400000 + str r2, [r0, #0x890] + str r2, [r1, #0x890] + ldr r2, =0x00055555 + str r2, [r1, #0x8bc] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0xf3333333 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + str r2, [r1, #0x82c] + str r2, [r1, #0x830] + str r2, [r1, #0x834] + str r2, [r1, #0x838] + + ldr r2, =0x49383b39 + str r2, [r0, #0x848] + ldr r2, =0x30364738 + str r2, [r0, #0x850] + + ldr r2, =0x3e3c3846 + str r2, [r1, #0x848] + ldr r2, =0x4c294b35 + str r2, [r1, #0x850] + + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + str r2, [r1, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + str r2, [r1, #0x840] + + ldr r2, =0x00000f00 + str r2, [r0, #0x858] + str r2, [r1, #0x858] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x555a61a5 + str r2, [r0, #0xc] + ldr r2, =0x00020036 + str r2, [r0, #0x4] + ldr r2, =0x00160e83 + str r2, [r0, #0x10] + ldr r2, =0x000000dd + str r2, [r0, #0x14] + ldr r2, =0x0008174C + str r2, [r0, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x2c] + ldr r2, =0x0000020e + str r2, [r0, #0x30] + ldr r2, =0x200aac + str r2, [r0, #0x38] + ldr r2, =0x00000000 + str r2, [r0, #0x8] + + ldr r2, =0x0000005f + str r2, [r0, #0x40] + + ldr r2, =0xc3010000 + str r2, [r0, #0x0] + + ldr r2, =0x555a61a5 + str r2, [r1, #0xc] + ldr r2, =0x00020036 + str r2, [r1, #0x4] + ldr r2, =0x00160e83 + str r2, [r1, #0x10] + ldr r2, =0x000000dd + str r2, [r1, #0x14] + ldr r2, =0x0008174C + str r2, [r1, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r1, #0x2c] + ldr r2, =0x0000020e + str r2, [r1, #0x30] + ldr r2, =0x00200aac + str r2, [r1, #0x38] + ldr r2, =0x00000000 + str r2, [r1, #0x8] + + ldr r2, =0x0000003f + str r2, [r1, #0x40] + + ldr r2, =0xc3010000 + str r2, [r1, #0x0] + + ldr r2, =0x003f8030 + str r2, [r0, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x1c] + ldr r2, =0xc2018030 + str r2, [r0, #0x1c] + ldr r2, =0x06028030 + str r2, [r0, #0x1c] + ldr r2, =0x02038030 + str r2, [r0, #0x1c] + + ldr r2, =0x003f8030 + str r2, [r1, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r1, #0x1c] + ldr r2, =0xc2018030 + str r2, [r1, #0x1c] + ldr r2, =0x06028030 + str r2, [r1, #0x1c] + ldr r2, =0x02038030 + str r2, [r1, #0x1c] + + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + + ldr r2, =0x00007800 + str r2, [r0, #0x20] + str r2, [r1, #0x20] + + ldr r2, =0x00000000 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00000000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + + ldr r2, =0x00011006 + str r2, [r0, #0x404] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + ldr r1, =0x007F007F + str r1, [r0, #0x18] + ldr r1, =0x007F007F + str r1, [r0, #0x1c] +.endm + +.macro imx6dq_pop_arm2_lpddr2_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + str r1, [r0, #0x58c] + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + ldr r1, =0x00003030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + ldr r2, =0x1B5F0107 + str r2, [r0, #0x85c] + str r2, [r1, #0x85c] + ldr r2, =0xA1390003 + str r2, [r0, #0x800] + ldr r2, =0x00400000 + str r2, [r0, #0x890] + str r2, [r1, #0x890] + ldr r2, =0x3C3A3A44 + str r2, [r0, #0x848] + str r2, [r1, #0x848] + ldr r2, =0x4238423A + str r2, [r0, #0x850] + str r2, [r1, #0x850] + + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + ldr r2, =0x20000000 + str r2, [r1, #0x83c] + ldr r2, =0x00000000 + str r2, [r1, #0x840] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0xf3333333 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + str r2, [r1, #0x82c] + str r2, [r1, #0x830] + str r2, [r1, #0x834] + str r2, [r1, #0x838] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x4] + ldr r2, =0x00000000 + str r2, [r0, #0x8] + ldr r2, =0x444961A5 + str r2, [r0, #0xc] + ldr r2, =0x00160E83 + str r2, [r0, #0x10] + ldr r2, =0x000000DD + str r2, [r0, #0x14] + + ldr r2, =0x0000174C + str r2, [r0, #0x18] + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + ldr r2, =0x149F26D2 + str r2, [r0, #0x2c] + ldr r2, =0x00000010 + str r2, [r0, #0x30] + ldr r2, =0x0021099B + str r2, [r0, #0x38] + ldr r2, =0x0000004F + str r2, [r0, #0x40] + ldr r2, =0x11420000 + str r2, [r0, #0x400] + ldr r2, =0x83110000 + str r2, [r0, #0x0] + + ldr r2, =0x00020036 + str r2, [r1, #0x4] + ldr r2, =0x00000000 + str r2, [r1, #0x8] + ldr r2, =0x444961A5 + str r2, [r1, #0xc] + ldr r2, =0x00160E83 + str r2, [r1, #0x10] + ldr r2, =0x000000DD + str r2, [r1, #0x14] + + ldr r2, =0x0000174C + str r2, [r1, #0x18] + ldr r2, =0x00008000 + str r2, [r1, #0x1c] + ldr r2, =0x149F26D2 + str r2, [r1, #0x2c] + ldr r2, =0x00000010 + str r2, [r1, #0x30] + ldr r2, =0x0021099B + str r2, [r1, #0x38] + ldr r2, =0x00000017 + str r2, [r1, #0x40] + ldr r2, =0x11420000 + str r2, [r1, #0x400] + ldr r2, =0x83110000 + str r2, [r1, #0x0] + + ldr r2, =0x003F8030 + str r2, [r0, #0x1c] + ldr r2, =0xFF0A8030 + str r2, [r0, #0x1c] + ldr r2, =0xC2018030 + str r2, [r0, #0x1c] + ldr r2, =0x06028030 + str r2, [r0, #0x1c] + ldr r2, =0x02038030 + str r2, [r0, #0x1c] + + ldr r2, =0x003F8030 + str r2, [r1, #0x1c] + ldr r2, =0xFF0A8030 + str r2, [r1, #0x1c] + ldr r2, =0xC2018030 + str r2, [r1, #0x1c] + ldr r2, =0x06028030 + str r2, [r1, #0x1c] + ldr r2, =0x02038030 + str r2, [r1, #0x1c] + + ldr r2, =0xA1390003 + str r2, [r0, #0x800] + + ldr r2, =0x00001800 + str r2, [r0, #0x20] + str r2, [r1, #0x20] + + ldr r2, =0x00000000 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0x00025576 + str r2, [r0, #0x4] + str r2, [r1, #0x4] + + ldr r2, =0x00011006 + str r2, [r0, #0x404] + str r2, [r1, #0x404] + + ldr r2, =0x00000000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + ldr r1, =0x007F007F + str r1, [r0, #0x18] + ldr r1, =0x007F007F + str r1, [r0, #0x1c] +.endm + +.macro imx6_ddr_setting + #if defined (CONFIG_MX6DQ_POP_LPDDR2) + imx6dq_pop_arm2_lpddr2_setting + #elif defined (CONFIG_MX6DQ_LPDDR2) + imx6dqarm2_lpddr2_setting + #elif defined (CONFIG_MX6Q) + imx6dqarm2_ddr_setting + #elif defined (CONFIG_MX6DL_LPDDR2) + imx6dlarm2_lpddr2_setting + #elif defined (CONFIG_MX6DL) + imx6dlarm2_ddr_setting + #else + #error "SOC not configured" + #endif +.endm + +.macro imx6_clock_gating +.endm + +.macro imx6_qos_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sabreauto/Kconfig b/board/freescale/mx6sabreauto/Kconfig index 5b4faf6d5fd..3a63229bd7e 100644 --- a/board/freescale/mx6sabreauto/Kconfig +++ b/board/freescale/mx6sabreauto/Kconfig @@ -9,4 +9,12 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sabreauto" +config SYS_TEXT_BASE + default 0x17800000 + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. endif diff --git a/board/freescale/mx6sabreauto/imximage.cfg b/board/freescale/mx6sabreauto/imximage.cfg new file mode 100644 index 00000000000..4c97e8ff6af --- /dev/null +++ b/board/freescale/mx6sabreauto/imximage.cfg @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000028 +DATA 4 0x020e05b0 0x00000028 +DATA 4 0x020e0524 0x00000028 +DATA 4 0x020e051c 0x00000028 +DATA 4 0x020e0518 0x00000028 +DATA 4 0x020e050c 0x00000028 +DATA 4 0x020e05b8 0x00000028 +DATA 4 0x020e05c0 0x00000028 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000028 +DATA 4 0x020e0788 0x00000028 +DATA 4 0x020e0794 0x00000028 +DATA 4 0x020e079c 0x00000028 +DATA 4 0x020e07a0 0x00000028 +DATA 4 0x020e07a4 0x00000028 +DATA 4 0x020e07a8 0x00000028 +DATA 4 0x020e0748 0x00000028 +DATA 4 0x020e05ac 0x00000028 +DATA 4 0x020e05b4 0x00000028 +DATA 4 0x020e0528 0x00000028 +DATA 4 0x020e0520 0x00000028 +DATA 4 0x020e0514 0x00000028 +DATA 4 0x020e0510 0x00000028 +DATA 4 0x020e05bc 0x00000028 +DATA 4 0x020e05c4 0x00000028 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x43260335 +DATA 4 0x021b0840 0x031A030B +DATA 4 0x021b483c 0x4323033B +DATA 4 0x021b4840 0x0323026F +DATA 4 0x021b0848 0x483D4545 +DATA 4 0x021b4848 0x44433E48 +DATA 4 0x021b0850 0x41444840 +DATA 4 0x021b4850 0x4835483E +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x8A8F7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008F1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFF000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0xFFFFF300 +DATA 4 0x020c407c 0x0F0000F3 +DATA 4 0x020c4080 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif diff --git a/board/freescale/mx6sabreauto/mx6dl.cfg b/board/freescale/mx6sabreauto/mx6dl.cfg new file mode 100644 index 00000000000..8d01d4b8797 --- /dev/null +++ b/board/freescale/mx6sabreauto/mx6dl.cfg @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000028 +DATA 4 0x020e04c0 0x00000028 +DATA 4 0x020e04c4 0x00000028 +DATA 4 0x020e04c8 0x00000028 +DATA 4 0x020e04cc 0x00000028 +DATA 4 0x020e04d0 0x00000028 +DATA 4 0x020e04d4 0x00000028 +DATA 4 0x020e04d8 0x00000028 +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000028 +DATA 4 0x020e0770 0x00000028 +DATA 4 0x020e0778 0x00000028 +DATA 4 0x020e077c 0x00000028 +DATA 4 0x020e0780 0x00000028 +DATA 4 0x020e0784 0x00000028 +DATA 4 0x020e078c 0x00000028 +DATA 4 0x020e0748 0x00000028 +DATA 4 0x020e0470 0x00000028 +DATA 4 0x020e0474 0x00000028 +DATA 4 0x020e0478 0x00000028 +DATA 4 0x020e047c 0x00000028 +DATA 4 0x020e0480 0x00000028 +DATA 4 0x020e0484 0x00000028 +DATA 4 0x020e0488 0x00000028 +DATA 4 0x020e048c 0x00000028 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x42190217 +DATA 4 0x021b0840 0x017B017B +DATA 4 0x021b483c 0x4176017B +DATA 4 0x021b4840 0x015F016C +DATA 4 0x021b0848 0x4C4C4D4C +DATA 4 0x021b4848 0x4A4D4C48 +DATA 4 0x021b0850 0x3F3F3F40 +DATA 4 0x021b4850 0x3538382E +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020025 +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676B5313 +DATA 4 0x021b0010 0xB66E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006B1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025565 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFF000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0xFFFFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif diff --git a/board/freescale/mx6sabreauto/mx6qp.cfg b/board/freescale/mx6sabreauto/mx6qp.cfg new file mode 100644 index 00000000000..23e94d02f72 --- /dev/null +++ b/board/freescale/mx6sabreauto/mx6qp.cfg @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +/* image version */ + +#define __ASSEMBLY__ +#include + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001b001e +DATA 4 0x021b0810 0x002e0029 +DATA 4 0x021b480c 0x001b002a +DATA 4 0x021b4810 0x0019002c +DATA 4 0x021b083c 0x43240334 +DATA 4 0x021b0840 0x0324031a +DATA 4 0x021b483c 0x43340344 +DATA 4 0x021b4840 0x03280276 +DATA 4 0x021b0848 0x44383A3E +DATA 4 0x021b4848 0x3C3C3846 +DATA 4 0x021b0850 0x2e303230 +DATA 4 0x021b4850 0x38283E34 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08c0 0x24912249 +DATA 4 0x021b48c0 0x24914289 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x24444040 +DATA 4 0x021b000c 0x898E7955 +DATA 4 0x021b0010 0xFF320F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 + +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008E1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0400 0x14420000 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x021b0890 0x00400C58 +DATA 4 0x00bb0008 0x00000000 +DATA 4 0x00bb000c 0x2891E41A +DATA 4 0x00bb0038 0x00000564 +DATA 4 0x00bb0014 0x00000040 +DATA 4 0x00bb0028 0x00000020 +DATA 4 0x00bb002c 0x00000020 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFF000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0xFFFFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 +#endif diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c index 52b016b91d3..1a241050e12 100644 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Author: Fabio Estevam * @@ -33,6 +34,16 @@ #include #include "../common/pfuze.h" +#ifdef CONFIG_SATA +#include +#endif +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ + DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -43,6 +54,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) +/*Need more drive strength for SD1 slot on base board*/ +#define USDHC1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -57,10 +73,18 @@ DECLARE_GLOBAL_DATA_PTR; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + #define I2C_PMIC 1 int dram_init(void) @@ -91,31 +115,20 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), }; +#ifdef CONFIG_SYS_I2C /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */ -static struct i2c_pads_info mx6q_i2c_pad_info1 = { +static struct i2c_pads_info i2c_pad_info1 = { .scl = { - .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC, + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, .gp = IMX_GPIO_NR(2, 30) }, .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -static struct i2c_pads_info mx6dl_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; @@ -125,32 +138,20 @@ static struct i2c_pads_info mx6dl_i2c_pad_info1 = { * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor, * Compass Sensor, Accelerometer, Res Touch */ -static struct i2c_pads_info mx6q_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - -static struct i2c_pads_info mx6dl_i2c_pad_info2 = { +static struct i2c_pads_info i2c_pad_info2 = { .scl = { - .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, .gp = IMX_GPIO_NR(1, 3) }, .sda = { - .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC, + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, .gp = IMX_GPIO_NR(3, 18) } }; #endif +#endif static iomux_v3_cfg_t const i2c3_pads[] = { IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), @@ -160,6 +161,8 @@ static iomux_v3_cfg_t const port_exp[] = { IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; +#ifdef CONFIG_PCA953X + /*Define for building port exp gpio, pin starts from 0*/ #define PORTEXP_IO_NR(chip, pin) \ ((chip << 5) + pin) @@ -197,6 +200,7 @@ static int port_exp_direction_output(unsigned gpio, int value) return 0; } +#endif #ifdef CONFIG_MTD_NOR_FLASH static iomux_v3_cfg_t const eimnor_pads[] = { @@ -301,6 +305,19 @@ static void setup_iomux_enet(void) SETUP_IOMUX_PADS(enet_pads); } +static iomux_v3_cfg_t const usdhc1_pads[] = { + /*To avoid pin conflict with NAND, set usdhc1 to 4 pins*/ + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + + /*CD pin*/ + IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -322,22 +339,89 @@ static void setup_iomux_uart(void) } #ifdef CONFIG_FSL_ESDHC -static struct fsl_esdhc_cfg usdhc_cfg[1] = { + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) +#define USDHC3_CD_GPIO IMX_GPIO_NR(6, 15) + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 4}, {USDHC3_BASE_ADDR}, }; +int board_mmc_get_env_dev(int devno) +{ + /* + * need ubstract 1 to map to the mmc3 device id + * see the comments in board_mmc_init function + */ + if (devno == 2) + devno--; + + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + if (devno == 1) + devno = 2; + + return devno; +} + int board_mmc_getcd(struct mmc *mmc) { - gpio_direction_input(IMX_GPIO_NR(6, 15)); - return !gpio_get_value(IMX_GPIO_NR(6, 15)); + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + gpio_direction_input(USDHC1_CD_GPIO); + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + gpio_direction_input(USDHC3_CD_GPIO); + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; } int board_mmc_init(bd_t *bis) { - SETUP_IOMUX_PADS(usdhc3_pads); + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + return 0; } #endif @@ -379,20 +463,25 @@ static void setup_gpmi_nand(void) static void setup_fec(void) { + int ret; + if (is_mx6dqp()) { /* * select ENET MAC0 TX clock from PLL */ imx_iomux_set_gpr_register(5, 9, 1, 1); - enable_fec_anatop_clock(0, ENET_125MHZ); + } else { + imx_iomux_set_gpr_register(1, 21, 1, 1); } - setup_iomux_enet(); + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + printf("Error fec anatop clock settings!\n"); } int board_eth_init(bd_t *bis) { - setup_fec(); + setup_iomux_enet(); return cpu_eth_init(bis); } @@ -477,7 +566,7 @@ struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, + .detect = NULL, .enable = do_enable_hdmi, .mode = { .name = "HDMI", @@ -502,6 +591,7 @@ iomux_v3_cfg_t const backlight_pads[] = { static void setup_iomux_backlight(void) { + gpio_request(IMX_GPIO_NR(2, 9), "backlight"); gpio_direction_output(IMX_GPIO_NR(2, 9), 1); SETUP_IOMUX_PADS(backlight_pads); } @@ -570,6 +660,31 @@ int overwrite_console(void) return 1; } +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* Steer logic */ + IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + + gpio_request(IMX_GPIO_NR(3, 19), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + gpio_direction_output(IMX_GPIO_NR(3, 19), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(3, 19)) : -1; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -589,20 +704,20 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_SYS_I2C /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */ - if (is_mx6dq() || is_mx6dqp()) - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); - else - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#ifndef CONFIG_SYS_FLASH_CFI + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif +#endif + /* I2C 3 Steer */ + gpio_request(IMX_GPIO_NR(5, 4), "steer logic"); gpio_direction_output(IMX_GPIO_NR(5, 4), 1); SETUP_IOMUX_PADS(i2c3_pads); -#ifndef CONFIG_SYS_FLASH_CFI - if (is_mx6dq() || is_mx6dqp()) - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); - else - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); -#endif + + gpio_request(IMX_GPIO_NR(1, 15), "expander en"); gpio_direction_output(IMX_GPIO_NR(1, 15), 1); SETUP_IOMUX_PADS(port_exp); @@ -610,38 +725,235 @@ int board_init(void) setup_display(); #endif +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_SATA + setup_sata(); +#endif + #ifdef CONFIG_MTD_NOR_FLASH setup_iomux_eimnor(); #endif - return 0; -} -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; -} +#ifdef CONFIG_FEC_MXC + setup_fec(); #endif + return 0; +} + +#ifdef CONFIG_POWER int power_init_board(void) { - struct pmic *p; + struct pmic *pfuze; unsigned int value; + int ret; - p = pfuze_common_init(I2C_PMIC); - if (!p) + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) return -ENODEV; + if (is_mx6dqp()) + ret = pfuze_mode_init(pfuze, APS_APS); + else + ret = pfuze_mode_init(pfuze, APS_PFM); + + if (ret < 0) + return ret; + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value); + value &= ~0x3f; + value |= 0x1f; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value); + /* set SW2 staby volatage 0.975V*/ - pmic_reg_read(p, PFUZE100_SW2STBY, &value); + pmic_reg_read(pfuze, PFUZE100_SW2STBY, &value); value &= ~0x3f; value |= 0x17; - pmic_reg_write(p, PFUZE100_SW2STBY, value); + pmic_reg_write(pfuze, PFUZE100_SW2STBY, value); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW2CONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW2CONF, value); + } else { + /* set SW1AB staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* set SW1C staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value); + value &= ~0x3f; + value |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value); } - return pfuze_mode_init(p, APS_PFM); + return 0; } +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + unsigned int reg; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + if (is_mx6dqp()) + ret = pfuze_mode_init(dev, APS_APS); + else + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1f; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + + /* set SW2/VDDARM staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW2STBY); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(dev, PFUZE100_SW2STBY, reg); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW2CONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW2CONF, reg); + } else { + /* set SW1AB staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + } + + return 0; +} +#endif + +#ifdef CONFIG_LDO_BYPASS_CHECK +#ifdef CONFIG_POWER +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + value |= 0x29; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } else { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + } + /* increase VDDSOC to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + } +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29); + } else { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d); + } + /* increase VDDSOC to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d); + } +} +#endif +#endif #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { @@ -657,6 +969,11 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "SABREAUTO"); @@ -668,6 +985,10 @@ int board_late_init(void) env_set("board_rev", "MX6DL"); #endif +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + return 0; } @@ -679,11 +1000,31 @@ int checkboard(void) } #ifdef CONFIG_USB_EHCI_MX6 +#ifdef CONFIG_DM_USB +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + /* + * Set daisy chain for otg_pin_id on 6q. + * For 6dl, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + return 0; +} +#else #define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7) #define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1) iomux_v3_cfg_t const usb_otg_pads[] = { - IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL)), }; int board_ehci_hcd_init(int port) @@ -709,6 +1050,7 @@ int board_ehci_hcd_init(int port) int board_ehci_power(int port, int on) { +#ifdef CONFIG_PCA953X switch (port) { case 0: if (on) @@ -726,10 +1068,77 @@ int board_ehci_power(int port, int on) printf("MXC USB port %d not yet supported\n", port); return -EINVAL; } +#elif defined(CONFIG_DM_PCA953X) + struct gpio_desc desc; + int ret; + + switch (port) { + case 0: + ret = dm_gpio_lookup_name("gpio@34_1", &desc); + if (ret) + return ret; + + dm_gpio_request(&desc, "usb_otg_pwr"); + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + + if (on) + dm_gpio_set_value(&desc, 1); + else + dm_gpio_set_value(&desc, 0); + break; + case 1: + ret = dm_gpio_lookup_name("gpio@32_7", &desc); + if (ret) + return ret; + dm_gpio_request(&desc, "usb_host1_pwr"); + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + + if (on) + dm_gpio_set_value(&desc, 1); + else + dm_gpio_set_value(&desc, 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } +#endif return 0; } #endif +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY + +#define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 14) +iomux_v3_cfg_t const recovery_key_pads[] = { + IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +int is_recovery_key_pressing(void) +{ + int button_pressed = 0; + + /* Check Recovery Combo Button press or not. */ + SETUP_IOMUX_PADS(recovery_key_pads); + + gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key"); + gpio_direction_input(GPIO_VOL_DN_KEY); + + if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return button_pressed; +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ + +#endif /*CONFIG_FSL_FASTBOOT*/ + #ifdef CONFIG_SPL_BUILD #include diff --git a/board/freescale/mx6sabreauto/mx6solo.cfg b/board/freescale/mx6sabreauto/mx6solo.cfg new file mode 100644 index 00000000000..abce4f9ea6b --- /dev/null +++ b/board/freescale/mx6sabreauto/mx6solo.cfg @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4, 0x020e0774, 0x000C0000 +DATA 4, 0x020e0754, 0x00000000 +DATA 4, 0x020e04ac, 0x00000030 +DATA 4, 0x020e04b0, 0x00000030 +DATA 4, 0x020e0464, 0x00000030 +DATA 4, 0x020e0490, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e0494, 0x00000030 +DATA 4, 0x020e04a0, 0x00000000 +DATA 4, 0x020e04b4, 0x00000030 +DATA 4, 0x020e04b8, 0x00000030 +DATA 4, 0x020e076c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e04bc, 0x00000028 +DATA 4, 0x020e04c0, 0x00000028 +DATA 4, 0x020e04c4, 0x00000028 +DATA 4, 0x020e04c8, 0x00000028 +DATA 4, 0x020e0760, 0x00020000 +DATA 4, 0x020e0764, 0x00000028 +DATA 4, 0x020e0770, 0x00000028 +DATA 4, 0x020e0778, 0x00000028 +DATA 4, 0x020e077c, 0x00000028 +DATA 4, 0x020e0470, 0x00000028 +DATA 4, 0x020e0474, 0x00000028 +DATA 4, 0x020e0478, 0x00000028 +DATA 4, 0x020e047c, 0x00000028 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001F001F +DATA 4, 0x021b0810, 0x001F001F +DATA 4, 0x021b083c, 0x421C0216 +DATA 4, 0x021b0840, 0x017B017A +DATA 4, 0x021b0848, 0x4B4A4E4C +DATA 4, 0x021b0850, 0x3F3F3334 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b0004, 0x00020025 +DATA 4, 0x021b0008, 0x00333030 +DATA 4, 0x021b000c, 0x676B5313 +DATA 4, 0x021b0010, 0xB66E8B63 +DATA 4, 0x021b0014, 0x01FF00DB +DATA 4, 0x021b0018, 0x00001740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x006B1023 +DATA 4, 0x021b0040, 0x00000027 +DATA 4, 0x021b0000, 0x84190000 +DATA 4, 0x021b001c, 0x04008032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x05208030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b0004, 0x00025565 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFF000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0xFFFFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif diff --git a/board/freescale/mx6sabreauto/plugin.S b/board/freescale/mx6sabreauto/plugin.S new file mode 100644 index 00000000000..6301ae1990f --- /dev/null +++ b/board/freescale/mx6sabreauto/plugin.S @@ -0,0 +1,675 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6dqpsabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001b001e + str r2, [r0, #0x80c] + ldr r2, =0x002e0029 + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x001b002a + str r2, [r1, #0x80c] + ldr r2, =0x0019002c + str r2, [r1, #0x810] + + ldr r2, =0x43240334 + str r2, [r0, #0x83c] + ldr r2, =0x0324031a + str r2, [r0, #0x840] + + ldr r2, =0x43340344 + str r2, [r1, #0x83c] + ldr r2, =0x03280276 + str r2, [r1, #0x840] + + ldr r2, =0x44383A3E + str r2, [r0, #0x848] + ldr r2, =0x3C3C3846 + str r2, [r1, #0x848] + + ldr r2, =0x2e303230 + str r2, [r0, #0x850] + ldr r2, =0x38283E34 + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x24912249 + str r2, [r0, #0x8c0] + ldr r2, =0x24914289 + str r2, [r1, #0x8c0] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x24444040 + str r2, [r0, #0x008] + + ldr r2, =0x898E7955 + str r2, [r0, #0x00c] + ldr r2, =0xFF320F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x008E1023 + str r2, [r0, #0x030] + ldr r2, =0x00000047 + str r2, [r0, #0x040] + + ldr r2, =0x14420000 + str r2, [r0, #0x400] + ldr r2, =0x841A0000 + str r2, [r0, #0x000] + + ldr r2, =0x00400C58 + str r2, [r0, #0x890] + + ldr r3, =0x00bb0000 + ldr r2, =0x00000000 + str r2, [r3, #0x008] + ldr r2, =0x2891E41A + str r2, [r3, #0x00c] + ldr r2, =0x00000564 + str r2, [r3, #0x038] + ldr r2, =0x00000040 + str r2, [r3, #0x014] + ldr r2, =0x00000020 + str r2, [r3, #0x028] + str r2, [r3, #0x02c] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dqsabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000028 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000028 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x43260335 + str r2, [r0, #0x83c] + ldr r2, =0x031A030B + str r2, [r0, #0x840] + + ldr r2, =0x4323033B + str r2, [r1, #0x83c] + ldr r2, =0x0323026F + str r2, [r1, #0x840] + + ldr r2, =0x483D4545 + str r2, [r0, #0x848] + ldr r2, =0x44433E48 + str r2, [r1, #0x848] + + ldr r2, =0x41444840 + str r2, [r0, #0x850] + ldr r2, =0x4835483E + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x09444040 + str r2, [r0, #0x008] + + ldr r2, =0x8A8F7955 + str r2, [r0, #0x00c] + ldr r2, =0xFF328F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x008F1023 + str r2, [r0, #0x030] + ldr r2, =0x00000047 + str r2, [r0, #0x040] + + ldr r2, =0x841A0000 + str r2, [r0, #0x000] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dlsabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000028 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + str r1, [r0, #0x4cc] + str r1, [r0, #0x4d0] + str r1, [r0, #0x4d4] + str r1, [r0, #0x4d8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000028 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x780] + str r1, [r0, #0x784] + str r1, [r0, #0x78c] + str r1, [r0, #0x748] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + str r1, [r0, #0x480] + str r1, [r0, #0x484] + str r1, [r0, #0x488] + str r1, [r0, #0x48c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001f001f + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x42190217 + str r2, [r0, #0x83c] + ldr r2, =0x017b017b + str r2, [r0, #0x840] + + ldr r2, =0x4176017b + str r2, [r1, #0x83c] + ldr r2, =0x015f016c + str r2, [r1, #0x840] + + ldr r2, =0x4c4c4d4c + str r2, [r0, #0x848] + ldr r2, =0x4a4d4c48 + str r2, [r1, #0x848] + + ldr r2, =0x3f3f3f40 + str r2, [r0, #0x850] + ldr r2, =0x3538382e + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020025 + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x676b5313 + str r2, [r0, #0x00c] + ldr r2, =0xb66e8b63 + str r2, [r0, #0x010] + + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x00000047 + str r2, [r0, #0x040] + + ldr r2, =0x841a0000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025565 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6solosabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000028 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000028 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + + ldr r2, =0x421C0216 + str r2, [r0, #0x83c] + ldr r2, =0x017B017A + str r2, [r0, #0x840] + + ldr r2, =0x4B4A4E4C + str r2, [r0, #0x848] + + ldr r2, =0x3F3F3334 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x00020025 + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x676B5313 + str r2, [r0, #0x00c] + ldr r2, =0xB66E8B63 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006B1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x84190000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x00025565 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00C03F3F + str r1, [r0, #0x068] + ldr r1, =0x0030FC03 + str r1, [r0, #0x06c] + ldr r1, =0x0FFFF000 + str r1, [r0, #0x070] + ldr r1, =0x3FF00000 + str r1, [r0, #0x074] + ldr r1, =0xFFFFF300 + str r1, [r0, #0x078] + ldr r1, =0x0F0000C3 + str r1, [r0, #0x07c] + ldr r1, =0x00000FFF + str r1, [r0, #0x080] + +#ifdef CONFIG_IMX_OPTEE +#ifndef CONFIG_MX6QP + ldr r0, =0x20e0024 + ldr r1, =0x3 + str r1, [r0] +#endif +#endif +.endm + +.macro imx6_qos_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + +#if defined(CONFIG_MX6QP) + ldr r1, =0x77177717 + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#else + ldr r1, =0x007F007F + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#endif +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_MX6S) + imx6solosabreauto_ddr_setting +#elif defined (CONFIG_MX6DL) + imx6dlsabreauto_ddr_setting +#elif defined (CONFIG_MX6QP) + imx6dqpsabreauto_ddr_setting +#elif defined (CONFIG_MX6Q) + imx6dqsabreauto_ddr_setting +#else + #error "SOC not configured" +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sabresd/Kconfig b/board/freescale/mx6sabresd/Kconfig index e87dea0d7a2..f7822390b59 100644 --- a/board/freescale/mx6sabresd/Kconfig +++ b/board/freescale/mx6sabresd/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sabresd" +config SYS_TEXT_BASE + default 0x17800000 + endif diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg new file mode 100644 index 00000000000..07fb280afe3 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000030 +DATA 4 0x020e04c0 0x00000030 +DATA 4 0x020e04c4 0x00000030 +DATA 4 0x020e04c8 0x00000030 +DATA 4 0x020e04cc 0x00000030 +DATA 4 0x020e04d0 0x00000030 +DATA 4 0x020e04d4 0x00000030 +DATA 4 0x020e04d8 0x00000030 +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000030 +DATA 4 0x020e0770 0x00000030 +DATA 4 0x020e0778 0x00000030 +DATA 4 0x020e077c 0x00000030 +DATA 4 0x020e0780 0x00000030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e0470 0x00000030 +DATA 4 0x020e0474 0x00000030 +DATA 4 0x020e0478 0x00000030 +DATA 4 0x020e047c 0x00000030 +DATA 4 0x020e0480 0x00000030 +DATA 4 0x020e0484 0x00000030 +DATA 4 0x020e0488 0x00000030 +DATA 4 0x020e048c 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x4220021F +DATA 4 0x021b0840 0x0207017E +DATA 4 0x021b483c 0x4201020C +DATA 4 0x021b4840 0x01660172 +DATA 4 0x021b0848 0x4A4D4E4D +DATA 4 0x021b4848 0x4A4F5049 +DATA 4 0x021b0850 0x3F3C3D31 +DATA 4 0x021b4850 0x3238372B +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x0002002D +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x3F435313 +DATA 4 0x021b0010 0xB66E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x00431023 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x0002556D +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFF000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg new file mode 100644 index 00000000000..41ef70363ec --- /dev/null +++ b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x43270338 +DATA 4 0x021b0840 0x03200314 +DATA 4 0x021b483c 0x431A032F +DATA 4 0x021b4840 0x03200263 +DATA 4 0x021b0848 0x4B434748 +DATA 4 0x021b4848 0x4445404C +DATA 4 0x021b0850 0x38444542 +DATA 4 0x021b4850 0x4935493A +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x555A7975 +DATA 4 0x021b0010 0xFF538F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x005A1023 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFF000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000F3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb +#endif diff --git a/board/freescale/mx6sabresd/mx6qp.cfg b/board/freescale/mx6sabresd/mx6qp.cfg new file mode 100644 index 00000000000..e53603dbac6 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6qp.cfg @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4, 0x020e0798, 0x000c0000 +DATA 4, 0x020e0758, 0x00000000 +DATA 4, 0x020e0588, 0x00000030 +DATA 4, 0x020e0594, 0x00000030 +DATA 4, 0x020e056c, 0x00000030 +DATA 4, 0x020e0578, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e057c, 0x00000030 +DATA 4, 0x020e058c, 0x00000000 +DATA 4, 0x020e059c, 0x00000030 +DATA 4, 0x020e05a0, 0x00000030 +DATA 4, 0x020e078c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e05a8, 0x00000030 +DATA 4, 0x020e05b0, 0x00000030 +DATA 4, 0x020e0524, 0x00000030 +DATA 4, 0x020e051c, 0x00000030 +DATA 4, 0x020e0518, 0x00000030 +DATA 4, 0x020e050c, 0x00000030 +DATA 4, 0x020e05b8, 0x00000030 +DATA 4, 0x020e05c0, 0x00000030 + +DATA 4, 0x020e0534, 0x00018200 +DATA 4, 0x020e0538, 0x00008000 +DATA 4, 0x020e053c, 0x00018200 +DATA 4, 0x020e0540, 0x00018200 +DATA 4, 0x020e0544, 0x00018200 +DATA 4, 0x020e0548, 0x00018200 +DATA 4, 0x020e054c, 0x00018200 +DATA 4, 0x020e0550, 0x00018200 + +DATA 4, 0x020e0774, 0x00020000 +DATA 4, 0x020e0784, 0x00000030 +DATA 4, 0x020e0788, 0x00000030 +DATA 4, 0x020e0794, 0x00000030 +DATA 4, 0x020e079c, 0x00000030 +DATA 4, 0x020e07a0, 0x00000030 +DATA 4, 0x020e07a4, 0x00000030 +DATA 4, 0x020e07a8, 0x00000030 +DATA 4, 0x020e0748, 0x00000030 +DATA 4, 0x020e05ac, 0x00000030 +DATA 4, 0x020e05b4, 0x00000030 +DATA 4, 0x020e0528, 0x00000030 +DATA 4, 0x020e0520, 0x00000030 +DATA 4, 0x020e0514, 0x00000030 +DATA 4, 0x020e0510, 0x00000030 +DATA 4, 0x020e05bc, 0x00000030 +DATA 4, 0x020e05c4, 0x00000030 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001b001e +DATA 4, 0x021b0810, 0x002e0029 +DATA 4, 0x021b480c, 0x001b002a +DATA 4, 0x021b4810, 0x0019002c +DATA 4, 0x021b083c, 0x43240334 +DATA 4, 0x021b0840, 0x0324031a +DATA 4, 0x021b483c, 0x43340344 +DATA 4, 0x021b4840, 0x03280276 +DATA 4, 0x021b0848, 0x44383A3E +DATA 4, 0x021b4848, 0x3C3C3846 +DATA 4, 0x021b0850, 0x2e303230 +DATA 4, 0x021b4850, 0x38283E34 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b481c, 0x33333333 +DATA 4, 0x021b4820, 0x33333333 +DATA 4, 0x021b4824, 0x33333333 +DATA 4, 0x021b4828, 0x33333333 +DATA 4, 0x021b08c0, 0x24912489 +DATA 4, 0x021b48c0, 0x24914452 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b48b8, 0x00000800 +DATA 4, 0x021b0004, 0x00020036 +DATA 4, 0x021b0008, 0x24444040 +DATA 4, 0x021b000c, 0x555A7955 +DATA 4, 0x021b0010, 0xFF320F64 +DATA 4, 0x021b0014, 0x01ff00db +DATA 4, 0x021b0018, 0x00011740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x005A1023 +DATA 4, 0x021b0040, 0x00000027 +DATA 4, 0x021b0400, 0x14420000 +DATA 4, 0x021b0000, 0x831A0000 +DATA 4, 0x021b0890, 0x00400C58 +DATA 4, 0x00bb0008, 0x00000000 +DATA 4, 0x00bb000c, 0x2891E41A +DATA 4, 0x00bb0038, 0x00000564 +DATA 4, 0x00bb0014, 0x00000040 +DATA 4, 0x00bb0028, 0x00000020 +DATA 4, 0x00bb002c, 0x00000020 +DATA 4, 0x021b001c, 0x04088032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x09408030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b4818, 0x00011117 +DATA 4, 0x021b0004, 0x00025576 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFF000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 +#endif diff --git a/board/freescale/mx6sabresd/mx6qp_optee.cfg b/board/freescale/mx6sabresd/mx6qp_optee.cfg new file mode 100644 index 00000000000..70b442036d9 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6qp_optee.cfg @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4, 0x020e0798, 0x000c0000 +DATA 4, 0x020e0758, 0x00000000 +DATA 4, 0x020e0588, 0x00000030 +DATA 4, 0x020e0594, 0x00000030 +DATA 4, 0x020e056c, 0x00000030 +DATA 4, 0x020e0578, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e057c, 0x00000030 +DATA 4, 0x020e058c, 0x00000000 +DATA 4, 0x020e059c, 0x00000030 +DATA 4, 0x020e05a0, 0x00000030 +DATA 4, 0x020e078c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e05a8, 0x00000030 +DATA 4, 0x020e05b0, 0x00000030 +DATA 4, 0x020e0524, 0x00000030 +DATA 4, 0x020e051c, 0x00000030 +DATA 4, 0x020e0518, 0x00000030 +DATA 4, 0x020e050c, 0x00000030 +DATA 4, 0x020e05b8, 0x00000030 +DATA 4, 0x020e05c0, 0x00000030 + +DATA 4, 0x020e0534, 0x00018200 +DATA 4, 0x020e0538, 0x00008000 +DATA 4, 0x020e053c, 0x00018200 +DATA 4, 0x020e0540, 0x00018200 +DATA 4, 0x020e0544, 0x00018200 +DATA 4, 0x020e0548, 0x00018200 +DATA 4, 0x020e054c, 0x00018200 +DATA 4, 0x020e0550, 0x00018200 + +DATA 4, 0x020e0774, 0x00020000 +DATA 4, 0x020e0784, 0x00000030 +DATA 4, 0x020e0788, 0x00000030 +DATA 4, 0x020e0794, 0x00000030 +DATA 4, 0x020e079c, 0x00000030 +DATA 4, 0x020e07a0, 0x00000030 +DATA 4, 0x020e07a4, 0x00000030 +DATA 4, 0x020e07a8, 0x00000030 +DATA 4, 0x020e0748, 0x00000030 +DATA 4, 0x020e05ac, 0x00000030 +DATA 4, 0x020e05b4, 0x00000030 +DATA 4, 0x020e0528, 0x00000030 +DATA 4, 0x020e0520, 0x00000030 +DATA 4, 0x020e0514, 0x00000030 +DATA 4, 0x020e0510, 0x00000030 +DATA 4, 0x020e05bc, 0x00000030 +DATA 4, 0x020e05c4, 0x00000030 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001b001e +DATA 4, 0x021b0810, 0x002e0029 +DATA 4, 0x021b480c, 0x001b002a +DATA 4, 0x021b4810, 0x0019002c +DATA 4, 0x021b083c, 0x43240334 +DATA 4, 0x021b0840, 0x0324031a +DATA 4, 0x021b483c, 0x43340344 +DATA 4, 0x021b4840, 0x03280276 +DATA 4, 0x021b0848, 0x44383A3E +DATA 4, 0x021b4848, 0x3C3C3846 +DATA 4, 0x021b0850, 0x2e303230 +DATA 4, 0x021b4850, 0x38283E34 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b481c, 0x33333333 +DATA 4, 0x021b4820, 0x33333333 +DATA 4, 0x021b4824, 0x33333333 +DATA 4, 0x021b4828, 0x33333333 +DATA 4, 0x021b08c0, 0x24912489 +DATA 4, 0x021b48c0, 0x24914452 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b48b8, 0x00000800 +DATA 4, 0x021b0004, 0x00020036 +DATA 4, 0x021b0008, 0x24444040 +DATA 4, 0x021b000c, 0x555A7955 +DATA 4, 0x021b0010, 0xFF320F64 +DATA 4, 0x021b0014, 0x01ff00db +DATA 4, 0x021b0018, 0x00011740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x005A1023 +DATA 4, 0x021b0040, 0x00000027 +DATA 4, 0x021b0400, 0x10420000 +DATA 4, 0x021b0000, 0x831A0000 +DATA 4, 0x021b0890, 0x00400C58 +DATA 4, 0x021b001c, 0x04088032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x09408030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b4818, 0x00011117 +DATA 4, 0x021b0004, 0x00025576 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFF000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 +#endif diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index d75dd88dbc5..e35e75b3999 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * Author: Fabio Estevam * @@ -32,6 +33,20 @@ #include "../common/pfuze.h" #include #include +#include +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#ifdef CONFIG_SATA +#include +#endif +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -53,6 +68,14 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + + #define I2C_PMIC 1 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -92,17 +115,22 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; -static void setup_iomux_enet(void) +static void fec_phy_reset(void) { - SETUP_IOMUX_PADS(enet_pads); - /* Reset AR8031 PHY */ + gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset"); gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); mdelay(10); gpio_set_value(IMX_GPIO_NR(1, 25), 1); udelay(100); } +static void setup_iomux_enet(void) +{ + SETUP_IOMUX_PADS(enet_pads); + fec_phy_reset(); +} + static iomux_v3_cfg_t const usdhc2_pads[] = { IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -144,6 +172,7 @@ static iomux_v3_cfg_t const usdhc4_pads[] = { IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; +#ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t const ecspi1_pads[] = { IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), @@ -151,6 +180,18 @@ static iomux_v3_cfg_t const ecspi1_pads[] = { IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; +static void setup_spi(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 9), "ECSPI1 CS"); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; +} +#endif + static iomux_v3_cfg_t const rgb_pads[] = { IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)), @@ -190,6 +231,7 @@ static iomux_v3_cfg_t const bl_pads[] = { static void enable_backlight(void) { SETUP_IOMUX_PADS(bl_pads); + gpio_request(DISP0_PWR_EN, "Display Power Enable"); gpio_direction_output(DISP0_PWR_EN, 1); } @@ -204,37 +246,22 @@ static void enable_lvds(struct display_info_t const *dev) enable_backlight(); } -static struct i2c_pads_info mx6q_i2c_pad_info1 = { +#ifdef CONFIG_SYS_I2C +static struct i2c_pads_info i2c_pad_info1 = { .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, .gp = IMX_GPIO_NR(4, 12) }, .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, .gp = IMX_GPIO_NR(4, 13) } }; +#endif -static struct i2c_pads_info mx6dl_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -static void setup_spi(void) -{ - SETUP_IOMUX_PADS(ecspi1_pads); -} - +#ifdef CONFIG_PCIE_IMX iomux_v3_cfg_t const pcie_pads[] = { IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */ @@ -243,7 +270,10 @@ iomux_v3_cfg_t const pcie_pads[] = { static void setup_pcie(void) { SETUP_IOMUX_PADS(pcie_pads); + gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable"); + gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset"); } +#endif iomux_v3_cfg_t const di0_pads[] = { IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */ @@ -256,6 +286,54 @@ static void setup_iomux_uart(void) SETUP_IOMUX_PADS(uart1_pads); } +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +static iomux_v3_cfg_t const epdc_enable_pads[] = { + IOMUX_PADS(PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22), + IOMUX_PADS(PAD_EIM_DA10__GPIO3_IO10), + IOMUX_PADS(PAD_EIM_DA12__GPIO3_IO12), + IOMUX_PADS(PAD_EIM_DA11__GPIO3_IO11), + IOMUX_PADS(PAD_EIM_LBA__GPIO2_IO27), + IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30), + IOMUX_PADS(PAD_EIM_CS0__GPIO2_IO23), + IOMUX_PADS(PAD_EIM_RW__GPIO2_IO26), + IOMUX_PADS(PAD_EIM_A21__GPIO2_IO17), + IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16), + IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06), + IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04), + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31), + IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27), + IOMUX_PADS(PAD_EIM_DA1__GPIO3_IO01), + IOMUX_PADS(PAD_EIM_EB1__GPIO2_IO29), + IOMUX_PADS(PAD_EIM_DA2__GPIO3_IO02), + IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04), + IOMUX_PADS(PAD_EIM_DA5__GPIO3_IO05), + IOMUX_PADS(PAD_EIM_DA6__GPIO3_IO06), +}; +#endif + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[3] = { {USDHC2_BASE_ADDR}, @@ -271,6 +349,11 @@ int board_mmc_get_env_dev(int devno) return devno - 1; } +int mmc_map_to_kernel_blk(int devno) +{ + return devno + 1; +} + int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; @@ -308,11 +391,13 @@ int board_mmc_init(bd_t *bis) switch (i) { case 0: SETUP_IOMUX_PADS(usdhc2_pads); + gpio_request(USDHC2_CD_GPIO, "USDHC2 CD"); gpio_direction_input(USDHC2_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); break; case 1: SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "USDHC3 CD"); gpio_direction_input(USDHC3_CD_GPIO); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; @@ -376,14 +461,20 @@ static int ar8031_phy_fixup(struct phy_device *phydev) unsigned short val; /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + if (!is_mx6dqp()) { + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + } - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + /* set the IO voltage to 1.8v */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); /* introduce tx clock delay */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); @@ -404,6 +495,176 @@ int board_phy_config(struct phy_device *phydev) return 0; } +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 800, + .vl_row = 600, + .vl_pixclock = 26666667, + .vl_left_margin = 8, + .vl_right_margin = 100, + .vl_upper_margin = 4, + .vl_lower_margin = 8, + .vl_hsync = 4, + .vl_vsync = 1, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 419, + .gdsp_offs = 20, + .gdoe_offs = 0, + .gdclk_offs = 5, + .num_ce = 1, +}; + +static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = { + IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), +}; + +static void setup_epdc_power(void) +{ + SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads); + + /* Setup epdc voltage */ + + /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ + /* Set as input */ + gpio_request(IMX_GPIO_NR(2, 21), "EPDC PWRSTAT"); + gpio_direction_input(IMX_GPIO_NR(2, 21)); + + /* EIM_D17 - GPIO3[17] for VCOM control */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(3, 17), "EPDC VCOM0"); + gpio_direction_output(IMX_GPIO_NR(3, 17), 1); + + /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(3, 20), "EPDC PWR WAKEUP"); + gpio_direction_output(IMX_GPIO_NR(3, 20), 1); + + /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 20), "EPDC PWR CTRL0"); + gpio_direction_output(IMX_GPIO_NR(2, 20), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + SETUP_IOMUX_PADS(epdc_enable_pads); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO */ + SETUP_IOMUX_PADS(epdc_disable_pads); +} + +static void setup_epdc(void) +{ + unsigned int reg; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /*** Set pixel clock rates for EPDC ***/ + + /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ + reg = readl(&ccm_regs->cscdr3); + reg &= ~0x7C000; + reg |= (1 << 16) | (1 << 14); + writel(reg, &ccm_regs->cscdr3); + + /* EPDC AXI clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x00C0; + writel(reg, &ccm_regs->CCGR3); + + /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ + reg = readl(&ccm_regs->cscdr2); + reg &= ~0x3FE00; + reg |= (2 << 15) | (5 << 12); + writel(reg, &ccm_regs->cscdr2); + + /* PLL5 enable (defaults to 650) */ + reg = readl(&ccm_regs->analog_pll_video); + reg &= ~((1 << 16) | (1 << 12)); + reg |= (1 << 13); + writel(reg, &ccm_regs->analog_pll_video); + + /* EPDC PIX clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x0C00; + writel(reg, &ccm_regs->CCGR3); + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 20), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 20), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 21))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 17), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 20), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 17), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 20), 0); +} +#endif + #if defined(CONFIG_VIDEO_IPUV3) static void disable_lvds(struct display_info_t const *dev) { @@ -447,21 +708,21 @@ struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, + .detect = NULL, .enable = do_enable_hdmi, .mode = { .name = "HDMI", .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15384, - .left_margin = 160, - .right_margin = 24, - .upper_margin = 29, - .lower_margin = 3, - .hsync_len = 136, - .vsync_len = 6, - .sync = FB_SYNC_EXT, + .xres = 640, + .yres = 480, + .pixclock = 39721, + .left_margin = 48, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 96, + .vsync_len = 2, + .sync = 0, .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 0, @@ -551,15 +812,48 @@ int overwrite_console(void) return 1; } +static void setup_fec(void) +{ + if (is_mx6dqp()) { + int ret; + + /* select ENET MAC0 TX clock from PLL */ + imx_iomux_set_gpr_register(5, 9, 1, 1); + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + printf("Error fec anatop clock settings!\n"); + } + + fec_phy_reset(); +} + int board_eth_init(bd_t *bis) { setup_iomux_enet(); - setup_pcie(); - return cpu_eth_init(bis); } #ifdef CONFIG_USB_EHCI_MX6 +#ifdef CONFIG_DM_USB +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + /* + * Set daisy chain for otg_pin_id on 6q. + * For 6dl, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + return 0; +} +#else #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) @@ -572,30 +866,33 @@ static iomux_v3_cfg_t const usb_hc1_pads[] = { IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; -static void setup_usb(void) -{ - SETUP_IOMUX_PADS(usb_otg_pads); - - /* - * set daisy chain for otg_pin_id on 6q. - * for 6dl, this bit is reserved - */ - imx_iomux_set_gpr_register(1, 13, 1, 0); - - SETUP_IOMUX_PADS(usb_hc1_pads); -} - int board_ehci_hcd_init(int port) { u32 *usbnc_usb_ctrl; - if (port > 1) - return -EINVAL; + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg_pads); + + /* + * Set daisy chain for otg_pin_id on 6q. + * For 6dl, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); - usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + port * 4); - setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + break; + case 1: + SETUP_IOMUX_PADS(usb_hc1_pads); + gpio_request(IMX_GPIO_NR(1, 29), "USB HC1 Power Enable"); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } return 0; } @@ -619,10 +916,14 @@ int board_ehci_power(int port, int on) return 0; } #endif +#endif int board_early_init_f(void) { setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif return 0; } @@ -635,54 +936,392 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif - if (is_mx6dq() || is_mx6dqp()) - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); - else - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); -#if defined(CONFIG_VIDEO_IPUV3) - setup_display(); + +#ifdef CONFIG_SYS_I2C + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif -#ifdef CONFIG_USB_EHCI_MX6 - setup_usb(); + +#ifdef CONFIG_PCIE_IMX + setup_pcie(); +#endif + +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) + setup_epdc(); #endif +#ifdef CONFIG_SATA + setup_sata(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +#ifdef CONFIG_POWER +int power_init_board(void) +{ + struct pmic *pfuze; + unsigned int reg; + int ret; + + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; + + if (is_mx6dqp()) + ret = pfuze_mode_init(pfuze, APS_APS); + else + ret = pfuze_mode_init(pfuze, APS_PFM); + + if (ret < 0) + return ret; + /* VGEN3 and VGEN5 corrected on i.mx6qp board */ + if (!is_mx6dqp()) { + /* Increase VGEN3 from 2.5 to 2.8V */ + pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; + pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg); + + /* Increase VGEN5 from 2.8 to 3V */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_3_00V; + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg); + } + + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1f; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + /* set SW2/VDDARM staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW2STBY, ®); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW2CONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg); + } else { + /* set SW1AB staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + } + return 0; } +#elif defined(CONFIG_DM_PMIC_PFUZE100) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; unsigned int reg; int ret; - p = pfuze_common_init(I2C_PMIC); - if (!p) + dev = pfuze_common_init(); + if (!dev) return -ENODEV; - ret = pfuze_mode_init(p, APS_PFM); + if (is_mx6dqp()) + ret = pfuze_mode_init(dev, APS_APS); + else + ret = pfuze_mode_init(dev, APS_PFM); if (ret < 0) return ret; - /* Increase VGEN3 from 2.5 to 2.8V */ - pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_2_80V; - pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); + /* VGEN3 and VGEN5 corrected on i.mx6qp board */ + if (!is_mx6dqp()) { + /* Increase VGEN3 from 2.5 to 2.8V */ + reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; + pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg); + + /* Increase VGEN5 from 2.8 to 3V */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_3_00V; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + } - /* Increase VGEN5 from 2.8 to 3V */ - pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_3_00V; - pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1f; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + + /* set SW2/VDDARM staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW2STBY); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(dev, PFUZE100_SW2STBY, reg); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW2CONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW2CONF, reg); + } else { + /* set SW1AB staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + } return 0; } +#endif -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) +#ifdef CONFIG_LDO_BYPASS_CHECK +#ifdef CONFIG_POWER +void ldo_mode_set(int ldo_bypass) { - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; + unsigned int value; + int is_400M; + unsigned char vddarm; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + value |= 0x29; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } else { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + } + /* increase VDDSOC to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + } + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + if (is_mx6dqp()) { + /* decrease VDDARM for 400Mhz DQP:1.1V*/ + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + value |= 0x1c; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } else { + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + if (is_mx6dl()) + value |= 0x27; + else + value |= 0x20; + + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + } + /* increase VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x28; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + /* + * MX6Q/DQP: + * VDDARM:1.15V@800M; VDDSOC:1.175V@800M + * VDDARM:0.975V@400M; VDDSOC:1.175V@400M + * MX6DL: + * VDDARM:1.175V@800M; VDDSOC:1.175V@800M + * VDDARM:1.15V@400M; VDDSOC:1.175V@400M + */ + is_400M = set_anatop_bypass(2); + if (is_mx6dqp()) { + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + if (is_400M) + value |= 0x17; + else + value |= 0x1e; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } + + if (is_400M) { + if (is_mx6dl()) + vddarm = 0x22; + else + vddarm = 0x1b; + } else { + if (is_mx6dl()) + vddarm = 0x23; + else + vddarm = 0x22; + } + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.175V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x23; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } } +#elif defined(CONFIG_DM_PMIC_PFUZE100) +void ldo_mode_set(int ldo_bypass) +{ + int is_400M; + unsigned char vddarm; + struct udevice *dev; + int ret; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29); + } else { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d); + } + /* increase VDDSOC to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d); + } + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + if (is_mx6dqp()) { + /* decrease VDDARM for 400Mhz DQP:1.1V*/ + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1c); + } else { + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + if (is_mx6dl()) + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x27); + else + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20); + } + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28); + + /* + * MX6Q/DQP: + * VDDARM:1.15V@800M; VDDSOC:1.175V@800M + * VDDARM:0.975V@400M; VDDSOC:1.175V@400M + * MX6DL: + * VDDARM:1.175V@800M; VDDSOC:1.175V@800M + * VDDARM:1.15V@400M; VDDSOC:1.175V@400M + */ + is_400M = set_anatop_bypass(2); + if (is_mx6dqp()) { + if (is_400M) + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x17); + else + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1e); + } + + if (is_400M) { + if (is_mx6dl()) + vddarm = 0x22; + else + vddarm = 0x1b; + } else { + if (is_mx6dl()) + vddarm = 0x23; + else + vddarm = 0x22; + } + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif #endif #ifdef CONFIG_CMD_BMODE @@ -702,6 +1341,11 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "SABRESD"); @@ -713,6 +1357,10 @@ int board_late_init(void) env_set("board_rev", "MX6DL"); #endif +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + return 0; } @@ -722,6 +1370,36 @@ int checkboard(void) return 0; } +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY + +#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5) +iomux_v3_cfg_t const recovery_key_pads[] = { + IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +int is_recovery_key_pressing(void) +{ + int button_pressed = 0; + + /* Check Recovery Combo Button press or not. */ + SETUP_IOMUX_PADS(recovery_key_pads); + + gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key"); + gpio_direction_input(GPIO_VOL_DN_KEY); + + if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return button_pressed; +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ + +#endif /*CONFIG_FSL_FASTBOOT*/ + #ifdef CONFIG_SPL_BUILD #include #include @@ -730,6 +1408,7 @@ int checkboard(void) #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { + gpio_request(KEY_VOL_UP, "KEY Volume UP"); gpio_direction_input(KEY_VOL_UP); /* Only enter in Falcon mode if KEY_VOL_UP is pressed */ diff --git a/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg new file mode 100644 index 00000000000..ec37548dcc4 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4, 0x020e0774, 0x000C0000 +DATA 4, 0x020e0754, 0x00000000 +DATA 4, 0x020e04ac, 0x00000030 +DATA 4, 0x020e04b0, 0x00000030 +DATA 4, 0x020e0464, 0x00000030 +DATA 4, 0x020e0490, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e0494, 0x00000030 +DATA 4, 0x020e04a0, 0x00000000 +DATA 4, 0x020e04b4, 0x00000030 +DATA 4, 0x020e04b8, 0x00000030 +DATA 4, 0x020e076c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e04bc, 0x00000030 +DATA 4, 0x020e04c0, 0x00000030 +DATA 4, 0x020e04c4, 0x00000030 +DATA 4, 0x020e04c8, 0x00000030 +DATA 4, 0x020e0760, 0x00020000 +DATA 4, 0x020e0764, 0x00000030 +DATA 4, 0x020e0770, 0x00000030 +DATA 4, 0x020e0778, 0x00000030 +DATA 4, 0x020e077c, 0x00000030 +DATA 4, 0x020e0470, 0x00000030 +DATA 4, 0x020e0474, 0x00000030 +DATA 4, 0x020e0478, 0x00000030 +DATA 4, 0x020e047c, 0x00000030 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001F001F +DATA 4, 0x021b0810, 0x001F001F +DATA 4, 0x021b083c, 0x42190219 +DATA 4, 0x021b0840, 0x017B0177 +DATA 4, 0x021b0848, 0x4B4D4E4D +DATA 4, 0x021b0850, 0x3F3E2D36 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b0004, 0x0002002D +DATA 4, 0x021b0008, 0x00333030 +DATA 4, 0x021b000c, 0x3F435313 +DATA 4, 0x021b0010, 0xB66E8B63 +DATA 4, 0x021b0014, 0x01FF00DB +DATA 4, 0x021b0018, 0x00001740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x00431023 +DATA 4, 0x021b0040, 0x00000017 +DATA 4, 0x021b0000, 0x83190000 +DATA 4, 0x021b001c, 0x04008032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x05208030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b0004, 0x0002556D +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFF000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif diff --git a/board/freescale/mx6sabresd/plugin.S b/board/freescale/mx6sabresd/plugin.S new file mode 100644 index 00000000000..d99349f48e0 --- /dev/null +++ b/board/freescale/mx6sabresd/plugin.S @@ -0,0 +1,690 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6dqpsabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00018200 + str r1, [r0, #0x534] + ldr r1, =0x00008000 + str r1, [r0, #0x538] + ldr r1, =0x00018200 + str r1, [r0, #0x53c] + str r1, [r0, #0x540] + str r1, [r0, #0x544] + str r1, [r0, #0x548] + str r1, [r0, #0x54c] + str r1, [r0, #0x550] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001b001e + str r2, [r0, #0x80c] + ldr r2, =0x002e0029 + str r2, [r0, #0x810] + + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x001b002a + str r2, [r1, #0x80c] + ldr r2, =0x0019002c + str r2, [r1, #0x810] + + ldr r2, =0x43240334 + str r2, [r0, #0x83c] + ldr r2, =0x0324031a + str r2, [r0, #0x840] + + ldr r2, =0x43340344 + str r2, [r1, #0x83c] + ldr r2, =0x03280276 + str r2, [r1, #0x840] + + ldr r2, =0x44383A3E + str r2, [r0, #0x848] + ldr r2, =0x3C3C3846 + str r2, [r1, #0x848] + + ldr r2, =0x2e303230 + str r2, [r0, #0x850] + ldr r2, =0x38283E34 + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x24912489 + str r2, [r0, #0x8c0] + ldr r2, =0x24914452 + str r2, [r1, #0x8c0] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x24444040 + str r2, [r0, #0x008] + + ldr r2, =0x555A7955 + str r2, [r0, #0x00c] + ldr r2, =0xFF320F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x005A1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x14420000 + str r2, [r0, #0x400] + + ldr r2, =0x831A0000 + str r2, [r0, #0x000] + + ldr r2, =0x00400C58 + str r2, [r0, #0x890] + + ldr r3, =0x00bb0000 + ldr r2, =0x00000000 + str r2, [r3, #0x008] + ldr r2, =0x2891E41A + str r2, [r3, #0x00C] + ldr r2, =0x00000564 + str r2, [r3, #0x038] + ldr r2, =0x00000040 + str r2, [r3, #0x014] + ldr r2, =0x00000020 + str r2, [r3, #0x028] + ldr r2, =0x00000020 + str r2, [r3, #0x02c] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dqsabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x43270338 + str r2, [r0, #0x83c] + ldr r2, =0x03200314 + str r2, [r0, #0x840] + + ldr r2, =0x431A032F + str r2, [r1, #0x83c] + ldr r2, =0x03200263 + str r2, [r1, #0x840] + + ldr r2, =0x4B434748 + str r2, [r0, #0x848] + ldr r2, =0x4445404C + str r2, [r1, #0x848] + + ldr r2, =0x38444542 + str r2, [r0, #0x850] + ldr r2, =0x4935493A + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x09444040 + str r2, [r0, #0x008] + + ldr r2, =0x555A7975 + str r2, [r0, #0x00c] + ldr r2, =0xFF538F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x005A1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x831A0000 + str r2, [r0, #0x000] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dlsabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + str r1, [r0, #0x4cc] + str r1, [r0, #0x4d0] + str r1, [r0, #0x4d4] + str r1, [r0, #0x4d8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000030 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x780] + str r1, [r0, #0x784] + str r1, [r0, #0x78c] + str r1, [r0, #0x748] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + str r1, [r0, #0x480] + str r1, [r0, #0x484] + str r1, [r0, #0x488] + str r1, [r0, #0x48c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001f001f + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x4220021F + str r2, [r0, #0x83c] + ldr r2, =0x0207017E + str r2, [r0, #0x840] + + ldr r2, =0x4201020C + str r2, [r1, #0x83c] + ldr r2, =0x01660172 + str r2, [r1, #0x840] + + ldr r2, =0x4A4D4E4D + str r2, [r0, #0x848] + ldr r2, =0x4A4F5049 + str r2, [r1, #0x848] + + ldr r2, =0x3F3C3D31 + str r2, [r0, #0x850] + ldr r2, =0x3238372B + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x0002002D + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x3F435313 + str r2, [r0, #0x00c] + ldr r2, =0xB66E8B63 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x00431023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x831A0000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x0002556D + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6solosabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000030 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + + ldr r2, =0x42190219 + str r2, [r0, #0x83c] + ldr r2, =0x017B0177 + str r2, [r0, #0x840] + + ldr r2, =0x4B4D4E4D + str r2, [r0, #0x848] + + ldr r2, =0x3F3E2D36 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x0002002D + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x3F435313 + str r2, [r0, #0x00c] + ldr r2, =0xB66E8B63 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x00431023 + str r2, [r0, #0x030] + ldr r2, =0x00000017 + str r2, [r0, #0x040] + + ldr r2, =0x83190000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x0002556D + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00C03F3F + str r1, [r0, #0x068] + ldr r1, =0x0030FC03 + str r1, [r0, #0x06c] + ldr r1, =0x0FFFF000 + str r1, [r0, #0x070] + ldr r1, =0x3FF00000 + str r1, [r0, #0x074] + ldr r1, =0x00FFF300 + str r1, [r0, #0x078] + ldr r1, =0x0F0000C3 + str r1, [r0, #0x07c] + ldr r1, =0x000003FF + str r1, [r0, #0x080] +#ifdef CONFIG_IMX_OPTEE +#ifndef CONFIG_MX6QP + ldr r0, =0x20e0024 + ldr r1, =0x3 + str r1, [r0] +#endif +#endif +.endm + +.macro imx6_qos_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + +#if defined(CONFIG_MX6QP) + ldr r1, =0x77177717 + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#else + ldr r1, =0x007F007F + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#endif +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_MX6S) + imx6solosabresd_ddr_setting +#elif defined (CONFIG_MX6DL) + imx6dlsabresd_ddr_setting +#elif defined (CONFIG_MX6QP) + imx6dqpsabresd_ddr_setting +#elif defined (CONFIG_MX6Q) + imx6dqsabresd_ddr_setting +#else + #error "SOC not configured" +#endif + +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6slevk/Kconfig b/board/freescale/mx6slevk/Kconfig index 18482b551e5..42a2debf195 100644 --- a/board/freescale/mx6slevk/Kconfig +++ b/board/freescale/mx6slevk/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6slevk" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg index 9722eb5d7e1..e6d62f576cd 100644 --- a/board/freescale/mx6slevk/imximage.cfg +++ b/board/freescale/mx6slevk/imximage.cfg @@ -1,5 +1,6 @@ /* - * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * SPDX-License-Identifier: GPL-2.0+ * @@ -22,9 +23,11 @@ IMAGE_VERSION 2 BOOT_FROM sd -/* - * Secure boot support - */ +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6slevk/plugin.bin 0x00907000 +#else + #ifdef CONFIG_SECURE_BOOT CSF CONFIG_CSF_SIZE #endif @@ -50,6 +53,11 @@ DATA 4 0x020c4078 0xffffffff DATA 4 0x020c407c 0xffffffff DATA 4 0x020c4080 0xffffffff +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x020e0024 0x00000001 +CHECK_BITS_SET 4 0x020e0024 0x1 +#endif + DATA 4 0x020e0344 0x00003030 DATA 4 0x020e0348 0x00003030 DATA 4 0x020e034c 0x00003030 @@ -106,6 +114,7 @@ DATA 4 0x021b0038 0x00190778 DATA 4 0x021b0008 0x00000000 DATA 4 0x021b0040 0x0000004f DATA 4 0x021b0000 0xc3110000 +DATA 4 0x021b001c 0x00008010 DATA 4 0x021b001c 0x003f8030 DATA 4 0x021b001c 0xff0a8030 DATA 4 0x021b001c 0x82018030 @@ -122,3 +131,4 @@ DATA 4 0x021b08b8 0x00000800 DATA 4 0x021b0004 0x00025564 DATA 4 0x021b0404 0x00011006 DATA 4 0x021b001c 0x00000000 +#endif diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 1bc7356c447..431ae47f9c2 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,19 @@ #include #include #include "../common/pfuze.h" +#include +#include +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include "../common/recovery_keypad.h" +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -45,11 +59,22 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_FAST) +#define ELAN_INTR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_HYS) + +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + #define ETH_PHY_POWER IMX_GPIO_NR(4, 21) int dram_init(void) @@ -59,6 +84,19 @@ int dram_init(void) return 0; } +phys_size_t get_effective_memsize(void) +{ + return SZ_512M; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -121,6 +159,12 @@ static iomux_v3_cfg_t const fec_pads[] = { MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static iomux_v3_cfg_t const elan_pads[] = { + MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 | MUX_PAD_CTRL(ELAN_INTR_PAD_CTRL), + MX6_PAD_KEY_COL6__GPIO_4_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + #ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t ecspi1_pads[] = { MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -137,9 +181,60 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) static void setup_spi(void) { imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + + gpio_request(IMX_GPIO_NR(4, 11), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(4, 11), 0); } #endif +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX6_PAD_EPDC_D0__EPDC_SDDO_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D1__EPDC_SDDO_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D2__EPDC_SDDO_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D3__EPDC_SDDO_3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D4__EPDC_SDDO_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D5__EPDC_SDDO_5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D6__EPDC_SDDO_6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D7__EPDC_SDDO_7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_BDR0__EPDC_BDR_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX6_PAD_EPDC_D0__GPIO_1_7, + MX6_PAD_EPDC_D1__GPIO_1_8, + MX6_PAD_EPDC_D2__GPIO_1_9, + MX6_PAD_EPDC_D3__GPIO_1_10, + MX6_PAD_EPDC_D4__GPIO_1_11, + MX6_PAD_EPDC_D5__GPIO_1_12, + MX6_PAD_EPDC_D6__GPIO_1_13, + MX6_PAD_EPDC_D7__GPIO_1_14, + MX6_PAD_EPDC_GDCLK__GPIO_1_31, + MX6_PAD_EPDC_GDSP__GPIO_2_2, + MX6_PAD_EPDC_GDOE__GPIO_2_0, + MX6_PAD_EPDC_GDRL__GPIO_2_1, + MX6_PAD_EPDC_SDCLK__GPIO_1_23, + MX6_PAD_EPDC_SDOE__GPIO_1_25, + MX6_PAD_EPDC_SDLE__GPIO_1_24, + MX6_PAD_EPDC_SDSHR__GPIO_1_26, + MX6_PAD_EPDC_BDR0__GPIO_2_5, + MX6_PAD_EPDC_SDCE0__GPIO_1_27, + MX6_PAD_EPDC_SDCE1__GPIO_1_28, + MX6_PAD_EPDC_SDCE2__GPIO_1_29, +}; +#endif + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -160,53 +255,206 @@ int board_mmc_get_env_dev(int devno) return devno; } -#ifdef CONFIG_DM_PMIC_PFUZE100 +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .sda = { + .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC, + .gp = IMX_GPIO_NR(3, 13), + }, + .scl = { + .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC, + .gp = IMX_GPIO_NR(3, 12), + }, +}; +#endif + +#ifdef CONFIG_POWER int power_init_board(void) { - struct udevice *dev; + struct pmic *pfuze; + unsigned int reg; int ret; - u32 dev_id, rev_id, i; - u32 switch_num = 6; - u32 offset = PFUZE100_SW1CMODE; - ret = pmic_get("pfuze100", &dev); - if (ret == -ENODEV) - return 0; + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; - if (ret != 0) + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) return ret; - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - /* set SW1AB staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); /* set SW1C staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); - /* Init mode to APS_PFM */ - pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); + return 0; +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + unsigned int reg; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + /* set SW1AB staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); - for (i = 0; i < switch_num - 1; i++) - pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); return 0; } #endif +#ifdef CONFIG_LDO_BYPASS_CHECK +#ifdef CONFIG_POWER +void ldo_mode_set(int ldo_bypass) +{ + u32 value; + int is_400M; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No pmic!\n"); + return; + } + + /* swith to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM to 1.1V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= 0x20; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* increase VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x28; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + is_400M = set_anatop_bypass(0); + + /* + * MX6SL: VDDARM:1.175V@800M; VDDSOC:1.175V@800M + * VDDARM:0.975V@400M; VDDSOC:1.175V@400M + */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + if (is_400M) + value |= 0x1b; + else + value |= 0x23; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.175V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x23; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20); + + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28); + + is_400M = set_anatop_bypass(0); + if (is_400M) + vddarm = 0x1b; + else + vddarm = 0x23; + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#endif + #ifdef CONFIG_FEC_MXC int board_eth_init(bd_t *bis) { - setup_iomux_fec(); - return cpu_eth_init(bis); } @@ -214,6 +462,7 @@ static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + setup_iomux_fec(); /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); @@ -221,6 +470,52 @@ static int setup_fec(void) } #endif +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OTG1 */ + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), + /* OTG2 */ + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -228,20 +523,261 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_MXC_EPDC +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 800, + .vl_row = 600, + .vl_rot = 0, + .vl_pixclock = 26666667, + .vl_left_margin = 8, + .vl_right_margin = 100, + .vl_upper_margin = 4, + .vl_lower_margin = 8, + .vl_hsync = 4, + .vl_vsync = 1, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 419, + .gdsp_offs = 20, + .gdoe_offs = 0, + .gdclk_offs = 5, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 13), "EPDC PWRSTAT"); + gpio_direction_input(IMX_GPIO_NR(2, 13)); + + /* EPDC_VCOM0 - GPIO2[3] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 3), "EPDC VCOM0"); + gpio_direction_output(IMX_GPIO_NR(2, 3), 1); + + /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 14), "EPDC PWR WAKEUP"); + gpio_direction_output(IMX_GPIO_NR(2, 14), 1); + + /* EPDC_PWRCTRL0 - GPIO2[7] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 7), "EPDC PWRCTRL0"); + gpio_direction_output(IMX_GPIO_NR(2, 7), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + unsigned int reg; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /*** Set pixel clock rates for EPDC ***/ + + /* EPDC AXI clk from PFD_400M, set to 396/2 = 198MHz */ + reg = readl(&ccm_regs->chsccdr); + reg &= ~0x3F000; + reg |= (0x4 << 15) | (1 << 12); + writel(reg, &ccm_regs->chsccdr); + + /* EPDC AXI clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x0030; + writel(reg, &ccm_regs->CCGR3); + + /* EPDC PIX clk from PFD_540M, set to 540/4/5 = 27MHz */ + reg = readl(&ccm_regs->cscdr2); + reg &= ~0x03F000; + reg |= (0x5 << 15) | (4 << 12); + writel(reg, &ccm_regs->cscdr2); + + reg = readl(&ccm_regs->cbcmr); + reg &= ~0x03800000; + reg |= (0x3 << 23); + writel(reg, &ccm_regs->cbcmr); + + /* EPDC PIX clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x0C00; + writel(reg, &ccm_regs->CCGR3); + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 13))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 0); +} +#endif + +void setup_elan_pads(void) +{ +#define TOUCH_CS IMX_GPIO_NR(2, 9) +#define TOUCH_INT IMX_GPIO_NR(2, 10) +#define TOUCH_RST IMX_GPIO_NR(4, 4) + imx_iomux_v3_setup_multiple_pads(elan_pads, ARRAY_SIZE(elan_pads)); + gpio_request(TOUCH_CS, "TOUCH CS"); + gpio_request(TOUCH_INT, "TOUCH Interrupt"); + gpio_request(TOUCH_RST, "TOUCH Reset"); +} + int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_MXC_SPI - gpio_request(IMX_GPIO_NR(4, 11), "spi_cs"); - setup_spi(); +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif + setup_elan_pads(); + #ifdef CONFIG_FEC_MXC setup_fec(); #endif +#ifdef CONFIG_MXC_EPDC + setup_epdc(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + + return 0; +} + +void elan_init(void) +{ + gpio_direction_input(TOUCH_INT); + /* + * If epdc panel not plugged in, gpio_get_value(TOUCH_INT) will + * return 1. And no need to mdelay, which will make i2c operation + * slow. + * If epdc panel plugged in, gpio_get_value(TOUCH_INT) will + * return 0. And elan init flow will be executed. + */ + if (gpio_get_value(TOUCH_INT)) + return; + gpio_direction_output(TOUCH_CS , 1); + gpio_set_value(TOUCH_CS, 0); + gpio_direction_output(TOUCH_RST , 1); + gpio_set_value(TOUCH_RST, 0); + mdelay(10); + gpio_set_value(TOUCH_RST, 1); + gpio_set_value(TOUCH_CS, 1); + mdelay(100); +} + +/* + * This function overwrite the function defined in + * drivers/i2c/mxc_i2c.c, which is a weak symbol + */ +void i2c_force_reset_slave(void) +{ + elan_init(); +} + +int board_late_init(void) +{ + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif return 0; } @@ -252,6 +788,40 @@ int checkboard(void) return 0; } +#ifdef CONFIG_MXC_KPD +#define MX6SL_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_120ohm) + +iomux_v3_cfg_t const mxc_kpd_pads[] = { + (MX6_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)), + (MX6_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)), + (MX6_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)), + (MX6_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)), + + (MX6_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), + (MX6_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), + (MX6_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), + (MX6_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), +}; +int setup_mxc_kpd(void) +{ + imx_iomux_v3_setup_multiple_pads(mxc_kpd_pads, + ARRAY_SIZE(mxc_kpd_pads)); + + return 0; +} +#endif /*CONFIG_MXC_KPD*/ + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return is_recovery_keypad_pressing(); +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + #ifdef CONFIG_SPL_BUILD #include #include diff --git a/board/freescale/mx6slevk/plugin.S b/board/freescale/mx6slevk/plugin.S new file mode 100644 index 00000000000..e23146d74a4 --- /dev/null +++ b/board/freescale/mx6slevk/plugin.S @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6slevk_ddr_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00260324 + str r1, [r0, #0x018] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00020000 + str r1, [r0, #0x5c0] + ldr r1, =0x00000000 + str r1, [r0, #0x5b4] + + ldr r1, =0x00000028 + str r1, [r0, #0x338] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x31c] + str r1, [r0, #0x320] + + ldr r1, =0x00000000 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x5ac] + str r1, [r0, #0x5c8] + + ldr r1, =0x00020000 + str r1, [r0, #0x5b0] + + ldr r1, =0x00003030 + str r1, [r0, #0x344] + str r1, [r0, #0x348] + str r1, [r0, #0x34c] + str r1, [r0, #0x350] + + ldr r1, =0x00080000 + str r1, [r0, #0x5d0] + + ldr r1, =0x00000030 + str r1, [r0, #0x5c4] + str r1, [r0, #0x5cc] + str r1, [r0, #0x5d4] + str r1, [r0, #0x5d8] + + str r1, [r0, #0x30c] + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x318] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + + ldr r2, =0x1b4700c7 + str r2, [r0, #0x85c] + + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x00300000 + str r2, [r0, #0x890] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + + ldr r2, =0x4241444a + str r2, [r0, #0x848] + + ldr r2, =0x3030312b + str r2, [r0, #0x850] + + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + + ldr r2, =0x00000000 + str r2, [r0, #0x840] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33374133 + str r2, [r0, #0x00c] + + ldr r2, =0x00020024 + str r2, [r0, #0x004] + + ldr r2, =0x00100A82 + str r2, [r0, #0x010] + ldr r2, =0x00000093 + str r2, [r0, #0x014] + ldr r2, =0x00001688 + str r2, [r0, #0x018] + ldr r2, =0x0F9F26D2 + str r2, [r0, #0x02c] + + ldr r2, =0x0000020E + str r2, [r0, #0x030] + ldr r2, =0x00190778 + str r2, [r0, #0x038] + ldr r2, =0x00000000 + str r2, [r0, #0x008] + ldr r2, =0x0000004F + str r2, [r0, #0x040] + ldr r2, =0xC3110000 + str r2, [r0, #0x000] + + ldr r2, =0x00008010 + str r2, [r0, #0x01c] + ldr r2, =0x003F8030 + str r2, [r0, #0x01c] + ldr r2, =0xFF0A8030 + str r2, [r0, #0x01c] + ldr r2, =0x82018030 + str r2, [r0, #0x01c] + ldr r2, =0x04028030 + str r2, [r0, #0x01c] + ldr r2, =0x02038030 + str r2, [r0, #0x01c] + ldr r2, =0xFF0A8038 + str r2, [r0, #0x01c] + ldr r2, =0x82018038 + str r2, [r0, #0x01c] + ldr r2, =0x04028038 + str r2, [r0, #0x01c] + ldr r2, =0x02038038 + str r2, [r0, #0x01c] + + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + + ldr r2, =0x00001800 + str r2, [r0, #0x020] + + ldr r2, =0x00000000 + str r2, [r0, #0x818] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x00025564 + str r2, [r0, #0x004] + + ldr r2, =0x00011006 + str r2, [r0, #0x404] + + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6slevk_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sll_arm2/Kconfig b/board/freescale/mx6sll_arm2/Kconfig new file mode 100644 index 00000000000..5e7bed63c79 --- /dev/null +++ b/board/freescale/mx6sll_arm2/Kconfig @@ -0,0 +1,18 @@ +if TARGET_MX6SLL_ARM2 + +config SYS_BOARD + default "mx6sll_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6sll_arm2" + +config LPDDR2_BOARD + bool "set if the board uses the LPDDR2 not default LPDDR3" + +config SYS_TEXT_BASE + default 0x87800000 + +endif diff --git a/board/freescale/mx6sll_arm2/Makefile b/board/freescale/mx6sll_arm2/Makefile new file mode 100644 index 00000000000..267788ea28d --- /dev/null +++ b/board/freescale/mx6sll_arm2/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sll_arm2.o diff --git a/board/freescale/mx6sll_arm2/imximage.cfg b/board/freescale/mx6sll_arm2/imximage.cfg new file mode 100644 index 00000000000..898411f8010 --- /dev/null +++ b/board/freescale/mx6sll_arm2/imximage.cfg @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sll_arm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E0550 0x00080000 +DATA 4 0x020E0534 0x00000000 +DATA 4 0x020E02AC 0x00000030 +DATA 4 0x020E0548 0x00000030 +DATA 4 0x020E052C 0x00000030 +DATA 4 0x020E0530 0x00020000 +DATA 4 0x020E02B0 0x00003030 +DATA 4 0x020E02B4 0x00003030 +DATA 4 0x020E02B8 0x00003030 +DATA 4 0x020E02BC 0x00003030 +DATA 4 0x020E0540 0x00020000 +DATA 4 0x020E0544 0x00000030 +DATA 4 0x020E054C 0x00000030 +DATA 4 0x020E0554 0x00000030 +DATA 4 0x020E0558 0x00000030 +DATA 4 0x020E0294 0x00000030 +DATA 4 0x020E0298 0x00000030 +DATA 4 0x020E029C 0x00000030 +DATA 4 0x020E02A0 0x00000030 +DATA 4 0x020E02C0 0x00082030 + +DATA 4 0x021B001C 0x00008000 + +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B085c 0x084700C7 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B0848 0x3C3A3C3C +DATA 4 0x021B0850 0x24293625 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B0824 0x33333333 +DATA 4 0x021B0828 0x33333333 + +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B0834 0xf3333333 +DATA 4 0x021B0838 0xf3333333 +DATA 4 0x021B08C0 0x24922492 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B000C 0x53574333 +DATA 4 0x021B0010 0x00100B22 +DATA 4 0x021B0038 0x00170778 +DATA 4 0x021B0014 0x00C700DB +DATA 4 0x021B0018 0x00201718 +DATA 4 0x021B002C 0x0F9F26D2 +DATA 4 0x021B0030 0x009F0E10 +DATA 4 0x021B0040 0x0000005F +DATA 4 0x021B0000 0xC4190000 + +DATA 4 0x021B001C 0x00008050 +DATA 4 0x021B001C 0x00008058 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0x003F8038 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0xFF0A8038 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x04028038 +DATA 4 0x021B001C 0x83018030 +DATA 4 0x021B001C 0x83018038 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B001C 0x01038038 + +DATA 4 0x021B083C 0x20000000 + +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6sll_arm2/imximage_lpddr2.cfg b/board/freescale/mx6sll_arm2/imximage_lpddr2.cfg new file mode 100644 index 00000000000..aff19c18920 --- /dev/null +++ b/board/freescale/mx6sll_arm2/imximage_lpddr2.cfg @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sll_arm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E0550 0x00080000 +DATA 4 0x020E0534 0x00000000 +DATA 4 0x020E02AC 0x00000030 +DATA 4 0x020E0548 0x00000030 +DATA 4 0x020E052C 0x00000030 +DATA 4 0x020E0530 0x00020000 +DATA 4 0x020E02B0 0x00003030 +DATA 4 0x020E02B4 0x00003030 +DATA 4 0x020E02B8 0x00003030 +DATA 4 0x020E02BC 0x00003030 +DATA 4 0x020E0540 0x00020000 +DATA 4 0x020E0544 0x00000030 +DATA 4 0x020E054C 0x00000030 +DATA 4 0x020E0554 0x00000030 +DATA 4 0x020E0558 0x00000030 +DATA 4 0x020E0294 0x00000030 +DATA 4 0x020E0298 0x00000030 +DATA 4 0x020E029C 0x00000030 +DATA 4 0x020E02A0 0x00000030 +DATA 4 0x020E02C0 0x00082030 + +DATA 4 0x021B001C 0x00008000 + +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B085c 0x084700C7 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B0848 0x3A383C40 +DATA 4 0x021B0850 0x242C3020 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B0824 0x33333333 +DATA 4 0x021B0828 0x33333333 + +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B0834 0xf3333333 +DATA 4 0x021B0838 0xf3333333 +DATA 4 0x021B08C0 0x24922492 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B000C 0x53574333 +DATA 4 0x021B0010 0x00100A82 +DATA 4 0x021B0038 0x00170777 +DATA 4 0x021B0014 0x00C70093 +DATA 4 0x021B0018 0x00201708 +DATA 4 0x021B002C 0x0F9F26D2 +DATA 4 0x021B0030 0x009F0E10 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0xC3110000 + +DATA 4 0x021B001C 0x00008050 +DATA 4 0x021B001C 0x00008058 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0x003F8038 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0xFF0A8038 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x04028038 +DATA 4 0x021B001C 0x82018030 +DATA 4 0x021B001C 0x82018038 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B001C 0x01038038 + +DATA 4 0x021B083C 0x20000000 + +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6sll_arm2/mx6sll_arm2.c b/board/freescale/mx6sll_arm2/mx6sll_arm2.c new file mode 100644 index 00000000000..4f6a34f5997 --- /dev/null +++ b/board/freescale/mx6sll_arm2/mx6sll_arm2.c @@ -0,0 +1,755 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EPD */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + /* conflict with usb_otg2_pwr */ + .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_I2C1_SCL__GPIO3_IO12 | PC, + .gp = IMX_GPIO_NR(3, 12), + }, + .sda = { + /* conflict with usb_otg2_oc */ + .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_I2C1_SDA__GPIO3_IO13 | PC, + .gp = IMX_GPIO_NR(3, 13), + }, +}; + +/* I2C2 for LCD and ADV */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_I2C2_SCL__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_I2C2_SCL__GPIO3_IO14 | PC, + .gp = IMX_GPIO_NR(3, 14), + }, + .sda = { + .i2c_mode = MX6_PAD_I2C2_SDA__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_I2C2_SDA__GPIO3_IO15 | PC, + .gp = IMX_GPIO_NR(3, 15), + }, +}; + +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const led_pads[] = { + MX6_PAD_EPDC_VCOM1__GPIO2_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* 8bit SD1 */ +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA4__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA5__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA6__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA7__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD */ + MX6_PAD_KEY_ROW7__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* WP */ + MX6_PAD_GPIO4_IO22__SD1_WP | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* EMMC */ +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* DQS */ + MX6_PAD_GPIO4_IO21__SD2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_SD2_RESET__GPIO4_IO27 | MUX_PAD_CTRL(USDHC_PAD_CTRL | PAD_CTL_LVE), +}; + +/* Wifi SD */ +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD */ + MX6_PAD_REF_CLK_32K__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); + + SETUP_IOMUX_PADS(led_pads); +} + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8, 1}, + {USDHC2_BASE_ADDR, 0, 8, 0, 1}, /* fixed 1.8v IO voltage for eMMC chip */ + {USDHC3_BASE_ADDR, 0, 4}, +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 27) +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + ret = 1; + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 2: + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + u32 rev_id, value; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE100"); + if (!pfuze) + return -ENODEV; + + ret = pmic_probe(pfuze); + if (ret) + return ret; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value); + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id); + + /* set SW1AB standby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* set SW1C staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value); + value &= ~0x3f; + value |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value); + + return 0; +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} + +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS0 */ + MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 11), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(4, 11), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCD_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCD_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCD_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCD_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCD_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCD_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCD_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCD_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCD_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCD_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_ECSPI1_SCLK__GPIO4_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_PWM1__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) + +{ + int ret; + + ret = enable_lcdif_clock(dev->bus, 1); + if (ret) { + printf("Enable LCDIF clock failed, %d\n", ret); + return; + } + + SETUP_IOMUX_PADS(lcd_pads); + + /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(2, 19), "lcd reset"); + gpio_direction_output(IMX_GPIO_NR(2, 19) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(2, 19) , 1); + + gpio_request(IMX_GPIO_NR(4, 8), "lcd pwr en"); + gpio_direction_output(IMX_GPIO_NR(4, 8) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(3, 23), "backlight"); + gpio_direction_output(IMX_GPIO_NR(3, 23) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = MX6SLL_LCDIF_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX6_PAD_EPDC_DATA00__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA01__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA02__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA03__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA04__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA05__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA06__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA07__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA08__EPDC_DATA08 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA09__EPDC_DATA09 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA10__EPDC_DATA10 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA11__EPDC_DATA11 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA12__EPDC_DATA12 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA13__EPDC_DATA13 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA14__EPDC_DATA14 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA15__EPDC_DATA15 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX6_PAD_EPDC_DATA01__GPIO1_IO08, + MX6_PAD_EPDC_DATA02__GPIO1_IO09, + MX6_PAD_EPDC_DATA03__GPIO1_IO10, + MX6_PAD_EPDC_DATA04__GPIO1_IO11, + MX6_PAD_EPDC_DATA05__GPIO1_IO12, + MX6_PAD_EPDC_DATA06__GPIO1_IO13, + MX6_PAD_EPDC_DATA07__GPIO1_IO14, + MX6_PAD_EPDC_DATA08__GPIO1_IO15, + MX6_PAD_EPDC_DATA09__GPIO1_IO16, + MX6_PAD_EPDC_DATA10__GPIO1_IO17, + MX6_PAD_EPDC_DATA11__GPIO1_IO18, + MX6_PAD_EPDC_DATA12__GPIO1_IO19, + MX6_PAD_EPDC_DATA13__GPIO1_IO20, + MX6_PAD_EPDC_DATA14__GPIO1_IO21, + MX6_PAD_EPDC_DATA15__GPIO1_IO22, + MX6_PAD_EPDC_SDCLK__GPIO1_IO23, + MX6_PAD_EPDC_SDLE__GPIO1_IO24, + MX6_PAD_EPDC_SDOE__GPIO1_IO25, + MX6_PAD_EPDC_SDSHR__GPIO1_IO26, + MX6_PAD_EPDC_SDCE0__GPIO1_IO27, + MX6_PAD_EPDC_GDCLK__GPIO1_IO31, + MX6_PAD_EPDC_GDOE__GPIO2_IO00, + MX6_PAD_EPDC_GDRL__GPIO2_IO01, + MX6_PAD_EPDC_GDSP__GPIO2_IO02, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = { + IOMUX_PADS(PAD_EPDC_PWR_STAT__GPIO2_IO13 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EPDC_VCOM0__GPIO2_IO03 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EPDC_PWR_WAKE__GPIO2_IO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EPDC_PWR_CTRL0__GPIO2_IO07 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), +}; + +static void setup_epdc_power(void) +{ + SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads); + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ + gpio_request(IMX_GPIO_NR(2, 13), "EPDC_PWRSTAT"); + gpio_direction_input(IMX_GPIO_NR(2, 13)); + + /* EPDC_VCOM0 - GPIO2[03] for VCOM control */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 3), "EPDC_VCOM0"); + gpio_direction_output(IMX_GPIO_NR(2, 3), 1); + + /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 14), "EPDC_PWRWAKEUP"); + gpio_direction_output(IMX_GPIO_NR(2, 14), 1); + + /* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 7), "EPDC_PWRCTRL0"); + gpio_direction_output(IMX_GPIO_NR(2, 7), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + SETUP_IOMUX_PADS(epdc_enable_pads); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + SETUP_IOMUX_PADS(epdc_disable_pads); +} + +static void setup_epdc(void) +{ + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 13))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 0); +} +#endif + + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_KEY_COL4__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_KEY_ROW4__USB_OTG1_OC | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX6_PAD_KEY_COL5__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +int board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg1_pads); + break; + case 1: + SETUP_IOMUX_PADS(usb_otg2_pads); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + enable_uart_clk(true); + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_MXC_EPDC + enable_epdc_clock(); + setup_epdc(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + SETUP_IOMUX_PADS(wdog_pads); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ +#ifdef CONFIG_LPDDR2_BOARD + puts("Board: MX6SLL LPDDR2 ARM2\n"); +#else + puts("Board: MX6SLL LPDDR3 ARM2\n"); +#endif + + return 0; +} diff --git a/board/freescale/mx6sll_arm2/plugin.S b/board/freescale/mx6sll_arm2/plugin.S new file mode 100644 index 00000000000..1f4b122b7ae --- /dev/null +++ b/board/freescale/mx6sll_arm2/plugin.S @@ -0,0 +1,285 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sll_lpddr3_arm2_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x550] + ldr r1, =0x00000000 + str r1, [r0, #0x534] + ldr r1, =0x00000030 + str r1, [r0, #0x2AC] + str r1, [r0, #0x548] + str r1, [r0, #0x52C] + ldr r1, =0x00020000 + str r1, [r0, #0x530] + ldr r1, =0x00003030 + str r1, [r0, #0x2B0] + str r1, [r0, #0x2B4] + str r1, [r0, #0x2B8] + str r1, [r0, #0x2BC] + + ldr r1, =0x00020000 + str r1, [r0, #0x540] + ldr r1, =0x00000030 + str r1, [r0, #0x544] + str r1, [r0, #0x54C] + str r1, [r0, #0x554] + str r1, [r0, #0x558] + str r1, [r0, #0x294] + str r1, [r0, #0x298] + str r1, [r0, #0x29C] + str r1, [r0, #0x2A0] + + ldr r1, =0x00082030 + str r1, [r0, #0x2C0] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x084700C7 + str r1, [r0, #0x85C] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x3C3A3C3C + str r1, [r0, #0x848] + ldr r1, =0x24293625 + str r1, [r0, #0x850] + + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + str r1, [r0, #0x824] + str r1, [r0, #0x828] + + ldr r1, =0xf3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + str r1, [r0, #0x834] + str r1, [r0, #0x838] + + ldr r1, =0x24922492 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x53574333 + str r1, [r0, #0x00C] + ldr r1, =0x00100B22 + str r1, [r0, #0x010] + ldr r1, =0x00170778 + str r1, [r0, #0x038] + ldr r1, =0x00C700DB + str r1, [r0, #0x014] + ldr r1, =0x00201718 + str r1, [r0, #0x018] + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x02C] + ldr r1, =0x009F0E10 + str r1, [r0, #0x030] + ldr r1, =0x0000005F + str r1, [r0, #0x040] + ldr r1, =0xC4190000 + str r1, [r0, #0x000] + + ldr r1, =0x00008050 + str r1, [r0, #0x01C] + ldr r1, =0x00008058 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0x003F8038 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x04028038 + str r1, [r0, #0x01C] + ldr r1, =0x83018030 + str r1, [r0, #0x01C] + ldr r1, =0x83018038 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x01038038 + str r1, [r0, #0x01C] + + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6sll_lpddr2_arm2_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x550] + ldr r1, =0x00000000 + str r1, [r0, #0x534] + ldr r1, =0x00000030 + str r1, [r0, #0x2AC] + str r1, [r0, #0x548] + str r1, [r0, #0x52C] + ldr r1, =0x00020000 + str r1, [r0, #0x530] + ldr r1, =0x00003030 + str r1, [r0, #0x2B0] + str r1, [r0, #0x2B4] + str r1, [r0, #0x2B8] + str r1, [r0, #0x2BC] + + ldr r1, =0x00020000 + str r1, [r0, #0x540] + ldr r1, =0x00000030 + str r1, [r0, #0x544] + str r1, [r0, #0x54C] + str r1, [r0, #0x554] + str r1, [r0, #0x558] + str r1, [r0, #0x294] + str r1, [r0, #0x298] + str r1, [r0, #0x29C] + str r1, [r0, #0x2A0] + + ldr r1, =0x00082030 + str r1, [r0, #0x2C0] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x084700C7 + str r1, [r0, #0x85C] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x3A383C40 + str r1, [r0, #0x848] + ldr r1, =0x242C3020 + str r1, [r0, #0x850] + + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + str r1, [r0, #0x824] + str r1, [r0, #0x828] + + ldr r1, =0xf3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + str r1, [r0, #0x834] + str r1, [r0, #0x838] + + ldr r1, =0x24922492 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x53574333 + str r1, [r0, #0x00C] + ldr r1, =0x00100A82 + str r1, [r0, #0x010] + ldr r1, =0x00170777 + str r1, [r0, #0x038] + ldr r1, =0x00C70093 + str r1, [r0, #0x014] + ldr r1, =0x00201708 + str r1, [r0, #0x018] + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x02C] + ldr r1, =0x009F0E10 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0xC3110000 + str r1, [r0, #0x000] + + ldr r1, =0x00008050 + str r1, [r0, #0x01C] + ldr r1, =0x00008058 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0x003F8038 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x04028038 + str r1, [r0, #0x01C] + ldr r1, =0x82018030 + str r1, [r0, #0x01C] + ldr r1, =0x82018038 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x01038038 + str r1, [r0, #0x01C] + + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_LPDDR2_BOARD) + imx6sll_lpddr2_arm2_setting +#else + imx6sll_lpddr3_arm2_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sllevk/Kconfig b/board/freescale/mx6sllevk/Kconfig index 4ba9bbf1418..7c179c72f63 100644 --- a/board/freescale/mx6sllevk/Kconfig +++ b/board/freescale/mx6sllevk/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sllevk" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg index 7d8b3236009..705a9e85c01 100644 --- a/board/freescale/mx6sllevk/imximage.cfg +++ b/board/freescale/mx6sllevk/imximage.cfg @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ * @@ -53,6 +54,11 @@ DATA 4 0x020c4078 0xffffffff DATA 4 0x020c407c 0xffffffff DATA 4 0x020c4080 0xffffffff +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + DATA 4 0x020E0550 0x00080000 DATA 4 0x020E0534 0x00000000 DATA 4 0x020E02AC 0x00000030 diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c index 33aada179f8..05b50d7a00d 100644 --- a/board/freescale/mx6sllevk/mx6sllevk.c +++ b/board/freescale/mx6sllevk/mx6sllevk.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,16 +18,29 @@ #include #include #include +#include #include #include #include "../common/pfuze.h" +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#include + DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -91,6 +105,306 @@ int power_init_board(void) } #endif +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCD_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCD_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCD_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCD_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCD_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCD_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCD_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCD_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCD_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCD_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_KEY_ROW5__GPIO4_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_PWM1__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) + +{ + int ret; + + ret = enable_lcdif_clock(dev->bus, 1); + if (ret) { + printf("Enable LCDIF clock failed, %d\n", ret); + return; + } + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(2, 19), "lcd reset"); + gpio_direction_output(IMX_GPIO_NR(2, 19) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(2, 19) , 1); + + gpio_request(IMX_GPIO_NR(4, 3), "lcd pwr en"); + gpio_direction_output(IMX_GPIO_NR(4, 3) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(3, 23), "backlight"); + gpio_direction_output(IMX_GPIO_NR(3, 23) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = MX6SLL_LCDIF_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX6_PAD_EPDC_DATA00__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA01__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA02__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA03__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA04__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA05__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA06__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA07__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA08__EPDC_DATA08 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA09__EPDC_DATA09 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA10__EPDC_DATA10 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA11__EPDC_DATA11 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA12__EPDC_DATA12 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA13__EPDC_DATA13 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA14__EPDC_DATA14 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA15__EPDC_DATA15 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX6_PAD_EPDC_DATA01__GPIO1_IO08, + MX6_PAD_EPDC_DATA02__GPIO1_IO09, + MX6_PAD_EPDC_DATA03__GPIO1_IO10, + MX6_PAD_EPDC_DATA04__GPIO1_IO11, + MX6_PAD_EPDC_DATA05__GPIO1_IO12, + MX6_PAD_EPDC_DATA06__GPIO1_IO13, + MX6_PAD_EPDC_DATA07__GPIO1_IO14, + MX6_PAD_EPDC_DATA08__GPIO1_IO15, + MX6_PAD_EPDC_DATA09__GPIO1_IO16, + MX6_PAD_EPDC_DATA10__GPIO1_IO17, + MX6_PAD_EPDC_DATA11__GPIO1_IO18, + MX6_PAD_EPDC_DATA12__GPIO1_IO19, + MX6_PAD_EPDC_DATA13__GPIO1_IO20, + MX6_PAD_EPDC_DATA14__GPIO1_IO21, + MX6_PAD_EPDC_DATA15__GPIO1_IO22, + MX6_PAD_EPDC_SDCLK__GPIO1_IO23, + MX6_PAD_EPDC_SDLE__GPIO1_IO24, + MX6_PAD_EPDC_SDOE__GPIO1_IO25, + MX6_PAD_EPDC_SDSHR__GPIO1_IO26, + MX6_PAD_EPDC_SDCE0__GPIO1_IO27, + MX6_PAD_EPDC_GDCLK__GPIO1_IO31, + MX6_PAD_EPDC_GDOE__GPIO2_IO00, + MX6_PAD_EPDC_GDRL__GPIO2_IO01, + MX6_PAD_EPDC_GDSP__GPIO2_IO02, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 13), "epdc_pwrstat"); + gpio_direction_input(IMX_GPIO_NR(2, 13)); + + /* EPDC_VCOM0 - GPIO2[03] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO2_IO03 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 3), "epdc_vcom0"); + gpio_direction_output(IMX_GPIO_NR(2, 3), 1); + + /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 14), "epdc_pwr_wake"); + gpio_direction_output(IMX_GPIO_NR(2, 14), 1); + + /* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 7), "epdc_pwr_ctrl0"); + gpio_direction_output(IMX_GPIO_NR(2, 7), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + /*** epdc Maxim PMIC settings ***/ + + /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_VCOM0 - GPIO2[03] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO2_IO03 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 13))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 0); +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -103,13 +417,30 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_MXC_EPDC + enable_epdc_clock(); + setup_epdc(); +#endif + return 0; } int board_late_init(void) { + + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } diff --git a/board/freescale/mx6sx_17x17_arm2/Kconfig b/board/freescale/mx6sx_17x17_arm2/Kconfig new file mode 100644 index 00000000000..e83dc9d9eb7 --- /dev/null +++ b/board/freescale/mx6sx_17x17_arm2/Kconfig @@ -0,0 +1,23 @@ +if TARGET_MX6SX_17X17_ARM2 || TARGET_MX6SX_14X14_ARM2 + +config SYS_BOARD + default "mx6sx_17x17_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6sx_17x17_arm2" + +config SYS_TEXT_BASE + default 0x87800000 + +config LPDDR2_BOARD + bool "Select for the board using LPDDR2 not default DDR3" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. +endif diff --git a/board/freescale/mx6sx_17x17_arm2/Makefile b/board/freescale/mx6sx_17x17_arm2/Makefile new file mode 100644 index 00000000000..c07e9c80d37 --- /dev/null +++ b/board/freescale/mx6sx_17x17_arm2/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sx_17x17_arm2.o diff --git a/board/freescale/mx6sx_17x17_arm2/imximage.cfg b/board/freescale/mx6sx_17x17_arm2/imximage.cfg new file mode 100644 index 00000000000..def6fded969 --- /dev/null +++ b/board/freescale/mx6sx_17x17_arm2/imximage.cfg @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_17x17_arm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x00270025 +DATA 4 0x021b0810 0x001B001E +DATA 4 0x021b083c 0x4144013C +DATA 4 0x021b0840 0x01300128 +DATA 4 0x021b0848 0x4044464A +DATA 4 0x021b0850 0x3A383C34 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00068031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_17x17_arm2/imximage_wp.cfg b/board/freescale/mx6sx_17x17_arm2/imximage_wp.cfg new file mode 100644 index 00000000000..7a8df0122e7 --- /dev/null +++ b/board/freescale/mx6sx_17x17_arm2/imximage_wp.cfg @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x002E003C +DATA 4 0x021b0810 0x001A003F +DATA 4 0x021b083c 0x41480150 +DATA 4 0x021b0840 0x012C0150 +DATA 4 0x021b0848 0x40404646 +DATA 4 0x021b0850 0x38363C32 +DATA 4 0x021b08c0 0x2492244A +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00068031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg b/board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg new file mode 100644 index 00000000000..f456ef54336 --- /dev/null +++ b/board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_17x17_arm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020c4018 0x00260324 + +DATA 4 0x020e0618 0x00080000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000028 +DATA 4 0x020e02fc 0x00000028 +DATA 4 0x020e05f4 0x00000028 +DATA 4 0x020e0340 0x00000028 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000000 +DATA 4 0x020e0314 0x00000000 +DATA 4 0x020e0614 0x00000028 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00003028 +DATA 4 0x020e0334 0x00003028 +DATA 4 0x020e0338 0x00003028 +DATA 4 0x020e033c 0x00003028 + +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000028 +DATA 4 0x020e0610 0x00000028 +DATA 4 0x020e061c 0x00000028 +DATA 4 0x020e0620 0x00000028 + +DATA 4 0x020e02ec 0x00000028 +DATA 4 0x020e02f0 0x00000028 +DATA 4 0x020e02f4 0x00000028 +DATA 4 0x020e02f8 0x00000028 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b085c 0x1b4700c7 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b0890 0x00380000 +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b082c 0x51111111 +DATA 4 0x021b0830 0x51111111 +DATA 4 0x021b0834 0x51111111 +DATA 4 0x021b0838 0x51111111 + +DATA 4 0x021b0848 0x42424244 + +DATA 4 0x021b0850 0x2E30322E +DATA 4 0x021b08c0 0x2492244A +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x0 + +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b000c 0x33374133 +DATA 4 0x021b0004 0x00020024 +DATA 4 0x021b0010 0x00100A42 +DATA 4 0x021b0014 0x00000093 +DATA 4 0x021b0018 0x00001748 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0038 0x00190778 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0xc3110000 + +DATA 4 0x021b001c 0x00008010 +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x01038030 + +DATA 4 0x021b001c 0x00008018 +DATA 4 0x021b001c 0x003f8038 +DATA 4 0x021b001c 0xff0a8038 +DATA 4 0x021b001c 0x82018038 +DATA 4 0x021b001c 0x04028038 +DATA 4 0x021b001c 0x01038038 + +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b0818 0x00000000 + +DATA 4 0x021b0800 0xa1310003 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c new file mode 100644 index 00000000000..6aedd77dccd --- /dev/null +++ b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c @@ -0,0 +1,847 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SYS_I2C_MXC +#include +#include +#endif +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *pfuze; + unsigned int reg; + int ret; + + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + /* set SW1AB staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(11750); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } + +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750)); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifndef CONFIG_MXC_SPI +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + /* AR8031 PHY Reset. For arm2 board, silder the resistance */ + MX6_PAD_QSPI1A_SS0_B__GPIO4_IO_22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec1(void) +{ + SETUP_IOMUX_PADS(fec1_pads); +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) + +#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + + /* Set the clock */ + enable_qspi_clk(1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) + +int board_mmc_get_env_dev(int dev_no) +{ +#ifdef CONFIG_MXC_SPI + dev_no -= 2; +#else + dev_no--; +#endif + + return dev_no; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ +#ifdef CONFIG_MXC_SPI + return dev_no + 2; +#else + return dev_no + 1; +#endif +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = 1; /*always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /*always present */ + break; + } + + return ret; +} + +#ifdef CONFIG_MXC_SPI +int board_mmc_init(bd_t *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SD3 (SDB) + * mmc1 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} + +#else +int board_mmc_init(bd_t *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SD2 (SDA) + * mmc1 SD3 (SDB) + * mmc2 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi4_pads[] = { + MX6_PAD_SD2_CLK__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_SD2_DATA3__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_SD2_CMD__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_SD2_DATA2__GPIO6_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi4_pads); + gpio_request(IMX_GPIO_NR(6, 10), "ecspi cs"); + gpio_direction_output(IMX_GPIO_NR(6, 10), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(6, 10)) : -1; +} +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +iomux_v3_cfg_t eimnor_pads[] = { + MX6_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) , + MX6_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_NAND_CE0_B__WEIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), + + MX6_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), +}; +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00610089, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x1c022000, WEIM_BASE_ADDR + 0x008); + writel(0x00000000, WEIM_BASE_ADDR + 0x00c); + writel(0x1404a38e, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} +#endif + +#ifdef CONFIG_NAND_MXS +iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(gpmi_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec1(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +#define MAX7322_I2C_ADDR 0x68 +#define MAX7322_I2C_BUS 1 + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + unsigned char value = 1; + + /* clear gpr1[13], gpr1[17] to select anatop clock */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + +/* Reset AR8031 PHY */ + gpio_request(IMX_GPIO_NR(4, 22), "ar8031 reset"); + gpio_direction_output(IMX_GPIO_NR(4, 22) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(4, 22), 1); + +#ifdef CONFIG_DM_I2C + struct udevice *bus, *dev; + ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS - 1, &bus); + if (ret) { + printf("Get i2c bus %u failed, ret = %d\n", MAX7322_I2C_BUS - 1, ret); + return ret; + } + + ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &dev); + if (ret) { + printf("MAX7322 Not found, ret = %d\n", ret); + return ret; + } + + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + ret = dm_i2c_write(dev, 0, &value, 1); + if (ret) { + printf("MAX7322 write failed, ret = %d\n", ret); + return ret; + } +#else + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + i2c_set_bus_num(MAX7322_I2C_BUS); + + if (!i2c_probe(MAX7322_I2C_ADDR)) { + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + if (i2c_write(MAX7322_I2C_ADDR, 0, 0, &value, 1)) + printf("MAX7322 write failed\n"); + } else { + printf("MAX7322 Not found\n"); + } +#endif + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ +#ifdef CONFIG_FEC_ENABLE_MAX7322 + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); +#endif + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +iomux_v3_cfg_t const usb_otg_pads[] = { + /*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/ + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +static void setup_usb(void) +{ + SETUP_IOMUX_PADS(usb_otg_pads); +} + +int board_usb_phy_mode(int port) +{ + return USB_INIT_HOST; +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port >= 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_eimnor(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x60, 0x38, 0x00, 0x00)}, + {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, + {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)}, + {"nand", MAKE_CFGVAL(0x80, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_MX6SX_14X14_ARM2 + puts("Board: MX6SX 14x14 ARM2\n"); +#else + puts("Board: MX6SX 17x17 ARM2\n"); +#endif + + return 0; +} diff --git a/board/freescale/mx6sx_17x17_arm2/plugin.S b/board/freescale/mx6sx_17x17_arm2/plugin.S new file mode 100644 index 00000000000..f58e40a7475 --- /dev/null +++ b/board/freescale/mx6sx_17x17_arm2/plugin.S @@ -0,0 +1,281 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sx_17x17_ddr3_evk_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000030 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000030 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000030 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00270025 + str r2, [r0, #0x80c] + ldr r2, =0x001B001E + str r2, [r0, #0x810] + ldr r2, =0x4144013C + str r2, [r0, #0x83c] + ldr r2, =0x01300128 + str r2, [r0, #0x840] + ldr r2, =0x4044464A + str r2, [r0, #0x848] + ldr r2, =0x3A383C34 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000005f + str r2, [r0, #0x040] + ldr r2, =0x84190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00068031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6sx_14x14_lpddr2_arm2_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000028 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + str r1, [r0, #0x310] + str r1, [r0, #0x314] + ldr r1, =0x00000028 + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00003028 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000028 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + ldr r2, =0x1b4700c7 + str r2, [r0, #0x85c] + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00380000 + str r2, [r0, #0x890] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x51111111 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + + ldr r2, =0x42424244 + str r2, [r0, #0x848] + ldr r2, =0x2E30322E + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33374133 + str r2, [r0, #0x00c] + ldr r2, =0x00020024 + str r2, [r0, #0x004] + ldr r2, =0x00100A42 + str r2, [r0, #0x010] + ldr r2, =0x00000093 + str r2, [r0, #0x014] + ldr r2, =0x00001748 + str r2, [r0, #0x018] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x02c] + ldr r2, =0x0000020e + str r2, [r0, #0x030] + ldr r2, =0x00190778 + str r2, [r0, #0x038] + ldr r2, =0x00000000 + str r2, [r0, #0x008] + ldr r2, =0x0000004f + str r2, [r0, #0x040] + ldr r2, =0xc3110000 + str r2, [r0, #0x000] + + ldr r2, =0x00008010 + str r2, [r0, #0x01c] + ldr r2, =0x003f8030 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x01c] + ldr r2, =0x82018030 + str r2, [r0, #0x01c] + ldr r2, =0x04028030 + str r2, [r0, #0x01c] + ldr r2, =0x01038030 + str r2, [r0, #0x01c] + + ldr r2, =0x00008018 + str r2, [r0, #0x01c] + ldr r2, =0x003f8038 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8038 + str r2, [r0, #0x01c] + ldr r2, =0x82018038 + str r2, [r0, #0x01c] + ldr r2, =0x04028038 + str r2, [r0, #0x01c] + ldr r2, =0x01038038 + str r2, [r0, #0x01c] + + ldr r2, =0x00001800 + str r2, [r0, #0x020] + ldr r2, =0x00000000 + str r2, [r0, #0x818] + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6_ddr_setting +#if defined(CONFIG_TARGET_MX6SX_14X14_ARM2) && defined (CONFIG_LPDDR2_BOARD) + imx6sx_14x14_lpddr2_arm2_ddr_setting +#else + imx6sx_17x17_ddr3_evk_ddr_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sx_19x19_arm2/Kconfig b/board/freescale/mx6sx_19x19_arm2/Kconfig new file mode 100644 index 00000000000..86a7a1ad065 --- /dev/null +++ b/board/freescale/mx6sx_19x19_arm2/Kconfig @@ -0,0 +1,23 @@ +if TARGET_MX6SX_19X19_ARM2 + +config SYS_BOARD + default "mx6sx_19x19_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6sx_19x19_arm2" + +config SYS_TEXT_BASE + default 0x87800000 + +config LPDDR2_BOARD + bool "Select for the board using LPDDR2 not default DDR3" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. +endif diff --git a/board/freescale/mx6sx_19x19_arm2/Makefile b/board/freescale/mx6sx_19x19_arm2/Makefile new file mode 100644 index 00000000000..decef40eb66 --- /dev/null +++ b/board/freescale/mx6sx_19x19_arm2/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sx_19x19_arm2.o diff --git a/board/freescale/mx6sx_19x19_arm2/imximage.cfg b/board/freescale/mx6sx_19x19_arm2/imximage.cfg new file mode 100644 index 00000000000..0a49c119048 --- /dev/null +++ b/board/freescale/mx6sx_19x19_arm2/imximage.cfg @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_19x19_arm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* IOMUX */ +/* DDR IO TYPE */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 + +/* CLOCK */ +DATA 4 0x020e032c 0x00000030 + +/* ADDRESS */ +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 + +/* CONTROL */ +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +/* DATA STROBE */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 + +/* DATA */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 + +/* Calibrations */ +/* ZQ */ +DATA 4 0x021b0800 0xa1390003 +/* write leveling */ +DATA 4 0x021b080c 0x002C003D +DATA 4 0x021b0810 0x00110046 + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x4160016C +DATA 4 0x021b0840 0x013C016C + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x46424446 +DATA 4 0x021b0850 0x3A3C3C3A + +DATA 4 0x021b08c0 0x2492244A + +/* read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +/* Complete calibration by forced measurment */ +DATA 4 0x021b08b8 0x00000800 + +/* MMDC init */ +/* in DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000007f +DATA 4 0x021b0000 0x85190000 + +/* Initialize CS0: MT41K256M16HA-125 */ +/* MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00068031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 + +/* final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg b/board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg new file mode 100644 index 00000000000..7c946718592 --- /dev/null +++ b/board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_19x19_arm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020e0618 0x00080000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000028 +DATA 4 0x020e02fc 0x00000028 +DATA 4 0x020e05f4 0x00000028 +DATA 4 0x020e0340 0x00000028 +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000000 +DATA 4 0x020e0314 0x00000000 +DATA 4 0x020e0614 0x00000028 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00003028 +DATA 4 0x020e0334 0x00003028 +DATA 4 0x020e0338 0x00003028 +DATA 4 0x020e033c 0x00003028 +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000028 +DATA 4 0x020e0610 0x00000028 +DATA 4 0x020e061c 0x00000028 +DATA 4 0x020e0620 0x00000028 +DATA 4 0x020e02ec 0x00000028 +DATA 4 0x020e02f0 0x00000028 +DATA 4 0x020e02f4 0x00000028 +DATA 4 0x020e02f8 0x00000028 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b085c 0x1b4700c7 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b0890 0x00380000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b082c 0x51111111 +DATA 4 0x021b0830 0x51111111 +DATA 4 0x021b0834 0x51111111 +DATA 4 0x021b0838 0x51111111 +DATA 4 0x021b0848 0x42424244 +DATA 4 0x021b0850 0x2E30322E +DATA 4 0x021b08c0 0x2492244A +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b000c 0x33374133 +DATA 4 0x021b0004 0x00020024 +DATA 4 0x021b0010 0x00100A42 +DATA 4 0x021b0014 0x00000093 +DATA 4 0x021b0018 0x00001748 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0038 0x00190778 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0xc3110000 + +DATA 4 0x021b001c 0x00008010 +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x01038030 + +DATA 4 0x021b001c 0x00008018 +DATA 4 0x021b001c 0x003f8038 +DATA 4 0x021b001c 0xff0a8038 +DATA 4 0x021b001c 0x82018038 +DATA 4 0x021b001c 0x04028038 +DATA 4 0x021b001c 0x01038038 + +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b0800 0xa1310003 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c b/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c new file mode 100644 index 00000000000..61209715433 --- /dev/null +++ b/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c @@ -0,0 +1,854 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SYS_I2C_MXC +#include +#include +#endif +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *pfuze; + unsigned int reg; + int ret; + + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + /* set SW1AB staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(11750); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } + +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750)); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lvds_ctrl_pads[] = { + /* CABC enable */ + MX6_PAD_KEY_ROW1__GPIO2_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_lvds(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + enable_lvds_bridge(dev->bus); + + SETUP_IOMUX_PADS(lvds_ctrl_pads); + + /* Enable CABC */ + gpio_request(IMX_GPIO_NR(2, 16), "cabc enable"); + gpio_direction_output(IMX_GPIO_NR(2, 16) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 12), "backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); +} + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + SETUP_IOMUX_PADS(lcd_pads); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 27), "lcd pwr"); + gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 12), "backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = LCDIF2_BASE_ADDR, + .addr = 0, + .pixfmt = 18, + .enable = do_enable_lvds, + .detect = NULL, + .mode = { + .name = "Hannstar-XGA", + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = MX6SX_LCDIF1_BASE_ADDR, + .pixfmt = 24, + .addr = 0, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + /* AR8031 PHY Reset. For arm2 board, silder the resistance */ + MX6_PAD_SD4_DATA4__GPIO6_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec1(void) +{ + SETUP_IOMUX_PADS(fec1_pads); +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) + +#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + + /* Set the clock */ + enable_qspi_clk(1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Assume boot SD always present */ +} +int board_mmc_init(bd_t *bis) +{ + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 (SDA) + */ + SETUP_IOMUX_PADS(usdhc1_pads); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi4_pads[] = { + MX6_PAD_SD2_CLK__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_SD2_DATA3__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_SD2_CMD__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_SD2_DATA2__GPIO6_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi4_pads); + gpio_request(IMX_GPIO_NR(6, 10), "ecspi cs"); + gpio_direction_output(IMX_GPIO_NR(6, 10), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(6, 10)) : -1; +} +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +iomux_v3_cfg_t eimnor_pads[] = { + MX6_PAD_QSPI1A_SCLK__WEIM_DATA_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_SS0_B__WEIM_DATA_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_SS1_B__WEIM_DATA_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA3__WEIM_DATA_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA2__WEIM_DATA_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA1__WEIM_DATA_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA0__WEIM_DATA_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DQS__WEIM_DATA_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_SCLK__WEIM_DATA_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_SS0_B__WEIM_DATA_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_SS1_B__WEIM_DATA_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA3__WEIM_DATA_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA2__WEIM_DATA_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA1__WEIM_DATA_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA0__WEIM_DATA_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DQS__WEIM_DATA_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + + MX6_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) , + MX6_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA05__WEIM_ADDR_26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), + + MX6_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), +}; +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00010181, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x0a020000, WEIM_BASE_ADDR + 0x008); + writel(0x0000c000, WEIM_BASE_ADDR + 0x00c); + writel(0x0804a240, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} +#endif + +#ifdef CONFIG_NAND_MXS +iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(gpmi_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC + +#define MAX7322_I2C_ADDR 0x68 +#define MAX7322_I2C_BUS 1 + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + unsigned char value = 1; + + /* clear gpr1[13], gpr1[17] to select anatop clock */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + + /* Reset AR8031 PHY */ + gpio_request(IMX_GPIO_NR(6, 18), "ar8031 reset"); + gpio_direction_output(IMX_GPIO_NR(6, 18) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(6, 18), 1); + +#ifdef CONFIG_DM_I2C + struct udevice *bus, *dev; + ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS - 1, &bus); + if (ret) { + printf("Get i2c bus %u failed, ret = %d\n", MAX7322_I2C_BUS - 1, ret); + return ret; + } + + ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &dev); + if (ret) { + printf("MAX7322 Not found, ret = %d\n", ret); + return ret; + } + + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + ret = dm_i2c_write(dev, 0, &value, 1); + if (ret) { + printf("MAX7322 write failed, ret = %d\n", ret); + return ret; + } +#else + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + i2c_set_bus_num(MAX7322_I2C_BUS); + + if (!i2c_probe(MAX7322_I2C_ADDR)) { + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + if (i2c_write(MAX7322_I2C_ADDR, 0, 0, &value, 1)) + printf("MAX7322 write failed\n"); + } else { + printf("MAX7322 Not found\n"); + } +#endif + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec1(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ +#ifdef CONFIG_FEC_ENABLE_MAX7322 + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); +#endif + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + SETUP_IOMUX_PADS(usb_otg_pads); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port >= 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_eimnor(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, + {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)}, + {"eimnor", MAKE_CFGVAL(0x00, 0x80, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6SX 19x19 ARM2\n"); + + return 0; +} diff --git a/board/freescale/mx6sx_19x19_arm2/plugin.S b/board/freescale/mx6sx_19x19_arm2/plugin.S new file mode 100644 index 00000000000..a8bba251432 --- /dev/null +++ b/board/freescale/mx6sx_19x19_arm2/plugin.S @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sx_19x19_ddr3_arm2_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000030 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000030 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000030 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x002C003D + str r2, [r0, #0x80c] + ldr r2, =0x00110046 + str r2, [r0, #0x810] + ldr r2, =0x4160016C + str r2, [r0, #0x83c] + ldr r2, =0x013C016C + str r2, [r0, #0x840] + ldr r2, =0x46424446 + str r2, [r0, #0x848] + ldr r2, =0x3A3C3C3A + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000007f + str r2, [r0, #0x040] + ldr r2, =0x85190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00068031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00022227 + str r2, [r0, #0x818] + ldr r2, =0x0002556d + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm + +.macro imx6sx_19x19_lpddr2_arm2_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000028 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + str r1, [r0, #0x310] + str r1, [r0, #0x314] + ldr r1, =0x00000028 + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00003028 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000028 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + ldr r2, =0x1b4700c7 + str r2, [r0, #0x85c] + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00380000 + str r2, [r0, #0x890] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x51111111 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + + ldr r2, =0x42424244 + str r2, [r0, #0x848] + ldr r2, =0x2E30322E + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33374133 + str r2, [r0, #0x00c] + ldr r2, =0x00020024 + str r2, [r0, #0x004] + ldr r2, =0x00100A42 + str r2, [r0, #0x010] + ldr r2, =0x00000093 + str r2, [r0, #0x014] + ldr r2, =0x00001748 + str r2, [r0, #0x018] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x02c] + ldr r2, =0x0000020e + str r2, [r0, #0x030] + ldr r2, =0x00190778 + str r2, [r0, #0x038] + ldr r2, =0x00000000 + str r2, [r0, #0x008] + ldr r2, =0x0000004f + str r2, [r0, #0x040] + ldr r2, =0xc3110000 + str r2, [r0, #0x000] + + ldr r2, =0x00008010 + str r2, [r0, #0x01c] + ldr r2, =0x003f8030 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x01c] + ldr r2, =0x82018030 + str r2, [r0, #0x01c] + ldr r2, =0x04028030 + str r2, [r0, #0x01c] + ldr r2, =0x01038030 + str r2, [r0, #0x01c] + + ldr r2, =0x00008018 + str r2, [r0, #0x01c] + ldr r2, =0x003f8038 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8038 + str r2, [r0, #0x01c] + ldr r2, =0x82018038 + str r2, [r0, #0x01c] + ldr r2, =0x04028038 + str r2, [r0, #0x01c] + ldr r2, =0x01038038 + str r2, [r0, #0x01c] + + ldr r2, =0x00001800 + str r2, [r0, #0x020] + ldr r2, =0x00000000 + str r2, [r0, #0x818] + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_LPDDR2_BOARD) + imx6sx_19x19_lpddr2_arm2_ddr_setting +#else + imx6sx_19x19_ddr3_arm2_ddr_setting +#endif + +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig index ae2ea024394..5e9c06cde0d 100644 --- a/board/freescale/mx6sxsabreauto/Kconfig +++ b/board/freescale/mx6sxsabreauto/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sxsabreauto" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg index 529e555639e..432e0e85412 100644 --- a/board/freescale/mx6sxsabreauto/imximage.cfg +++ b/board/freescale/mx6sxsabreauto/imximage.cfg @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -16,7 +16,22 @@ IMAGE_VERSION 2 * spi/sd/nand/onenand, qspi/nor */ +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sxsabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif /* * Device Configuration Data (DCD) @@ -40,6 +55,11 @@ DATA 4 0x020c407c 0xffffffff DATA 4 0x020c4080 0xffffffff DATA 4 0x020c4084 0xffffffff +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + /* IOMUX - DDR IO Type */ DATA 4 0x020e0618 0x000c0000 DATA 4 0x020e05fc 0x00000000 @@ -134,3 +154,4 @@ DATA 4 0x021b0818 0x00022227 DATA 4 0x021b0004 0x0002556d DATA 4 0x021b0404 0x00011006 DATA 4 0x021b001c 0x00000000 +#endif diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 83473d80b01..e2b1ddc2922 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 nxp * * Author: Ye Li * @@ -27,6 +28,14 @@ #include #include #include +#include +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#include "../common/recovery_keypad.h" +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -49,6 +58,13 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SRE_FAST) #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -61,6 +77,23 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + static iomux_v3_cfg_t const fec2_pads[] = { MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -83,24 +116,30 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static int setup_fec(void) +static int setup_fec(int fec_id) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); + if (0 == fec_id) + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + else + /* Use 125M anatop REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); - return enable_fec_anatop_clock(1, ENET_125MHZ); + return enable_fec_anatop_clock(fec_id, ENET_125MHZ); } int board_eth_init(bd_t *bis) { int ret; - imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); - setup_fec(); + if (0 == CONFIG_FEC_ENET_DEV) + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + else + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); - ret = fecmxc_initialize_multi(bis, 1, + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); if (ret) printf("FEC%d MXC: %s:failed\n", 1, __func__); @@ -131,51 +170,64 @@ int power_init_board(void) { struct udevice *dev; int ret; - u32 dev_id, rev_id, i; - u32 switch_num = 6; - u32 offset = PFUZE100_SW1CMODE; - ret = pmic_get("pfuze100", &dev); - if (ret == -ENODEV) - return 0; + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; - if (ret != 0) + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) return ret; - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + /* set SW1C staby volatage 1.10V */ + pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20); + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); - /* Init mode to APS_PFM */ - pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); + /* Enable power of VGEN5 3V3, needed for SD3 */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, LDO_VOL_MASK, (LDOB_3_30V | (1 << LDO_EN))); - for (i = 0; i < switch_num - 1; i++) - pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); + return 0; +} - /* set SW1AB staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; - /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } - /* set SW1C staby volatage 1.10V */ - pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20); + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.15V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, SW1x_1_150V); - /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); + /* decrease VDDSOC to 1.15V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, SW1x_1_150V); - return 0; + set_anatop_bypass(1); + + printf("switch to ldo_bypass mode!\n"); + } } +#endif #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) static iomux_v3_cfg_t const usb_otg_pads[] = { /* OGT1 */ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), /* OTG2 */ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) }; @@ -210,6 +262,7 @@ int board_ehci_hcd_init(int port) return 0; } #endif +#endif int board_early_init_f(void) { @@ -218,8 +271,136 @@ int board_early_init_f(void) return 0; } +int board_mmc_get_env_dev(int devno) +{ + /* + * need subtract 2 to map to the mmc device id + * see the comments in board_mmc_init function + */ + return devno - 2; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno + 2; +} + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lvds_ctrl_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_lvds(struct display_info_t const *dev) +{ + struct gpio_desc desc; + int ret; + + enable_lcdif_clock(dev->bus, 1); + enable_lvds_bridge(dev->bus); + + imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads, + ARRAY_SIZE(lvds_ctrl_pads)); + + /* LVDS Enable pin */ + ret = dm_gpio_lookup_name("gpio@30_7", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "lvds_en"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(6, 3), "lcd backlight"); + gpio_direction_output(IMX_GPIO_NR(6, 3) , 1); +} + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 27), "lcd reset"); + gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = LCDIF2_BASE_ADDR, + .addr = 0, + .pixfmt = 18, + .detect = NULL, + .enable = do_enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = MX6SX_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 18, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "Boundary-LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + #ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI #define QSPI_PAD_CTRL1 \ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) @@ -238,13 +419,15 @@ static iomux_v3_cfg_t const quadspi_pads[] = { MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), }; +#endif int board_qspi_init(void) { +#ifndef CONFIG_DM_SPI /* Set the iomux */ imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); - +#endif /* Set the clock */ enable_qspi_clk(0); @@ -321,8 +504,10 @@ int board_init(void) dm_gpio_set_value(&desc, 0); #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB setup_usb(); #endif +#endif #ifdef CONFIG_FSL_QSPI board_qspi_init(); @@ -332,6 +517,11 @@ int board_init(void) setup_gpmi_nand(); #endif + /* Also used for OF_CONTROL enabled */ +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + return 0; } @@ -351,6 +541,18 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + /* set WDOG_B to reset whole system */ + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } @@ -360,3 +562,15 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return is_recovery_keypad_pressing(); +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ + +#endif /*CONFIG_FSL_FASTBOOT*/ + diff --git a/board/freescale/mx6sxsabreauto/plugin.S b/board/freescale/mx6sxsabreauto/plugin.S new file mode 100644 index 00000000000..ea5640ca15d --- /dev/null +++ b/board/freescale/mx6sxsabreauto/plugin.S @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sx_sabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000030 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000030 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000030 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x002C003D + str r2, [r0, #0x80c] + ldr r2, =0x00110046 + str r2, [r0, #0x810] + ldr r2, =0x4160016C + str r2, [r0, #0x83c] + ldr r2, =0x013C016C + str r2, [r0, #0x840] + ldr r2, =0x46424446 + str r2, [r0, #0x848] + ldr r2, =0x3A3C3C3A + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000007f + str r2, [r0, #0x040] + ldr r2, =0x85190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00068031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00022227 + str r2, [r0, #0x818] + ldr r2, =0x0002556d + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x20e4024 + ldr r1, =0x1 + str r1, [r0] +#endif +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6sx_sabreauto_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sxsabresd/Kconfig b/board/freescale/mx6sxsabresd/Kconfig index fcfac0aae4e..9a4e3057799 100644 --- a/board/freescale/mx6sxsabresd/Kconfig +++ b/board/freescale/mx6sxsabresd/Kconfig @@ -9,4 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sxsabresd" +config MX6SXSABRESD_EMMC_REWORK + bool "Select for the board with eMMC rework" + +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg index c862617094c..77b1ff5016a 100644 --- a/board/freescale/mx6sxsabresd/imximage.cfg +++ b/board/freescale/mx6sxsabresd/imximage.cfg @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -16,7 +16,20 @@ IMAGE_VERSION 2 * spi/sd/nand/onenand, qspi/nor */ +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#else BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sxsabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif /* * Device Configuration Data (DCD) @@ -40,6 +53,11 @@ DATA 4 0x020c407c 0xffffffff DATA 4 0x020c4080 0xffffffff DATA 4 0x020c4084 0xffffffff +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + /* IOMUX - DDR IO Type */ DATA 4 0x020e0618 0x000c0000 DATA 4 0x020e05fc 0x00000000 @@ -130,3 +148,4 @@ DATA 4 0x021b001c 0x04008040 DATA 4 0x021b0020 0x00000800 DATA 4 0x021b0818 0x00011117 DATA 4 0x021b001c 0x00000000 +#endif diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 6c135130c96..fc60cc8c2e0 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Author: Fabio Estevam * @@ -14,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +28,21 @@ #include #include #include "../common/pfuze.h" +#include +#include +#include + +#ifdef CONFIG_IMX_RDC +#include +#include +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -37,6 +54,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) @@ -47,12 +69,24 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) +#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_40ohm) + #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm) +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -65,6 +99,60 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD pin */ + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* RST_B, used for power reset cycle */ + MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK +static iomux_v3_cfg_t const usdhc4_emmc_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#else +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + static iomux_v3_cfg_t const wdog_b_pad = { MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -85,6 +173,23 @@ static iomux_v3_cfg_t const fec1_pads[] = { MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), }; +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + static iomux_v3_cfg_t const peri_3v3_pads[] = { MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), }; @@ -100,21 +205,39 @@ static iomux_v3_cfg_t const phy_control_pads[] = { MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +#ifdef CONFIG_PCIE_IMX +iomux_v3_cfg_t const pcie_pads[] = { + MX6_PAD_ENET1_COL__GPIO2_IO_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ + MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ +}; + +static void setup_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); + gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable"); + gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset"); +} +#endif + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static int setup_fec(void) +static int setup_fec(int fec_id) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; int reg, ret; - /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + if (0 == fec_id) + /* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + else + /* Use 125M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); - ret = enable_fec_anatop_clock(0, ENET_125MHZ); + ret = enable_fec_anatop_clock(fec_id, ENET_125MHZ); if (ret) return ret; @@ -122,11 +245,11 @@ static int setup_fec(void) ARRAY_SIZE(phy_control_pads)); /* Enable the ENET power, active low */ - gpio_request(IMX_GPIO_NR(2, 6), "enet_rst"); + gpio_request(IMX_GPIO_NR(2, 6), "fec power en"); gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); /* Reset AR8031 PHY */ - gpio_request(IMX_GPIO_NR(2, 7), "phy_rst"); + gpio_request(IMX_GPIO_NR(2, 7), "ar8031 reset"); gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); mdelay(10); gpio_set_value(IMX_GPIO_NR(2, 7), 1); @@ -140,12 +263,93 @@ static int setup_fec(void) int board_eth_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - setup_fec(); + if (0 == CONFIG_FEC_ENET_DEV) + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + else + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); return cpu_eth_init(bis); } +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +#ifdef CONFIG_POWER +int power_init_board(void) +{ + struct pmic *pfuze; + unsigned int reg; + int ret; + + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + /* set SW1AB standby volatage 1.10V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(11000); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C standby volatage 1.10V */ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(11000); + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + /* Enable power of VGEN5 3V3, needed for SD3 */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= (LDOB_3_30V | (1 << LDO_EN)); + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg); + + return 0; +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) int power_init_board(void) { struct udevice *dev; @@ -160,14 +364,176 @@ int power_init_board(void) if (ret < 0) return ret; + /* set SW1AB staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(11000); + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(11000); + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + /* Enable power of VGEN5 3V3, needed for SD3 */ reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); reg &= ~LDO_VOL_MASK; reg |= (LDOB_3_30V | (1 << LDO_EN)); pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + return 0; +} +#endif + +#ifdef CONFIG_LDO_BYPASS_CHECK +#ifdef CONFIG_POWER +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(11750); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } + +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750)); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OGT1 */ + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), + /* OTG2 */ + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); return 0; } +#endif +#endif int board_phy_config(struct phy_device *phydev) { @@ -188,8 +554,22 @@ int board_phy_config(struct phy_device *phydev) return 0; } +#ifdef CONFIG_IMX_RDC +static rdc_peri_cfg_t const shared_resources[] = { + (RDC_PER_GPIO1 | RDC_DOMAIN(0) | RDC_DOMAIN(1)), +}; +#endif + int board_early_init_f(void) { +#ifdef CONFIG_IMX_RDC + imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources)); +#endif + +#ifdef CONFIG_SYS_AUXCORE_FASTUP + arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA); +#endif + setup_iomux_uart(); /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ @@ -199,13 +579,112 @@ int board_early_init_f(void) return 0; } +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK + {USDHC4_BASE_ADDR, 0, 8}, +#else + {USDHC4_BASE_ADDR}, +#endif +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) +#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) + int board_mmc_get_env_dev(int devno) { - return devno; + return devno - 1; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no + 1; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = 1; /* Assume uSDHC2 is always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK + ret = 1; +#else + ret = !gpio_get_value(USDHC4_CD_GPIO); +#endif + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC2 + * mmc1 USDHC3 + * mmc2 USDHC4 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_request(USDHC3_PWR_GPIO, "usdhc3 pwr"); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK + imx_iomux_v3_setup_multiple_pads( + usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads)); +#else + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + gpio_request(USDHC4_CD_GPIO, "usdhc4 cd"); + gpio_direction_input(USDHC4_CD_GPIO); +#endif + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; } #ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI #define QSPI_PAD_CTRL1 \ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) @@ -226,13 +705,15 @@ static iomux_v3_cfg_t const quadspi_pads[] = { MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), }; +#endif int board_qspi_init(void) { +#ifndef CONFIG_DM_SPI /* Set the iomux */ imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); - +#endif /* Set the clock */ enable_qspi_clk(1); @@ -240,7 +721,25 @@ int board_qspi_init(void) } #endif +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd3", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)}, + {"sd4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + #ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lvds_ctrl_pads[] = { + /* CABC enable */ + MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const lcd_pads[] = { MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), @@ -276,9 +775,43 @@ static iomux_v3_cfg_t const lcd_pads[] = { MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static int setup_lcd(void) +void do_enable_lvds(struct display_info_t const *dev) { - enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); + int ret; + + ret = enable_lcdif_clock(dev->bus, 1); + if (ret) { + printf("Enable LCDIF clock failed, %d\n", ret); + return; + } + ret = enable_lvds_bridge(dev->bus); + if (ret) { + printf("Enable LVDS bridge failed, %d\n", ret); + return; + } + + imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads, + ARRAY_SIZE(lvds_ctrl_pads)); + + /* Enable CABC */ + gpio_request(IMX_GPIO_NR(4, 18), "CABC enable"); + gpio_direction_output(IMX_GPIO_NR(4, 18) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(6, 3), "lvds backlight"); + gpio_direction_output(IMX_GPIO_NR(6, 3) , 1); +} + +void do_enable_parallel_lcd(struct display_info_t const *dev) + +{ + int ret; + + ret = enable_lcdif_clock(dev->bus, 1); + if (ret) { + printf("Enable LCDIF clock failed, %d\n", ret); + return; + } imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); @@ -291,9 +824,48 @@ static int setup_lcd(void) /* Set Brightness to high */ gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright"); gpio_direction_output(IMX_GPIO_NR(6, 4) , 1); - - return 0; } + +struct display_info_t const displays[] = {{ + .bus = LCDIF2_BASE_ADDR, + .addr = 0, + .pixfmt = 18, + .detect = NULL, + .enable = do_enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = MX6SX_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); #endif int board_init(void) @@ -314,12 +886,28 @@ int board_init(void) gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en"); gpio_direction_output(IMX_GPIO_NR(4, 16), 1); +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + #ifdef CONFIG_FSL_QSPI board_qspi_init(); #endif -#ifdef CONFIG_VIDEO_MXS - setup_lcd(); +#ifdef CONFIG_PCIE_IMX + setup_pcie(); +#endif + + /* Also used for OF_CONTROL enabled */ +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); #endif return 0; @@ -336,6 +924,19 @@ int board_late_init(void) if (is_reva()) env_set("board_rev", "REVA"); #endif + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif return 0; } @@ -346,6 +947,35 @@ int checkboard(void) return 0; } +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY + +#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 19) +iomux_v3_cfg_t const recovery_key_pads[] = { + (MX6_PAD_CSI_DATA05__GPIO1_IO_19 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)), +}; + +int is_recovery_key_pressing(void) +{ + int button_pressed = 0; + + /* Check Recovery Combo Button press or not. */ + imx_iomux_v3_setup_multiple_pads(recovery_key_pads, + ARRAY_SIZE(recovery_key_pads)); + + gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key"); + gpio_direction_input(GPIO_VOL_DN_KEY); + + if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return button_pressed; +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + #ifdef CONFIG_SPL_BUILD #include #include diff --git a/board/freescale/mx6sxsabresd/plugin.S b/board/freescale/mx6sxsabresd/plugin.S new file mode 100644 index 00000000000..afdb781c749 --- /dev/null +++ b/board/freescale/mx6sxsabresd/plugin.S @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sx_sabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000020 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000020 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000028 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000028 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00290025 + str r2, [r0, #0x80c] + ldr r2, =0x00220022 + str r2, [r0, #0x810] + ldr r2, =0x41480144 + str r2, [r0, #0x83c] + ldr r2, =0x01340130 + str r2, [r0, #0x840] + ldr r2, =0x3C3E4244 + str r2, [r0, #0x848] + ldr r2, =0x34363638 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000005f + str r2, [r0, #0x040] + ldr r2, =0x84190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] + +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x20e4024 + ldr r1, =0x1 + str r1, [r0] +#endif +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6sx_sabresd_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig b/board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig new file mode 100644 index 00000000000..254f21639f7 --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig @@ -0,0 +1,26 @@ +if TARGET_MX6UL_14X14_DDR3_ARM2 + +config SYS_BOARD + default "mx6ul_14x14_ddr3_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6ul_14x14_ddr3_arm2" + +config MX6UL_DDR3_ARM2_EMMC_REWORK + bool "Select this for the board with eMMC rework" + +config SYS_TEXT_BASE + default 0x87800000 + +config MX6UL_DDR3_ARM2_USDHC2_REWORK + bool "Select this for the board with 8bits USDHC2 rework" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. +endif diff --git a/board/freescale/mx6ul_14x14_ddr3_arm2/Makefile b/board/freescale/mx6ul_14x14_ddr3_arm2/Makefile new file mode 100644 index 00000000000..31e2fb0be58 --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_arm2/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ul_14x14_ddr3_arm2.o diff --git a/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg b/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg new file mode 100644 index 00000000000..4e933683cd3 --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 + +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x0013000F +DATA 4 0x021B083C 0x415D0159 +DATA 4 0x021B0848 0x4040484F +DATA 4 0x021B0850 0x40405247 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00922012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333000 +DATA 4 0x021B000C 0x676B54B3 +DATA 4 0x021B0010 0xB68E0A83 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00211740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000005F +DATA 4 0x021B0000 0x85180000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c b/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c new file mode 100644 index 00000000000..1b241b9f2ad --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c @@ -0,0 +1,1069 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + /* conflict with usb_otg2_pwr */ + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + /* conflict with usb_otg2_oc */ + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK +static iomux_v3_cfg_t const usdhc1_emmc_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* + * The following 4 pins conflicts with qspi. + * You can comment out the following 4 pins and change + * {USDHC1_BASE_ADDR, 0, 8} -> {USDHC1_BASE_ADDR, 0, 4} + * to make emmc and qspi coexists. + */ + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* Default NO WP for emmc, since we use pull down */ + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#else +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +#if !defined(CONFIG_CMD_NAND) +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_CSI_VSYNC__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_HSYNC__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#ifdef CONFIG_MX6UL_DDR3_ARM2_USDHC2_REWORK +#if defined(CONFIG_MTD_NOR_FLASH) || defined(CONFIG_MXC_SPI) +#error "Pin conflicts!" +#endif + /* conflict with eimnor/spinor */ + MX6_PAD_CSI_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#endif + /* VSELECT */ + MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* + * Pin conflicts with NAND ALE, if want to test nand, + * Connect R169(B), disconnect R169(A). + * + * RST_B + */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +#ifdef CONFIG_CMD_NAND +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(nand_pads); + + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_MXC_SPI +/* pin conflicts with eim nor */ +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_CSI_DATA06__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA04__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA07__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS Pin */ + MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 26), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(4, 26), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 26)) : -1; +} +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +/* pin conflicts with nand usdhc2 lcd enet */ +static iomux_v3_cfg_t const eimnor_pads[] = { + MX6_PAD_CSI_DATA00__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA01__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA02__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA03__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA04__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA05__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA06__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA07__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA00__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CLE__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_ALE__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CE1_B__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CMD__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CLK__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA0__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA1__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA2__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA3__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__EIM_ADDR26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_PIXCLK__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_VSYNC__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_LCD_DATA08__EIM_DATA00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA09__EIM_DATA01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA10__EIM_DATA02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA11__EIM_DATA03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA12__EIM_DATA04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA13__EIM_DATA05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA14__EIM_DATA06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA15__EIM_DATA07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA16__EIM_DATA08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA17__EIM_DATA09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA18__EIM_DATA10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA19__EIM_DATA11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA20__EIM_DATA12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA21__EIM_DATA13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA22__EIM_DATA14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA23__EIM_DATA15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_MCLK__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DQS__EIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00010181, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x0a020000, WEIM_BASE_ADDR + 0x008); + writel(0x0000c000, WEIM_BASE_ADDR + 0x00c); + writel(0x0804a240, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + if (check_module_fused(MX6_MODULE_EIM)) { + printf("WEIM@0x%x is fused, disable it\n", WEIM_BASE_ADDR); + return; + } + + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} + +int board_flash_wp_on(void) +{ + if (check_module_fused(MX6_MODULE_EIM)) + return 1; /* Skip flash init */ + + return 0; +} + +#endif + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + /* Pin conflicts with LCD PWM1 */ + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec1_phy_rst[] = { + /* + * ALT5 mode is only valid when TAMPER pin is used for GPIO. + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0]. + * + * ENET1_RST + */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_phy_rst[] = { + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) { + SETUP_IOMUX_PADS(fec1_pads); + } else { + SETUP_IOMUX_PADS(fec2_pads); + } +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI + +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + + MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[2] = { +#ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK + /* If want to use qspi, should change to 4 bit width */ + {USDHC1_BASE_ADDR, 0, 8}, +#else + {USDHC1_BASE_ADDR, 0, 4}, +#endif +#if !defined(CONFIG_CMD_NAND) + {USDHC2_BASE_ADDR, 0, 4}, +#endif +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) +#define USDHC1_VSELECT IMX_GPIO_NR(1, 5) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 17) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +int board_mmc_get_env_dev(int devno) +{ + if (devno == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) + devno = 0; + + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + if (devno == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) + devno = 1; + + return devno; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: +#ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK + ret = 1; +#else + ret = !gpio_get_value(USDHC1_CD_GPIO); +#endif + break; +#if !defined(CONFIG_CMD_NAND) + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; +#endif + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: +#ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK + SETUP_IOMUX_PADS(usdhc1_emmc_pads); +#else + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); +#endif + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + /* 3.3V */ + gpio_request(USDHC1_VSELECT, "usdhc1 vsel"); + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr"); + gpio_direction_output(USDHC1_VSELECT, 0); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; +#if !defined(CONFIG_CMD_NAND) + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; +#endif + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * PWM1, pin conflicts with ENET1_RX_DATA0 + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + /* MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),*/ +}; + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + SETUP_IOMUX_PADS(lcd_pads); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd power"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + /* gpio_direction_output(IMX_GPIO_NR(2, 0) , 1); */ +} + +struct display_info_t const displays[] = {{ + .bus = MX6UL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + if (0 == fec_id) { + if (check_module_fused(MX6_MODULE_ENET1)) + return -1; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17] + */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + SETUP_IOMUX_PADS(fec1_phy_rst); + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 2), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 2), 1); + + } else { + if (check_module_fused(MX6_MODULE_ENET2)) + return -1; + + /* clk from phy, set gpr1[14], clear gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK); + + SETUP_IOMUX_PADS(fec2_phy_rst); + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + } + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (CONFIG_FEC_ENET_DEV == 0) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + } else if (CONFIG_FEC_ENET_DEV == 1) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + int ret; + u32 rev_id, value; + static struct pmic *pfuze; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE100"); + if (!pfuze) + return -ENODEV; + + ret = pmic_probe(pfuze); + if (ret) + return ret; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value); + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* set SW1AB standby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* Enable power of VGEN5 3V3 */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value); + value &= ~0x1F; + value |= 0x1F; + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) + return ret; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* Set SW1AB stanby volage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Enable power of VGEN5 3V3 */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~0x1F; + reg |= 0x1F; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + set_anatop_bypass(1); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Because kernel set WDOG_B mux before pad with the commone pinctrl + * framwork now and wdog reset will be triggered once set WDOG_B mux + * with default pad setting, we set pad setting here to workaround this. + * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set + * as GPIO mux firstly here to workaround it. + * + * Here we can not set this, since SD1_RST_B conflicts with GWDOG. + * We use SD1, so will not set WDOG pads, also GWDOG default is + * DNP. + */ + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_CMD_NAND + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_eimnor(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6UL 14X14 DDR3 ARM2\n"); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* + * Leave it here, but default configuration only supports 1 port now, + * because we need sd1 and i2c1 + */ +iomux_v3_cfg_t const usb_otg2_pads[] = { + /* conflict with i2c1_scl */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + /* conflict with sd1_vselect */ + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +int board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg1_pads); + break; + case 1: + SETUP_IOMUX_PADS(usb_otg2_pads); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif diff --git a/board/freescale/mx6ul_14x14_ddr3_arm2/plugin.S b/board/freescale/mx6ul_14x14_ddr3_arm2/plugin.S new file mode 100644 index 00000000000..3ce00dadb91 --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_arm2/plugin.S @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ul_ddr3_arm2_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x0013000F + str r1, [r0, #0x80C] + ldr r1, =0x415D0159 + str r1, [r0, #0x83C] + ldr r1, =0x4040484F + str r1, [r0, #0x848] + ldr r1, =0x40405247 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00922012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333000 + str r1, [r0, #0x008] + ldr r1, =0x676B54B3 + str r1, [r0, #0x00C] + ldr r1, =0xB68E0A83 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00211740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000005F + str r1, [r0, #0x040] + ldr r1, =0x85180000 + str r1, [r0, #0x000] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] + str r1, [r0, #0x84] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6ul_ddr3_arm2_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig index 8210cd3cb88..1f192a1f92b 100644 --- a/board/freescale/mx6ul_14x14_evk/Kconfig +++ b/board/freescale/mx6ul_14x14_evk/Kconfig @@ -9,4 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6ul_14x14_evk" +config MX6UL_14X14_EVK_EMMC_REWORK + bool "Select this for the board with eMMC rework" + +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6ul_14x14_evk/imximage.cfg b/board/freescale/mx6ul_14x14_evk/imximage.cfg new file mode 100644 index 00000000000..12bb9fa287c --- /dev/null +++ b/board/freescale/mx6ul_14x14_evk/imximage.cfg @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_14x14_evk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#ifdef CONFIG_DDR3L_MT41K256M16HA + +/* DDR type MT41K256M16HA-125 which is EOL */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41490145 +DATA 4 0x021B0848 0x40404546 +DATA 4 0x021B0850 0x4040524D +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x00333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D8B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + +#else + +/* New DDR type MT41K256M16TW-107 */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41570155 +DATA 4 0x021B0848 0x4040474A +DATA 4 0x021B0850 0x40405550 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x23400A38 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif +#endif diff --git a/board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg b/board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg new file mode 100644 index 00000000000..2c35a7d7016 --- /dev/null +++ b/board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_14x14_evk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + +DATA 4 0x020E04B4 0x00080000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000000 +DATA 4 0x020E0264 0x00000000 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00003030 +DATA 4 0x020E0284 0x00003030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 + +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B085C 0x1b4700c7 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0890 0x00470000 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B083C 0x20000000 +DATA 4 0x021B0848 0x4040484F +DATA 4 0x021B0850 0x40405247 +DATA 4 0x021B08C0 0x00922012 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020012 +DATA 4 0x021B0008 0x00000000 +DATA 4 0x021B000C 0x33374133 +DATA 4 0x021B0010 0x00100A82 +DATA 4 0x021B0038 0x00170557 +DATA 4 0x021B0014 0x00000093 +DATA 4 0x021B0018 0x00001748 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x0F9F0682 +DATA 4 0x021B0030 0x009F0010 +DATA 4 0x021B0040 0x00000047 +DATA 4 0x021B0000 0x83100000 +DATA 4 0x021B001C 0x00008010 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0x82018030 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0818 0x00000000 +DATA 4 0x021B0800 0xA1310003 +DATA 4 0x021B0004 0x00025576 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index a7b0fa86e0a..5c330a04ce9 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -22,12 +23,21 @@ #include #include #include +#include #include #include #include #include "../common/pfuze.h" #include #include +#include + +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -52,6 +62,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) @@ -60,6 +75,11 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifndef CONFIG_DM_74X164 #define IOX_SDI IMX_GPIO_NR(5, 10) #define IOX_STCP IMX_GPIO_NR(5, 7) #define IOX_SHCP IMX_GPIO_NR(5, 11) @@ -152,8 +172,9 @@ static void iox74lv_init(void) */ gpio_direction_output(IOX_STCP, 1); }; +#endif -#ifdef CONFIG_SYS_I2C_MXC +#ifdef CONFIG_SYS_I2C #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1 for PMIC and EEPROM */ static struct i2c_pads_info i2c_pad_info1 = { @@ -193,7 +214,9 @@ int power_init_board(void) reg, rev_id); /* disable Low Power Mode during standby mode */ - pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); /* SW1B step ramp up time from 2us to 4us/25mV */ reg = 0x40; @@ -210,6 +233,119 @@ int power_init_board(void) return 0; } + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + + struct pmic *p = pmic_get("PFUZE3000"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= PFUZE3000_SW1AB_SETP(12750); + pmic_reg_write(p, PFUZE3000_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE3000_SW1AB_SETP(11750); + + pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(p, PFUZE3000_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif +#endif + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id; + unsigned int reg; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(dev, PFUZE3000_SW1BCONF, reg); + + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + struct udevice *dev; + int ret; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + value &= ~0x1f; + value |= PFUZE3000_SW1AB_SETP(12750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE3000_SW1AB_SETP(11750); + + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} #endif #endif @@ -296,6 +432,7 @@ static void setup_iomux_uart(void) #ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI #define QSPI_PAD_CTRL1 \ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) @@ -308,12 +445,15 @@ static iomux_v3_cfg_t const quadspi_pads[] = { MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), }; +#endif static int board_qspi_init(void) { +#ifndef CONFIG_DM_SPI /* Set the iomux */ imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); +#endif /* Set the clock */ enable_qspi_clk(0); @@ -336,6 +476,22 @@ static struct fsl_esdhc_cfg usdhc_cfg[2] = { #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) +int board_mmc_get_env_dev(int devno) +{ + if (devno == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) + devno = 0; + + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + if (devno == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) + devno = 1; + + return devno; +} + int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; @@ -350,6 +506,7 @@ int board_mmc_getcd(struct mmc *mmc) ret = 1; #else imx_iomux_v3_setup_pad(usdhc2_cd_pad); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); gpio_direction_input(USDHC2_CD_GPIO); /* @@ -394,6 +551,7 @@ int board_mmc_init(bd_t *bis) case 0: imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); @@ -409,6 +567,7 @@ int board_mmc_init(bd_t *bis) imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); #endif + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); gpio_direction_output(USDHC2_PWR_GPIO, 0); udelay(500); gpio_direction_output(USDHC2_PWR_GPIO, 1); @@ -422,7 +581,6 @@ int board_mmc_init(bd_t *bis) ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) { printf("Warning: failed to initialize mmc dev %d\n", i); - return ret; } } #endif @@ -431,11 +589,13 @@ int board_mmc_init(bd_t *bis) #endif #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) static iomux_v3_cfg_t const usb_otg_pads[] = { - MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), }; /* At default the 3v3 enables the MIC2026 for VBUS power */ @@ -469,6 +629,43 @@ int board_ehci_hcd_init(int port) return 0; } #endif +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif #ifdef CONFIG_FEC_MXC /* @@ -527,6 +724,9 @@ static int setup_fec(int fec_id) int ret; if (fec_id == 0) { + if (check_module_fused(MX6_MODULE_ENET1)) + return -1; + /* * Use 50M anatop loopback REF_CLK1 for ENET1, * clear gpr1[13], set gpr1[17]. @@ -534,6 +734,9 @@ static int setup_fec(int fec_id) clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); } else { + if (check_module_fused(MX6_MODULE_ENET2)) + return -1; + /* * Use 50M anatop loopback REF_CLK2 for ENET2, * clear gpr1[14], set gpr1[18]. @@ -600,22 +803,44 @@ static iomux_v3_cfg_t const lcd_pads[] = { MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static int setup_lcd(void) +void do_enable_parallel_lcd(struct display_info_t const *dev) { - enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); + enable_lcdif_clock(dev->bus, 1); imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(5, 9), "lcd reset"); gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); udelay(500); gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 8), "backlight"); gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); - - return 0; } + +struct display_info_t const displays[] = {{ + .bus = MX6UL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "TFT43AB", + .xres = 480, + .yres = 272, + .pixclock = 108695, + .left_margin = 8, + .right_margin = 4, + .upper_margin = 2, + .lower_margin = 4, + .hsync_len = 41, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); #endif int board_early_init_f(void) @@ -630,11 +855,13 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifndef CONFIG_DM_74X164 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); iox74lv_init(); +#endif -#ifdef CONFIG_SYS_I2C_MXC +#ifdef CONFIG_SYS_I2C setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif @@ -643,15 +870,17 @@ int board_init(void) #endif #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB setup_usb(); #endif +#endif #ifdef CONFIG_FSL_QSPI board_qspi_init(); #endif -#ifdef CONFIG_VIDEO_MXS - setup_lcd(); +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); #endif return 0; @@ -673,6 +902,11 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "EVK"); @@ -682,6 +916,12 @@ int board_late_init(void) env_set("board_rev", "14X14"); #endif +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } @@ -695,6 +935,18 @@ int checkboard(void) return 0; } +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + /* No key defined for this board */ + return 0; +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ + +#endif /*CONFIG_FSL_FASTBOOT*/ + #ifdef CONFIG_SPL_BUILD #include #include diff --git a/board/freescale/mx6ul_14x14_evk/plugin.S b/board/freescale/mx6ul_14x14_evk/plugin.S new file mode 100644 index 00000000000..e420d5d2d33 --- /dev/null +++ b/board/freescale/mx6ul_14x14_evk/plugin.S @@ -0,0 +1,373 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ul_ddr3_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + ldr r1, =0x00000030 + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + ldr r1, =0x00000030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x80C] + ldr r1, =0x41570155 + str r1, [r0, #0x83C] + ldr r1, =0x4040474A + str r1, [r0, #0x848] + ldr r1, =0x40405550 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D0B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00201740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x84180000 + str r1, [r0, #0x000] + ldr r1, =0x23400A38 + str r1, [r0, #0x890] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6ul_ddr3_eol_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + ldr r1, =0x00000030 + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + ldr r1, =0x00000030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x80C] + ldr r1, =0x41490145 + str r1, [r0, #0x83C] + ldr r1, =0x40404546 + str r1, [r0, #0x848] + ldr r1, =0x4040524D + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x00333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D8B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00201740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x84180000 + str r1, [r0, #0x000] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6ul_lpddr2_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + str r1, [r0, #0x260] + str r1, [r0, #0x264] + + ldr r1, =0x00000030 + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00003030 + str r1, [r0, #0x280] + ldr r1, =0x00003030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0x1b4700c7 + str r1, [r0, #0x85c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00470000 + str r1, [r0, #0x890] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + ldr r1, =0x4040484F + str r1, [r0, #0x848] + ldr r1, =0x40405247 + str r1, [r0, #0x850] + ldr r1, =0x00922012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020012 + str r1, [r0, #0x004] + ldr r1, =0x00000000 + str r1, [r0, #0x008] + ldr r1, =0x33374133 + str r1, [r0, #0x00C] + ldr r1, =0x00100A82 + str r1, [r0, #0x010] + ldr r1, =0x00170557 + str r1, [r0, #0x038] + ldr r1, =0x00000093 + str r1, [r0, #0x014] + ldr r1, =0x00001748 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x0F9F0682 + str r1, [r0, #0x02C] + ldr r1, =0x009F0010 + str r1, [r0, #0x030] + ldr r1, =0x00000047 + str r1, [r0, #0x040] + ldr r1, =0x83100000 + str r1, [r0, #0x000] + ldr r1, =0x00008010 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0x82018030 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0x00000000 + str r1, [r0, #0x818] + ldr r1, =0xA1310003 + str r1, [r0, #0x800] + ldr r1, =0x00025576 + str r1, [r0, #0x004] + ldr r1, =0x00010106 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] + +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x20e4024 + ldr r1, =1 + str r1, [r0] +#endif +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_TARGET_MX6UL_9X9_EVK) + imx6ul_lpddr2_evk_setting +#elif defined(CONFIG_DDR3L_MT41K256M16HA) + imx6ul_ddr3_eol_evk_setting +#else + imx6ul_ddr3_evk_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig b/board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig new file mode 100644 index 00000000000..7632988653f --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig @@ -0,0 +1,24 @@ +if TARGET_MX6UL_14X14_LPDDR2_ARM2 + +config SYS_BOARD + default "mx6ul_14x14_lpddr2_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6ul_14x14_lpddr2_arm2" + +config SYS_TEXT_BASE + default 0x87800000 + +config MX6UL_LPDDR2_ARM2_USDHC2_REWORK + bool "Select this for the board with 8bits USDHC2 rework" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. + +endif diff --git a/board/freescale/mx6ul_14x14_lpddr2_arm2/Makefile b/board/freescale/mx6ul_14x14_lpddr2_arm2/Makefile new file mode 100644 index 00000000000..9a28784f98c --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_arm2/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ul_14x14_lpddr2_arm2.o diff --git a/board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg b/board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg new file mode 100644 index 00000000000..0a084ce6611 --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_14x14_lpddr2_arm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020E04B4 0x00080000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000028 +DATA 4 0x020E0250 0x00000028 +DATA 4 0x020E024C 0x00000028 +DATA 4 0x020E0490 0x00000028 +DATA 4 0x020E0288 0x00000028 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000000 +DATA 4 0x020E0264 0x00000000 +DATA 4 0x020E04A0 0x00000028 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00003028 +DATA 4 0x020E0284 0x00003028 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000028 +DATA 4 0x020E04A4 0x00000028 +DATA 4 0x020E0244 0x00000028 +DATA 4 0x020E0248 0x00000028 + +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B085C 0x1b4700c7 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0890 0x00470000 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B083C 0x20000000 +DATA 4 0x021B0848 0x4040484F +DATA 4 0x021B0850 0x40405247 +DATA 4 0x021B08C0 0x00922012 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020012 +DATA 4 0x021B0008 0x00000000 +DATA 4 0x021B000C 0x33374133 +DATA 4 0x021B0010 0x00100A82 +DATA 4 0x021B0038 0x00170557 +DATA 4 0x021B0014 0x00000093 +DATA 4 0x021B0018 0x00001748 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x0F9F0682 +DATA 4 0x021B0030 0x009F0010 +DATA 4 0x021B0040 0x00000047 +DATA 4 0x021B0000 0x83100000 +DATA 4 0x021B001C 0x00008010 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0x82018030 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0818 0x00000000 +DATA 4 0x021B0800 0xA1310003 +DATA 4 0x021B0004 0x00025576 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c b/board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c new file mode 100644 index 00000000000..cdf8aca27b6 --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c @@ -0,0 +1,1005 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + /* conflict with usb_otg2_pwr */ + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + /* conflict with usb_otg2_oc */ + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + +#if !defined(CONFIG_CMD_NAND) + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#endif + + MX6_PAD_CSI_DATA04__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#if !defined(CONFIG_CMD_NAND) + +#ifdef CONFIG_MX6UL_LPDDR2_ARM2_USDHC2_REWORK +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX6_PAD_UART1_CTS_B__USDHC2_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#else +static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* Default NO WP for emmc, since we use pull down */ + MX6_PAD_UART1_CTS_B__USDHC2_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP), + + /* RST_B */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif +#endif + +#ifdef CONFIG_CMD_NAND +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(nand_pads); + + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_MXC_SPI +/* pin conflicts with eim nor */ +static iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS Pin */ + MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 22), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(4, 22), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 22)) : -1; +} +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +/* pin conflicts with ECSIP2, USDHC1, USDCH2, NAND, SIM, ENET2 */ +static iomux_v3_cfg_t const eimnor_pads[] = { + MX6_PAD_NAND_CLE__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_ALE__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CE1_B__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CMD__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CLK__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA0__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA1__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA2__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA3__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_PIXCLK__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_VSYNC__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_HSYNC__EIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_DATA00__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA01__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA02__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA03__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA04__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA05__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA06__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA07__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA00__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_MCLK__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_WP_B__EIM_BCLK | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DQS__EIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00610089, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x1c022000, WEIM_BASE_ADDR + 0x008); + writel(0x00000000, WEIM_BASE_ADDR + 0x00c); + writel(0x1404a38e, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} +#endif + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec1_phy_rst[] = { + /* + * ALT5 mode is only valid when TAMPER pin is used for GPIO. + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0]. + * + * ENET1_RST + */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* Conflict with UART1 */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_CTS_B__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_RTS_B__ENET1_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_CTS_B__ENET1_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_phy_rst[] = { + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) { + SETUP_IOMUX_PADS(fec1_pads); + } else { + SETUP_IOMUX_PADS(fec2_pads); + } +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI + +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + + MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +#if !defined(CONFIG_CMD_NAND) +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 1}, + {USDHC2_BASE_ADDR, 0, 8}, +}; +#else +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; +#endif + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 26) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(4, 11) +#define USDHC1_VSELECT IMX_GPIO_NR(1, 5) +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; +#if !defined(CONFIG_CMD_NAND) + case USDHC2_BASE_ADDR: +#ifdef CONFIG_MX6UL_LPDDR2_ARM2_USDHC2_REWORK + ret = !gpio_get_value(USDHC2_CD_GPIO); +#else + ret = 1; +#endif + break; +#endif + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr"); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; +#if !defined(CONFIG_CMD_NAND) + case 1: +#ifdef CONFIG_MX6UL_LPDDR2_ARM2_USDHC2_REWORK + SETUP_IOMUX_PADS(usdhc2_pads); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +#else + SETUP_IOMUX_PADS(usdhc2_emmc_pads); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +#endif + break; +#endif + default: + printf("Warning: you configured more USDHC controllers (%d)" + " than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * PWM1, pin conflicts with ENET1_RX_DATA0 + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + SETUP_IOMUX_PADS(lcd_pads); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd power"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(4, 16), "backlight"); + gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = MX6UL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + if (1 == fec_id) { + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18] + */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + SETUP_IOMUX_PADS(fec1_phy_rst); + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 2), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 2), 1); + } else { + /* clk from phy, set gpr1[13], clear gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK); + + SETUP_IOMUX_PADS(fec2_phy_rst); + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + } + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (CONFIG_FEC_ENET_DEV == 1) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + } else if (CONFIG_FEC_ENET_DEV == 0) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + u32 rev_id, value; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE100"); + if (!pfuze) + return -ENODEV; + + ret = pmic_probe(pfuze); + if (ret) + return ret; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value); + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* set SW1AB standby volatage 1.3V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* Enable power of VGEN5 3V3 */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value); + value &= ~0x1F; + value |= 0x1F; + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) + return ret; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* Set SW1AB stanby volage to 1.3V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Enable power of VGEN5 3V3 */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~0x1F; + reg |= 0x1F; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + set_anatop_bypass(1); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_CMD_NAND + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + /* + * This function should be invoked after setup_fec, + * because ENET2_RX_ER conflicts. However, we rarely need + * ENET2_RX_ER for enet, and when use eimnor, we do not + * have sd1/sd2, enet is a must to boot kernel and nfsrootfs. + */ + setup_eimnor(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6UL 14X14 LPDDR2 ARM2\n"); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* + * Leave it here, but default configuration only supports 1 port now, + * because we need sd1 and i2c1 + */ +iomux_v3_cfg_t const usb_otg2_pads[] = { + /* conflict with i2c1_scl */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + /* conflict with sd1_vselect */ + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +int board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg1_pads); + break; + case 1: + SETUP_IOMUX_PADS(usb_otg2_pads); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif diff --git a/board/freescale/mx6ul_14x14_lpddr2_arm2/plugin.S b/board/freescale/mx6ul_14x14_lpddr2_arm2/plugin.S new file mode 100644 index 00000000000..129d2dd2982 --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_arm2/plugin.S @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ul_lpddr2_arm2_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000028 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + str r1, [r0, #0x260] + str r1, [r0, #0x264] + + ldr r1, =0x00000028 + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00003028 + str r1, [r0, #0x280] + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000028 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0x1b4700c7 + str r1, [r0, #0x5C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00470000 + str r1, [r0, #0x890] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + ldr r1, =0x4040484F + str r1, [r0, #0x848] + ldr r1, =0x40405247 + str r1, [r0, #0x850] + ldr r1, =0x00922012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x00020012 + str r1, [r0, #0x004] + ldr r1, =0x00000000 + str r1, [r0, #0x008] + ldr r1, =0x33374133 + str r1, [r0, #0x00C] + ldr r1, =0x00100A82 + str r1, [r0, #0x010] + ldr r1, =0x00170557 + str r1, [r0, #0x038] + ldr r1, =0x00000093 + str r1, [r0, #0x014] + ldr r1, =0x00001748 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x0F9F0682 + str r1, [r0, #0x02C] + ldr r1, =0x009F0010 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x83100000 + str r1, [r0, #0x000] + ldr r1, =0x00008010 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0x82018030 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0x00000000 + str r1, [r0, #0x818] + ldr r1, =0xA1310003 + str r1, [r0, #0x800] + ldr r1, =0x00025576 + str r1, [r0, #0x004] + ldr r1, =0x00010106 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] + str r1, [r0, #0x84] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6ul_lpddr2_arm2_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ul_nxpu_iopb/Kconfig b/board/freescale/mx6ul_nxpu_iopb/Kconfig new file mode 100644 index 00000000000..8141c05f27d --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6UL_NXPU_IOPB + +config SYS_BOARD + default "mx6ul_nxpu_iopb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6ul_nxpu_iopb" + +endif diff --git a/board/freescale/mx6ul_nxpu_iopb/MAINTAINERS b/board/freescale/mx6ul_nxpu_iopb/MAINTAINERS new file mode 100644 index 00000000000..600c0002bcd --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/MAINTAINERS @@ -0,0 +1,6 @@ +MX6ULIOPB BOARD +M: Fang Hui +S: Maintained +F: board/freescale/mx6ul_nxpu_iopb/ +F: include/configs/mx6ul_nxpu_iopb.h +F: configs/mx6ul_nxpu_iopb_defconfig diff --git a/board/freescale/mx6ul_nxpu_iopb/Makefile b/board/freescale/mx6ul_nxpu_iopb/Makefile new file mode 100644 index 00000000000..ca0dbf7d71c --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ul_nxpu_iopb.o diff --git a/board/freescale/mx6ul_nxpu_iopb/imximage.cfg b/board/freescale/mx6ul_nxpu_iopb/imximage.cfg new file mode 100644 index 00000000000..34423ef8ce9 --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/imximage.cfg @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_nxpu_iopb/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#ifdef CONFIG_DDR3L_MT41K256M16HA + +/* DDR type MT41K256M16HA-125 which is EOL */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41490145 +DATA 4 0x021B0848 0x40404546 +DATA 4 0x021B0850 0x4040524D +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x00333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D8B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + +#else + +/* New DDR type MT41K256M16TW-107 */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41570155 +DATA 4 0x021B0848 0x4040474A +DATA 4 0x021B0850 0x40405550 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x23400A38 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif + +#endif diff --git a/board/freescale/mx6ul_nxpu_iopb/mx6ul_nxpu_iopb.c b/board/freescale/mx6ul_nxpu_iopb/mx6ul_nxpu_iopb.c new file mode 100644 index 00000000000..d1c90233e9d --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/mx6ul_nxpu_iopb.c @@ -0,0 +1,546 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_POWER +#include +#include +#include "../common/pfuze.h" +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ + + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) + + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ +#ifdef CONFIG_IMX_TRUSTY_OS + gd->ram_size = PHYS_SDRAM_SIZE - TRUSTY_OS_RAM_SIZE; +#else + gd->ram_size = PHYS_SDRAM_SIZE; +#endif + return 0; +} + +static iomux_v3_cfg_t const uart3_pads[] = { + MX6_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), /* MDIO */ + MX6_PAD_ENET2_RX_DATA1__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), /* MDC */ + + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_CTS_B__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_LCD_HSYNC__GPIO3_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ + MX6_PAD_UART2_CTS_B__ENET1_CRS | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_UART2_RTS_B__ENET1_COL | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + else + printf("Warning: fec_id %d, should be 0\n", fec_id); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 17) + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) + dev_no = 1; + + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + } + } + + return 0; +} + +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + if (0 == fec_id) { + if (check_module_fused(MX6_MODULE_ENET1)) + return -1; + + /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[17](ENET1_TX_CLK), + set gpr1[13](ENET1_CLK_SEL) */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK); + } else { + if (check_module_fused(MX6_MODULE_ENET2)) + return -1; + + /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* + * Leave it here, but default configuration only supports 1 port now, + * because we need sd1 and i2c1 + */ +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* At default the 3v3 enables the MIC2026 for VBUS power */ +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, + ARRAY_SIZE(usb_otg1_pads)); + + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, + ARRAY_SIZE(usb_otg2_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE3000"); + ret = pmic_probe(pfuze); + if (ret) + return ret; + + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE300 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); + + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); + + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value); + value &= ~0x1f; + value |= PFUZE300_SW1AB_SETP(1275); + pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE300_SW1AB_SETP(1175); + + pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + gpio_request(IMX_GPIO_NR(3, 2), "reset_gpio"); + gpio_direction_output(IMX_GPIO_NR(3, 2) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(3, 2) , 1); + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6UL NXPU IOPB\n"); + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + /* No key defined for this board */ + return 0; +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/freescale/mx6ul_nxpu_iopb/plugin.S b/board/freescale/mx6ul_nxpu_iopb/plugin.S new file mode 100644 index 00000000000..0c49b35378d --- /dev/null +++ b/board/freescale/mx6ul_nxpu_iopb/plugin.S @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ul_ddr3_iopb_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + ldr r1, =0x00000030 + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + ldr r1, =0x00000030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x80C] + ldr r1, =0x41570155 + str r1, [r0, #0x83C] + ldr r1, =0x4040474A + str r1, [r0, #0x848] + ldr r1, =0x40405550 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D0B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00201740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x84180000 + str r1, [r0, #0x000] + ldr r1, =0x23400A38 + str r1, [r0, #0x890] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6ul_ddr3_iopb_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ul_spriot/Kconfig b/board/freescale/mx6ul_spriot/Kconfig new file mode 100644 index 00000000000..7feb2fe4799 --- /dev/null +++ b/board/freescale/mx6ul_spriot/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6UL_SPRIOT + +config SYS_BOARD + default "mx6ul_spriot" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6ul_spriot" + +endif diff --git a/board/freescale/mx6ul_spriot/Makefile b/board/freescale/mx6ul_spriot/Makefile new file mode 100644 index 00000000000..6d25a2adcc0 --- /dev/null +++ b/board/freescale/mx6ul_spriot/Makefile @@ -0,0 +1,8 @@ +# (C) Copyright 2017 Murata Electronics +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# (C) Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ul_spriot.o diff --git a/board/freescale/mx6ul_spriot/imximage.cfg b/board/freescale/mx6ul_spriot/imximage.cfg new file mode 100644 index 00000000000..6e93fe07747 --- /dev/null +++ b/board/freescale/mx6ul_spriot/imximage.cfg @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2017 Murata Electronics. + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_spriot/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* New DDR type MT41K256M16TW-107 */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x000C0030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x415C015C +DATA 4 0x021B0848 0x40404244 +DATA 4 0x021B0850 0x40405A58 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + +#endif diff --git a/board/freescale/mx6ul_spriot/mx6ul_spriot.c b/board/freescale/mx6ul_spriot/mx6ul_spriot.c new file mode 100644 index 00000000000..c11f5a1d841 --- /dev/null +++ b/board/freescale/mx6ul_spriot/mx6ul_spriot.c @@ -0,0 +1,774 @@ +/* + * Copyright (C) 2017 Murata Electronics + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * Specified for EVK consisting of Murata spriot (iMX6UL + PMIC + eMMC + WiFi/BT) + iMX6UL-Base board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_POWER +#include +#include +#include "../common/pfuze.h" +#else + #error "Not defined: CONFIG_POWER" +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ + + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) + + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define IOX_SDI IMX_GPIO_NR(5, 10) +#define IOX_STCP IMX_GPIO_NR(5, 7) +#define IOX_SHCP IMX_GPIO_NR(5, 11) +#define IOX_OE IMX_GPIO_NR(5, 8) + +static iomux_v3_cfg_t const iox_pads[] = { + /* IOX_SDI */ + MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_SHCP */ + MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_STCP */ + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_nOE */ + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* + * HDMI_nRST --> Q0 + * ENET1_nRST --> Q1 + * ENET2_nRST --> Q2 + * CAN1_2_STBY --> Q3 + * BT_nPWD --> Q4 + * CSI_RST --> Q5 + * CSI_PWDN --> Q6 + * LCD_nPWREN --> Q7 + */ +enum qn { + HDMI_nRST, + ENET1_nRST, + ENET2_nRST, + CAN1_2_STBY, + BT_nPWD, + CSI_RST, + CSI_PWDN, + LCD_nPWREN, +}; + +enum qn_func { + qn_reset, + qn_enable, + qn_disable, +}; + +enum qn_level { + qn_low = 0, + qn_high = 1, +}; + +static enum qn_level seq[3][2] = { + {0, 1}, {1, 1}, {0, 0} +}; + +static enum qn_func qn_output[8] = { + qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, + qn_disable, qn_disable +}; + +static void iox74lv_init(void) +{ + int i; + + gpio_direction_output(IOX_OE, 0); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); +}; + + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, + .gp = IMX_GPIO_NR(1, 28), + }, + .sda = { + .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, + .gp = IMX_GPIO_NR(1, 29), + }, +}; +#else +/* Murata spriot uses PMIC */ + #error "Need to define CONFIG_SYS_I2C_MXC" +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + +/* Murata spriot does not use VSELECT, CD and RST_B for WiFi control */ +}; + +/* Murata spriot uses 8-bit eMMC at uSDHC2 */ +static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* + * RST_B + */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + else + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_QSPI + +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); + + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 4}, + {USDHC2_BASE_ADDR, 0, 8}, +}; + +/* Murata spriot eMMC reset */ +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +int mmc_get_env_devno(void) +{ + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + int dev_no; + u32 bootsel; + + bootsel = (soc_sbmr & 0x000000FF) >> 6 ; + + /* If not boot from sd/mmc, use default value */ + if (bootsel != 1) + return CONFIG_SYS_MMC_ENV_DEV; + + /* BOOT_CFG2[3] and BOOT_CFG2[4] */ + dev_no = (soc_sbmr & 0x00001800) >> 11; + + /* Murata spriot always use uSDHC2 for eMMC. Note the 1 difference in mapping. */ + if (dev_no == 2 && mx6_esdhc_fused(USDHC2_BASE_ADDR)) + { + dev_no = 1; + } + + return dev_no; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + /* Murata spriot always use uSDHC2 for eMMC and uSDHC1 for WiFi. Note the 1 difference in mapping. */ + if (dev_no == 1 && mx6_esdhc_fused(USDHC2_BASE_ADDR)) + { + dev_no = 2; + } + + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + /* Murata spriot always has WiFi connected to uSDHC1 which is not available for storage*/ + ret = 0; + break; + case USDHC2_BASE_ADDR: + /* Murata spriot always has eMMC connected to uSDHC2 */ + ret = 1; + break; + } + + return ret; + +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 --> WiFi + * mmc1 USDHC2 --> eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); + + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + } + } + + return 0; +} + +#else + #error "Not defined: CONFIG_FSL_ESDHC" +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + /* LCD_RST */ + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(5, 9), "lcd reset"); + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 8), "backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = MX6UL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "TFT43AB", + .xres = 480, + .yres = 272, + .pixclock = 108695, + .left_margin = 8, + .right_margin = 4, + .upper_margin = 2, + .lower_margin = 4, + .hsync_len = 41, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + if (0 == fec_id) { + if (check_module_fused(MX6_MODULE_ENET1)) + return -1; + + /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + if (check_module_fused(MX6_MODULE_ENET2)) + return -1; + + /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* At default the 3v3 enables the MIC2026 for VBUS power */ +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE3000"); + ret = pmic_probe(pfuze); + if (ret) + return ret; + + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); + + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); + + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= PFUZE3000_SW1AB_SETP(12750); + pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE3000_SW1AB_SETP(11750); + + pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); + + iox74lv_init(); + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: Murata MX6UL-spriot\n"); + + return 0; +} + +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + /* No key defined for this board */ + return 0; +} +#endif diff --git a/board/freescale/mx6ul_spriot/plugin.S b/board/freescale/mx6ul_spriot/plugin.S new file mode 100644 index 00000000000..802a510b271 --- /dev/null +++ b/board/freescale/mx6ul_spriot/plugin.S @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ul_ddr3_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + ldr r1, =0x00000030 + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + ldr r1, =0x00000030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x80C] + ldr r1, =0x41570155 + str r1, [r0, #0x83C] + ldr r1, =0x4040474A + str r1, [r0, #0x848] + ldr r1, =0x40405550 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D0B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00201740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x84180000 + str r1, [r0, #0x000] + ldr r1, =0x23400A38 + str r1, [r0, #0x890] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6ul_ddr3_eol_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + ldr r1, =0x00000030 + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + ldr r1, =0x00000030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x80C] + ldr r1, =0x41490145 + str r1, [r0, #0x83C] + ldr r1, =0x40404546 + str r1, [r0, #0x848] + ldr r1, =0x4040524D + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x00333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D8B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00201740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x84180000 + str r1, [r0, #0x000] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6ul_lpddr2_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + str r1, [r0, #0x260] + str r1, [r0, #0x264] + + ldr r1, =0x00000030 + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00003030 + str r1, [r0, #0x280] + ldr r1, =0x00003030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0x1b4700c7 + str r1, [r0, #0x85c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00470000 + str r1, [r0, #0x890] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + ldr r1, =0x4040484F + str r1, [r0, #0x848] + ldr r1, =0x40405247 + str r1, [r0, #0x850] + ldr r1, =0x00922012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020012 + str r1, [r0, #0x004] + ldr r1, =0x00000000 + str r1, [r0, #0x008] + ldr r1, =0x33374133 + str r1, [r0, #0x00C] + ldr r1, =0x00100A82 + str r1, [r0, #0x010] + ldr r1, =0x00170557 + str r1, [r0, #0x038] + ldr r1, =0x00000093 + str r1, [r0, #0x014] + ldr r1, =0x00001748 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x0F9F0682 + str r1, [r0, #0x02C] + ldr r1, =0x009F0010 + str r1, [r0, #0x030] + ldr r1, =0x00000047 + str r1, [r0, #0x040] + ldr r1, =0x83100000 + str r1, [r0, #0x000] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0x82018030 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0x00000000 + str r1, [r0, #0x818] + ldr r1, =0xA1310003 + str r1, [r0, #0x800] + ldr r1, =0x00025576 + str r1, [r0, #0x004] + ldr r1, =0x00010106 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_MX6UL_9X9_LPDDR2) + imx6ul_lpddr2_evk_setting +#elif defined(CONFIG_DDR3L_MT41K256M16HA) + imx6ul_ddr3_eol_evk_setting +#else + imx6ul_ddr3_evk_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ull_ddr3_arm2/Kconfig b/board/freescale/mx6ull_ddr3_arm2/Kconfig new file mode 100644 index 00000000000..280e6837d2a --- /dev/null +++ b/board/freescale/mx6ull_ddr3_arm2/Kconfig @@ -0,0 +1,24 @@ +if TARGET_MX6ULL_DDR3_ARM2 + +config SYS_BOARD + default "mx6ull_ddr3_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6ull_ddr3_arm2" + +config MX6ULL_DDR3_ARM2_EMMC_REWORK + bool "Select this for the board with eMMC rework" + +config SYS_TEXT_BASE + default 0x87800000 + +config MX6ULL_DDR3_ARM2_TSC_REWORK + bool "Select this for the board with screen touch rework" + +config MX6ULL_DDR3_ARM2_QSPIB_REWORK + bool "Select this for the board with flash on QSPI-B port rework" + +endif diff --git a/board/freescale/mx6ull_ddr3_arm2/Makefile b/board/freescale/mx6ull_ddr3_arm2/Makefile new file mode 100644 index 00000000000..4567ad6326d --- /dev/null +++ b/board/freescale/mx6ull_ddr3_arm2/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ull_ddr3_arm2.o diff --git a/board/freescale/mx6ull_ddr3_arm2/imximage.cfg b/board/freescale/mx6ull_ddr3_arm2/imximage.cfg new file mode 100644 index 00000000000..da76e0f4199 --- /dev/null +++ b/board/freescale/mx6ull_ddr3_arm2/imximage.cfg @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ull_ddr3_arm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x000C0030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00150019 +DATA 4 0x021B083C 0x41550153 +DATA 4 0x021B0848 0x40403A3E +DATA 4 0x021B0850 0x40402F2A +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00944009 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00211740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000005F +DATA 4 0x021B0000 0x85180000 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c b/board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c new file mode 100644 index 00000000000..cf39b9f5541 --- /dev/null +++ b/board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c @@ -0,0 +1,1176 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define EPDC_PAD_CTRL 0x010b1 + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + /* conflict with usb_otg2_pwr */ + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + /* conflict with usb_otg2_oc */ + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK +static iomux_v3_cfg_t const usdhc1_emmc_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* + * The following 4 pins conflicts with qspi and nand flash. + * You can comment out the following 4 pins and change + * {USDHC1_BASE_ADDR, 0, 8} -> {USDHC1_BASE_ADDR, 0, 4} + * to make emmc and qspi coexists. + */ + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* Default NO WP for emmc, since we use pull down */ + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#else +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__GPIO1_IO05 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK) +static iomux_v3_cfg_t const usdhc2_pads[] = { + /* usdhc2_clk, nand_re_b, qspi1b_clk */ + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* usdhc2_cmd, nand_we_b, qspi1b_cs0_b */ + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* usdhc2_data0, nand_data0, qspi1b_cs1_b */ + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* usdhc2_data1, nand_data1 */ + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* usdhc2_data2, nand_data2, qspi1b_dat0 */ + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* usdhc2_data3, nand_data3, qspi1b_dat1 */ + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* + * VSELECT + * Conflicts with WDOG1, so default disabled. + * MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + */ + /* + * CD + * Share with sdhc1 + * MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), + */ + /* + * RST_B + * Pin conflicts with NAND ALE, if want to test nand, + * Connect R169(B), disconnect R169(A). + */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +#ifdef CONFIG_CMD_NAND +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(nand_pads); + + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_MXC_SPI +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_CSI_DATA06__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA04__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA07__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS Pin */ + MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 26), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(4, 26), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 26)) : -1; +} +#endif + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + /* Pin conflicts with LCD PWM1 */ + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec1_phy_rst[] = { + /* + * ALT5 mode is only valid when TAMPER pin is used for GPIO. + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0]. + * + * ENET1_RST + */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_phy_rst[] = { + /* + * ENET2_RST + * + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0] + */ + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) { + SETUP_IOMUX_PADS(fec1_pads); + } else { + SETUP_IOMUX_PADS(fec2_pads); + } +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI + +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + +#ifdef CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK + MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +#endif +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[2] = { +#ifdef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK + /* If want to use qspi, should change to 4 bit width */ + {USDHC1_BASE_ADDR, 0, 8}, +#else + {USDHC1_BASE_ADDR, 0, 4}, +#endif +#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK) + {USDHC2_BASE_ADDR, 0, 4}, +#endif +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) +#define USDHC1_VSELECT IMX_GPIO_NR(1, 5) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +int board_mmc_get_env_dev(int devno) +{ + if (devno == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) + devno = 0; + + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + if (devno == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) + devno = 1; + + return devno; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: +#ifdef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK + ret = 1; +#else + ret = !gpio_get_value(USDHC1_CD_GPIO); +#endif + break; +#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK) + case USDHC2_BASE_ADDR: + ret = 1; + break; +#endif + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: +#ifdef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK + SETUP_IOMUX_PADS(usdhc1_emmc_pads); +#else + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); +#endif + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + /* 3.3V */ + gpio_request(USDHC1_VSELECT, "usdhc1 vsel"); + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr"); + gpio_direction_output(USDHC1_VSELECT, 0); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; +#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK) + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; +#endif + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * PWM1, pin conflicts with ENET1_RX_DATA0 + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + /* MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),*/ +}; + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + SETUP_IOMUX_PADS(lcd_pads); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd power"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + /* gpio_direction_output(IMX_GPIO_NR(2, 0) , 1); */ +} + +struct display_info_t const displays[] = {{ + .bus = MX6ULL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__EPDC_SDDO10 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__EPDC_SDDO13 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__EPDC_SDDO15 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_CLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_ENABLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_HSYNC__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_VSYNC__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA00__EPDC_SDDO00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA01__EPDC_SDDO01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA02__EPDC_SDDO02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA03__EPDC_SDDO03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA04__EPDC_SDDO04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA05__EPDC_SDDO05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA06__EPDC_SDDO06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA07__EPDC_SDDO07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA14__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA15__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA16__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA17__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_RESET__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08, + MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09, + MX6_PAD_ENET2_RX_EN__GPIO2_IO10, + MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11, + MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12, + MX6_PAD_ENET2_TX_EN__GPIO2_IO13, + MX6_PAD_ENET2_TX_CLK__GPIO2_IO14, + MX6_PAD_ENET2_RX_ER__GPIO2_IO15, + MX6_PAD_LCD_CLK__GPIO3_IO00, + MX6_PAD_LCD_ENABLE__GPIO3_IO01, + MX6_PAD_LCD_HSYNC__GPIO3_IO02, + MX6_PAD_LCD_VSYNC__GPIO3_IO03, + MX6_PAD_LCD_DATA00__GPIO3_IO05, + MX6_PAD_LCD_DATA01__GPIO3_IO06, + MX6_PAD_LCD_DATA02__GPIO3_IO07, + MX6_PAD_LCD_DATA03__GPIO3_IO08, + MX6_PAD_LCD_DATA04__GPIO3_IO09, + MX6_PAD_LCD_DATA05__GPIO3_IO10, + MX6_PAD_LCD_DATA06__GPIO3_IO11, + MX6_PAD_LCD_DATA07__GPIO3_IO12, + MX6_PAD_LCD_DATA14__GPIO3_IO19, + MX6_PAD_LCD_DATA15__GPIO3_IO20, + MX6_PAD_LCD_DATA16__GPIO3_IO21, + MX6_PAD_LCD_DATA17__GPIO3_IO22, + MX6_PAD_LCD_RESET__GPIO3_IO04, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = { + IOMUX_PADS(PAD_LCD_DATA11__GPIO3_IO16 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_LCD_DATA19__GPIO3_IO24 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_LCD_DATA09__GPIO3_IO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_LCD_DATA12__GPIO3_IO17 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), +}; + +static void setup_epdc_power(void) +{ + SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads); + + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO3[16] for PWR_GOOD status */ + gpio_request(IMX_GPIO_NR(3, 16), "EPDC_PWRSTAT"); + gpio_direction_input(IMX_GPIO_NR(3, 16)); + + /* EPDC_VCOM0 - GPIO3[24] for VCOM control */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(3, 24), "EPDC_VCOM0"); + gpio_direction_output(IMX_GPIO_NR(3, 24), 1); + + /* EPDC_PWRWAKEUP - GPIO3[14] for EPD PMIC WAKEUP */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(3, 14), "EPDC_PWRWAKEUP"); + gpio_direction_output(IMX_GPIO_NR(3, 14), 1); + + /* EPDC_PWRCTRL0 - GPIO3[17] for EPD PWR CTL0 */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(3, 17), "EPDC_PWRCTRL0"); + gpio_direction_output(IMX_GPIO_NR(3, 17), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + SETUP_IOMUX_PADS(epdc_enable_pads); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + SETUP_IOMUX_PADS(epdc_disable_pads); +} + +static void setup_epdc(void) +{ + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO3_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(3, 17), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 14), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 16))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 24), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 14), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 24), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(3, 17), 0); +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + if (0 == fec_id) { + if (check_module_fused(MX6_MODULE_ENET1)) + return -1; + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17] + */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + SETUP_IOMUX_PADS(fec1_phy_rst); + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 2), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 2), 1); + + } else { + if (check_module_fused(MX6_MODULE_ENET2)) + return -1; + + /* clk from phy, set gpr1[14], clear gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK); + + SETUP_IOMUX_PADS(fec2_phy_rst); + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + } + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (CONFIG_FEC_ENET_DEV == 0) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + } else if (CONFIG_FEC_ENET_DEV == 1) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + u32 rev_id, value; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE100"); + if (!pfuze) + return -ENODEV; + + ret = pmic_probe(pfuze); + if (ret) + return ret; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value); + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* set SW1AB standby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* Enable power of VGEN5 3V3 */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value); + value &= ~0x1F; + value |= 0x1F; + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) + return ret; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* Set SW1AB stanby volage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Enable power of VGEN5 3V3 */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~0x1F; + reg |= 0x1F; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + set_anatop_bypass(1); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_CMD_NAND + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_MXC_EPDC + enable_epdc_clock(); + setup_epdc(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6ULL 14X14 DDR3 ARM2\n"); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* + * Leave it here, but default configuration only supports 1 port now, + * because we need sd1 and i2c1 + */ +iomux_v3_cfg_t const usb_otg2_pads[] = { + /* conflict with i2c1_scl */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + /* conflict with sd1_vselect */ + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +int board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg1_pads); + break; + case 1: + SETUP_IOMUX_PADS(usb_otg2_pads); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif diff --git a/board/freescale/mx6ull_ddr3_arm2/plugin.S b/board/freescale/mx6ull_ddr3_arm2/plugin.S new file mode 100644 index 00000000000..37d666959c7 --- /dev/null +++ b/board/freescale/mx6ull_ddr3_arm2/plugin.S @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ull_ddr3_arm2_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + ldr r1, =0x000C0030 + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00150019 + str r1, [r0, #0x80C] + ldr r1, =0x41550153 + str r1, [r0, #0x83C] + ldr r1, =0x40403A3E + str r1, [r0, #0x848] + ldr r1, =0x40402F2A + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00944009 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D0B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00211740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000005F + str r1, [r0, #0x040] + ldr r1, =0x85180000 + str r1, [r0, #0x000] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6ull_ddr3_arm2_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig index 7eec497e3ea..985763c84f0 100644 --- a/board/freescale/mx6ullevk/Kconfig +++ b/board/freescale/mx6ullevk/Kconfig @@ -1,4 +1,4 @@ -if TARGET_MX6ULL_14X14_EVK +if TARGET_MX6ULL_14X14_EVK || TARGET_MX6ULL_9X9_EVK config SYS_BOARD default "mx6ullevk" @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6ullevk" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg index 80cb0385864..e77b18cee68 100644 --- a/board/freescale/mx6ullevk/imximage.cfg +++ b/board/freescale/mx6ullevk/imximage.cfg @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ * @@ -59,6 +60,11 @@ DATA 4 0x020c4078 0xffffffff DATA 4 0x020c407c 0xffffffff DATA 4 0x020c4080 0xffffffff +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + DATA 4 0x020E04B4 0x000C0000 DATA 4 0x020E04AC 0x00000000 DATA 4 0x020E027C 0x00000030 diff --git a/board/freescale/mx6ullevk/imximage_lpddr2.cfg b/board/freescale/mx6ullevk/imximage_lpddr2.cfg new file mode 100644 index 00000000000..3e3ad269f16 --- /dev/null +++ b/board/freescale/mx6ullevk/imximage_lpddr2.cfg @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + +DATA 4 0x020E04B4 0x00080000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000000 +DATA 4 0x020E0264 0x00000000 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00003030 +DATA 4 0x020E0284 0x00003030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 + +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B085C 0x1b4700c7 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0890 0x23400A38 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B083C 0x20000000 +DATA 4 0x021B0848 0x40403439 +DATA 4 0x021B0850 0x4040342D +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B0008 0x00000000 +DATA 4 0x021B000C 0x33374133 +DATA 4 0x021B0010 0x00100A82 +DATA 4 0x021B0038 0x00170557 +DATA 4 0x021B0014 0x00000093 +DATA 4 0x021B0018 0x00201748 +DATA 4 0x021B002C 0x0F9F26D2 +DATA 4 0x021B0030 0x009F0010 +DATA 4 0x021B0040 0x00000047 +DATA 4 0x021B0000 0x83100000 +DATA 4 0x021B001C 0x00008010 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0x82018030 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0818 0x00000000 +DATA 4 0x021B0800 0xA1310003 +DATA 4 0x021B0004 0x00025552 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index cebcec738fc..eeebcb38531 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,11 +14,19 @@ #include #include #include +#include #include #include +#include +#include #include #include #include +#include +#include +#include +#include +#include "../common/pfuze.h" DECLARE_GLOBAL_DATA_PTR; @@ -25,6 +34,194 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, + .gp = IMX_GPIO_NR(1, 28), + }, + .sda = { + .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, + .gp = IMX_GPIO_NR(1, 29), + }, +}; + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + if (is_mx6ull_9x9_evk()) { + struct pmic *pfuze; + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE3000"); + ret = pmic_probe(pfuze); + if (ret) + return ret; + + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", + reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); + + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); + + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); + } + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + + struct pmic *p = pmic_get("PFUZE3000"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= PFUZE3000_SW1AB_SETP(12750); + pmic_reg_write(p, PFUZE3000_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE3000_SW1AB_SETP(11750); + + pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(p, PFUZE3000_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif +#endif + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id; + unsigned int reg; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(dev, PFUZE3000_SW1BCONF, reg); + + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + struct udevice *dev; + int ret; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + value &= ~0x1f; + value |= PFUZE3000_SW1AB_SETP(12750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE3000_SW1AB_SETP(11750); + + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -42,6 +239,121 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +#ifdef CONFIG_FSL_QSPI + +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; +#endif + +static int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, + ARRAY_SIZE(quadspi_pads)); +#endif + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC +static int setup_fec(int fec_id) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (fec_id == 0) { + if (check_module_fused(MX6_MODULE_ENET1)) + return -1; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + if (check_module_fused(MX6_MODULE_ENET2)) + return -1; + + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + int board_mmc_get_env_dev(int devno) { return devno; @@ -52,6 +364,84 @@ int mmc_map_to_kernel_blk(int devno) return devno; } +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + /* LCD_RST */ + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period. */ + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(5, 9), "lcd reset"); + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 8), "backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = MX6UL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "TFT43AB", + .xres = 480, + .yres = 272, + .pixclock = 108695, + .left_margin = 8, + .right_margin = 4, + .upper_margin = 2, + .lower_margin = 4, + .hsync_len = 41, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -64,6 +454,22 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + return 0; } @@ -83,17 +489,42 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "EVK"); - env_set("board_rev", "14X14"); + + if (is_mx6ull_9x9_evk()) + env_set("board_rev", "9X9"); + else + env_set("board_rev", "14X14"); + + if (is_cpu_type(MXC_CPU_MX6ULZ)) { + env_set("board_name", "ULZ-EVK"); + env_set("usb_net_cmd", "usb start"); + } #endif +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } int checkboard(void) { - puts("Board: MX6ULL 14x14 EVK\n"); + if (is_mx6ull_9x9_evk()) + puts("Board: MX6ULL 9x9 EVK\n"); + else if (is_cpu_type(MXC_CPU_MX6ULZ)) + puts("Board: MX6ULZ 14x14 EVK\n"); + else + puts("Board: MX6ULL 14x14 EVK\n"); return 0; } diff --git a/board/freescale/mx6ullevk/plugin.S b/board/freescale/mx6ullevk/plugin.S index 65a3c455ef0..6b78df598bd 100644 --- a/board/freescale/mx6ullevk/plugin.S +++ b/board/freescale/mx6ullevk/plugin.S @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -116,6 +117,120 @@ str r1, [r0, #0x01C] .endm +.macro imx6ull_lpddr2_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + str r1, [r0, #0x260] + str r1, [r0, #0x264] + + ldr r1, =0x00000030 + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00003030 + str r1, [r0, #0x280] + ldr r1, =0x00003030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0x1b4700c7 + str r1, [r0, #0x85c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x23400A38 + str r1, [r0, #0x890] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + ldr r1, =0x40403439 + str r1, [r0, #0x848] + ldr r1, =0x4040342D + str r1, [r0, #0x850] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x00000000 + str r1, [r0, #0x008] + ldr r1, =0x33374133 + str r1, [r0, #0x00C] + ldr r1, =0x00100A82 + str r1, [r0, #0x010] + ldr r1, =0x00170557 + str r1, [r0, #0x038] + ldr r1, =0x00000093 + str r1, [r0, #0x014] + ldr r1, =0x00201748 + str r1, [r0, #0x018] + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x02C] + ldr r1, =0x009F0010 + str r1, [r0, #0x030] + ldr r1, =0x00000047 + str r1, [r0, #0x040] + ldr r1, =0x83100000 + str r1, [r0, #0x000] + ldr r1, =0x00008010 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0x82018030 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0x00000000 + str r1, [r0, #0x818] + ldr r1, =0xA1310003 + str r1, [r0, #0x800] + ldr r1, =0x00025552 + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + .macro imx6_clock_gating ldr r0, =CCM_BASE_ADDR ldr r1, =0xFFFFFFFF @@ -126,13 +241,23 @@ str r1, [r0, #0x78] str r1, [r0, #0x7C] str r1, [r0, #0x80] + +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x20e4024 + ldr r1, =0x1 + str r1, [r0] +#endif .endm .macro imx6_qos_setting .endm .macro imx6_ddr_setting +#if defined (CONFIG_TARGET_MX6ULL_9X9_EVK) + imx6ull_lpddr2_evk_setting +#else imx6ull_ddr3_evk_setting +#endif .endm /* include the common plugin code here */ diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/Kconfig b/board/freescale/mx7d_12x12_ddr3_arm2/Kconfig new file mode 100644 index 00000000000..5d8c2fb775c --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_arm2/Kconfig @@ -0,0 +1,14 @@ +if TARGET_MX7D_12X12_DDR3_ARM2 + +config SYS_BOARD + default "mx7d_12x12_ddr3_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7d_12x12_ddr3_arm2" + +config SYS_TEXT_BASE + default 0x87800000 +endif diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/Makefile b/board/freescale/mx7d_12x12_ddr3_arm2/Makefile new file mode 100644 index 00000000000..6636874103d --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_arm2/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7d_12x12_ddr3_arm2.o diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg b/board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg new file mode 100644 index 00000000000..c5c8fc9f6cb --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * sd/onenand, nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000b24 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg b/board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg new file mode 100644 index 00000000000..766b9cad3ea --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * sd/onenand, nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30360070 0x00703021 +DATA 4 0x30360090 0x0 +DATA 4 0x30360070 0x00603021 +CHECK_BITS_SET 4 0x30360070 0x80000000 +DATA 4 0x30389880 0x1 + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000dee +DATA 4 0x3079007c 0x18181818 +DATA 4 0x30790080 0x18181818 +DATA 4 0x30790084 0x40401818 +DATA 4 0x30790088 0x00000040 +DATA 4 0x3079006c 0x40404040 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c b/board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c new file mode 100644 index 00000000000..cf5cfa52834 --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no + 1; +} +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SD1_WP__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SD1_CD_B__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + /* Chip selects CS0:CS3 */ + MX7D_PAD_SD1_CLK__GPIO5_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX7D_PAD_SD1_CMD__GPIO5_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX7D_PAD_SD1_DATA0__GPIO5_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX7D_PAD_SD1_DATA1__GPIO5_IO6 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(5, 3), "ecspi1_cs"); + gpio_direction_output(IMX_GPIO_NR(5, 3), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 3 && cs == 0) ? (IMX_GPIO_NR(5, 3)) : -1; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id, reg; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + /* set SW1B normal voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(9750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX7D 12x12 DDR3 ARM2\n"); + + return 0; +} diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/plugin.S b/board/freescale/mx7d_12x12_ddr3_arm2/plugin.S new file mode 100644 index 00000000000..3950ae58b37 --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_arm2/plugin.S @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x18181818 + str r1, [r0, #0x7c] + ldr r1, =0x18181818 + str r1, [r0, #0x80] + ldr r1, =0x40401818 + str r1, [r0, #0x84] + ldr r1, =0x00000040 + str r1, [r0, #0x88] + ldr r1, =0x40404040 + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_ddr_freq_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne FREQ_DEFAULT_533 + + /* Change to 400Mhz for TO1.1 */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x70 + ldr r2, =0x00703021 + str r2, [r0, r1] + ldr r1, =0x90 + ldr r2, =0x0 + str r2, [r0, r1] + ldr r1, =0x70 + ldr r2, =0x00603021 + str r2, [r0, r1] + + ldr r3, =0x80000000 +wait_lock: + ldr r2, [r0, r1] + and r2, r3 + cmp r2, r3 + bne wait_lock + + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x9880 + ldr r2, =0x1 + str r2, [r0, r1] + +FREQ_DEFAULT_533: +.endm + +.macro imx7d_12x12_ddr3_arm2_ddr_setting + imx7d_ddr_freq_setting + + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x01040001 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00400046 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00020001 + str r1, [r0, #0xd0] + ldr r1, =0x00690000 + str r1, [r0, #0xd4] + ldr r1, =0x09300004 + str r1, [r0, #0xdc] + ldr r1, =0x04080000 + str r1, [r0, #0xe0] + ldr r1, =0x00100004 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x09081109 + str r1, [r0, #0x100] + ldr r1, =0x0007020d + str r1, [r0, #0x104] + ldr r1, =0x03040407 + str r1, [r0, #0x108] + ldr r1, =0x00002006 + str r1, [r0, #0x10c] + ldr r1, =0x04020205 + str r1, [r0, #0x110] + ldr r1, =0x03030202 + str r1, [r0, #0x114] + ldr r1, =0x00000803 + str r1, [r0, #0x120] + ldr r1, =0x00800020 + str r1, [r0, #0x180] + ldr r1, =0x02000100 + str r1, [r0, #0x184] + ldr r1, =0x02098204 + str r1, [r0, #0x190] + ldr r1, =0x00030303 + str r1, [r0, #0x194] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00080808 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 + str r1, [r0, #0x214] + ldr r1, =0x0f070707 + str r1, [r0, #0x218] + + ldr r1, =0x06000604 + str r1, [r0, #0x240] + ldr r1, =0x00000001 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17420f40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00060807 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + imx7d_ddrphy_latency_setting + ldr r1, =0x08080808 + str r1, [r0, #0x20] + ldr r1, =0x08080808 + str r1, [r0, #0x30] + ldr r1, =0x01000010 + str r1, [r0, #0x50] + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_12x12_ddr3_arm2_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig b/board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig new file mode 100644 index 00000000000..6a2f54ee31a --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig @@ -0,0 +1,14 @@ +if TARGET_MX7D_12X12_LPDDR3_ARM2 + +config SYS_BOARD + default "mx7d_12x12_lpddr3_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7d_12x12_lpddr3_arm2" + +config SYS_TEXT_BASE + default 0x87800000 +endif diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/Makefile b/board/freescale/mx7d_12x12_lpddr3_arm2/Makefile new file mode 100644 index 00000000000..f9f6e37e648 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7d_12x12_lpddr3_arm2.o diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg new file mode 100644 index 00000000000..736b8fb3d47 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03040008 +DATA 4 0x307a0064 0x00200038 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00dc 0x00c3000a +DATA 4 0x307a00e0 0x00010000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x0a0e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x03060708 +DATA 4 0x307a010c 0x00a0500c +DATA 4 0x307a0110 0x05020307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098205 +DATA 4 0x307a0194 0x00060303 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 + +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00090909 +DATA 4 0x307a0210 0x00000f00 +DATA 4 0x307a0214 0x08080808 +DATA 4 0x307a0218 0x0f0f0808 + +DATA 4 0x307a0240 0x06000600 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421e40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x0007080c +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009c 0x00000b24 + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x30790018 0x0000000f +DATA 4 0x307900c0 0x0e487304 +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e4c7306 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg new file mode 100644 index 00000000000..09be01151ea --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03040008 +DATA 4 0x307a0064 0x00200038 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00dc 0x00c3000a +DATA 4 0x307a00e0 0x00010000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x0a0e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x03060708 +DATA 4 0x307a010c 0x00a0500c +DATA 4 0x307a0110 0x05020307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098205 +DATA 4 0x307a0194 0x00060303 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 + +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00090909 +DATA 4 0x307a0210 0x00000f00 +DATA 4 0x307a0214 0x08080808 +DATA 4 0x307a0218 0x0f0f0808 + +DATA 4 0x307a0240 0x06000601 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421e40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x0007080c +DATA 4 0x3079007c 0x1c1c1c1c +DATA 4 0x30790080 0x1c1c1c1c +DATA 4 0x30790084 0x30301c1c +DATA 4 0x30790088 0x00000030 +DATA 4 0x3079006c 0x30303030 +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009c 0x0db60d6e + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x30790018 0x0000000f +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487306 +DATA 4 0x307900c0 0x1e4c7304 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x1e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c b/board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c new file mode 100644 index 00000000000..3f45d9f31cb --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c @@ -0,0 +1,659 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include + +#ifdef CONFIG_VIDEO_MXS +#include +#endif +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define EPDC_PAD_CTRL 0x0 + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwm_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = ELCDIF1_IPS_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + + +static iomux_v3_cfg_t const per_rst_pads[] = { + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec1(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +static iomux_v3_cfg_t const quadspi_pads[] = { + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); +#endif + + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec1(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + ret = set_clk_enet(ENET_125MHZ); + if (ret) + return ret; + + return 0; +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS0 */ + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(4, 19), "ecspi1_cs"); + gpio_direction_output(IMX_GPIO_NR(4, 19), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 19)) : -1; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX7D_PAD_EPDC_DATA00__GPIO2_IO0, + MX7D_PAD_EPDC_DATA01__GPIO2_IO1, + MX7D_PAD_EPDC_DATA02__GPIO2_IO2, + MX7D_PAD_EPDC_DATA03__GPIO2_IO3, + MX7D_PAD_EPDC_DATA04__GPIO2_IO4, + MX7D_PAD_EPDC_DATA05__GPIO2_IO5, + MX7D_PAD_EPDC_DATA06__GPIO2_IO6, + MX7D_PAD_EPDC_DATA07__GPIO2_IO7, + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16, + MX7D_PAD_EPDC_SDLE__GPIO2_IO17, + MX7D_PAD_EPDC_SDOE__GPIO2_IO18, + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19, + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20, + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21, + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22, + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23, + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24, + MX7D_PAD_EPDC_GDOE__GPIO2_IO25, + MX7D_PAD_EPDC_GDRL__GPIO2_IO26, + MX7D_PAD_EPDC_GDSP__GPIO2_IO27, + MX7D_PAD_EPDC_BDR0__GPIO2_IO28, + MX7D_PAD_EPDC_BDR1__GPIO2_IO29, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0); + + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 31), "epdc_pwrstat"); + gpio_direction_input(IMX_GPIO_NR(2, 31)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_request(IMX_GPIO_NR(4, 14), "epdc_vcom0"); + gpio_direction_output(IMX_GPIO_NR(4, 14), 1); + + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(4, 23), "epdc_pwrwakeup"); + gpio_direction_output(IMX_GPIO_NR(4, 23), 1); + + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(4, 20), "epdc_pwrctrl0"); + gpio_direction_output(IMX_GPIO_NR(4, 20), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + /*** epdc Maxim PMIC settings ***/ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(4, 20), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(4, 23), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 31))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(4, 23), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(4, 20), 0); +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* Reset peripherals */ + imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 3), "per_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 3) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 3), 1); + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_MXC_EPDC + setup_epdc(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x10, 0x12, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x10, 0x16, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id, reg; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + /* below are for LPSR mode support */ + reg = pmic_reg_read(dev, PFUZE3000_SW3MODE); + reg |= 0x20; + pmic_reg_write(dev, PFUZE3000_SW3MODE, reg); + + reg = pmic_reg_read(dev, PFUZE3000_VLDO1CTL); + reg |= 0x80; + pmic_reg_write(dev, PFUZE3000_VLDO1CTL, reg); + + reg = pmic_reg_read(dev, PFUZE3000_VLDO3CTL); + reg |= 0x80; + pmic_reg_write(dev, PFUZE3000_VLDO3CTL, reg); + + reg = pmic_reg_read(dev, PFUZE3000_SW2MODE); + reg |= 0x20; + pmic_reg_write(dev, PFUZE3000_SW2MODE, reg); + + /* set SW1B normal voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(9750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX7D 12x12 LPDDR3 ARM2\n"); + + return 0; +} diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S new file mode 100644 index 00000000000..af8770c4b93 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S @@ -0,0 +1,657 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne TUNE_END + + /*TO 1.1*/ + ldr r1, =0x1c1c1c1c + str r1, [r0, #0x7c] + ldr r1, =0x1c1c1c1c + str r1, [r0, #0x80] + ldr r1, =0x30301c1c + str r1, [r0, #0x84] + ldr r1, =0x00000030 + str r1, [r0, #0x88] + ldr r1, =0x30303030 + str r1, [r0, #0x6c] + +TUNE_END: +.endm + +.macro imx7d_12x12_lpddr3_arm2_setting + + /* check whether it is a LPSR resume */ + ldr r1, =0x30270000 + ldr r7, [r1] + cmp r7, #0 + beq 16f + + /* disable wdog powerdown counter */ + ldr r0, =0x30280000 + ldrh r1, =0x0 + strh r1, [r0, #0x8] + + /* initialize AIPs 1-3 port */ + ldr r0, =0x301f0000 + ldr r1, =0x77777777 + str r1, [r0] + str r1, [r0, #0x4] + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4c] + str r1, [r0, #0x50] + + ldr r0, =0x305f0000 + ldr r1, =0x77777777 + str r1, [r0] + str r1, [r0, #0x4] + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4c] + str r1, [r0, #0x50] + + ldr r0, =0x309f0000 + ldr r1, =0x77777777 + str r1, [r0] + str r1, [r0, #0x4] + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4c] + str r1, [r0, #0x50] + + ldr r1, =0x30360000 + ldr r2, =0x30390000 + ldr r3, =0x307a0000 + ldr r4, =0x30790000 + ldr r10, =0x30380000 + ldr r11, =0x30340000 + + /* turn on ddr power */ + ldr r7, =(0x1 << 29) + str r7, [r1, #0x388] + + ldr r6, =50 +1: + subs r6, r6, #0x1 + bne 1b + + /* clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + orr r7, r7, #0x3 + str r7, [r2, r6] + ldr r7, [r2, r6] + bic r7, r7, #0x1 + str r7, [r2, r6] + + /* restore DDRC */ + ldr r6, =0x0 + ldr r7, =0x03040008 + str r7, [r3, r6] + + ldr r6, =0x1a0 + ldr r7, =0x80400003 + str r7, [r3, r6] + + ldr r6, =0x1a4 + ldr r7, =0x00100020 + str r7, [r3, r6] + + ldr r6, =0x1a8 + ldr r7, =0x80100004 + str r7, [r3, r6] + + ldr r6, =0x64 + ldr r7, =0x00200038 + str r7, [r3, r6] + + ldr r6, =0xd0 + ldr r7, =0xc0350001 + str r7, [r3, r6] + + ldr r6, =0xdc + ldr r7, =0x00C3000A + str r7, [r3, r6] + + ldr r6, =0xe0 + ldr r7, =0x00010000 + str r7, [r3, r6] + + ldr r6, =0xe4 + ldr r7, =0x00110006 + str r7, [r3, r6] + + ldr r6, =0xf4 + ldr r7, =0x0000033F + str r7, [r3, r6] + + ldr r6, =0x100 + ldr r7, =0x0A0E110B + str r7, [r3, r6] + + ldr r6, =0x104 + ldr r7, =0x00020211 + str r7, [r3, r6] + + ldr r6, =0x108 + ldr r7, =0x03060708 + str r7, [r3, r6] + + ldr r6, =0x10c + ldr r7, =0x00A0500C + str r7, [r3, r6] + + ldr r6, =0x110 + ldr r7, =0x05020307 + str r7, [r3, r6] + + ldr r6, =0x114 + ldr r7, =0x02020404 + str r7, [r3, r6] + + ldr r6, =0x118 + ldr r7, =0x02020003 + str r7, [r3, r6] + + ldr r6, =0x11c + ldr r7, =0x00000202 + str r7, [r3, r6] + + ldr r6, =0x120 + ldr r7, =0x00000202 + str r7, [r3, r6] + + ldr r6, =0x180 + ldr r7, =0x00600018 + str r7, [r3, r6] + + ldr r6, =0x184 + ldr r7, =0x00e00100 + str r7, [r3, r6] + + ldr r6, =0x190 + ldr r7, =0x02098205 + str r7, [r3, r6] + + ldr r6, =0x194 + ldr r7, =0x00060303 + str r7, [r3, r6] + + ldr r6, =0x200 + ldr r7, =0x00000016 + str r7, [r3, r6] + + ldr r6, =0x204 + ldr r7, =0x00090909 + str r7, [r3, r6] + + ldr r6, =0x210 + ldr r7, =0xF00 + str r7, [r3, r6] + + ldr r6, =0x214 + ldr r7, =0x08080808 + str r7, [r3, r6] + + ldr r6, =0x218 + ldr r7, =0x0f0f0808 + str r7, [r3, r6] + + ldr r6, =0x240 + ldr r7, =0x06000600 + str r7, [r3, r6] + + ldr r6, =0x244 + ldr r7, =0x00000000 + str r7, [r3, r6] + + ldr r7, =0x20 + str r7, [r3, #0x30] + ldr r7, =0x0 + str r7, [r3, #0x1b0] + + /* do PHY, clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + bic r7, r7, #0x2 + str r7, [r2, r6] + + ldr r7, [r1, #0x800] + and r7, r7, #0xFF + cmp r7, #0x11 + bne 2f + + /* for TO1.1 */ + ldr r7, [r11] + bic r7, r7, #(1 << 27) + str r7, [r11] + ldr r7, [r11] + bic r7, r7, #(1 << 29) + str r7, [r11] +2: + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r7, =(0x1 << 30) + str r7, [r1, #0x388] + ldr r7, =(0x1 << 30) + str r7, [r1, #0x384] + + /* need to delay ~5mS */ + ldr r6, =0x100000 +3: + subs r6, r6, #0x1 + bne 3b + + /* restore DDR PHY */ + ldr r6, =0x0 + ldr r7, =0x17421E40 + str r7, [r4, r6] + + ldr r6, =0x4 + ldr r7, =0x10210100 + str r7, [r4, r6] + + ldr r6, =0x8 + ldr r7, =0x00010000 + str r7, [r4, r6] + + ldr r6, =0x10 + ldr r7, =0x0007080C + str r7, [r4, r6] + + ldr r6, =0xb0 + ldr r7, =0x1010007e + str r7, [r4, r6] + + ldr r7, [r1, #0x800] + and r7, r7, #0xFF + cmp r7, #0x11 + bne 4f + + ldr r6, =0x7c + ldr r7, =0x1c1c1c1c + str r7, [r4, r6] + + ldr r6, =0x80 + ldr r7, =0x1c1c1c1c + str r7, [r4, r6] + + ldr r6, =0x84 + ldr r7, =0x30301c1c + str r7, [r4, r6] + + ldr r6, =0x88 + ldr r7, =0x00000030 + str r7, [r4, r6] + + ldr r6, =0x6c + ldr r7, =0x30303030 + str r7, [r4, r6] + + ldr r6, =0x1c + ldr r7, =0x01010000 + str r7, [r4, r6] + + ldr r6, =0x9c + ldr r7, =0x0DB60D6E + str r7, [r4, r6] + + b 5f + +4: + ldr r6, =0x1c + ldr r7, =0x01010000 + str r7, [r4, r6] + + ldr r6, =0x9c + ldr r7, =0x00000b24 + str r7, [r4, r6] + +5: + ldr r6, =0x20 + ldr r7, =0x0a0a0a0a + str r7, [r4, r6] + + ldr r6, =0x30 + ldr r7, =0x06060606 + str r7, [r4, r6] + + ldr r6, =0x50 + ldr r7, =0x01000008 + str r7, [r4, r6] + + ldr r6, =0x50 + ldr r7, =0x00000008 + str r7, [r4, r6] + + ldr r6, =0xc0 + ldr r7, =0x0e487304 + str r7, [r4, r6] + + ldr r6, =0xc0 + ldr r7, =0x0e4c7304 + str r7, [r4, r6] + + ldr r6, =0xc0 + ldr r7, =0x0e4c7306 + str r7, [r4, r6] + +6: + ldr r7, [r4, #0xc4] + tst r7, #0x1 + beq 6b + + ldr r6, =0xc0 + ldr r7, =0x0e487304 + str r7, [r4, r6] + + ldr r7, =0x0 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0x170 + orr r7, r7, #0x8 + str r7, [r11, #0x20] + + ldr r7, =0x2 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0xf + str r7, [r4, #0x18] + + /* wait until self-refresh mode entered */ +11: + ldr r7, [r3, #0x4] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 11b + ldr r7, =0x0 + str r7, [r3, #0x320] + ldr r7, =0x1 + str r7, [r3, #0x1b0] + ldr r7, =0x1 + str r7, [r3, #0x320] +12: + ldr r7, [r3, #0x324] + and r7, r7, #0x1 + cmp r7, #0x1 + bne 12b +13: + ldr r7, [r3, #0x4] + and r7, r7, #0x20 + cmp r7, #0x20 + bne 13b + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r3, #0x30] +14: + ldr r7, [r3, #0x4] + and r7, r7, #0x30 + cmp r7, #0x0 + bne 14b + +15: + ldr r7, [r3, #0x4] + and r7, r7, #0x3 + cmp r7, #0x1 + bne 15b + + imx7_qos_setting + + /* enable port */ + ldr r7, =0x1 + str r7, [r3, #0x490] + + /* jump to kernel resume */ + ldr r1, =0x30270000 + ldr r7, [r1] + + mov pc, r7 +16: + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x03040008 + str r1, [r0] + ldr r1, =0x00200038 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00350001 + str r1, [r0, #0xd0] + ldr r1, =0x00c3000a + str r1, [r0, #0xdc] + ldr r1, =0x00010000 + str r1, [r0, #0xe0] + ldr r1, =0x00110006 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x0a0e110b + str r1, [r0, #0x100] + ldr r1, =0x00020211 + str r1, [r0, #0x104] + ldr r1, =0x03060708 + str r1, [r0, #0x108] + ldr r1, =0x00a0500c + str r1, [r0, #0x10c] + ldr r1, =0x05020307 + str r1, [r0, #0x110] + ldr r1, =0x02020404 + str r1, [r0, #0x114] + ldr r1, =0x02020003 + str r1, [r0, #0x118] + ldr r1, =0x00000202 + str r1, [r0, #0x11c] + ldr r1, =0x00000202 + str r1, [r0, #0x120] + ldr r1, =0x00600018 + str r1, [r0, #0x180] + ldr r1, =0x00e00100 + str r1, [r0, #0x184] + ldr r1, =0x02098205 + str r1, [r0, #0x190] + ldr r1, =0x00060303 + str r1, [r0, #0x194] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00090909 + str r1, [r0, #0x204] + ldr r1, =0x00000f00 + str r1, [r0, #0x210] + ldr r1, =0x08080808 + str r1, [r0, #0x214] + ldr r1, =0x0f0f0808 + str r1, [r0, #0x218] + + ldr r1, =0x06000600 + str r1, [r0, #0x240] + mov r1, #0x0 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17421e40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00010000 + str r1, [r0, #0x8] + ldr r1, =0x0007080c + str r1, [r0, #0x10] + imx7d_ddrphy_latency_setting + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + ldr r1, =0x01010000 + str r1, [r0, #0x1c] + + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne 17f + + ldr r1, =0x0db60d6e + str r1, [r0, #0x9c] + b 18f +17: + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] +18: + ldr r1, =0x06060606 + str r1, [r0, #0x30] + ldr r1, =0x0a0a0a0a + str r1, [r0, #0x20] + ldr r1, =0x01000008 + str r1, [r0, #0x50] + ldr r1, =0x00000008 + str r1, [r0, #0x50] + + ldr r1, =0x0000000f + str r1, [r0, #0x18] + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x30340024 + ldr r1, =0x1 + str r1, [r0] +#endif +.endm + +.macro imx7_qos_setting + ldr r0, =REGS_QOS_BASE + ldr r1, =0 + str r1, [r0, #0] + + ldr r1, =0 + str r1, [r0, #0x60] + + ldr r0, =REGS_QOS_EPDC + ldr r1, =0 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_PXP1 + ldr r1, =0 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_EPDC + ldr r1, =0x0f020f22 + str r1, [r0, #0xd0] + str r1, [r0, #0xe0] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x1 + str r1, [r0, #0] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x0f020222 + str r1, [r0, #0x50] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0x50] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x0f020222 + str r1, [r0, #0x60] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0x60] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x0f020422 + str r1, [r0, #0x70] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0x70] + + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0xe080 + str r1, [r0, #0x34] +.endm + +.macro imx7_ddr_setting + imx7d_12x12_lpddr3_arm2_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/Kconfig b/board/freescale/mx7d_19x19_ddr3_arm2/Kconfig new file mode 100644 index 00000000000..b69dadb1b22 --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_arm2/Kconfig @@ -0,0 +1,14 @@ +if TARGET_MX7D_19X19_DDR3_ARM2 + +config SYS_BOARD + default "mx7d_19x19_ddr3_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7d_19x19_ddr3_arm2" + +config SYS_TEXT_BASE + default 0x87800000 +endif diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/Makefile b/board/freescale/mx7d_19x19_ddr3_arm2/Makefile new file mode 100644 index 00000000000..d7e89fd364e --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_arm2/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7d_19x19_ddr3_arm2.o diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg b/board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg new file mode 100644 index 00000000000..ad02389d902 --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_ddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000b24 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/imximage_TO_1_1.cfg b/board/freescale/mx7d_19x19_ddr3_arm2/imximage_TO_1_1.cfg new file mode 100644 index 00000000000..3cf82357e1a --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_arm2/imximage_TO_1_1.cfg @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_ddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30360070 0x00703021 +DATA 4 0x30360090 0x0 +DATA 4 0x30360070 0x00603021 +CHECK_BITS_SET 4 0x30360070 0x80000000 +DATA 4 0x30389880 0x1 + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000dee +DATA 4 0x3079007c 0x18181818 +DATA 4 0x30790080 0x18181818 +DATA 4 0x30790084 0x40401818 +DATA 4 0x30790088 0x00000040 +DATA 4 0x3079006c 0x40404040 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c b/board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c new file mode 100644 index 00000000000..a3283a6c35e --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c @@ -0,0 +1,645 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#ifdef CONFIG_SYS_I2C_MXC +#include +#include +#endif +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, + .gp = IMX_GPIO_NR(4, 8), + }, + .sda = { + .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, + .gp = IMX_GPIO_NR(4, 9), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC, + .gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC, + .gp = IMX_GPIO_NR(4, 10), + }, + .sda = { + .i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC, + .gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC, + .gp = IMX_GPIO_NR(4, 11), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_emmc_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_ECSPI2_MISO__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_ECSPI2_SS0__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX7D_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_GPIO1_IO12__SD2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD2_CD_B__GPIO5_IO9 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_GPIO1_IO13__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwm_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = ELCDIF1_IPS_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +static iomux_v3_cfg_t const per_rst_pads[] = { + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec2_pads[] = { + MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec2(void) +{ + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_QSPI + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); + + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 9) +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14) + +#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(5, 11) +#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) + + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; /* Assume uSDHC1 emmc is always present */ + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} +int board_mmc_init(bd_t *bis) +{ + int i; + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 (eMMC) + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_emmc_pads, ARRAY_SIZE(usdhc1_emmc_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_pwr"); + gpio_request(USDHC2_CD_GPIO, "usdhc2_cd"); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); + gpio_request(USDHC3_CD_GPIO, "usdhc3_cd"); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec2(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + /* Use 125M anatop REF_CLK for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0); + + ret = set_clk_enet(ENET_125MHZ); + if (ret) + return ret; + + return 0; +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS0 */ + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(4, 19), "ecspi1_cs"); + gpio_direction_output(IMX_GPIO_NR(4, 19), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 19)) : -1; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX7 +#ifndef CONFIG_DM_USB +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads)); + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads)); +} +#endif +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_USB_EHCI_MX7 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* Reset peripherals */ + imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 3), "per_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 3), 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 3), 1); + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x10, 0x16, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)}, + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE3000"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE3000_DEVICEID, ®); + pmic_reg_read(p, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); + + /* set SW1B normal voltage to 0.975V */ + pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(9750); + pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id, reg; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + /* set SW1B normal voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(9750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX7D 19x19 DDR3 ARM2\n"); + + return 0; +} diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/plugin.S b/board/freescale/mx7d_19x19_ddr3_arm2/plugin.S new file mode 100644 index 00000000000..c2ca47a4fe4 --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_arm2/plugin.S @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x18181818 + str r1, [r0, #0x7c] + ldr r1, =0x18181818 + str r1, [r0, #0x80] + ldr r1, =0x40401818 + str r1, [r0, #0x84] + ldr r1, =0x00000040 + str r1, [r0, #0x88] + ldr r1, =0x40404040 + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_ddr_freq_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne FREQ_DEFAULT_533 + + /* Change to 400Mhz for TO1.1 */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x70 + ldr r2, =0x00703021 + str r2, [r0, r1] + ldr r1, =0x90 + ldr r2, =0x0 + str r2, [r0, r1] + ldr r1, =0x70 + ldr r2, =0x00603021 + str r2, [r0, r1] + + ldr r3, =0x80000000 +wait_lock: + ldr r2, [r0, r1] + and r2, r3 + cmp r2, r3 + bne wait_lock + + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x9880 + ldr r2, =0x1 + str r2, [r0, r1] + +FREQ_DEFAULT_533: +.endm + +.macro imx7d_19x19_ddr3_arm2_ddr_setting + imx7d_ddr_freq_setting + + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x01040001 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00400046 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00020001 + str r1, [r0, #0xd0] + ldr r1, =0x00690000 + str r1, [r0, #0xd4] + ldr r1, =0x09300004 + str r1, [r0, #0xdc] + ldr r1, =0x04080000 + str r1, [r0, #0xe0] + ldr r1, =0x00100004 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x09081109 + str r1, [r0, #0x100] + ldr r1, =0x0007020d + str r1, [r0, #0x104] + ldr r1, =0x03040407 + str r1, [r0, #0x108] + ldr r1, =0x00002006 + str r1, [r0, #0x10c] + ldr r1, =0x04020205 + str r1, [r0, #0x110] + ldr r1, =0x03030202 + str r1, [r0, #0x114] + ldr r1, =0x00000803 + str r1, [r0, #0x120] + ldr r1, =0x00800020 + str r1, [r0, #0x180] + ldr r1, =0x02000100 + str r1, [r0, #0x184] + ldr r1, =0x02098204 + str r1, [r0, #0x190] + ldr r1, =0x00030303 + str r1, [r0, #0x194] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00080808 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 + str r1, [r0, #0x214] + ldr r1, =0x0f070707 + str r1, [r0, #0x218] + + ldr r1, =0x06000604 + str r1, [r0, #0x240] + ldr r1, =0x00000001 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17420f40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00060807 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + imx7d_ddrphy_latency_setting + ldr r1, =0x08080808 + str r1, [r0, #0x20] + ldr r1, =0x08080808 + str r1, [r0, #0x30] + ldr r1, =0x01000010 + str r1, [r0, #0x50] + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_19x19_ddr3_arm2_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig b/board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig new file mode 100644 index 00000000000..d4111f1b2a1 --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig @@ -0,0 +1,20 @@ +if TARGET_MX7D_19X19_LPDDR3_ARM2 || TARGET_MX7D_19X19_LPDDR2_ARM2 + +config SYS_BOARD + default "mx7d_19x19_lpddr3_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7d_19x19_lpddr3_arm2" + +config SYS_TEXT_BASE + default 0x87800000 + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. +endif diff --git a/board/freescale/mx7d_19x19_lpddr3_arm2/Makefile b/board/freescale/mx7d_19x19_lpddr3_arm2/Makefile new file mode 100644 index 00000000000..6faae15ed86 --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_arm2/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7d_19x19_lpddr3_arm2.o diff --git a/board/freescale/mx7d_19x19_lpddr3_arm2/imximage.cfg b/board/freescale/mx7d_19x19_lpddr3_arm2/imximage.cfg new file mode 100644 index 00000000000..ec81ebd89da --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_arm2/imximage.cfg @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03040008 +DATA 4 0x307a0064 0x00200038 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00dc 0x00c3000a +DATA 4 0x307a00e0 0x00010000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x0a0e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x03060708 +DATA 4 0x307a010c 0x00a0500c +DATA 4 0x307a0110 0x05020307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098205 +DATA 4 0x307a0194 0x00060303 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 + +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00090909 +DATA 4 0x307a0210 0x00000f00 +DATA 4 0x307a0214 0x08080808 +DATA 4 0x307a0218 0x0f0f0808 + +DATA 4 0x307a0240 0x06000600 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421e40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x0007080c +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009c 0x00000b24 + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x30790018 0x0000000f +DATA 4 0x307900c0 0x0e487304 +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e4c7306 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_TO_1_1.cfg b/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_TO_1_1.cfg new file mode 100644 index 00000000000..fbd79821fb4 --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_TO_1_1.cfg @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03040008 +DATA 4 0x307a0064 0x00200038 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00dc 0x00c3000a +DATA 4 0x307a00e0 0x00010000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x0a0e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x03060708 +DATA 4 0x307a010c 0x00a0500c +DATA 4 0x307a0110 0x05020307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098205 +DATA 4 0x307a0194 0x00060303 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 + +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00090909 +DATA 4 0x307a0210 0x00000f00 +DATA 4 0x307a0214 0x08080808 +DATA 4 0x307a0218 0x0f0f0808 + +DATA 4 0x307a0240 0x06000601 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421e40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x0007080c +DATA 4 0x3079007c 0x1c1c1c1c +DATA 4 0x30790080 0x1c1c1c1c +DATA 4 0x30790084 0x30301c1c +DATA 4 0x30790088 0x00000030 +DATA 4 0x3079006c 0x30303030 +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009c 0x0db60d6e + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x30790018 0x0000000f +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487306 +DATA 4 0x307900c0 0x1e4c7304 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x1e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg b/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg new file mode 100644 index 00000000000..171d2ad30aa --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03020004 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00200023 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00d8 0x00001105 +DATA 4 0x307a00dc 0x00c20006 +DATA 4 0x307a00e0 0x00020000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x080e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x02040706 +DATA 4 0x307a010c 0x00504000 +DATA 4 0x307a0110 0x05010307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098203 +DATA 4 0x307a0194 0x00060303 + +DATA 4 0x307a0200 0x00000015 +DATA 4 0x307a0204 0x00161616 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x04040404 +DATA 4 0x307a0218 0x0f0f0404 + +DATA 4 0x307a0240 0x06000600 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421640 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x00050408 +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009C 0x00000d6e +DATA 4 0x30790018 0x0000000f + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x307900c0 0x0e487304 +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e4c7306 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x000001f8 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2_TO_1_1.cfg b/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2_TO_1_1.cfg new file mode 100644 index 00000000000..ab49d573edd --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2_TO_1_1.cfg @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03020004 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00200023 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00d8 0x00001105 +DATA 4 0x307a00dc 0x00c20006 +DATA 4 0x307a00e0 0x00020000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x080e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x02040706 +DATA 4 0x307a010c 0x00504000 +DATA 4 0x307a0110 0x05010307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098203 +DATA 4 0x307a0194 0x00060303 + +DATA 4 0x307a0200 0x00000015 +DATA 4 0x307a0204 0x00161616 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x04040404 +DATA 4 0x307a0218 0x0f0f0404 + +DATA 4 0x307a0240 0x06000600 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421640 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x00050408 +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009C 0x00000dee +DATA 4 0x3079007c 0x08080808 +DATA 4 0x30790080 0x08080808 +DATA 4 0x30790084 0x0a0a0808 +DATA 4 0x30790088 0x0000000a +DATA 4 0x3079006c 0x0a0a0a0a +DATA 4 0x30790018 0x0000000f + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x307900c0 0x0e487304 +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e4c7306 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x000001f8 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_19x19_lpddr3_arm2/mx7d_19x19_lpddr3_arm2.c b/board/freescale/mx7d_19x19_lpddr3_arm2/mx7d_19x19_lpddr3_arm2.c new file mode 100644 index 00000000000..e5f8260418e --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_arm2/mx7d_19x19_lpddr3_arm2.c @@ -0,0 +1,640 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#ifdef CONFIG_SYS_I2C +#include +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_PUS_PU100KOHM) + + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, + .gp = IMX_GPIO_NR(4, 8), + }, + .sda = { + .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, + .gp = IMX_GPIO_NR(4, 9), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC, + .gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC, + .gp = IMX_GPIO_NR(4, 10), + }, + .sda = { + .i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC, + .gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC, + .gp = IMX_GPIO_NR(4, 11), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_GPIO1_IO08__SD1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_MTD_NOR_FLASH +static iomux_v3_cfg_t const eimnor_pads[] = { + MX7D_PAD_LCD_DATA00__EIM_DATA0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA01__EIM_DATA1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA02__EIM_DATA2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA03__EIM_DATA3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA04__EIM_DATA4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA05__EIM_DATA5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA06__EIM_DATA6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA07__EIM_DATA7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA08__EIM_DATA8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA09__EIM_DATA9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA10__EIM_DATA10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA11__EIM_DATA11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA12__EIM_DATA12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA13__EIM_DATA13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA14__EIM_DATA14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA15__EIM_DATA15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX7D_PAD_EPDC_DATA00__EIM_AD0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__EIM_AD1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__EIM_AD2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__EIM_AD3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__EIM_AD4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__EIM_AD5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__EIM_AD6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__EIM_AD7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_BDR1__EIM_AD8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_PWR_COM__EIM_AD9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_BDR0__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA20__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA21__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA22__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX7D_PAD_EPDC_DATA08__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA09__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA10__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA12__EIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA13__EIM_WAIT | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), +}; + +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_IPS_BASE_ADDR + 0x090); + writel(0x00210081, WEIM_IPS_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_IPS_BASE_ADDR + 0x004); + writel(0x0e020000, WEIM_IPS_BASE_ADDR + 0x008); + writel(0x00000000, WEIM_IPS_BASE_ADDR + 0x00c); + writel(0x0704a040, WEIM_IPS_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + imx_iomux_v3_setup_multiple_pads(eimnor_pads, + ARRAY_SIZE(eimnor_pads)); + + eimnor_cs_setup(); +} +#endif + +static iomux_v3_cfg_t const per_rst_pads[] = { + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec2_pads[] = { + MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec2(void) +{ + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +static iomux_v3_cfg_t const quadspi_pads[] = { + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); +#endif + + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + /* + * NAND_USDHC_BUS_CLK is set in rom + */ + + set_clk_nand(); + + /* + * APBH clock root is set in init_esdhc, USDHC3_CLK. + * There is no clk gate for APBHDMA. + * No touch here. + */ +} +#endif + + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) + + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); + gpio_direction_input(USDHC1_CD_GPIO); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec2(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + /* Use 125M anatop REF_CLK for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0); + + ret = set_clk_enet(ENET_125MHZ); + if (ret) + return ret; + + return 0; +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS0 */ + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); + gpio_direction_output(IMX_GPIO_NR(4, 7), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 7)) : -1; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX7 +#ifndef CONFIG_DM_USB + +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads)); + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads)); +} +#endif +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_USB_EHCI_MX7 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* Reset peripherals */ + imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 3), "per rst"); + gpio_direction_output(IMX_GPIO_NR(1, 3) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 3), 1); + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_eimnor(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x10, 0x12, 0x00, 0x00)}, + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE3000"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE3000_DEVICEID, ®); + pmic_reg_read(p, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); + + /* set SW1B normal voltage to 0.975V */ + pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(9750); + pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id, reg; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + /* set SW1B normal voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(9750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_MX7D_19X19_LPDDR2_ARM2 + puts("Board: MX7D 19x19 LPDDR2 ARM2\n"); +#else + puts("Board: MX7D 19x19 LPDDR3 ARM2\n"); +#endif + return 0; +} diff --git a/board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S b/board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S new file mode 100644 index 00000000000..85db17472bb --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S @@ -0,0 +1,378 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_lpddr3_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne TUNE_END + + /*TO 1.1*/ + ldr r1, =0x1c1c1c1c + str r1, [r0, #0x7c] + ldr r1, =0x1c1c1c1c + str r1, [r0, #0x80] + ldr r1, =0x30301c1c + str r1, [r0, #0x84] + ldr r1, =0x00000030 + str r1, [r0, #0x88] + ldr r1, =0x30303030 + str r1, [r0, #0x6c] + +TUNE_END: +.endm + +.macro imx7d_ddrphy_lpddr2_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x08080808 + str r1, [r0, #0x7c] + ldr r1, =0x08080808 + str r1, [r0, #0x80] + ldr r1, =0x0a0a0808 + str r1, [r0, #0x84] + ldr r1, =0x0000000a + str r1, [r0, #0x88] + ldr r1, =0x0a0a0a0a + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000d6e + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_19x19_lpddr3_arm2_setting + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x03040008 + str r1, [r0] + ldr r1, =0x00200038 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00350001 + str r1, [r0, #0xd0] + ldr r1, =0x00c3000a + str r1, [r0, #0xdc] + ldr r1, =0x00010000 + str r1, [r0, #0xe0] + ldr r1, =0x00110006 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x0a0e110b + str r1, [r0, #0x100] + ldr r1, =0x00020211 + str r1, [r0, #0x104] + ldr r1, =0x03060708 + str r1, [r0, #0x108] + ldr r1, =0x00a0500c + str r1, [r0, #0x10c] + ldr r1, =0x05020307 + str r1, [r0, #0x110] + ldr r1, =0x02020404 + str r1, [r0, #0x114] + ldr r1, =0x02020003 + str r1, [r0, #0x118] + ldr r1, =0x00000202 + str r1, [r0, #0x11c] + ldr r1, =0x00000202 + str r1, [r0, #0x120] + ldr r1, =0x00600018 + str r1, [r0, #0x180] + ldr r1, =0x00e00100 + str r1, [r0, #0x184] + ldr r1, =0x02098205 + str r1, [r0, #0x190] + ldr r1, =0x00060303 + str r1, [r0, #0x194] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00090909 + str r1, [r0, #0x204] + ldr r1, =0x00000f00 + str r1, [r0, #0x210] + ldr r1, =0x08080808 + str r1, [r0, #0x214] + ldr r1, =0x0f0f0808 + str r1, [r0, #0x218] + + ldr r1, =0x06000600 + str r1, [r0, #0x240] + mov r1, #0x0 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17421e40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00010000 + str r1, [r0, #0x8] + ldr r1, =0x0007080c + str r1, [r0, #0x10] + imx7d_ddrphy_lpddr3_latency_setting + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + ldr r1, =0x01010000 + str r1, [r0, #0x1c] + + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne 1f + + ldr r1, =0x0db60d6e + str r1, [r0, #0x9c] + b 2f +1: + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] +2: + ldr r1, =0x06060606 + str r1, [r0, #0x30] + ldr r1, =0x0a0a0a0a + str r1, [r0, #0x20] + ldr r1, =0x01000008 + str r1, [r0, #0x50] + ldr r1, =0x00000008 + str r1, [r0, #0x50] + + ldr r1, =0x0000000f + str r1, [r0, #0x18] + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7d_19x19_lpddr2_arm2_setting + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x03020004 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00200023 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00350001 + str r1, [r0, #0xd0] + ldr r1, =0x00001105 + str r1, [r0, #0xd8] + ldr r1, =0x00c20006 + str r1, [r0, #0xdc] + ldr r1, =0x00020000 + str r1, [r0, #0xe0] + ldr r1, =0x00110006 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x080e110b + str r1, [r0, #0x100] + ldr r1, =0x00020211 + str r1, [r0, #0x104] + ldr r1, =0x02040706 + str r1, [r0, #0x108] + ldr r1, =0x00504000 + str r1, [r0, #0x10c] + ldr r1, =0x05010307 + str r1, [r0, #0x110] + ldr r1, =0x02020404 + str r1, [r0, #0x114] + ldr r1, =0x02020003 + str r1, [r0, #0x118] + ldr r1, =0x00000202 + str r1, [r0, #0x11c] + ldr r1, =0x00000202 + str r1, [r0, #0x120] + ldr r1, =0x00600018 + str r1, [r0, #0x180] + ldr r1, =0x00e00100 + str r1, [r0, #0x184] + ldr r1, =0x02098203 + str r1, [r0, #0x190] + ldr r1, =0x00060303 + str r1, [r0, #0x194] + + ldr r1, =0x00000015 + str r1, [r0, #0x200] + ldr r1, =0x00161616 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x04040404 + str r1, [r0, #0x214] + ldr r1, =0x0f0f0404 + str r1, [r0, #0x218] + + ldr r1, =0x06000600 + str r1, [r0, #0x240] + mov r1, #0x0 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17421640 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00010000 + str r1, [r0, #0x8] + ldr r1, =0x00050408 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + ldr r1, =0x01010000 + str r1, [r0, #0x1c] + imx7d_ddrphy_lpddr2_latency_setting + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r1, =0x06060606 + str r1, [r0, #0x30] + ldr r1, =0x0a0a0a0a + str r1, [r0, #0x20] + ldr r1, =0x01000008 + str r1, [r0, #0x50] + ldr r1, =0x00000008 + str r1, [r0, #0x50] + + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e4c7304 + str r1, [r0, #0xc0] + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x1f8 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting +#if defined (TARGET_MX7D_19X19_LPDDR2_ARM2) + imx7d_19x19_lpddr2_arm2_setting +#else + imx7d_19x19_lpddr3_arm2_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx7dsabresd/Kconfig b/board/freescale/mx7dsabresd/Kconfig index c6a969ca67f..beef4c06d1a 100644 --- a/board/freescale/mx7dsabresd/Kconfig +++ b/board/freescale/mx7dsabresd/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx7dsabresd" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg index c2b3a8c9c4b..07497a12ed6 100644 --- a/board/freescale/mx7dsabresd/imximage.cfg +++ b/board/freescale/mx7dsabresd/imximage.cfg @@ -1,5 +1,6 @@ /* * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ * @@ -22,6 +23,10 @@ IMAGE_VERSION 2 BOOT_FROM sd +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000 +#else /* * Secure boot support */ @@ -41,7 +46,14 @@ CSF CONFIG_CSF_SIZE * value value to be stored in the register */ +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x30340024 0x1 +CHECK_BITS_SET 4 0x30340024 0x1 +#endif DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 DATA 4 0x30391000 0x00000002 DATA 4 0x307a0000 0x01040001 @@ -68,9 +80,10 @@ DATA 4 0x307a0184 0x02000100 DATA 4 0x307a0190 0x02098204 DATA 4 0x307a0194 0x00030303 DATA 4 0x307a0200 0x00000016 -DATA 4 0x307a0204 0x00171717 -DATA 4 0x307a0214 0x04040404 -DATA 4 0x307a0218 0x0f040404 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 DATA 4 0x307a0240 0x06000604 DATA 4 0x307a0244 0x00000001 DATA 4 0x30391000 0x00000000 @@ -78,7 +91,7 @@ DATA 4 0x30790000 0x17420f40 DATA 4 0x30790004 0x10210100 DATA 4 0x30790010 0x00060807 DATA 4 0x307900b0 0x1010007e -DATA 4 0x3079009c 0x00000d6e +DATA 4 0x3079009c 0x00000b24 DATA 4 0x30790020 0x08080808 DATA 4 0x30790030 0x08080808 DATA 4 0x30790050 0x01000010 @@ -90,7 +103,6 @@ DATA 4 0x307900c0 0x0e447306 CHECK_BITS_SET 4 0x307900c4 0x1 -DATA 4 0x307900c0 0x0e447304 DATA 4 0x307900c0 0x0e407304 DATA 4 0x30384130 0x00000000 @@ -99,3 +111,5 @@ DATA 4 0x30384130 0x00000002 DATA 4 0x30790018 0x0000000f CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg new file mode 100644 index 00000000000..70596f167bd --- /dev/null +++ b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x30340024 0x1 +CHECK_BITS_SET 4 0x30340024 0x1 +#endif +DATA 4 0x30360070 0x00703021 +DATA 4 0x30360090 0x0 +DATA 4 0x30360070 0x00603021 +CHECK_BITS_SET 4 0x30360070 0x80000000 +DATA 4 0x30389880 0x1 + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000dee +DATA 4 0x3079007c 0x18181818 +DATA 4 0x30790080 0x18181818 +DATA 4 0x30790084 0x40401818 +DATA 4 0x30790088 0x00000040 +DATA 4 0x3079006c 0x40404040 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 5819b1825dc..ffc75fa3635 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +25,18 @@ #include #include #include +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#include + +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -47,6 +61,10 @@ DECLARE_GLOBAL_DATA_PTR; #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) +#define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define EPDC_PAD_CTRL 0x0 + #ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t const ecspi3_pads[] = { MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -82,6 +100,55 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#define BOARD_REV_C 0x300 +#define BOARD_REV_B 0x200 +#define BOARD_REV_A 0x100 + +static int mx7sabre_rev(void) +{ + /* + * Get Board ID information from OCOTP_GP1[15:8] + * i.MX7D SDB RevA: 0x41 + * i.MX7D SDB RevB: 0x42 + */ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[14]; + int reg = readl(&bank->fuse_regs[0]); + int ret; + + if (reg != 0) { + switch (reg >> 8 & 0x0F) { + case 0x3: + ret = BOARD_REV_C; + break; + case 0x02: + ret = BOARD_REV_B; + break; + case 0x01: + default: + ret = BOARD_REV_A; + break; + } + } else { + /* If the gp1 fuse is not burn, we have to use TO rev for the board rev */ + if (is_soc_rev(CHIP_REV_1_0)) + ret = BOARD_REV_A; + else if (is_soc_rev(CHIP_REV_1_1)) + ret = BOARD_REV_B; + else + ret = BOARD_REV_C; + } + + return ret; +} + +u32 get_board_rev(void) +{ + int rev = mx7sabre_rev(); + + return (get_cpu_rev() & ~(0xF << 8)) | rev; +} + #ifdef CONFIG_NAND_MXS static iomux_v3_cfg_t const gpmi_pads[] = { MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), @@ -153,7 +220,7 @@ static iomux_v3_cfg_t const pwm_pads[] = { MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static int setup_lcd(void) +void do_enable_parallel_lcd(struct display_info_t const *dev) { imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); @@ -168,35 +235,32 @@ static int setup_lcd(void) /* Set Brightness to high */ gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight"); gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); - - return 0; } -#endif - -#ifdef CONFIG_FEC_MXC -static iomux_v3_cfg_t const fec1_pads[] = { - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), - MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), -}; -static void setup_iomux_fec(void) -{ - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); -} +struct display_info_t const displays[] = {{ + .bus = ELCDIF1_IPS_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "TFT43AB", + .xres = 480, + .yres = 272, + .pixclock = 108695, + .left_margin = 8, + .right_margin = 4, + .upper_margin = 2, + .lower_margin = 4, + .hsync_len = 41, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); #endif + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -219,8 +283,11 @@ int mmc_map_to_kernel_blk(int dev_no) } #ifdef CONFIG_FEC_MXC -int board_eth_init(bd_t *bis) +static int setup_fec(int fec_id) { + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; unsigned int gpio; @@ -230,7 +297,7 @@ int board_eth_init(bd_t *bis) return -ENODEV; } - ret = gpio_request(gpio, "fec_rst"); + ret = gpio_request(gpio, "enet_phy_rst"); if (ret && ret != -EBUSY) { printf("gpio: requesting pin %u failed\n", gpio); return ret; @@ -240,30 +307,29 @@ int board_eth_init(bd_t *bis) udelay(500); gpio_direction_output(gpio, 1); - setup_iomux_fec(); - - ret = fecmxc_initialize_multi(bis, 0, - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); - if (ret) - printf("FEC1 MXC: %s:failed\n", __func__); - - return ret; -} - -static int setup_fec(void) -{ - struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs - = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; - - /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ - clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], - (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | - IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + if (0 == fec_id) { + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + } else { + /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0); + + if (mx7sabre_rev() >= BOARD_REV_B) { + /* On RevB, GPIO1_IO04 is used for ENET2 EN, + * so set its output to low to enable ENET2 signals + */ + gpio_request(IMX_GPIO_NR(1, 4), "fec2_en"); + gpio_direction_output(IMX_GPIO_NR(1, 4), 0); + } + } return set_clk_enet(ENET_125MHZ); } - int board_phy_config(struct phy_device *phydev) { /* enable rgmii rxc skew and phy mode select to RGMII copper */ @@ -279,6 +345,7 @@ int board_phy_config(struct phy_device *phydev) #endif #ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI static iomux_v3_cfg_t const quadspi_pads[] = { MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), @@ -287,12 +354,15 @@ static iomux_v3_cfg_t const quadspi_pads[] = { MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), }; +#endif int board_qspi_init(void) { +#ifndef CONFIG_DM_SPI /* Set the iomux */ imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); +#endif /* Set the clock */ set_clk_qspi(); @@ -301,6 +371,221 @@ int board_qspi_init(void) } #endif +#ifdef CONFIG_MXC_EPDC +iomux_v3_cfg_t const epdc_en_pads[] = { + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX7D_PAD_EPDC_DATA00__GPIO2_IO0, + MX7D_PAD_EPDC_DATA01__GPIO2_IO1, + MX7D_PAD_EPDC_DATA02__GPIO2_IO2, + MX7D_PAD_EPDC_DATA03__GPIO2_IO3, + MX7D_PAD_EPDC_DATA04__GPIO2_IO4, + MX7D_PAD_EPDC_DATA05__GPIO2_IO5, + MX7D_PAD_EPDC_DATA06__GPIO2_IO6, + MX7D_PAD_EPDC_DATA07__GPIO2_IO7, + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16, + MX7D_PAD_EPDC_SDLE__GPIO2_IO17, + MX7D_PAD_EPDC_SDOE__GPIO2_IO18, + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19, + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20, + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21, + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24, + MX7D_PAD_EPDC_GDOE__GPIO2_IO25, + MX7D_PAD_EPDC_GDRL__GPIO2_IO26, + MX7D_PAD_EPDC_GDSP__GPIO2_IO27, + MX7D_PAD_EPDC_BDR0__GPIO2_IO28, + MX7D_PAD_EPDC_BDR1__GPIO2_IO29, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0); + + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 31), "epdc_pwrstat"); + gpio_direction_input(IMX_GPIO_NR(2, 31)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_request(IMX_GPIO_NR(4, 14), "epdc_vcom"); + gpio_direction_output(IMX_GPIO_NR(4, 14), 1); + + /* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 23), "epdc_pmic"); + gpio_direction_output(IMX_GPIO_NR(2, 23), 1); + + /* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 30), "epdc_pwr_ctl0"); + gpio_direction_output(IMX_GPIO_NR(2, 30), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + /*** epdc Maxim PMIC settings ***/ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 30), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 23), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 31))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 23), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 30), 0); +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -314,21 +599,32 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC - setup_fec(); + setup_fec(CONFIG_FEC_ENET_DEV); #endif #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif -#ifdef CONFIG_VIDEO_MXS - setup_lcd(); -#endif - #ifdef CONFIG_FSL_QSPI board_qspi_init(); #endif +#ifdef CONFIG_MXC_EPDC + if (mx7sabre_rev() >= BOARD_REV_B) { + /* + * On RevB, GPIO1_IO04 is used for ENET2 EN, + * so set its output to high to isolate the + * ENET2 signals for EPDC + */ + imx_iomux_v3_setup_multiple_pads(epdc_en_pads, + ARRAY_SIZE(epdc_en_pads)); + gpio_request(IMX_GPIO_NR(1, 4), "epdc_en"); + gpio_direction_output(IMX_GPIO_NR(1, 4), 1); + } + setup_epdc(); +#endif + #ifdef CONFIG_MXC_SPI setup_spi(); #endif @@ -336,11 +632,23 @@ int board_init(void) return 0; } +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, + /* TODO: Nand */ + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + #ifdef CONFIG_DM_PMIC int power_init_board(void) { struct udevice *dev; int ret, dev_id, rev_id; + u32 sw3mode; ret = pmic_get("pfuze3000", &dev); if (ret == -ENODEV) @@ -359,6 +667,12 @@ int power_init_board(void) * the MIPI DSI and MIPI CSI inputs. */ pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA); + + /* change sw3 mode to avoid DDR power off */ + sw3mode = pmic_reg_read(dev, PFUZE3000_SW3MODE); + ret = pmic_reg_write(dev, PFUZE3000_SW3MODE, sw3mode | 0x20); + if (ret < 0) + printf("PMIC: PFUZE3000 change sw3 mode failed\n"); return 0; } @@ -367,30 +681,82 @@ int power_init_board(void) int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); - /* - * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), - * since we use PMIC_PWRON to reset the board. - */ - clrsetbits_le16(&wdog->wcr, 0, 0x10); - return 0; } int checkboard(void) { + int rev = mx7sabre_rev(); char *mode; + char *revname; if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) mode = "secure"; else mode = "non-secure"; - printf("Board: i.MX7D SABRESD in %s mode\n", mode); + switch (rev) { + case BOARD_REV_C: + revname = "C"; + break; + case BOARD_REV_B: + revname = "B"; + break; + case BOARD_REV_A: + default: + revname = "A"; + break; + } + + printf("Board: i.MX7D SABRESD Rev%s in %s mode\n", revname, mode); return 0; } + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY + +/* Use S3 button for recovery key */ +#define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10) +iomux_v3_cfg_t const recovery_key_pads[] = { + (MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)), +}; + +int is_recovery_key_pressing(void) +{ + int button_pressed = 0; + + /* Check Recovery Combo Button press or not. */ + imx_iomux_v3_setup_multiple_pads(recovery_key_pads, + ARRAY_SIZE(recovery_key_pads)); + + gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key"); + gpio_direction_input(GPIO_VOL_DN_KEY); + + if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return button_pressed; +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/freescale/mx7dsabresd/plugin.S b/board/freescale/mx7dsabresd/plugin.S new file mode 100644 index 00000000000..1f64e468350 --- /dev/null +++ b/board/freescale/mx7dsabresd/plugin.S @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x18181818 + str r1, [r0, #0x7c] + ldr r1, =0x18181818 + str r1, [r0, #0x80] + ldr r1, =0x40401818 + str r1, [r0, #0x84] + ldr r1, =0x00000040 + str r1, [r0, #0x88] + ldr r1, =0x40404040 + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_ddr_freq_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne FREQ_DEFAULT_533 + + /* Change to 400Mhz for TO1.1 */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x70 + ldr r2, =0x00703021 + str r2, [r0, r1] + ldr r1, =0x90 + ldr r2, =0x0 + str r2, [r0, r1] + ldr r1, =0x70 + ldr r2, =0x00603021 + str r2, [r0, r1] + + ldr r3, =0x80000000 +wait_lock: + ldr r2, [r0, r1] + and r2, r3 + cmp r2, r3 + bne wait_lock + + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x9880 + ldr r2, =0x1 + str r2, [r0, r1] + +FREQ_DEFAULT_533: +.endm + +.macro imx7d_sabresd_ddr_setting + imx7d_ddr_freq_setting + + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x01040001 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00400046 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00020001 + str r1, [r0, #0xd0] + ldr r1, =0x00690000 + str r1, [r0, #0xd4] + ldr r1, =0x09300004 + str r1, [r0, #0xdc] + ldr r1, =0x04080000 + str r1, [r0, #0xe0] + ldr r1, =0x00100004 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x09081109 + str r1, [r0, #0x100] + ldr r1, =0x0007020d + str r1, [r0, #0x104] + ldr r1, =0x03040407 + str r1, [r0, #0x108] + ldr r1, =0x00002006 + str r1, [r0, #0x10c] + ldr r1, =0x04020205 + str r1, [r0, #0x110] + ldr r1, =0x03030202 + str r1, [r0, #0x114] + ldr r1, =0x00000803 + str r1, [r0, #0x120] + ldr r1, =0x00800020 + str r1, [r0, #0x180] + ldr r1, =0x02000100 + str r1, [r0, #0x184] + ldr r1, =0x02098204 + str r1, [r0, #0x190] + ldr r1, =0x00030303 + str r1, [r0, #0x194] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00080808 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 + str r1, [r0, #0x214] + ldr r1, =0x0f070707 + str r1, [r0, #0x218] + + ldr r1, =0x06000604 + str r1, [r0, #0x240] + ldr r1, =0x00000001 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17420f40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00060807 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + imx7d_ddrphy_latency_setting + ldr r1, =0x08080808 + str r1, [r0, #0x20] + ldr r1, =0x08080808 + str r1, [r0, #0x30] + ldr r1, =0x01000010 + str r1, [r0, #0x50] + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x30340024 + ldr r1, =0x1 + str r1, [r0] +#endif +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_sabresd_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx7ulp_arm2/Kconfig b/board/freescale/mx7ulp_arm2/Kconfig new file mode 100644 index 00000000000..7fa0c0bbf35 --- /dev/null +++ b/board/freescale/mx7ulp_arm2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX7ULP_10X10_ARM2 || TARGET_MX7ULP_14X14_ARM2 + +config SYS_BOARD + default "mx7ulp_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7ulp_arm2" + +endif diff --git a/board/freescale/mx7ulp_arm2/Makefile b/board/freescale/mx7ulp_arm2/Makefile new file mode 100644 index 00000000000..57e795a0786 --- /dev/null +++ b/board/freescale/mx7ulp_arm2/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7ulp_arm2.o diff --git a/board/freescale/mx7ulp_arm2/imximage.cfg b/board/freescale/mx7ulp_arm2/imximage.cfg new file mode 100644 index 00000000000..5cb6e0094b3 --- /dev/null +++ b/board/freescale/mx7ulp_arm2/imximage.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7ulp_arm2/plugin.bin 0x2F020000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x403f00e0 0x00000000 +DATA 4 0x403e0040 0x01000020 +DATA 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808080 +DATA 4 0x403e0508 0x00160002 +DATA 4 0x403E0510 0x00000000 +DATA 4 0x403E0514 0x00000001 +DATA 4 0x403e0500 0x00000001 +CHECK_BITS_SET 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808019 +CHECK_BITS_SET 4 0x403e050c 0x00000040 +DATA 4 0x403E0030 0x00000001 +DATA 4 0x403e0040 0x11000020 +DATA 4 0x403f00e0 0x42000000 + +DATA 4 0x40B300AC 0x40000000 + +DATA 4 0x40AD0128 0x00040000 +DATA 4 0x40AD00F8 0x00000000 +DATA 4 0x40AD00D8 0x00000180 +DATA 4 0x40AD0108 0x00000180 +DATA 4 0x40AD0104 0x00000180 +DATA 4 0x40AD0124 0x00010000 +DATA 4 0x40AD0080 0x0000018C +DATA 4 0x40AD0084 0x0000018C +DATA 4 0x40AD0088 0x0000018C +DATA 4 0x40AD008C 0x0000018C + +DATA 4 0x40AD0120 0x00010000 +DATA 4 0x40AD010C 0x00000180 +DATA 4 0x40AD0110 0x00000180 +DATA 4 0x40AD0114 0x00000180 +DATA 4 0x40AD0118 0x00000180 +DATA 4 0x40AD0090 0x00000180 +DATA 4 0x40AD0094 0x00000180 +DATA 4 0x40AD0098 0x00000180 +DATA 4 0x40AD009C 0x00000180 + +DATA 4 0x40AD00E0 0x00040000 +DATA 4 0x40AD00E4 0x00040000 + +DATA 4 0x40AB001C 0x00008000 +DATA 4 0x40AB0800 0xA1390003 +DATA 4 0x40AB085C 0x0D3900A0 +DATA 4 0x40AB0890 0x00400000 + +DATA 4 0x40AB0848 0x39373939 +DATA 4 0x40AB0850 0x2F313D36 +DATA 4 0x40AB081C 0x33333333 +DATA 4 0x40AB0820 0x33333333 +DATA 4 0x40AB0824 0x33333333 +DATA 4 0x40AB0828 0x33333333 + +DATA 4 0x40AB08C0 0x24922492 +DATA 4 0x40AB08B8 0x00000800 + +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB000C 0x424642F3 +DATA 4 0x40AB0010 0x00100A22 +DATA 4 0x40AB0038 0x00120556 +DATA 4 0x40AB0014 0x00C700DA +DATA 4 0x40AB0018 0x00211718 +DATA 4 0x40AB002C 0x0F9F26D2 +DATA 4 0x40AB0030 0x009F0E10 +DATA 4 0x40AB0040 0x0000004F +DATA 4 0x40AB0000 0x84190000 + +DATA 4 0x40AB001C 0x00008010 +DATA 4 0x40AB001C 0x003F8030 +DATA 4 0x40AB001C 0xFF0A8030 +DATA 4 0x40AB001C 0x04028030 +DATA 4 0x40AB001C 0x83018030 +DATA 4 0x40AB001C 0x01038030 + +DATA 4 0x40AB083C 0x20000000 + +DATA 4 0x40AB0020 0x00001800 +DATA 4 0x40AB0800 0xA1310003 +DATA 4 0x40AB001C 0x00000000 + +#endif diff --git a/board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg b/board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg new file mode 100644 index 00000000000..43f05174984 --- /dev/null +++ b/board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg @@ -0,0 +1,133 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7ulp_arm2/plugin.bin 0x2F020000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x403f00e0 0x00000000 +DATA 4 0x403e0040 0x01000020 +DATA 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808080 +DATA 4 0x403e0508 0x00160002 +DATA 4 0x403E0510 0x00000000 +DATA 4 0x403E0514 0x00000001 +DATA 4 0x403e0500 0x00000001 +CHECK_BITS_SET 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808019 +CHECK_BITS_SET 4 0x403e050c 0x00000040 +DATA 4 0x403E0030 0x00000001 +DATA 4 0x403e0040 0x11000020 +DATA 4 0x403f00e0 0x42000000 + +DATA 4 0x40B300AC 0x40000000 + +DATA 4 0x40AD0128 0x00040000 +DATA 4 0x40AD00F8 0x00000000 +DATA 4 0x40AD00D8 0x0000018C +DATA 4 0x40AD0108 0x00000180 +DATA 4 0x40AD0104 0x00000180 +DATA 4 0x40AD0124 0x00010000 +DATA 4 0x40AD0080 0x0000018C +DATA 4 0x40AD0084 0x0000018C +DATA 4 0x40AD0088 0x0000018C +DATA 4 0x40AD008C 0x0000018C + +DATA 4 0x40AD0120 0x00010000 +DATA 4 0x40AD010C 0x00000180 +DATA 4 0x40AD0110 0x00000180 +DATA 4 0x40AD0114 0x00000180 +DATA 4 0x40AD0118 0x00000180 +DATA 4 0x40AD0090 0x00000180 +DATA 4 0x40AD0094 0x00000180 +DATA 4 0x40AD0098 0x00000180 +DATA 4 0x40AD009C 0x00000180 + +DATA 4 0x40AD00E0 0x00040000 +DATA 4 0x40AD00E4 0x00040000 + +DATA 4 0x40AB001C 0x00008000 +DATA 4 0x40AB0800 0xA1390003 +DATA 4 0x40AB085C 0x0D3900A0 +DATA 4 0x40AB0890 0x00400000 + +DATA 4 0x40AB0848 0x40404040 +DATA 4 0x40AB0850 0x40404040 +DATA 4 0x40AB081C 0x33333333 +DATA 4 0x40AB0820 0x33333333 +DATA 4 0x40AB0824 0x33333333 +DATA 4 0x40AB0828 0x33333333 + +DATA 4 0x40AB08C0 0x24922492 +DATA 4 0x40AB08B8 0x00000800 + +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB000C 0x292C42F3 +DATA 4 0x40AB0010 0x00100A22 +DATA 4 0x40AB0038 0x00120556 +DATA 4 0x40AB0014 0x00C700DB +DATA 4 0x40AB0018 0x00211708 +DATA 4 0x40AB002C 0x0F9F26D2 +DATA 4 0x40AB0030 0x009F0E10 +DATA 4 0x40AB0040 0x0000003F +DATA 4 0x40AB0000 0xC3110000 + +DATA 4 0x40AB001C 0x00008010 +DATA 4 0x40AB001C 0x00008018 +DATA 4 0x40AB001C 0x003F8030 +DATA 4 0x40AB001C 0x003F8038 +DATA 4 0x40AB001C 0xFF0A8030 +DATA 4 0x40AB001C 0xFF0A8038 +DATA 4 0x40AB001C 0x04028030 +DATA 4 0x40AB001C 0x04028038 +DATA 4 0x40AB001C 0x82018030 +DATA 4 0x40AB001C 0x82018038 +DATA 4 0x40AB001C 0x01038030 +DATA 4 0x40AB001C 0x01038038 + +DATA 4 0x40AB083C 0x20000000 + +DATA 4 0x40AB0020 0x00001800 +DATA 4 0x40AB0800 0xA1390003 +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB0404 0x00011006 +DATA 4 0x40AB001C 0x00000000 + +#endif diff --git a/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c b/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c new file mode 100644 index 00000000000..955f86da92b --- /dev/null +++ b/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE) +#define ESDHC_CD_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_PUS_UP) + +#define UART_PAD_CTRL (PAD_CTL_PUS_UP) + +#define GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_IBE_ENABLE) + +#define OTG_ID_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE) +#define OTG_PWR_GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE) + +#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE) + +#define QSPI_PAD_CTRL0 (PAD_CTL_PUS_UP | PAD_CTL_DSE \ + | PAD_CTL_OBE_ENABLE) + + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 +/* PTF11 and PTF10 also can mux to LPUART6 on 10x10 ARM2, depends on rework*/ +static iomux_cfg_t const lpuart6_pads[] = { + MX7ULP_PAD_PTE11__LPUART6_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7ULP_PAD_PTE10__LPUART6_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; +#else +static iomux_cfg_t const lpuart4_pads[] = { + MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; +#endif + +static void setup_iomux_uart(void) +{ +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 + mx7ulp_iomux_setup_multiple_pads(lpuart6_pads, ARRAY_SIZE(lpuart6_pads)); +#else + mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, ARRAY_SIZE(lpuart4_pads)); +#endif +} + +#ifdef CONFIG_USB_EHCI_MX7 + +static iomux_cfg_t const usb_otg1_pads[] = { + +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 + MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */ + MX7ULP_PAD_PTC1__PTC1 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */ +#else + /*Need rework for ID and PWR_EN pins on 14x14 ARM2*/ + MX7ULP_PAD_PTC18__PTC18 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */ + MX7ULP_PAD_PTA31__PTA31 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */ +#endif +}; + +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 +#define OTG0_ID_GPIO IMX_GPIO_NR(3, 0) +#define OTG0_PWR_EN IMX_GPIO_NR(3, 1) +#else +#define OTG0_ID_GPIO IMX_GPIO_NR(3, 18) +#define OTG0_PWR_EN IMX_GPIO_NR(1, 31) +#endif +static void setup_usb(void) +{ + mx7ulp_iomux_setup_multiple_pads(usb_otg1_pads, + ARRAY_SIZE(usb_otg1_pads)); + + gpio_request(OTG0_ID_GPIO, "otg_id"); + gpio_direction_input(OTG0_ID_GPIO); +} + +/*Needs to override the ehci power if controlled by GPIO */ +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + if (on) + gpio_direction_output(OTG0_PWR_EN, 1); + else + gpio_direction_output(OTG0_PWR_EN, 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + + return 0; +} + +int board_usb_phy_mode(int port) +{ + int ret = 0; + + if (port == 0) { + ret = gpio_get_value(OTG0_ID_GPIO); + + if (ret) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; + } + + return USB_INIT_HOST; +} + +#endif + + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_FSL_QSPI +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 +static iomux_cfg_t const quadspi_pads[] = { + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0), + MX7ULP_PAD_PTB14__QSPIA_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0), + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL0), + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + + MX7ULP_PAD_PTB5__PTB5 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +#define QSPI_RST_GPIO IMX_GPIO_NR(2, 5) +#else +/* MT35XU512ABA supports 8 bits I/O, since our driver only support 4, so mux 4 data pins*/ +static iomux_cfg_t const quadspi_pads[] = { + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0), + MX7ULP_PAD_PTB9__QSPIA_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL0), + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + + MX7ULP_PAD_PTB12__PTB12 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +#define QSPI_RST_GPIO IMX_GPIO_NR(2, 12) + +#endif +int board_qspi_init(void) +{ + u32 val; + mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); + /* enable clock */ + val = readl(PCC1_RBASE + 0x94); + + if (!(val & 0x20000000)) { + writel(0x03000003, (PCC1_RBASE + 0x94)); + writel(0x43000003, (PCC1_RBASE + 0x94)); + } + + /* Enable QSPI as a wakeup source on B0 */ + if (soc_rev() >= CHIP_REV_2_0) + setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL); + + gpio_request(QSPI_RST_GPIO, "qspi_reset"); + gpio_direction_output(QSPI_RST_GPIO, 0); + mdelay(10); + gpio_direction_output(QSPI_RST_GPIO, 1); + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_USB_EHCI_MX7 + setup_usb(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifndef CONFIG_DM_MMC +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC0_RBASE, 0, 8}, + {USDHC1_RBASE, 0}, +}; + +static iomux_cfg_t const usdhc0_emmc_pads[] = { + MX7ULP_PAD_PTD0__SDHC0_RESET_b | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTD1__SDHC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTD2__SDHC0_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTD3__SDHC0_D7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTD4__SDHC0_D6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTD5__SDHC0_D5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTD6__SDHC0_D4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTD7__SDHC0_D3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTD8__SDHC0_D2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTD9__SDHC0_D1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTD10__SDHC0_D0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTD11__SDHC0_DQS | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t const usdhc1_pads[] = { + MX7ULP_PAD_PTE11__SDHC1_RESET_b | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTE3__SDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTE2__SDHC1_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTE9__SDHC1_D7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTE8__SDHC1_D6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTE7__SDHC1_D5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTE6__SDHC1_D4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTE4__SDHC1_D3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTE5__SDHC1_D2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTE0__SDHC1_D1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTE1__SDHC1_D0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + MX7ULP_PAD_PTE10__SDHC1_DQS | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + + MX7ULP_PAD_PTE13__PTE13 | MUX_PAD_CTRL(ESDHC_CD_GPIO_PAD_CTRL), /*CD*/ +}; + +#define USDHC0_CD_GPIO IMX_GPIO_NR(5, 13) + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC0 + * mmc1 USDHC1 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + mx7ulp_iomux_setup_multiple_pads(usdhc0_emmc_pads, ARRAY_SIZE(usdhc0_emmc_pads)); + init_clk_usdhc(0); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + break; + case 1: + mx7ulp_iomux_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + init_clk_usdhc(1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + gpio_request(USDHC0_CD_GPIO, "usdhc1_cd"); + gpio_direction_input(USDHC0_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC0_RBASE: + ret = 1; + break; + case USDHC1_RBASE: + ret = !gpio_get_value(USDHC0_CD_GPIO); + break; + } + return ret; +} +#endif + + +int board_late_init(void) +{ + return 0; +} + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 + printf("Board: i.MX7ULP 10x10 ARM2 board\n"); +#else + printf("Board: i.MX7ULP 14x14 ARM2 board\n"); +#endif + return 0; +} diff --git a/board/freescale/mx7ulp_arm2/plugin.S b/board/freescale/mx7ulp_arm2/plugin.S new file mode 100644 index 00000000000..ce7b597bec8 --- /dev/null +++ b/board/freescale/mx7ulp_arm2/plugin.S @@ -0,0 +1,352 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +.macro imx7ulp_ddr_freq_decrease + ldr r2, =0x403f0000 + ldr r3, =0x00000000 + str r3, [r2, #0xe0] + + ldr r2, =0x403e0000 + ldr r3, =0x01000020 + str r3, [r2, #0x40] + ldr r3, =0x01000000 + str r3, [r2, #0x500] + + ldr r3, =0x80808080 + str r3, [r2, #0x50c] + ldr r3, =0x00160002 + str r3, [r2, #0x508] + ldr r3, =0x00000000 + str r3, [r2, #0x510] + ldr r3, =0x00000001 + str r3, [r2, #0x514] + ldr r3, =0x00000001 + str r3, [r2, #0x500] + + ldr r3, =0x01000000 +wait1: + ldr r4, [r2, #0x500] + and r4, r3 + cmp r4, r3 + bne wait1 + + ldr r3, =0x80808019 + str r3, [r2, #0x50c] + + ldr r3, =0x00000040 +wait2: + ldr r4, [r2, #0x50c] + and r4, r3 + cmp r4, r3 + bne wait2 + + ldr r3, =0x00000001 + str r3, [r2, #0x30] + ldr r3, =0x11000020 + str r3, [r2, #0x40] + + ldr r2, =0x403f0000 + ldr r3, =0x42000000 + str r3, [r2, #0xe0] + +.endm + +.macro imx7ulp_arm2_lpddr3_setting + + imx7ulp_ddr_freq_decrease + + /* Enable MMDC PCC clock */ + ldr r2, =0x40b30000 + ldr r3, =0x40000000 + str r3, [r2, #0xac] + + /* Configure DDR pad */ + ldr r0, =0x40ad0000 + ldr r1, =0x00040000 + str r1, [r0, #0x128] + ldr r1, =0x0 + str r1, [r0, #0xf8] + ldr r1, =0x00000180 + str r1, [r0, #0xd8] + ldr r1, =0x00000180 + str r1, [r0, #0x108] + ldr r1, =0x00000180 + str r1, [r0, #0x104] + ldr r1, =0x00010000 + str r1, [r0, #0x124] + ldr r1, =0x0000018C + str r1, [r0, #0x80] + ldr r1, =0x0000018C + str r1, [r0, #0x84] + ldr r1, =0x0000018C + str r1, [r0, #0x88] + ldr r1, =0x0000018C + str r1, [r0, #0x8c] + + ldr r1, =0x00010000 + str r1, [r0, #0x120] + ldr r1, =0x00000180 + str r1, [r0, #0x10c] + ldr r1, =0x00000180 + str r1, [r0, #0x110] + ldr r1, =0x00000180 + str r1, [r0, #0x114] + ldr r1, =0x00000180 + str r1, [r0, #0x118] + ldr r1, =0x00000180 + str r1, [r0, #0x90] + ldr r1, =0x00000180 + str r1, [r0, #0x94] + ldr r1, =0x00000180 + str r1, [r0, #0x98] + ldr r1, =0x00000180 + str r1, [r0, #0x9c] + ldr r1, =0x00040000 + str r1, [r0, #0xe0] + ldr r1, =0x00040000 + str r1, [r0, #0xe4] + + ldr r0, =0x40ab0000 + ldr r1, =0x00008000 + str r1, [r0, #0x1c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x0D3900A0 + str r1, [r0, #0x85c] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x39373939 + str r1, [r0, #0x848] + ldr r1, =0x2F313D36 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81c] + ldr r1, =0x33333333 + str r1, [r0, #0x820] + ldr r1, =0x33333333 + str r1, [r0, #0x824] + ldr r1, =0x33333333 + str r1, [r0, #0x828] + + ldr r1, =0x24922492 + str r1, [r0, #0x8c0] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x424642F3 + str r1, [r0, #0xc] + ldr r1, =0x00100A22 + str r1, [r0, #0x10] + ldr r1, =0x00120556 + str r1, [r0, #0x38] + ldr r1, =0x00C700DA + str r1, [r0, #0x14] + ldr r1, =0x00211718 + str r1, [r0, #0x18] + + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x2c] + ldr r1, =0x009F0E10 + str r1, [r0, #0x30] + ldr r1, =0x0000004F + str r1, [r0, #0x40] + ldr r1, =0x84190000 + str r1, [r0, #0x0] + + ldr r1, =0x00008010 + str r1, [r0, #0x1c] + ldr r1, =0x003F8030 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x1c] + ldr r1, =0x04028030 + str r1, [r0, #0x1c] + ldr r1, =0x83018030 + str r1, [r0, #0x1c] + ldr r1, =0x01038030 + str r1, [r0, #0x1c] + + ldr r1, =0x20000000 + str r1, [r0, #0x83c] + + ldr r1, =0x00001800 + str r1, [r0, #0x20] + ldr r1, =0xA1310003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x1c] + +.endm + +.macro imx7ulp_arm2_lpddr2_setting + + imx7ulp_ddr_freq_decrease + + /* Enable MMDC PCC clock */ + ldr r2, =0x40b30000 + ldr r3, =0x40000000 + str r3, [r2, #0xac] + + /* Configure DDR pad */ + ldr r0, =0x40ad0000 + ldr r1, =0x00040000 + str r1, [r0, #0x128] + ldr r1, =0x0 + str r1, [r0, #0xf8] + ldr r1, =0x0000018C + str r1, [r0, #0xd8] + ldr r1, =0x00000180 + str r1, [r0, #0x108] + ldr r1, =0x00000180 + str r1, [r0, #0x104] + ldr r1, =0x00010000 + str r1, [r0, #0x124] + ldr r1, =0x0000018C + str r1, [r0, #0x80] + ldr r1, =0x0000018C + str r1, [r0, #0x84] + ldr r1, =0x0000018C + str r1, [r0, #0x88] + ldr r1, =0x0000018C + str r1, [r0, #0x8c] + + ldr r1, =0x00010000 + str r1, [r0, #0x120] + ldr r1, =0x00000180 + str r1, [r0, #0x10c] + ldr r1, =0x00000180 + str r1, [r0, #0x110] + ldr r1, =0x00000180 + str r1, [r0, #0x114] + ldr r1, =0x00000180 + str r1, [r0, #0x118] + ldr r1, =0x00000180 + str r1, [r0, #0x90] + ldr r1, =0x00000180 + str r1, [r0, #0x94] + ldr r1, =0x00000180 + str r1, [r0, #0x98] + ldr r1, =0x00000180 + str r1, [r0, #0x9c] + ldr r1, =0x00040000 + str r1, [r0, #0xe0] + ldr r1, =0x00040000 + str r1, [r0, #0xe4] + + ldr r0, =0x40ab0000 + ldr r1, =0x00008000 + str r1, [r0, #0x1c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x0D3900A0 + str r1, [r0, #0x85c] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x40404040 + str r1, [r0, #0x848] + ldr r1, =0x40404040 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81c] + ldr r1, =0x33333333 + str r1, [r0, #0x820] + ldr r1, =0x33333333 + str r1, [r0, #0x824] + ldr r1, =0x33333333 + str r1, [r0, #0x828] + + ldr r1, =0x24922492 + str r1, [r0, #0x8c0] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x292C42F3 + str r1, [r0, #0xc] + ldr r1, =0x00100A22 + str r1, [r0, #0x10] + ldr r1, =0x00120556 + str r1, [r0, #0x38] + ldr r1, =0x00C700DB + str r1, [r0, #0x14] + ldr r1, =0x00211708 + str r1, [r0, #0x18] + + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x2c] + ldr r1, =0x009F0E10 + str r1, [r0, #0x30] + ldr r1, =0x0000003F + str r1, [r0, #0x40] + ldr r1, =0xC3110000 + str r1, [r0, #0x0] + + ldr r1, =0x00008010 + str r1, [r0, #0x1c] + ldr r1, =0x00008018 + str r1, [r0, #0x1c] + ldr r1, =0x003F8030 + str r1, [r0, #0x1c] + ldr r1, =0x003F8038 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x1c] + ldr r1, =0x04028030 + str r1, [r0, #0x1c] + ldr r1, =0x04028038 + str r1, [r0, #0x1c] + ldr r1, =0x82018030 + str r1, [r0, #0x1c] + ldr r1, =0x82018038 + str r1, [r0, #0x1c] + ldr r1, =0x01038030 + str r1, [r0, #0x1c] + ldr r1, =0x01038038 + str r1, [r0, #0x1c] + + ldr r1, =0x20000000 + str r1, [r0, #0x83c] + + ldr r1, =0x00001800 + str r1, [r0, #0x20] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x1c] + +.endm + + +.macro imx7ulp_clock_gating +.endm + +.macro imx7ulp_qos_setting +.endm + +.macro imx7ulp_ddr_setting +#if defined (CONFIG_TARGET_MX7ULP_10X10_ARM2) + imx7ulp_arm2_lpddr2_setting +#else + imx7ulp_arm2_lpddr3_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg index e4e4cb3b217..c1328da65f1 100644 --- a/board/freescale/mx7ulp_evk/imximage.cfg +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -46,12 +46,12 @@ DATA 4 0x403f00dc 0x00000000 DATA 4 0x403e0040 0x01000020 DATA 4 0x403e0500 0x01000000 DATA 4 0x403e050c 0x80808080 -DATA 4 0x403e0508 0x00140000 -DATA 4 0x403E0510 0x00000004 -DATA 4 0x403E0514 0x00000002 +DATA 4 0x403e0508 0x00160002 +DATA 4 0x403E0510 0x00000001 +DATA 4 0x403E0514 0x00000014 DATA 4 0x403e0500 0x00000001 CHECK_BITS_SET 4 0x403e0500 0x01000000 -DATA 4 0x403e050c 0x8080801E +DATA 4 0x403e050c 0x8080801B CHECK_BITS_SET 4 0x403e050c 0x00000040 DATA 4 0x403E0030 0x00000001 DATA 4 0x403e0040 0x11000020 @@ -95,11 +95,6 @@ DATA 4 0x40AB0820 0x33333333 DATA 4 0x40AB0824 0x33333333 DATA 4 0x40AB0828 0x33333333 -DATA 4 0x40AB082C 0xf3333333 -DATA 4 0x40AB0830 0xf3333333 -DATA 4 0x40AB0834 0xf3333333 -DATA 4 0x40AB0838 0xf3333333 - DATA 4 0x40AB08C0 0x24922492 DATA 4 0x40AB08B8 0x00000800 @@ -114,8 +109,8 @@ DATA 4 0x40AB0030 0x009F0E10 DATA 4 0x40AB0040 0x0000003F DATA 4 0x40AB0000 0xC3190000 -DATA 4 0x40AB001C 0x00008050 -DATA 4 0x40AB001C 0x00008058 +DATA 4 0x40AB001C 0x00008010 +DATA 4 0x40AB001C 0x00008018 DATA 4 0x40AB001C 0x003F8030 DATA 4 0x40AB001C 0x003F8038 DATA 4 0x40AB001C 0xFF0A8030 diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c index 361871525ef..13676328322 100644 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -9,10 +9,29 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_FSL_FASTBOOT +#include +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_UP) +#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE) +#define OTG_ID_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE) + +#define MIPI_GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE) int dram_init(void) { @@ -32,6 +51,40 @@ static void setup_iomux_uart(void) ARRAY_SIZE(lpuart4_pads)); } +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +static iomux_cfg_t const quadspi_pads[] = { + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; +#endif + +int board_qspi_init(void) +{ + u32 val; +#ifndef CONFIG_DM_SPI + mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); +#endif + + /* enable clock */ + val = readl(PCC1_RBASE + 0x94); + + if (!(val & 0x20000000)) { + writel(0x03000003, (PCC1_RBASE + 0x94)); + writel(0x43000003, (PCC1_RBASE + 0x94)); + } + + /* Enable QSPI as a wakeup source on B0 */ + if (soc_rev() >= CHIP_REV_2_0) + setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL); + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -39,10 +92,161 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_VIDEO_MXS + +#define MIPI_RESET_GPIO IMX_GPIO_NR(3, 19) +#define LED_PWM_EN_GPIO IMX_GPIO_NR(6, 2) + +static iomux_cfg_t const mipi_reset_pad[] = { + MX7ULP_PAD_PTC19__PTC19 | MUX_PAD_CTRL(MIPI_GPIO_PAD_CTRL), +}; + +static iomux_cfg_t const led_pwm_en_pad[] = { + MX7ULP_PAD_PTF2__PTF2 | MUX_PAD_CTRL(MIPI_GPIO_PAD_CTRL), +}; + +struct mipi_dsi_client_dev hx8363_dev = { + .channel = 0, + .lanes = 2, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE, +}; + +struct mipi_dsi_client_dev rm68200_dev = { + .channel = 0, + .lanes = 2, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE, +}; + +int board_mipi_panel_reset(void) +{ + gpio_direction_output(MIPI_RESET_GPIO, 0); + udelay(1000); + gpio_direction_output(MIPI_RESET_GPIO, 1); + return 0; +} + +int board_mipi_panel_shutdown(void) +{ + gpio_direction_output(MIPI_RESET_GPIO, 0); + gpio_direction_output(LED_PWM_EN_GPIO, 0); + return 0; +} + +void setup_mipi_reset(void) +{ + mx7ulp_iomux_setup_multiple_pads(mipi_reset_pad, ARRAY_SIZE(mipi_reset_pad)); + gpio_request(MIPI_RESET_GPIO, "mipi_panel_reset"); +} + +void do_enable_mipi_dsi(struct display_info_t const *dev) +{ + setup_mipi_reset(); + + /* Enable backlight */ + mx7ulp_iomux_setup_multiple_pads(led_pwm_en_pad, ARRAY_SIZE(led_pwm_en_pad)); + gpio_request(LED_PWM_EN_GPIO, "led_pwm_en"); + gpio_direction_output(LED_PWM_EN_GPIO, 1); + + /* Setup DSI host driver */ + mipi_dsi_northwest_setup(DSI_RBASE, SIM0_RBASE); + + if (!strcmp(dev->mode.name, "HX8363_WVGA")) { + /* Init hx8363 driver, must after dsi host driver setup */ + hx8363_init(); + hx8363_dev.name = dev->mode.name; + imx_mipi_dsi_bridge_attach(&hx8363_dev); /* attach hx8363 device */ + } else { + rm68200_init(); + rm68200_dev.name = dev->mode.name; + imx_mipi_dsi_bridge_attach(&rm68200_dev); + } + +} + +struct display_info_t const displays[] = {{ + .bus = LCDIF_RBASE, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_mipi_dsi, + .mode = { + .name = "RM68200_WXGA", + .xres = 720, + .yres = 1280, + .pixclock = 16040, + .left_margin = 32, + .right_margin = 32, + .upper_margin = 14, + .lower_margin = 16, + .hsync_len = 8, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = LCDIF_RBASE, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_mipi_dsi, + .mode = { + .name = "HX8363_WVGA", + .xres = 480, + .yres = 854, + .pixclock = 41042, + .left_margin = 40, + .right_margin = 60, + .upper_margin = 3, + .lower_margin = 3, + .hsync_len = 8, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + return 0; } + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + /* TODO: uboot can get the key event from M4 core*/ + return 0; +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S index 9eab36520a5..62173b2e1b0 100644 --- a/board/freescale/mx7ulp_evk/plugin.S +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -16,13 +17,14 @@ str r3, [r2, #0x40] ldr r3, =0x01000000 str r3, [r2, #0x500] + ldr r3, =0x80808080 str r3, [r2, #0x50c] - ldr r3, =0x00140000 + ldr r3, =0x00160002 str r3, [r2, #0x508] - ldr r3, =0x00000004 + ldr r3, =0x00000001 str r3, [r2, #0x510] - ldr r3, =0x00000002 + ldr r3, =0x00000014 str r3, [r2, #0x514] ldr r3, =0x00000001 str r3, [r2, #0x500] @@ -34,7 +36,7 @@ wait1: cmp r4, r3 bne wait1 - ldr r3, =0x8080801E + ldr r3, =0x8080801B str r3, [r2, #0x50c] ldr r3, =0x00000040 @@ -133,15 +135,6 @@ wait2: ldr r1, =0x33333333 str r1, [r0, #0x828] - ldr r1, =0xf3333333 - str r1, [r0, #0x82c] - ldr r1, =0xf3333333 - str r1, [r0, #0x830] - ldr r1, =0xf3333333 - str r1, [r0, #0x834] - ldr r1, =0xf3333333 - str r1, [r0, #0x838] - ldr r1, =0x24922492 str r1, [r0, #0x8c0] ldr r1, =0x00000800 @@ -169,9 +162,9 @@ wait2: ldr r1, =0xC3190000 str r1, [r0, #0x0] - ldr r1, =0x00008050 + ldr r1, =0x00008010 str r1, [r0, #0x1c] - ldr r1, =0x00008058 + ldr r1, =0x00008018 str r1, [r0, #0x1c] ldr r1, =0x003F8030 str r1, [r0, #0x1c] diff --git a/board/freescale/pico-imx7d/Kconfig b/board/freescale/pico-imx7d/Kconfig new file mode 100644 index 00000000000..a581f29d905 --- /dev/null +++ b/board/freescale/pico-imx7d/Kconfig @@ -0,0 +1,19 @@ +if TARGET_PICO_IMX7D + +config SYS_BOARD + default "pico-imx7d" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx7" + +config SYS_CONFIG_NAME + default "pico-imx7d" + +config USE_STDINT + bool "Whether to use stdint" + default n + +endif diff --git a/board/technexion/pico-imx6dl/Kconfig b/board/technexion/pico-imx6dl/Kconfig new file mode 100644 index 00000000000..8df904c0609 --- /dev/null +++ b/board/technexion/pico-imx6dl/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PICO_IMX6DL + +config SYS_BOARD + default "pico-imx6dl" + +config SYS_VENDOR + default "technexion" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "pico-imx6dl" + +endif diff --git a/board/technexion/pico-imx6dl/MAINTAINERS b/board/technexion/pico-imx6dl/MAINTAINERS new file mode 100644 index 00000000000..5c03e173c4a --- /dev/null +++ b/board/technexion/pico-imx6dl/MAINTAINERS @@ -0,0 +1,6 @@ +Technexion PICO-IMX6 board +M: Richard Hu +S: Maintained +F: board/pico-imx6dl/ +F: include/configs/pico-imx6dl.h +F: configs/pico-imx6dl_defconfig diff --git a/board/technexion/pico-imx6dl/Makefile b/board/technexion/pico-imx6dl/Makefile new file mode 100644 index 00000000000..93ba9d3ba21 --- /dev/null +++ b/board/technexion/pico-imx6dl/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2015 Technexion Ltd. +# (C) Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pico-imx6dl.o diff --git a/board/technexion/pico-imx6dl/pico-imx6dl.c b/board/technexion/pico-imx6dl/pico-imx6dl.c new file mode 100644 index 00000000000..05e0d3f00a1 --- /dev/null +++ b/board/technexion/pico-imx6dl/pico-imx6dl.c @@ -0,0 +1,639 @@ +/* + * Copyright (C) 2015 Technexion Ltd. + * Copyright 2017 NXP + * + * Author: Richard Hu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define BASEBOARD_USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define USDHC1_CD_GPIO IMX_GPIO_NR(3, 9) +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 2) +#define ETH_PHY_RESET IMX_GPIO_NR(1, 26) +#define WL_REG_ON IMX_GPIO_NR(1, 7) +#define BT_NRST IMX_GPIO_NR(7, 12) +#define LVDS0_EN IMX_GPIO_NR(2, 8) +#define LVDS0_BL_EN IMX_GPIO_NR(2, 9) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)), + /* Carrier MicroSD Card Detect */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + /* SOM MicroSD Card Detect */ + IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const lvds_pads[] = { + /* lvds */ + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +static bool cpu_is_pop(void) +{ + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + u32 ddr_map; + + /* BOOT_CFG3[4] and BOOT_CFG3[5] */ + ddr_map = (soc_sbmr >> 20) & 0x3; + + if (ddr_map == 0x2) + return true; + else + return false; +} + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + { USDHC3_BASE_ADDR, 0, 8 }, + {USDHC1_BASE_ADDR, 0, 8 }, +}; + +int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no + 2; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + u32 index = 0; + + /* + * Following map is done: + * (USDHC) (Physical Port) + * usdhc3 SOM MicroSD/MMC + * usdhc1 Carrier board MicroSD + * Always set boot USDHC as mmc0 + */ + + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_direction_input(USDHC3_CD_GPIO); + + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_direction_input(USDHC1_CD_GPIO); + + switch (get_boot_device()) { + case SD1_BOOT: + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + + case SD3_BOOT: + default: + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + } + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; +} + +int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} + +static int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe7; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +#if defined(CONFIG_VIDEO_IPUV3) +struct i2c_pads_info mx6q_i2c2_pad_info = { + .scl = { + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 13) + } +}; + +struct i2c_pads_info mx6dl_i2c2_pad_info = { + .scl = { + .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 13) + } +}; + +struct i2c_pads_info mx6q_i2c3_pad_info = { + .scl = { + .i2c_mode = MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(3, 18) + } +}; + +struct i2c_pads_info mx6dl_i2c3_pad_info = { + .scl = { + .i2c_mode = MX6DL_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6DL_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(3, 18) + } +}; +#endif + +#if defined(CONFIG_VIDEO_IPUV3) +static iomux_v3_cfg_t const ej050na_pads[] = { + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */ + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */ + IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */ + IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */ + IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), + IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), + IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), + IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), + IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), + IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), + IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), + IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), + IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), + IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), + IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), + IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), + IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), + IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), + IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), + IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), + IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), + IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), + IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18), + IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19), + IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20), + IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21), + IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22), + IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23), + IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */ +}; + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return (0 == i2c_set_bus_num(dev->bus)) && + (0 == i2c_probe(dev->addr)); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + + /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + + /* Enable Backlight - use GPIO for Brightness adjustment */ + SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09); + gpio_direction_output(IMX_GPIO_NR(2, 9), 1); + + SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08); + gpio_direction_output(IMX_GPIO_NR(2, 8), 1); +} + +static void enable_ej050na(struct display_info_t const *dev) +{ + SETUP_IOMUX_PADS(ej050na_pads); + + gpio_direction_output(IMX_GPIO_NR(2, 10), 1); + gpio_direction_output(IMX_GPIO_NR(2, 11), 1); +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "hj070na", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 1, + .addr = 0x38, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_i2c, + .enable = enable_ej050na, + .mode = { + .name = "EJ050NA", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 64, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ + SETUP_IOMUX_PADS(lvds_pads); + gpio_direction_output(LVDS0_EN, 1); + gpio_direction_output(LVDS0_BL_EN, 1); + + enable_ipu_clock(); + imx_setup_hdmi(); + + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT + | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + reg = readl(&iomux->gpr[3]); + + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK + | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + + writel(reg, &iomux->gpr[3]); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +int board_eth_init(bd_t *bis) +{ +#if 0 // fix me, cause exception + setup_iomux_enet(); + return cpu_eth_init(bis); +#endif + + return 0; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#define I2C_PMIC 1 +int board_init_pmic(void) { + struct pmic *p; + unsigned int reg; + + power_pfuze100_init(1); + + /* configure PFUZE100 PMIC */ + power_pfuze100_init(I2C_PMIC); + p = pmic_get("PFUZE100"); + if (p && !pmic_probe(p)) { + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set VGEN2 to 1.5V and enable */ + pmic_reg_read(p, PFUZE100_VGEN2VOL, ®); + reg &= ~(LDO_VOL_MASK); + reg |= (LDOA_1_50V | (1 << (LDO_EN))); + pmic_reg_write(p, PFUZE100_VGEN2VOL, reg); + } + + return 0; +} + +int board_late_init(void) +{ + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#if defined(CONFIG_VIDEO_IPUV3) + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { + //setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info); + } else { + //setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c1_pad_info); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info); + } +#endif + return 0; +} + +int checkboard(void) +{ + if (cpu_is_pop()) + printf("Board: pico-imx6-pop\n"); + else + printf("Board: pico-imx6\n"); + + printf("Available baseboard: dwarf, hobbit, nymph\n"); + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; + +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + diff --git a/board/technexion/pico-imx6dl/pico-imx6dl.cfg b/board/technexion/pico-imx6dl/pico-imx6dl.cfg new file mode 100644 index 00000000000..a5b8e8a221e --- /dev/null +++ b/board/technexion/pico-imx6dl/pico-imx6dl.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 +DATA 4 0x020e04ac 0x00000028 +DATA 4 0x020e04b0 0x00000028 +DATA 4 0x020e0464 0x00000028 +DATA 4 0x020e0490 0x00000028 +DATA 4 0x020e074c 0x00000028 +DATA 4 0x020e0494 0x00000028 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000028 +DATA 4 0x020e04b8 0x00000028 +DATA 4 0x020e076c 0x00000028 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000028 +DATA 4 0x020e04c0 0x00000028 +DATA 4 0x020e04c4 0x00000028 +DATA 4 0x020e04c8 0x00000028 +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000028 +DATA 4 0x020e0770 0x00000028 +DATA 4 0x020e0778 0x00000028 +DATA 4 0x020e077c 0x00000028 +DATA 4 0x020e0470 0x00000028 +DATA 4 0x020e0474 0x00000028 +DATA 4 0x020e0478 0x00000028 +DATA 4 0x020e047c 0x00000028 + +DATA 4 0x021b0800 0xA1390003 + +DATA 4 0x021b080c 0x003D0044 +DATA 4 0x021b0810 0x0036003A + +DATA 4 0x021b083c 0x0240023C +DATA 4 0x021b0840 0x0224022C + +DATA 4 0x021b0848 0x42464848 + +DATA 4 0x021b0850 0x3A383636 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b0004 0x0002002D +DATA 4 0x021b0008 0x00333040 +DATA 4 0x021b000c 0x676B5333 +DATA 4 0x021b0010 0xB68E8B63 +DATA 4 0x021b0014 0x01FF00DB + +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026D2 +DATA 4 0x021b0030 0x006B1023 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x84190000 + +DATA 4 0x021b001c 0x02008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 + +DATA 4 0x021b0020 0x00007800 +DATA 4 0x021b0818 0x00022227 + +DATA 4 0x021b0004 0x0002556D +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F diff --git a/board/technexion/pico-imx7d/imximage.cfg b/board/technexion/pico-imx7d/imximage.cfg index 202956a1b0f..fd6bb5345e0 100644 --- a/board/technexion/pico-imx7d/imximage.cfg +++ b/board/technexion/pico-imx7d/imximage.cfg @@ -18,7 +18,11 @@ IMAGE_VERSION 2 BOOT_FROM sd -/* Secure boot support */ +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/technexion/pico-imx7d/plugin.bin 0x00910000 +#else + #ifdef CONFIG_SECURE_BOOT CSF CONFIG_CSF_SIZE #endif @@ -96,3 +100,5 @@ DATA 4 0x30384130 0x00000002 DATA 4 0x30790018 0x0000000f CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/technexion/pico-imx7d/imximage_512mb.cfg b/board/technexion/pico-imx7d/imximage_512mb.cfg new file mode 100644 index 00000000000..df5df2de317 --- /dev/null +++ b/board/technexion/pico-imx7d/imximage_512mb.cfg @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * 2015-2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/technexion/pico-imx7d/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* IOMUXC_GPR_GPR1 */ +DATA 4 0x30340004 0x4F400005 + +/* DDR3L */ +/* assuming MEMC_FREQ_RATIO = 2 */ +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000002 +/* DDRC_MSTR */ +DATA 4 0x307a0000 0x01040001 +/* DDRC_RFSHTMG */ +DATA 4 0x307a0064 0x00400046 +/* DDRC_MP_PCTRL_0 */ +DATA 4 0x307a0490 0x00000001 +/* DDRC_INIT0 */ +DATA 4 0x307a00d0 0x00020083 +/* DDRC_INIT1 */ +DATA 4 0x307a00d4 0x00690000 +/* DDRC_INIT3 MR0/MR1 */ +DATA 4 0x307a00dc 0x09300004 +/* DDRC_INIT4 MR2/MR3 */ +DATA 4 0x307a00e0 0x04080000 +/* DDRC_INIT5 */ +DATA 4 0x307a00e4 0x00100004 +/* DDRC_RANKCTL */ +DATA 4 0x307a00f4 0x0000033f +/* DDRC_DRAMTMG0 */ +DATA 4 0x307a0100 0x09081109 +/* DDRC_DRAMTMG1 */ +DATA 4 0x307a0104 0x0007020D +/* DDRC_DRAMTMG2 */ +DATA 4 0x307a0108 0x03040407 +/* DDRC_DRAMTMG3 */ +DATA 4 0x307a010c 0x00002006 +/* DDRC_DRAMTMG4 */ +DATA 4 0x307a0110 0x04020205 +/* DDRC_DRAMTMG5 */ +DATA 4 0x307a0114 0x03030202 +/* DDRC_DRAMTMG8 */ +DATA 4 0x307a0120 0x00000803 +/* DDRC_ZQCTL0 */ +DATA 4 0x307a0180 0x00800020 +/* DDRC_DFITMG0 */ +DATA 4 0x307a0190 0x02098204 +/* DDRC_DFITMG1 */ +DATA 4 0x307a0194 0x00030303 +/* DDRC_DFIUPD0 */ +DATA 4 0x307a01a0 0x80400003 +/* DDRC_DFIUPD1 */ +DATA 4 0x307a01a4 0x00100020 +/* DDRC_DFIUPD2 */ +DATA 4 0x307a01a8 0x80100004 +/* DDRC_ADDRMAP0 */ +DATA 4 0x307a0200 0x00000015 +/* DDRC_ADDRMAP1 */ +DATA 4 0x307a0204 0x00161616 +/* DDRC_ADDRMAP4 */ +DATA 4 0x307A0210 0x00000F0F +/* DDRC_ADDRMAP5 */ +DATA 4 0x307a0214 0x04040404 +/* DDRC_ADDRMAP6 */ +DATA 4 0x307a0218 0x0F0F0404 +/* DDRC_ODTCFG */ +DATA 4 0x307a0240 0x06000604 +/* DDRC_ODTMAP */ +DATA 4 0x307a0244 0x00000001 +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000000 +/* DDR_PHY_PHY_CON0 */ +DATA 4 0x30790000 0x17420f40 +/* DDR_PHY_PHY_CON1 */ +DATA 4 0x30790004 0x10210100 +/* DDR_PHY_PHY_CON4 */ +DATA 4 0x30790010 0x00060807 +/* DDR_PHY_MDLL_CON0 */ +DATA 4 0x307900b0 0x1010007e +/* DDR_PHY_DRVDS_CON0 */ +DATA 4 0x3079009c 0x00000d6e + +/* DDR_PHY_OFFSET_RD_CON0 */ +DATA 4 0x30790020 0x08080808 +/* DDR_PHY_OFFSET_WR_CON0 */ +DATA 4 0x30790030 0x08080808 +/* DDR_PHY_CMD_SDLL_CON0 */ +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 +/* DDR_PHY_ZQ_CON1 */ +CHECK_BITS_SET 4 0x307900c4 0x1 +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 + +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000000 +/* IOMUXC_GPR_GPR8 */ +DATA 4 0x30340020 0x00000178 +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000002 +/* DDR_PHY_LP_CON0 */ +DATA 4 0x30790018 0x0000000f + +/* DDRC_STAT */ +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 67bab51dfd4..7b4d14d7767 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,21 @@ #include #include #include "../../freescale/common/pfuze.h" +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#ifdef CONFIG_VIDEO_MXS +#include +#include +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -40,8 +56,39 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1*/ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX7D_PAD_UART1_RX_DATA__I2C1_SCL | PC, + .gpio_mode = MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 | PC, + .gp = IMX_GPIO_NR(4, 0), + }, + .sda = { + .i2c_mode = MX7D_PAD_UART1_TX_DATA__I2C1_SDA | PC, + .gpio_mode = MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 | PC, + .gp = IMX_GPIO_NR(4, 1), + }, +}; + +/* I2C2 */ +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX7D_PAD_UART2_RX_DATA__I2C2_SCL | PC, + .gpio_mode = MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 | PC, + .gp = IMX_GPIO_NR(4, 2), + }, + .sda = { + .i2c_mode = MX7D_PAD_UART2_TX_DATA__I2C2_SDA | PC, + .gpio_mode = MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 | PC, + .gp = IMX_GPIO_NR(4, 3), + }, +}; + /* I2C4 for PMIC */ static struct i2c_pads_info i2c_pad_info4 = { .scl = { @@ -59,7 +106,11 @@ static struct i2c_pads_info i2c_pad_info4 = { int dram_init(void) { - gd->ram_size = PHYS_SDRAM_SIZE; +#ifdef CONFIG_IMX_TRUSTY_OS + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024) - TRUSTY_OS_RAM_SIZE; +#else + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); +#endif return 0; } @@ -103,7 +154,7 @@ int power_init_board(void) /* decrease SW1B normal voltage to 0.975V */ pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); reg &= ~0x1f; - reg |= PFUZE3000_SW1AB_SETP(975); + reg |= PFUZE3000_SW1AB_SETP(9750); pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); return 0; @@ -119,6 +170,32 @@ static iomux_v3_cfg_t const uart5_pads[] = { MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_RESET_B__SD1_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +/* SD */ +#ifdef PICO_SD +#define USDHC3_CD_GPIO IMX_GPIO_NR(6, 9) +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__GPIO6_IO9 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#else +/* EMMC */ +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14) static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -132,11 +209,131 @@ static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(LCD_PAD_CTRL), /* LCD_VDD_EN */ +}; + +static iomux_v3_cfg_t const pwm_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* LCD_BLT_CTRL */ +}; + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); + + /* Reset LCD */ + gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_direction_output(IMX_GPIO_NR(1, 11) , 1); + /* Set LCD enable to high */ + gpio_direction_output(IMX_GPIO_NR(1, 6) , 1); +} + +static struct lcd_panel_info_t const displays[] = {{ + .lcdif_base_addr = ELCDIF1_IPS_BASE_ADDR, + .depth = 24, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "EJ050NA", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = env_get("panel"); + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + i = 0; + } else { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < ARRAY_SIZE(displays)) { + ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth, + displays[i].lcdif_base_addr); + if (!ret) { + if (displays[i].enable) + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + return -EINVAL; + } + + return 0; +} +#endif #ifdef CONFIG_FEC_MXC static iomux_v3_cfg_t const fec1_pads[] = { - MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), - MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_SD2_CD_B__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_SD2_WP__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -187,10 +384,16 @@ static int setup_fec(void) int board_phy_config(struct phy_device *phydev) { + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + /*phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);*/ + unsigned short val; /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); +/* phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); @@ -198,7 +401,7 @@ int board_phy_config(struct phy_device *phydev) val &= 0xffe7; val |= 0x18; phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - +*/ /* introduce tx clock delay */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); @@ -207,46 +410,146 @@ int board_phy_config(struct phy_device *phydev) if (phydev->drv->config) phydev->drv->config(phydev); - return 0; } #endif +static iomux_v3_cfg_t const bcm4339_pads[] = { + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), //wifi reset + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), //bt reset +}; + +static iomux_v3_cfg_t const ccm_clko_pads[] = { + MX7D_PAD_GPIO1_IO03__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX7D_PAD_GPIO1_IO02__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR, 0, 4}, {USDHC3_BASE_ADDR}, }; +int board_mmc_get_env_dev(int devno) +{ + if (2 == devno) + devno--; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + if (1 == dev_no) + dev_no++; + + return dev_no; +} + int board_mmc_getcd(struct mmc *mmc) { - /* Assume uSDHC3 emmc is always present */ - return 1; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); /* Assume uSDHC1 sd is always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); /* Assume uSDHC3 emmc is always present */ + break; + } + + return ret; } int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads( - usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc2 USDHC3 (eMMC) + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); + gpio_request(USDHC3_CD_GPIO, "usdhc3_cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + return 0; } -int board_early_init_f(void) +int check_mmc_autodetect(void) { - setup_iomux_uart(); + char *autodetect_str = env_get("mmcautodetect"); -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} #endif +int board_early_init_f(void) +{ + setup_iomux_uart(); return 0; } +#define BT_RST_GPIO IMX_GPIO_NR(6, 16) +#define WIFI_RST_GPIO IMX_GPIO_NR(6, 17) + int board_init(void) { /* address of boot parameters */ @@ -256,34 +559,102 @@ int board_init(void) setup_fec(); #endif +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); +#endif + + //pico-imx7 custom initialize + imx_iomux_v3_setup_multiple_pads(bcm4339_pads, ARRAY_SIZE(bcm4339_pads)); + imx_iomux_v3_setup_multiple_pads(ccm_clko_pads, ARRAY_SIZE(ccm_clko_pads)); + + gpio_direction_output(BT_RST_GPIO, 1); + udelay(500); + gpio_direction_output(WIFI_RST_GPIO, 1); + udelay(500); + clock_set_src(IPP_DO_CLKO2,OSC_32K_CLK); + udelay(500); + clock_set_src(IPP_DO_CLKO1,OSC_24M_CLK); + return 0; } +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, + /* TODO: Nand */ + /*{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},*/ + {NULL, 0}, +}; +#endif + int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); - /* - * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), - * since we use PMIC_PWRON to reset the board. - */ - clrsetbits_le16(&wdog->wcr, 0, 0x10); - return 0; } +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + int checkboard(void) { - puts("Board: i.MX7D PICOSOM\n"); + char *mode; + if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) + mode = "secure"; + else + mode = "non-secure"; + + printf("Board: i.MX7D PICOSOM in %s mode\n", mode); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX7 +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, + ARRAY_SIZE(usb_otg1_pads)); + break; + + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } return 0; } +#endif -int board_usb_phy_mode(int port) +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) { - return USB_INIT_DEVICE; + /* No key defined for this board */ + return 0; } +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/technexion/pico-imx7d/plugin.S b/board/technexion/pico-imx7d/plugin.S new file mode 100644 index 00000000000..75033f7234f --- /dev/null +++ b/board/technexion/pico-imx7d/plugin.S @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x18181818 + str r1, [r0, #0x7c] + ldr r1, =0x18181818 + str r1, [r0, #0x80] + ldr r1, =0x40401818 + str r1, [r0, #0x84] + ldr r1, =0x00000040 + str r1, [r0, #0x88] + ldr r1, =0x40404040 + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_ddr_freq_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne FREQ_DEFAULT_533 + + /* Change to 400Mhz for TO1.1 */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x70 + ldr r2, =0x00703021 + str r2, [r0, r1] + ldr r1, =0x90 + ldr r2, =0x0 + str r2, [r0, r1] + ldr r1, =0x70 + ldr r2, =0x00603021 + str r2, [r0, r1] + + ldr r3, =0x80000000 +wait_lock: + ldr r2, [r0, r1] + and r2, r3 + cmp r2, r3 + bne wait_lock + + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x9880 + ldr r2, =0x1 + str r2, [r0, r1] + +FREQ_DEFAULT_533: +.endm + +.macro imx7d_sabresd_ddr_setting + imx7d_ddr_freq_setting + + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x01040001 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00400046 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00020001 + str r1, [r0, #0xd0] + ldr r1, =0x00690000 + str r1, [r0, #0xd4] + ldr r1, =0x09300004 + str r1, [r0, #0xdc] + ldr r1, =0x04080000 + str r1, [r0, #0xe0] + ldr r1, =0x00100004 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x09081109 + str r1, [r0, #0x100] + ldr r1, =0x0007020d + str r1, [r0, #0x104] + ldr r1, =0x03040407 + str r1, [r0, #0x108] + ldr r1, =0x00002006 + str r1, [r0, #0x10c] + ldr r1, =0x04020205 + str r1, [r0, #0x110] + ldr r1, =0x03030202 + str r1, [r0, #0x114] + ldr r1, =0x00000803 + str r1, [r0, #0x120] + ldr r1, =0x00800020 + str r1, [r0, #0x180] + ldr r1, =0x02000100 + str r1, [r0, #0x184] + ldr r1, =0x02098204 + str r1, [r0, #0x190] + ldr r1, =0x00030303 + str r1, [r0, #0x194] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00080808 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 + str r1, [r0, #0x214] + ldr r1, =0x0f070707 + str r1, [r0, #0x218] + + ldr r1, =0x06000604 + str r1, [r0, #0x240] + ldr r1, =0x00000001 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17420f40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00060807 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + imx7d_ddrphy_latency_setting + ldr r1, =0x08080808 + str r1, [r0, #0x20] + ldr r1, =0x08080808 + str r1, [r0, #0x30] + ldr r1, =0x01000010 + str r1, [r0, #0x50] + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_sabresd_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/technexion/picosom-imx6ul/Kconfig b/board/technexion/picosom-imx6ul/Kconfig new file mode 100644 index 00000000000..72980e96a69 --- /dev/null +++ b/board/technexion/picosom-imx6ul/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PICOSOM_IMX6UL + +config SYS_BOARD + default "picosom-imx6ul" + +config SYS_VENDOR + default "technexion" + +config SYS_CONFIG_NAME + default "picosom-imx6ul" + +endif diff --git a/board/technexion/picosom-imx6ul/MAINTAINERS b/board/technexion/picosom-imx6ul/MAINTAINERS new file mode 100644 index 00000000000..9ae1ff6303d --- /dev/null +++ b/board/technexion/picosom-imx6ul/MAINTAINERS @@ -0,0 +1,6 @@ +Technexion PICOSOM-IMX6UL board +M: Richard Hu +S: Maintained +F: board/picosom-imx6ul/ +F: include/configs/picosom-imx6ul.h +F: configs/picosom-imx6ul_defconfig diff --git a/board/technexion/picosom-imx6ul/Makefile b/board/technexion/picosom-imx6ul/Makefile new file mode 100644 index 00000000000..a16bea92590 --- /dev/null +++ b/board/technexion/picosom-imx6ul/Makefile @@ -0,0 +1,7 @@ +# (C) Copyright 2015 Technexion Ltd. +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := picosom-imx6ul.o diff --git a/board/technexion/picosom-imx6ul/imximage.cfg b/board/technexion/picosom-imx6ul/imximage.cfg new file mode 100644 index 00000000000..a4dc24de4ce --- /dev/null +++ b/board/technexion/picosom-imx6ul/imximage.cfg @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41490145 +DATA 4 0x021B0848 0x40404546 +DATA 4 0x021B0850 0x4040524D +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x00333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D8B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 diff --git a/board/technexion/picosom-imx6ul/picosom-imx6ul.c b/board/technexion/picosom-imx6ul/picosom-imx6ul.c new file mode 100644 index 00000000000..4b0d1221a24 --- /dev/null +++ b/board/technexion/picosom-imx6ul/picosom-imx6ul.c @@ -0,0 +1,693 @@ +/* + * Copyright (C) 2015 Technexion Ltd. + * + * Author: Richard Hu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_POWER +#include +#include +#include "../../freescale/common/pfuze.h" +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ + + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_SD_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) + + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define VERSION_DET_DDR_SIZE IMX_GPIO_NR(5, 1) + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C2 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ +#ifdef CONFIG_IMX_TRUSTY_OS + gd->ram_size = PHYS_SDRAM_SIZE - TRUSTY_OS_RAM_SIZE; +#else + gd->ram_size = PHYS_SDRAM_SIZE; +#endif + + return 0; +} + +static iomux_v3_cfg_t const uart6_pads[] = { + MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#ifndef CONFIG_SYS_USE_NAND + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#endif + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const version_detection_pads[] = { + /* dram size detection */ + MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#ifdef CONFIG_SYS_USE_NAND +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* + * config gpmi and bch clock to 100 MHz + * bch/gpmi select PLL2 PFD2 400M + * 100M = 400M / 4 + */ + clrbits_le32(&mxc_ccm->cscmr1, + MXC_CCM_CSCMR1_BCH_CLK_SEL | + MXC_CCM_CSCMR1_GPMI_CLK_SEL); + clrsetbits_le32(&mxc_ccm->cscdr1, + MXC_CCM_CSCDR1_BCH_PODF_MASK | + MXC_CCM_CSCDR1_GPMI_PODF_MASK, + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec_pads[] = { + MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define RMII_PHY_RESET IMX_GPIO_NR(1, 28) + +static void setup_iomux_fec(int fec_id) +{ + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); +} +#endif + +static void setup_iomux_version_detection(void) +{ + SETUP_IOMUX_PADS(version_detection_pads); +} +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[2] = { +#ifdef CONFIG_SYS_USE_NAND + { USDHC1_BASE_ADDR, 0, 4 }, +#else + { USDHC1_BASE_ADDR, 0, 8 }, /* 8-bit emmc */ +#endif /* CONFIG_SYS_USE_NAND */ +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: +#ifdef CONFIG_SYS_USE_NAND + ret = !gpio_get_value(USDHC1_CD_GPIO); +#else + ret = 1; +#endif + break; + } + + return ret; + +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + /* LCD_RST */ + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Reset the LCD */ + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); + + /* Set Brightness to high */ + gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); +} + +static struct display_info_t const displays[] = {{ + .lcdif_base_addr = MX6UL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "TFT43AB", + .xres = 480, + .yres = 272, + .pixclock = 108695, + .left_margin = 8, + .right_margin = 4, + .upper_margin = 2, + .lower_margin = 4, + .hsync_len = 41, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + gpio_direction_output(RMII_PHY_RESET, 0); + udelay(500); + gpio_direction_output(RMII_PHY_RESET, 1); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + if (0 == fec_id) { + /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* At default the 3v3 enables the MIC2026 for VBUS power */ +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE3000"); + ret = pmic_probe(pfuze); + if (ret) + return ret; + + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); + + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); + + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= PFUZE3000_SW1AB_SETP(12750); + pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE3000_SW1AB_SETP(11750); + + pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_SYS_USE_NAND + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +void version_detection(void) +{ + setup_iomux_version_detection(); + gpio_direction_input(VERSION_DET_DDR_SIZE); + if (gpio_get_value(VERSION_DET_DDR_SIZE)) + printf("DRAM size is 512MB \r\n"); + else + printf("DRAM size is 256MB \r\n"); +} +int checkboard(void) +{ + version_detection(); + puts("Board: PicoSOM i.mx6UL\n"); + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + /* No key defined for this board */ + return 0; +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/cmd/Kconfig b/cmd/Kconfig index 136836d1465..16748e1f8b2 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -337,6 +337,12 @@ config CMD_FITUPD Implements the 'fitupd' command, which allows to automatically store software updates present on a TFTP server in NOR Flash +config CMD_FSL_CAAM_KB + bool "Freescale i.MX CAAM command" + help + Implement the "caam" command to generate DEK blob for one block of data + or decap the DEK blob to its original data. + config CMD_THOR_DOWNLOAD bool "thor - TIZEN 'thor' download" help @@ -1297,6 +1303,8 @@ config CMD_AES config CMD_BLOB bool "Enable the 'blob' command" + depends on !MX6ULL && !MX6SLL && !MX6SL + select SECURE_BOOT if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_IMX8M help This is used with the Freescale secure boot mechanism. diff --git a/cmd/Makefile b/cmd/Makefile index 9a358e48011..295f4e944b4 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_CMD_FLASH) += flash.o obj-$(CONFIG_CMD_FPGA) += fpga.o obj-$(CONFIG_CMD_FPGAD) += fpgad.o obj-$(CONFIG_CMD_FS_GENERIC) += fs.o +obj-$(CONFIG_CMD_FSL_CAAM_KB) += cmd_fsl_caam.o obj-$(CONFIG_CMD_FUSE) += fuse.o obj-$(CONFIG_CMD_GETTIME) += gettime.o obj-$(CONFIG_CMD_GPIO) += gpio.o diff --git a/cmd/blob.c b/cmd/blob.c index bdd4cfda0b3..4bb6639a46e 100644 --- a/cmd/blob.c +++ b/cmd/blob.c @@ -11,6 +11,11 @@ #include #include #include +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ + defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8M) +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -77,6 +82,17 @@ static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) src_ptr = (uint8_t *)(uintptr_t)src_addr; dst_ptr = (uint8_t *)(uintptr_t)dst_addr; +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ + defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8M) + + hab_caam_clock_enable(1); + + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + FSL_CAAM_ORSR_JRa_OFFSET); + if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) + sec_init(); +#endif + if (enc) ret = blob_encap(km_ptr, src_ptr, dst_ptr, len); else diff --git a/cmd/booti.c b/cmd/booti.c index fff93697635..e7039b753fc 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -44,6 +44,16 @@ static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc, if (ret != 0) return 1; +#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_AVB_SUPPORT) + extern int authenticate_image( + uint32_t ddr_start, uint32_t raw_image_size); + if (authenticate_image(ld, image_size) != 0) { + printf("Authenticate Image Fail, Please check\n"); + return 1; + } + +#endif + /* Handle BOOTM_STATE_LOADOS */ if (relocated_addr != ld) { debug("Moving Image from 0x%lx to 0x%lx\n", ld, relocated_addr); diff --git a/cmd/bootm.c b/cmd/bootm.c index df0bbe19ca2..7fa0de06fc6 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -123,6 +123,69 @@ int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return do_bootm_subcommand(cmdtp, flag, argc, argv); } +#ifdef CONFIG_SECURE_BOOT + extern int authenticate_image( + uint32_t ddr_start, uint32_t raw_image_size); + +#ifdef CONFIG_IMX_OPTEE + ulong tee_addr = 0; + int ret; + ulong zi_start, zi_end; + + tee_addr = env_get_ulong("tee_addr", 16, tee_addr); + if (!tee_addr) { + printf("Not valid tee_addr, Please check\n"); + return 1; + } + + switch (genimg_get_format((const void *)tee_addr)) { + case IMAGE_FORMAT_LEGACY: + if (authenticate_image(tee_addr, + image_get_image_size((image_header_t *)tee_addr)) != 0) { + printf("Authenticate uImage Fail, Please check\n"); + return 1; + } + break; + default: + printf("Not valid image format for Authentication, Please check\n"); + return 1; + }; + + ret = bootz_setup(load_addr, &zi_start, &zi_end); + if (ret != 0) + return 1; + + if (authenticate_image(load_addr, zi_end - zi_start) != 0) { + printf("Authenticate zImage Fail, Please check\n"); + return 1; + } + +#else + + switch (genimg_get_format((const void *)load_addr)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) + case IMAGE_FORMAT_LEGACY: + if (authenticate_image(load_addr, + image_get_image_size((image_header_t *)load_addr)) != 0) { + printf("Authenticate uImage Fail, Please check\n"); + return 1; + } + break; +#endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + case IMAGE_FORMAT_ANDROID: + default: + /* Android use AVB verify. Also here we cannot get IMAGE_FORMAT_ANDROID */ + break; +#else + default: + printf("Not valid image format for Authentication, Please check\n"); + return 1; +#endif /* CONFIG_ANDROID_BOOT_IMAGE */ + } +#endif +#endif + return do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START | BOOTM_STATE_FINDOS | BOOTM_STATE_FINDOTHER | BOOTM_STATE_LOADOS | diff --git a/cmd/bootz.c b/cmd/bootz.c index ceff01bc041..7d8a77d8d9e 100644 --- a/cmd/bootz.c +++ b/cmd/bootz.c @@ -55,6 +55,14 @@ static int bootz_start(cmd_tbl_t *cmdtp, int flag, int argc, if (bootm_find_images(flag, argc, argv)) return 1; +#ifdef CONFIG_SECURE_BOOT + extern int authenticate_image( + uint32_t ddr_start, uint32_t raw_image_size); + if (authenticate_image(images->ep, zi_end - zi_start) != 0) { + printf("Authenticate zImage Fail, Please check\n"); + return 1; + } +#endif return 0; } diff --git a/cmd/cmd_fsl_caam.c b/cmd/cmd_fsl_caam.c new file mode 100644 index 00000000000..468be549e57 --- /dev/null +++ b/cmd/cmd_fsl_caam.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include + +static int do_caam(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + + int ret, i; + + if (argc < 2) + return CMD_RET_USAGE; + + if (strcmp(argv[1], "genblob") == 0) { + + if (argc != 5) + return CMD_RET_USAGE; + + void *data_addr; + void *blob_addr; + int size; + + data_addr = (void *)simple_strtoul(argv[2], NULL, 16); + blob_addr = (void *)simple_strtoul(argv[3], NULL, 16); + size = simple_strtoul(argv[4], NULL, 10); + if (size <= 48) + return CMD_RET_USAGE; + + caam_open(); + ret = caam_gen_blob((uint32_t)data_addr, (uint32_t)blob_addr, (uint32_t)size); + + if(ret != SUCCESS){ + printf("Error during blob encap operation: 0x%x\n", ret); + return 0; + } + + /* Print the generated DEK blob */ + printf("DEK blob is available at 0x%08X and equals:\n",(unsigned int)blob_addr); + for(i=0;i #include -int do_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_raw_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *ep; struct blk_desc *dev_desc = NULL; @@ -75,7 +75,7 @@ int do_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } U_BOOT_CMD( - read, 6, 0, do_read, + read, 6, 0, do_raw_read, "Load binary data from a partition", " addr blk# cnt" ); diff --git a/cmd/sata.c b/cmd/sata.c index 7817442532a..1df9674b5d2 100644 --- a/cmd/sata.c +++ b/cmd/sata.c @@ -91,8 +91,10 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc == 3) devnum = (int)simple_strtoul(argv[2], NULL, 10); - if (!strcmp(argv[1], "stop")) + if (!strcmp(argv[1], "stop")) { + sata_curr_device = -1; return sata_remove(devnum); + } if (!strcmp(argv[1], "init")) { if (sata_curr_device != -1) { @@ -101,7 +103,11 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return rc; } - return sata_probe(devnum); + rc = sata_probe(devnum); + if (rc < 0) + return CMD_RET_FAILURE; + sata_curr_device = rc; + return CMD_RET_SUCCESS; } } diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c index cfeecb7068a..ec7906ba00d 100644 --- a/cmd/usb_mass_storage.c +++ b/cmd/usb_mass_storage.c @@ -167,7 +167,7 @@ static int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, goto cleanup_ums_init; } - rc = fsg_init(ums, ums_count); + rc = fsg_init(ums, ums_count, controller_index); if (rc) { pr_err("fsg_init failed"); rc = CMD_RET_FAILURE; diff --git a/common/autoboot.c b/common/autoboot.c index 2eef7a04cc7..08a0798eeae 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -15,6 +15,10 @@ #include #include +#ifdef is_boot_from_usb +#include +#endif + DECLARE_GLOBAL_DATA_PTR; #define MAX_DELAY_STOP_STR 32 @@ -307,6 +311,21 @@ const char *bootdelay_process(void) s = env_get("bootdelay"); bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY; +#if defined(is_boot_from_usb) + if (is_boot_from_usb() && env_get("bootcmd_mfg")) { + disconnect_from_pc(); + printf("Boot from USB for mfgtools\n"); + bootdelay = 0; + set_default_env("Use default environment for \ + mfgtools\n"); + } else if (is_boot_from_usb()) { + printf("Boot from USB for uuu\n"); + env_set("bootcmd", "fastboot 0"); + } else { + printf("Normal Boot\n"); + } +#endif + #ifdef CONFIG_OF_CONTROL bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay", bootdelay); @@ -333,6 +352,13 @@ const char *bootdelay_process(void) #endif /* CONFIG_BOOTCOUNT_LIMIT */ s = env_get("bootcmd"); +#if defined(is_boot_from_usb) + if (is_boot_from_usb() && env_get("bootcmd_mfg")) { + s = env_get("bootcmd_mfg"); + printf("Run bootcmd_mfg: %s\n", s); + } +#endif + process_fdt_options(gd->fdt_blob); stored_bootdelay = bootdelay; diff --git a/common/board_f.c b/common/board_f.c index c6bc53e1bf0..cfd9de0e9fb 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -783,7 +783,9 @@ static const init_fnc_t init_sequence_f[] = { #endif env_init, /* initialize environment */ init_baud_rate, /* initialze baudrate settings */ +#ifndef CONFIG_ANDROID_AUTO_SUPPORT serial_init, /* serial communications setup */ +#endif console_init_f, /* stage 1 init of console */ display_options, /* say that we are here */ display_text_info, /* show debugging info if required */ diff --git a/common/board_r.c b/common/board_r.c index 482f5066616..9444bc17b81 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -54,6 +54,9 @@ #include #include #include +#ifdef CONFIG_FSL_FASTBOOT +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -651,6 +654,37 @@ static int initr_kbd(void) } #endif +#if defined(AVB_RPMB) && !defined(CONFIG_SPL) +extern int init_avbkey(void); +static int initr_avbkey(void) +{ + return init_avbkey(); +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +static int initr_fastboot_setup(void) +{ + fastboot_setup(); + return 0; +} + +static int initr_check_fastboot(void) +{ + fastboot_run_bootmode(); + return 0; +} +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +extern void tee_setup(void); +static int initr_tee_setup(void) +{ + tee_setup(); + return 0; +} +#endif + static int run_main_loop(void) { #ifdef CONFIG_SANDBOX @@ -823,6 +857,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_BOARD_LATE_INIT board_late_init, #endif +#ifdef CONFIG_FSL_FASTBOOT + initr_fastboot_setup, +#endif #if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI) INIT_FUNC_WATCHDOG_RESET initr_scsi, @@ -861,6 +898,15 @@ static init_fnc_t init_sequence_r[] = { #endif #ifdef CONFIG_PS2KBD initr_kbd, +#endif +#if defined(AVB_RPMB) && !defined(CONFIG_SPL) + initr_avbkey, +#endif +#ifdef CONFIG_IMX_TRUSTY_OS + initr_tee_setup, +#endif +#ifdef CONFIG_FSL_FASTBOOT + initr_check_fastboot, #endif run_main_loop, }; diff --git a/common/image-android.c b/common/image-android.c index 5ad3a1fa38a..145e87e72fe 100644 --- a/common/image-android.c +++ b/common/image-android.c @@ -1,6 +1,9 @@ /* * Copyright (c) 2011 Sebastian Andrzej Siewior * + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,6 +12,12 @@ #include #include #include +#include +#include +#include +#include +#include +#include #define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR 0x10008000 @@ -51,6 +60,7 @@ static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr) int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, ulong *os_data, ulong *os_len) { + extern boot_metric metrics; u32 kernel_addr = android_image_get_kernel_addr(hdr); /* @@ -66,31 +76,188 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, printf("Kernel load addr 0x%08x size %u KiB\n", kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024)); - int len = 0; - if (*hdr->cmdline) { - printf("Kernel command line: %s\n", hdr->cmdline); - len += strlen(hdr->cmdline); + char newbootargs[512] = {0}; + char commandline[2048] = {0}; + int offset; + char *bootargs = env_get("bootargs"); + + if (bootargs) { + if (strlen(bootargs) + 1 > sizeof(commandline)) { + printf("bootargs is too long!\n"); + return -1; + } + else + strncpy(commandline, bootargs, sizeof(commandline) - 1); + } else { + offset = fdt_path_offset(gd->fdt_blob, "/chosen"); + if (offset > 0) { + bootargs = (char *)fdt_getprop(gd->fdt_blob, offset, + "bootargs", NULL); + if (bootargs) + sprintf(commandline, "%s ", bootargs); + } + + if (*hdr->cmdline) { + if (strlen(hdr->cmdline) + 1 > + sizeof(commandline) - strlen(commandline)) { + printf("cmdline in bootimg is too long!\n"); + return -1; + } + else + strncat(commandline, hdr->cmdline, sizeof(commandline) - strlen(commandline)); + } } - char *bootargs = env_get("bootargs"); - if (bootargs) - len += strlen(bootargs); + /* Add 'bootargs_ram_capacity' to hold the parameters based on different ram capacity */ + char *bootargs_ram_capacity = env_get("bootargs_ram_capacity"); + if (bootargs_ram_capacity) { + strncat(commandline, " ", sizeof(commandline) - strlen(commandline)); + strncat(commandline, bootargs_ram_capacity, + sizeof(commandline) - strlen(commandline)); + } + +#ifdef CONFIG_SERIAL_TAG + struct tag_serialnr serialnr; + get_board_serial(&serialnr); + + sprintf(newbootargs, + " androidboot.serialno=%08x%08x", + serialnr.high, + serialnr.low); + strncat(commandline, newbootargs, sizeof(commandline) - strlen(commandline)); - char *newbootargs = malloc(len + 2); - if (!newbootargs) { - puts("Error: malloc in android_image_get_kernel failed!\n"); - return -ENOMEM; + char bd_addr[16]={0}; + sprintf(bd_addr, + "%08x%08x", + serialnr.high, + serialnr.low); + sprintf(newbootargs, + " androidboot.btmacaddr=%c%c:%c%c:%c%c:%c%c:%c%c:%c%c", + bd_addr[0],bd_addr[1],bd_addr[2],bd_addr[3],bd_addr[4],bd_addr[5], + bd_addr[6],bd_addr[7],bd_addr[8],bd_addr[9],bd_addr[10],bd_addr[11]); + strncat(commandline, newbootargs, sizeof(commandline) - strlen(commandline)); +#endif + + /* append soc type into bootargs */ + char *soc_type = env_get("soc_type"); + if (soc_type) { + sprintf(newbootargs, + " androidboot.soc_type=%s", + soc_type); + strncat(commandline, newbootargs, sizeof(commandline) - strlen(commandline)); } - *newbootargs = '\0'; - if (bootargs) { - strcpy(newbootargs, bootargs); - strcat(newbootargs, " "); + char *storage_type = env_get("storage_type"); + if (storage_type) { + sprintf(newbootargs, + " androidboot.storage_type=%s", + storage_type); + strncat(commandline, newbootargs, sizeof(commandline) - strlen(commandline)); + } else { + int bootdev = get_boot_device(); + if (bootdev == SD1_BOOT || bootdev == SD2_BOOT || + bootdev == SD3_BOOT || bootdev == SD4_BOOT) { + sprintf(newbootargs, + " androidboot.storage_type=sd"); + } else if (bootdev == MMC1_BOOT || bootdev == MMC2_BOOT || + bootdev == MMC3_BOOT || bootdev == MMC4_BOOT) { + sprintf(newbootargs, + " androidboot.storage_type=emmc"); + } else if (bootdev == NAND_BOOT) { + sprintf(newbootargs, + " androidboot.storage_type=nand"); + } else + printf("boot device type is incorrect.\n"); + strncat(commandline, newbootargs, sizeof(commandline) - strlen(commandline)); + if (bootloader_gpt_overlay()) { + sprintf(newbootargs, " gpt"); + strncat(commandline, newbootargs, sizeof(commandline) - strlen(commandline)); + } + } + + /* boot metric variables */ + metrics.ble_1 = get_timer(0); + sprintf(newbootargs, + " androidboot.boottime=1BLL:%d,1BLE:%d,KL:%d,KD:%d,AVB:%d,ODT:%d,SW:%d", + metrics.bll_1, metrics.ble_1, metrics.kl, metrics.kd, metrics.avb, + metrics.odt, metrics.sw); + strncat(commandline, newbootargs, sizeof(commandline) - strlen(commandline)); + +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ + defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8M) + char cause[18]; + + memset(cause, '\0', sizeof(cause)); + get_reboot_reason(cause); + if (strstr(cause, "POR")) + sprintf(newbootargs," androidboot.bootreason=cold,powerkey"); + else if (strstr(cause, "WDOG") || strstr(cause, "WDG")) + sprintf(newbootargs," androidboot.bootreason=watchdog"); + else + sprintf(newbootargs," androidboot.bootreason=reboot"); +#else + sprintf(newbootargs," androidboot.bootreason=reboot"); +#endif + strncat(commandline, newbootargs, sizeof(commandline) - strlen(commandline)); + +#ifdef CONFIG_AVB_SUPPORT + /* secondary cmdline added by avb */ + char *bootargs_sec = env_get("bootargs_sec"); + if (bootargs_sec) { + strncat(commandline, " ", sizeof(commandline) - strlen(commandline)); + strncat(commandline, bootargs_sec, sizeof(commandline) - strlen(commandline)); } - if (*hdr->cmdline) - strcat(newbootargs, hdr->cmdline); +#endif +#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT + /* Normal boot: + * cmdline to bypass ramdisk in boot.img, but use the system.img + * Recovery boot: + * Use the ramdisk in boot.img + */ + char *bootargs_3rd = env_get("bootargs_3rd"); + if (bootargs_3rd) { + strncat(commandline, " ", sizeof(commandline) - strlen(commandline)); + strncat(commandline, bootargs_3rd, sizeof(commandline) - strlen(commandline)); + } +#endif - env_set("bootargs", newbootargs); + /* VTS need this commandline to verify fdt overlay. Pass the + * dtb index as "0" here since we only have one dtb in dtbo + * partition and haven't enabled the dtb overlay. + */ +#if defined(CONFIG_ANDROID_SUPPORT) || defined(CONFIG_ANDROID_AUTO_SUPPORT) + sprintf(newbootargs," androidboot.dtbo_idx=0"); + strncat(commandline, newbootargs, sizeof(commandline) - strlen(commandline)); +#endif + + char *keystore = env_get("keystore"); + if ((keystore == NULL) || strncmp(keystore, "trusty", sizeof("trusty"))) { + char *bootargs_trusty = "androidboot.keystore=software"; + strncat(commandline, " ", sizeof(commandline) - strlen(commandline)); + strncat(commandline, bootargs_trusty, sizeof(commandline) - strlen(commandline)); + } else { + char *bootargs_trusty = "androidboot.keystore=trusty"; + strncat(commandline, " ", sizeof(commandline) - strlen(commandline)); + strncat(commandline, bootargs_trusty, sizeof(commandline) - strlen(commandline)); + } + +#ifdef CONFIG_APPEND_BOOTARGS + /* Add 'append_bootargs' to hold some paramemters which need to be appended + * to bootargs */ + char *append_bootargs = env_get("append_bootargs"); + if (append_bootargs) { + if (strlen(append_bootargs) + 2 > + (sizeof(commandline) - strlen(commandline))) { + printf("The 'append_bootargs' is too long to be appended to bootargs\n"); + } else { + strncat(commandline, " ", sizeof(commandline) - strlen(commandline)); + strncat(commandline, append_bootargs, sizeof(commandline) - strlen(commandline)); + } + } +#endif + + debug("Kernel command line: %s\n", commandline); + env_set("bootargs", commandline); if (os_data) { *os_data = (ulong)hdr; @@ -202,3 +369,15 @@ void android_print_contents(const struct andr_img_hdr *hdr) printf("%scmdline: %s\n", p, hdr->cmdline); } #endif + +#define ARM64_IMAGE_MAGIC 0x644d5241 +bool image_arm64(void *images) +{ + struct header_image *ih; + + ih = (struct header_image *)images; + debug("image magic: %x\n", ih->magic); + if (ih->magic == le32_to_cpu(ARM64_IMAGE_MAGIC)) + return true; + return false; +} diff --git a/common/image-fdt.c b/common/image-fdt.c index 25103ba3b5d..5691e964f5b 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -6,6 +6,8 @@ * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -413,7 +415,34 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, debug("## No Flattened Device Tree\n"); goto no_fdt; } - } else { + } +#ifdef CONFIG_ANDROID_BOOT_IMAGE + else if (genimg_get_format((void *)images->os.start) == + IMAGE_FORMAT_ANDROID) { + ulong fdt_data, fdt_len; + android_image_get_second((void *)images->os.start, + &fdt_data, &fdt_len); + + if (fdt_len) { + fdt_blob = (char *)fdt_data; + printf(" Booting using the fdt at 0x%p\n", fdt_blob); + + if (fdt_check_header(fdt_blob) != 0) { + fdt_error("image is not a fdt"); + goto error; + } + + if (fdt_totalsize(fdt_blob) != fdt_len) { + fdt_error("fdt size != image size"); + goto error; + } + } else { + debug("## No Flattened Device Tree\n"); + goto no_fdt; + } + } +#endif + else { debug("## No Flattened Device Tree\n"); goto no_fdt; } diff --git a/common/image-sparse.c b/common/image-sparse.c index ddf5772cf82..f3806431f9d 100644 --- a/common/image-sparse.c +++ b/common/image-sparse.c @@ -59,7 +59,7 @@ void write_sparse_image( uint32_t bytes_written = 0; unsigned int chunk; unsigned int offset; - unsigned int chunk_data_sz; + uint64_t chunk_data_sz; uint32_t *fill_buf = NULL; uint32_t fill_val; sparse_header_t *sparse_header; @@ -130,7 +130,7 @@ void write_sparse_image( sizeof(chunk_header_t)); } - chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz; + chunk_data_sz = (uint64_t)sparse_header->blk_sz * (uint64_t)chunk_header->chunk_sz; blkcnt = chunk_data_sz / info->blksz; switch (chunk_header->chunk_type) { case CHUNK_TYPE_RAW: @@ -200,6 +200,7 @@ void write_sparse_image( __func__); fastboot_fail( "Request would exceed partition size!"); + free(fill_buf); return; } diff --git a/common/lcd.c b/common/lcd.c index 4b3d7dcd34b..07417ea3228 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -35,11 +35,6 @@ #define CONFIG_LCD_ALIGNMENT PAGE_SIZE #endif -#if (LCD_BPP != LCD_COLOR8) && (LCD_BPP != LCD_COLOR16) && \ - (LCD_BPP != LCD_COLOR32) -#error Unsupported LCD BPP. -#endif - DECLARE_GLOBAL_DATA_PTR; static int lcd_init(void *lcdbase); @@ -171,11 +166,14 @@ int drv_lcd_init(void) void lcd_clear(void) { - int bg_color; char *s; ulong addr; static int do_splash = 1; -#if LCD_BPP == LCD_COLOR8 +#if LCD_BPP == LCD_MONOCHROME + /* Setting the palette */ + lcd_initcolregs(); + +#elif LCD_BPP == LCD_COLOR8 /* Setting the palette */ lcd_setcolreg(CONSOLE_COLOR_BLACK, 0, 0, 0); lcd_setcolreg(CONSOLE_COLOR_RED, 0xFF, 0, 0); @@ -191,11 +189,9 @@ void lcd_clear(void) #ifndef CONFIG_SYS_WHITE_ON_BLACK lcd_setfgcolor(CONSOLE_COLOR_BLACK); lcd_setbgcolor(CONSOLE_COLOR_WHITE); - bg_color = CONSOLE_COLOR_WHITE; #else lcd_setfgcolor(CONSOLE_COLOR_WHITE); lcd_setbgcolor(CONSOLE_COLOR_BLACK); - bg_color = CONSOLE_COLOR_BLACK; #endif /* CONFIG_SYS_WHITE_ON_BLACK */ #ifdef LCD_TEST_PATTERN @@ -203,14 +199,15 @@ void lcd_clear(void) #else /* set framebuffer to background color */ #if (LCD_BPP != LCD_COLOR32) - memset((char *)lcd_base, bg_color, lcd_line_length * panel_info.vl_row); + memset((char *)lcd_base, COLOR_MASK(lcd_getbgcolor()), + lcd_line_length * panel_info.vl_row); #else u32 *ppix = lcd_base; u32 i; for (i = 0; i < (lcd_line_length * panel_info.vl_row)/NBYTES(panel_info.vl_bpix); i++) { - *ppix++ = bg_color; + *ppix++ = COLOR_MASK(lcd_getbgcolor()); } #endif #endif @@ -295,7 +292,7 @@ ulong lcd_setmem(ulong addr) ulong size; int line_length; - debug("LCD panel info: %d x %d, %d bit/pix\n", panel_info.vl_col, + debug("LCD panel info: %lu x %lu, %d bit/pix\n", panel_info.vl_col, panel_info.vl_row, NBITS(panel_info.vl_bpix)); size = lcd_get_size(&line_length); diff --git a/common/lcd_console.c b/common/lcd_console.c index bb0d7c54858..4c91def37eb 100644 --- a/common/lcd_console.c +++ b/common/lcd_console.c @@ -46,17 +46,34 @@ static void lcd_putc_xy0(struct console_t *pcons, ushort x, ushort y, char c) { int fg_color = lcd_getfgcolor(); int bg_color = lcd_getbgcolor(); - int i, row; + int row; +#if LCD_BPP == LCD_MONOCHROME + ushort off = x * (1 << LCD_BPP) % 8; +#else + int i; +#endif + fbptr_t *dst = (fbptr_t *)pcons->fbbase + y * pcons->lcdsizex + x; for (row = 0; row < VIDEO_FONT_HEIGHT; row++) { uchar bits = video_fontdata[c * VIDEO_FONT_HEIGHT + row]; +#if LCD_BPP == LCD_MONOCHROME + uchar rest = *dst & -(1 << (8 - off)); + uchar sym; + + sym = (COLOR_MASK(fg_color) & bits) | + (COLOR_MASK(bg_color) & ~bits); + *dst++ = rest | (sym >> off); + rest = sym << (8 - off); + *dst = rest | (*dst & ((1 << (8 - off)) - 1)); +#else /* LCD_BPP == LCD_COLOR8 or LCD_COLOR16 or LCD_COLOR32 */ for (i = 0; i < VIDEO_FONT_WIDTH; ++i) { *dst++ = (bits & 0x80) ? fg_color : bg_color; bits <<= 1; } +#endif dst += (pcons->lcdsizex - VIDEO_FONT_WIDTH); } } @@ -114,7 +131,7 @@ static inline void console_newline(void) for (i = 0; i < cons.rows-rows; i++) cons.fp_console_moverow(&cons, i, i+rows); for (i = 0; i < rows; i++) - cons.fp_console_setrow(&cons, cons.rows-i-1, bg_color); + cons.fp_console_setrow(&cons, cons.rows-i-1, COLOR_MASK(bg_color)); cons.curr_row -= rows; } lcd_sync(); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 9609fceea59..ab6fdfc15ce 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -56,7 +56,7 @@ config SPL_BOOTROM_SUPPORT config SPL_RAW_IMAGE_SUPPORT bool "Support SPL loading and booting of RAW images" - default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT)) + default n if ((ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT)) || ARCH_IMX8 || ARCH_IMX8M) default y if !TI_SECURE_DEVICE help SPL will support loading and booting a RAW image when this option @@ -247,6 +247,7 @@ config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT default y if MACH_SUN50I || MACH_SUN50I_H5 + default y if ARCH_IMX8M help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight. @@ -723,6 +724,14 @@ config SPL_USB_SDP_SUPPORT Enable Serial Download Protocol (SDP) device support in SPL. This allows to download images into memory and execute (jump to) them using the same protocol as implemented by the i.MX family's boot ROM. + +config SPL_SDP_USB_DEV + int "SDP USB controller index" + default 0 + depends on SPL_USB_SDP_SUPPORT + help + Some boards have USB controller other than 0. Define this option + so it can be used in compiled environment. endif config SPL_WATCHDOG_SUPPORT diff --git a/common/spl/spl.c b/common/spl/spl.c index b1ce56d0d07..a45e9d5df23 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -139,6 +139,25 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) spl_image->name = "U-Boot"; } +#if defined(CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE) +void spl_set_header_raw_atf(struct spl_image_info *spl_image) +{ + ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos); + + spl_image->size = CONFIG_SYS_MONITOR_LEN; + if (u_boot_pos != BINMAN_SYM_MISSING) { + /* biman does not support separate entry addresses at present */ + spl_image->entry_point = u_boot_pos; + spl_image->load_addr = u_boot_pos; + } else { + spl_image->entry_point = CONFIG_SYS_ATF_START; + spl_image->load_addr = CONFIG_ATF_TEXT_BASE; + } + spl_image->os = IH_OS_ARM_TRUSTED_FIRMWARE; + spl_image->name = "Arm Trusted Firmware"; +} +#endif + int spl_parse_image_header(struct spl_image_info *spl_image, const struct image_header *header) { @@ -205,7 +224,11 @@ int spl_parse_image_header(struct spl_image_info *spl_image, /* Signature not found - assume u-boot.bin */ debug("mkimage signature not found - ih_magic = %x\n", header->ih_magic); +#if defined(CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE) + spl_set_header_raw_atf(spl_image); +#else spl_set_header_raw_uboot(spl_image); +#endif #else /* RAW image not supported, proceed to other boot methods. */ debug("Raw boot image support not enabled, proceeding to other boot methods\n"); @@ -430,10 +453,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2) case IH_OS_U_BOOT: debug("Jumping to U-Boot\n"); break; -#if CONFIG_IS_ENABLED(ATF) +#if CONFIG_IS_ENABLED(ATF) || defined(CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE) case IH_OS_ARM_TRUSTED_FIRMWARE: debug("Jumping to U-Boot via ARM Trusted Firmware\n"); +#if !defined(CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE) spl_invoke_atf(&spl_image); +#endif break; #endif #ifdef CONFIG_SPL_OS_BOOT diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index b705d030e77..80e784ac5cc 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -15,6 +15,27 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) #endif +__weak void board_spl_fit_post_load(ulong load_addr, size_t length) +{ + +} + +__weak ulong board_spl_fit_size_align(ulong size) +{ + return size; +} + +__weak void* board_spl_fit_buffer_addr(ulong fit_size, int bl_len) +{ + int align_len = ARCH_DMA_MINALIGN - 1; + return (void *)((CONFIG_SYS_TEXT_BASE - fit_size - bl_len - + align_len) & ~align_len); +} + +#ifdef CONFIG_DUAL_BOOTLOADER +extern int spl_fit_get_rbindex(const void *fit, int images); +#endif + /** * spl_fit_get_image_name(): By using the matching configuration subnode, * retrieve the name of an image, specified by a property name and an index @@ -141,6 +162,15 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, return (data_size + info->bl_len - 1) / info->bl_len; } +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_IMX_TRUSTY_OS) +__weak int get_tee_load(ulong *load) +{ + /* default return ok */ + return 0; +} + +#endif + /** * spl_load_fit_image(): load the image described in a certain FIT node * @info: points to information about the device to load data from @@ -190,6 +220,21 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector, if (fit_image_get_load(fit, node, &load_addr)) load_addr = image_info->load_addr; +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_IMX_TRUSTY_OS) + char *desc = NULL; + + if (fit_get_desc(fit, node, &desc)) { + printf("can't found node description!\n"); + return -ENOENT; + } else if (!strncmp(desc, "TEE firmware", + strlen("TEE firmware"))) { + if (get_tee_load(&load_addr)) { + printf("Failed to get TEE load address!\n"); + return -ENOENT; + } + } +#endif + if (!fit_image_get_data_position(fit, node, &offset)) { external_data = true; } else if (!fit_image_get_data_offset(fit, node, &offset)) { @@ -331,7 +376,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, struct spl_image_info image_info; int node = -1; int images, ret; - int base_offset, align_len = ARCH_DMA_MINALIGN - 1; + int base_offset; int index = 0; /* @@ -341,6 +386,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, */ size = fdt_totalsize(fit); size = (size + 3) & ~3; + size = board_spl_fit_size_align(size); base_offset = (size + 3) & ~3; /* @@ -360,12 +406,12 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, * For FIT with data embedded, data is loaded as part of FIT image. * For FIT with external data, data is not loaded in this step. */ - fit = (void *)((CONFIG_SYS_TEXT_BASE - size - info->bl_len - - align_len) & ~align_len); + fit = board_spl_fit_buffer_addr(size, info->bl_len); sectors = get_aligned_image_size(info, size, 0); count = info->read(info, sector, sectors, fit); - debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n", - sector, sectors, fit, count); + debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n", + sector, sectors, fit, count, size); + if (count == 0) return -EIO; @@ -376,6 +422,16 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, return -1; } +#ifdef CONFIG_DUAL_BOOTLOADER + int rbindex; + rbindex = spl_fit_get_rbindex(fit, images); + if (rbindex < 0) { + printf("Error! Can't get rollback index!\n"); + return -1; + } else + spl_image->rbindex = rbindex; +#endif + /* * Find the U-Boot image using the following search order: * - start at 'firmware' (e.g. an ARM Trusted Firmware) @@ -473,5 +529,11 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0) spl_image->entry_point = spl_image->load_addr; + spl_image->flags |= SPL_FIT_FOUND; + +#ifdef CONFIG_SECURE_BOOT + board_spl_fit_post_load((ulong)fit, size); +#endif + return 0; } diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 351f4edd41e..12ba4411a34 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -4,6 +4,8 @@ * * Aneesh V * + * Copyright 2018 NXP + * * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -18,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; -static int mmc_load_legacy(struct spl_image_info *spl_image, struct mmc *mmc, +int mmc_load_legacy(struct spl_image_info *spl_image, struct mmc *mmc, ulong sector, struct image_header *header) { u32 image_size_sectors; @@ -44,7 +46,7 @@ static int mmc_load_legacy(struct spl_image_info *spl_image, struct mmc *mmc, return 0; } -static ulong h_spl_load_read(struct spl_load_info *load, ulong sector, +ulong h_spl_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { struct mmc *mmc = load->dev; @@ -52,25 +54,40 @@ static ulong h_spl_load_read(struct spl_load_info *load, ulong sector, return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf); } +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) +/* Pre-declaration of check_rpmb_blob. */ +int check_rpmb_blob(struct mmc *mmc); +#endif + +#ifdef CONFIG_DUAL_BOOTLOADER +/* Pre-declaration of mmc_load_image_raw_sector_dual_uboot(). + */ +extern int mmc_load_image_raw_sector_dual_uboot(struct spl_image_info *spl_image, + struct mmc *mmc); +extern int mmc_load_image_parse_container_dual_uboot(struct spl_image_info *spl_image, + struct mmc *mmc); +#else static __maybe_unused int mmc_load_image_raw_sector(struct spl_image_info *spl_image, - struct mmc *mmc, unsigned long sector) + struct mmc *mmc, unsigned long sector) { - unsigned long count; - struct image_header *header; + struct image_header *header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); int ret = 0; - header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - - sizeof(struct image_header)); +#if !defined(CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE) || defined(CONFIG_SPL_LOAD_FIT) + unsigned long count = 0; /* read image header to find the image size & load address */ count = blk_dread(mmc_get_blk_desc(mmc), sector, 1, header); debug("hdr read sector %lx, count=%lu\n", sector, count); if (count == 0) { - ret = -EIO; - goto end; +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + puts("mmc_load_image_raw_sector: mmc block read error\n"); +#endif + return -1; } - +#endif if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && image_get_magic(header) == FDT_MAGIC) { struct spl_load_info load; @@ -86,7 +103,6 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, ret = mmc_load_legacy(spl_image, mmc, sector, header); } -end: if (ret) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT puts("mmc_load_image_raw_sector: mmc block read error\n"); @@ -94,9 +110,15 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, return -1; } - return 0; + /* Images loaded, now check the rpmb keyblob for Trusty OS. */ +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) + ret = check_rpmb_blob(mmc); +#endif + return ret; } +#endif /* CONFIG_DUAL_BOOTLOADER */ + static int spl_mmc_get_device_index(u32 boot_device) { switch (boot_device) { @@ -165,7 +187,7 @@ static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info); if (err) continue; - if (info.sys_ind == + if (info.sys_ind == CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) { partition = type_part; break; @@ -292,6 +314,29 @@ u32 __weak spl_boot_mode(const u32 boot_device) #endif } +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +unsigned long __weak spl_mmc_get_uboot_raw_sector(struct mmc *mmc) +{ + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; +} +#endif + +#ifdef CONFIG_PARSE_CONTAINER +int __weak mmc_load_image_parse_container(struct spl_image_info *spl_image, + struct mmc *mmc, unsigned long sector) +{ + return -ENODEV; +}; + +#ifdef CONFIG_DUAL_BOOTLOADER +int __weak mmc_load_image_parse_container_dual_bootloader(struct spl_image_info *spl_image, + struct mmc *mmc, unsigned long sector) +{ + return -ENODEV; +}; +#endif +#endif + int spl_mmc_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { @@ -321,10 +366,15 @@ int spl_mmc_load_image(struct spl_image_info *spl_image, * 1 and 2 match up to boot0 / boot1 and 7 is user data * which is the first physical partition (0). */ +#ifdef CONFIG_DUAL_BOOTLOADER + /* Bootloader is stored in eMMC user partition for dual bootloader */ + part = 0; +#else part = (mmc->part_config >> 3) & PART_ACCESS_MASK; if (part == 7) part = 0; +#endif if (CONFIG_IS_ENABLED(MMC_TINY)) err = mmc_switch_part(mmc, part); @@ -353,8 +403,23 @@ int spl_mmc_load_image(struct spl_image_info *spl_image, return err; #endif #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#ifdef CONFIG_DUAL_BOOTLOADER +#ifdef CONFIG_PARSE_CONTAINER + err = mmc_load_image_parse_container_dual_uboot(spl_image, + mmc); +#else + err = mmc_load_image_raw_sector_dual_uboot(spl_image, + mmc); +#endif +#else +#ifdef CONFIG_PARSE_CONTAINER + err = mmc_load_image_parse_container(spl_image, mmc, + spl_mmc_get_uboot_raw_sector(mmc)); +#else err = mmc_load_image_raw_sector(spl_image, mmc, - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); + spl_mmc_get_uboot_raw_sector(mmc)); +#endif +#endif if (!err) return err; #endif diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index d0759853745..91446dde5a2 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -12,16 +12,32 @@ #include #include +#ifdef CONFIG_PARSE_CONTAINER +int __weak nand_load_image_parse_container(struct spl_image_info *spl_image, + unsigned long offset) +{ + return -EINVAL; +} +#endif + +uint32_t __weak spl_nand_get_uboot_raw_page(void) +{ + return CONFIG_SYS_NAND_U_BOOT_OFFS; +} + #if defined(CONFIG_SPL_NAND_RAW_ONLY) int spl_nand_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { nand_init(); - - nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE, - (void *)CONFIG_SYS_NAND_U_BOOT_DST); + nand_spl_load_image(spl_nand_get_uboot_raw_page(), + CONFIG_SYS_NAND_U_BOOT_SIZE, + (void *)CONFIG_SYS_NAND_U_BOOT_DST); +#if defined(CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE) + spl_set_header_raw_atf(spl_image); +#else spl_set_header_raw_uboot(spl_image); +#endif nand_deselect(); return 0; @@ -61,11 +77,15 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, load.read = spl_nand_fit_read; return spl_load_simple_fit(spl_image, &load, offset, header); } else { +#ifdef CONFIG_PARSE_CONTAINER + return nand_load_image_parse_container(spl_image, offset); +#else err = spl_parse_image_header(spl_image, header); if (err) return err; return nand_spl_load_image(offset, spl_image->size, (void *)(ulong)spl_image->load_addr); +#endif } } @@ -136,7 +156,7 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, #endif #endif /* Load u-boot */ - err = spl_nand_load_element(spl_image, CONFIG_SYS_NAND_U_BOOT_OFFS, + err = spl_nand_load_element(spl_image, spl_nand_get_uboot_raw_page(), header); #ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND #if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 1ef8ac8b89b..4929963395c 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2012 Stefan Roese + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,9 +8,52 @@ #include #include +static ulong spl_nor_fit_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf) +{ + memcpy(buf, (void *)sector, count); + + return count; +} + +unsigned long __weak spl_nor_get_uboot_base(void) +{ + return CONFIG_SYS_UBOOT_BASE; +} + +#ifdef CONFIG_PARSE_CONTAINER +int __weak nor_load_image_parse_container(struct spl_image_info *spl_image, + unsigned long offset) +{ + return -EINVAL; +} +#else +static int nor_load_legacy(struct spl_image_info *spl_image) +{ + int ret; + + /* + * Load real U-Boot from its location in NOR flash to its + * defined location in SDRAM + */ + ret = spl_parse_image_header(spl_image, + (const struct image_header *)spl_nor_get_uboot_base()); + if (ret) + return ret; + + memcpy((void *)(unsigned long)spl_image->load_addr, + (void *)(spl_nor_get_uboot_base() + sizeof(struct image_header)), + spl_image->size); + + return 0; +} +#endif + static int spl_nor_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { + const struct image_header *header; + int ret; /* * Loading of the payload to SDRAM is done with skipping of @@ -19,7 +63,6 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_OS_BOOT if (!spl_start_uboot()) { - const struct image_header *header; /* * Load Linux from its location in NOR flash to its defined @@ -50,19 +93,33 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, } #endif - /* - * Load real U-Boot from its location in NOR flash to its - * defined location in SDRAM - */ - ret = spl_parse_image_header(spl_image, - (const struct image_header *)CONFIG_SYS_UBOOT_BASE); - if (ret) - return ret; + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); - memcpy((void *)(unsigned long)spl_image->load_addr, - (void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)), - spl_image->size); + memcpy((void *)header, (void *)spl_nor_get_uboot_base(), 0x40); - return 0; + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && + image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + debug("Found FIT\n"); + load.dev = NULL; + load.priv = NULL; + load.filename = NULL; + load.bl_len = 1; + load.read = spl_nor_fit_read; + ret = spl_load_simple_fit(spl_image, &load, + spl_nor_get_uboot_base(), + (void *)header); + } else { +#ifdef CONFIG_PARSE_CONTAINER + ret = nor_load_image_parse_container(spl_image, + spl_nor_get_uboot_base()); +#else + ret = nor_load_legacy(spl_image); +#endif + } + + return ret; } SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image); diff --git a/common/spl/spl_sdp.c b/common/spl/spl_sdp.c index 0c4603a3db3..d59ddc805bd 100644 --- a/common/spl/spl_sdp.c +++ b/common/spl/spl_sdp.c @@ -13,11 +13,18 @@ DECLARE_GLOBAL_DATA_PTR; +void board_sdp_cleanup(void) +{ + board_usb_cleanup(CONFIG_SPL_SDP_USB_DEV, USB_INIT_DEVICE); +} + static int spl_sdp_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { int ret; - const int controller_index = 0; + const int controller_index = CONFIG_SPL_SDP_USB_DEV; + + board_usb_init(controller_index, USB_INIT_DEVICE); g_dnl_clear_detach(); g_dnl_register("usb_dnl_sdp"); diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 42880d56b91..5551397e95b 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -51,6 +51,22 @@ static int spi_load_image_os(struct spl_image_info *spl_image, } #endif +#ifdef CONFIG_SYS_SPI_U_BOOT_OFFS +unsigned long __weak spl_spi_get_uboot_raw_sector(struct spi_flash *flash) +{ + return CONFIG_SYS_SPI_U_BOOT_OFFS; +} +#endif + +#ifdef CONFIG_PARSE_CONTAINER +int __weak spi_load_image_parse_container(struct spl_image_info *spl_image, + struct spi_flash *flash, + unsigned long offset) +{ + return -EINVAL; +} +#endif + static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { @@ -72,7 +88,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { int err = 0; - unsigned payload_offs = CONFIG_SYS_SPI_U_BOOT_OFFS; + unsigned payload_offs = 0; struct spi_flash *flash; struct image_header *header; @@ -89,6 +105,8 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, return -ENODEV; } + payload_offs = spl_spi_get_uboot_raw_sector(flash); + /* use CONFIG_SYS_TEXT_BASE as temporary storage area */ header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); @@ -125,12 +143,18 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, payload_offs, header); } else { +#ifdef CONFIG_PARSE_CONTAINER + err = spi_load_image_parse_container(spl_image, + flash, + payload_offs); +#else err = spl_parse_image_header(spl_image, header); if (err) return err; err = spi_flash_read(flash, payload_offs, spl_image->size, (void *)spl_image->load_addr); +#endif } } diff --git a/configs/imx6dlsabreautoandroid_defconfig b/configs/imx6dlsabreautoandroid_defconfig new file mode 100644 index 00000000000..0cf7b95f358 --- /dev/null +++ b/configs/imx6dlsabreautoandroid_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_NOT_UUU_BUILD=y diff --git a/configs/imx6dlsabresdandroid_defconfig b/configs/imx6dlsabresdandroid_defconfig new file mode 100644 index 00000000000..a7427da2d47 --- /dev/null +++ b/configs/imx6dlsabresdandroid_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_NOT_UUU_BUILD=y diff --git a/configs/imx6qarm2android_pop_lpddr2_revb_defconfig b/configs/imx6qarm2android_pop_lpddr2_revb_defconfig new file mode 100644 index 00000000000..ba1995ca16a --- /dev/null +++ b/configs/imx6qarm2android_pop_lpddr2_revb_defconfig @@ -0,0 +1,45 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/mt128x64mx32.cfg,MX6DQ_POP_LPDDR2,DDR_MB=512" +CONFIG_FASTBOOT=y +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-pop-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-pop-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/imx6qpsabreautoandroid_defconfig b/configs/imx6qpsabreautoandroid_defconfig new file mode 100644 index 00000000000..a9c74e5f07f --- /dev/null +++ b/configs/imx6qpsabreautoandroid_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_NOT_UUU_BUILD=y diff --git a/configs/imx6qpsabresdandroid_defconfig b/configs/imx6qpsabresdandroid_defconfig new file mode 100644 index 00000000000..e8d1e70f921 --- /dev/null +++ b/configs/imx6qpsabresdandroid_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6qp.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_NOT_UUU_BUILD=y diff --git a/configs/imx6qsabreautoandroid_defconfig b/configs/imx6qsabreautoandroid_defconfig new file mode 100644 index 00000000000..99b61fcca7c --- /dev/null +++ b/configs/imx6qsabreautoandroid_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_NOT_UUU_BUILD=y diff --git a/configs/imx6qsabresdandroid_defconfig b/configs/imx6qsabresdandroid_defconfig new file mode 100644 index 00000000000..9b412452378 --- /dev/null +++ b/configs/imx6qsabresdandroid_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_NOT_UUU_BUILD=y diff --git a/configs/imx6slevkandroid_defconfig b/configs/imx6slevkandroid_defconfig new file mode 100644 index 00000000000..f934a057999 --- /dev/null +++ b/configs/imx6slevkandroid_defconfig @@ -0,0 +1,54 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLEVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,ANDROID_SUPPORT" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_ETH=y diff --git a/configs/imx6solosabreautoandroid_defconfig b/configs/imx6solosabreautoandroid_defconfig new file mode 100644 index 00000000000..2cf39984351 --- /dev/null +++ b/configs/imx6solosabreautoandroid_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SOLOSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6solo.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_ENV_IS_IN_MMC=y diff --git a/configs/imx6solosabresdandroid_defconfig b/configs/imx6solosabresdandroid_defconfig new file mode 100644 index 00000000000..f7e3c4749b2 --- /dev/null +++ b/configs/imx6solosabresdandroid_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SOLOSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_ENV_IS_IN_MMC=y diff --git a/configs/imx6sxsabreautoandroid_defconfig b/configs/imx6sxsabreautoandroid_defconfig new file mode 100644 index 00000000000..7dba7b01032 --- /dev/null +++ b/configs/imx6sxsabreautoandroid_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SXSABREAUTO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y + +CONFIG_IMX_BOOTAUX=y diff --git a/configs/imx6sxsabresdandroid_defconfig b/configs/imx6sxsabresdandroid_defconfig new file mode 100644 index 00000000000..7b06bfefbaa --- /dev/null +++ b/configs/imx6sxsabresdandroid_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_NXP_BOARD_REVISION=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHYLIB=y +CONFIG_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y + +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_NOT_UUU_BUILD=y diff --git a/configs/imx6ul_14x14_evk_android_defconfig b/configs/imx6ul_14x14_evk_android_defconfig new file mode 100644 index 00000000000..2c3b24cf1c5 --- /dev/null +++ b/configs/imx6ul_14x14_evk_android_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_DM_ETH=y diff --git a/configs/imx6ul_14x14_evk_brillo_defconfig b/configs/imx6ul_14x14_evk_brillo_defconfig new file mode 100644 index 00000000000..6b4d9928f17 --- /dev/null +++ b/configs/imx6ul_14x14_evk_brillo_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_DM_ETH=y diff --git a/configs/imx7dsabresdandroid_defconfig b/configs/imx7dsabresdandroid_defconfig new file mode 100644 index 00000000000..3087751112e --- /dev/null +++ b/configs/imx7dsabresdandroid_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_NOT_UUU_BUILD=y diff --git a/configs/imx7dsabresdbrillo_defconfig b/configs/imx7dsabresdbrillo_defconfig new file mode 100644 index 00000000000..b05b747458c --- /dev/null +++ b/configs/imx7dsabresdbrillo_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOOTDELAY=0 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/imx7ulp_evk_android_defconfig b/configs/imx7ulp_evk_android_defconfig new file mode 100644 index 00000000000..4e43ebcaadc --- /dev/null +++ b/configs/imx7ulp_evk_android_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_VIDEO=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_IMX_NORTHWEST_MIPI_DSI=y + +CONFIG_NOT_UUU_BUILD=y diff --git a/configs/imx8dx_17x17_val_defconfig b/configs/imx8dx_17x17_val_defconfig new file mode 100644 index 00000000000..1006107fb1e --- /dev/null +++ b/configs/imx8dx_17x17_val_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-17x17-val" +CONFIG_TARGET_IMX8X_17X17_VAL=y +CONFIG_DEFAULT_FDT_FILE="fsl-imx8dx-17x17-val.dtb" +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_USB_CDNS3=y +# CONFIG_USB_CDNS3_GADGET=y +# CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_EFI_PARTITION=y + +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y diff --git a/configs/imx8mm_ddr3l_val_defconfig b/configs/imx8mm_ddr3l_val_defconfig new file mode 100644 index 00000000000..6f80330978b --- /dev/null +++ b/configs/imx8mm_ddr3l_val_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MM_DDR3L_VAL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000" +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-ddr3l-val" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-ddr3l-val.dtb" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +# CONFIG_DM_PMIC=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y + +CONFIG_CMD_SF=y +CONFIG_MXC_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y \ No newline at end of file diff --git a/configs/imx8mm_ddr4_evk_android_defconfig b/configs/imx8mm_ddr4_evk_android_defconfig new file mode 100755 index 00000000000..a0f006d3847 --- /dev/null +++ b/configs/imx8mm_ddr4_evk_android_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MM_DDR4_EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000,ANDROID_SUPPORT" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-ddr4-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +# CONFIG_DM_PMIC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y + +CONFIG_NOT_UUU_BUILD=y +CONFIG_APPEND_BOOTARGS=y diff --git a/configs/imx8mm_ddr4_evk_android_uuu_defconfig b/configs/imx8mm_ddr4_evk_android_uuu_defconfig new file mode 100755 index 00000000000..63b28f077f9 --- /dev/null +++ b/configs/imx8mm_ddr4_evk_android_uuu_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MM_DDR4_EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000,ANDROID_SUPPORT" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-ddr4-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +# CONFIG_DM_PMIC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/imx8mm_ddr4_evk_defconfig b/configs/imx8mm_ddr4_evk_defconfig new file mode 100644 index 00000000000..29a8cb66eb5 --- /dev/null +++ b/configs/imx8mm_ddr4_evk_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MM_DDR4_EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-ddr4-evk" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-ddr4-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_CONTROL=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +# CONFIG_DM_PMIC=y +CONFIG_EFI_PARTITION=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_VIDEO=y +CONFIG_IMX_SEC_MIPI_DSI=y + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y diff --git a/configs/imx8mm_ddr4_evk_nand_defconfig b/configs/imx8mm_ddr4_evk_nand_defconfig new file mode 100644 index 00000000000..168afa4c3ae --- /dev/null +++ b/configs/imx8mm_ddr4_evk_nand_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MM_DDR4_EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-ddr4-evk" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-ddr4-evk.dtb" +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_CONTROL=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +# CONFIG_DM_PMIC=y +CONFIG_EFI_PARTITION=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_VIDEO=y +CONFIG_IMX_SEC_MIPI_DSI=y + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y \ No newline at end of file diff --git a/configs/imx8mm_ddr4_val_defconfig b/configs/imx8mm_ddr4_val_defconfig new file mode 100644 index 00000000000..f95cba28706 --- /dev/null +++ b/configs/imx8mm_ddr4_val_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MM_DDR4_VAL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000" +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-ddr4-val" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-ddr4-val.dtb" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +# CONFIG_DM_PMIC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 diff --git a/configs/imx8mm_evk_android_defconfig b/configs/imx8mm_evk_android_defconfig new file mode 100755 index 00000000000..316e15f7ff0 --- /dev/null +++ b/configs/imx8mm_evk_android_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000,ANDROID_SUPPORT" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +# CONFIG_DM_PMIC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y + +CONFIG_NOT_UUU_BUILD=y +CONFIG_APPEND_BOOTARGS=y diff --git a/configs/imx8mm_evk_android_trusty_defconfig b/configs/imx8mm_evk_android_trusty_defconfig new file mode 100755 index 00000000000..b18590b0c8c --- /dev/null +++ b/configs/imx8mm_evk_android_trusty_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000,ANDROID_SUPPORT" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +# CONFIG_DM_PMIC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y diff --git a/configs/imx8mm_evk_android_uuu_defconfig b/configs/imx8mm_evk_android_uuu_defconfig new file mode 100755 index 00000000000..5db4c1175d4 --- /dev/null +++ b/configs/imx8mm_evk_android_uuu_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000,ANDROID_SUPPORT" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +# CONFIG_DM_PMIC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig new file mode 100644 index 00000000000..125587560ed --- /dev/null +++ b/configs/imx8mm_evk_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_CONTROL=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +# CONFIG_DM_PMIC=y +CONFIG_EFI_PARTITION=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_VIDEO=y +CONFIG_IMX_SEC_MIPI_DSI=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig new file mode 100644 index 00000000000..8d77d9c7bdf --- /dev/null +++ b/configs/imx8mm_evk_fspi_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_qspi.cfg,SPL_TEXT_BASE=0x7E2000" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_CONTROL=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +# CONFIG_DM_PMIC=y +CONFIG_EFI_PARTITION=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_VIDEO=y +CONFIG_IMX_SEC_MIPI_DSI=y diff --git a/configs/imx8mq_aiy_android_defconfig b/configs/imx8mq_aiy_android_defconfig new file mode 100644 index 00000000000..fc59c08be62 --- /dev/null +++ b/configs/imx8mq_aiy_android_defconfig @@ -0,0 +1,80 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_AIY=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_BOOTDELAY=3 +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-aiy" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_BCB_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_CMD_UUID=y +CONFIG_LIB_RAND=y +CONFIG_AVB_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 + +CONFIG_NOT_UUU_BUILD=y +CONFIG_APPEND_BOOTARGS=y diff --git a/configs/imx8mq_aiy_android_trusty_defconfig b/configs/imx8mq_aiy_android_trusty_defconfig new file mode 100644 index 00000000000..1fe10c9c545 --- /dev/null +++ b/configs/imx8mq_aiy_android_trusty_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_AIY=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_BOOTDELAY=3 +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-aiy" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_BCB_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_CMD_UUID=y +CONFIG_LIB_RAND=y +CONFIG_AVB_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 + +CONFIG_NOT_UUU_BUILD=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_IMX_TRUSTY_OS=y diff --git a/configs/imx8mq_aiy_android_uuu_defconfig b/configs/imx8mq_aiy_android_uuu_defconfig new file mode 100644 index 00000000000..ffecd38eeb6 --- /dev/null +++ b/configs/imx8mq_aiy_android_uuu_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_AIY=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_BOOTDELAY=3 +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-aiy" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_BCB_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_CMD_UUID=y +CONFIG_LIB_RAND=y +CONFIG_AVB_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 diff --git a/configs/imx8mq_ddr3l_arm2_defconfig b/configs/imx8mq_ddr3l_arm2_defconfig new file mode 100644 index 00000000000..837df2587e9 --- /dev/null +++ b/configs/imx8mq_ddr3l_arm2_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_DDR3L_ARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mq-ddr3l-arm2.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MEMTEST=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-ddr3l-arm2" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y + +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y diff --git a/configs/imx8mq_ddr4_arm2_defconfig b/configs/imx8mq_ddr4_arm2_defconfig new file mode 100644 index 00000000000..2098f102b38 --- /dev/null +++ b/configs/imx8mq_ddr4_arm2_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_DDR4_ARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mq-ddr4-arm2.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MEMTEST=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-ddr4-arm2" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y + +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y diff --git a/configs/imx8mq_ddr4_arm2_nand_defconfig b/configs/imx8mq_ddr4_arm2_nand_defconfig new file mode 100644 index 00000000000..e7abb6ae4f3 --- /dev/null +++ b/configs/imx8mq_ddr4_arm2_nand_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_DDR4_ARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mq-ddr4-arm2.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MEMTEST=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-ddr4-arm2" +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_CMD_NAND=y +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_CMD_UBI=y + +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y diff --git a/configs/imx8mq_evk_android_defconfig b/configs/imx8mq_evk_android_defconfig new file mode 100644 index 00000000000..38705418ec1 --- /dev/null +++ b/configs/imx8mq_evk_android_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_BOOTDELAY=1 +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MEMTEST=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX8_HDMI=y +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_BCB_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_NOT_UUU_BUILD=y +CONFIG_APPEND_BOOTARGS=y diff --git a/configs/imx8mq_evk_android_uuu_defconfig b/configs/imx8mq_evk_android_uuu_defconfig new file mode 100644 index 00000000000..9bada1f0022 --- /dev/null +++ b/configs/imx8mq_evk_android_uuu_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_BOOTDELAY=1 +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MEMTEST=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX8_HDMI=y +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_BCB_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y diff --git a/configs/imx8mq_evk_androidthings_defconfig b/configs/imx8mq_evk_androidthings_defconfig new file mode 100644 index 00000000000..8af23498e70 --- /dev/null +++ b/configs/imx8mq_evk_androidthings_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_BOOTDELAY=1 +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MEMTEST=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX8_HDMI=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_BCB_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DUAL_BOOTLOADER=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig new file mode 100644 index 00000000000..372ab570942 --- /dev/null +++ b/configs/imx8mq_evk_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MEMTEST=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX8_HDMI=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y diff --git a/configs/imx8mq_phanbell_androidthings_defconfig b/configs/imx8mq_phanbell_androidthings_defconfig new file mode 100644 index 00000000000..ce1a1821850 --- /dev/null +++ b/configs/imx8mq_phanbell_androidthings_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_PHANBELL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_BOOTDELAY=3 +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-phanbell" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_BCB_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_CMD_UUID=y +CONFIG_LIB_RAND=y +CONFIG_AVB_SUPPORT=y +CONFIG_SECURE_BOOT=y diff --git a/configs/imx8mq_phanbell_androidthings_trusty_defconfig b/configs/imx8mq_phanbell_androidthings_trusty_defconfig new file mode 100644 index 00000000000..30678cb319d --- /dev/null +++ b/configs/imx8mq_phanbell_androidthings_trusty_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_PHANBELL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_AVB_SUPPORT=y +CONFIG_AVB_ATX=y +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_LOAD_FDT_FROM_PART=y +CONFIG_BOOTDELAY=3 +CONFIG_CMD_CACHE=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-phanbell" +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_CMD_UUID=y +CONFIG_LIB_RAND=y + +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FSL_FASTBOOT=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_BCB_SUPPORT=y diff --git a/configs/imx8mq_phanbell_androidthings_uuu_defconfig b/configs/imx8mq_phanbell_androidthings_uuu_defconfig new file mode 100644 index 00000000000..cb23f86e552 --- /dev/null +++ b/configs/imx8mq_phanbell_androidthings_uuu_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_PHANBELL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_BOOTDELAY=0 +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-phanbell" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_BCB_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_CMD_UUID=y +CONFIG_LIB_RAND=y +CONFIG_AVB_SUPPORT=y diff --git a/configs/imx8qm_ddr4_arm2_defconfig b/configs/imx8qm_ddr4_arm2_defconfig new file mode 100644 index 00000000000..602603587c6 --- /dev/null +++ b/configs/imx8qm_ddr4_arm2_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-ddr4-arm2" +CONFIG_TARGET_IMX8QM_DDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_ddr4_arm2_spl_defconfig b/configs/imx8qm_ddr4_arm2_spl_defconfig new file mode 100644 index 00000000000..c0a4f5dbd87 --- /dev/null +++ b/configs/imx8qm_ddr4_arm2_spl_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-ddr4-arm2" +CONFIG_TARGET_IMX8QM_DDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_SPL=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_SPL_OF_CONTROL=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_lpddr4_arm2_android_defconfig b/configs/imx8qm_lpddr4_arm2_android_defconfig new file mode 100644 index 00000000000..760f299929f --- /dev/null +++ b/configs/imx8qm_lpddr4_arm2_android_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" +CONFIG_EFI_PARTITION=y +CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_lpddr4_arm2_defconfig b/configs/imx8qm_lpddr4_arm2_defconfig new file mode 100644 index 00000000000..20c3ca2f710 --- /dev/null +++ b/configs/imx8qm_lpddr4_arm2_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2" +CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_lpddr4_arm2_fspi_defconfig b/configs/imx8qm_lpddr4_arm2_fspi_defconfig new file mode 100644 index 00000000000..418255e9357 --- /dev/null +++ b/configs/imx8qm_lpddr4_arm2_fspi_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2" +CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_QSPI_BOOT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_SPI_FLASH=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_lpddr4_arm2_spl_defconfig b/configs/imx8qm_lpddr4_arm2_spl_defconfig new file mode 100644 index 00000000000..b83f868429f --- /dev/null +++ b/configs/imx8qm_lpddr4_arm2_spl_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2" +CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_SPL=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_SPL_OF_CONTROL=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_mek_android_defconfig b/configs/imx8qm_mek_android_defconfig new file mode 100644 index 00000000000..a5816488b0e --- /dev/null +++ b/configs/imx8qm_mek_android_defconfig @@ -0,0 +1,96 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_EFI_PARTITION=y +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y + +CONFIG_NOT_UUU_BUILD=y +CONFIG_APPEND_BOOTARGS=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 diff --git a/configs/imx8qm_mek_android_uuu_defconfig b/configs/imx8qm_mek_android_uuu_defconfig new file mode 100644 index 00000000000..75a0d1fbd26 --- /dev/null +++ b/configs/imx8qm_mek_android_uuu_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_EFI_PARTITION=y +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_mek_androidauto2_trusty_defconfig b/configs/imx8qm_mek_androidauto2_trusty_defconfig new file mode 100644 index 00000000000..5e611156ad8 --- /dev/null +++ b/configs/imx8qm_mek_androidauto2_trusty_defconfig @@ -0,0 +1,126 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-auto" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_EFI_PARTITION=y +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_DM_WARN=n +CONFIG_DM_DEVICE_REMOVE=n +CONFIG_IMX_TRUSTY_OS=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=n + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y + +CONFIG_USB_GADGET=y +#CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_CMD_NET=n +CONFIG_CMD_NFS=n +CONFIG_CMD_BDI=n +CONFIG_CMD_CONSOLE=n +CONFIG_CMD_BOOTD=n +CONFIG_CMD_BOOTEFI=n +CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n +CONFIG_CMD_ELF=n +CONFIG_CMD_GO=n +CONFIG_CMD_RUN=n +CONFIG_CMD_IMI=n +CONFIG_CMD_IMLS=n +CONFIG_CMD_XIMG=n +CONFIG_CMD_EXPORTENV=n +CONFIG_CMD_IMPORTENV=n +CONFIG_CMD_EDITENV=n +CONFIG_CMD_ENV_EXISTS=n +CONFIG_CMD_CRC32=n +CONFIG_CMD_DM=n +CONFIG_CMD_LOADB=n +CONFIG_CMD_LOADS=n +CONFIG_CMD_FLASH=n +CONFIG_CMD_GPT=n +CONFIG_CMD_FPGA=n +CONFIG_CMD_ECHO=n +CONFIG_CMD_ITEST=n +CONFIG_CMD_SOURCE=n +CONFIG_CMD_SETEXPR=n +CONFIG_CMD_MISC=n +CONFIG_CMD_UNZIP=n +CONFIG_CMD_LZMADEC=n +CONFIG_CMD_SAVEENV=n + +CONFIG_DISPLAY_CPUINFO=n +CONFIG_DISPLAY_BOARDINFO=n +CONFIG_EFI_LOADER=n + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y + +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y + +CONFIG_NOT_UUU_BUILD=y +CONFIG_SHA256=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_APPEND_BOOTARGS=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 diff --git a/configs/imx8qm_mek_androidauto_defconfig b/configs/imx8qm_mek_androidauto_defconfig new file mode 100644 index 00000000000..2065e1988c8 --- /dev/null +++ b/configs/imx8qm_mek_androidauto_defconfig @@ -0,0 +1,116 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-auto" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_EFI_PARTITION=y +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_DM_WARN=n +CONFIG_DM_DEVICE_REMOVE=n + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=n + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y + +CONFIG_USB_GADGET=y +#CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_CMD_NET=n +CONFIG_CMD_NFS=n +CONFIG_CMD_BDI=n +CONFIG_CMD_CONSOLE=n +CONFIG_CMD_BOOTD=n +CONFIG_CMD_BOOTEFI=n +CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n +CONFIG_CMD_ELF=n +CONFIG_CMD_GO=n +CONFIG_CMD_RUN=n +CONFIG_CMD_IMI=n +CONFIG_CMD_IMLS=n +CONFIG_CMD_XIMG=n +CONFIG_CMD_EXPORTENV=n +CONFIG_CMD_IMPORTENV=n +CONFIG_CMD_EDITENV=n +CONFIG_CMD_ENV_EXISTS=n +CONFIG_CMD_CRC32=n +CONFIG_CMD_DM=n +CONFIG_CMD_LOADB=n +CONFIG_CMD_LOADS=n +CONFIG_CMD_FLASH=n +CONFIG_CMD_GPT=n +CONFIG_CMD_FPGA=n +CONFIG_CMD_ECHO=n +CONFIG_CMD_ITEST=n +CONFIG_CMD_SOURCE=n +CONFIG_CMD_SETEXPR=n +CONFIG_CMD_MISC=n +CONFIG_CMD_UNZIP=n +CONFIG_CMD_LZMADEC=n +CONFIG_CMD_SAVEENV=n + +CONFIG_DISPLAY_CPUINFO=n +CONFIG_DISPLAY_BOARDINFO=n +CONFIG_EFI_LOADER=n + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_mek_androidauto_trusty_defconfig b/configs/imx8qm_mek_androidauto_trusty_defconfig new file mode 100644 index 00000000000..1f7e10d4d81 --- /dev/null +++ b/configs/imx8qm_mek_androidauto_trusty_defconfig @@ -0,0 +1,126 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-auto" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_EFI_PARTITION=y +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_DM_WARN=n +CONFIG_DM_DEVICE_REMOVE=n +CONFIG_IMX_TRUSTY_OS=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=n + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y + +CONFIG_USB_GADGET=y +#CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_CMD_NET=n +CONFIG_CMD_NFS=n +CONFIG_CMD_BDI=n +CONFIG_CMD_CONSOLE=n +CONFIG_CMD_BOOTD=n +CONFIG_CMD_BOOTEFI=n +CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n +CONFIG_CMD_ELF=n +CONFIG_CMD_GO=n +CONFIG_CMD_RUN=n +CONFIG_CMD_IMI=n +CONFIG_CMD_IMLS=n +CONFIG_CMD_XIMG=n +CONFIG_CMD_EXPORTENV=n +CONFIG_CMD_IMPORTENV=n +CONFIG_CMD_EDITENV=n +CONFIG_CMD_ENV_EXISTS=n +CONFIG_CMD_CRC32=n +CONFIG_CMD_DM=n +CONFIG_CMD_LOADB=n +CONFIG_CMD_LOADS=n +CONFIG_CMD_FLASH=n +CONFIG_CMD_GPT=n +CONFIG_CMD_FPGA=n +CONFIG_CMD_ECHO=n +CONFIG_CMD_ITEST=n +CONFIG_CMD_SOURCE=n +CONFIG_CMD_SETEXPR=n +CONFIG_CMD_MISC=n +CONFIG_CMD_UNZIP=n +CONFIG_CMD_LZMADEC=n +CONFIG_CMD_SAVEENV=n + +CONFIG_DISPLAY_CPUINFO=n +CONFIG_DISPLAY_BOARDINFO=n +CONFIG_EFI_LOADER=n + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y + +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y + +CONFIG_NOT_UUU_BUILD=y +CONFIG_SHA256=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_APPEND_BOOTARGS=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88800000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x02000000 diff --git a/configs/imx8qm_mek_androidauto_xen_defconfig b/configs/imx8qm_mek_androidauto_xen_defconfig new file mode 100644 index 00000000000..572592a3289 --- /dev/null +++ b/configs/imx8qm_mek_androidauto_xen_defconfig @@ -0,0 +1,128 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-xen" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x80080000 +CONFIG_EFI_PARTITION=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_DM_WARN=n +CONFIG_DM_DEVICE_REMOVE=n +CONFIG_IMX_TRUSTY_OS=n + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=n +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=n +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=n +CONFIG_CMD_I2C=n + +CONFIG_USB_XHCI_HCD=n +CONFIG_USB_XHCI_IMX8=n + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=n + +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=n +CONFIG_USB_CDNS3_GADGET=n +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_DM_GPIO=n +CONFIG_DM_PCA953X=n +CONFIG_BOOTDELAY=1 +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=n +CONFIG_DM_SPI=n +CONFIG_DM_SPI_FLASH=n +CONFIG_SPI_FLASH=n +CONFIG_SPI_FLASH_4BYTES_ADDR=n +CONFIG_SPI_FLASH_STMICRO=n + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=n +CONFIG_DM_REGULATOR_GPIO=n + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_CMD_NET=n +CONFIG_CMD_NFS=n +CONFIG_CMD_BDI=n +CONFIG_CMD_CONSOLE=n +CONFIG_CMD_BOOTD=n +CONFIG_CMD_BOOTEFI=n +CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n +CONFIG_CMD_ELF=n +CONFIG_CMD_GO=n +CONFIG_CMD_RUN=n +CONFIG_CMD_IMI=n +CONFIG_CMD_IMLS=n +CONFIG_CMD_XIMG=n +CONFIG_CMD_EXPORTENV=n +CONFIG_CMD_IMPORTENV=n +CONFIG_CMD_EDITENV=n +CONFIG_CMD_ENV_EXISTS=n +CONFIG_CMD_MEMORY=y +CONFIG_CMD_CRC32=n +CONFIG_CMD_DM=n +CONFIG_CMD_LOADB=n +CONFIG_CMD_LOADS=n +CONFIG_CMD_FLASH=n +CONFIG_CMD_GPT=n +CONFIG_CMD_FPGA=n +CONFIG_CMD_ECHO=n +CONFIG_CMD_ITEST=n +CONFIG_CMD_SOURCE=n +CONFIG_CMD_SETEXPR=n +CONFIG_CMD_MISC=n +CONFIG_CMD_UNZIP=n +CONFIG_CMD_LZMADEC=n +CONFIG_CMD_SAVEENV=n + +CONFIG_DISPLAY_CPUINFO=n +CONFIG_DISPLAY_BOARDINFO=n +CONFIG_EFI_LOADER=n + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=n +CONFIG_IMX_SC_THERMAL=n + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y +CONFIG_XEN=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +CONFIG_XEN_DEBUG_SERIAL=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_FIT=y +CONFIG_SPL=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y + +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_mek_androidauto_xen_dual_defconfig b/configs/imx8qm_mek_androidauto_xen_dual_defconfig new file mode 100644 index 00000000000..8051bbfef2b --- /dev/null +++ b/configs/imx8qm_mek_androidauto_xen_dual_defconfig @@ -0,0 +1,130 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-xen" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x81080000 +CONFIG_EFI_PARTITION=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_DM_WARN=n +CONFIG_DM_DEVICE_REMOVE=n +CONFIG_IMX_TRUSTY_OS=n + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=n +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=n +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=n +CONFIG_CMD_I2C=n + +CONFIG_USB_XHCI_HCD=n +CONFIG_USB_XHCI_IMX8=n + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=n + +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=n +CONFIG_USB_CDNS3_GADGET=n +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_DM_GPIO=n +CONFIG_DM_PCA953X=n +CONFIG_BOOTDELAY=1 +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=n +CONFIG_DM_SPI=n +CONFIG_DM_SPI_FLASH=n +CONFIG_SPI_FLASH=n +CONFIG_SPI_FLASH_4BYTES_ADDR=n +CONFIG_SPI_FLASH_STMICRO=n + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=n +CONFIG_DM_REGULATOR_GPIO=n + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_CMD_NET=n +CONFIG_CMD_NFS=n +CONFIG_CMD_BDI=n +CONFIG_CMD_CONSOLE=n +CONFIG_CMD_BOOTD=n +CONFIG_CMD_BOOTEFI=n +CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n +CONFIG_CMD_ELF=n +CONFIG_CMD_GO=n +CONFIG_CMD_RUN=n +CONFIG_CMD_IMI=n +CONFIG_CMD_IMLS=n +CONFIG_CMD_XIMG=n +CONFIG_CMD_EXPORTENV=n +CONFIG_CMD_IMPORTENV=n +CONFIG_CMD_EDITENV=n +CONFIG_CMD_ENV_EXISTS=n +CONFIG_CMD_MEMORY=y +CONFIG_CMD_CRC32=n +CONFIG_CMD_DM=n +CONFIG_CMD_LOADB=n +CONFIG_CMD_LOADS=n +CONFIG_CMD_FLASH=n +CONFIG_CMD_GPT=n +CONFIG_CMD_FPGA=n +CONFIG_CMD_ECHO=n +CONFIG_CMD_ITEST=n +CONFIG_CMD_SOURCE=n +CONFIG_CMD_SETEXPR=n +CONFIG_CMD_MISC=n +CONFIG_CMD_UNZIP=n +CONFIG_CMD_LZMADEC=n +CONFIG_CMD_SAVEENV=n + +CONFIG_DISPLAY_CPUINFO=n +CONFIG_DISPLAY_BOARDINFO=n +CONFIG_EFI_LOADER=n + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=n +CONFIG_IMX_SC_THERMAL=n + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y +CONFIG_XEN=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +CONFIG_XEN_DEBUG_SERIAL=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y + +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y + +CONFIG_NOT_UUU_BUILD=y +CONFIG_SHA256=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_APPEND_BOOTARGS=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88800000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x02000000 diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig new file mode 100644 index 00000000000..27803eee36b --- /dev/null +++ b/configs/imx8qm_mek_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_mek_fspi_defconfig b/configs/imx8qm_mek_fspi_defconfig new file mode 100644 index 00000000000..5d0ea83b068 --- /dev/null +++ b/configs/imx8qm_mek_fspi_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_QSPI_BOOT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_SPI_FLASH=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_mek_spl_defconfig b/configs/imx8qm_mek_spl_defconfig new file mode 100644 index 00000000000..5fd773098e6 --- /dev/null +++ b/configs/imx8qm_mek_spl_defconfig @@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_SPL=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_SPL_OF_CONTROL=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_mek_spl_fspi_defconfig b/configs/imx8qm_mek_spl_fspi_defconfig new file mode 100644 index 00000000000..c0735a81d05 --- /dev/null +++ b/configs/imx8qm_mek_spl_fspi_defconfig @@ -0,0 +1,117 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_SPL=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_PANIC_HANG=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qm_mek_spl_trusty_defconfig b/configs/imx8qm_mek_spl_trusty_defconfig new file mode 100644 index 00000000000..6da27b83439 --- /dev/null +++ b/configs/imx8qm_mek_spl_trusty_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_SPL=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_SPL_OF_CONTROL=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +#CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y +CONFIG_IMX8_TRUSTY_XEN=y + +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_17x17_val_defconfig b/configs/imx8qxp_17x17_val_defconfig new file mode 100644 index 00000000000..46a91a86949 --- /dev/null +++ b/configs/imx8qxp_17x17_val_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-17x17-val" +CONFIG_TARGET_IMX8X_17X17_VAL=y +CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-17x17-val.dtb" +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_USB_CDNS3=y +# CONFIG_USB_CDNS3_GADGET=y +# CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_EFI_PARTITION=y + +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_ddr3_arm2_defconfig b/configs/imx8qxp_ddr3_arm2_defconfig new file mode 100644 index 00000000000..80db94abf7e --- /dev/null +++ b/configs/imx8qxp_ddr3_arm2_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-ddr3l-val.dtb" +CONFIG_TARGET_IMX8QXP_DDR3_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y + +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_lpddr4_arm2_android_defconfig b/configs/imx8qxp_lpddr4_arm2_android_defconfig new file mode 100644 index 00000000000..25037c25546 --- /dev/null +++ b/configs/imx8qxp_lpddr4_arm2_android_defconfig @@ -0,0 +1,92 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" +CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_EFI_PARTITION=y +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y + +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_lpddr4_arm2_defconfig b/configs/imx8qxp_lpddr4_arm2_defconfig new file mode 100644 index 00000000000..1550860a5ec --- /dev/null +++ b/configs/imx8qxp_lpddr4_arm2_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" +CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y + +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 +CONFIG_EFI_PARTITION=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_lpddr4_arm2_fspi_defconfig b/configs/imx8qxp_lpddr4_arm2_fspi_defconfig new file mode 100644 index 00000000000..35b7969f5bf --- /dev/null +++ b/configs/imx8qxp_lpddr4_arm2_fspi_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" +CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_QSPI_BOOT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_SPI_FLASH=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_lpddr4_arm2_nand_defconfig b/configs/imx8qxp_lpddr4_arm2_nand_defconfig new file mode 100644 index 00000000000..ab9e1cfaec5 --- /dev/null +++ b/configs/imx8qxp_lpddr4_arm2_nand_defconfig @@ -0,0 +1,99 @@ + +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" +CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_NAND=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 +CONFIG_EFI_PARTITION=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_lpddr4_arm2_spl_defconfig b/configs/imx8qxp_lpddr4_arm2_spl_defconfig new file mode 100644 index 00000000000..473110005ff --- /dev/null +++ b/configs/imx8qxp_lpddr4_arm2_spl_defconfig @@ -0,0 +1,111 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" +CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_SPL=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_SPL_OF_CONTROL=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y + +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM_DEVICE_REMOVE=n + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 +CONFIG_EFI_PARTITION=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_lpddr4_arm2_spl_nand_defconfig b/configs/imx8qxp_lpddr4_arm2_spl_nand_defconfig new file mode 100644 index 00000000000..fdcf2f98982 --- /dev/null +++ b/configs/imx8qxp_lpddr4_arm2_spl_nand_defconfig @@ -0,0 +1,106 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" +CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x20000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_SPL=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_SPL_OF_CONTROL=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y + +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_NAND=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 +CONFIG_EFI_PARTITION=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_mek_android_defconfig b/configs/imx8qxp_mek_android_defconfig new file mode 100644 index 00000000000..1915b5de18a --- /dev/null +++ b/configs/imx8qxp_mek_android_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_EFI_PARTITION=y +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y + +CONFIG_NOT_UUU_BUILD=y +CONFIG_APPEND_BOOTARGS=y + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000 diff --git a/configs/imx8qxp_mek_android_uuu_defconfig b/configs/imx8qxp_mek_android_uuu_defconfig new file mode 100644 index 00000000000..df2e61f9628 --- /dev/null +++ b/configs/imx8qxp_mek_android_uuu_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_EFI_PARTITION=y +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_mek_androidauto2_trusty_defconfig b/configs/imx8qxp_mek_androidauto2_trusty_defconfig new file mode 100644 index 00000000000..4215fe10655 --- /dev/null +++ b/configs/imx8qxp_mek_androidauto2_trusty_defconfig @@ -0,0 +1,127 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek-auto" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_EFI_PARTITION=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_DM_WARN=n +CONFIG_DM_DEVICE_REMOVE=n +CONFIG_IMX_TRUSTY_OS=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=n +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y + +CONFIG_USB_GADGET=y +#CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_CMD_NET=n +CONFIG_CMD_NFS=n +CONFIG_CMD_BDI=n +CONFIG_CMD_CONSOLE=n +CONFIG_CMD_BOOTD=n +CONFIG_CMD_BOOTEFI=n +CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n +CONFIG_CMD_ELF=n +CONFIG_CMD_GO=n +CONFIG_CMD_RUN=n +CONFIG_CMD_IMI=n +CONFIG_CMD_IMLS=n +CONFIG_CMD_XIMG=n +CONFIG_CMD_EXPORTENV=n +CONFIG_CMD_IMPORTENV=n +CONFIG_CMD_EDITENV=n +CONFIG_CMD_ENV_EXISTS=n +CONFIG_CMD_CRC32=n +CONFIG_CMD_DM=n +CONFIG_CMD_LOADB=n +CONFIG_CMD_LOADS=n +CONFIG_CMD_FLASH=n +CONFIG_CMD_GPT=n +CONFIG_CMD_FPGA=n +CONFIG_CMD_ECHO=n +CONFIG_CMD_ITEST=n +CONFIG_CMD_SOURCE=n +CONFIG_CMD_SETEXPR=n +CONFIG_CMD_MISC=n +CONFIG_CMD_UNZIP=n +CONFIG_CMD_LZMADEC=n +CONFIG_CMD_SAVEENV=n + +CONFIG_DISPLAY_CPUINFO=n +CONFIG_DISPLAY_BOARDINFO=n +CONFIG_EFI_LOADER=n + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y + +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y + +CONFIG_NOT_UUU_BUILD=y +CONFIG_SHA256=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_APPEND_BOOTARGS=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000 diff --git a/configs/imx8qxp_mek_androidauto_defconfig b/configs/imx8qxp_mek_androidauto_defconfig new file mode 100644 index 00000000000..4b4fdb231e6 --- /dev/null +++ b/configs/imx8qxp_mek_androidauto_defconfig @@ -0,0 +1,117 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek-auto" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_EFI_PARTITION=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_DM_WARN=n +CONFIG_DM_DEVICE_REMOVE=n + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=n +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y + +CONFIG_USB_GADGET=y +#CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_CMD_NET=n +CONFIG_CMD_NFS=n +CONFIG_CMD_BDI=n +CONFIG_CMD_CONSOLE=n +CONFIG_CMD_BOOTD=n +CONFIG_CMD_BOOTEFI=n +CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n +CONFIG_CMD_ELF=n +CONFIG_CMD_GO=n +CONFIG_CMD_RUN=n +CONFIG_CMD_IMI=n +CONFIG_CMD_IMLS=n +CONFIG_CMD_XIMG=n +CONFIG_CMD_EXPORTENV=n +CONFIG_CMD_IMPORTENV=n +CONFIG_CMD_EDITENV=n +CONFIG_CMD_ENV_EXISTS=n +CONFIG_CMD_CRC32=n +CONFIG_CMD_DM=n +CONFIG_CMD_LOADB=n +CONFIG_CMD_LOADS=n +CONFIG_CMD_FLASH=n +CONFIG_CMD_GPT=n +CONFIG_CMD_FPGA=n +CONFIG_CMD_ECHO=n +CONFIG_CMD_ITEST=n +CONFIG_CMD_SOURCE=n +CONFIG_CMD_SETEXPR=n +CONFIG_CMD_MISC=n +CONFIG_CMD_UNZIP=n +CONFIG_CMD_LZMADEC=n +CONFIG_CMD_SAVEENV=n + +CONFIG_DISPLAY_CPUINFO=n +CONFIG_DISPLAY_BOARDINFO=n +CONFIG_EFI_LOADER=n + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_mek_androidauto_trusty_defconfig b/configs/imx8qxp_mek_androidauto_trusty_defconfig new file mode 100644 index 00000000000..6720adde8eb --- /dev/null +++ b/configs/imx8qxp_mek_androidauto_trusty_defconfig @@ -0,0 +1,127 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek-auto" +CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_EFI_PARTITION=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_DM_WARN=n +CONFIG_DM_DEVICE_REMOVE=n +CONFIG_IMX_TRUSTY_OS=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=n +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y + +CONFIG_USB_GADGET=y +#CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=1 +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_CMD_NET=n +CONFIG_CMD_NFS=n +CONFIG_CMD_BDI=n +CONFIG_CMD_CONSOLE=n +CONFIG_CMD_BOOTD=n +CONFIG_CMD_BOOTEFI=n +CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n +CONFIG_CMD_ELF=n +CONFIG_CMD_GO=n +CONFIG_CMD_RUN=n +CONFIG_CMD_IMI=n +CONFIG_CMD_IMLS=n +CONFIG_CMD_XIMG=n +CONFIG_CMD_EXPORTENV=n +CONFIG_CMD_IMPORTENV=n +CONFIG_CMD_EDITENV=n +CONFIG_CMD_ENV_EXISTS=n +CONFIG_CMD_CRC32=n +CONFIG_CMD_DM=n +CONFIG_CMD_LOADB=n +CONFIG_CMD_LOADS=n +CONFIG_CMD_FLASH=n +CONFIG_CMD_GPT=n +CONFIG_CMD_FPGA=n +CONFIG_CMD_ECHO=n +CONFIG_CMD_ITEST=n +CONFIG_CMD_SOURCE=n +CONFIG_CMD_SETEXPR=n +CONFIG_CMD_MISC=n +CONFIG_CMD_UNZIP=n +CONFIG_CMD_LZMADEC=n +CONFIG_CMD_SAVEENV=n + +CONFIG_DISPLAY_CPUINFO=n +CONFIG_DISPLAY_BOARDINFO=n +CONFIG_EFI_LOADER=n + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_LZ4=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y + +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y + +CONFIG_NOT_UUU_BUILD=y +CONFIG_SHA256=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_APPEND_BOOTARGS=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x02000000 diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig new file mode 100644 index 00000000000..b9cec95b995 --- /dev/null +++ b/configs/imx8qxp_mek_defconfig @@ -0,0 +1,103 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_mek_fspi_defconfig b/configs/imx8qxp_mek_fspi_defconfig new file mode 100644 index 00000000000..0bc248794ca --- /dev/null +++ b/configs/imx8qxp_mek_fspi_defconfig @@ -0,0 +1,104 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_QSPI_BOOT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_SPI_FLASH=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_mek_spl_defconfig b/configs/imx8qxp_mek_spl_defconfig new file mode 100644 index 00000000000..b578288cd16 --- /dev/null +++ b/configs/imx8qxp_mek_spl_defconfig @@ -0,0 +1,118 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y + +CONFIG_SPL=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_SPL_OF_CONTROL=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/imx8qxp_mek_spl_fspi_defconfig b/configs/imx8qxp_mek_spl_fspi_defconfig new file mode 100644 index 00000000000..53c8c9441b4 --- /dev/null +++ b/configs/imx8qxp_mek_spl_fspi_defconfig @@ -0,0 +1,122 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y + +CONFIG_SPL=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_PANIC_HANG=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y + +CONFIG_USB=y +CONFIG_USB_TCPC=y + +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y + +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/configs/multa-imx7d_defconfig b/configs/multa-imx7d_defconfig new file mode 100644 index 00000000000..2ff4eb49946 --- /dev/null +++ b/configs/multa-imx7d_defconfig @@ -0,0 +1,35 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/multa-imx7d/imximage.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_TARGET_MULTA_IMX7D=y +CONFIG_BOOTDELAY=3 +CONFIG_EFI_PARTITION=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_VIDEO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig index 1dc4e975ff3..17175f471b9 100644 --- a/configs/mx6dlarm2_defconfig +++ b/configs/mx6dlarm2_defconfig @@ -1,18 +1,17 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048" +CONFIG_TARGET_MX6DLARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,DDR_MB=2048" CONFIG_BOOTDELAY=3 -CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -26,6 +25,19 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6dl-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig index 8f07f8feead..8e031b7d9e1 100644 --- a/configs/mx6dlarm2_lpddr2_defconfig +++ b/configs/mx6dlarm2_lpddr2_defconfig @@ -1,18 +1,17 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512" +CONFIG_TARGET_MX6DLARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL_LPDDR2,DDR_MB=512" CONFIG_BOOTDELAY=3 -CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -26,6 +25,19 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6dl-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlarm2_lpddr2_plugin_defconfig b/configs/mx6dlarm2_lpddr2_plugin_defconfig new file mode 100644 index 00000000000..646cff44593 --- /dev/null +++ b/configs/mx6dlarm2_lpddr2_plugin_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL_LPDDR2,DDR_MB=512" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6dl-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlarm2_plugin_defconfig b/configs/mx6dlarm2_plugin_defconfig new file mode 100644 index 00000000000..0f0a2a86abe --- /dev/null +++ b/configs/mx6dlarm2_plugin_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,DDR_MB=2048" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6dl-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig new file mode 100644 index 00000000000..2975c49587d --- /dev/null +++ b/configs/mx6dlsabreauto_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabreauto_eimnor_defconfig b/configs/mx6dlsabreauto_eimnor_defconfig new file mode 100644 index 00000000000..31357cd68b0 --- /dev/null +++ b/configs/mx6dlsabreauto_eimnor_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_CMD_FLASH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabreauto_nand_defconfig b/configs/mx6dlsabreauto_nand_defconfig new file mode 100644 index 00000000000..6a9c87a8407 --- /dev/null +++ b/configs/mx6dlsabreauto_nand_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabreauto_optee_defconfig b/configs/mx6dlsabreauto_optee_defconfig new file mode 100644 index 00000000000..79135c113bc --- /dev/null +++ b/configs/mx6dlsabreauto_optee_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabreauto_plugin_defconfig b/configs/mx6dlsabreauto_plugin_defconfig new file mode 100644 index 00000000000..df44cf7b003 --- /dev/null +++ b/configs/mx6dlsabreauto_plugin_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabreauto_spinor_defconfig b/configs/mx6dlsabreauto_spinor_defconfig new file mode 100644 index 00000000000..8a7da459c4b --- /dev/null +++ b/configs/mx6dlsabreauto_spinor_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_SPI_BOOT=y +CONFIG_CMD_SF=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-ecspi" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig new file mode 100644 index 00000000000..2cc406d88d7 --- /dev/null +++ b/configs/mx6dlsabresd_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6dlsabresd_epdc_defconfig b/configs/mx6dlsabresd_epdc_defconfig new file mode 100644 index 00000000000..d622c35a69b --- /dev/null +++ b/configs/mx6dlsabresd_epdc_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_MXC_EPDC=y +CONFIG_LCD=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6dlsabresd_optee_defconfig b/configs/mx6dlsabresd_optee_defconfig new file mode 100644 index 00000000000..6b833beba1b --- /dev/null +++ b/configs/mx6dlsabresd_optee_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6dlsabresd_plugin_defconfig b/configs/mx6dlsabresd_plugin_defconfig new file mode 100644 index 00000000000..d7a4d0a02af --- /dev/null +++ b/configs/mx6dlsabresd_plugin_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6DLSABRESD=y +CONFIG_VIDEO=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig index 925fc16d6cb..f62cf42465a 100644 --- a/configs/mx6qarm2_defconfig +++ b/configs/mx6qarm2_defconfig @@ -1,18 +1,17 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,DDR_MB=2048" CONFIG_BOOTDELAY=3 -CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -26,6 +25,19 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig index b907cb42255..ec8f1940d45 100644 --- a/configs/mx6qarm2_lpddr2_defconfig +++ b/configs/mx6qarm2_lpddr2_defconfig @@ -1,18 +1,17 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_MX6QARM2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6DQ_LPDDR2,DDR_MB=512" CONFIG_BOOTDELAY=3 -CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -26,6 +25,19 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_lpddr2_plugin_defconfig b/configs/mx6qarm2_lpddr2_plugin_defconfig new file mode 100644 index 00000000000..9eb57208cea --- /dev/null +++ b/configs/mx6qarm2_lpddr2_plugin_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6DQ_LPDDR2,DDR_MB=512" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_plugin_defconfig b/configs/mx6qarm2_plugin_defconfig new file mode 100644 index 00000000000..a80a72ff05c --- /dev/null +++ b/configs/mx6qarm2_plugin_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,DDR_MB=2048" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_pop_lpddr2_defconfig b/configs/mx6qarm2_pop_lpddr2_defconfig new file mode 100644 index 00000000000..15d4ee374d8 --- /dev/null +++ b/configs/mx6qarm2_pop_lpddr2_defconfig @@ -0,0 +1,43 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6DQ_POP_LPDDR2,DDR_MB=256" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-pop-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-pop-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_pop_lpddr2_revb_defconfig b/configs/mx6qarm2_pop_lpddr2_revb_defconfig new file mode 100644 index 00000000000..634275b31c7 --- /dev/null +++ b/configs/mx6qarm2_pop_lpddr2_revb_defconfig @@ -0,0 +1,43 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/mt128x64mx32.cfg,MX6DQ_POP_LPDDR2,DDR_MB=512" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-pop-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-pop-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig new file mode 100644 index 00000000000..ad310999f2a --- /dev/null +++ b/configs/mx6qpsabreauto_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabreauto_eimnor_defconfig b/configs/mx6qpsabreauto_eimnor_defconfig new file mode 100644 index 00000000000..2c772295584 --- /dev/null +++ b/configs/mx6qpsabreauto_eimnor_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_CMD_FLASH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabreauto_nand_defconfig b/configs/mx6qpsabreauto_nand_defconfig new file mode 100644 index 00000000000..d13f90226e9 --- /dev/null +++ b/configs/mx6qpsabreauto_nand_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabreauto_optee_defconfig b/configs/mx6qpsabreauto_optee_defconfig new file mode 100644 index 00000000000..53c454c4f68 --- /dev/null +++ b/configs/mx6qpsabreauto_optee_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabreauto_plugin_defconfig b/configs/mx6qpsabreauto_plugin_defconfig new file mode 100644 index 00000000000..6b0970cc3e2 --- /dev/null +++ b/configs/mx6qpsabreauto_plugin_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabreauto_sata_defconfig b/configs/mx6qpsabreauto_sata_defconfig new file mode 100644 index 00000000000..46bb1980684 --- /dev/null +++ b/configs/mx6qpsabreauto_sata_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_SATA_BOOT=y +CONFIG_CMD_SATA=y +CONFIG_SATA=y +CONFIG_ENV_IS_IN_SATA=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_BLK is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_STORAGE_SATA=y +CONFIG_FASTBOOT_SATA_NO=0 diff --git a/configs/mx6qpsabreauto_spinor_defconfig b/configs/mx6qpsabreauto_spinor_defconfig new file mode 100644 index 00000000000..ce8c5e4cd22 --- /dev/null +++ b/configs/mx6qpsabreauto_spinor_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_SPI_BOOT=y +CONFIG_CMD_SF=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto-ecspi" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabresd_defconfig b/configs/mx6qpsabresd_defconfig new file mode 100644 index 00000000000..9aab38b82bd --- /dev/null +++ b/configs/mx6qpsabresd_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6qp.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabresd_optee_defconfig b/configs/mx6qpsabresd_optee_defconfig new file mode 100644 index 00000000000..2bd80911938 --- /dev/null +++ b/configs/mx6qpsabresd_optee_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6qp.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabresd_sata_defconfig b/configs/mx6qpsabresd_sata_defconfig new file mode 100644 index 00000000000..e3f7fa257fb --- /dev/null +++ b/configs/mx6qpsabresd_sata_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QPSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6qp.cfg" +CONFIG_SATA_BOOT=y +CONFIG_CMD_SATA=y +CONFIG_SATA=y +CONFIG_ENV_IS_IN_SATA=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_BLK is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_STORAGE_SATA=y +CONFIG_FASTBOOT_SATA_NO=0 + diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig new file mode 100644 index 00000000000..028bcafa462 --- /dev/null +++ b/configs/mx6qsabreauto_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabreauto_eimnor_defconfig b/configs/mx6qsabreauto_eimnor_defconfig new file mode 100644 index 00000000000..6dbdfacbc3b --- /dev/null +++ b/configs/mx6qsabreauto_eimnor_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_CMD_FLASH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabreauto_nand_defconfig b/configs/mx6qsabreauto_nand_defconfig new file mode 100644 index 00000000000..9453a992073 --- /dev/null +++ b/configs/mx6qsabreauto_nand_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabreauto_optee_defconfig b/configs/mx6qsabreauto_optee_defconfig new file mode 100644 index 00000000000..ddd3362a0f7 --- /dev/null +++ b/configs/mx6qsabreauto_optee_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabreauto_plugin_defconfig b/configs/mx6qsabreauto_plugin_defconfig new file mode 100644 index 00000000000..5f45e02121c --- /dev/null +++ b/configs/mx6qsabreauto_plugin_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabreauto_sata_defconfig b/configs/mx6qsabreauto_sata_defconfig new file mode 100644 index 00000000000..1348adb71bd --- /dev/null +++ b/configs/mx6qsabreauto_sata_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_SATA_BOOT=y +CONFIG_CMD_SATA=y +CONFIG_SATA=y +CONFIG_ENV_IS_IN_SATA=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_BLK is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_STORAGE_SATA=y +CONFIG_FASTBOOT_SATA_NO=0 diff --git a/configs/mx6qsabreauto_spinor_defconfig b/configs/mx6qsabreauto_spinor_defconfig new file mode 100644 index 00000000000..b57d573a681 --- /dev/null +++ b/configs/mx6qsabreauto_spinor_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_SPI_BOOT=y +CONFIG_CMD_SF=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-ecspi" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig new file mode 100644 index 00000000000..95ce29893de --- /dev/null +++ b/configs/mx6qsabresd_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabresd_optee_defconfig b/configs/mx6qsabresd_optee_defconfig new file mode 100644 index 00000000000..fa548396076 --- /dev/null +++ b/configs/mx6qsabresd_optee_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabresd_plugin_defconfig b/configs/mx6qsabresd_plugin_defconfig new file mode 100644 index 00000000000..fd5da25f5f0 --- /dev/null +++ b/configs/mx6qsabresd_plugin_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABRESD=y +CONFIG_VIDEO=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabresd_sata_defconfig b/configs/mx6qsabresd_sata_defconfig new file mode 100644 index 00000000000..a5f0bdbc761 --- /dev/null +++ b/configs/mx6qsabresd_sata_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg" +CONFIG_SATA_BOOT=y +CONFIG_CMD_SATA=y +CONFIG_SATA=y +CONFIG_ENV_IS_IN_SATA=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_BLK is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_PCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_PCI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_STORAGE_SATA=y +CONFIG_FASTBOOT_SATA_NO=0 + diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index a49e9cd72ab..6145b33f42b 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -1,15 +1,15 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_MX6SLEVK=y -# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" -CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -50,3 +50,20 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6slevk_epdc_defconfig b/configs/mx6slevk_epdc_defconfig new file mode 100644 index 00000000000..e7fa073d202 --- /dev/null +++ b/configs/mx6slevk_epdc_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLEVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_ETH=y +CONFIG_LCD=y +CONFIG_MXC_EPDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6slevk_optee_defconfig b/configs/mx6slevk_optee_defconfig new file mode 100644 index 00000000000..0519db90696 --- /dev/null +++ b/configs/mx6slevk_optee_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLEVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6slevk_plugin_defconfig b/configs/mx6slevk_plugin_defconfig new file mode 100644 index 00000000000..1b6ee74b209 --- /dev/null +++ b/configs/mx6slevk_plugin_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLEVK=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 76fc5840559..a617e31bf06 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -1,19 +1,20 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_MX6SLEVK=y -# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" CONFIG_SPI_BOOT=y -CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -50,3 +51,21 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_ETH=y + +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sll_lpddr2_arm2_defconfig b/configs/mx6sll_lpddr2_arm2_defconfig new file mode 100644 index 00000000000..dc5fb75d010 --- /dev/null +++ b/configs/mx6sll_lpddr2_arm2_defconfig @@ -0,0 +1,49 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_arm2/imximage_lpddr2.cfg" +CONFIG_LPDDR2_BOARD=y +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLL_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr2-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr2-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_STORAGE=y diff --git a/configs/mx6sll_lpddr3_arm2_defconfig b/configs/mx6sll_lpddr3_arm2_defconfig new file mode 100644 index 00000000000..d8eb27618a0 --- /dev/null +++ b/configs/mx6sll_lpddr3_arm2_defconfig @@ -0,0 +1,48 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLL_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_STORAGE=y diff --git a/configs/mx6sll_lpddr3_arm2_epdc_defconfig b/configs/mx6sll_lpddr3_arm2_epdc_defconfig new file mode 100644 index 00000000000..c93d63b036c --- /dev/null +++ b/configs/mx6sll_lpddr3_arm2_epdc_defconfig @@ -0,0 +1,50 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLL_ARM2=y +CONFIG_VIDEO=y +CONFIG_MXC_EPDC=y +CONFIG_LCD=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_STORAGE=y diff --git a/configs/mx6sll_lpddr3_arm2_plugin_defconfig b/configs/mx6sll_lpddr3_arm2_plugin_defconfig new file mode 100644 index 00000000000..9255ca75a12 --- /dev/null +++ b/configs/mx6sll_lpddr3_arm2_plugin_defconfig @@ -0,0 +1,49 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLL_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-arm2.dtb" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_STORAGE=y diff --git a/configs/mx6sll_lpddr3_arm2_spinor_defconfig b/configs/mx6sll_lpddr3_arm2_spinor_defconfig new file mode 100644 index 00000000000..1d8039d57cf --- /dev/null +++ b/configs/mx6sll_lpddr3_arm2_spinor_defconfig @@ -0,0 +1,51 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLL_ARM2=y +CONFIG_SPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-arm2-ecspi" +CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_STORAGE=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index 39c1cef3ce5..44a5a5139fa 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -1,14 +1,14 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_MX6SLLEVK=y -# CONFIG_CMD_BMODE is not set +CONFIG_VIDEO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" -CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -21,6 +21,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FASTBOOT=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y @@ -42,3 +43,17 @@ CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sllevk_epdc_defconfig b/configs/mx6sllevk_epdc_defconfig new file mode 100644 index 00000000000..7756400fc89 --- /dev/null +++ b/configs/mx6sllevk_epdc_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLLEVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" +CONFIG_MXC_EPDC=y +CONFIG_LCD=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FASTBOOT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sllevk_optee_defconfig b/configs/mx6sllevk_optee_defconfig new file mode 100644 index 00000000000..3ee80bc569a --- /dev/null +++ b/configs/mx6sllevk_optee_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLLEVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FASTBOOT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 86f51958059..53aa572b697 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -1,15 +1,15 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_MX6SLLEVK=y CONFIG_USE_IMXIMG_PLUGIN=y -# CONFIG_CMD_BMODE is not set +CONFIG_VIDEO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" -CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -22,6 +22,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_FSL_FASTBOOT=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y @@ -43,3 +44,16 @@ CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabreauto_defconfig b/configs/mx6solosabreauto_defconfig new file mode 100644 index 00000000000..ba01c7fa83e --- /dev/null +++ b/configs/mx6solosabreauto_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SOLOSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6solo.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabreauto_eimnor_defconfig b/configs/mx6solosabreauto_eimnor_defconfig new file mode 100644 index 00000000000..bf5f4baae87 --- /dev/null +++ b/configs/mx6solosabreauto_eimnor_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SOLOSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6solo.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_CMD_FLASH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabreauto_nand_defconfig b/configs/mx6solosabreauto_nand_defconfig new file mode 100644 index 00000000000..ad7c8527663 --- /dev/null +++ b/configs/mx6solosabreauto_nand_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SOLOSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6solo.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabreauto_optee_defconfig b/configs/mx6solosabreauto_optee_defconfig new file mode 100644 index 00000000000..aa9006a9511 --- /dev/null +++ b/configs/mx6solosabreauto_optee_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SOLOSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6solo.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabreauto_spinor_defconfig b/configs/mx6solosabreauto_spinor_defconfig new file mode 100644 index 00000000000..e037e98587d --- /dev/null +++ b/configs/mx6solosabreauto_spinor_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SOLOSABREAUTO=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6solo.cfg" +CONFIG_SPI_BOOT=y +CONFIG_CMD_SF=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-ecspi" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabresd_defconfig b/configs/mx6solosabresd_defconfig new file mode 100644 index 00000000000..f848fc4d2b2 --- /dev/null +++ b/configs/mx6solosabresd_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SOLOSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6solosabresd_optee_defconfig b/configs/mx6solosabresd_optee_defconfig new file mode 100644 index 00000000000..b83951e0fb6 --- /dev/null +++ b/configs/mx6solosabresd_optee_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SOLOSABRESD=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6sx_14x14_lpddr2_arm2_defconfig b/configs/mx6sx_14x14_lpddr2_arm2_defconfig new file mode 100644 index 00000000000..f8f1270a496 --- /dev/null +++ b/configs/mx6sx_14x14_lpddr2_arm2_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_14X14_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-arm2.dtb" +CONFIG_LPDDR2_BOARD=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_14x14_lpddr2_arm2_nand_defconfig b/configs/mx6sx_14x14_lpddr2_arm2_nand_defconfig new file mode 100644 index 00000000000..3fff0694c3e --- /dev/null +++ b/configs/mx6sx_14x14_lpddr2_arm2_nand_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_14X14_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-arm2.dtb" +CONFIG_NAND_BOOT=y +CONFIG_LPDDR2_BOARD=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6sx_14x14_lpddr2_arm2_plugin_defconfig b/configs/mx6sx_14x14_lpddr2_arm2_plugin_defconfig new file mode 100644 index 00000000000..69cee04690a --- /dev/null +++ b/configs/mx6sx_14x14_lpddr2_arm2_plugin_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_14X14_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-arm2.dtb" +CONFIG_LPDDR2_BOARD=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_arm2_defconfig b/configs/mx6sx_17x17_arm2_defconfig new file mode 100644 index 00000000000..16e1de52072 --- /dev/null +++ b/configs/mx6sx_17x17_arm2_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_17X17_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_arm2_eimnor_defconfig b/configs/mx6sx_17x17_arm2_eimnor_defconfig new file mode 100644 index 00000000000..2a399c6debd --- /dev/null +++ b/configs/mx6sx_17x17_arm2_eimnor_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_17X17_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_ENV_IS_IN_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6sx_17x17_arm2_nand_defconfig b/configs/mx6sx_17x17_arm2_nand_defconfig new file mode 100644 index 00000000000..e028ba3e232 --- /dev/null +++ b/configs/mx6sx_17x17_arm2_nand_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_17X17_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-arm2-gpmi-weim" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6sx_17x17_arm2_plugin_defconfig b/configs/mx6sx_17x17_arm2_plugin_defconfig new file mode 100644 index 00000000000..98a4243cc61 --- /dev/null +++ b/configs/mx6sx_17x17_arm2_plugin_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_17X17_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_arm2_qspi2_defconfig b/configs/mx6sx_17x17_arm2_qspi2_defconfig new file mode 100644 index 00000000000..e5a07e22c5a --- /dev/null +++ b/configs/mx6sx_17x17_arm2_qspi2_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_17X17_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_arm2_spinor_defconfig b/configs/mx6sx_17x17_arm2_spinor_defconfig new file mode 100644 index 00000000000..32032cf5e69 --- /dev/null +++ b/configs/mx6sx_17x17_arm2_spinor_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_17X17_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-arm2-ecspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" +CONFIG_SPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6sx_17x17wp_arm2_defconfig b/configs/mx6sx_17x17wp_arm2_defconfig new file mode 100644 index 00000000000..250b67d7bea --- /dev/null +++ b/configs/mx6sx_17x17wp_arm2_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_17X17_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage_wp.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_arm2_defconfig b/configs/mx6sx_19x19_ddr3_arm2_defconfig new file mode 100644 index 00000000000..8df2baef4f6 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_arm2_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_19X19_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_arm2_eimnor_defconfig b/configs/mx6sx_19x19_ddr3_arm2_eimnor_defconfig new file mode 100644 index 00000000000..99681c8e57c --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_arm2_eimnor_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_19X19_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_ENV_IS_IN_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6sx_19x19_ddr3_arm2_nand_defconfig b/configs/mx6sx_19x19_ddr3_arm2_nand_defconfig new file mode 100644 index 00000000000..6fce155f585 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_arm2_nand_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_19X19_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-arm2-gpmi-weim" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6sx_19x19_ddr3_arm2_plugin_defconfig b/configs/mx6sx_19x19_ddr3_arm2_plugin_defconfig new file mode 100644 index 00000000000..8801c33cfed --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_arm2_plugin_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_19X19_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_arm2_qspi2_defconfig b/configs/mx6sx_19x19_ddr3_arm2_qspi2_defconfig new file mode 100644 index 00000000000..a57bc5758d7 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_arm2_qspi2_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_19X19_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_arm2_spinor_defconfig b/configs/mx6sx_19x19_ddr3_arm2_spinor_defconfig new file mode 100644 index 00000000000..cf0a3162644 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_arm2_spinor_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_19X19_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +CONFIG_SPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6sx_19x19_lpddr2_arm2_defconfig b/configs/mx6sx_19x19_lpddr2_arm2_defconfig new file mode 100644 index 00000000000..a48de3a0122 --- /dev/null +++ b/configs/mx6sx_19x19_lpddr2_arm2_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_19X19_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg" +CONFIG_LPDDR2_BOARD=y +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_lpddr2_arm2_plugin_defconfig b/configs/mx6sx_19x19_lpddr2_arm2_plugin_defconfig new file mode 100644 index 00000000000..cabf23e7c40 --- /dev/null +++ b/configs/mx6sx_19x19_lpddr2_arm2_plugin_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_19X19_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg" +CONFIG_LPDDR2_BOARD=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_lpddr2_arm2_qspi2_defconfig b/configs/mx6sx_19x19_lpddr2_arm2_qspi2_defconfig new file mode 100644 index 00000000000..6e3abbe3cba --- /dev/null +++ b/configs/mx6sx_19x19_lpddr2_arm2_qspi2_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SX_19X19_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg" +CONFIG_QSPI_BOOT=y +CONFIG_LPDDR2_BOARD=y +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 2ea2877b5c5..49b8f2604b4 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -1,17 +1,18 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_MX6SXSABREAUTO=y -# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" -CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y @@ -34,6 +35,8 @@ CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_NAND=y CONFIG_NAND_MXS=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y @@ -46,9 +49,32 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6sxsabreauto_nand_defconfig b/configs/mx6sxsabreauto_nand_defconfig new file mode 100644 index 00000000000..c34c451de85 --- /dev/null +++ b/configs/mx6sxsabreauto_nand_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SXSABREAUTO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y + +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sxsabreauto_optee_defconfig b/configs/mx6sxsabreauto_optee_defconfig new file mode 100644 index 00000000000..84a1bfacb17 --- /dev/null +++ b/configs/mx6sxsabreauto_optee_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SXSABREAUTO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_IMX_OPTEE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6sxsabreauto_plugin_defconfig b/configs/mx6sxsabreauto_plugin_defconfig new file mode 100644 index 00000000000..6955a13c5c3 --- /dev/null +++ b/configs/mx6sxsabreauto_plugin_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SXSABREAUTO=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/mx6sxsabreauto_qspi1_defconfig b/configs/mx6sxsabreauto_qspi1_defconfig new file mode 100644 index 00000000000..5a2d1390ba9 --- /dev/null +++ b/configs/mx6sxsabreauto_qspi1_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SXSABREAUTO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 2856a7fd8a4..6fc11ff781a 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -1,19 +1,20 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_MX6SXSABRESD=y -# CONFIG_CMD_BMODE is not set CONFIG_NXP_BOARD_REVISION=y CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" +CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SUPPORT_RAW_INITRD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_PCI=y @@ -25,6 +26,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -34,8 +36,12 @@ CONFIG_OF_CONTROL=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PCI=y CONFIG_PINCTRL=y @@ -52,3 +58,24 @@ CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y + +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6sxsabresd_emmc_defconfig b/configs/mx6sxsabresd_emmc_defconfig new file mode 100644 index 00000000000..0816b054c8f --- /dev/null +++ b/configs/mx6sxsabresd_emmc_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_NXP_BOARD_REVISION=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb-emmc" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" +CONFIG_MX6SXSABRESD_EMMC_REWORK=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHYLIB=y +CONFIG_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y + +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6sxsabresd_m4fastup_defconfig b/configs/mx6sxsabresd_m4fastup_defconfig new file mode 100644 index 00000000000..c5f25a2ba52 --- /dev/null +++ b/configs/mx6sxsabresd_m4fastup_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_NXP_BOARD_REVISION=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,SYS_AUXCORE_FASTUP" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PHYLIB=y +CONFIG_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y + +CONFIG_DM_ETH=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sxsabresd_optee_defconfig b/configs/mx6sxsabresd_optee_defconfig new file mode 100644 index 00000000000..dea2f2576d0 --- /dev/null +++ b/configs/mx6sxsabresd_optee_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_NXP_BOARD_REVISION=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_IMX_OPTEE=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHYLIB=y +CONFIG_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y + +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6sxsabresd_plugin_defconfig b/configs/mx6sxsabresd_plugin_defconfig new file mode 100644 index 00000000000..a56f586c63d --- /dev/null +++ b/configs/mx6sxsabresd_plugin_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_NXP_BOARD_REVISION=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHYLIB=y +CONFIG_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y + +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6sxsabresd_qspi2_defconfig b/configs/mx6sxsabresd_qspi2_defconfig new file mode 100644 index 00000000000..3e29f6cb0ec --- /dev/null +++ b/configs/mx6sxsabresd_qspi2_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_NXP_BOARD_REVISION=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHYLIB=y +CONFIG_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y + +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_IMX_BOOTAUX=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_ANDROID_BOOT_IMAGE=y diff --git a/configs/mx6ul_14x14_ddr3_arm2_defconfig b/configs/mx6ul_14x14_ddr3_arm2_defconfig new file mode 100644 index 00000000000..3d60f970eea --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_arm2_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-arm2.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ul_14x14_ddr3_arm2_eimnor_defconfig b/configs/mx6ul_14x14_ddr3_arm2_eimnor_defconfig new file mode 100644 index 00000000000..fb108abcfe7 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_arm2_eimnor_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-arm2.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_NET=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=n diff --git a/configs/mx6ul_14x14_ddr3_arm2_emmc_defconfig b/configs/mx6ul_14x14_ddr3_arm2_emmc_defconfig new file mode 100644 index 00000000000..aac74d6a226 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_arm2_emmc_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-arm2-emmc" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-arm2.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg" +CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ul_14x14_ddr3_arm2_nand_defconfig b/configs/mx6ul_14x14_ddr3_arm2_nand_defconfig new file mode 100644 index 00000000000..df3d20d6481 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_arm2_nand_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-arm2-gpmi-weim" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-arm2.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ul_14x14_ddr3_arm2_plugin_defconfig b/configs/mx6ul_14x14_ddr3_arm2_plugin_defconfig new file mode 100644 index 00000000000..73c9f591ca5 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_arm2_plugin_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-arm2.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ul_14x14_ddr3_arm2_qspi1_defconfig b/configs/mx6ul_14x14_ddr3_arm2_qspi1_defconfig new file mode 100644 index 00000000000..71963ffaa51 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_arm2_qspi1_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-arm2.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg" +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ul_14x14_ddr3_arm2_spinor_defconfig b/configs/mx6ul_14x14_ddr3_arm2_spinor_defconfig new file mode 100644 index 00000000000..a38a0f140d2 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_arm2_spinor_defconfig @@ -0,0 +1,54 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-arm2.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg" +CONFIG_SPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index a9926859b77..b9c2e41e1b2 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -1,24 +1,15 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_MX6UL_14X14_EVK=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -29,19 +20,51 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_FSL_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_evk_emmc_defconfig b/configs/mx6ul_14x14_evk_emmc_defconfig new file mode 100644 index 00000000000..854ab20e587 --- /dev/null +++ b/configs/mx6ul_14x14_evk_emmc_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk-emmc" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_MX6UL_14X14_EVK_EMMC_REWORK=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_evk_nand_defconfig b/configs/mx6ul_14x14_evk_nand_defconfig new file mode 100644 index 00000000000..55291935047 --- /dev/null +++ b/configs/mx6ul_14x14_evk_nand_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk-gpmi-weim" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ul_14x14_evk_optee_defconfig b/configs/mx6ul_14x14_evk_optee_defconfig new file mode 100644 index 00000000000..8a34a9353f3 --- /dev/null +++ b/configs/mx6ul_14x14_evk_optee_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_evk_plugin_defconfig b/configs/mx6ul_14x14_evk_plugin_defconfig new file mode 100644 index 00000000000..f1cd90cab30 --- /dev/null +++ b/configs/mx6ul_14x14_evk_plugin_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_evk_qspi1_defconfig b/configs/mx6ul_14x14_evk_qspi1_defconfig new file mode 100644 index 00000000000..fbfc3a20dcd --- /dev/null +++ b/configs/mx6ul_14x14_evk_qspi1_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_DM_ETH=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_evk_spl_defconfig b/configs/mx6ul_14x14_evk_spl_defconfig new file mode 100644 index 00000000000..a9926859b77 --- /dev/null +++ b/configs/mx6ul_14x14_evk_spl_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_VIDEO=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6ul_14x14_lpddr2_arm2_defconfig b/configs/mx6ul_14x14_lpddr2_arm2_defconfig new file mode 100644 index 00000000000..cd1f76dd41e --- /dev/null +++ b/configs/mx6ul_14x14_lpddr2_arm2_defconfig @@ -0,0 +1,48 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_LPDDR2_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-lpddr2-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-lpddr2-arm2.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ul_14x14_lpddr2_arm2_eimnor_defconfig b/configs/mx6ul_14x14_lpddr2_arm2_eimnor_defconfig new file mode 100644 index 00000000000..2dcdf926bc0 --- /dev/null +++ b/configs/mx6ul_14x14_lpddr2_arm2_eimnor_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_LPDDR2_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-lpddr2-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-lpddr2-arm2.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index a36a872bac2..47952a4cb6a 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -1,24 +1,15 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_MX6UL_9X9_EVK=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg" +CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -29,19 +20,54 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_FSL_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_9x9_evk_optee_defconfig b/configs/mx6ul_9x9_evk_optee_defconfig new file mode 100644 index 00000000000..2b9051132d1 --- /dev/null +++ b/configs/mx6ul_9x9_evk_optee_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_9x9_evk_plugin_defconfig b/configs/mx6ul_9x9_evk_plugin_defconfig new file mode 100644 index 00000000000..20e45f4f675 --- /dev/null +++ b/configs/mx6ul_9x9_evk_plugin_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_9x9_evk_qspi1_defconfig b/configs/mx6ul_9x9_evk_qspi1_defconfig new file mode 100644 index 00000000000..61e38ebca0c --- /dev/null +++ b/configs/mx6ul_9x9_evk_qspi1_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg" +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_DM_ETH=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_9x9_evk_spl_defconfig b/configs/mx6ul_9x9_evk_spl_defconfig new file mode 100644 index 00000000000..a36a872bac2 --- /dev/null +++ b/configs/mx6ul_9x9_evk_spl_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_VIDEO=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6ul_nxpu_iopb_defconfig b/configs/mx6ul_nxpu_iopb_defconfig new file mode 100644 index 00000000000..ac4afd108bd --- /dev/null +++ b/configs/mx6ul_nxpu_iopb_defconfig @@ -0,0 +1,33 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_nxpu_iopb/imximage.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_MX6UL_NXPU_IOPB=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_BOOTDELAY=-2 +CONFIG_EFI_PARTITION=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y +CONFIG_AVB_ATX=y diff --git a/configs/mx6ul_nxpu_iopb_trusty_defconfig b/configs/mx6ul_nxpu_iopb_trusty_defconfig new file mode 100644 index 00000000000..46daa24db5e --- /dev/null +++ b/configs/mx6ul_nxpu_iopb_trusty_defconfig @@ -0,0 +1,35 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_nxpu_iopb/imximage.cfg,ANDROID_THINGS_SUPPORT,ARMV7_NONSEC" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_IMX_TRUSTY_OS=y +CONFIG_AVB_ATX=y +CONFIG_TARGET_MX6UL_NXPU_IOPB=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_BOOTDELAY=-2 +CONFIG_EFI_PARTITION=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y + diff --git a/configs/mx6ul_spriot_defconfig b/configs/mx6ul_spriot_defconfig new file mode 100644 index 00000000000..6c597b95b00 --- /dev/null +++ b/configs/mx6ul_spriot_defconfig @@ -0,0 +1,33 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_spriot/imximage.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_MX6UL_SPRIOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_BOOTDELAY=-2 +CONFIG_EFI_PARTITION=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y +CONFIG_AVB_ATX=y diff --git a/configs/mx6ull_14x14_ddr3_arm2_defconfig b/configs/mx6ull_14x14_ddr3_arm2_defconfig new file mode 100644 index 00000000000..b143225663e --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_arm2_defconfig @@ -0,0 +1,55 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ull_14x14_ddr3_arm2_emmc_defconfig b/configs/mx6ull_14x14_ddr3_arm2_emmc_defconfig new file mode 100644 index 00000000000..53cb45b3c0c --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_arm2_emmc_defconfig @@ -0,0 +1,49 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-arm2-emmc" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-arm2.dtb" +CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ull_14x14_ddr3_arm2_epdc_defconfig b/configs/mx6ull_14x14_ddr3_arm2_epdc_defconfig new file mode 100644 index 00000000000..bc262d66b21 --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_arm2_epdc_defconfig @@ -0,0 +1,57 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_LCD=y +CONFIG_MXC_EPDC=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-arm2-epdc" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ull_14x14_ddr3_arm2_nand_defconfig b/configs/mx6ull_14x14_ddr3_arm2_nand_defconfig new file mode 100644 index 00000000000..f3cc16f3b4a --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_arm2_nand_defconfig @@ -0,0 +1,49 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-arm2-gpmi-weim" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-arm2.dtb" +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ull_14x14_ddr3_arm2_plugin_defconfig b/configs/mx6ull_14x14_ddr3_arm2_plugin_defconfig new file mode 100644 index 00000000000..d78d4bc319f --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_arm2_plugin_defconfig @@ -0,0 +1,56 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-arm2.dtb" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ull_14x14_ddr3_arm2_qspi1_defconfig b/configs/mx6ull_14x14_ddr3_arm2_qspi1_defconfig new file mode 100644 index 00000000000..80bececc375 --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_arm2_qspi1_defconfig @@ -0,0 +1,56 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-arm2.dtb" +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ull_14x14_ddr3_arm2_spinor_defconfig b/configs/mx6ull_14x14_ddr3_arm2_spinor_defconfig new file mode 100644 index 00000000000..5cd62015030 --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_arm2_spinor_defconfig @@ -0,0 +1,54 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-arm2.dtb" +CONFIG_SPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ull_14x14_ddr3_arm2_tsc_defconfig b/configs/mx6ull_14x14_ddr3_arm2_tsc_defconfig new file mode 100644 index 00000000000..54772f7dab3 --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_arm2_tsc_defconfig @@ -0,0 +1,51 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-arm2-tsc" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-arm2.dtb" +CONFIG_MX6ULL_DDR3_ARM2_TSC_REWORK=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 375db54a757..2d9618c83c3 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -1,26 +1,30 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_VIDEO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" -CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y +CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM_GPIO=y @@ -34,5 +38,32 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_14x14_evk_emmc_defconfig b/configs/mx6ull_14x14_evk_emmc_defconfig new file mode 100644 index 00000000000..d056b5ab725 --- /dev/null +++ b/configs/mx6ull_14x14_evk_emmc_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk-emmc" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_14x14_evk_nand_defconfig b/configs/mx6ull_14x14_evk_nand_defconfig new file mode 100644 index 00000000000..38f2dcf304b --- /dev/null +++ b/configs/mx6ull_14x14_evk_nand_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk-gpmi-weim" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y diff --git a/configs/mx6ull_14x14_evk_optee_defconfig b/configs/mx6ull_14x14_evk_optee_defconfig new file mode 100644 index 00000000000..f93e48ac284 --- /dev/null +++ b/configs/mx6ull_14x14_evk_optee_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index ce2271549e6..a2f6f54aaa5 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -1,27 +1,31 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_MX6ULL_14X14_EVK=y CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_VIDEO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" -CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y +CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM_GPIO=y @@ -35,5 +39,32 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_14x14_evk_qspi1_defconfig b/configs/mx6ull_14x14_evk_qspi1_defconfig new file mode 100644 index 00000000000..e4486c3af3f --- /dev/null +++ b/configs/mx6ull_14x14_evk_qspi1_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_9x9_evk_defconfig b/configs/mx6ull_9x9_evk_defconfig new file mode 100644 index 00000000000..b9e6c6ca17f --- /dev/null +++ b/configs/mx6ull_9x9_evk_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_9X9_EVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-9x9-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage_lpddr2.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_9x9_evk_plugin_defconfig b/configs/mx6ull_9x9_evk_plugin_defconfig new file mode 100644 index 00000000000..8aa13480874 --- /dev/null +++ b/configs/mx6ull_9x9_evk_plugin_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_9X9_EVK=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-9x9-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage_lpddr2.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_9x9_evk_qspi1_defconfig b/configs/mx6ull_9x9_evk_qspi1_defconfig new file mode 100644 index 00000000000..3fad8a6e353 --- /dev/null +++ b/configs/mx6ull_9x9_evk_qspi1_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_9X9_EVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-9x9-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage_lpddr2.cfg" +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig new file mode 100644 index 00000000000..370a9c327b2 --- /dev/null +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ulz_14x14_evk_emmc_defconfig b/configs/mx6ulz_14x14_evk_emmc_defconfig new file mode 100644 index 00000000000..5e0f92eb4a2 --- /dev/null +++ b/configs/mx6ulz_14x14_evk_emmc_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk-emmc" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ulz_14x14_evk_nand_defconfig b/configs/mx6ulz_14x14_evk_nand_defconfig new file mode 100644 index 00000000000..9c94dd35c42 --- /dev/null +++ b/configs/mx6ulz_14x14_evk_nand_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk-gpmi-weim" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ulz_14x14_evk_optee_defconfig b/configs/mx6ulz_14x14_evk_optee_defconfig new file mode 100644 index 00000000000..0698c2ae1c7 --- /dev/null +++ b/configs/mx6ulz_14x14_evk_optee_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ulz_14x14_evk_qspi1_defconfig b/configs/mx6ulz_14x14_evk_qspi1_defconfig new file mode 100644 index 00000000000..31a4bddc0e8 --- /dev/null +++ b/configs/mx6ulz_14x14_evk_qspi1_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_BMP=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7d_12x12_ddr3_arm2_TO_1_1_defconfig b/configs/mx7d_12x12_ddr3_arm2_TO_1_1_defconfig new file mode 100644 index 00000000000..50178bd326b --- /dev/null +++ b/configs/mx7d_12x12_ddr3_arm2_TO_1_1_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_DDR3_ARM2=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-ddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-ddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y diff --git a/configs/mx7d_12x12_ddr3_arm2_defconfig b/configs/mx7d_12x12_ddr3_arm2_defconfig new file mode 100644 index 00000000000..90915332fd4 --- /dev/null +++ b/configs/mx7d_12x12_ddr3_arm2_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_DDR3_ARM2=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-ddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-ddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y diff --git a/configs/mx7d_12x12_lpddr3_arm2_TO_1_1_defconfig b/configs/mx7d_12x12_lpddr3_arm2_TO_1_1_defconfig new file mode 100644 index 00000000000..034e500f4a0 --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_arm2_TO_1_1_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_ARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_arm2_defconfig b/configs/mx7d_12x12_lpddr3_arm2_defconfig new file mode 100644 index 00000000000..7f8d130d0bc --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_arm2_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_ARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_arm2_epdc_defconfig b/configs/mx7d_12x12_lpddr3_arm2_epdc_defconfig new file mode 100644 index 00000000000..c3c6b646d40 --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_arm2_epdc_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_ARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" +CONFIG_LCD=y +CONFIG_MXC_EPDC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_arm2_optee_defconfig b/configs/mx7d_12x12_lpddr3_arm2_optee_defconfig new file mode 100644 index 00000000000..ff6641fa2e5 --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_arm2_optee_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_ARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +CONFIG_IMX_OPTEE=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_arm2_qspi1_defconfig b/configs/mx7d_12x12_lpddr3_arm2_qspi1_defconfig new file mode 100644 index 00000000000..96acf0a7225 --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_arm2_qspi1_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_ARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-arm2-qspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_arm2_spinor_defconfig b/configs/mx7d_12x12_lpddr3_arm2_spinor_defconfig new file mode 100644 index 00000000000..0d355cd5ca6 --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_arm2_spinor_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_ARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-arm2-ecspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_SPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set diff --git a/configs/mx7d_19x19_ddr3_arm2_TO_1_1_defconfig b/configs/mx7d_19x19_ddr3_arm2_TO_1_1_defconfig new file mode 100644 index 00000000000..0519ab7def1 --- /dev/null +++ b/configs/mx7d_19x19_ddr3_arm2_TO_1_1_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_TARGET_MX7D_19X19_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-ddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_ddr3_arm2/imximage_TO_1_1.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-ddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_19x19_ddr3_arm2_defconfig b/configs/mx7d_19x19_ddr3_arm2_defconfig new file mode 100644 index 00000000000..1f126485ddf --- /dev/null +++ b/configs/mx7d_19x19_ddr3_arm2_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_TARGET_MX7D_19X19_DDR3_ARM2=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-ddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-ddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_19x19_lpddr2_arm2_TO_1_1_defconfig b/configs/mx7d_19x19_lpddr2_arm2_TO_1_1_defconfig new file mode 100644 index 00000000000..77f4fb1054e --- /dev/null +++ b/configs/mx7d_19x19_lpddr2_arm2_TO_1_1_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_TARGET_MX7D_19X19_LPDDR2_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr2-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2_TO_1_1.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr2-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y diff --git a/configs/mx7d_19x19_lpddr2_arm2_defconfig b/configs/mx7d_19x19_lpddr2_arm2_defconfig new file mode 100644 index 00000000000..13da6ccdc64 --- /dev/null +++ b/configs/mx7d_19x19_lpddr2_arm2_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_TARGET_MX7D_19X19_LPDDR2_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr2-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr2-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y diff --git a/configs/mx7d_19x19_lpddr3_arm2_TO_1_1_defconfig b/configs/mx7d_19x19_lpddr3_arm2_TO_1_1_defconfig new file mode 100644 index 00000000000..64d27c0acfa --- /dev/null +++ b/configs/mx7d_19x19_lpddr3_arm2_TO_1_1_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_TARGET_MX7D_19X19_LPDDR3_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_lpddr3_arm2/imximage_TO_1_1.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y diff --git a/configs/mx7d_19x19_lpddr3_arm2_defconfig b/configs/mx7d_19x19_lpddr3_arm2_defconfig new file mode 100644 index 00000000000..94591da423f --- /dev/null +++ b/configs/mx7d_19x19_lpddr3_arm2_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_TARGET_MX7D_19X19_LPDDR3_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y diff --git a/configs/mx7d_19x19_lpddr3_arm2_eimnor_defconfig b/configs/mx7d_19x19_lpddr3_arm2_eimnor_defconfig new file mode 100644 index 00000000000..81439ebbac6 --- /dev/null +++ b/configs/mx7d_19x19_lpddr3_arm2_eimnor_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_TARGET_MX7D_19X19_LPDDR3_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_ENV_IS_IN_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set diff --git a/configs/mx7d_19x19_lpddr3_arm2_nand_defconfig b/configs/mx7d_19x19_lpddr3_arm2_nand_defconfig new file mode 100644 index 00000000000..dbfd506753e --- /dev/null +++ b/configs/mx7d_19x19_lpddr3_arm2_nand_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_TARGET_MX7D_19X19_LPDDR3_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index a7f08c5c4fd..18b02f4247c 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -1,19 +1,18 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y -# CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set @@ -22,6 +21,7 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y @@ -73,3 +73,14 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_epdc_defconfig b/configs/mx7dsabresd_epdc_defconfig new file mode 100644 index 00000000000..9b6f3a64da1 --- /dev/null +++ b/configs/mx7dsabresd_epdc_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_MXC_EPDC=y +CONFIG_LCD=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_NET=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_nand_defconfig b/configs/mx7dsabresd_nand_defconfig new file mode 100644 index 00000000000..f6c764418a2 --- /dev/null +++ b/configs/mx7dsabresd_nand_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-gpmi-weim" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_nonsec_defconfig b/configs/mx7dsabresd_nonsec_defconfig new file mode 100644 index 00000000000..553c11553ce --- /dev/null +++ b/configs/mx7dsabresd_nonsec_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_MX7DSABRESD=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +# CONFIG_CMD_BMODE is not set +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_optee_defconfig b/configs/mx7dsabresd_optee_defconfig new file mode 100644 index 00000000000..15635135229 --- /dev/null +++ b/configs/mx7dsabresd_optee_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_secure_defconfig b/configs/mx7dsabresd_plugin_defconfig similarity index 93% rename from configs/mx7dsabresd_secure_defconfig rename to configs/mx7dsabresd_plugin_defconfig index a4cbf963caa..975d344f36e 100644 --- a/configs/mx7dsabresd_secure_defconfig +++ b/configs/mx7dsabresd_plugin_defconfig @@ -1,20 +1,19 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_MX7DSABRESD=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set +CONFIG_USE_IMXIMG_PLUGIN=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y -# CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set @@ -75,3 +74,4 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7dsabresd_qspi1_defconfig b/configs/mx7dsabresd_qspi1_defconfig new file mode 100644 index 00000000000..a783083134d --- /dev/null +++ b/configs/mx7dsabresd_qspi1_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_QSPI_BOOT=y +CONFIG_FSL_QSPI=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_reva_defconfig b/configs/mx7dsabresd_reva_defconfig new file mode 100644 index 00000000000..be54852b4a3 --- /dev/null +++ b/configs/mx7dsabresd_reva_defconfig @@ -0,0 +1,86 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-reva" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_revb_defconfig b/configs/mx7dsabresd_revb_defconfig new file mode 100644 index 00000000000..c3330678fbf --- /dev/null +++ b/configs/mx7dsabresd_revb_defconfig @@ -0,0 +1,86 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage_TO_1_1.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7ulp_10x10_arm2_defconfig b/configs/mx7ulp_10x10_arm2_defconfig new file mode 100644 index 00000000000..ff491447e8d --- /dev/null +++ b/configs/mx7ulp_10x10_arm2_defconfig @@ -0,0 +1,48 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_TARGET_MX7ULP_10X10_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-10x10-arm2" +CONFIG_DEFAULT_FDT_FILE="imx7ulp-10x10-arm2.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y diff --git a/configs/mx7ulp_14x14_arm2_defconfig b/configs/mx7ulp_14x14_arm2_defconfig new file mode 100644 index 00000000000..5774f4b84f0 --- /dev/null +++ b/configs/mx7ulp_14x14_arm2_defconfig @@ -0,0 +1,48 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_arm2/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_TARGET_MX7ULP_14X14_ARM2=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-14x14-arm2" +CONFIG_DEFAULT_FDT_FILE="imx7ulp-14x14-arm2.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index 57c5ebf0753..dcc2d7dc51a 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -2,14 +2,18 @@ CONFIG_ARM=y CONFIG_ARCH_MX7ULP=y CONFIG_SYS_TEXT_BASE=0x67800000 CONFIG_TARGET_MX7ULP_EVK=y -CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi" +CONFIG_DEFAULT_FDT_FILE="imx7ulp-evk" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y @@ -18,6 +22,7 @@ CONFIG_IMX_RGPIO2P=y # CONFIG_MXC_GPIO is not set CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SYS_I2C_IMX_LPI2C=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y CONFIG_DM_REGULATOR=y @@ -25,3 +30,36 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_VIDEO=y +CONFIG_IMX_NORTHWEST_MIPI_DSI=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x60800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_CMD_READ=y diff --git a/configs/mx7ulp_evk_emmc_defconfig b/configs/mx7ulp_evk_emmc_defconfig new file mode 100644 index 00000000000..52884057007 --- /dev/null +++ b/configs/mx7ulp_evk_emmc_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-emmc" +CONFIG_DEFAULT_FDT_FILE="imx7ulp-evk-emmc" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_VIDEO=y +CONFIG_IMX_NORTHWEST_MIPI_DSI=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x60800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_CMD_READ=y diff --git a/configs/mx7ulp_evk_m4boot_defconfig b/configs/mx7ulp_evk_m4boot_defconfig new file mode 100644 index 00000000000..4ef9b55b269 --- /dev/null +++ b/configs/mx7ulp_evk_m4boot_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi" +CONFIG_DEFAULT_FDT_FILE="imx7ulp-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_VIDEO=y +CONFIG_IMX_NORTHWEST_MIPI_DSI=y +CONFIG_IMX_M4_BIND=y diff --git a/configs/mx7ulp_evk_optee_defconfig b/configs/mx7ulp_evk_optee_defconfig new file mode 100644 index 00000000000..debae2346c2 --- /dev/null +++ b/configs/mx7ulp_evk_optee_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi" +CONFIG_DEFAULT_FDT_FILE="imx7ulp-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_VIDEO=y +CONFIG_IMX_NORTHWEST_MIPI_DSI=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x60800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y +CONFIG_CMD_READ=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index ab782a095fc..8ea4d88bf77 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -2,13 +2,17 @@ CONFIG_ARM=y CONFIG_ARCH_MX7ULP=y CONFIG_SYS_TEXT_BASE=0x67800000 CONFIG_TARGET_MX7ULP_EVK=y -CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y @@ -17,6 +21,7 @@ CONFIG_IMX_RGPIO2P=y # CONFIG_MXC_GPIO is not set CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SYS_I2C_IMX_LPI2C=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y CONFIG_DM_REGULATOR=y @@ -24,3 +29,20 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_VIDEO=y diff --git a/configs/pico-imx6dl_defconfig b/configs/pico-imx6dl_defconfig new file mode 100644 index 00000000000..a4fadb66e06 --- /dev/null +++ b/configs/pico-imx6dl_defconfig @@ -0,0 +1,40 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6dl/pico-imx6dl.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_PICO_IMX6DL=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_BOOTDELAY=-2 +CONFIG_EFI_PARTITION=y +CONFIG_VIDEO=y +CONFIG_ENV_IS_IN_MMC=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DFU_MMC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/pico-imx7d-trusty_defconfig b/configs/pico-imx7d-trusty_defconfig new file mode 100644 index 00000000000..e7fdf9db1f5 --- /dev/null +++ b/configs/pico-imx7d-trusty_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_PICO_IMX7D=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_IMX_RDC=y +CONFIG_BOOTDELAY=3 +CONFIG_EFI_PARTITION=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_VIDEO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx7d/imximage_512mb.cfg,ANDROID_THINGS_SUPPORT,DDR_MB=512,ARMV7_NONSEC" +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y +CONFIG_AVB_SUPPORT=y +CONFIG_AVB_ATX=y +CONFIG_USE_STDINT=y +CONFIG_LIB_RAND=y +CONFIG_CMD_UUID=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index edfe7257bdd..490a8fcf73f 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -2,35 +2,38 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_PICO_IMX7D=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx7d/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_EFI_PARTITION=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_VIDEO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx7d/imximage_512mb.cfg,ANDROID_THINGS_SUPPORT,DDR_MB=512" CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y -CONFIG_PHYLIB=y +CONFIG_CMD_FS_GENERIC=y CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="FSL" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_OF_LIBFDT=y +CONFIG_AVB_SUPPORT=y +CONFIG_AVB_ATX=y +CONFIG_LIB_RAND=y diff --git a/configs/picosom-imx6ul-trusty_defconfig b/configs/picosom-imx6ul-trusty_defconfig new file mode 100644 index 00000000000..c93d30471d9 --- /dev/null +++ b/configs/picosom-imx6ul-trusty_defconfig @@ -0,0 +1,34 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/picosom-imx6ul/imximage.cfg,ANDROID_THINGS_SUPPORT,ARMV7_NONSEC" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_IMX_TRUSTY_OS=y +CONFIG_AVB_ATX=y +CONFIG_TARGET_PICOSOM_IMX6UL=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_BOOTDELAY=-2 +CONFIG_EFI_PARTITION=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/configs/picosom-imx6ul_defconfig b/configs/picosom-imx6ul_defconfig new file mode 100644 index 00000000000..11df9dff68b --- /dev/null +++ b/configs/picosom-imx6ul_defconfig @@ -0,0 +1,34 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/picosom-imx6ul/imximage.cfg,ANDROID_THINGS_SUPPORT" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_PICOSOM_IMX6UL=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_BOOTDELAY=-2 +CONFIG_EFI_PARTITION=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y +CONFIG_AVB_ATX=y +# CONFIG_EFI_LOADER is not set diff --git a/disk/part_efi.c b/disk/part_efi.c index fb221eec090..b778106449b 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -135,6 +135,25 @@ static int validate_gpt_header(gpt_header *gpt_h, lbaint_t lba, return 0; } +static void prepare_last_lba_gpt_header(struct blk_desc *dev_desc, gpt_header *gpt_h) +{ + uint32_t calc_crc32; + uint64_t val; + + /* recalculate the values for the Backup GPT Header */ + val = le64_to_cpu(gpt_h->my_lba); + gpt_h->my_lba = cpu_to_le64(dev_desc->lba - 1);; + gpt_h->alternate_lba = cpu_to_le64(val); + gpt_h->last_usable_lba = cpu_to_le64(dev_desc->lba - 34); + gpt_h->partition_entry_lba = + cpu_to_le64(le64_to_cpu(gpt_h->last_usable_lba) + 1); + gpt_h->header_crc32 = 0; + + calc_crc32 = efi_crc32((const unsigned char *)gpt_h, + le32_to_cpu(gpt_h->header_size)); + gpt_h->header_crc32 = cpu_to_le32(calc_crc32); +} + static int validate_gpt_entries(gpt_header *gpt_h, gpt_entry *gpt_e) { uint32_t calc_crc32; @@ -145,7 +164,7 @@ static int validate_gpt_entries(gpt_header *gpt_h, gpt_entry *gpt_e) le32_to_cpu(gpt_h->sizeof_partition_entry)); if (calc_crc32 != le32_to_cpu(gpt_h->partition_entry_array_crc32)) { - printf("%s: 0x%x != 0x%x\n", + debug("%s: 0x%x != 0x%x\n", "GUID Partition Table Entry Array CRC is wrong", le32_to_cpu(gpt_h->partition_entry_array_crc32), calc_crc32); @@ -261,8 +280,10 @@ void part_print_efi(struct blk_desc *dev_desc) printf("\tguid:\t%s\n", uuid); } +#if !defined(CONFIG_DUAL_BOOTLOADER) || !defined(CONFIG_SPL_BUILD) /* Remember to free pte */ free(gpt_pte); +#endif return; } @@ -281,14 +302,14 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part, /* This function validates AND fills in the GPT header and PTE */ if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid GPT ***\n", __func__); + debug("%s: *** ERROR: Invalid GPT ***\n", __func__); if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), gpt_head, &gpt_pte) != 1) { printf("%s: *** ERROR: Invalid Backup GPT ***\n", __func__); return -1; } else { - printf("%s: *** Using Backup GPT ***\n", + debug("%s: *** Using Backup GPT ***\n", __func__); } } @@ -297,7 +318,9 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part, !is_pte_valid(&gpt_pte[part - 1])) { debug("%s: *** ERROR: Invalid partition number %d ***\n", __func__, part); +#if !defined(CONFIG_DUAL_BOOTLOADER) || !defined(CONFIG_SPL_BUILD) free(gpt_pte); +#endif return -1; } @@ -324,8 +347,14 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part, debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s\n", __func__, info->start, info->size, info->name); - /* Remember to free pte */ +#if !defined(CONFIG_DUAL_BOOTLOADER) || !defined(CONFIG_SPL_BUILD) + /* Heap memory is very limited in SPL, if the dual bootloader is + * enabled, just load pte to dram instead of oc-ram. In such case, + * this part of memory shouldn't be freed. But in common routine, + * don't forget to free the memory after use. + */ free(gpt_pte); +#endif return 0; } @@ -869,6 +898,58 @@ int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf) return 0; } +int write_backup_gpt_partitions(struct blk_desc *dev_desc, void *buf) +{ + gpt_header *gpt_h; + gpt_entry *gpt_e; + int gpt_e_blk_cnt; + lbaint_t lba; + int cnt; + + if (is_valid_gpt_buf(dev_desc, buf)) + return -1; + + /* determine start of GPT Header in the buffer */ + gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA * + dev_desc->blksz); + + /* determine start of GPT Entries in the buffer */ + gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) * + dev_desc->blksz); + gpt_e_blk_cnt = BLOCK_CNT((le32_to_cpu(gpt_h->num_partition_entries) * + le32_to_cpu(gpt_h->sizeof_partition_entry)), + dev_desc); + + /* write MBR */ + lba = 0; /* MBR is always at 0 */ + cnt = 1; /* MBR (1 block) */ + if (blk_dwrite(dev_desc, lba, cnt, buf) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "MBR", cnt, lba); + return 1; + } + + prepare_last_lba_gpt_header(dev_desc, gpt_h); + + /* write Backup GPT */ + lba = le64_to_cpu(gpt_h->partition_entry_lba); + cnt = gpt_e_blk_cnt; + if (blk_dwrite(dev_desc, lba, cnt, gpt_e) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "Backup GPT Entries", cnt, lba); + return 1; + } + + lba = le64_to_cpu(gpt_h->my_lba); + cnt = 1; /* GPT Header (1 block) */ + if (blk_dwrite(dev_desc, lba, cnt, gpt_h) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "Backup GPT Header", cnt, lba); + return 1; + } + + return 0; +} #endif /* @@ -968,10 +1049,17 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba, } if (validate_gpt_entries(pgpt_head, *pgpt_pte)) { + +#if !defined(CONFIG_DUAL_BOOTLOADER) || !defined(CONFIG_SPL_BUILD) + /* Heap memory is very limited in SPL, if the dual bootloader is + * enabled, just load pte to dram instead of oc-ram. In such case, + * this part of memory shouldn't be freed. But in common routine, + * don't forget to free the memory after use. + */ free(*pgpt_pte); +#endif return 0; } - /* We're done, all's well */ return 1; } @@ -1005,10 +1093,19 @@ static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc, (u32) le32_to_cpu(pgpt_head->sizeof_partition_entry), (ulong)count); - /* Allocate memory for PTE, remember to FREE */ + /* Allocate memory for PTE. + * Heap memory is very limited in SPL, if the dual bootloader is + * enabled, just load pte to dram instead of oc-ram. In such case, + * this part of memory shouldn't be freed. But in common routine, + * don't forget to free the memory after use. + */ if (count != 0) { +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_SPL_BUILD) + pte = (gpt_entry *)CONFIG_SYS_SPL_PTE_RAM_BASE; +#else pte = memalign(ARCH_DMA_MINALIGN, PAD_TO_BLOCKSIZE(count, dev_desc)); +#endif } if (count == 0 || pte == NULL) { @@ -1016,13 +1113,14 @@ static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc, __func__, (ulong)count); return NULL; } - /* Read GPT Entries from device */ blk = le64_to_cpu(pgpt_head->partition_entry_lba); blk_cnt = BLOCK_CNT(count, dev_desc); if (blk_dread(dev_desc, blk, (lbaint_t)blk_cnt, pte) != blk_cnt) { printf("*** ERROR: Can't read GPT Entries ***\n"); +#if !defined(CONFIG_DUAL_BOOTLOADER) || !defined(CONFIG_SPL_BUILD) free(pte); +#endif return NULL; } return pte; diff --git a/doc/README.mxc_hab b/doc/README.mxc_hab deleted file mode 100644 index 75390a505e6..00000000000 --- a/doc/README.mxc_hab +++ /dev/null @@ -1,144 +0,0 @@ -1. High Assurance Boot (HAB) for i.MX CPUs ------------------------------------------- - -To enable the authenticated or encrypted boot mode of U-Boot, it is -required to set the proper configuration for the target board. This -is done by adding the following configuration in the defconfig file: - -CONFIG_SECURE_BOOT=y - -In addition, the U-Boot image to be programmed into the -boot media needs to be properly constructed, i.e. it must contain a -proper Command Sequence File (CSF). - -The CSF itself is generated by the i.MX High Assurance Boot Reference -Code Signing Tool. -https://www.nxp.com/webapp/sps/download/license.jsp?colCode=IMX_CST_TOOL - -More information about the CSF and HAB can be found in the AN4581. -https://www.nxp.com/docs/en/application-note/AN4581.pdf - -We don't want to explain how to create a PKI tree or SRK table as -this is well explained in the Application Note. - -2. Secure Boot on non-SPL targets ---------------------------------- - -On non-SPL targets a singe U-Boot binary is generated, mkimage will -output additional information about "HAB Blocks" which can be used -in the CST to authenticate the U-Boot image (entries in the CSF file). - -Image Type: Freescale IMX Boot Image -Image Ver: 2 (i.MX53/6 compatible) -Data Size: 327680 Bytes = 320.00 kB = 0.31 MB -Load Address: 177ff420 -Entry Point: 17800000 -HAB Blocks: 177ff400 00000000 0004dc00 - ^^^^^^^^ ^^^^^^^^ ^^^^^^^^ - | | | - | | -------- (1) - | | - | ------------------- (2) - | - --------------------------- (3) - -(1) Size of area in file u-boot-dtb.imx to sign - This area should include the IVT, the Boot Data the DCD - and U-Boot itself. -(2) Start of area in u-boot-dtb.imx to sign -(3) Start of area in RAM to authenticate - -CONFIG_SECURE_BOOT currently enables only an additional command -'hab_status' in U-Boot to retrieve the HAB status and events. This -can be useful while developing and testing HAB. - -Commands to generate a signed U-Boot using i.MX HAB CST tool: -# Compile CSF and create signature -cst --o csf-u-boot.bin --i command_sequence_uboot.csf -# Append compiled CSF to Binary -cat u-boot-dtb.imx csf-u-boot.bin > u-boot-signed.imx - -3. Secure Boot on SPL targets ------------------------------ - -This version of U-Boot is able to build a signable version of the SPL -as well as a signable version of the U-Boot image. The signature can -be verified through High Assurance Boot (HAB). - -After building, you need to create a command sequence file and use -i.MX HAB Code Signing Tool to sign both binaries. After creation, -the mkimage tool outputs the required information about the HAB Blocks -parameter for the CSF. During the build, the information is preserved -in log files named as the binaries. (SPL.log and u-boot-ivt.log). - -Example Output of the SPL (imximage) creation: - Image Type: Freescale IMX Boot Image - Image Ver: 2 (i.MX53/6/7 compatible) - Mode: DCD - Data Size: 61440 Bytes = 60.00 kB = 0.06 MB - Load Address: 00907420 - Entry Point: 00908000 - HAB Blocks: 00907400 00000000 0000cc00 - -Example Output of the u-boot-ivt.img (firmware_ivt) creation: - Image Name: U-Boot 2016.11-rc1-31589-g2a4411 - Created: Sat Nov 5 21:53:28 2016 - Image Type: ARM U-Boot Firmware with HABv4 IVT (uncompressed) - Data Size: 352192 Bytes = 343.94 kB = 0.34 MB - Load Address: 17800000 - Entry Point: 00000000 - HAB Blocks: 0x177fffc0 0x0000 0x00054020 - -# Compile CSF and create signature -cst --o csf-u-boot.bin --i command_sequence_uboot.csf -cst --o csf-SPL.bin --i command_sequence_spl.csf -# Append compiled CSF to Binary -cat SPL csf-SPL.bin > SPL-signed -cat u-boot-ivt.img csf-u-boot.bin > u-boot-signed.img - -These two signed binaries can be used on an i.MX in closed -configuration when the according SRK Table Hash has been flashed. - -4. Setup U-Boot Image for Encrypted Boot ----------------------------------------- -An authenticated U-Boot image is used as starting point for -Encrypted Boot. The image is encrypted by i.MX Code Signing -Tool (CST). The CST replaces only the image data of -u-boot-dtb.imx with the encrypted data. The Initial Vector Table, -DCD, and Boot data, remains in plaintext. - -The image data is encrypted with a Encryption Key (DEK). -Therefore, this key is needed to decrypt the data during the -booting process. The DEK is protected by wrapping it in a Blob, -which needs to be appended to the U-Boot image and specified in -the CSF file. - -The DEK blob is generated by an authenticated U-Boot image with -the dek_blob cmd enabled. The image used for DEK blob generation -needs to have the following configurations enabled in Kconfig: - -CONFIG_SECURE_BOOT=y -CONFIG_CMD_DEKBLOB=y - -Note: The encrypted boot feature is only supported by HABv4 or -greater. - -The dek_blob command then can be used to generate the DEK blob of -a DEK previously loaded in memory. The command is used as follows: - -dek_blob -example: dek_blob 0x10800000 0x10801000 192 - -The resulting DEK blob then is used to construct the encrypted -U-Boot image. Note that the blob needs to be transferred back -to the host.Then the following commands are used to construct -the final image. - -cat u-boot-dtb.imx csf-u-boot.bin > u-boot-signed.imx -objcopy -I binary -O binary --pad-to --gap-fill=0x00 \ - u-boot-signed.imx u-boot-signed-pad.bin -cat u-boot-signed-pad.imx DEK_blob.bin > u-boot-encrypted.imx - - NOTE: u-boot-signed.bin needs to be padded to the value - equivalent to the address in which the DEK blob is specified - in the CSF. diff --git a/Documentation/devicetree/bindings/phy/no-op.txt b/doc/device-tree-bindings/phy/no-op.txt similarity index 100% rename from Documentation/devicetree/bindings/phy/no-op.txt rename to doc/device-tree-bindings/phy/no-op.txt diff --git a/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt b/doc/device-tree-bindings/rtc/brcm,brcmstb-waketimer.txt similarity index 100% rename from Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt rename to doc/device-tree-bindings/rtc/brcm,brcmstb-waketimer.txt diff --git a/doc/imx/ahab/csf_examples/csf_boot_image.txt b/doc/imx/ahab/csf_examples/csf_boot_image.txt new file mode 100644 index 00000000000..1f296f09007 --- /dev/null +++ b/doc/imx/ahab/csf_examples/csf_boot_image.txt @@ -0,0 +1,21 @@ +[Header] +Target = AHAB +Version = 1.0 + +[Install SRK] +# SRK table generated by srktool +File = "./release/crts/SRK_1_2_3_4_table.bin" +# Public key certificate in PEM format +Source = "./release/crts/SRK1_sha384_secp384r1_v3_usr_crt.pem" +# Index of the public key certificate within the SRK table (0 .. 3) +Source index = 0 +# Type of SRK set (NXP or OEM) +Source set = OEM +# bitmask of the revoked SRKs +Revocations = 0x0 + +[Authenticate Data] +# Binary to be signed generated by mkimage +File = "flash.bin" +# Offsets = Container header Signature block (printed out by mkimage) +Offsets = 0x400 0x590 diff --git a/doc/imx/ahab/csf_examples/csf_boot_image_sgk.txt b/doc/imx/ahab/csf_examples/csf_boot_image_sgk.txt new file mode 100644 index 00000000000..ec42f4f09ea --- /dev/null +++ b/doc/imx/ahab/csf_examples/csf_boot_image_sgk.txt @@ -0,0 +1,28 @@ +[Header] +Target = AHAB +Version = 1.0 + +[Install SRK] +# SRK table generated by srktool +File = "./release/crts/SRK_1_2_3_4_table.bin" +# Public key certificate in PEM format +Source = "./release/crts/SRK1_sha384_secp384r1_v3_ca_crt.pem" +# Index of the public key certificate within the SRK table (0 .. 3) +Source index = 0 +# Type of SRK set (NXP or OEM) +Source set = OEM +# bitmask of the revoked SRKs +Revocations = 0x0 + +# Optional subordinate SGK key +[Install Certificate] +# Public key certificate in PEM format +File = "./release/crts/SGK1_sha384_secp384r1_v3_usr_crt.pem" +# bitmask of the permissions +Permissions = 0x1 + +[Authenticate Data] +# Binary to be signed generated by mkimage +File = "flash.bin" +# Offsets = Container header Signature block (printed out by mkimage) +Offsets = 0x400 0x590 diff --git a/doc/imx/ahab/csf_examples/csf_linux_img.txt b/doc/imx/ahab/csf_examples/csf_linux_img.txt new file mode 100644 index 00000000000..b5aa5238023 --- /dev/null +++ b/doc/imx/ahab/csf_examples/csf_linux_img.txt @@ -0,0 +1,21 @@ +[Header] +Target = AHAB +Version = 1.0 + +[Install SRK] +# SRK table generated by srktool +File = "./release/crts/SRK_1_2_3_4_table.bin" +# Public key certificate in PEM format +Source = "./release/crts/SRK1_sha384_secp384r1_v3_usr_crt.pem" +# Index of the public key certificate within the SRK table (0 .. 3) +Source index = 0 +# Type of SRK set (NXP or OEM) +Source set = OEM +# bitmask of the revoked SRKs +Revocations = 0x0 + +[Authenticate Data] +# Binary to be signed generated by mkimage +File = "flash_os.bin" +# Offsets = Container header Signature block (printed out by mkimage) +Offsets = 0x0 0x110 diff --git a/doc/imx/ahab/csf_examples/cst_uboot_atf.txt b/doc/imx/ahab/csf_examples/cst_uboot_atf.txt new file mode 100644 index 00000000000..c4d23bcce4b --- /dev/null +++ b/doc/imx/ahab/csf_examples/cst_uboot_atf.txt @@ -0,0 +1,21 @@ +[Header] +Target = AHAB +Version = 1.0 + +[Install SRK] +# SRK table generated by srktool +File = "../crts/SRK_1_2_3_4_table.bin" +# Public key certificate in PEM format on this example only using SRK key +Source = "../crts/SRK1_sha384_secp384r1_v3_usr_crt.pem" +# Index of the public key certificate within the SRK table (0 .. 3) +Source index = 0 +# Type of SRK set (NXP or OEM) +Source set = OEM +# bitmask of the revoked SRKs +Revocations = 0x0 + +[Authenticate Data] +# Binary to be signed generated by mkimage +File = "u-boot-atf-container.img" +# Offsets = Container header Signature block (printed out by mkimage) +Offsets = 0x0 0x110 diff --git a/doc/imx/ahab/guides/mx8_mx8x_secure_boot.txt b/doc/imx/ahab/guides/mx8_mx8x_secure_boot.txt new file mode 100644 index 00000000000..ab292350ac6 --- /dev/null +++ b/doc/imx/ahab/guides/mx8_mx8x_secure_boot.txt @@ -0,0 +1,398 @@ + +=========================================================+ + + i.MX 8, i.MX 8X Secure Boot guide using AHAB + + +=========================================================+ + +1. AHAB secure boot process +---------------------------- + +This document describes a step-by-step procedure on how to sign and +securely boot a flash.bin image. It is assumed that the reader is +familiar with basic AHAB concepts and with the PKI tree generation. + +It is also assumed that the reader is familiar with all pieces of +software needed. The procedure to built SCFW, ATF and download the +firmwares are out of scope of this document, please refer to the Linux +BSP Release Notes and AN12212[1] for further details. + +Details about AHAB can be found in the introduction_ahab.txt document +and in processors Security Reference Manual Document (SRM). + +1.1 Preparing the environment to build a secure boot image +----------------------------------------------------------- + +Before continuing, be sure to have already downloaded and built the +following: + +- imx-mkimage downloaded and built with i.MX 8 container support. +- SECO firmware downloaded. +- U-Boot downloaded and built. Please check section 1.2. +- ARM Trusted Firmware (ATF) downloaded and built for your target. +- System Controller Firmware (SCFW). +- Kernel image. + +You should also have downloaded the Code Signing Tool, available on NXP +website. + +In the following sections, designates the repository where all +parts have been downloaded and built. + +1.2 Preparing U-Boot to support AHAB secure boot features +---------------------------------------------------------- + +The U-Boot provides extra functions for AHAB, such as the ability to +authenticate additional container images by calling the SCU API +sc_misc_seco_authenticate() function. + +The support is enabled by adding CONFIG_AHAB_BOOT to the defconfig file used +for your target: + + - Defconfig: + CONFIG_AHAB_BOOT=y + - Kconfig: + ARM architecture -> Support i.MX 8 AHAB features + +1.3 Building an image supporting secure boot +--------------------------------------------- + +The boot image is composed of different layers: + + +---------------------------+ <-- *start + | 1st Container header | + | and signature | + +---------------------------+ + | Padding for 1kB alignment | + +---------------------------+ <-- *start + 0x400 + | 2nd Container header | + | and signature | + +---------------------------+ + | Padding | + +---------------------------+ + | SECO FW | + +---------------------------+ + | Padding | + +---------------------------+ + | SCU FW with DDR | + | initialization Image | + | embedded | + +---------------------------+ + | Cortex-M4 Image | + +---------------------------+ + | Cortex-A bootloader | + +---------------------------+ + +It contains two containers, one for the SECO firmware (AHAB), and one for +the SCFW, the ATF, U-Boot and M4 Image. They are preceded by their headers. +The first one, containing the SECO firmware image, is padded to 0x1000 to +fix the start address of the second one, which can contain one or multiple +images. + +If you are familiar with secure boot process with HABv4, you will notice +there is no need for CSF in this architecture. The CST is responsible to +handle the Signature block: + + +----------------------------+ ^ + | | | + | | | + | Container header | | + | | | + | | | + +---+------------------------+ | + | S | Signature block header | | Signed + | i +------------------------+ | + | g | | | + | n | | | + | a | SRK table | | + | t | | | + | u | | | + | r +------------------------+ v + | e | Signature | + | +------------------------+ + | b | | + | l | SGK Key | + | o | Certificate (optional) | + | c | | + | k | | + +---+------------------------+ + +The certificate block is divided into: + + +---------------+ ^ + | Public key | | Signed + | Permission | | + +---------------+ v + | Signature | + +---------------+ + +The first block (public key permission) verify the Signature block +preceding (between SRK table and Certificate blocks), while the second +block (signature) is verified by the SRK table block. + +1.4 Prepare the boot image layout +---------------------------------- + +To generate the flash.bin file: + +- On i.MX 8 QXP: + + $ cd /imx-mkimage + $ make SOC=iMX8QX flash + +- On i.MX 8 QM: + + $ cd /imx-mkimage + $ make SOC=iMX8QM flash + +If the command ends successfully, the end of the result should look +like: + + CST: CONTAINER 0 offset: 0x400 + CST: CONTAINER 0: Signature Block: offset is at 0x590 + DONE. + Note: Please copy image to offset: IVT_OFFSET + IMAGE_OFFSET + +Keep in mind the offsets above to be used with CST/CSF. + +Please note that on this example we not including an Cortex-M4 Image, on +i.MX8/8x MEK boards the SCU console may be replaced by the M4 console not +being possible to run the steps documented in section "1.5.5 Verify SECO +events". + +1.5 Secure boot setup with the CST +----------------------------------- + +1.5.1 Creating the CSF description file for the second container +----------------------------------------------------------------- + +The CSF contains all the commands that the AHAB executes during the secure +boot. These commands instruct the AHAB on which memory areas of the image +to authenticate, which keys to install, use and etc. + +CSF examples are available under doc/imx/ahab/csf_examples/ +directory. + +This csf_boot_image.txt file example should be updated with the offset values +of the 1.4 section and the path to your flash.bin file. It is the last part +of the file: + + [Authenticate Data] + # Binary to be signed generated by mkimage + File = "flash.bin" + # Offsets = Container header Signature block (printed out by mkimage) + Offsets = 0x400 0x590 + +1.5.2 Signing the boot image +----------------------------- + +Now you use the CST to generate the signed boot image from the previously +created csf_boot_image.txt Commands Sequence File: + + $ cd + $ ./release/linux64/bin/cst -i csf_boot_image.txt -o flash.signed.bin + +1.5.3 Flash the signed image +----------------------------- + +Write the signed U-Boot image: + + $ sudo dd if=flash.signed.bin of=/dev/sdX bs=1k seek=32 ; sync + +Then insert the SD Card into the board and plug your device to your computer +with an USB serial cable. + +1.5.4 Programming SRK Hash +--------------------------- + +As explained in introduction_ahab.txt document the SRK Hash fuse values are +generated by the srktool and should be programmed in the SoC SRK_HASH[511:0] +fuses. + +Be careful when programming these values, as this data is the basis for the +root of trust. An error in SRK Hash results in a part that does not boot. + +The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs. + +- Dump SRK Hash fuses values in host machine: + + $ od -t x4 SRK_1_2_3_4_fuse.bin + 0000000 d436cc46 8ecccda9 b89e1601 5fada3db + 0000020 d454114a b6cd51f4 77384870 c50ee4b2 + 0000040 a27e5132 eba887cf 592c1e2b bb501799 + 0000060 ee702e07 cf8ce73e fb55e2d5 eba6bbd2 + +- Program SRK_HASH[511:0] fuses: + + * On i.MX 8 QXP: + + => fuse prog 0 730 0xd436cc46 + => fuse prog 0 731 0x8ecccda9 + => fuse prog 0 732 0xb89e1601 + => fuse prog 0 733 0x5fada3db + => fuse prog 0 734 0xd454114a + => fuse prog 0 735 0xb6cd51f4 + => fuse prog 0 736 0x77384870 + => fuse prog 0 737 0xc50ee4b2 + => fuse prog 0 738 0xa27e5132 + => fuse prog 0 739 0xeba887cf + => fuse prog 0 740 0x592c1e2b + => fuse prog 0 741 0xbb501799 + => fuse prog 0 742 0xee702e07 + => fuse prog 0 743 0xcf8ce73e + => fuse prog 0 744 0xfb55e2d5 + => fuse prog 0 745 0xeba6bbd2 + + * On i.MX 8 QM: + + => fuse prog 0 722 0xd436cc46 + => fuse prog 0 723 0x8ecccda9 + => fuse prog 0 724 0xb89e1601 + => fuse prog 0 725 0x5fada3db + => fuse prog 0 726 0xd454114a + => fuse prog 0 727 0xb6cd51f4 + => fuse prog 0 728 0x77384870 + => fuse prog 0 729 0xc50ee4b2 + => fuse prog 0 730 0xa27e5132 + => fuse prog 0 731 0xeba887cf + => fuse prog 0 732 0x592c1e2b + => fuse prog 0 733 0xbb501799 + => fuse prog 0 734 0xee702e07 + => fuse prog 0 735 0xcf8ce73e + => fuse prog 0 736 0xfb55e2d5 + => fuse prog 0 737 0xeba6bbd2 + +1.5.5 Verify SECO events +------------------------- + +If the fuses have been written properly, there should be no SECO events after +boot. To validate this, power on the board, and run ahab_status command on +U-Boot terminal. + +No events should be returned after this command: + + => ahab_status + Lifecycle: 0x0020, NXP closed + + No SECO Events Found! + +U-Boot will decode the SECO events and provide more details on the failure, +for example in case container image was signed with wrong keys and are not +matching the OTP SRK hashes: + + => ahab_status + Lifecycle: 0x0020, NXP closed + + SECO Event[0] = 0x0087EE00 + CMD = AHAB_AUTH_CONTAINER_REQ (0x87) + IND = AHAB_NO_AUTHENTICATION_IND (0xEE) + +Note: In case your SRK fuses are not programmed yet the event 0x0087FA00 may +also be displayed. + +1.5.6 Close the device +----------------------- + +After the device successfully boots a signed image without generating any +SECO security events, it is safe to close the device. The SECO lifecycle +should be changed from 0x20 NXP closed to 0x80 OEM closed. Be aware this +step can damage your board if a previous step failed. It is also +irreversible. Run on the U-Boot terminal: + + => ahab_close + +Now reboot the target, and run: + + => ahab_status + +The lifecycle value should now be 0x80 OEM closed. + +2. Authenticating the OS container +----------------------------------- + +Note that the following section is not mandatory. If you do not plan to +authenticate the kernel image, you can disable this behavior by setting +sec_boot=no in U-Boot environment variable. + +Note, you can also authenticate the OS image by running a U-Boot command: + + => auth_cntr + +2.1 Prepare the OS container image +----------------------------------- + +You need to generate the OS container image. First, copy the binary previously +generated to the directory to save it for later: + +- On i.MX 8 QXP + + $ cd /imx-mkimage + $ cp iMX8QX/flash.bin .. + $ make SOC=iMX8QX flash_linux + $ mv iMX8QX/flash.bin iMX8QX/flash_os.bin + $ cp iMX8QX/flash_os.bin .. + +- On i.MX 8 QM + + $ cd /imx-mkimage + $ cp iMX8QM/flash.bin .. + $ make SOC=iMX8QM flash_linux + $ mv iMX8QM/flash.bin iMX8QM/flash_os.bin + $ cp iMX8QM/flash_os.bin .. + +If the make command ends successfully, the end of the result should look +like: + + CST: CONTAINER 0 offset: 0x0 + CST: CONTAINER 0: Signature Block: offset is at 0x110 + DONE. + Note: Please copy image to offset: IVT_OFFSET + IMAGE_OFFSET + +Keep in mind the offsets above to be used with CST/CSF + +2.2 Creating the CSF description file for OS container image +------------------------------------------------------------- + +CSF examples are available under doc/imx/ahab/csf_examples/ +directory. + +This csf_linux_img.txt file example should be updated with the offset values +of the 2.1 chapter and the path to your flash_os.bin file. It it the last +part of the file: + + [Authenticate Data] + # Binary to be signed generated by mkimage + File = "flash_os.bin" + # Offsets = Container header Signature block (printed out by mkimage) + Offsets = 0x0 0x110 + +2.3 Authenticating container image +----------------------------------- + +Now you use the CST to signed the OS image using the previously +created csf_linux_img.txt Commands Sequence File: + + $ cd + $ ./release/linux64/bin/cst -i csf_linux_img.txt -o os_cntr_signed.bin + +2.4 Copy OS container +---------------------- + +Mount the SD Card: + + $ sudo mount /dev/sdX1 partition + +Copy the OS signed image on the SD Card: + +- For i.MX 8 QXP + + $ sudo cp os_cntr_signed.bin /media/UserID/Boot\ imx8qx + +- For i.MX 8 QM + + $ sudo cp os_cntr_signed.bin /media/UserID/Boot\ imx8qm + +Finally: + + $ sudo umount partition + +References: +[1] AN12212: "Software Solutions for Migration Guide from Aarch32 to + Aarch64" - Rev 0." diff --git a/doc/imx/ahab/guides/mx8_mx8x_spl_secure_boot.txt b/doc/imx/ahab/guides/mx8_mx8x_spl_secure_boot.txt new file mode 100644 index 00000000000..a3f595078de --- /dev/null +++ b/doc/imx/ahab/guides/mx8_mx8x_spl_secure_boot.txt @@ -0,0 +1,358 @@ + +=========================================================+ + + i.MX 8, i.MX 8X AHAB guide on SPL targets + + +=========================================================+ + +1. AHAB secure boot process +---------------------------- + +This document provides a step-by-step guide on how securely boot a flash.bin +image generated by Secondary Program Loader (SPL) targets. It is assumed that +the reader is familiar with basic AHAB concepts and with the PKI tree +generation. + +Details about AHAB can be found in the introduction_ahab.txt document and in +processors Security Reference Manual Document (SRM). + +1.1 Preparing the environment to build a secure boot image +----------------------------------------------------------- + +The following files and projects are used to prepare a secure boot image +for i.MX8/8x device: + +- imx-mkimage. +- SECO Firmware. +- U-Boot proper and SPL. (Please refer to section 1.2) +- ARM Trusted Firmware (ATF). +- System Controller Firmware (SCFW). +- Cortex M binary. (Optional) +- Kernel image. (Optional) +- Code signing tools (CST). + +The procedure to download the SECO firmware and build U-Boot, SCFW and ATF are +out of the scope of this document, please refer to the Linux BSP Release Notes +and AN12212[1] for further details. + +1.2 Preparing U-Boot to support AHAB secure boot features +---------------------------------------------------------- + +The U-Boot provides an alternative SPL target for i.MX8 and i.MX8x devices. The +SPL is intended to be used by applications that requires a initial bootloader +prior to initialize the ARM Trusted Firmware (ATF) and the U-Boot proper. + +The U-Boot support AHAB functions that are essential to completely authenticate +the flash.bin image. On SPL targets only the SCFW, SPL and M4 IMG are +authenticated at SCU ROM level, in order to authenticate the ATF and U-Boot +proper it's necessary to call the SCU API sc_misc_seco_authenticate() function +at SPL level. + +The support is enabled by adding CONFIG_AHAB_BOOT to the defconfig file used +by your target: + + - Defconfig: + CONFIG_AHAB_BOOT=y + - Kconfig: + ARM architecture -> Support i.MX 8 AHAB features + +1.3 Building a SPL image supporting secure boot +------------------------------------------------ + +The boot image generated by SPL targets has three containers: + + +---------------------------+ --------- + | 1st Container header | ^ + | and signature | | + +---------------------------+ | + | Padding for 1kB alignment | | + +---------------------------+ | + | 2nd Container header | | + | and signature | | + +---------------------------+ | + | Padding | | Authenticated at + +---------------------------+ | SCU ROM Level + | SECO FW | | + +---------------------------+ | + | Padding | | + +---------------------------+ | + | SCU FW + DCD Table | | + +---------------------------+ | + | Cortex-M Image | | + +---------------------------+ | + | SPL Image | v + +---------------------------+ --------- + | 3rd Container header | ^ + | and signature | | + +---------------------------+ | + | Padding | | Authenticated + +---------------------------+ | at SPL Level + | U-Boot Proper IMG | | + +---------------------------+ | + | ARM Trusted FW (ATF) | v + +---------------------------+ --------- + +The first container includes the SECO firmware which is signed using NXP keys, +this container is authenticated by SECO ROM at SCU ROM level. + +The second container includes the SCFW, SPL and Cortex M SW images which are +signed using OEM keys, this container is authenticated by SECO FW at SCU ROM +level. + +The third container includes the U-Boot proper and the ATF. The SPL is in +charge to load this container and also to interface with SCU requesting +SECO FW to authenticate the additional container. + +The signing procedure is slightly different when compared with HABv4 series. On +AHAB the signature is directly included in the container, the CST is +responsible to sign and handle the "Signature Block": + + +----------------------------+ --------- + | | ^ + | | | + | Container header | | + | | | + | | | + +---+----------------------- + | + | S | Signature block header | | Signed + | i +------------------------+ | + | g | | | + | n | | | + | a | SRK table | | + | t | | | + | u | | v + | r +------------------------+ --------- + | e | Signature | + | +------------------------+ + | B | | + | l | SGK Key | + | o | Certificate (optional) | + | c | | + | k | | + +---+------------------------+ + +In case using the optional subordinate SGK key, the container signature is +verified against the SGK key certificate. This certificate is verified +against the SRK table. + +In case not using the subordinate key, the container signature is verified +against the SRK keys directly. + +1.4 Preparing the boot image +----------------------------- + +1.4.1 Preparing the 3rd container +---------------------------------- + +The first step is to generate the third container including the U-Boot proper +and ATF images. + +The imx-mkimage project includes a target which only generates this third +container: + +- Generating the U-Boot proper + ATF container: + + $ make SOC= u-boot-atf-container.img + +The mkimage log provides the container and signature block offsets used by the +CSF description file: + + CST: CONTAINER 0 offset: 0x0 + CST: CONTAINER 0: Signature Block: offset is at 0x110 + +The u-boot-atf-container.img file is the third container which have to be +signed using the Code Signing Tool (CST). + +1.4.2 Signing the 3rd container +-------------------------------- + +The CSF description file contains all the commands that the SECO executes +during the secure boot procedure. These commands instruct the AHAB code on +which memory areas of the image to authenticate, which keys to install, use +and etc. + +CSF examples are available under doc/imx/ahab/csf_examples/ directory. + +As explained in section above the mkimage log provides the container and +signature block offsets used by the CSF description file: + +- "Authenticate Data" command in cst_uboot_atf.txt file: + + [Authenticate Data] + # Binary to be signed generated by mkimage + File = "u-boot-atf-container.img" + # Offsets = Container header Signature block + Offsets = 0x0 0x110 + +- Sign the third container: + + $ ./cst -i cst_uboot_atf.txt -o signed-u-boot-atf-container.img + +The signed-u-boot-atf-container.img have to be copied to imx-mkimage directory +and renamed to u-boot-atf-container.img. + +1.4.3 Preparing the flash.bin image +------------------------------------ + +The signed 3rd container can be now used to create the final flash.bin image, +be sure that your signed container were successfully replaced and is named +as u-boot-atf-container.img. + +- Generating the flash.bin image: + + $ make SOC= flash_spl_container + +The mkimage log provides the container and signature block offsets used by the +CSF description file: + + CST: CONTAINER 0 offset: 0x400 + CST: CONTAINER 0: Signature Block: offset is at 0x510 + +The flash.bin file include three containers and the second container have to be +signed using the Code Signing Tool (CST). + +1.4.4 Signing the flash.bin image +---------------------------------- + +As mentioned above the CSF description file contains all the commands that +the SECO executes during the secure boot procedure. + +The procedure for signing the flash.bin image is similar as documented in +mx8_mx8x_secure_boot.txt guide. + +- "Authenticate Data" command in csf_boot_image.txt file: + + [Authenticate Data] + # Binary to be signed generated by mkimage + File = "flash.bin" + # Offsets = Container header Signature block + Offsets = 0x400 0x510 + +- Sign the flash.bin container: + + $ ./cst -i csf_boot_image.txt -o signed-flash.bin + +The signed-flash.bin image contains all the signatures and can be flashed in +the device. + +1.5 Flashing the signed image +------------------------------ + +After completing all steps in section "1.4 Preparing the boot image" the +signed flash.bin image can be flashed in the device: + + $ sudo dd if=signed-flash.bin of=/dev/sd bs=1k seek=32 && sync + +1.6 Programming SRK Hash +------------------------- + +As explained in introduction_ahab.txt document the SRK Hash fuse values are +generated by the srktool and should be programmed in the SoC SRK_HASH[511:0] +fuses. + +Be careful when programming these values, as this data is the basis +for the root of trust. An error in SRK Hash results in a part that +does not boot. + +The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs. + +- Dump SRK Hash fuses values in host machine: + + $ od -t x4 SRK_1_2_3_4_fuse.bin + 0000000 d436cc46 8ecccda9 b89e1601 5fada3db + 0000020 d454114a b6cd51f4 77384870 c50ee4b2 + 0000040 a27e5132 eba887cf 592c1e2b bb501799 + 0000060 ee702e07 cf8ce73e fb55e2d5 eba6bbd2 + +- Program SRK_HASH[511:0] fuses: + + * On i.MX 8 QXP: + + => fuse prog 0 730 0xd436cc46 + => fuse prog 0 731 0x8ecccda9 + => fuse prog 0 732 0xb89e1601 + => fuse prog 0 733 0x5fada3db + => fuse prog 0 734 0xd454114a + => fuse prog 0 735 0xb6cd51f4 + => fuse prog 0 736 0x77384870 + => fuse prog 0 737 0xc50ee4b2 + => fuse prog 0 738 0xa27e5132 + => fuse prog 0 739 0xeba887cf + => fuse prog 0 740 0x592c1e2b + => fuse prog 0 741 0xbb501799 + => fuse prog 0 742 0xee702e07 + => fuse prog 0 743 0xcf8ce73e + => fuse prog 0 744 0xfb55e2d5 + => fuse prog 0 745 0xeba6bbd2 + + * On i.MX 8 QM: + + => fuse prog 0 722 0xd436cc46 + => fuse prog 0 723 0x8ecccda9 + => fuse prog 0 724 0xb89e1601 + => fuse prog 0 725 0x5fada3db + => fuse prog 0 726 0xd454114a + => fuse prog 0 727 0xb6cd51f4 + => fuse prog 0 728 0x77384870 + => fuse prog 0 729 0xc50ee4b2 + => fuse prog 0 730 0xa27e5132 + => fuse prog 0 731 0xeba887cf + => fuse prog 0 732 0x592c1e2b + => fuse prog 0 733 0xbb501799 + => fuse prog 0 734 0xee702e07 + => fuse prog 0 735 0xcf8ce73e + => fuse prog 0 736 0xfb55e2d5 + => fuse prog 0 737 0xeba6bbd2 + +1.7 Verify SECO events +----------------------- + +If the fuses have been written properly, there should be no SECO events after +boot. To validate this, power on the board, and run ahab_status command on +U-Boot terminal. + +No events should be returned after this command: + + => ahab_status + Lifecycle: 0x0020, NXP closed + + No SECO Events Found! + +U-Boot will decode the SECO events and provide more details on the failure, +for example in case container image was signed with wrong keys and are not +matching the OTP SRK hashes: + + => ahab_status + Lifecycle: 0x0020, NXP closed + + SECO Event[0] = 0x0087EE00 + CMD = AHAB_AUTH_CONTAINER_REQ (0x87) + IND = AHAB_NO_AUTHENTICATION_IND (0xEE) + +Note: In case your SRK fuses are not programmed yet the event 0x0087FA00 may +also be displayed. + +1.8 Close the device +--------------------- + +After the device successfully boots a signed image without generating any +SECO security events, it is safe to close the device. The SECO lifecycle +should be changed from 0x20 NXP closed to 0x80 OEM closed. Be aware this +step can damage your board if a previous step failed. It is also +irreversible. Run on the U-Boot terminal: + + => ahab_close + +Now reboot the target, and run: + + => ahab_status + +The lifecycle value should now be 0x80 OEM closed. + +2. Authenticating the OS container +----------------------------------- + +The procedure for authenticating the OS container is similar as in Non-SPL +targets, for a complete procedure please refer to mx8_mx8x_secure_boot.txt +document available under doc/imx/ahab/guides/ directory. + +References: +[1] AN12212: "Software Solutions for Migration Guide from Aarch32 to + Aarch64" - Rev 0." diff --git a/doc/imx/ahab/introduction_ahab.txt b/doc/imx/ahab/introduction_ahab.txt new file mode 100644 index 00000000000..bc3406014d6 --- /dev/null +++ b/doc/imx/ahab/introduction_ahab.txt @@ -0,0 +1,304 @@ + +=======================================================+ + + i.MX8/8x AHAB Secure Boot introduction + + +=======================================================+ + +1. Introduction +---------------- + +The i.MX8 and i.MX8x family of applications processors introduce a new +secure boot concept. Due to the multi-core architecture the Security +Controller (SECO) and System Control Unit (SCU) are heavily involved in +the secure boot process. + +Step-by-step guides are available under doc/imx/ahab/guides/ directory, +users familiar with AHAB architecture and CST PKI tree generation should +refer to this directory instead. + +1.1 The AHAB Secure Boot Architecture +-------------------------------------- + +The Advanced High Assurance Boot (AHAB) feature relies in digital signatures to +prevent unauthorized software execution during the device boot sequence. In +case a malware takes control of the boot sequence, sensitive data, services and +network can be impacted. + +The AHAB authentication is based on public key cryptography in which image +data is signed offline using one or more private keys. The resulting signed +image data is then verified on the i.MX processor using the corresponding +public keys. The public keys are included in the final binary and the SRK +Hash is programmed in the SoC fuses for establishing the root of trust. + +In i.MX8 and i.MX8x families the SCU is responsible to interface with the boot +media, managing the process of loading the firmware and software images in +different partitions of the SoC. The SECO is responsible to authenticate the +images and authorize the execution of them. + +1.1.1 The System Control Unit (SCU) +------------------------------------ + +The System Control Unit SCU is a subsystem equipped with a programmable M4 +core, which is responsible to handle the resource allocation, power, clocking, +IO configuration and muxing. + +The SCU is also responsible to interface between the rest of the system. In the +secure boot flow the SCU interfaces with the Security Controller (SECO), +requesting the image authentication. + +The System Control Unit FW (SCFW) is responsible to control all the +functionalities of the SCU. This firmware is distributed in a porting kit form. +Instructions to download the SCFW Porting Kit are available in the Linux BSP +Release Notes. + +Details about SCU can be found in the processors Reference Manual (RM). + +1.1.2 The Security Controller (SECO) +------------------------------------- + +The SECO is a M0+ core dedicated to handle the SoC security subsystem. The +controller communicates with SCU domain through a dedicate message unit (MU). + +The SECO has a dedicate ROM which is responsible to initialize low level +security features and to authenticate the SECO firmware previously loaded by +the SCU ROM. + +The SECO firmware provides security services at run-time to different domains +of the SoC, one of these being the capability of authenticate images. + +The SECO firmware is signed and distributed by NXP and is always authenticated +in OEM open and closed configuration, instructions to download the SECO FW are +available in the Linux BSP Release Notes. + +Details about SECO can be found in the processors Security Reference Manual +(SRM). + +1.2 The image container +------------------------ + +Due to the new the architecture, multiple firmwares and softwares are required +to boot i.MX8 and i.MX8x family devices. In order to store all the images in a +single binary the container image structure is used. + +At least two containers are needed for the boot process, the first container +must include only the SECO FW (provided by NXP). Additional containers can +contain one or multiple images, depending on the users specific application. + +The final binary is generated by the imx-mkimage tool. The tool can generate +additional containers and also combine all containers in a single binary. + +1.3 The i.MX8/8x secure boot flow +---------------------------------- + +As mentioned in the introduction, due to the multiple cores architecture the +i.MX8 boot sequence involves SCU ROM, SCFW, SECO ROM, and SECO FW. + +The diagram below illustrate the secure boot flow overview: + +System Controller │ Security Controller │ Cortex-M │ Cortex-A + (SCU) │ (SECO) │ │ + │ │ │ + ╔═════════════╗ │ ╔═════════════╗ ┌───────────┐ ┌─────────┐ + ║ SCU INIT ║ │ ║ SECO INIT ║ │ │ │ │ │ │ + ╚══════╤══════╝ │ ╚══════╤══════╝ │ │ v │ │ v + │ │ │ │ │ ┌──────────┐ │ │ ┌────────────┐ + ╔══════╧══════╗ │ │ │ │ │ Start M4 │ │ │ │ Start AP │ + ║Load SECO FW ║ │ │ │ │ │ IMG │ │ │ │ IMG │ + ╚══════╤══════╝ │ ╔══════╧══════╗ │ │ └──────────┘ │ │ └─────┬──────┘ + ├──────────────>║Auth SECO FW ║ │ │ │ │ │ + ╔══════╧══════╗ │ ╚══════╤══════╝ │ │ ┌────────────┘ │ │ + ║ Load SCU FW ║ │ │ │ │ │ │ │ + ║ and DCD ║ │ │ │ │ │ │ ┌─────┴──────┐ + ╚══════╤══════╝ │ ┌──────┴──────┐ │ │ │ │ │ Load │ + ├──────────────>│ Auth SCU FW │ │ │ │ │ │ Add AP IMG │ + │ │ │ and DCD │ │ │ │ │ └─────┬──────┘ + ╔══════╧══════╗ │ └──────┬──────┘ │ │ │ │ │ + ║ Run DCD ║<──────────────┤ │ │ │ │ │ + ╚══════╤══════╝ │ │ │ │ │ ┌───────────────┤ + │ │ │ │ │ │ │ │ │ + ╔══════╧══════╗ │ │ │ │ │ │ │ │ + ║ Load M4 IMG ║ │ │ │ │ │ │ │ │ + ╚══════╤══════╝ │ ┌──────┴──────┐ │ │ │ │ │ │ + ├──────────────>│ Auth M4 IMG │ │ │ │ │ │ │ + ╔══════╧══════╗ │ └──────┬──────┘ │ │ │ │ │ ┌─────┴──────┐ + ║ Load AP IMG ║ │ │ │ │ │ │ │ │ Run │ + ╚══════╤══════╝ │ ┌──────┴──────┐ │ │ │ │ │ │ Add AP IMG │ + ├──────────────>│ Auth AP IMG │ │ │ │ │ │ └────────────┘ + ╔══════╧══════╗ │ └─────────────┘ │ │ │ │ │ + ║Start SCU FW ║ │ ┌──────────────────┘ │ │ │ │ + ╚══════╤══════╝ │ │ │ │ │ │ + │ │ │ ┌─────────────────────┘ │ │ + ┌──────┴──────┐ │ │ │ │ │ │ + │ Start M4 ├──────┘ │ ┌──────────────────────┘ │ + └──────┬──────┘ │ │ │ │ │ + │ │ │ │ │ │ + ┌──────┴──────┐ │ │ │ │ │ + │ Start AP ├──────────┘ │ │ │ + └─────────────┘ │ │ │ │ + ┌───────────────────────┘ │ │ + │ │ │ │ + v │ │ │ + ┌─────────────┐ │ ┌─────────────┐ │ │ + │Request SECO ├───────>│ Auth AP IMG │ │ │ + └─────────────┘ │ └─────────────┘ │ │ + │ │ │ + +Notes: +All boxes enclosed by double dash (═) are performed at SCU/SECO ROM level. + +The sequence below explains the i.MX8 and i.MX8x boot flow: + +1 - At reset, the SCU ROM and SECO ROM both start execution. +2 - The SCU ROM reads the boot configuration and loads the SECO FW (First + container) from the boot media to the SECO TCM. +3 - A message is sent by the SCU ROM via MU requesting the SECO ROM to + authenticate the SECO FW which is signed using NXP key. +4 - The SCU ROM loads the second container from the boot media, this container + must contain at least the SCFW which is signed using the OEM keys. +5 - The SCU ROM loads the SCFW to the SCU TCM, a message is sent via MU + requesting the SECO FW to authenticate the SCFW and DCD table. +6 - The SCU ROM configures the DDR and loads the M4 and AP images included in + the second container to their respective load addresses. +7 - The SCU ROM request the SECO FW to authenticate the M4 image. +8 - The SCU ROM request the SECO FW to authenticate the AP image. This image + is the initial AP core software, depending in the U-Boot target it can + be the U-Boot and ATF or only SPL. +9 - The SCFW is initialized and starts the ARM Cortex-M and Cortex-A cores. +10 - From this point additional containers can be loaded by Cortex-M and + Cortex-A cores and authenticated by SECO, the AP SW must interface with + SCU by calling the sc_misc_seco_authenticate() API function. In current + U-Boot implementation the additional image can be the Linux Kernel binary + or the U-Boot proper and ATF. Details about current U-Boot implementation + can be found in AHAB guides included in doc/imx/ahab/guides/ directory. + +2. Generating a PKI tree +------------------------- + +The first step is to generate the private keys and public keys certificates. +The AHAB architecture is based on a Public Key Infrastructure (PKI) tree. + +The Code Signing Tools package contains an OpenSSL based key generation script +under keys/ directory. The ahab_pki_tree.sh script generates a PKI tree +containing 4 Super Root Keys (SRK), possible to also include a subordinate +SGK key. + +The AHAB supports both RSA and ECC keys, a new PKI tree can be generated by +following the example below: + +- Generating a P384 ECC PKI tree on CST v3.1.0: + + $ ./ahab_pki_tree.sh + ... + Do you want to use an existing CA key (y/n)?: n + Do you want to use Elliptic Curve Cryptography (y/n)?: y + Enter length for elliptic curve to be used for PKI tree: + Possible values p256, p384, p521: p384 + Enter the digest algorithm to use: sha384 + Enter PKI tree duration (years): 5 + Do you want the SRK certificates to have the CA flag set? (y/n)?: n + +The diagram below illustrate the PKI tree generated: + + ┌─────────┐ + │ CA │ + └────┬────┘ + │ + │ + ┌───────────────┬────────┴────────┬───────────────┐ + │ │ │ │ + │ │ │ │ + v v v v + ┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐ + │ SRK1 │ │ SRK2 │ │ SRK3 │ │ SRK4 │ + └────────┘ └────────┘ └────────┘ └────────┘ + +2.1 Generating a PKI tree including a subordinate SGK key +---------------------------------------------------------- + +The ahab_pki_tree.sh script is also able to generate a PKI tree containing a +subordinate key of the SRK, this key can be used to verify the signature +included in the final signed image. + +Users should set the CA flag when generating the SRK certificates. + +- Generating a P384 ECC PKI tree with a subordinate SGK key on CST v3.1.0: + + $ ./ahab_pki_tree.sh + ... + Do you want to use an existing CA key (y/n)?: n + Do you want to use Elliptic Curve Cryptography (y/n)?: y + Enter length for elliptic curve to be used for PKI tree: + Possible values p256, p384, p521: p384 + Enter the digest algorithm to use: sha384 + Enter PKI tree duration (years): 5 + Do you want the SRK certificates to have the CA flag set? (y/n)?: y + +The diagram below illustrate the PKI tree generated: + + ┌─────────┐ + │ CA │ + └────┬────┘ + │ + │ + ┌───────────────┬────────┴────────┬───────────────┐ + │ │ │ │ + v v v v + ┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐ + │ SRK1 │ │ SRK2 │ │ SRK3 │ │ SRK4 │ + └────┬───┘ └───┬────┘ └────┬───┘ └───┬────┘ + │ │ │ │ + v v v v + ┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐ + │ SGK1 │ │ SGK2 │ │ SGK3 │ │ SGK4 │ + └────────┘ └────────┘ └────────┘ └────────┘ + +Note: Due to a limitation in i.MX8QXP B0 silicon it's not possible to use RSA +4096-bit SRK keys with an additional subordinate SGK key. + +2.2 Generating a SRK Table and SRK Hash +---------------------------------------- + +The next step is to generated the SRK Table and its respective SRK Table Hash +from the SRK public key certificates created in one of the steps above. + +In the AHAB architecture, the SRK Table is included in the signed image and the +SRK Hash is programmed in the SoC SRK_HASH[511:0] fuses. + +On the target device during the authentication process the AHAB code verify the +SRK Table against the SoC SRK_HASH fuses, in case the verification is successful +the root of trust is established and the AHAB code can progress with the image +authentication. + +The srktool can be used for generating the SRK Table and its respective SRK +Table Hash. + +- Generating SRK Table and SRK Hash in Linux 64-bit machines: + + $ cd ../crts/ + $ ../linux64/bin/srktool -a -s sha384 -t SRK_1_2_3_4_table.bin \ + -e SRK_1_2_3_4_fuse.bin -f 1 -c \ + SRK1_sha384_secp384r1_v3_usr_crt.pem,\ + SRK2_sha384_secp384r1_v3_usr_crt.pem,\ + SRK3_sha384_secp384r1_v3_usr_crt.pem,\ + SRK4_sha384_secp384r1_v3_usr_crt.pem + +- Optionally users can check if the sha512sum of SRK_1_2_3_4_table matches with + the SRK_1_2_3_4_fuse.bin: + + $ od -t x4 --endian=big SRK_1_2_3_4_fuse.bin + 0000000 01b04697 0253376b 2066fe56 aaef9a91 + 0000020 e62e09d8 14fb7e36 d5b38d05 0982edab + 0000040 7ada6576 2f6b4f59 1fd9347e 46e7305d + 0000060 46e34bf0 89780bd1 c809e714 a17e2f4e + + $ sha512sum SRK_1_2_3_4_table.bin + 01b046970253376b2066fe56aaef9a91\ + e62e09d814fb7e36d5b38d050982edab\ + 7ada65762f6b4f591fd9347e46e7305d\ + 46e34bf089780bd1c809e714a17e2f4e\ + SRK_1_2_3_4_table.bin + +NOTE: The commands above cannot be used as reference to program the SoC + SRK_HASH fuses. + +The SRK_1_2_3_4_table.bin and SRK_1_2_3_4_fuse.bin files can be used in further +steps as explained in AHAB guides available under doc/imx/ahab/guides/ +directory. diff --git a/doc/README.imx25 b/doc/imx/common/imx25.txt similarity index 100% rename from doc/README.imx25 rename to doc/imx/common/imx25.txt diff --git a/doc/README.imx27 b/doc/imx/common/imx27.txt similarity index 100% rename from doc/README.imx27 rename to doc/imx/common/imx27.txt diff --git a/doc/README.imx5 b/doc/imx/common/imx5.txt similarity index 100% rename from doc/README.imx5 rename to doc/imx/common/imx5.txt diff --git a/doc/README.imx6 b/doc/imx/common/imx6.txt similarity index 73% rename from doc/README.imx6 rename to doc/imx/common/imx6.txt index b0644f8491f..eab88353f6c 100644 --- a/doc/README.imx6 +++ b/doc/imx/common/imx6.txt @@ -88,28 +88,3 @@ Reading bank 4: Word 0x00000002: 9f027772 00000004 -2. Using imx_usb_loader for first install with SPL --------------------------------------------------- - -imx_usb_loader is a very nice tool by Boundary Devices that -allow to install U-Boot without a JTAG debugger, using -the USB boot mode as described in the manual. It is -a replacement for Freescale's MFGTOOLS. - -The sources can be found here: - - https://github.com/boundarydevices/imx_usb_loader.git - -Booting in USB mode, the i.MX6 announces itself to the Linux Host as: - -Bus 001 Device 111: ID 15a2:0061 Freescale Semiconductor, Inc. - -imx_usb_loader is able to download a single file (u-boot.imx) -to the board. For boards without SPL support, it is enough to -issue the command: - - sudo ../imx_usb_loader/imx_usb -v u-boot.imx - -In order to load SPL and u-boot.img via imx_usb_loader tool, -please refer to doc/README.sdp. - diff --git a/doc/README.mxs b/doc/imx/common/mxs.txt similarity index 100% rename from doc/README.mxs rename to doc/imx/common/mxs.txt diff --git a/doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt b/doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt new file mode 100644 index 00000000000..589fd56f068 --- /dev/null +++ b/doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt @@ -0,0 +1,34 @@ +[Header] + Version = 4.2 + Hash Algorithm = sha256 + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + Engine = CAAM + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # Key used to authenticate the CSF data + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Install Key] + # Key slot index used to authenticate the key to be installed + Verification index = 0 + # Target key slot in HAB key store where key will be installed + Target Index = 2 + # Key to install + File= "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + # Key slot index used to authenticate the image data + Verification index = 2 + # Authenticate Start Address, Offset, Length and file + Blocks = 0x80800000 0x00000000 0x006EA000 "zImage", \ + 0x83800000 0x00000000 0x0000B927 "imx7d-sdb.dtb", \ + 0x84000000 0x00000000 0x000425B8 "uTee-7dsdb" diff --git a/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_enc.txt b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_enc.txt new file mode 100644 index 00000000000..96083a6a589 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_enc.txt @@ -0,0 +1,50 @@ +[Header] + Version = 4.2 + Hash Algorithm = sha256 + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + Engine = CAAM + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # Key used to authenticate the CSF data + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Install Key] + # Key slot index used to authenticate the key to be installed + Verification index = 0 + # Target key slot in HAB key store where key will be installed + Target Index = 2 + # Key to install + File= "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + # Key slot index used to authenticate the image data + Verification index = 2 + # This Authenticate Data command covers the IVT and DCD Data + # The image file referenced will remain unmodified by CST + Blocks = 0x877ff400 0x000 0xc00 "u-boot-dtb.imx" + +[Install Secret Key] + # Install the blob + Verification Index = 0 + Target Index = 0 + Key = "dek.bin" + Key Length = 128 + # Start address + padding 0x2000 + length + Blob Address = 0x878a0000 + +[Decrypt Data] + # The decrypt data command below causes CST to modify the input + # file and encrypt the specified block of data. This image file + # is a copy of the file used for the authentication command above + Verification Index = 0 + Mac Bytes = 16 + Blocks = 0x87800000 0x00000c00 0x9e000 "u-boot-dtb.imx-enc" diff --git a/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_sign_enc.txt b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_sign_enc.txt new file mode 100644 index 00000000000..7e508020af3 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_sign_enc.txt @@ -0,0 +1,53 @@ +[Header] + Version = 4.2 + Hash Algorithm = sha256 + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + Engine = CAAM + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # Key used to authenticate the CSF data + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Install Key] + # Key slot index used to authenticate the key to be installed + Verification index = 0 + # Target key slot in HAB key store where key will be installed + Target Index = 2 + # Key to install + File= "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + # This Authenticate Data commandcovers both clear and encrypted data. + # The image file referenced will remain unmodified by CST. + # Key slot index used to authenticate the image data + Verification index = 2 + # Authenticate Start Address, Offset, Length and file + Blocks = 0x877ff400 0x000 0x0009ec00 "u-boot-dtb.imx-enc" + +[Install Secret Key] + # Install the blob - This will manage a new key that will not be used in + # the final image, so the file name has to be different + Verification Index = 0 + Target Index = 0 + Key = "dek-dummy.bin" + Key Length = 128 + # Start address + padding 0x2000 + length + Blob Address = 0x878a000 + +[Decrypt Data] + # The decrypt Data command is a place holder to ensure the + # CSF includes the decrypt data command from the first pass. + # The file that CST will encrypt will not be used, so the file + # name has to be different. + Verification Index = 0 + Mac Bytes = 16 + Blocks = 0x87800000 0x00000c00 0x9e000 "u-boot-dtb.imx-dummy" diff --git a/doc/imx/habv4/csf_examples/mx6_mx7/csf_uboot.txt b/doc/imx/habv4/csf_examples/mx6_mx7/csf_uboot.txt new file mode 100644 index 00000000000..39986243e4b --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx6_mx7/csf_uboot.txt @@ -0,0 +1,32 @@ +[Header] + Version = 4.2 + Hash Algorithm = sha256 + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + Engine = CAAM + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # Key used to authenticate the CSF data + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Install Key] + # Key slot index used to authenticate the key to be installed + Verification index = 0 + # Target key slot in HAB key store where key will be installed + Target Index = 2 + # Key to install + File= "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + # Key slot index used to authenticate the image data + Verification index = 2 + # Authenticate Start Address, Offset, Length and file + Blocks = 0x877ff400 0x00000000 0x0009ec00 "u-boot-dtb.imx" diff --git a/doc/imx/habv4/csf_examples/mx6_mx7/csf_uboot_fast_authentication.txt b/doc/imx/habv4/csf_examples/mx6_mx7/csf_uboot_fast_authentication.txt new file mode 100644 index 00000000000..cdb34bcf741 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx6_mx7/csf_uboot_fast_authentication.txt @@ -0,0 +1,23 @@ +[Header] + Version = 4.2 + Hash Algorithm = sha256 + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + Engine = CAAM + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install NOCAK] + File = "../crts/SRK1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Authenticate Data] + # Key slot index 0 used to authenticate the image data + Verification index = 0 + # Authenticate Start Address, Offset, Length and file + Blocks = 0x877ff400 0x00000000 0x0009ec00 "u-boot-dtb.imx" diff --git a/doc/imx/habv4/csf_examples/mx8m_mx8mm/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m_mx8mm/csf_fit.txt new file mode 100644 index 00000000000..d9218ab4311 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m_mx8mm/csf_fit.txt @@ -0,0 +1,36 @@ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # Key used to authenticate the CSF data + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Install Key] + # Key slot index used to authenticate the key to be installed + Verification index = 0 + # Target key slot in HAB key store where key will be installed + Target index = 2 + # Key to install + File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + # Key slot index used to authenticate the image data + Verification index = 2 + # Authenticate Start Address, Offset, Length and file + Blocks = 0x401fcdc0 0x057c00 0x01020 "flash.bin", \ + 0x40200000 0x05AC00 0x9AAC8 "flash.bin", \ + 0x00910000 0x0F56C8 0x09139 "flash.bin", \ + 0xFE000000 0x0FE804 0x4D268 "flash.bin", \ + 0x4029AAC8 0x14BA6C 0x06DCF "flash.bin" diff --git a/doc/imx/habv4/csf_examples/mx8m_mx8mm/csf_spl.txt b/doc/imx/habv4/csf_examples/mx8m_mx8mm/csf_spl.txt new file mode 100644 index 00000000000..39adf7a3eb8 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m_mx8mm/csf_spl.txt @@ -0,0 +1,37 @@ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # Key used to authenticate the CSF data + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Unlock] + # Leave Job Ring and DECO master ID registers Unlocked + Engine = CAAM + Features = MID + +[Install Key] + # Key slot index used to authenticate the key to be installed + Verification index = 0 + # Target key slot in HAB key store where key will be installed + Target index = 2 + # Key to install + File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + # Key slot index used to authenticate the image data + Verification index = 2 + # Authenticate Start Address, Offset, Length and file + Blocks = 0x7e0fc0 0x1a000 0x2a600 "flash.bin" diff --git a/doc/imx/habv4/guides/mx6_mx7_encrypted_boot.txt b/doc/imx/habv4/guides/mx6_mx7_encrypted_boot.txt new file mode 100644 index 00000000000..0569fb3c6d3 --- /dev/null +++ b/doc/imx/habv4/guides/mx6_mx7_encrypted_boot.txt @@ -0,0 +1,278 @@ ++==========================================================+ ++ i.MX6, i.MX7 U-Boot Encrypted Boot guide using HABv4 + ++==========================================================+ + +1. HABv4 Encrypted Boot process +------------------------------- + +This document describes a step-by-step procedure on how to encrypt and +sign an U-Boot image. It is assumed that the reader is familiar +with basic HAB concepts and has already followed the mx6_mx7_secure_boot.txt +guide and got a working closed device. + +Details about HAB and encrypted boot process can be found in application +notes AN4581[1] and AN12056[2] and in the introduction_habv4.txt document. + +Before continuing, be sure to have fatwrite and dek_blob commands +available in U-Boot. If not, enable them in Kconfig and rebuild +U-Boot: + +- Defconfig + + CONFIG_FAT_WRITE=y + CONFIG_CMD_DEKBLOB=y + CONFIG_CMD_PRIBLOB=y + +- Kconfig + + File systems -> Enable FAT filesystem support-> Enable FAT filesystem + write support + ARM architecture -> Support the 'dek_blob' command + ARM architecture -> Support the set_priblob_bitfield command + +1.1 Building an encrypted U-Boot image +-------------------------------------- + +This U-Boot is built the same way the one from the secure document is, +so it provides the same access the the HAB APIs, extra functions +for HAB, etc... + +However, the layout of the new image is different, as a part of it is +encrypted, and a DEK blob is appended at the end. The diagram below +illustrates an encrypted u-boot-dtb.imx image layout: + + ----------------------- +-----------------------------+ <--- *start + ^ ^ | Image Vector Table | + | | +-----------------------------+ <--- *boot_data + | | | Boot Data | + | Plain | +-----------------------------+ <--- *dcd + | text | | DCD Table | + | | +-----------------------------+ + Signed | v | Padding | + data | ------- +-----------------------------+ <--- *entry + | ^ | | + | | | | + | Encrypted | | u-boot-dtb.bin | + | data | | | + | | | | + | | +-----------------------------+ + v v | Padding | + ----------------------- +-----------------------------+ <--- *csf + ^ | Command Sequence File | + 0x2000 | | (commands + SRK table + | + (in bytes) | | signatures + certificates + | + v | Nonce + MAC) | + ------- +-----------------------------+ + | Padding | + +-----------------------------+ <--- *csf + 0x2000 + | DEK Blob | + +-----------------------------+ + | Padding | + +-----------------------------+ + +1.2 Get a secure boot working +----------------------------- + +You need to go through all the steps described into the +mx6_mx7_secure_boot.txt guide, and get a signed U-Boot which can +boot successfully on a closed target. Otherwise, the following +steps will not work. + +1.3 Compile the CST to enable the encrypting feature +---------------------------------------------------- + +The encrypting feature is not enabled by default. You need to +execute the following commands to enable it: + + $ sudo apt-get install libssl-dev openssl + $ cd /code/back_end/src + $ gcc -o cst_encrypted -I ../hdr -L ../../../linux64/lib *.c + -lfrontend -lcrypto + $ cp cst_encrypted ../../../ + +1.4 Creating the CSF description files +-------------------------------------- + +The CSF contains all the commands that the ROM executes during the +secure boot. These commands instruct the HAB on which memory areas +of the image to authenticate, which keys to install, use, etc... + +CSF examples for encrypted boot are available under +doc/imx/habv4/csf_examples/ directory. + +For both CSF, first part is same compared to the CSF used for +the secure boot step. +Here we describe how to encrypt the U-Boot image and then sign it. + +1.4.1 csf_u-boot_enc.txt +------------------------- + +This first CSF is used to encrypt the U-Boot image and generate the +dek.bin file. The Authenticate Data command has to be modified, and +two new commands have to be added: + +- Modify the Authenticate Data command to only cover IVT and DCD: + + Blocks = 0x877ff400 0x00000000 0x00000c00 "u-boot-dtb.imx" + +- Add the new Install Secret Key command to generate the dek.bin + file and install the blob. The parameter which depends of your + configuration is the Blob Address. Padding of 0x2000 is + recommended. Following the csf_uboot.txt data for instance: + + Blob Address = Authenticate Start Address + Padding + length + = 0x877ff400 + 0x2000 + 0x9ec00 = 0x878a0000 + +- Add the new Decrypt Data command to encrypt the file. As the file + specified in parameter will be modified, we suggest to copy it. + Then modify the Blocks command depending of your U-Boot image. + In our example: + + $ cp u-boot-dtb.imx u-boot-dtb.imx-enc + Block = (Authenticate start addr + 0xc00) 0xc00 (length - 0xc00) + u-boot-dtb.imx-enc + = (0x877ff400 + 0xc00) 0xc00 (0x9ec00 - 0xc00) + u-boot-dtb.imx-enc + = 0x87800000 0xc00 0x9e000 u-boot-dtb.imx-enc + +1.4.2 csf_u-boot_sign_enc.txt +----------------------------- + +This second CSF is used to sign the encrypted U-Boot image previously +generated (u-boot-dtb.imx-enc). The Authenticate Data part has also +to be changed, the modifications are the following: + +- The Authenticate Data command is same compared to the one in + csf_uboot.txt file, except that this time, the file parameter + is the file previously encrypted: u-boot-dtb.imx-enc. + + Blocks = 0x877ff400 0x000 0x0009ec00 "u-boot-dtb.imx-enc" + +- For the two new commands, we do not want to they modify our previously + signed/generated files. Therefore, for the Key parameter of the + Install Secret Key command, the value is now dek-dummy.bin, which + will generate a new dek file instead of erasing the previous one. + About the decrypt data command, you need to copy the u-boot-dtb.imx + file again in a u-boot-dtb.imx-dummy file, to not replace the + original encrypted file with an encrypted one: + + Key = "dek-dummy.bin" + Blocks = 0x87800000 0x00000c00 0x9e000 "u-boot-dtb.imx-dummy" + +1.5 Encrypt the U-Boot image +---------------------------- + +The image is encrypted using the Code Signing Tool. It generates also +a CSF binary and a dek.bin file, which will be used on the future +steps below. + +- Create the CSF binary file and encrypt the U-Boot image + + $ ./cst_encrypted -i csf_u-boot_enc.txt -o csf_u-boot_enc.bin + +1.6 Sign the encrypted U-Boot image +----------------------------------- + +The image is then signed using the Code Signing Tool. It also +generate a CSF binary, which will be used on the future steps below. + +- Create the CSF binary file and sign the encrypted U-Boot image + + $ ./cst_encrypted -i csf_u-boot_sign_enc.txt -o csf_u-boot_sign_enc.bin + +1.7 Swap Nonce/MAC from csf_u-boot_enc.bin to csf_u-boot_sign_enc.bin +--------------------------------------------------------------------- + +First, calculate Nonce/MAC size based on MAC bytes value +in CSF. As Mac bytes is 16: + + Nonce/MAC size = Nonce size + MAC bytes + CSF header for Nonce/Mac + = 12 + 16 + 8 = 36 bytes + +Then, calculate Nonce/MAC offset in CSF: + + MAC offset = csf_u-boot-enc.bin size - Nonce/MAC size + = 3972 - 36 = 3936 Bytes + +In the next step, extract Nonce/NAC from the first CSF: + + $ dd if=csf_u-boot_enc.bin of=noncemac.bin bs=1 skip=3936 count=36 + +Finally, replace the MAC of csf_u-boot_sign_enc.bin with the extracted +one: + + $ dd if=noncemac.bin of=csf_u-boot_sign_enc.bin bs=1 seek=3936 count=36 + +1.8 Generate encryptedu-boot with no dek +---------------------------------------- + +As described in the layout in the first part of this document, the +final image is composed of these different parts padded to known +values, to make it compliant with the CSF. + +First, pad the CSF to 0x2000: + + $ objcopy -I binary -O binary --pad-to 0x2000 --gap-fill=0xff + csf_u-boot_sign_enc.bin csf_u-boot_sign_enc_padded.bin + +Then, append this file to the encrypted U-Boot image: + + $ cat u-boot-dtb.imx-enc csf_u-boot_sign_enc_padded.bin > + u-boot_encrypted_no_dek.bin + +Pad this new file to width+offset (0x9ec00 + 0x2000 = 0xa0c00): + + $ objcopy -I binary -O binary --pad-to 0xa0c00 --gap-fill=0x00 + u-boot_encrypted_no_dek.bin u-boot_encrypted_no_dek_padded.bin + +1.9 Generate the DEK Blob +------------------------- +The missing part to get our final U-Boot encrypted image is a DEK +blob. To generate it, copy the dek.bin file generated at step 1.5 +on the Boot partition of your SD Card. Then interrupt the boot +and your chip. You need the fatwrite and dek_blob command, which +should be enabled by the secure boot. If not, you have to enable +them in Kconfig and recompile U-Boot + +Run the following commands: + + => mmc list + FSL_SDHC: 0 (SD) #index to use for mmc in following commands + => fatload mmc 0 0x80800000 dek.bin + => dek_blob 0x80800000 0x80801000 128 + => fatwrite mmc 0 0x80801000 dek_blob.bin 0x48 + +1.10 Finalize the encrypted U-Boot image +---------------------------------------- + +Finally, copy the generated dek_blob.bin file from your SDCard to +your CST repository. Append it with the last padded file to get your +final image: + + $ cat u-boot_encrypted_no_dek_padded.bin dek_blob.bin > + u-boot_encrypted.bin + +If the image does not boot, please verify the size of your +U-Boot image, the length specified into CSF and the padding values. + +2. About the PRIBLOB bitfield from CAAM SCFGR register +------------------------------------------------------ + +It is highly recommended to set the PRIBLOB bitfield from the CAAM +SCFGR register to 0x3 once your encrypted U-Boot image is completed. +To do so, a command has been implemented in u-boot: + + => set_priblob_bitfield + +Once this bitfield is set to 0x3, it ensures cryptographic separation +of private blob types avoiding any modification or replacement of +DEK blobs. Newly created blobs will be incompatible with blobs +required to decrypt an encrypted boot image. When the HAB later +executes the command to decrypt the DEK, an incompatible DEK blob +will be detected and cause an error. A substitute encrypted boot image +will not be decrypted, and will not be executed. + +References: +[1] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series +using HABv4" - Rev. 2 +[2] AN12056: "Encrypted Boot on HABv4 and CAAM Enabled Devices" - Rev. 1 diff --git a/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt new file mode 100644 index 00000000000..3e6339dc520 --- /dev/null +++ b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt @@ -0,0 +1,444 @@ + +=======================================================+ + + i.MX6, i.MX7 U-Boot Secure Boot guide using HABv4 + + +=======================================================+ + +1. HABv4 secure boot process +----------------------------- + +This document describes a step-by-step procedure on how to sign and securely +boot an U-Boot image. It is assumed that the reader is familiar with basic +HAB concepts and with the PKI tree generation. + +Details about HAB can be found in the application note AN4581[1] and in the +introduction_habv4.txt document. + +1.1 Building a u-boot-dtb.imx image supporting secure boot +----------------------------------------------------------- + +The U-Boot provides support to secure boot configuration and also provide +access to the HAB APIs exposed by the ROM vector table, the support is +enabled by selecting the CONFIG_SECURE_BOOT option. + +When built with this configuration, the U-Boot provides extra functions for +HAB, such as the HAB status logs retrievement through the hab_status command +and support for extending the root of trust. + +The U-Boot also correctly pads the final image by aligning to the next 0xC00 +address, so the CSF signature data generated by CST can be concatenated to +image. + +The diagram below illustrate a signed u-boot-dtb.imx image layout: + + ------- +-----------------------------+ <-- *start + ^ | Image Vector Table | + | +-----------------------------+ <-- *boot_data + | | Boot Data | + | +-----------------------------+ <-- *dcd + | | DCD Table | + | +-----------------------------+ + Signed | | Padding | + Data | +-----------------------------+ <-- *entry + | | | + | | | + | | u-boot-dtb.bin | + | | | + | | | + | +-----------------------------+ + v | Padding | + ------- +-----------------------------+ <-- *csf + | | + | Command Sequence File (CSF) | + | | + +-----------------------------+ + | Padding (optional) | + +-----------------------------+ + +1.2 Enabling the secure boot support +------------------------------------- + +The first step is to generate an U-Boot image supporting the HAB features +mentioned above, this can be achieved by adding CONFIG_SECURE_BOOT to the +build configuration: + +- Defconfig: + + CONFIG_SECURE_BOOT=y + +- Kconfig: + + ARM architecture -> Support i.MX HAB features + +1.3 Creating the CSF description file +-------------------------------------- + +The CSF contains all the commands that the ROM executes during the secure +boot. These commands instruct the HAB on which memory areas of the image +to authenticate, which keys to install, use and etc. + +CSF examples are available under doc/imx/habv4/csf_examples/ directory. + +A build log containing the "Authenticate Data" parameters is available after +the U-Boot build, the example below is a log for mx7dsabresd_defconfig target: + +- mkimage build log: + + $ cat u-boot-dtb.imx.log + + Image Type: Freescale IMX Boot Image + Image Ver: 2 (i.MX53/6/7 compatible) + Mode: DCD + Data Size: 667648 Bytes = 652.00 KiB = 0.64 MiB + Load Address: 877ff420 + Entry Point: 87800000 + HAB Blocks: 877ff400 00000000 0009ec00 + ^^^^^^^^ ^^^^^^^^ ^^^^^^^^ + | | | + | | ------- (1) + | | + | ---------------- (2) + | + ------------------------- (3) + + (1) Size of area in file u-boot-dtb.imx to sign. + This area should include the IVT, the Boot Data the DCD + and the U-Boot itself. + (2) Start of area in u-boot-dtb.imx to sign. + (3) Start of area in RAM to authenticate. + +- In "Authenticate Data" CSF command users can copy and past the output + addresses: + + Block = 0x877ff400 0x00000000 0x0009ec00 "u-boot-dtb.imx" + +1.3.1 Avoiding Kernel crash when OP-TEE is enabled +--------------------------------------------------- + +For devices prior to HAB v4.4.0, the HAB code locks the Job Ring and DECO +master ID registers in HAB closed configuration. In case the user specific +application requires any changes in CAAM MID registers it's necessary to +add the "Unlock CAAM MID" command in CSF file. + +The current NXP OP-TEE implementation expects the CAAM registers to be unlocked +when configuring CAAM to operate in non-secure TrustZone world. + +- Add Unlock MID command in CSF: + + [Unlock] + Engine = CAAM + Features = MID + +1.4 Signing the U-Boot binary +------------------------------ + +The CST tool is used for singing the U-Boot binary and generating a CSF binary, +users should input the CSF description file created in the step above and +should receive a CSF binary, which contains the CSF commands, SRK table, +signatures and certificates. + +- Create CSF binary file: + + $ ./cst -i csf_uboot.txt -o csf_uboot.bin + +- Append CSF signature to the end of U-Boot image: + + $ cat u-boot-dtb.imx csf_uboot.bin > u-boot-signed.imx + +The u-boot-signed.imx is the signed binary and should be flashed into the boot +media. + +- Flash signed U-Boot binary: + + $ sudo dd if=u-boot-signed.imx of=/dev/sd bs=1K seek=1 && sync + +1.5 Programming SRK Hash +------------------------- + +As explained in AN4581[1] and in introduction_habv4.txt document the SRK Hash +fuse values are generated by the srktool and should be programmed in the +SoC SRK_HASH[255:0] fuses. + +Be careful when programming these values, as this data is the basis for the +root of trust. An error in SRK Hash results in a part that does not boot. + +The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs. + +- Dump SRK Hash fuses values in host machine: + + $ hexdump -e '/4 "0x"' -e '/4 "%X""\n"' SRK_1_2_3_4_fuse.bin + 0x20593752 + 0x6ACE6962 + 0x26E0D06C + 0xFC600661 + 0x1240E88F + 0x1209F144 + 0x831C8117 + 0x1190FD4D + +- Program SRK_HASH[255:0] fuses, using i.MX6 series as example: + + => fuse prog 3 0 0x20593752 + => fuse prog 3 1 0x6ACE6962 + => fuse prog 3 2 0x26E0D06C + => fuse prog 3 3 0xFC600661 + => fuse prog 3 4 0x1240E88F + => fuse prog 3 5 0x1209F144 + => fuse prog 3 6 0x831C8117 + => fuse prog 3 7 0x1190FD4D + +The table below lists the SRK_HASH bank and word according to the i.MX device: + + +-------------------+---------------+---------------+---------------+ + | | i.MX6 Series | i.MX7D/S | i.MX7ULP | + +-------------------+---------------+---------------+---------------+ + | SRK_HASH[31:00] | bank 3 word 0 | bank 6 word 0 | bank 5 word 0 | + +-------------------+---------------+---------------+---------------+ + | SRK_HASH[63:32] | bank 3 word 1 | bank 6 word 1 | bank 5 word 1 | + +-------------------+---------------+---------------+---------------+ + | SRK_HASH[95:64] | bank 3 word 2 | bank 6 word 2 | bank 5 word 2 | + +-------------------+---------------+---------------+---------------+ + | SRK_HASH[127:96] | bank 3 word 3 | bank 6 word 3 | bank 5 word 3 | + +-------------------+---------------+---------------+---------------+ + | SRK_HASH[159:128] | bank 3 word 4 | bank 7 word 0 | bank 5 word 4 | + +-------------------+---------------+---------------+---------------+ + | SRK_HASH[191:160] | bank 3 word 5 | bank 7 word 1 | bank 5 word 5 | + +-------------------+---------------+---------------+---------------+ + | SRK_HASH[223:192] | bank 3 word 6 | bank 7 word 2 | bank 5 word 6 | + +-------------------+---------------+---------------+---------------+ + | SRK_HASH[255:224] | bank 3 word 7 | bank 7 word 3 | bank 5 word 7 | + +-------------------+---------------+---------------+---------------+ + +1.6 Verifying HAB events +------------------------- + +The next step is to verify that the signature attached to U-Boot is +successfully processed without errors. HAB generates events when processing +the commands if it encounters issues. + +The hab_status U-Boot command call the hab_report_event() and hab_status() +HAB API functions to verify the processor security configuration and status. +This command displays any events that were generated during the process. + +Prior to closing the device users should ensure no HAB events were found, as +the example below: + +- Verify HAB events: + + => hab_status + + Secure boot disabled + + HAB Configuration: 0xf0, HAB State: 0x66 + No HAB Events Found! + +1.6.1 Verifying HAB events in i.MX7ULP +--------------------------------------- + +When booting i.MX7ULP in low power or dual boot modes the M4 binary is +authenticated by an independent HAB in M4 ROM code using a +different SRK key set. + +The U-Boot provides a M4 option in hab_status command so users can retrieve +M4 HAB failure and warning events. + +- Verify HAB M4 events: + + => hab_status m4 + + Secure boot disabled + + HAB Configuration: 0xf0, HAB State: 0x66 + No HAB Events Found! + +As HAB M4 API cannot be called from A7 core the command is parsing the M4 HAB +persistent memory region, M4 software should not modify this reserved region. + +Details about HAB persistent memory region can be found in AN12263[2]. + +1.7 Closing the device +----------------------- + +After the device successfully boots a signed image without generating any HAB +events, it is safe to close the device. This is the last step in the HAB +process, and is achieved by programming the SEC_CONFIG[1] fuse bit. + +Once the fuse is programmed, the chip does not load an image that has not been +signed using the correct PKI tree. + +- Program SEC_CONFIG[1] fuse, using i.MX6 series as example: + + => fuse prog 0 6 0x00000002 + +The table below list the SEC_CONFIG[1] bank and word according to the i.MX +device: + + +--------------+-----------------+------------+ + | Device | Bank and Word | Value | + +--------------+-----------------+------------+ + | i.MX6 Series | bank 0 word 6 | 0x00000002 | + +--------------+-----------------+------------+ + | i.MX7D/S | bank 1 word 3 | 0x02000000 | + +--------------+-----------------+------------+ + | i.MX7ULP | bank 29 word 6 | 0x80000000 | + +--------------+-----------------+------------+ + +1.8 Completely secure the device +--------------------------------- + +Additional fuses can be programmed for completely secure the device, more +details about these fuses and their possible impact can be found at AN4581[1]. + +- Program SRK_LOCK, using i.MX6 series as example: + + => fuse prog 0 0 0x4000 + +- Program DIR_BT_DIS, using i.MX6 series as example: + + => fuse prog 0 6 0x8 + +- Program SJC_DISABLE, using i.MX6 series as example: + + => fuse prog 0 6 0x100000 + +- JTAG_SMODE, using i.MX6 series as example: + + => fuse prog 0 6 0xC00000 + +The table below list the SRK_LOCK, DIR_BT_DIS, SJC_DISABLE, and JTAG_SMODE bank +and word according to the i.MX device: + + +--------------+---------------+------------+ + | Device | Bank and Word | Value | + +--------------+---------------+------------+ + | SRK_LOCK | + +-------------------------------------------+ + | i.MX6 Series | bank 0 word 0 | 0x00004000 | + +--------------+---------------+------------+ + | i.MX7D/S | bank 0 word 0 | 0x00000200 | + +--------------+---------------+------------+ + | i.MX7ULP | bank 1 word 1 | 0x00000080 | + +--------------+---------------+------------+ + | DIR_BT_DIS | + +-------------------------------------------+ + | i.MX6 Series | bank 0 word 6 | 0x00000008 | + +--------------+---------------+------------+ + | i.MX7D/S | bank 1 word 3 | 0x08000000 | + +--------------+---------------+------------+ + | i.MX7ULP | bank 1 word 1 | 0x00002000 | + +--------------+---------------+------------+ + | SJC_DISABLE | + +-------------------------------------------+ + | i.MX6 Series | bank 0 word 6 | 0x00100000 | + +--------------+---------------+------------+ + | i.MX7D/S | bank 1 word 3 | 0x00200000 | + +--------------+---------------+------------+ + | i.MX7ULP | bank 1 word 1 | 0x00000020 | + +--------------+---------------+------------+ + | JTAG_SMODE | + +-------------------------------------------+ + | i.MX6 Series | bank 0 word 6 | 0x00C00000 | + +--------------+---------------+------------+ + | i.MX7D/S | bank 1 word 3 | 0x00C00000 | + +--------------+---------------+------------+ + | i.MX7ULP | bank 1 word 1 | 0x000000C0 | + +--------------+---------------+------------+ + +2. Extending the root of trust +------------------------------- + +The High Assurance Boot (HAB) code located in the on-chip ROM provides an +Application Programming Interface (API) making it possible to call back +into the HAB code for authenticating additional boot images. + +The U-Boot supports this feature and can be used to authenticate the Linux +Kernel Image. + +The process of signing an additional image is similar to the U-Boot. +The diagram below illustrate the zImage layout: + + ------- +-----------------------------+ <-- *load_address + ^ | | + | | | + | | | + | | | + | | zImage | + Signed | | | + Data | | | + | | | + | +-----------------------------+ + | | Padding Next Boundary | + | +-----------------------------+ <-- *ivt + v | Image Vector Table | + ------- +-----------------------------+ <-- *csf + | | + | Command Sequence File (CSF) | + | | + +-----------------------------+ + | Padding (optional) | + +-----------------------------+ + +2.1 Padding the image +---------------------- + +The zImage must be padded to the next boundary address (0x1000), for instance +if the image size is 0x649920 it must be padded to 0x64A000. + +The tool objcopy can be used for padding the image. + +- Pad the zImage: + + $ objcopy -I binary -O binary --pad-to 0x6EA000 --gap-fill=0x00 \ + zImage zImage_pad.bin + +2.2 Generating Image Vector Table +---------------------------------- + +The HAB code requires an Image Vector Table (IVT) for determining the image +length and the CSF location. Since zImage does not include an IVT this has +to be manually created and appended to the end of the padded zImage, the +script genIVT.pl in script_examples directory can be used as reference. + +- Generate IVT: + + $ genIVT.pl + +Note: The load Address may change depending on the device. + +- Append the ivt.bin at the end of the padded zImage: + + $ cat zImage_pad.bin ivt.bin > zImage_pad_ivt.bin + +2.3 Signing the image +---------------------- + +A CSF file has to be created to sign the image. HAB does not allow to change +the SRK once the first image is authenticated, so the same SRK key used in +U-Boot must be used when extending the root of trust. + +CSF examples are available in ../csf_examples/additional_images/ +directory. + +- Create CSF binary file: + + $ ./cst --i csf_additional_images.txt --o csf_zImage.bin + +- Attach the CSF binary to the end of the image: + + $ cat zImage_pad_ivt.bin csf_zImage.bin > zImage_signed.bin + +2.4 Verifying HAB events +------------------------- + +The U-Boot includes the hab_auth_img command which can be used for +authenticating and troubleshooting the signed image, zImage must be +loaded at the load address specified in the IVT. + +- Authenticate additional image: + + => hab_auth_img + +If no HAB events were found the zImage is successfully signed. + +References: +[1] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using + HABv4" - Rev 2. +[2] AN12263: "HABv4 RVT Guidelines and Recommendations" - Rev 0. diff --git a/doc/imx/habv4/guides/mx8m_mx8mm_secure_boot.txt b/doc/imx/habv4/guides/mx8m_mx8mm_secure_boot.txt new file mode 100644 index 00000000000..5922a1c31f2 --- /dev/null +++ b/doc/imx/habv4/guides/mx8m_mx8mm_secure_boot.txt @@ -0,0 +1,538 @@ + +=======================================================+ + + i.MX8M, i.MX8MM Secure Boot guide using HABv4 + + +=======================================================+ + +1. HABv4 secure boot process +----------------------------- + +This document describes a step-by-step procedure on how to sign and securely +boot a bootloader image on i.MX8M and i.MX8MM devices. It is assumed that +the reader is familiar with basic HAB concepts and with the PKI tree generation. + +Details about HAB can be found in the application note AN4581[1] and in the +introduction_habv4.txt document. + +1.1 Understanding the i.MX8M and i.MX8MM flash.bin image layout +---------------------------------------------------------------- + +Due to the new the architecture, multiple firmwares and softwares are required +to boot i.MX8M and i.MX8MM devices. In order to store all the images in a +single binary the FIT (Flattened Image Tree) image structure is used. + +The final image is generated by the imx-mkimage project, the tool combines all +the input images in a FIT structure, generating a flash.bin image with an +appropriate IVT set. + +For a secure boot process users should ensure all images included in flash.bin +file are covered by a digital signature. + +- The diagram below illustrate a signed flash.bin image layout: + + +-----------------------------+ + | | + | *Signed HDMI/DP FW | + | | + +-----------------------------+ + | Padding | + ------- +-----------------------------+ -------- + ^ | IVT - SPL | ^ + Signed | +-----------------------------+ | + Data | | u-boot-spl.bin | | + | | + | | SPL + v | DDR FW | | Image + ------- +-----------------------------+ | + | CSF - SPL + DDR FW | v + +-----------------------------+ -------- + | Padding | + ------- +-----------------------------+ -------- + Signed ^ | FDT - FIT | ^ + Data | +-----------------------------+ | + v | IVT - FIT | | + ------- +-----------------------------+ | + | CSF - FIT | | + ------- +-----------------------------+ | + ^ | u-boot-nodtb.bin | | FIT + | | + | | Image + | | u-boot.bin | | + Signed | +-----------------------------+ | + Data | | OP-TEE (Optional) | | + | +-----------------------------+ | + | | bl31.bin (ATF) | | + | +-----------------------------+ | + v | u-boot.dtb | v + ------- +-----------------------------+ -------- + * Only supported on i.MX8M series + +The boot flow on i.MX8M and i.MX8MM devices are slightly different when compared +with i.MX6 and i.MX7 series, the diagram below illustrate the boot sequence +overview: + +- i.MX8M and i.MX8MM devices boot flow: + + Secure World Non-Secure World + | + | + +------------+ +------------+ | + | SPL | | i.MX 8M/MM | | + | + | ---> | ROM | | + | DDR FW | | + HAB | | + +------------+ +------------+ | + | | + v | + +------------+ | + | *Signed | | + | HDMI/DP FW | | + +------------+ | + | | + v | + +------------+ +------------+ | + | FIT Image: | | SPL | | + | ATF + TEE | ---> | + | | + | + U-Boot | | DDR FW | | +-----------+ + +------------+ +------------+ | | Linux | + | | +-----------+ + v | ^ + +------------+ | | +-------+ + | ARM | | +-----------+ | Linux | + | Trusted | ----+---> | U-Boot | <--- | + | + | Firmware | | +-----------+ | DTB | + +------------+ | +-------+ + | | + v | + +----------+ | + | **OP-TEE | | + +----------+ | + * Only supported on i.MX8M series + ** Optional + +On i.MX8M devices the HDMI firmware or DisplayPort firmware are the first image +to boot on the device. These firmwares are signed and distributed by NXP, and +are always authenticated regardless of security configuration. In case not +required by the application the HDMI or DisplayPort controllers can be disabled +by eFuses and the firmwares are not required anymore. + +The next images are not signed by NXP and users should follow the signing +procedure as described in this document. + +The Second Program Loader (SPL) and DDR firmware are loaded and authenticated +by the ROM code, these images are executed in the internal RAM and responsible +for initializing essential features such as DDR, UART, PMIC and clock +enablement. + +Once the DDR is available, the SPL code loads all the images included in the +FIT structure to their specific execution addresses, the HAB APIs are called +to extend the root of trust, authenticating the U-Boot, ARM trusted firmware +(ATF) and OP-TEE (If included). + +The root of trust can be extended again at U-Boot level to authenticate Kernel +and M4 images. + +1.2 Enabling the secure boot support in U-Boot +----------------------------------------------- + +The first step is to generate an U-Boot image supporting the HAB features, +similar to i.MX6 and i.MX7 series the U-Boot provides extra functions for +HAB, such as the HAB status logs retrievement through the hab_status command +and support to extend the root of trust. + +The support is enabled by adding the CONFIG_SECURE_BOOT to the build +configuration: + +- Defconfig: + + CONFIG_SECURE_BOOT=y + +- Kconfig: + + ARM architecture -> Support i.MX HAB features + +1.3 Preparing the fit image +---------------------------- + +The imx-mkimage project is used to combines all the images in a single +flash.bin binary, the following files are required: + +- U-Boot: + u-boot.bin + u-boot-nodtb.bin + u-boot-spl.bin + U-Boot DTB file (e.g. fsl-imx8mq-evk.dtb) + +- ATF image: + bl31.bin + +- DDR firmware: + lpddr4_pmu_train_1d_dmem.bin + lpddr4_pmu_train_1d_imem.bin + lpddr4_pmu_train_2d_dmem.bin + lpddr4_pmu_train_2d_imem.bin + +- HDMI firmware (Only in i.MX8M): + signed_hdmi_imx8m.bin + +- DisplayPort firmware (Only in i.MX8M): + signed_dp_imx8m.bin + +- OP-TEE (Optional): + tee.bin + +The procedure to build ATF and download the firmwares are out of the scope +of this document, please refer to the Linux BSP Release Notes and AN12212[2] +for further details. + +Copy all files to iMX8M directory and run the following command according to +the target device, on this example we are building a HDMI target and also +including the OP-TEE binary: + +- Assembly flash.bin binary: + + $ make SOC= flash_hdmi_spl_uboot + +The mkimage log can be used to calculate the authenticate image command +parameters and CSF offsets: + +- imx-mkimage build log: + + Loader IMAGE: + header_image_off 0x1a000 + dcd_off 0x0 + image_off 0x1a040 + csf_off 0x44600 + spl hab block: 0x7e0fd0 0x1a000 0x2e600 + + Second Loader IMAGE: + sld_header_off 0x57c00 + sld_csf_off 0x58c20 + sld hab block: 0x401fcdc0 0x57c00 0x1020 + +Additional HAB information is provided by running the following command: + +- Printing HAB FIT information: + + $ make SOC= print_fit_hab + + TEE_LOAD_ADDR=0xfe000000 ATF_LOAD_ADDR=0x00910000 ./print_fit_hab.sh \ + 0x60000 fsl-imx8mq-evk.dtb + 0x40200000 0x5AC00 0x9AAC8 + 0x910000 0xF56C8 0x9139 + 0xFE000000 0xFE804 0x4D268 + 0x4029AAC8 0x14BA6C 0x6DCF + +1.4 Creating the CSF description file +-------------------------------------- + +The CSF contains all the commands that the ROM executes during the secure +boot. These commands instruct the HAB code on which memory areas of the image +to authenticate, which keys to install, use and etc. + +CSF examples are available under doc/imx/habv4/csf_examples/ directory. + +As explained in sections above the SPL is first authenticated by the ROM code +and the root of trust is extended to the FIT image, hence two CSF files are +necessary to completely sign an flash.bin image. + +The build log provided by imx-mkimage can be used to define the "Authenticate +Data" parameter in CSF. + +- SPL "Authenticate Data" addresses in flash.bin build log: + + spl hab block: 0x7e0fd0 0x1a000 0x2e600 + +- "Authenticate Data" command in csf_spl.txt file: + + Blocks = 0x7e0fd0 0x1a000 0x2e600 "flash.bin" + +- FIT image "Authenticate Data" addresses in flash.bin build log: + + sld hab block: 0x401fcdc0 0x57c00 0x1020 + +- FIT image "Authenticate Data" addresses in print_fit_hab build log: + + 0x40200000 0x5AC00 0x9AAC8 + 0x910000 0xF56C8 0x9139 + 0xFE000000 0xFE804 0x4D268 + 0x4029AAC8 0x14BA6C 0x6DCF + +- "Authenticate Data" command in csf_fit.txt file: + + Blocks = 0x401fcdc0 0x057c00 0x01020 "flash.bin", \ + 0x40200000 0x05AC00 0x9AAC8 "flash.bin", \ + 0x00910000 0x0F56C8 0x09139 "flash.bin", \ + 0xFE000000 0x0FE804 0x4D268 "flash.bin", \ + 0x4029AAC8 0x14BA6C 0x06DCF "flash.bin" + +1.4.1 Avoiding Kernel crash in closed devices +---------------------------------------------- + +For devices prior to HAB v4.4.0, the HAB code locks the Job Ring and DECO +master ID registers in closed configuration. In case the user specific +application requires any changes in CAAM MID registers it's necessary to +add the "Unlock CAAM MID" command in CSF file. + +The current NXP BSP implementation expects the CAAM registers to be unlocked +when configuring CAAM to operate in non-secure TrustZone world. + +The Unlock command is already included by default in the signed HDMI and +DisplayPort firmwares, on i.MX8MM devices or in case the HDMI or DisplayPort +controllers are disabled, users must ensure this command is included in SPL CSF. + +- Add Unlock MID command in csf_spl.txt: + + [Unlock] + Engine = CAAM + Features = MID + +1.5 Signing the flash.bin binary +--------------------------------- + +The CST tool is used for singing the flash.bin image and generating the CSF +binary. Users should input the CSF description file created in the step above +and receive a CSF binary, which contains the CSF commands, SRK table, +signatures and certificates. + +- Create SPL CSF binary file: + + $ ./cst -i csf_spl.txt -o csf_spl.bin + +- Create FIT CSF binary file: + + $ ./cst -i csf_fit.txt -o csf_fit.bin + +1.6 Assembling the CSF in flash.bin binary +------------------------------------------- + +The CSF binaries generated in the step above have to be inserted into the +flash.bin image. + +The CSF offsets can be obtained from the flash.bin build log: + +- SPL CSF offset: + + csf_off 0x44600 + +- FIT CSF offset: + + sld_csf_off 0x58c20 + +The signed flash.bin image can be then assembled: + +- Create a flash.bin copy: + + $ cp flash.bin signed_flash.bin + +- Insert csf_spl.bin in signed_flash.bin at 0x44600 offset: + + $ dd if=csf_spl.bin of=signed_flash.bin seek=$((0x44600)) bs=1 conv=notrunc + +- Insert csf_fit.bin in signed_flash.bin at 0x58c20 offset: + + $ dd if=csf_fit.bin of=signed_flash.bin seek=$((0x58c20)) bs=1 conv=notrunc + +- Flash signed flash.bin image: + + $ sudo dd if=signed_flash.bin of=/dev/sd bs=1K seek=33 && sync + +1.7 Programming SRK Hash +------------------------- + +As explained in AN4581[1] and in introduction_habv4.txt document the SRK Hash +fuse values are generated by the srktool and should be programmed in the +SoC SRK_HASH[255:0] fuses. + +Be careful when programming these values, as this data is the basis for the +root of trust. An error in SRK Hash results in a part that does not boot. + +The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs. + +- Dump SRK Hash fuses values in host machine: + + $ hexdump -e '/4 "0x"' -e '/4 "%X""\n"' SRK_1_2_3_4_fuse.bin + 0x20593752 + 0x6ACE6962 + 0x26E0D06C + 0xFC600661 + 0x1240E88F + 0x1209F144 + 0x831C8117 + 0x1190FD4D + +- Program SRK_HASH[255:0] fuses on i.MX8MQ and i.MX8MM devices: + + => fuse prog 6 0 0x20593752 + => fuse prog 6 1 0x6ACE6962 + => fuse prog 6 2 0x26E0D06C + => fuse prog 6 3 0xFC600661 + => fuse prog 7 0 0x1240E88F + => fuse prog 7 1 0x1209F144 + => fuse prog 7 2 0x831C8117 + => fuse prog 7 3 0x1190FD4D + + +1.8 Verifying HAB events +------------------------- + +The next step is to verify that the signatures included in flash.bin image is +successfully processed without errors. HAB generates events when processing +the commands if it encounters issues. + +The hab_status U-Boot command call the hab_report_event() and hab_status() +HAB API functions to verify the processor security configuration and status. +This command displays any events that were generated during the process. + +Prior to closing the device users should ensure no HAB events were found, as +the example below: + +- Verify HAB events: + + => hab_status + + Secure boot disabled + + HAB Configuration: 0xf0, HAB State: 0x66 + +1.9 Closing the device +----------------------- + +After the device successfully boots a signed image without generating any HAB +events, it is safe to close the device. This is the last step in the HAB +process, and is achieved by programming the SEC_CONFIG[1] fuse bit. + +Once the fuse is programmed, the chip does not load an image that has not been +signed using the correct PKI tree. + +- Program SEC_CONFIG[1] fuse on i.MX8MQ and i.MX8MM devices: + + => fuse prog 1 3 0x2000000 + +1.10 Completely secure the device +---------------------------------- + +Additional fuses can be programmed for completely secure the device, more +details about these fuses and their possible impact can be found at AN4581[1]. + +- Program SRK_LOCK: + + => fuse prog 0 0 0x200 + +- Program DIR_BT_DIS: + + => fuse prog 1 3 0x8000000 + +- Program SJC_DISABLE: + + => fuse prog 1 3 0x200000 + +- JTAG_SMODE: + + => fuse prog 1 3 0xC00000 + +2. Authenticating additional boot images +----------------------------------------- + +The High Assurance Boot (HAB) code located in the on-chip ROM provides an +Application Programming Interface (API) making it possible to call back +into the HAB code for authenticating additional boot images. + +The U-Boot is running in non-secure TrustZone world and to make use of this +feature it's necessary to use a SIP call to the ATF, this is already +implemented in hab.c code and it's transparent to the user. + +The process of signing an additional image is similar as in i.MX6 and i.MX7 +series devices, the steps below are using the Linux Kernel image as example. + +The diagram below illustrate the Image layout: + + ------- +-----------------------------+ <-- *load_address + ^ | | + | | | + | | | + | | | + | | Image | + Signed | | | + Data | | | + | | | + | +-----------------------------+ + | | Padding to Image size | + | | in header | + | +-----------------------------+ <-- *ivt + v | Image Vector Table | + ------- +-----------------------------+ <-- *csf + | | + | Command Sequence File (CSF) | + | | + +-----------------------------+ + | Padding (optional) | + +-----------------------------+ + +2.1 Padding the image +---------------------- + +The Image must be padded to the size specified in the Image header, this can be +achieved by using the od command. + +- Read Image size: + + $ od -x -j 0x10 -N 0x4 --endian=little Image + 0000020 5000 0145 + 0000024 + +The tool objcopy can be used for padding the image. + +- Pad the Image: + + $ objcopy -I binary -O binary --pad-to 0x1455000 --gap-fill=0x00 \ + Image Image_pad.bin + +2.2 Generating Image Vector Table +---------------------------------- + +The HAB code requires an Image Vector Table (IVT) for determining the image +length and the CSF location. Since Image does not include an IVT this has +to be manually created and appended to the end of the padded Image, the +script genIVT.pl in script_examples directory can be used as reference. + +- Generate IVT: + + $ genIVT.pl + +Note: The load Address may change depending on the device. + +- Append the ivt.bin at the end of the padded Image: + + $ cat Image_pad.bin ivt.bin > Image_pad_ivt.bin + +2.3 Signing the image +---------------------- + +A CSF file has to be created to sign the image. HAB does not allow to change +the SRK once the first image is authenticated, so the same SRK key used in +the initial image must be used when extending the root of trust. + +CSF examples are available in ../csf_examples/additional_images/ directory. + +- Create CSF binary file: + + $ ./cst --i csf_additional_images.txt --o csf_Image.bin + +- Attach the CSF binary to the end of the image: + + $ cat Image_pad_ivt.bin csf_Image.bin > Image_signed.bin + +2.4 Verifying HAB events +------------------------- + +The U-Boot includes the hab_auth_img command which can be used for +authenticating and troubleshooting the signed image, the Image must be +loaded at the load address specified in the IVT. + +- Authenticate additional image: + + => hab_auth_img + +If no HAB events were found the Image is successfully signed. + +References: +[1] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using + HABv4" - Rev 2. +[2] AN12212: "Software Solutions for Migration Guide from Aarch32 to +Aarch64" - Rev 0. diff --git a/doc/imx/habv4/introduction_habv4.txt b/doc/imx/habv4/introduction_habv4.txt new file mode 100644 index 00000000000..25711bbe95a --- /dev/null +++ b/doc/imx/habv4/introduction_habv4.txt @@ -0,0 +1,262 @@ + +=======================================================+ + + i.MX Secure and Encrypted Boot using HABv4 + + +=======================================================+ + +1. Introduction +---------------- + +The i.MX family of applications processors provides the High Assurance Boot +(HAB) feature in the on-chip ROM. The ROM is responsible for loading the +initial program image (U-Boot) from the boot media and HAB enables the ROM +to authenticate and/or decrypt the program image by using cryptography +operations. + +This feature is supported in i.MX 50, i.MX 53, i.MX 6, i.MX 7 series and + i.MX 8M, i.MX 8MM devices. + +Step-by-step guides are available under doc/imx/habv4/guides/ directory, +users familiar with HAB and CST PKI tree generation should refer to these +documents instead. + +1.1 The HABv4 Secure Boot Architecture +--------------------------------------- + +The HABv4 secure boot feature uses digital signatures to prevent unauthorized +software execution during the device boot sequence. In case a malware takes +control of the boot sequence, sensitive data, services and network can be +impacted. + +The HAB authentication is based on public key cryptography using the RSA +algorithm in which image data is signed offline using a series of private +keys. The resulting signed image data is then verified on the i.MX processor +using the corresponding public keys. The public keys are included in the CSF +binary and the SRK Hash is programmed in the SoC fuses for establishing the +root of trust. + +The diagram below illustrate the secure boot process overview: + + Host PC + CST i.MX + HAB + +----------+ +----------+ + ---> | U-Boot | | Compare | + | +----------+ +----------+ + | | ^ ^ + | v Reference / \ Generated + | +----------+ Hash / \ Hash + | | Hash | Private / \ + | +----------+ Key / \ + | | | +----------+ +----------+ + | v | | Verify | | Hash | + | +----------+ | +----------+ +----------+ + | | Sign | <--- SRK ^ ^ + | +----------+ HASH \ / + | | | CSF \ / U-Boot + | v v \ / + | +----------+ +----------+ +----------+ + | | U-Boot | | | | U-Boot | + ---> | + | -----> | i.MX | -----> | + | + | CSF | | | | CSF | + +----------+ +----------+ +----------+ + +The U-Boot image to be programmed into the boot media needs to be properly +constructed i.e. it must contain a proper Command Sequence File (CSF). + +The CSF is a binary data structure interpreted by the HAB to guide +authentication process, this is generated by the Code Signing Tool[1]. +The CSF structure contains the commands, SRK table, signatures and +certificates. + +Details about the Secure Boot and Code Signing Tool (CST) can be found in +the application note AN4581[2] and in the secure boot guides. + +1.2 The HABv4 Encrypted Boot Architecture +------------------------------------------ + +The HAB Encrypted Boot feature available in CAAM supported devices adds an +extra security operation to the bootloading sequence. It uses cryptographic +techniques (AES-CCM) to obscure the U-Boot data, so it cannot be seen or used +by unauthorized users. This mechanism protects the U-Boot code residing on +flash or external memory and also ensures that the final image is unique +per device. + +The process can be divided into two protection mechanisms. The first mechanism +is the bootloader code encryption which provides data confidentiality and the +second mechanism is the digital signature, which authenticates the encrypted +image. + +Keep in mind that the encrypted boot makes use of both mechanisms whatever the +order is (sign and then encrypt, or encrypt and then sign), both operations +can be applied on the same region with exception of the U-Boot Header (IVT, +boot data and DCD) which can only be signed, not encrypted. + +The diagram below illustrate the encrypted boot process overview: + + Host PC + CST i.MX + HAB + +------------+ +--------------+ + | U-Boot | | U-Boot | + +------------+ +--------------+ + | ^ + | | + v DEK +--------------+ + +------------+ | ----> | Decrypt | + | Encrypt | <--- | +--------------+ + +------------+ DEK | ^ + | | | + | Private | | + v Key +------+ +--------------+ + +------------+ | | CAAM | | Authenticate | + | Sign | <--- +------+ +--------------+ + +------------+ DEK ^ ^ + | + OTPMK DEK \ / U-Boot + | | Blob \ / + CSF + v v \ / + +------------+ +----------+ +------------+ + | Enc U-Boot | | | | Enc U-Boot | + | + CSF | ----> | i.MX | -------> | + CSF | + | + DEK Blob | | | | + DEK Blob | + +------------+ +----------+ +------------+ + ^ | + | | + --------------------- + DEK Blob + (CAAM) + +The Code Signing Tool automatically generates a random AES Data Encryption Key +(DEK) when encrypting an image. This key is used in both encrypt and decrypt +operations and should be present in the final image structure encapsulated +by a CAAM blob. + +The OTP Master Key (OTPMK) is used to encrypt and wrap the DEK in a blob +structure. The OTPMK is unique per device and can be accessed by CAAM only. +To further add to the security of the DEK, the blob is decapsulated and +decrypted inside a secure memory partition that can only be accessed by CAAM. + +During the design of encrypted boot using DEK blob, it is necessary to inhibit +any modification or replacement of DEK blob with a counterfeit one allowing +execution of malicious code. The PRIBLOB setting in CAAM allows secure boot +software to have its own private blobs that cannot be decapsulated or +encapsulated by any other user code, including any software running in trusted +mode. + +Details about DEK Blob generation and PRIBLOB setting can be found in the +encrypted boot guide and application note AN12056[3] . + +2. Generating a PKI tree +------------------------- + +The first step is to generate the private keys and public keys certificates. +The HAB architecture is based in a Public Key Infrastructure (PKI) tree. + +The Code Signing Tools package contains an OpenSSL based key generation script +under keys/ directory. The hab4_pki_tree.sh script is able to generate a PKI +tree containing up to 4 Super Root Keys (SRK) as well as their subordinated +IMG and CSF keys. + +A new PKI tree can be generated by following the example below: + +- Generating 2048-bit PKI tree on CST v3.1.0: + + $ ./hab4_pki_tree.sh + ... + Do you want to use an existing CA key (y/n)?: n + Do you want to use Elliptic Curve Cryptography (y/n)?: n + Enter key length in bits for PKI tree: 2048 + Enter PKI tree duration (years): 5 + How many Super Root Keys should be generated? 4 + Do you want the SRK certificates to have the CA flag set? (y/n)?: y + +The diagram below illustrate the PKI tree: + + +---------+ + | CA | + +---------+ + | + | + --------------------------------------------------- + | | | | + | | | | + v v v v + +--------+ +--------+ +--------+ +--------+ + | SRK1 | | SRK2 | | SRK3 | | SRK4 | + +--------+ +--------+ +--------+ +--------+ + / \ / \ / \ / \ + v v v v v v v v + +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ + |CSF1| |IMG1| |CSF2| |IMG2| |CSF3| |IMG3| |CSF4| |IMG4| + +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ + +After running the script users can check the private keys under keys/ directory +and their respective X.509v3 public key certificates under crts/ directory. +Those files will be used during the signing and authentication process. + +2.1 Generating a fast authentication PKI tree +---------------------------------------------- + +Starting in HAB v4.1.2 users can use a single SRK key to authenticate the both +CSF and IMG contents. This reduces the number of key pair authentications that +must occur during the ROM/HAB boot stage, thus providing a faster boot process. + +The script hab4_pki_tree.sh is also able to generate a Public Key Infrastructure +(PKI) tree which only contains SRK Keys, users should not set the CA flag when +generating the SRK certificates. + +- Generating 2048-bit fast authentication PKI tree on CST v3.1.0: + + $ ./hab4_pki_tree.sh + ... + Do you want to use an existing CA key (y/n)?: n + Do you want to use Elliptic Curve Cryptography (y/n)?: n + Enter key length in bits for PKI tree: 2048 + Enter PKI tree duration (years): 5 + How many Super Root Keys should be generated? 4 + Do you want the SRK certificates to have the CA flag set? (y/n)?: n + +The diagram below illustrate the PKI tree generated: + + +---------+ + | CA | + +---------+ + | + | + --------------------------------------------------- + | | | | + | | | | + v v v v + +--------+ +--------+ +--------+ +--------+ + | SRK1 | | SRK2 | | SRK3 | | SRK4 | + +--------+ +--------+ +--------+ +--------+ + +2.2 Generating a SRK Table and SRK Hash +---------------------------------------- + +The next step is to generated the SRK Table and its respective SRK Table Hash +from the SRK public key certificates created in one of the steps above. + +In the HAB architecture, the SRK Table is included in the CSF binary and the +SRK Hash is programmed in the SoC SRK_HASH[255:0] fuses. + +On the target device during the authentication process the HAB code verify the +SRK Table against the SoC SRK_HASH fuses, in case the verification success the +root of trust is established and the HAB code can progress with the image +authentication. + +The srktool can be used for generating the SRK Table and its respective SRK +Table Hash. + +- Generating SRK Table and SRK Hash in Linux 64-bit machines: + + $ ../linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e \ + SRK_1_2_3_4_fuse.bin -d sha256 -c \ + SRK1_sha256_2048_65537_v3_ca_crt.pem,\ + SRK2_sha256_2048_65537_v3_ca_crt.pem,\ + SRK3_sha256_2048_65537_v3_ca_crt.pem,\ + SRK4_sha256_2048_65537_v3_ca_crt.pem + +The SRK_1_2_3_4_table.bin and SRK_1_2_3_4_fuse.bin files can be used in further +steps as explained in HAB guides available under doc/imx/habv4/guides/ +directory. + +References: +[1] CST: i.MX High Assurance Boot Reference Code Signing Tool. +[2] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using + HABv4" - Rev 2. +[3] AN12056: "Encrypted Boot on HABv4 and CAAM Enabled Devices" - Rev. 1 diff --git a/doc/imx/habv4/script_examples/genIVT.pl b/doc/imx/habv4/script_examples/genIVT.pl new file mode 100644 index 00000000000..84a4fcb16f3 --- /dev/null +++ b/doc/imx/habv4/script_examples/genIVT.pl @@ -0,0 +1,12 @@ +#! /usr/bin/perl -w +use strict; +open(my $out, '>:raw', 'ivt.bin') or die "Unable to open: $!"; +print $out pack("V", 0x412000D1); # Signature +print $out pack("V", 0x80800000); # Load Address (*load_address) +print $out pack("V", 0x0); # Reserved +print $out pack("V", 0x0); # DCD pointer +print $out pack("V", 0x0); # Boot Data +print $out pack("V", 0x80EEA000); # Self Pointer (*ivt) +print $out pack("V", 0x80EEA020); # CSF Pointer (*csf) +print $out pack("V", 0x0); # Reserved +close($out); diff --git a/doc/README.sdp b/doc/imx/misc/sdp.txt similarity index 82% rename from doc/README.sdp rename to doc/imx/misc/sdp.txt index 178ea688a7c..6ea6e413950 100644 --- a/doc/README.sdp +++ b/doc/imx/misc/sdp.txt @@ -16,14 +16,19 @@ protocols allow to access a USB device without OS specific drivers. The U-Boot implementation has primarly been tested using the open source imx_loader utility (https://github.com/boundarydevices/imx_usb_loader). +imx_usb_loader is a very nice tool by Boundary Devices that allow to +install U-Boot without a JTAG debugger, using the USB boot mode as +described in the manual. It is a replacement for Freescale's +MFGTOOLS. + The host side utilities are typically capable to interpret the i.MX specific image header (see doc/README.imximage). There are extensions for imx_loader's imx_usb utility which allow to interpret the U-Boot specific legacy image format (see mkimage(1)). Also the U-Boot side support beside the i.MX specific header the U-Boot legacy header. -Usage ------ +1. Using imx_usb_loader for first install with SPL +-------------------------------------------------- This implementation can be started in U-Boot using the sdp command (CONFIG_CMD_USB_SDP) or in SPL if Serial Downloader boot mode has been @@ -98,3 +103,16 @@ With that SPL and U-Boot can be downloaded with a single invocation of imx_usb without arguments: # imx_usb + +2. Using imx_usb_loader non-SPL images +--------------------------------------- + +Booting in USB mode, the i.MX6 announces itself to the Linux Host as: + +Bus 001 Device 111: ID 15a2:0061 Freescale Semiconductor, Inc. + +imx_usb_loader is able to download a single file (u-boot.imx) +to the board. For boards without SPL support, it is enough to +issue the command: + + sudo ../imx_usb_loader/imx_usb -v u-boot.imx diff --git a/doc/README.imximage b/doc/imx/mkimage/imximage.txt similarity index 100% rename from doc/README.imximage rename to doc/imx/mkimage/imximage.txt diff --git a/doc/README.mxsimage b/doc/imx/mkimage/mxsimage.txt similarity index 100% rename from doc/README.mxsimage rename to doc/imx/mkimage/mxsimage.txt diff --git a/drivers/Kconfig b/drivers/Kconfig index c2e813f5adf..95459516f1d 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -24,6 +24,8 @@ source "drivers/demo/Kconfig" source "drivers/ddr/fsl/Kconfig" +source "drivers/ddr/imx8m/Kconfig" + source "drivers/dfu/Kconfig" source "drivers/dma/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 2673428cb69..6b52d3c671c 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ +obj-$(CONFIG_ARCH_IMX8M) += ddr/imx8m/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/ diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 86ec628104b..30fa9a2f026 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -79,6 +79,12 @@ config MVSATA_IDE Enable this driver to support the SATA controller found in some Marvell SoCs, running in IDE compatibility mode using PIO. +config SATA_IMX + bool "Enable SATA driver support for i.MX8QM" + select LIBATA + help + Enable this driver to support the SATA controller found in i.MX8QM SoCs. + config SATA_MV bool "Enable Marvell SATA controller driver support" select LIBATA diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index a94c804e7a4..41aee2231b7 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_LIBATA) += libata.o obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o obj-$(CONFIG_SATA) += sata.o obj-$(CONFIG_SATA_CEVA) += sata_ceva.o +obj-$(CONFIG_SATA_IMX) += sata_imx.o obj-$(CONFIG_SATA_MV) += sata_mv.o obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o obj-$(CONFIG_SATA_SIL) += sata_sil.o diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 690d35c890d..0889d741137 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -27,6 +27,16 @@ #include #include +#ifdef CONFIG_SCSI_AHCI_PLAT +#ifdef CONFIG_FSL_HSIO +#define HW_PP2C 0xAC +#define HW_PP3C 0xB0 +#define HW_PP4C 0xB4 +#define HW_PP5C 0xB8 +#define HW_PAXIC 0xC0 +#endif +#endif + static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port); #ifndef CONFIG_DM_SCSI @@ -192,6 +202,16 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) debug("ahci_host_init: start\n"); +#ifdef CONFIG_SCSI_AHCI_PLAT +#ifdef CONFIG_FSL_HSIO + writel((1 << 28) | (1 << 24) | readl(mmio + HW_PAXIC), mmio + HW_PAXIC); + writel(0x2718461C, mmio + HW_PP2C); + writel(0x0D081907, mmio + HW_PP3C); + writel(0x06000815, mmio + HW_PP4C); + writel(0x800C96A4, mmio + HW_PP5C); +#endif +#endif + cap_save = readl(mmio + HOST_CAP); cap_save &= ((1 << 28) | (1 << 17)); cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ @@ -271,6 +291,11 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) ret = ahci_link_up(uc_priv, i); if (ret) { printf("SATA link %d timeout.\n", i); +#ifdef CONFIG_SCSI_AHCI_PLAT +#ifdef CONFIG_FSL_HSIO + return -ENODEV; +#endif +#endif continue; } else { debug("SATA link ok.\n"); diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index 480ae115afd..28e9141eedd 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -222,7 +222,7 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ timeout = 1000; - while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X) + while (!(readl(&port_mmio->serr) & SATA_PORT_SERR_DIAG_X) && --timeout) ; if (timeout <= 0) { @@ -449,7 +449,6 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); if (!mem) { - free(pp); printf("No mem for table!\n"); return -ENOMEM; } @@ -854,6 +853,9 @@ static int ahci_init_one(int pdev) struct ahci_uc_priv *uc_priv = NULL; uc_priv = malloc(sizeof(struct ahci_uc_priv)); + if (!uc_priv) + return -ENOMEM; + memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); uc_priv->dev = pdev; @@ -878,6 +880,8 @@ static int ahci_init_one(int pdev) return 0; err_out: + if (uc_priv) + free(uc_priv); return rc; } @@ -921,6 +925,9 @@ int reset_sata(int dev) while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) udelay(100); + free(uc_priv); + memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc)); + return 0; } diff --git a/drivers/ata/sata_imx.c b/drivers/ata/sata_imx.c new file mode 100644 index 00000000000..90293a6e49a --- /dev/null +++ b/drivers/ata/sata_imx.c @@ -0,0 +1,64 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include + +int sata_init(void) +{ + int ret; + u32 val, i = 0; + + printf("start sata init\n"); + writel(0x22222222, GPR_LPCG_PHYX2APB_0_APB); + writel(0x22222222, GPR_LPCG_PHYX1_APB); + + setbits_le32(0x5F130008, BIT(21)); + setbits_le32(0x5F130008, BIT(23)); + + /* PHY_MODE to SATA100Mhz ref clk */ + setbits_le32(HW_PHYX1_CTRL0_ADDR, BIT(19)); + + /* + * bit 0 rx ena, bit 1 tx ena, bit 11 fast_init, + * bit12 PHY_X1_EPCS_SEL 1. + */ + setbits_le32(HW_MISC_CTRL0_ADDR, HW_MISC_CTRL0_IOB_RXENA + | HW_MISC_CTRL0_PHY_X1_EPCS_SEL); + + clrbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_PHY_RESET); + setbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_PHY_RESET); + setbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_RESET); + udelay(1); + clrbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_RESET); + setbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_RESET); + + setbits_le32(HW_PHYX1_CTRL0_ADDR, HW_PHYX1_CTRL0_APB_RSTN); + + for (i = 0; i < 100; i++) { + val = readl(HW_PHYX1_STTS0_ADDR); + val &= HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK; + if (val == HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK) + break; + udelay(1); + } + + if (val != HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK) { + printf("TX PLL is not locked.\n"); + return -ENODEV; + } + + ret = ahci_init((void __iomem *)AHCI_BASE_ADDR); + if (ret) + return ret; + scsi_scan(1); + + return 0; +} diff --git a/drivers/core/device.c b/drivers/core/device.c index 940a153c583..dec99e77f2b 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -27,6 +27,9 @@ #include #include #include +#ifdef CONFIG_POWER_DOMAIN +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -376,6 +379,21 @@ int device_probe(struct udevice *dev) if (dev->parent && device_get_uclass_id(dev) != UCLASS_PINCTRL) pinctrl_select_state(dev, "default"); +#ifdef CONFIG_POWER_DOMAIN + if (dev->parent && device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) { + struct power_domain pd; + if (!power_domain_get(dev, &pd)) { + if (!(dev->driver->flags & DM_FLAG_IGNORE_POWER_ON)) { + ret = power_domain_on(&pd); + if (ret) { + power_domain_free(&pd); + goto fail; + } + } + } + } +#endif + ret = uclass_pre_probe_device(dev); if (ret) goto fail; diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c index 3847dd836e3..9a3b4c312af 100644 --- a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -49,12 +49,17 @@ fdt_addr_t devfdt_get_addr_index(struct udevice *dev, int index) reg += index * (na + ns); - /* - * Use the full-fledged translate function for complex - * bus setups. - */ - addr = fdt_translate_address((void *)gd->fdt_blob, - dev_of_offset(dev), reg); + if (ns) { + /* + * Use the full-fledged translate function for complex + * bus setups. + */ + addr = fdt_translate_address((void *)gd->fdt_blob, + dev_of_offset(dev), reg); + } else { + /* Non translatable if #size-cells == 0 */ + addr = fdt_read_number(reg, na); + } } else { /* * Use the "simple" translate function for less complex diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 4e4532651fc..5909a25f856 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -227,13 +227,16 @@ fdt_addr_t ofnode_get_addr_index(ofnode node, int index) uint flags; u64 size; int na; + int ns; prop_val = of_get_address(ofnode_to_np(node), index, &size, &flags); if (!prop_val) return FDT_ADDR_T_NONE; - if (IS_ENABLED(CONFIG_OF_TRANSLATE)) { + ns = of_n_size_cells(ofnode_to_np(node)); + + if (IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0) { return of_translate_address(ofnode_to_np(node), prop_val); } else { na = of_n_addr_cells(ofnode_to_np(node)); diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 1ea116be750..02f05c04ab1 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -1,5 +1,8 @@ menu "Hardware crypto devices" +config CAAM_KB_SELF_TEST + bool "Freescale CAAM SELF TEST" + source drivers/crypto/fsl/Kconfig endmenu diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index fb8c10b38c2..233d48e404e 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -6,5 +6,6 @@ # obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o +obj-$(CONFIG_FSL_CAAM_KB) += fsl_caam.o obj-y += rsa_mod_exp/ obj-y += fsl/ diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index ea878e18220..87bdde7ab86 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o obj-$(CONFIG_CMD_BLOB) += fsl_blob.o obj-$(CONFIG_CMD_DEKBLOB) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o +obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 081bce53cff..ed36482bfaf 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -739,6 +739,7 @@ struct __packed pdb_mp_sign { }; #define PDB_MP_CSEL_SHIFT 17 +#define PDB_MP_CSEL_WIDTH 4 #define PDB_MP_CSEL_P256 0x3 << PDB_MP_CSEL_SHIFT /* P-256 */ #define PDB_MP_CSEL_P384 0x4 << PDB_MP_CSEL_SHIFT /* P-384 */ #define PDB_MP_CSEL_P521 0x5 << PDB_MP_CSEL_SHIFT /* P-521 */ diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index 7dad7539813..56d29de8847 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -2,6 +2,7 @@ * caam descriptor construction helper functions * * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ * @@ -13,7 +14,7 @@ #define IMMEDIATE (1 << 23) #define CAAM_CMD_SZ sizeof(u32) -#define CAAM_PTR_SZ sizeof(dma_addr_t) +#define CAAM_PTR_SZ sizeof(u32) #define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE) #define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3) @@ -36,7 +37,7 @@ LDST_SRCDST_WORD_DECOCTRL | \ (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) union ptr_addr_t { u64 m_whole; struct { @@ -53,9 +54,9 @@ union ptr_addr_t { }; #endif -static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr) +static inline void pdb_add_ptr(u32 *offset, u32 ptr) { -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset; @@ -105,11 +106,11 @@ static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes) options); } -static inline void append_ptr(u32 *desc, dma_addr_t ptr) +static inline void append_ptr(u32 *desc, uint32_t ptr) { - dma_addr_t *offset = (dma_addr_t *)desc_end(desc); + u32 *offset = (u32 *)desc_end(desc); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset; @@ -161,7 +162,7 @@ static inline u32 *write_cmd(u32 *desc, u32 command) return desc + 1; } -static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, +static inline void append_cmd_ptr(u32 *desc, uint32_t ptr, int len, u32 command) { append_cmd(desc, command | len); @@ -169,7 +170,7 @@ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, } /* Write length after pointer, rather than inside command */ -static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr, +static inline void append_cmd_ptr_extlen(u32 *desc, uint32_t ptr, unsigned int len, u32 command) { append_cmd(desc, command); @@ -227,7 +228,7 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD) APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE) #define APPEND_CMD_PTR(cmd, op) \ -static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \ +static inline void append_##cmd(u32 *desc, uint32_t ptr, unsigned int len, \ u32 options) \ { \ PRINT_POS; \ @@ -238,7 +239,7 @@ APPEND_CMD_PTR(load, LOAD) APPEND_CMD_PTR(fifo_load, FIFO_LOAD) APPEND_CMD_PTR(fifo_store, FIFO_STORE) -static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, +static inline void append_store(u32 *desc, uint32_t ptr, unsigned int len, u32 options) { u32 cmd_src; @@ -256,7 +257,7 @@ static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, } #define APPEND_SEQ_PTR_INTLEN(cmd, op) \ -static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \ +static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, uint32_t ptr, \ unsigned int len, \ u32 options) \ { \ @@ -280,7 +281,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD); APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD); #define APPEND_CMD_PTR_EXTLEN(cmd, op) \ -static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \ +static inline void append_##cmd##_extlen(u32 *desc, uint32_t ptr, \ unsigned int len, u32 options) \ { \ PRINT_POS; \ @@ -294,7 +295,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR) * the size of its type */ #define APPEND_CMD_PTR_LEN(cmd, op, type) \ -static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \ +static inline void append_##cmd(u32 *desc, uint32_t ptr, \ type len, u32 options) \ { \ PRINT_POS; \ diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index cb315dfd89d..5d24f3339d6 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -63,6 +63,9 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); + flush_dcache_range((unsigned long)dst, + (unsigned long)dst + size); + ret = run_descriptor_jr(desc); if (ret) { @@ -128,6 +131,9 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); + flush_dcache_range((unsigned long)dst, + (unsigned long)dst + size); + ret = run_descriptor_jr(desc); if (ret) { diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 9373a399310..0797f2a3970 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -1,5 +1,6 @@ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ * @@ -93,7 +94,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf, return -EINVAL; } -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32)); #else sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0); diff --git a/drivers/crypto/fsl/fsl_mfgprot.c b/drivers/crypto/fsl/fsl_mfgprot.c new file mode 100644 index 00000000000..d08b7d153c2 --- /dev/null +++ b/drivers/crypto/fsl/fsl_mfgprot.c @@ -0,0 +1,162 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include "desc.h" +#include "desc_constr.h" +#include "jobdesc.h" +#include "jr.h" + +/* Size of MFG descriptor */ +#define MFG_PUBK_DSC_WORDS 4 +#define MFG_SIGN_DSC_WORDS 8 + +static void mfg_build_sign_dsc(u32 *dsc_ptr, const u8 *m, int size, + u8 *dgst, u8 *c, u8 *d) +{ + u32 *dsc = dsc_ptr; + struct pdb_mp_sign *pdb; + + init_job_desc_pdb(dsc, 0, sizeof(struct pdb_mp_sign)); + + pdb = (struct pdb_mp_sign *)desc_pdb(dsc); + + /* Curve */ + pdb->pdb_hdr = (PDB_MP_CSEL_P256); + + /* Message Pointer */ + pdb_add_ptr(&pdb->dma_addr_msg, virt_to_phys((void *)m)); + + /* mes-resp Pointer */ + pdb_add_ptr(&pdb->dma_addr_hash, virt_to_phys((void *)dgst)); + + /* C Pointer */ + pdb_add_ptr(&pdb->dma_addr_c_sig, virt_to_phys((void *)c)); + + /* d Pointer */ + pdb_add_ptr(&pdb->dma_addr_d_sig, virt_to_phys((void *)d)); + + /* Message Size */ + pdb->img_size = size; + + /* MP PubK generate key command */ + append_cmd(dsc, (CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | + OP_PCLID_MP_SIGN)); +} + +static void mfg_build_pubk_dsc(u32 *dsc_ptr, u8 *dst) +{ + u32 *dsc = dsc_ptr; + struct pdb_mp_pub_k *pdb; + + init_job_desc_pdb(dsc, 0, sizeof(struct pdb_mp_pub_k)); + + pdb = (struct pdb_mp_pub_k *)desc_pdb(dsc); + + /* Curve */ + pdb->pdb_hdr = (PDB_MP_CSEL_P256); + + /* Message Pointer */ + pdb_add_ptr(&pdb->dma_pkey, virt_to_phys((void *)dst)); + + /* MP Sign key command */ + append_cmd(dsc, (CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | + OP_PCLID_MP_PUB_KEY)); +} + +int gen_mppubk(u8 *dst) +{ + int size, ret; + u32 *dsc; + + /* Job Descriptor initialization */ + dsc = memalign(ARCH_DMA_MINALIGN, + sizeof(uint32_t) * MFG_PUBK_DSC_WORDS); + if (!dsc) { + debug("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + + mfg_build_pubk_dsc(dsc, dst); + + size = roundup(sizeof(uint32_t) * MFG_PUBK_DSC_WORDS, + ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dsc, (unsigned long)dsc + size); + + size = roundup(FSL_CAAM_MP_PUBK_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dst, (unsigned long)dst + size); + + /* Execute Job Descriptor */ + puts("\nGenerating Manufacturing Protection Public Key\n"); + + ret = run_descriptor_jr(dsc); + if (ret) { + debug("Error in public key generation %d\n", ret); + goto err; + } + + size = roundup(FSL_CAAM_MP_PUBK_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + size); +err: + free(dsc); + return ret; +} + +int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d) +{ + int size, ret; + u32 *dsc; + + /* Job Descriptor initialization */ + dsc = memalign(ARCH_DMA_MINALIGN, + sizeof(uint32_t) * MFG_SIGN_DSC_WORDS); + if (!dsc) { + debug("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + + mfg_build_sign_dsc(dsc, m, data_size, dgst, c, d); + + size = roundup(sizeof(uint32_t) * MFG_SIGN_DSC_WORDS, + ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dsc, (unsigned long)dsc + size); + + size = roundup(data_size, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)m, (unsigned long)m + size); + + size = roundup(FSL_CAAM_MP_MES_DGST_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dgst, (unsigned long)dgst + size); + + size = roundup(FSL_CAAM_MP_PRVK_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)c, (unsigned long)c + size); + flush_dcache_range((unsigned long)d, (unsigned long)d + size); + + /* Execute Job Descriptor */ + puts("\nSigning message with Manufacturing Protection Public Key\n"); + + ret = run_descriptor_jr(dsc); + if (ret) { + debug("Error in public key generation %d\n", ret); + goto err; + } + + size = roundup(FSL_CAAM_MP_MES_DGST_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dgst, + (unsigned long)dgst + size); + + size = roundup(FSL_CAAM_MP_PRVK_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)c, (unsigned long)c + size); + invalidate_dcache_range((unsigned long)d, (unsigned long)d + size); + +err: + free(dsc); + return ret; +} diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index aadf8511014..69cd3357833 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -3,6 +3,7 @@ * Basic job descriptor construction * * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ * @@ -14,7 +15,8 @@ #include "jobdesc.h" #include "rsa_caam.h" -#if defined(CONFIG_MX6) || defined(CONFIG_MX7) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ + defined(CONFIG_IMX8M) /*! * Secure memory run command * @@ -162,9 +164,10 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt, append_u32(desc, aad_w2); - append_cmd_ptr(desc, (dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR); + append_cmd_ptr(desc, (uint32_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR); - append_cmd_ptr(desc, (dma_addr_t)dek_blob + 8, out_sz, CMD_SEQ_OUT_PTR); + append_cmd_ptr(desc, (uint32_t)((ulong)dek_blob + 8), + out_sz, CMD_SEQ_OUT_PTR); append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB | OP_PCLID_SECMEM); @@ -180,7 +183,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc, /* SHA 256 , output is of length 32 words */ uint32_t storelen = alg_size; u32 options; - dma_addr_t dma_addr_in, dma_addr_out; + u32 dma_addr_in, dma_addr_out; dma_addr_in = virt_to_phys((void *)msg); dma_addr_out = virt_to_phys((void *)digest); @@ -209,7 +212,7 @@ void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *plain_txt, uint8_t *enc_blob, uint32_t in_sz) { - dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; /* output blob will have 32 bytes key blob in beginning and * 16 byte HMAC identifier at end of data blob */ @@ -234,7 +237,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *enc_blob, uint8_t *plain_txt, uint32_t out_sz) { - dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE; @@ -290,7 +293,7 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, struct pk_in_params *pkin, uint8_t *out, uint32_t out_siz) { - dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out; + u32 dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out; dma_addr_e = virt_to_phys((void *)pkin->e); dma_addr_a = virt_to_phys((void *)pkin->a); diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 34bd070426b..d6d0b3f21eb 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -1,5 +1,6 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ * @@ -28,10 +29,10 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { }; #define SEC_ADDR(idx) \ - ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) + (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) #define SEC_JR0_ADDR(idx) \ - (SEC_ADDR(idx) + \ + (ulong)(SEC_ADDR(idx) + \ (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET)) struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC]; @@ -79,13 +80,13 @@ static void jr_initregs(uint8_t sec_idx) phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring); phys_addr_t op_base = virt_to_phys((void *)jr->output_ring); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) sec_out32(®s->irba_h, ip_base >> 32); #else sec_out32(®s->irba_h, 0x0); #endif sec_out32(®s->irba_l, (uint32_t)ip_base); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) sec_out32(®s->orba_h, op_base >> 32); #else sec_out32(®s->orba_h, 0x0); @@ -111,7 +112,7 @@ static int jr_init(uint8_t sec_idx) jr->liodn = DEFAULT_JR_LIODN; #endif jr->size = JR_SIZE; - jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, + jr->input_ring = (uint32_t *)memalign(ARCH_DMA_MINALIGN, JR_SIZE * sizeof(dma_addr_t)); if (!jr->input_ring) return -1; @@ -188,7 +189,7 @@ static int jr_enqueue(uint32_t *desc_addr, uint32_t desc_word; int length = desc_len(desc_addr); int i; -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) uint32_t *addr_hi, *addr_lo; #endif @@ -215,7 +216,7 @@ static int jr_enqueue(uint32_t *desc_addr, sizeof(struct jr_info), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* Write the 64 bit Descriptor address on Input Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -264,7 +265,7 @@ static int jr_dequeue(int sec_idx) int idx, i, found; void (*callback)(uint32_t status, void *arg); void *arg = NULL; -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) uint32_t *addr_hi, *addr_lo; #else uint32_t *addr; @@ -276,7 +277,7 @@ static int jr_dequeue(int sec_idx) found = 0; phys_addr_t op_desc; - #ifdef CONFIG_PHYS_64BIT + #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* Read the 64 bit Descriptor address from Output Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -349,8 +350,8 @@ static void desc_done(uint32_t status, void *arg) static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) { - unsigned long long timeval = get_ticks(); - unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); + unsigned long long timeval = 0; + unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT; struct result op; int ret = 0; @@ -363,9 +364,10 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) goto out; } - timeval = get_ticks(); - timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); while (op.done != 1) { + udelay(1); + timeval += 1; + ret = jr_dequeue(sec_idx); if (ret) { debug("Error in SEC deq\n"); @@ -373,7 +375,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) goto out; } - if ((get_ticks() - timeval) > timeout) { + if (timeval > timeout) { debug("SEC Dequeue timed out\n"); ret = JQ_DEQ_TO_ERR; goto out; @@ -579,8 +581,6 @@ int sec_init_idx(uint8_t sec_idx) { ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); uint32_t mcr = sec_in32(&sec->mcfgr); - uint32_t jrown_ns; - int i; int ret = 0; #ifdef CONFIG_FSL_CORENET @@ -608,7 +608,7 @@ int sec_init_idx(uint8_t sec_idx) mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); #endif -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) mcr |= (1 << MCFGR_PS_SHIFT); #endif sec_out32(&sec->mcfgr, mcr); @@ -636,13 +636,6 @@ int sec_init_idx(uint8_t sec_idx) #endif #endif - /* Set ownership of job rings to non-TrustZone mode by default */ - for (i = 0; i < ARRAY_SIZE(sec->jrliodnr); i++) { - jrown_ns = sec_in32(&sec->jrliodnr[i].ms); - jrown_ns |= JROWN_NS | JRMID_NS; - sec_out32(&sec->jrliodnr[i].ms, jrown_ns); - } - ret = jr_init(sec_idx); if (ret < 0) { printf("SEC initialization failed\n"); diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index ef515e74f8c..b5225064711 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -1,5 +1,6 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ * @@ -11,8 +12,8 @@ #include #define JR_SIZE 4 -/* Timeout currently defined as 90 sec */ -#define CONFIG_SEC_DEQ_TIMEOUT 90000000U +/* Timeout currently defined as 10 sec */ +#define CONFIG_USEC_DEQ_TIMEOUT 10000000U #define DEFAULT_JR_ID 0 #define DEFAULT_JR_LIODN 0 @@ -34,8 +35,6 @@ #define JRNSLIODN_MASK 0x0fff0000 #define JRSLIODN_SHIFT 0 #define JRSLIODN_MASK 0x00000fff -#define JROWN_NS 0x00000008 -#define JRMID_NS 0x00000001 #define JQ_DEQ_ERR -1 #define JQ_DEQ_TO_ERR -2 @@ -44,8 +43,8 @@ #define RNG4_MAX_HANDLES 2 struct op_ring { - phys_addr_t desc; - uint32_t status; + u32 desc; + u32 status; } __packed; struct jr_info { @@ -86,7 +85,7 @@ struct jobring { * by SEC */ /*Circular Ring of i/p descriptors */ - dma_addr_t *input_ring; + u32 *input_ring; /* Circular Ring of o/p descriptors */ /* Circula Ring containing info regarding descriptors in i/p * and o/p ring diff --git a/drivers/crypto/fsl_caam.c b/drivers/crypto/fsl_caam.c new file mode 100644 index 00000000000..2ed4951cb4e --- /dev/null +++ b/drivers/crypto/fsl_caam.c @@ -0,0 +1,855 @@ +/* + * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * Copyright 2018 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#ifndef CONFIG_ARCH_MX7ULP +#include +#else +#include +#endif /* CONFIG_ARCH_MX7ULP */ +#include "fsl_caam_internal.h" +#include "fsl/desc_constr.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int do_cfg_jrqueue(void); +static int do_job(u32 *desc); +#ifndef CONFIG_ARCH_IMX8 +static void rng_init(void); +static void caam_clock_enable(void); +static int jr_reset(void); +#endif +#ifdef CONFIG_CAAM_KB_SELF_TEST +static void caam_test(void); +#endif + +/* + * Structures + */ +/* Definition of input ring object */ +struct inring_entry { + u32 desc; /* Pointer to input descriptor */ +}; + +/* Definition of output ring object */ +struct outring_entry { + u32 desc; /* Pointer to output descriptor */ + u32 status; /* Status of the Job Ring */ +}; + +/* Main job ring data structure */ +struct jr_data_st { + struct inring_entry *inrings; + struct outring_entry *outrings; + u32 status; /* Ring buffers init status */ + u32 *desc; /* Pointer to output descriptor */ + u32 raw_addr[DESC_MAX_SIZE * 2]; +}; + +/* + * Global variables + */ +static struct jr_data_st g_jrdata = {0, 0, 0xFFFFFFFF}; + +static u8 skeymod[] = { + 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, + 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 +}; + +/* + * Local functions + */ +static void dump_error(void) +{ + int i; + + debug("Dump CAAM Error\n"); + debug("MCFGR 0x%08X\n", __raw_readl(CAAM_MCFGR)); + debug("FAR 0x%08X\n", __raw_readl(CAAM_FAR)); + debug("FAMR 0x%08X\n", __raw_readl(CAAM_FAMR)); + debug("FADR 0x%08X\n", __raw_readl(CAAM_FADR)); + debug("CSTA 0x%08X\n", __raw_readl(CAAM_STA)); + debug("RTMCTL 0x%X\n", __raw_readl(CAAM_RTMCTL)); + debug("RTSTATUS 0x%X\n", __raw_readl(CAAM_RTSTATUS)); + debug("RDSTA 0x%X\n", __raw_readl(CAAM_RDSTA)); + + for (i = 0; i < desc_len(g_jrdata.desc); i++) + debug("desc[%d]: 0x%08x\n", i, g_jrdata.desc[i]); +} + +/*! + * Secure memory run command. + * + * @param sec_mem_cmd Secure memory command register + * @return cmd_status Secure memory command status register + */ +u32 secmem_set_cmd_1(u32 sec_mem_cmd) +{ + u32 temp_reg; + __raw_writel(sec_mem_cmd, CAAM_SMCJR0); + do { + temp_reg = __raw_readl(CAAM_SMCSJR0); + } while (temp_reg & CMD_COMPLETE); + + return temp_reg; +} + + +/*! + * Use CAAM to decapsulate a blob to secure memory. + * Such blob of secret key cannot be read once decrypted, + * but can still be used for enc/dec operation of user's data. + * + * @param blob_addr Location address of the blob. + * + * @return SUCCESS or ERROR_XXX + */ +u32 caam_decap_blob(u32 plain_text, u32 blob_addr, u32 size) +{ + u32 ret = SUCCESS; + u32 key_sz = sizeof(skeymod); + u32 *decap_desc = g_jrdata.desc; + + /* prepare job descriptor */ + init_job_desc(decap_desc, 0); + append_load(decap_desc, PTR2CAAMDMA(skeymod), key_sz, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); + append_seq_in_ptr_intlen(decap_desc, blob_addr, size + CAAM_PAD_LEN, 0); + append_seq_out_ptr_intlen(decap_desc, plain_text, size, 0); + append_operation(decap_desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB); + + flush_dcache_range((uintptr_t)blob_addr & ALIGN_MASK, + ((uintptr_t)blob_addr & ALIGN_MASK) + + ROUND(size + CAAM_PAD_LEN, ARCH_DMA_MINALIGN)); + flush_dcache_range((uintptr_t)plain_text & ALIGN_MASK, + (plain_text & ALIGN_MASK) + + ROUND(size, ARCH_DMA_MINALIGN)); + + /* Run descriptor with result written to blob buffer */ + ret = do_job(decap_desc); + + if (ret != SUCCESS) { + printf("Error: blob decap job failed 0x%x\n", ret); + } + + return ret; +} + +/*! + * Use CAAM to generate a blob. + * + * @param plain_data_addr Location address of the plain data. + * @param blob_addr Location address of the blob. + * + * @return SUCCESS or ERROR_XXX + */ +u32 caam_gen_blob(u32 plain_data_addr, u32 blob_addr, u32 size) +{ + u32 ret = SUCCESS; + u32 key_sz = sizeof(skeymod); + u32 *encap_desc = g_jrdata.desc; + /* Buffer to hold the resulting blob */ + u8 *blob = (u8 *)CAAMDMA2PTR(blob_addr); + + /* initialize the blob array */ + memset(blob,0,size); + + /* prepare job descriptor */ + init_job_desc(encap_desc, 0); + append_load(encap_desc, PTR2CAAMDMA(skeymod), key_sz, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); + append_seq_in_ptr_intlen(encap_desc, plain_data_addr, size, 0); + append_seq_out_ptr_intlen(encap_desc, PTR2CAAMDMA(blob), size + CAAM_PAD_LEN, 0); + append_operation(encap_desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB); + + flush_dcache_range((uintptr_t)plain_data_addr & ALIGN_MASK, + (plain_data_addr & ALIGN_MASK) + + ROUND(size, ARCH_DMA_MINALIGN)); + flush_dcache_range((uintptr_t)blob & ALIGN_MASK, + ((uintptr_t)blob & ALIGN_MASK) + + ROUND(size + CAAM_PAD_LEN, ARCH_DMA_MINALIGN)); + + ret = do_job(encap_desc); + + if (ret != SUCCESS) { + printf("Error: blob encap job failed 0x%x\n", ret); + } + + return ret; +} + +u32 caam_hwrng(u8 *output_ptr, u32 output_len) +{ + u32 ret = SUCCESS; + u32 *hwrng_desc = g_jrdata.desc; + /* Buffer to hold the resulting output*/ + u8 *output = (u8 *)output_ptr; + + /* initialize the output array */ + memset(output,0,output_len); + + /* prepare job descriptor */ + init_job_desc(hwrng_desc, 0); + append_operation(hwrng_desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG); + append_fifo_store(hwrng_desc, PTR2CAAMDMA(output), + output_len, FIFOST_TYPE_RNGSTORE); + + /* flush cache */ + flush_dcache_range((uintptr_t)hwrng_desc & ALIGN_MASK, + ((uintptr_t)hwrng_desc & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + + flush_dcache_range((uintptr_t)output & ALIGN_MASK, + ((uintptr_t)output & ALIGN_MASK) + + ROUND(2 * output_len, ARCH_DMA_MINALIGN)); + + ret = do_job(hwrng_desc); + + if (ret != SUCCESS) { + printf("Error: RNG generate failed 0x%x\n", ret); + } + + return ret; +} + +/*! + * Initialize the CAAM. + * + */ +void caam_open(void) +{ + int ret; + + /* switch on the clock */ + /* for imx8, the CAAM initialization should have been done + * in seco, so we should skip this part. + */ +#ifndef CONFIG_ARCH_IMX8 + u32 temp_reg; + + caam_clock_enable(); + + /* reset the CAAM */ + temp_reg = __raw_readl(CAAM_MCFGR) | + CAAM_MCFGR_DMARST | CAAM_MCFGR_SWRST; + __raw_writel(temp_reg, CAAM_MCFGR); + while (__raw_readl(CAAM_MCFGR) & CAAM_MCFGR_DMARST) + ; + + jr_reset(); + + ret = do_cfg_jrqueue(); + + if (ret != SUCCESS) { + printf("Error CAAM JR initialization\n"); + return; + } + + /* Check if the RNG is already instantiated */ + temp_reg = __raw_readl(CAAM_RDSTA); + if (temp_reg == (RDSTA_IF0 | RDSTA_IF1 | RDSTA_SKVN)) { + printf("RNG already instantiated 0x%X\n", temp_reg); + return; + } + rng_init(); +#else + ret = do_cfg_jrqueue(); + + if (ret != SUCCESS) { + printf("Error CAAM JR initialization\n"); + return; + } +#endif + +#ifdef CONFIG_CAAM_KB_SELF_TEST + caam_test(); +#endif +} + +/* + * Descriptors to instantiate SH0, SH1, load the keys + */ +static const u32 rng_inst_sh0_desc[] = { + /* Header, don't setup the size */ + CAAM_HDR_CTYPE | CAAM_HDR_ONE | CAAM_HDR_START_INDEX(0), + /* Operation instantiation (sh0) */ + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | ALGO_RNG_SH(0) | ALGO_RNG_INSTANTIATE, +}; + +static const u32 rng_inst_sh1_desc[] = { + /* wait for done - Jump to next entry */ + CAAM_C1_JUMP | CAAM_JUMP_LOCAL | CAAM_JUMP_TST_ALL_COND_TRUE + | CAAM_JUMP_OFFSET(1), + /* Clear written register (write 1) */ + CAAM_C0_LOAD_IMM | CAAM_DST_CLEAR_WRITTEN | sizeof(u32), + 0x00000001, + /* Operation instantiation (sh1) */ + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | ALGO_RNG_SH(1) + | ALGO_RNG_INSTANTIATE, +}; + +static const u32 rng_inst_load_keys[] = { + /* wait for done - Jump to next entry */ + CAAM_C1_JUMP | CAAM_JUMP_LOCAL | CAAM_JUMP_TST_ALL_COND_TRUE + | CAAM_JUMP_OFFSET(1), + /* Clear written register (write 1) */ + CAAM_C0_LOAD_IMM | CAAM_DST_CLEAR_WRITTEN | sizeof(u32), + 0x00000001, + /* Generate the Key */ + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | BM_ALGO_RNG_SK | ALGO_RNG_GENERATE, +}; + +static int do_job(u32 *desc) +{ + int ret; + phys_addr_t p_desc = virt_to_phys(desc); + + /* for imx8, JR0 and JR1 will be assigned to seco, so we use + * the JR3 instead. + */ +#ifndef CONFIG_ARCH_IMX8 + if (__raw_readl(CAAM_IRSAR0) == 0) +#else + if (__raw_readl(CAAM_IRSAR3) == 0) +#endif + return ERROR_ANY; + g_jrdata.inrings[0].desc = p_desc; + + flush_dcache_range((uintptr_t)g_jrdata.inrings & ALIGN_MASK, + ((uintptr_t)g_jrdata.inrings & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + flush_dcache_range((uintptr_t)desc & ALIGN_MASK, + ((uintptr_t)desc & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + + flush_dcache_range((uintptr_t)g_jrdata.outrings & ALIGN_MASK, + ((uintptr_t)g_jrdata.outrings & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + + /* Inform HW that a new JR is available */ +#ifndef CONFIG_ARCH_IMX8 + __raw_writel(1, CAAM_IRJAR0); + while (__raw_readl(CAAM_ORSFR0) == 0) + ; +#else + __raw_writel(1, CAAM_IRJAR3); + while (__raw_readl(CAAM_ORSFR3) == 0) + ; +#endif + + if (PTR2CAAMDMA(desc) == g_jrdata.outrings[0].desc) { + ret = g_jrdata.outrings[0].status; + } else { + dump_error(); + ret = ERROR_ANY; + } + + /* Acknowledge interrupt */ +#ifndef CONFIG_ARCH_IMX8 + setbits_le32(CAAM_JRINTR0, JRINTR_JRI); + /* Remove the JR from the output list even if no JR caller found */ + __raw_writel(1, CAAM_ORJRR0); +#else + setbits_le32(CAAM_JRINTR3, JRINTR_JRI); + /* Remove the JR from the output list even if no JR caller found */ + __raw_writel(1, CAAM_ORJRR3); +#endif + + return ret; +} + +static int do_cfg_jrqueue(void) +{ + u32 value = 0; + phys_addr_t ip_base; + phys_addr_t op_base; + + /* check if already configured after relocation */ + if (g_jrdata.status == RING_RELOC_INIT) + return 0; + + /* + * jr configuration needs to be updated once, after relocation to ensure + * using the right buffers. + * When buffers are updated after relocation the flag RING_RELOC_INIT + * is used to prevent extra updates + */ + if (gd->flags & GD_FLG_RELOC) { + g_jrdata.inrings = (struct inring_entry *) + memalign(ARCH_DMA_MINALIGN, + ARCH_DMA_MINALIGN); + g_jrdata.outrings = (struct outring_entry *) + memalign(ARCH_DMA_MINALIGN, + ARCH_DMA_MINALIGN); + g_jrdata.desc = (u32 *) + memalign(ARCH_DMA_MINALIGN, ARCH_DMA_MINALIGN); + g_jrdata.status = RING_RELOC_INIT; + } else { + u32 align_idx = 0; + u32 *addr; + +#if defined(CONFIG_SPL_BUILD) && CONFIG_VAL(SYS_MALLOC_F_LEN) + ulong maddr = (ulong)malloc(DESC_MAX_SIZE * 2 + 8); + addr = (u32*)ALIGN(maddr, 8); +#else + addr = g_jrdata.raw_addr; +#endif + /* Ensure 64bits buffers addresses alignment */ + if ((uintptr_t)addr & 0x7) + align_idx = 1; + g_jrdata.inrings = (struct inring_entry *) + (&addr[align_idx]); + g_jrdata.outrings = (struct outring_entry *) + (&addr[align_idx + 2]); + g_jrdata.desc = (u32 *)(&addr[align_idx + 4]); + g_jrdata.status = RING_EARLY_INIT; + } + + if (!g_jrdata.inrings || !g_jrdata.outrings) + return ERROR_ANY; + + /* Configure the HW Job Rings */ + ip_base = virt_to_phys((void *)g_jrdata.inrings); + op_base = virt_to_phys((void *)g_jrdata.outrings); + + /* for imx8, JR0 and JR1 will be assigned to seco, so we use + * the JR3 instead. + */ +#ifndef CONFIG_ARCH_IMX8 + __raw_writel(ip_base, CAAM_IRBAR0); + __raw_writel(1, CAAM_IRSR0); + + __raw_writel(op_base, CAAM_ORBAR0); + __raw_writel(1, CAAM_ORSR0); + + setbits_le32(CAAM_JRINTR0, JRINTR_JRI); +#else + __raw_writel(ip_base, CAAM_IRBAR3); + __raw_writel(1, CAAM_IRSR3); + + __raw_writel(op_base, CAAM_ORBAR3); + __raw_writel(1, CAAM_ORSR3); + + setbits_le32(CAAM_JRINTR3, JRINTR_JRI); +#endif + + /* + * Configure interrupts but disable it: + * Optimization to generate an interrupt either when there are + * half of the job done or when there is a job done and + * 10 clock cycles elapse without new job complete + */ + value = 10 << BS_JRCFGR_LS_ICTT; + value |= (1 << BS_JRCFGR_LS_ICDCT) & BM_JRCFGR_LS_ICDCT; + value |= BM_JRCFGR_LS_ICEN; + value |= BM_JRCFGR_LS_IMSK; +#ifndef CONFIG_ARCH_IMX8 + __raw_writel(value, CAAM_JRCFGR0_LS); + + /* Enable deco watchdog */ + setbits_le32(CAAM_MCFGR, BM_MCFGR_WDE); +#else + __raw_writel(value, CAAM_JRCFGR3_LS); +#endif + + return 0; +} + +#ifndef CONFIG_ARCH_IMX8 +static void do_clear_rng_error(void) +{ + u32 val; + + val = __raw_readl(CAAM_RTMCTL); + + if (val & (RTMCTL_ERR | RTMCTL_FCT_FAIL)) { + setbits_le32(CAAM_RTMCTL, RTMCTL_ERR); + val = __raw_readl(CAAM_RTMCTL); + } +} + +static void do_inst_desc(u32 *desc, u32 status) +{ + u32 *pdesc = desc; + u8 desc_len; + bool add_sh0 = false; + bool add_sh1 = false; + bool load_keys = false; + + /* + * Modify the the descriptor to remove if necessary: + * - The key loading + * - One of the SH already instantiated + */ + desc_len = RNG_DESC_SH0_SIZE; + if ((status & RDSTA_IF0) != RDSTA_IF0) + add_sh0 = true; + + if ((status & RDSTA_IF1) != RDSTA_IF1) { + add_sh1 = true; + if (add_sh0) + desc_len += RNG_DESC_SH1_SIZE; + } + + if ((status & RDSTA_SKVN) != RDSTA_SKVN) { + load_keys = true; + desc_len += RNG_DESC_KEYS_SIZE; + } + + /* Copy the SH0 descriptor anyway */ + memcpy(pdesc, rng_inst_sh0_desc, sizeof(rng_inst_sh0_desc)); + pdesc += RNG_DESC_SH0_SIZE; + + if (load_keys) { + debug("RNG - Load keys\n"); + memcpy(pdesc, rng_inst_load_keys, sizeof(rng_inst_load_keys)); + pdesc += RNG_DESC_KEYS_SIZE; + } + + if (add_sh1) { + if (add_sh0) { + debug("RNG - Instantiation of SH0 and SH1\n"); + /* Add the sh1 descriptor */ + memcpy(pdesc, rng_inst_sh1_desc, + sizeof(rng_inst_sh1_desc)); + } else { + debug("RNG - Instantiation of SH1 only\n"); + /* Modify the SH0 descriptor to instantiate only SH1 */ + desc[1] &= ~BM_ALGO_RNG_SH; + desc[1] |= ALGO_RNG_SH(1); + } + } + + /* Setup the descriptor size */ + desc[0] &= ~(0x3F); + desc[0] |= CAAM_HDR_DESCLEN(desc_len); +} + +static void kick_trng(u32 ent_delay) +{ + u32 samples = 512; /* number of bits to generate and test */ + u32 mono_min = 195; + u32 mono_max = 317; + u32 mono_range = mono_max - mono_min; + u32 poker_min = 1031; + u32 poker_max = 1600; + u32 poker_range = poker_max - poker_min + 1; + u32 retries = 2; + u32 lrun_max = 32; + s32 run_1_min = 27; + s32 run_1_max = 107; + s32 run_1_range = run_1_max - run_1_min; + s32 run_2_min = 7; + s32 run_2_max = 62; + s32 run_2_range = run_2_max - run_2_min; + s32 run_3_min = 0; + s32 run_3_max = 39; + s32 run_3_range = run_3_max - run_3_min; + s32 run_4_min = -1; + s32 run_4_max = 26; + s32 run_4_range = run_4_max - run_4_min; + s32 run_5_min = -1; + s32 run_5_max = 18; + s32 run_5_range = run_5_max - run_5_min; + s32 run_6_min = -1; + s32 run_6_max = 17; + s32 run_6_range = run_6_max - run_6_min; + u32 val; + + /* Put RNG in program mode */ + /* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to + * properly invalidate the entropy in the entropy register and + * force re-generation. + */ + setbits_le32(CAAM_RTMCTL, RTMCTL_PGM | RTMCTL_ACC); + + /* Configure the RNG Entropy Delay + * Performance-wise, it does not make sense to + * set the delay to a value that is lower + * than the last one that worked (i.e. the state handles + * were instantiated properly. Thus, instead of wasting + * time trying to set the values controlling the sample + * frequency, the function simply returns. + */ + val = __raw_readl(CAAM_RTSDCTL); + val &= BM_TRNG_ENT_DLY; + val >>= BS_TRNG_ENT_DLY; + if (ent_delay < val) { + /* Put RNG4 into run mode */ + clrbits_le32(CAAM_RTMCTL, RTMCTL_PGM | RTMCTL_ACC); + return; + } + + val = (ent_delay << BS_TRNG_ENT_DLY) | samples; + __raw_writel(val, CAAM_RTSDCTL); + + /* min. freq. count, equal to 1/2 of the entropy sample length */ + __raw_writel(ent_delay >> 1, CAAM_RTFRQMIN); + + /* max. freq. count, equal to 32 times the entropy sample length */ + __raw_writel(ent_delay << 5, CAAM_RTFRQMAX); + + __raw_writel((retries << 16) | lrun_max, CAAM_RTSCMISC); + __raw_writel(poker_max, CAAM_RTPKRMAX); + __raw_writel(poker_range, CAAM_RTPKRRNG); + __raw_writel((mono_range << 16) | mono_max, CAAM_RTSCML); + __raw_writel((run_1_range << 16) | run_1_max, CAAM_RTSCR1L); + __raw_writel((run_2_range << 16) | run_2_max, CAAM_RTSCR2L); + __raw_writel((run_3_range << 16) | run_3_max, CAAM_RTSCR3L); + __raw_writel((run_4_range << 16) | run_4_max, CAAM_RTSCR4L); + __raw_writel((run_5_range << 16) | run_5_max, CAAM_RTSCR5L); + __raw_writel((run_6_range << 16) | run_6_max, CAAM_RTSCR6PL); + + val = __raw_readl(CAAM_RTMCTL); + /* + * Select raw sampling in both entropy shifter + * and statistical checker + */ + val &= ~BM_TRNG_SAMP_MODE; + val |= TRNG_SAMP_MODE_RAW_ES_SC; + /* Put RNG4 into run mode */ + val &= ~(RTMCTL_PGM | RTMCTL_ACC); +/*test with sample mode only */ + __raw_writel(val, CAAM_RTMCTL); + + /* Clear the ERR bit in RTMCTL if set. The TRNG error can occur when the + * RNG clock is not within 1/2x to 8x the system clock. + * This error is possible if ROM code does not initialize the system PLLs + * immediately after PoR. + */ + /* setbits_le32(CAAM_RTMCTL, RTMCTL_ERR); */ +} + +static int do_instantiation(void) +{ + int ret = ERROR_ANY; + u32 cha_vid_ls; + u32 ent_delay; + u32 status; + + if (!g_jrdata.desc) { + printf("%d: CAAM Descriptor allocation error\n", __LINE__); + return ERROR_ANY; + } + + cha_vid_ls = __raw_readl(CAAM_CHAVID_LS); + + /* + * If SEC has RNG version >= 4 and RNG state handle has not been + * already instantiated, do RNG instantiation + */ + if (((cha_vid_ls & BM_CHAVID_LS_RNGVID) >> BS_CHAVID_LS_RNGVID) < 4) { + printf("%d: RNG already instantiated\n", __LINE__); + return 0; + } + + ent_delay = TRNG_SDCTL_ENT_DLY_MIN; + + do { + /* Read the CAAM RNG status */ + status = __raw_readl(CAAM_RDSTA); + + if ((status & RDSTA_IF0) != RDSTA_IF0) { + /* Configure the RNG entropy delay */ + kick_trng(ent_delay); + ent_delay += 400; + } + + do_clear_rng_error(); + + if ((status & (RDSTA_IF0 | RDSTA_IF1)) != + (RDSTA_IF0 | RDSTA_IF1)) { + /* Prepare the instantiation descriptor */ + do_inst_desc(g_jrdata.desc, status); + + /* Run Job */ + ret = do_job(g_jrdata.desc); + + if (ret == ERROR_ANY) { + /* CAAM JR failure ends here */ + printf("RNG Instantiation error\n"); + goto end_instantation; + } + } else { + ret = SUCCESS; + printf("RNG instantiation done (%d)\n", ent_delay); + goto end_instantation; + } + } while (ent_delay < TRNG_SDCTL_ENT_DLY_MAX); + + printf("RNG Instantation Failure - Entropy delay (%d)\n", ent_delay); + ret = ERROR_ANY; + +end_instantation: + return ret; +} + +static void rng_init(void) +{ + int ret; + + ret = jr_reset(); + if (ret != SUCCESS) { + printf("Error CAAM JR reset\n"); + return; + } + + ret = do_instantiation(); + + if (ret != SUCCESS) + printf("Error do_instantiation\n"); + + jr_reset(); + + return; +} + +static void caam_clock_enable(void) +{ +#if defined(CONFIG_ARCH_MX6) + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = __raw_readl(&mxc_ccm->CCGR0); + + reg |= (MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK); + + __raw_writel(reg, &mxc_ccm->CCGR0); + +#ifndef CONFIG_MX6UL + /* EMI slow clk */ + reg = __raw_readl(&mxc_ccm->CCGR6); + reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; + + __raw_writel(reg, &mxc_ccm->CCGR6); +#endif + +#elif defined(CONFIG_ARCH_MX7) + HW_CCM_CCGR_SET(36, MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK); +#elif defined(CONFIG_ARCH_MX7ULP) + pcc_clock_enable(PER_CLK_CAAM, true); +#endif +} + +static int jr_reset(void) +{ + /* + * Function reset the Job Ring HW + * Reset is done in 2 steps: + * - Flush all pending jobs (Set RESET bit) + * - Reset the Job Ring (Set RESET bit second time) + */ + u16 timeout = 10000; + u32 reg_val; + + /* Mask interrupts to poll for reset completion status */ + setbits_le32(CAAM_JRCFGR0_LS, BM_JRCFGR_LS_IMSK); + + /* Initiate flush (required prior to reset) */ + __raw_writel(JRCR_RESET, CAAM_JRCR0); + do { + reg_val = __raw_readl(CAAM_JRINTR0); + reg_val &= BM_JRINTR_HALT; + } while ((reg_val == JRINTR_HALT_ONGOING) && --timeout); + + if (!timeout || reg_val != JRINTR_HALT_DONE) { + printf("Failed to flush job ring\n"); + return ERROR_ANY; + } + + /* Initiate reset */ + timeout = 100; + __raw_writel(JRCR_RESET, CAAM_JRCR0); + do { + reg_val = __raw_readl(CAAM_JRCR0); + } while ((reg_val & JRCR_RESET) && --timeout); + + if (!timeout) { + printf("Failed to reset job ring\n"); + return ERROR_ANY; + } + + return 0; +} + +#endif /* !CONFIG_ARCH_IMX8 */ + +#ifdef CONFIG_CAAM_KB_SELF_TEST +static void caam_hwrng_test(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, out1, 32); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, out2, 32); + + memset(out1, 0x00, sizeof(out1)); + memset(out2, 0x00, sizeof(out2)); + + caam_hwrng(out1, sizeof(out1)); + caam_hwrng(out2, sizeof(out2)); + + if (memcmp(out1, out2, sizeof(out1))) + printf("caam hwrng test pass!\n"); + else + printf("caam hwrng test fail!\n"); +} + +static void caam_blob_test(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, plain, 32); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, blob, 128); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, plain_bak, 32); + + memset(plain, 0x00, sizeof(plain)); + memset(plain_bak, 0xff, sizeof(plain_bak)); + + /* encapsulate blob */ + caam_gen_blob((ulong)plain, (ulong)blob, sizeof(plain)); + + /* decapsulate blob */ + caam_decap_blob((ulong)plain_bak, (ulong)blob, sizeof(plain_bak)); + + if (memcmp(plain, plain_bak, sizeof(plain))) + printf("caam blob test fail!\n"); + else + printf("caam blob test pass!\n"); +} + +static void caam_test(void) +{ + caam_hwrng_test(); + caam_blob_test(); +} +#endif /* CONFIG_CAAM_KB_SELF_TEST */ diff --git a/drivers/crypto/fsl_caam_internal.h b/drivers/crypto/fsl_caam_internal.h new file mode 100644 index 00000000000..e922d505c83 --- /dev/null +++ b/drivers/crypto/fsl_caam_internal.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * Copyright 2018 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CAAM_INTERNAL_H__ +#define __CAAM_INTERNAL_H__ + +/* 4kbyte pages */ +#define CAAM_SEC_RAM_START_ADDR CAAM_ARB_BASE_ADDR + +#define SEC_MEM_PAGE0 CAAM_SEC_RAM_START_ADDR +#define SEC_MEM_PAGE1 (CAAM_SEC_RAM_START_ADDR + 0x1000) +#define SEC_MEM_PAGE2 (CAAM_SEC_RAM_START_ADDR + 0x2000) +#define SEC_MEM_PAGE3 (CAAM_SEC_RAM_START_ADDR + 0x3000) + +/* Configuration and special key registers */ +#define CAAM_MCFGR (CONFIG_SYS_FSL_SEC_ADDR + 0x0004) +#define CAAM_SCFGR (CONFIG_SYS_FSL_SEC_ADDR + 0x000c) +#define CAAM_JR0MIDR (CONFIG_SYS_FSL_SEC_ADDR + 0x0010) +#define CAAM_JR1MIDR (CONFIG_SYS_FSL_SEC_ADDR + 0x0018) +#define CAAM_DECORR (CONFIG_SYS_FSL_SEC_ADDR + 0x009c) +#define CAAM_DECO0MID (CONFIG_SYS_FSL_SEC_ADDR + 0x00a0) +#define CAAM_DAR (CONFIG_SYS_FSL_SEC_ADDR + 0x0120) +#define CAAM_DRR (CONFIG_SYS_FSL_SEC_ADDR + 0x0124) +#define CAAM_JDKEKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0400) +#define CAAM_TDKEKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0420) +#define CAAM_TDSKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0440) +#define CAAM_SKNR (CONFIG_SYS_FSL_SEC_ADDR + 0x04e0) +#define CAAM_SMSTA (CONFIG_SYS_FSL_SEC_ADDR + 0x0FB4) +#define CAAM_STA (CONFIG_SYS_FSL_SEC_ADDR + 0x0FD4) +#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC) +#define CAAM_CHAVID_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x0FEC) +#define CAAM_FAR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FC0) +#define CAAM_FAMR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FC8) +#define CAAM_FADR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FCC) + +/* RNG registers */ +#define CAAM_RTMCTL (CONFIG_SYS_FSL_SEC_ADDR + 0x0600) +#define CAAM_RTSCMISC (CONFIG_SYS_FSL_SEC_ADDR + 0x0604) +#define CAAM_RTPKRRNG (CONFIG_SYS_FSL_SEC_ADDR + 0x0608) +#define CAAM_RTPKRMAX (CONFIG_SYS_FSL_SEC_ADDR + 0x060C) +#define CAAM_RTSDCTL (CONFIG_SYS_FSL_SEC_ADDR + 0x0610) +#define CAAM_RTFRQMIN (CONFIG_SYS_FSL_SEC_ADDR + 0x0618) +#define CAAM_RTFRQMAX (CONFIG_SYS_FSL_SEC_ADDR + 0x061C) +#define CAAM_RTSCML (CONFIG_SYS_FSL_SEC_ADDR + 0x0620) +#define CAAM_RTSCR1L (CONFIG_SYS_FSL_SEC_ADDR + 0x0624) +#define CAAM_RTSCR2L (CONFIG_SYS_FSL_SEC_ADDR + 0x0628) +#define CAAM_RTSCR3L (CONFIG_SYS_FSL_SEC_ADDR + 0x062C) +#define CAAM_RTSCR4L (CONFIG_SYS_FSL_SEC_ADDR + 0x0630) +#define CAAM_RTSCR5L (CONFIG_SYS_FSL_SEC_ADDR + 0x0634) +#define CAAM_RTSCR6PL (CONFIG_SYS_FSL_SEC_ADDR + 0x0638) +#define CAAM_RTSTATUS (CONFIG_SYS_FSL_SEC_ADDR + 0x063C) +#define CAAM_RDSTA (CONFIG_SYS_FSL_SEC_ADDR + 0x06C0) + +/* Job Ring 0 registers */ +#define CAAM_IRBAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1004) +#define CAAM_IRSR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x100c) +#define CAAM_IRSAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1014) +#define CAAM_IRJAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x101c) +#define CAAM_ORBAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1024) +#define CAAM_ORSR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x102c) +#define CAAM_ORJRR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1034) +#define CAAM_ORSFR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x103c) +#define CAAM_JRSTAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1044) +#define CAAM_JRINTR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x104c) +#define CAAM_JRCFGR0_MS (CONFIG_SYS_FSL_SEC_ADDR + 0x1050) +#define CAAM_JRCFGR0_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x1054) +#define CAAM_IRRIR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x105c) +#define CAAM_ORWIR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1064) +#define CAAM_JRCR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x106c) +#define CAAM_SMCJR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x10f4) +#define CAAM_SMCSJR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x10fc) +#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16) +#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16) +#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16) +#define CAAM_SMAPJR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x1114) +#define CAAM_SMAG2JR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x1118) +#define CAAM_SMAG1JR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x111c) +#define CAAM_SMPO (CONFIG_SYS_FSL_SEC_ADDR + 0x1fbc) + +/* JR0 and JR1 will be assigned to seco in imx8, so we need to + * use JR3 instead. + */ +#ifdef CONFIG_ARCH_IMX8 +#define CAAM_IRBAR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x40004) +#define CAAM_IRSR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4000c) +#define CAAM_IRSAR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x40014) +#define CAAM_IRJAR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4001c) +#define CAAM_ORBAR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x40024) +#define CAAM_ORSR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4002c) +#define CAAM_ORSFR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4003c) +#define CAAM_JRINTR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4004c) +#define CAAM_ORJRR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x40034) +#define CAAM_JRCFGR3_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x40054) +#define CAAM_JRCR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4006c) +#endif + +#define DESC_MAX_SIZE (0x40) /* Descriptor max size */ +#define JRCFG_LS_IMSK (0x01) /* Interrupt Mask */ +#define JR_MID (0x02) /* Matches ROM configuration */ +#define KS_G1 BIT(JR_MID) /* CAAM only */ +#define PERM (0x0000B008) /* Clear on release, lock SMAP, + * lock SMAG and group 1 Blob + */ + +#define CMD_PAGE_ALLOC (0x1) +#define CMD_PAGE_DEALLOC (0x2) +#define CMD_PART_DEALLOC (0x3) +#define CMD_INQUIRY (0x5) +#define PAGE(x) (x << 16) +#define PARTITION(x) (x << 8) + +#define SMCSJR_AERR (3 << 12) +#define SMCSJR_CERR (3 << 14) +#define CMD_COMPLETE (3 << 14) + +#define SMCSJR_PO (3 << 6) +#define PAGE_AVAILABLE (0) +#define PAGE_OWNED (3 << 6) + +#define PARTITION_OWNER(x) (0x3 << (x*2)) + +#define CAAM_BUSY_MASK (0x00000001) /* BUSY from status reg */ +#define CAAM_IDLE_MASK (0x00000002) /* IDLE from status reg */ +#define CAAM_MCFGR_SWRST BIT(31) /* CAAM SW reset */ +#define CAAM_MCFGR_DMARST BIT(28) /* CAAM DMA reset */ + +#define JOB_RING_ENTRIES (1) +#define JOB_RING_STS (0xF << 28) + +/** OSC_DIV in RNG trim fuses */ +#define RNG_TRIM_OSC_DIV (0) +/** ENT_DLY multiplier in RNG trim fuses */ +#define TRNG_SDCTL_ENT_DLY_MIN (3200) +#define TRNG_SDCTL_ENT_DLY_MAX (4800) + +#define RTMCTL_PGM BIT(16) +#define RTMCTL_ERR BIT(12) +#define RTMCTL_RST BIT(6) +#define RTMCTL_ACC BIT(5) +#define RDSTA_IF0 (1) +#define RDSTA_IF1 (2) +#define RDSTA_SKVN BIT(30) +#define JRCR_RESET (1) +#define RTMCTL_FCT_FAIL BIT(8) + +#define BS_TRNG_ENT_DLY (16) +#define BM_TRNG_ENT_DLY (0xffff << BS_TRNG_ENT_DLY) +#define BM_TRNG_SAMP_MODE (3) +#define TRNG_SAMP_MODE_RAW_ES_SC (1) +#define BS_JRINTR_HALT (2) +#define BM_JRINTR_HALT (0x3 << BS_JRINTR_HALT) +#define JRINTR_HALT_ONGOING (0x1 << BS_JRINTR_HALT) +#define JRINTR_HALT_DONE (0x2 << BS_JRINTR_HALT) +#define JRINTR_JRI (0x1) +#define BS_JRCFGR_LS_ICTT (16) +#define BM_JRCFGR_LS_ICTT (0xFFFF << BS_JRCFGR_LS_ICTT) +#define BS_JRCFGR_LS_ICDCT (8) +#define BM_JRCFGR_LS_ICDCT (0xFF << BS_JRCFGR_LS_ICDCT) +#define BS_JRCFGR_LS_ICEN (1) +#define BM_JRCFGR_LS_ICEN (0x1 << BS_JRCFGR_LS_ICEN) +#define BS_JRCFGR_LS_IMSK (0) +#define BM_JRCFGR_LS_IMSK (0x1 << BS_JRCFGR_LS_IMSK) +#define BS_CHAVID_LS_RNGVID (16) +#define BM_CHAVID_LS_RNGVID (0xF << BS_CHAVID_LS_RNGVID) +#define BS_MCFGR_WDE (30) +#define BM_MCFGR_WDE (0x1 << BS_MCFGR_WDE) + +typedef enum { + PAGE_0, + PAGE_1, + PAGE_2, + PAGE_3, +} page_num_e; + +typedef enum { + PARTITION_0, + PARTITION_1, + PARTITION_2, + PARTITION_3, + PARTITION_4, + PARTITION_5, + PARTITION_6, + PARTITION_7, +} partition_num_e; + + +/* + * Local defines + */ +/* arm v7 need 64 align */ +#define ALIGN_MASK ~(ARCH_DMA_MINALIGN - 1) +/* caam dma and pointer conversion for arm and arm64 architectures */ +#ifdef CONFIG_IMX_CONFIG + #define PTR2CAAMDMA(x) (u32)((uintptr_t)(x) & 0xffffffff) + #define CAAMDMA2PTR(x) (uintptr_t)((x) & 0xffffffff) +#else + #define PTR2CAAMDMA(x) (uintptr_t)(x) + #define CAAMDMA2PTR(x) (uintptr_t)(x) +#endif +#define RING_EARLY_INIT (0x01) +#define RING_RELOC_INIT (0x02) + +#define CAAM_HDR_CTYPE (0x16u << 27) +#define CAAM_HDR_ONE BIT(23) +#define CAAM_HDR_START_INDEX(x) (((x) & 0x3F) << 16) +#define CAAM_HDR_DESCLEN(x) ((x) & 0x3F) +#define CAAM_PROTOP_CTYPE (0x10u << 27) + +/* State Handle */ +#define BS_ALGO_RNG_SH (4) +#define BM_ALGO_RNG_SH (0x3 << BS_ALGO_RNG_SH) +#define ALGO_RNG_SH(id) (((id) << BS_ALGO_RNG_SH) & BM_ALGO_RNG_SH) + +/* Secure Key */ +#define BS_ALGO_RNG_SK (12) +#define BM_ALGO_RNG_SK BIT(BS_ALGO_RNG_SK) + +/* State */ +#define BS_ALGO_RNG_AS (2) +#define BM_ALGO_RNG_AS (0x3 << BS_ALGO_RNG_AS) +#define ALGO_RNG_GENERATE (0x0 << BS_ALGO_RNG_AS) +#define ALGO_RNG_INSTANTIATE BIT(BS_ALGO_RNG_AS) + +#define CAAM_C1_RNG ((0x50 << 16) | (2 << 24)) + +#define BS_JUMP_LOCAL_OFFSET (0) +#define BM_JUMP_LOCAL_OFFSET (0xFF << BS_JUMP_LOCAL_OFFSET) + +#define CAAM_C1_JUMP ((0x14u << 27) | (1 << 25)) +#define CAAM_JUMP_LOCAL (0 << 20) +#define CAAM_JUMP_TST_ALL_COND_TRUE (0 << 16) +#define CAAM_JUMP_OFFSET(off) (((off) << BS_JUMP_LOCAL_OFFSET) \ + & BM_JUMP_LOCAL_OFFSET) + +#define CAAM_C0_LOAD_IMM ((0x2 << 27) | (1 << 23)) +#define CAAM_DST_CLEAR_WRITTEN (0x8 << 16) + +#define RNG_DESC_SH0_SIZE (ARRAY_SIZE(rng_inst_sh0_desc)) +#define RNG_DESC_SH1_SIZE (ARRAY_SIZE(rng_inst_sh1_desc)) +#define RNG_DESC_KEYS_SIZE (ARRAY_SIZE(rng_inst_load_keys)) +#define RNG_DESC_MAX_SIZE (RNG_DESC_SH0_SIZE + \ + RNG_DESC_SH1_SIZE + \ + RNG_DESC_KEYS_SIZE) + +#define CAAM_PAD_LEN 48 + +#endif /* __CAAM_INTERNAL_H__ */ diff --git a/drivers/ddr/imx8m/Kconfig b/drivers/ddr/imx8m/Kconfig new file mode 100644 index 00000000000..71f466f5ec3 --- /dev/null +++ b/drivers/ddr/imx8m/Kconfig @@ -0,0 +1,22 @@ +config IMX8M_DRAM + bool "imx8m dram" + +config IMX8M_LPDDR4 + bool "imx8m lpddr4" + select IMX8M_DRAM + help + Select the i.MX8M LPDDR4 driver support on i.MX8M SOC. + +config IMX8M_DDR4 + bool "imx8m ddr4" + select IMX8M_DRAM + help + Select the i.MX8M DDR4 driver support on i.MX8M SOC. + +config SAVED_DRAM_TIMING_BASE + hex "Define the base address for saved dram timing" + help + after DRAM is trained, need to save the dram related timming + info into memory for low power use. OCRAM_S is used for this + purpose on i.MX8MM. + default 0x180000 diff --git a/drivers/ddr/imx8m/Makefile b/drivers/ddr/imx8m/Makefile new file mode 100644 index 00000000000..079e143f6dc --- /dev/null +++ b/drivers/ddr/imx8m/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o +endif diff --git a/drivers/ddr/imx8m/ddr4_init.c b/drivers/ddr/imx8m/ddr4_init.c new file mode 100644 index 00000000000..cdb838764aa --- /dev/null +++ b/drivers/ddr/imx8m/ddr4_init.c @@ -0,0 +1,98 @@ +/* +* Copyright 2018 NXP +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include +#include +#include +#include +#include +#include +#include + +void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +void ddr_init(struct dram_timing_info *dram_timing) +{ + volatile unsigned int tmp_t; + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); /* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, [4]src_system_rst_b! */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); /* deassert [4]src_system_rst_b! */ + + /* change the clock source of dram_apb_clk_root */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); /* to source 4 --800MHz/4 */ + + dram_pll_init(DRAM_PLL_OUT_600M); + + reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8,5); /* PU_PGC_SW_PUP_REQ */ + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */ + + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + + while (0 != (0x7 & reg32_read(DDRC_STAT(0)))) + ; + + /* config the uMCTL2's registers */ + ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + + reg32_write(DDRC_RFSHCTL3(0), 0x00000001); + /* RESET: DEASSERTED */ + /* RESET: +#include +#include +#include + +void ddr_cfg_phy(struct dram_timing_info *dram_timing) +{ + struct dram_cfg_param *dram_cfg; + struct dram_fsp_msg *fsp_msg; + unsigned int num; + int i = 0; + int j = 0; + + /* initialize PHY configuration */ + dram_cfg = dram_timing->ddrphy_cfg; + num = dram_timing->ddrphy_cfg_num; + for (i = 0; i < num; i++) { + /* config phy reg */ + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* load the frequency setpoint message block config */ + fsp_msg = dram_timing->fsp_msg; + for (i = 0; i < dram_timing->fsp_msg_num; i++) { + printf("DRAM PHY training for %dMTS\n", fsp_msg->drate); + /* set dram PHY input clocks to desired frequency */ + ddrphy_init_set_dfi_clk(fsp_msg->drate); + + /* load the dram training firmware image */ + dwc_ddrphy_apb_wr(0xd0000,0x0); + ddr_load_train_firmware(fsp_msg->fw_type); + + /* load the frequency set point message block parameter */ + dram_cfg = fsp_msg->fsp_cfg; + num = fsp_msg->fsp_cfg_num; + for (j = 0; j < num; j++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* + * -------------------- excute the firmware -------------------- + * Running the firmware is a simply process to taking the + * PMU out of reset and stall, then the firwmare will be run + * 1. reset the PMU; + * 2. begin the excution; + * 3. wait for the training done; + * 4. read the message block result. + * ------------------------------------------------------------- + */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x9); + dwc_ddrphy_apb_wr(0xd0099, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x0); + + /* Wait for the training firmware to complete */ + wait_ddrphy_training_complete(); + + /* Halt the microcontroller. */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); + + /* Read the Message Block results */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + ddrphy_init_read_msg_block(fsp_msg->fw_type); + dwc_ddrphy_apb_wr(0xd0000, 0x1); + + fsp_msg++; + } + + /* Load PHY Init Engine Image */ + dram_cfg = dram_timing->ddrphy_pie; + num = dram_timing->ddrphy_pie_num; + for (i = 0; i < num; i++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* save the ddr PHY trained CSR in memory for low power use */ + ddrphy_trained_csr_save(dram_timing->ddrphy_trained_csr, + dram_timing->ddrphy_trained_csr_num); +} diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c new file mode 100644 index 00000000000..b7c314ec98a --- /dev/null +++ b/drivers/ddr/imx8m/ddrphy_utils.c @@ -0,0 +1,188 @@ +/* +* Copyright 2018 NXP +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include +#include +#include +#include +#include +#include +#include + +#define ddr_printf(args...) debug(args) + +static inline void poll_pmu_message_ready(void) +{ + unsigned int reg; + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+ 4*0xd0004); + } while (reg & 0x1); +} + +static inline void ack_pmu_message_recieve(void) +{ + unsigned int reg; + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+ 4*0xd0031, 0x0); + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+ 4*0xd0004); + } while (!(reg & 0x1)); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+ 4*0xd0031, 0x1); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+ 4*0xd0032); + + ack_pmu_message_recieve(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+ 4*0xd0032); + + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+ 4*0xd0034); + + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_recieve(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + ddr_printf("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + ddr_printf("PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)){ + arg = get_stream_message(); + ddr_printf("arg[%d] = 0x%08x\n", i, arg); + i++; + } + + ddr_printf("\n"); +} + +void wait_ddrphy_training_complete(void) +{ + unsigned int mail; + while (1) { + mail = get_mail(); + decode_major_message(mail); + if (mail == 0x08) { + decode_streaming_message(); + } else if (mail == 0x07) { + printf("Training PASS\n"); + break; + } else if (mail == 0xff) { + printf("Training FAILED\n"); + break; + } + } +} + +void ddrphy_init_set_dfi_clk(unsigned int drate) +{ + switch (drate) { + case 3200: + dram_pll_init(DRAM_PLL_OUT_800M); + dram_disable_bypass(); + break; + case 3000: + dram_pll_init(DRAM_PLL_OUT_750M); + dram_disable_bypass(); + break; + case 2400: + dram_pll_init(DRAM_PLL_OUT_600M); + dram_disable_bypass(); + break; + case 1600: + dram_pll_init(DRAM_PLL_OUT_400M); + dram_disable_bypass(); + break; + case 667: + dram_pll_init(DRAM_PLL_OUT_167M); + dram_disable_bypass(); + break; + case 400: + dram_enable_bypass(DRAM_BYPASSCLK_400M); + break; + case 100: + dram_enable_bypass(DRAM_BYPASSCLK_100M); + break; + default: + return; + } +} + +void ddrphy_init_read_msg_block(enum fw_type type) +{ + +} + +void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr, unsigned int mr_data) +{ + unsigned int tmp; + /* + * 1. Poll MRSTAT.mr_wr_busy until it is 0. + * This checks that there is no outstanding MR transaction. + * No writes should be performed to MRCTRL0 and MRCTRL1 if + * MRSTAT.mr_wr_busy = 1. + */ + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + /* + * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and + * (for MRWs) MRCTRL1.mr_data to define the MR transaction. + */ + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4)); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data); + reg32setbit(DDRC_MRCTRL0(0), 31); +} + +unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) +{ + unsigned int tmp; + + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1); + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8)); + reg32setbit(DDRC_MRCTRL0(0), 31); + do { + tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); + } while ((tmp & 0x8) == 0); + tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); + tmp = tmp & 0xff; + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); + + return tmp; +} diff --git a/drivers/ddr/imx8m/helper.c b/drivers/ddr/imx8m/helper.c new file mode 100644 index 00000000000..dff1e2a962a --- /dev/null +++ b/drivers/ddr/imx8m/helper.c @@ -0,0 +1,171 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define IMEM_LEN 32768 /* byte */ +#define DMEM_LEN 16384 /* byte */ +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +/* We need PHY iMEM PHY is 32KB padded */ +void ddr_load_train_firmware(enum fw_type type) +{ + u32 tmp32, i; + u32 error = 0; + unsigned long pr_to32, pr_from32; + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; + unsigned long imem_start = (unsigned long)&_end + fw_offset; + unsigned long dmem_start = imem_start + IMEM_LEN; + + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN; ) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN; ) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + printf("check ddr4_pmu_train_imem code\n"); + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN; ) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + + if(tmp32 != readl(pr_from32)){ + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + if (error) { + printf("check ddr4_pmu_train_imem code fail=%d\n",error); + } else { + printf("check ddr4_pmu_train_imem code pass\n"); + } + + printf("check ddr4_pmu_train_dmem code\n"); + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN;) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + if (tmp32 != readl(pr_from32)) { + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + + if (error) { + printf("check ddr4_pmu_train_dmem code fail=%d",error); + } else { + printf("check ddr4_pmu_train_dmem code pass\n"); + } +} + +void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, unsigned int num) +{ + int i = 0; + + /* enable the ddrphy apb */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + dwc_ddrphy_apb_wr(0xc0080, 0x3); + for (i = 0; i < num; i++) { + ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg); + ddrphy_csr++; + } + /* disable the ddrphy apb */ + dwc_ddrphy_apb_wr(0xc0080, 0x2); + dwc_ddrphy_apb_wr(0xd0000, 0x1); +} + +void dram_config_save(struct dram_timing_info *timing_info, + unsigned long saved_timing_base) +{ + int i = 0; + struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base; + struct dram_cfg_param *cfg; + + saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num; + saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num; + saved_timing->ddrphy_trained_csr_num = timing_info->ddrphy_trained_csr_num; + saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num; + + /* save the fsp table */ + for (i = 0; i < 4; i++) + saved_timing->fsp_table[i] = timing_info->fsp_table[i]; + + cfg = (struct dram_cfg_param *)(saved_timing_base + sizeof(*timing_info)); + + /* save ddrc config */ + saved_timing->ddrc_cfg = cfg; + for (i = 0; i < timing_info->ddrc_cfg_num; i++) { + cfg->reg = timing_info->ddrc_cfg[i].reg; + cfg->val = timing_info->ddrc_cfg[i].val; + cfg++; + } + + /* save ddrphy config */ + saved_timing->ddrphy_cfg = cfg; + for (i = 0; i < timing_info->ddrphy_cfg_num; i++) { + cfg->reg = timing_info->ddrphy_cfg[i].reg; + cfg->val = timing_info->ddrphy_cfg[i].val; + cfg++; + } + + /* save the ddrphy csr */ + saved_timing->ddrphy_trained_csr = cfg; + for (i = 0; i < timing_info->ddrphy_trained_csr_num; i++) { + cfg->reg = timing_info->ddrphy_trained_csr[i].reg; + cfg->val = timing_info->ddrphy_trained_csr[i].val; + cfg++; + } + + /* save the ddrphy pie */ + saved_timing->ddrphy_pie = cfg; + for (i = 0; i < timing_info->ddrphy_pie_num; i++) { + cfg->reg = timing_info->ddrphy_pie[i].reg; + cfg->val = timing_info->ddrphy_pie[i].val; + cfg++; + } +} diff --git a/drivers/ddr/imx8m/lpddr4_init.c b/drivers/ddr/imx8m/lpddr4_init.c new file mode 100644 index 00000000000..d6422b9b0ab --- /dev/null +++ b/drivers/ddr/imx8m/lpddr4_init.c @@ -0,0 +1,189 @@ +/* +* Copyright 2018 NXP +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +void ddr_init(struct dram_timing_info *dram_timing) +{ + unsigned int tmp; + + printf("DDRINFO: start lpddr4 ddr init\n"); + /* step 1: reset */ + if (is_imx8mq()) { + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + } else { + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + } + + mdelay(100); + + debug("DDRINFO: reset done\n"); + /* change the clock source of dram_apb_clk_root: source 4 800MHz /4 = 200MHz */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + /* disable iso */ + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + + debug("DDRINFO: cfg clk\n"); + if (is_imx8mq()) + dram_pll_init(DRAM_PLL_OUT_800M); + else + dram_pll_init(DRAM_PLL_OUT_750M); + + /* + * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /*step2 Configure uMCTL2's registers */ + debug("DDRINFO: ddrc config start\n"); + lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + debug("DDRINFO: ddrc config done\n"); + + /* + * step3 de-assert all reset + * RESET: DEASSERTED + * RESET: for Port 0 DEASSERT(0)ED + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + reg32_write(DDRC_DBG1(0), 0x00000000); + /* step4 */ + /* [0]dis_auto_refresh=1 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000011); + + /* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */ + reg32_write(DDRC_PWRCTL(0), 0x000000a8); + + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x33f) != 0x223); + + reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ + + /* step5 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step6 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) { + reg32_write(DDRC_DFIMISC(0), 0x00000210); + } else if (tmp == 0x1) { + reg32_write(DDRC_DFIMISC(0), 0x00000110); + } else { + reg32_write(DDRC_DFIMISC(0), 0x00000010); + } + + /* step7 [0]--1: disable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* step8 Configure LPDDR4 PHY's registers */ + debug("DDRINFO:ddrphy config start\n"); + ddr_cfg_phy(dram_timing); + debug("DDRINFO: ddrphy config done\n"); + + /* + * step14 CalBusy.0 =1, indicates the calibrator is actively + * calibrating. Wait Calibrating done. + */ + do { + tmp = reg32_read(DDRPHY_CalBusy(0)); + } while ((tmp & 0x1)); + + printf("DDRINFO:ddrphy calibration done\n"); + + /* step15 [0]--0: to enable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step16 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) { + reg32_write(DDRC_DFIMISC(0), 0x00000230); + } else if (tmp == 0x1) { + reg32_write(DDRC_DFIMISC(0), 0x00000130); + } else { + reg32_write(DDRC_DFIMISC(0), 0x00000030); + } + + /* step17 [0]--1: disable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + /* step18 wait DFISTAT.dfi_init_complete to 1 */ + do { + tmp = reg32_read(DDRC_DFISTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* step19 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step20~22 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) { + reg32_write(DDRC_DFIMISC(0), 0x00000210); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000211); + } else if (tmp == 0x1) { + reg32_write(DDRC_DFIMISC(0), 0x00000110); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000111); + } else { + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000010); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000011); + } + + /* step23 [5]selfref_sw=0; */ + reg32_write(DDRC_PWRCTL(0), 0x00000008); + /* step24 sw_done=1 */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* step25 wait SWSTAT.sw_done_ack to 1 */ + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + +#ifdef DFI_BUG_WR + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001); +#endif + /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x3) != 0x1); + + /* step26 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); + + /* enable port 0 */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + printf("DDRINFO: ddrmix config done\n"); + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); +} diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index fea8767d7ba..f8422dda170 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -5,7 +5,8 @@ * on behalf of DENX Software Engineering GmbH * * Based on code from LTIB: - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -88,7 +89,7 @@ void mxs_dma_flush_desc(struct mxs_dma_desc *desc) uint32_t addr; uint32_t size; - addr = (uint32_t)desc; + addr = (uintptr_t)desc; size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT); flush_dcache_range(addr, addr + size); @@ -126,10 +127,10 @@ static int mxs_dma_enable(int channel) return 0; } - pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); - if (pdesc == NULL) + if (list_empty(&pchan->active)) return -EFAULT; + pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); if (pchan->flags & MXS_DMA_FLAGS_BUSY) { if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN)) return 0; @@ -215,8 +216,8 @@ static int mxs_dma_reset(int channel) #if defined(CONFIG_MX23) uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set); uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET; -#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7)) - uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set); +#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) + uint32_t setreg = (uintptr_t)(&apbh_regs->hw_apbh_channel_ctrl_set); uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET; #endif @@ -224,7 +225,7 @@ static int mxs_dma_reset(int channel) if (ret) return ret; - writel(1 << (channel + offset), setreg); + writel(1 << (channel + offset), (uintptr_t)setreg); return 0; } @@ -574,6 +575,14 @@ void mxs_dma_init(void) struct mxs_apbh_regs *apbh_regs = (struct mxs_apbh_regs *)MXS_APBH_BASE; +#ifdef CONFIG_MX6 + if (check_module_fused(MX6_MODULE_APBHDMA)) { + printf("NAND APBH-DMA@0x%x is fused, disable it\n", + MXS_APBH_BASE); + return; + } +#endif + mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg); #ifdef CONFIG_APBH_DMA_BURST8 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 266c9588fff..29e63d895f9 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_AXP_GPIO) += axp_gpio.o endif obj-$(CONFIG_DM_GPIO) += gpio-uclass.o -obj-$(CONFIG_DM_PCA953X) += pca953x_gpio.o +obj-$(CONFIG_$(SPL_)DM_PCA953X) += pca953x_gpio.o obj-$(CONFIG_DM_74X164) += 74x164_gpio.o obj-$(CONFIG_AT91_GPIO) += at91_gpio.o diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index d0e365a54b0..2353b50b2a0 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -5,6 +5,9 @@ * Copyright (C) 2011 * Stefano Babic, DENX Software Engineering, * + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -14,6 +17,11 @@ #include #include #include +#include +#ifdef CONFIG_IMX_RDC +#include +#include +#endif enum mxc_gpio_direction { MXC_GPIO_DIRECTION_IN, @@ -41,23 +49,48 @@ static unsigned long gpio_ports[] = { [2] = GPIO3_BASE_ADDR, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX8M) + defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) [3] = GPIO4_BASE_ADDR, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX8M) + defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) [4] = GPIO5_BASE_ADDR, -#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M)) +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M)) [5] = GPIO6_BASE_ADDR, #endif #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_IMX8) #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) [6] = GPIO7_BASE_ADDR, #endif #endif +#if defined(CONFIG_IMX8) + [7] = GPIO8_BASE_ADDR, +#endif }; +#ifdef CONFIG_IMX_RDC +static unsigned int gpio_rdc[] = { + RDC_PER_GPIO1, + RDC_PER_GPIO2, + RDC_PER_GPIO3, + RDC_PER_GPIO4, + RDC_PER_GPIO5, + RDC_PER_GPIO6, + RDC_PER_GPIO7, +}; + +#define RDC_CHECK(x) imx_rdc_check_permission(gpio_rdc[x], 0) +#define RDC_SPINLOCK_UP(x) imx_rdc_sema_lock(gpio_rdc[x]) +#define RDC_SPINLOCK_DOWN(x) imx_rdc_sema_unlock(gpio_rdc[x]) +#else +#define RDC_CHECK(x) 0 +#define RDC_SPINLOCK_UP(x) +#define RDC_SPINLOCK_DOWN(x) +#endif + + static int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction) { @@ -68,6 +101,11 @@ static int mxc_gpio_direction(unsigned int gpio, if (port >= ARRAY_SIZE(gpio_ports)) return -1; + if (RDC_CHECK(port)) + return -1; + + RDC_SPINLOCK_UP(port); + gpio &= 0x1f; regs = (struct gpio_regs *)gpio_ports[port]; @@ -83,6 +121,8 @@ static int mxc_gpio_direction(unsigned int gpio, } writel(l, ®s->gpio_dir); + RDC_SPINLOCK_DOWN(port); + return 0; } @@ -95,6 +135,11 @@ int gpio_set_value(unsigned gpio, int value) if (port >= ARRAY_SIZE(gpio_ports)) return -1; + if (RDC_CHECK(port)) + return -1; + + RDC_SPINLOCK_UP(port); + gpio &= 0x1f; regs = (struct gpio_regs *)gpio_ports[port]; @@ -106,6 +151,8 @@ int gpio_set_value(unsigned gpio, int value) l &= ~(1 << gpio); writel(l, ®s->gpio_dr); + RDC_SPINLOCK_DOWN(port); + return 0; } @@ -118,11 +165,18 @@ int gpio_get_value(unsigned gpio) if (port >= ARRAY_SIZE(gpio_ports)) return -1; + if (RDC_CHECK(port)) + return -1; + + RDC_SPINLOCK_UP(port); + gpio &= 0x1f; regs = (struct gpio_regs *)gpio_ports[port]; - val = (readl(®s->gpio_psr) >> gpio) & 0x01; + val = (readl(®s->gpio_dr) >> gpio) & 0x01; + + RDC_SPINLOCK_DOWN(port); return val; } @@ -132,6 +186,10 @@ int gpio_request(unsigned gpio, const char *label) unsigned int port = GPIO_TO_PORT(gpio); if (port >= ARRAY_SIZE(gpio_ports)) return -1; + + if (RDC_CHECK(port)) + return -1; + return 0; } @@ -201,7 +259,7 @@ static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset, static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset) { - return (readl(®s->gpio_psr) >> offset) & 0x01; + return (readl(®s->gpio_dr) >> offset) & 0x01; } /* set GPIO pin 'gpio' as an input */ @@ -277,7 +335,11 @@ static int mxc_gpio_probe(struct udevice *dev) char name[18], *str; banknum = plat->bank_index; +#if defined(CONFIG_IMX8) + sprintf(name, "GPIO%d_", banknum); +#else sprintf(name, "GPIO%d_", banknum + 1); +#endif str = strdup(name); if (!str) return -ENOMEM; @@ -350,19 +412,22 @@ static const struct mxc_gpio_plat mxc_plat[] = { { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, #endif #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_IMX8) { 6, (struct gpio_regs *)GPIO7_BASE_ADDR }, #endif +#if defined(CONFIG_IMX8) + { 7, (struct gpio_regs *)GPIO8_BASE_ADDR }, +#endif }; U_BOOT_DEVICES(mxc_gpios) = { @@ -371,19 +436,22 @@ U_BOOT_DEVICES(mxc_gpios) = { { "gpio_mxc", &mxc_plat[2] }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) { "gpio_mxc", &mxc_plat[3] }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) { "gpio_mxc", &mxc_plat[4] }, -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M { "gpio_mxc", &mxc_plat[5] }, #endif #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_IMX8) { "gpio_mxc", &mxc_plat[6] }, #endif +#if defined(CONFIG_IMX8) + { "gpio_mxc", &mxc_plat[7] }, +#endif }; #endif #endif diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c index 08742f90c67..b1be6db85b6 100644 --- a/drivers/gpio/pca953x_gpio.c +++ b/drivers/gpio/pca953x_gpio.c @@ -131,6 +131,26 @@ static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val) return ret; } +static int pca953x_write_regs(struct udevice *dev, int reg, u8 *val) +{ + struct pca953x_info *info = dev_get_platdata(dev); + int ret = 0; + + if (info->gpio_count <= 8) { + ret = dm_i2c_write(dev, reg, val, 1); + } else if (info->gpio_count <= 16) { + ret = dm_i2c_write(dev, reg << 1, val, info->bank_count); + } else if (info->gpio_count == 40) { + /* Auto increment */ + ret = dm_i2c_write(dev, (reg << 3) | 0x80, val, info->bank_count); + } else { + dev_err(dev, "Unsupported now\n"); + return -EINVAL; + } + + return ret; +} + static int pca953x_is_output(struct udevice *dev, int offset) { struct pca953x_info *info = dev_get_platdata(dev); @@ -252,6 +272,7 @@ static int pca953x_probe(struct udevice *dev) int ret; int size; const u8 *tmp; + u8 val[MAX_BANK]; addr = dev_read_addr(dev); if (addr == 0) @@ -287,6 +308,14 @@ static int pca953x_probe(struct udevice *dev) return ret; } + /* Clear the polarity registers to no invert */ + memset(val, 0, MAX_BANK); + ret = pca953x_write_regs(dev, PCA953X_INVERT, val); + if (ret) { + dev_err(dev, "Error writing invert register\n"); + return ret; + } + tmp = dev_read_prop(dev, "label", &size); if (tmp) { diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 932abd30597..b34927b07a6 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -137,6 +137,13 @@ config SYS_I2C_IMX_LPI2C help Add support for the NXP i.MX LPI2C driver. +config SYS_I2C_IMX_VIRT_I2C + bool "NXP i.MX Virtual I2C driver" + select IMX_VSERVICE + help + Add support for the NXP i.MX Virtual I2C which needs AMP communtication + to work with remote core to access i2c bus. + config SYS_I2C_MESON bool "Amlogic Meson I2C driver" depends on DM_I2C && ARCH_MESON @@ -150,7 +157,7 @@ config SYS_I2C_MESON config SYS_I2C_MXC bool "NXP i.MX I2C driver" - depends on MX6 + depends on MX6 || MX7 || ARCH_IMX8M help Add support for the NXP i.MX I2C driver. This supports upto for bus channels and operating on standard mode upto 100 kbits/s and fast diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 169a2f1d7a9..4557364b620 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o +obj-$(CONFIG_SYS_I2C_IMX_VIRT_I2C) += imx_virt_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index de74e89efdc..c67727ecea1 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -1,5 +1,6 @@ /* * Copyright 2016 Freescale Semiconductors, Inc. + * Copyright 2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,7 +10,7 @@ #include #include #include -#include +#include #include #include #include @@ -17,8 +18,11 @@ DECLARE_GLOBAL_DATA_PTR; #define LPI2C_FIFO_SIZE 4 +#define LPI2C_NACK_TOUT_MS 1 #define LPI2C_TIMEOUT_MS 100 +static int bus_i2c_init(struct udevice *bus, int speed); + /* Weak linked function for overridden by some SoC power function */ int __weak init_i2c_power(unsigned i2c_num) { @@ -92,8 +96,9 @@ static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs) return result; } -static int bus_i2c_send(struct imx_lpi2c_reg *regs, u8 *txbuf, int len) +static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len) { + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); lpi2c_status_t result = LPI2C_SUCESS; /* empty tx */ @@ -112,8 +117,9 @@ static int bus_i2c_send(struct imx_lpi2c_reg *regs, u8 *txbuf, int len) return result; } -static int bus_i2c_receive(struct imx_lpi2c_reg *regs, u8 *rxbuf, int len) +static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len) { + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); lpi2c_status_t result = LPI2C_SUCESS; u32 val; ulong start_time = get_timer(0); @@ -154,15 +160,23 @@ static int bus_i2c_receive(struct imx_lpi2c_reg *regs, u8 *rxbuf, int len) return result; } -static int bus_i2c_start(struct imx_lpi2c_reg *regs, u8 addr, u8 dir) +static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir) { + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); lpi2c_status_t result = LPI2C_SUCESS; u32 val; result = imx_lpci2c_check_busy_bus(regs); if (result) { debug("i2c: start check busy bus: 0x%x\n", result); - return result; + + /* Try to init the lpi2c then check the bus busy again */ + bus_i2c_init(bus, 100000); + result = imx_lpci2c_check_busy_bus(regs); + if (result) { + printf("i2c: Error check busy bus: 0x%x\n", result); + return result; + } } /* clear all status flags */ writel(0x7f00, ®s->msr); @@ -182,10 +196,12 @@ static int bus_i2c_start(struct imx_lpi2c_reg *regs, u8 addr, u8 dir) return result; } -static int bus_i2c_stop(struct imx_lpi2c_reg *regs) +static int bus_i2c_stop(struct udevice *bus) { + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); lpi2c_status_t result = LPI2C_SUCESS; u32 status; + ulong start_time; result = bus_i2c_wait_for_tx_ready(regs); if (result) { @@ -196,7 +212,8 @@ static int bus_i2c_stop(struct imx_lpi2c_reg *regs) /* send stop command */ writel(LPI2C_MTDR_CMD(0x2), ®s->mtdr); - while (result == LPI2C_SUCESS) { + start_time = get_timer(0); + while (1) { status = readl(®s->msr); result = imx_lpci2c_check_clear_error(regs); /* stop detect flag */ @@ -206,39 +223,38 @@ static int bus_i2c_stop(struct imx_lpi2c_reg *regs) writel(status, ®s->msr); break; } + + if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) { + debug("stop timeout\n"); + return -ETIMEDOUT; + } } return result; } -static int bus_i2c_read(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len) +static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len) { lpi2c_status_t result = LPI2C_SUCESS; - result = bus_i2c_start(regs, chip, 1); - if (result) - return result; - result = bus_i2c_receive(regs, buf, len); + result = bus_i2c_start(bus, chip, 1); if (result) return result; - result = bus_i2c_stop(regs); + result = bus_i2c_receive(bus, buf, len); if (result) return result; return result; } -static int bus_i2c_write(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len) +static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len) { lpi2c_status_t result = LPI2C_SUCESS; - result = bus_i2c_start(regs, chip, 0); + result = bus_i2c_start(bus, chip, 0); if (result) return result; - result = bus_i2c_send(regs, buf, len); - if (result) - return result; - result = bus_i2c_stop(regs); + result = bus_i2c_send(bus, buf, len); if (result) return result; @@ -353,38 +369,32 @@ static int bus_i2c_init(struct udevice *bus, int speed) static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip, u32 chip_flags) { - struct imx_lpi2c_reg *regs; lpi2c_status_t result = LPI2C_SUCESS; - regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); - result = bus_i2c_start(regs, chip, 0); + result = bus_i2c_start(bus, chip, 0); if (result) { - bus_i2c_stop(regs); + bus_i2c_stop(bus); bus_i2c_init(bus, 100000); return result; } - result = bus_i2c_stop(regs); - if (result) { + result = bus_i2c_stop(bus); + if (result) bus_i2c_init(bus, 100000); - return -result; - } return result; } static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) { - struct imx_lpi2c_reg *regs; - int ret = 0; + int ret = 0, ret_stop; - regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); for (; nmsgs > 0; nmsgs--, msg++) { debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); if (msg->flags & I2C_M_RD) - ret = bus_i2c_read(regs, msg->addr, msg->buf, msg->len); + ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len); else { - ret = bus_i2c_write(regs, msg->addr, msg->buf, + ret = bus_i2c_write(bus, msg->addr, msg->buf, msg->len); if (ret) break; @@ -394,6 +404,12 @@ static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) if (ret) debug("i2c_write: error sending\n"); + ret_stop = bus_i2c_stop(bus); + if (ret_stop) + debug("i2c_xfer: stop bus error\n"); + + ret |= ret_stop; + return ret; } @@ -441,6 +457,18 @@ static int imx_lpi2c_probe(struct udevice *bus) return 0; } +int __weak board_imx_lpi2c_bind(struct udevice *dev) +{ + return 0; +} + +static int imx_lpi2c_bind(struct udevice *dev) +{ + debug("imx_lpi2c_bind, %s, seq %d\n", dev->name, dev->req_seq); + + return board_imx_lpi2c_bind(dev); +} + static const struct dm_i2c_ops imx_lpi2c_ops = { .xfer = imx_lpi2c_xfer, .probe_chip = imx_lpi2c_probe_chip, @@ -449,6 +477,7 @@ static const struct dm_i2c_ops imx_lpi2c_ops = { static const struct udevice_id imx_lpi2c_ids[] = { { .compatible = "fsl,imx7ulp-lpi2c", }, + { .compatible = "fsl,imx8qm-lpi2c", }, {} }; @@ -456,6 +485,7 @@ U_BOOT_DRIVER(imx_lpi2c) = { .name = "imx_lpi2c", .id = UCLASS_I2C, .of_match = imx_lpi2c_ids, + .bind = imx_lpi2c_bind, .probe = imx_lpi2c_probe, .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus), .ops = &imx_lpi2c_ops, diff --git a/drivers/i2c/imx_virt_i2c.c b/drivers/i2c/imx_virt_i2c.c new file mode 100644 index 00000000000..765622f3870 --- /dev/null +++ b/drivers/i2c/imx_virt_i2c.c @@ -0,0 +1,310 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MAX_SRTM_I2C_BUF_SIZE 16 +#define SRTM_I2C_CATEGORY 0x09 +#define SRTM_VERSION 0x0001 +#define SRTM_TYPE_REQ 0x0 +#define SRTM_TYPE_RESP 0x1 +#define SRTM_CMD_READ 0x0 +#define SRTM_CMD_WRITE 0x1 + +#define I2C_M_SELECT_MUX_BUS 0x010000 +#define I2C_M_SRTM_STOP 0x0200 + +struct imx_virt_i2c_bus { + int index; + ulong base; + struct imx_vservice_channel *vservice; +}; + +struct imx_srtm_i2c_msg { + u8 categary; + u8 version[2]; + u8 type; + u8 command; + u8 priority; + u8 reserved[4]; + + u8 i2c_bus; + u8 return_val; + u16 slave_addr; + u16 flag; + u16 data_length; + u8 data_buf[MAX_SRTM_I2C_BUF_SIZE]; +}; + +static void imx_virt_i2c_msg_dump(struct imx_srtm_i2c_msg *msg) +{ + u32 i = 0; + u32 size = sizeof(struct imx_srtm_i2c_msg); + u8 *buf = (u8 *)msg; + + for (; i < size; i++) { + debug("%02x ", buf[i]); + if (i % 16 == 15) + debug("\n"); + } +} + +static int imx_virt_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len, uint flag) +{ + struct imx_srtm_i2c_msg *msg; + u32 size; + int ret = 0; + struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus); + + debug("imx_virt_i2c_read, bus %d\n", i2c_bus->index); + + if (len > MAX_SRTM_I2C_BUF_SIZE) { + printf("virt_i2c_read exceed the buf length, len=%d\n", len); + return -EINVAL; + } + + size = sizeof(struct imx_srtm_i2c_msg); + msg = imx_vservice_get_buffer(i2c_bus->vservice, size); + if (msg == NULL) + return -ENOMEM; + + /* Fill buf with SRTM i2c format */ + msg->categary = SRTM_I2C_CATEGORY; + msg->version[0] = SRTM_VERSION & 0xff; + msg->version[1] = (SRTM_VERSION >> 8) & 0xff; + msg->type = SRTM_TYPE_REQ; + msg->command = SRTM_CMD_READ; + msg->priority = 1; + + msg->i2c_bus = i2c_bus->index; + msg->return_val = 0; + msg->slave_addr = (u16)chip; + msg->flag = (u16)flag; + msg->data_length = len; + + imx_virt_i2c_msg_dump(msg); + + /* Send request and get return data */ + ret = imx_vservice_blocking_request(i2c_bus->vservice, (u8 *)msg, &size); + if (ret) { + printf("Vservice request is failed, ret %d\n", ret); + return ret; + } + + if (msg->type != SRTM_TYPE_RESP || msg->categary != SRTM_I2C_CATEGORY + || msg->command !=SRTM_CMD_READ) { + printf("Error read response message\n"); + return -EIO; + } + + if (msg->return_val != 0) + return msg->return_val; + + if (len != 0) + memcpy(buf, msg->data_buf, msg->data_length); + + return ret; +} + +static int imx_virt_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len, uint flag) +{ + struct imx_srtm_i2c_msg *msg; + u32 size; + int ret = 0; + struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus); + + debug("imx_virt_i2c_write, bus %d\n", i2c_bus->index); + + if (len > MAX_SRTM_I2C_BUF_SIZE) { + printf("virt_i2c_read exceed the buf length, len=%d\n", len); + return -EINVAL; + } + + size = sizeof(struct imx_srtm_i2c_msg); + msg = imx_vservice_get_buffer(i2c_bus->vservice, size); + if (msg == NULL) + return -ENOMEM; + + /* Fill buf with SRTM i2c format */ + msg->categary = SRTM_I2C_CATEGORY; + msg->version[0] = SRTM_VERSION & 0xff; + msg->version[1] = (SRTM_VERSION >> 8) & 0xff; + msg->type = SRTM_TYPE_REQ; + msg->command = SRTM_CMD_WRITE; + msg->priority = 1; + + msg->i2c_bus = i2c_bus->index; + msg->return_val = 0; + msg->slave_addr = (u16)chip; + msg->flag = (u16)flag; + msg->data_length = len; + + imx_virt_i2c_msg_dump(msg); + + if (buf) /* probe chip does not have data buffer */ + memcpy(msg->data_buf, buf, msg->data_length); + + /* Send request and get return data */ + ret = imx_vservice_blocking_request(i2c_bus->vservice, (u8 *)msg, &size); + if (ret) { + printf("Vservice request is failed, ret %d\n", ret); + return ret; + } + + if (msg->type != SRTM_TYPE_RESP || msg->categary != SRTM_I2C_CATEGORY + || msg->command !=SRTM_CMD_WRITE) { + printf("Error write response message\n"); + return -EIO; + } + + if (msg->return_val != 0) { + debug("Peer process message, ret %d\n", msg->return_val); + return -EACCES; + } + + debug("imx_vservice_blocking_request get size = %d\n", size); + + return ret; + +} + +static int imx_virt_i2c_probe_chip(struct udevice *bus, u32 chip, + u32 chip_flags) +{ + debug("imx_virt_i2c_probe_chip\n"); + + return imx_virt_i2c_write(bus, chip, NULL, 0, I2C_M_SRTM_STOP); +} + +static int imx_virt_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + int ret = 0; + uint flag = 0; + + for (; nmsgs > 0; nmsgs--, msg++) { + debug("virt_i2c_xfer: chip=0x%x, len=0x%x, buf=0x%08x\n", msg->addr, msg->len, *msg->buf); + + flag = msg->flags; + if (nmsgs == 1) + flag |= I2C_M_SRTM_STOP; + + if (flag & I2C_M_RD) + ret = imx_virt_i2c_read(bus, msg->addr, msg->buf, msg->len, flag); + else { + ret = imx_virt_i2c_write(bus, msg->addr, msg->buf, + msg->len, flag); + if (ret) + break; + } + } + + if (ret) + printf("i2c_xfer: error %d\n", ret); + + return ret; +} + +static int imx_virt_i2c_probe(struct udevice *bus) +{ + struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus); + fdt_addr_t addr; + + addr = devfdt_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + i2c_bus->base = addr; + i2c_bus->index = bus->seq; + + debug("virt_i2c : controller bus %d at 0x%lx, bus udev 0x%lx\n", + bus->seq, i2c_bus->base, (ulong)bus); + + i2c_bus->vservice = imx_vservice_setup(bus); + if (i2c_bus->vservice == NULL) { + printf("virt_i2c: Faild to setup vservice\n"); + return -ENODEV; + } + + return 0; +} + +static int imx_virt_i2c_set_flags(struct udevice *child_dev, uint flags) +{ +#ifdef CONFIG_I2C_MUX_IMX_VIRT + if (child_dev->uclass->uc_drv->id == UCLASS_I2C_MUX) { + struct udevice *bus = child_dev->parent; + struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus); + + if (flags == 0) { + i2c_bus->index = bus->seq; + } else if (flags & I2C_M_SELECT_MUX_BUS) { + i2c_bus->index = (flags >> 24) & 0xff; + } + + debug("virt_i2c_set_flags bus %d\n", i2c_bus->index); + } +#endif + return 0; +} + +int __weak board_imx_virt_i2c_bind(struct udevice *dev) +{ + return 0; +} + +static int imx_virt_i2c_bind(struct udevice *dev) +{ + debug("imx_virt_i2c_bind, %s, seq %d\n", dev->name, dev->req_seq); + + return board_imx_virt_i2c_bind(dev); +} + +static int imx_virt_i2c_child_post_bind(struct udevice *child_dev) +{ +#ifdef CONFIG_I2C_MUX_IMX_VIRT + if (child_dev->uclass->uc_drv->id == UCLASS_I2C_MUX) { + if (!strcmp(child_dev->driver->name, "imx_virt_i2c_mux")) + return 0; + else + return -ENODEV; + } +#endif + + return 0; +} + +static const struct dm_i2c_ops imx_virt_i2c_ops = { + .xfer = imx_virt_i2c_xfer, + .probe_chip = imx_virt_i2c_probe_chip, + .set_flags = imx_virt_i2c_set_flags, +}; + +static const struct udevice_id imx_virt_i2c_ids[] = { + { .compatible = "fsl,imx-virt-i2c", }, + {} +}; + +U_BOOT_DRIVER(imx_virt_i2c) = { + .name = "imx_virt_i2c", + .id = UCLASS_I2C, + .of_match = imx_virt_i2c_ids, + .bind = imx_virt_i2c_bind, + .probe = imx_virt_i2c_probe, + .child_post_bind = imx_virt_i2c_child_post_bind, + .priv_auto_alloc_size = sizeof(struct imx_virt_i2c_bus), + .ops = &imx_virt_i2c_ops, + .flags = DM_FLAG_IGNORE_POWER_ON, +}; diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index 156380c1ccc..afa36233381 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -35,6 +35,12 @@ config I2C_MUX_PCA954x to the same I2C controller where driver handles proper routing to target i2c device. PCA9544 and PCA9548 are supported. +config I2C_MUX_IMX_VIRT + bool "i.MX Virtual I2C Mux/switches" + depends on I2C_MUX && SYS_I2C_IMX_VIRT_I2C + help + If you say yes here you get support for the i.MX Virtual I2C mux + config I2C_MUX_GPIO tristate "GPIO-based I2C multiplexer" depends on I2C_MUX && DM_GPIO diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile index 3831f4e4fba..87540680d2d 100644 --- a/drivers/i2c/muxes/Makefile +++ b/drivers/i2c/muxes/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o +obj-$(CONFIG_I2C_MUX_IMX_VIRT) += imx_virt_i2c_mux.o diff --git a/drivers/i2c/muxes/imx_virt_i2c_mux.c b/drivers/i2c/muxes/imx_virt_i2c_mux.c new file mode 100644 index 00000000000..cdf26e39879 --- /dev/null +++ b/drivers/i2c/muxes/imx_virt_i2c_mux.c @@ -0,0 +1,74 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define I2C_M_SELECT_MUX_BUS 0x010000 + +struct imx_virt_i2c_mux_priv { + u32 addr; /* I2C mux address */ + u32 i2c_bus_alias_off; +}; + +static int imx_virt_i2c_mux_deselect(struct udevice *mux, struct udevice *bus, + uint channel) +{ + return i2c_set_chip_flags(mux, 0); +} + +static int imx_virt_i2c_mux_select(struct udevice *mux, struct udevice *bus, + uint channel) +{ + struct imx_virt_i2c_mux_priv *priv = dev_get_priv(mux); + uint flags = I2C_M_SELECT_MUX_BUS; + + flags |= ((priv->i2c_bus_alias_off + channel) << 24); + + return i2c_set_chip_flags(mux, flags); +} + +static const struct i2c_mux_ops imx_virt_i2c_mux_ops = { + .select = imx_virt_i2c_mux_select, + .deselect = imx_virt_i2c_mux_deselect, +}; + +static const struct udevice_id imx_virt_i2c_mux_ids[] = { + { .compatible = "fsl,imx-virt-i2c-mux", }, + { } +}; + +static int imx_virt_i2c_mux_probe(struct udevice *dev) +{ + struct imx_virt_i2c_mux_priv *priv = dev_get_priv(dev); + + priv->addr = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", 0); + if (!priv->addr) { + debug("MUX not found\n"); + return -ENODEV; + } + + priv->i2c_bus_alias_off = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "virtual-bus-seq", 0); + + debug("Device %s at 0x%x with i2c_bus_alias_off %d\n", + dev->name, priv->addr, priv->i2c_bus_alias_off); + return 0; +} + +U_BOOT_DRIVER(imx_virt_i2c_mux) = { + .name = "imx_virt_i2c_mux", + .id = UCLASS_I2C_MUX, + .of_match = imx_virt_i2c_mux_ids, + .probe = imx_virt_i2c_mux_probe, + .ops = &imx_virt_i2c_mux_ops, + .priv_auto_alloc_size = sizeof(struct imx_virt_i2c_mux_priv), +}; diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index 2b70ff82bdd..c7ac125edb5 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -18,7 +18,8 @@ DECLARE_GLOBAL_DATA_PTR; enum pca_type { PCA9544, PCA9547, - PCA9548 + PCA9548, + PCA9646 }; struct chip_desc { @@ -52,6 +53,11 @@ static const struct chip_desc chips[] = { .muxtype = pca954x_isswi, .width = 8, }, + [PCA9646] = { + .enable = 0x0, + .muxtype = pca954x_isswi, + .width = 4, + }, }; static int pca954x_deselect(struct udevice *mux, struct udevice *bus, @@ -87,6 +93,7 @@ static const struct udevice_id pca954x_ids[] = { { .compatible = "nxp,pca9544", .data = PCA9544 }, { .compatible = "nxp,pca9547", .data = PCA9547 }, { .compatible = "nxp,pca9548", .data = PCA9548 }, + { .compatible = "nxp,pca9646", .data = PCA9646 }, { } }; diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 79228c2757b..4ef8f6c802b 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -4,6 +4,8 @@ * (c) 2007 Pengutronix, Sascha Hauer * (c) 2011 Marek Vasut * + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * * Based on i2c-imx.c from linux kernel: * Copyright (C) 2005 Torsten Koschorrek * Copyright (C) 2005 Matthias Blaschke @@ -25,6 +27,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -648,6 +651,14 @@ void bus_i2c_init(int index, int speed, int unused, return; } +#ifdef CONFIG_MX6 + if (mx6_i2c_fused((u32)mxc_i2c_buses[index].base)) { + printf("I2C@0x%x is fused, disable it\n", + (u32)mxc_i2c_buses[index].base); + return; + } +#endif + /* * Warning: Be careful to allow the assignment to a static * variable here. This function could be called while U-Boot is @@ -761,6 +772,13 @@ static int mxc_i2c_probe(struct udevice *bus) if (addr == FDT_ADDR_T_NONE) return -EINVAL; +#ifdef CONFIG_MX6 + if (mx6_i2c_fused(addr)) { + printf("I2C@0x%lx is fused, disable it\n", addr); + return -ENODEV; + } +#endif + i2c_bus->base = addr; i2c_bus->index = bus->seq; i2c_bus->bus = bus; diff --git a/drivers/input/Makefile b/drivers/input/Makefile index 9109ac6dbad..cdd9b3bfd39 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -18,3 +18,4 @@ obj-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o endif obj-y += input.o obj-$(CONFIG_$(SPL_)OF_CONTROL) += key_matrix.o +obj-$(CONFIG_MXC_KPD) += mxc_keyb.o diff --git a/drivers/input/mxc_keyb.c b/drivers/input/mxc_keyb.c new file mode 100644 index 00000000000..dabe2c98a4e --- /dev/null +++ b/drivers/input/mxc_keyb.c @@ -0,0 +1,592 @@ +/* + * Copyright (C) 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * @file mxc_keyb.c + * + * @brief Driver for the Freescale Semiconductor MXC keypad port. + * + * The keypad driver is designed as a standard Input driver which interacts + * with low level keypad port hardware. Upon opening, the Keypad driver + * initializes the keypad port. When the keypad interrupt happens the driver + * calles keypad polling timer and scans the keypad matrix for key + * press/release. If all key press/release happened it comes out of timer and + * waits for key press interrupt. The scancode for key press and release events + * are passed to Input subsytem. + * + * @ingroup keypad + */ + +#include +#include +#include +#include +#include +#include + +/* + * * Module header file + * */ +#include + +/*! + * Comment KPP_DEBUG to disable debug messages + */ + +#undef KPP_DEBUG + +#ifdef KPP_DEBUG +#define KPP_PRINTF(fmt, args...) printf(fmt , ##args) + +static void mxc_kpp_dump_regs() +{ + unsigned short t1, t2, t3; + + t1 = __raw_readw(KPCR); + t2 = __raw_readw(KPSR); + t3 = __raw_readw(KDDR); + /* + KPP_PRINTF("KPCR=0x%04x, KPSR=0x%04x, KDDR=0x%04x\n", + t1, t2, t3); + */ +} +#else +#define KPP_PRINTF(fmt, args...) +#endif + +static u16 mxc_key_mapping[] = CONFIG_MXC_KEYMAPPING; + +/*! + * This structure holds the keypad private data structure. + */ +static struct keypad_priv kpp_dev; + +/*! Indicates if the key pad device is enabled. */ + +/*! This static variable indicates whether a key event is pressed/released. */ +static unsigned short KPress; + +/*! cur_rcmap and prev_rcmap array is used to detect key press and release. */ +static unsigned short *cur_rcmap; /* max 64 bits (8x8 matrix) */ +static unsigned short *prev_rcmap; + +/*! + * Debounce polling period(10ms) in system ticks. + */ +/*static unsigned short KScanRate = (10 * CONFIG_SYS_HZ) / 1000;*/ + +/*! + * These arrays are used to store press and release scancodes. + */ +static short **press_scancode; +static short **release_scancode; + +static const unsigned short *mxckpd_keycodes; +static unsigned short mxckpd_keycodes_size; + +/*! + * This function is called to scan the keypad matrix to find out the key press + * and key release events. Make scancode and break scancode are generated for + * key press and key release events. + * + * The following scanning sequence are done for + * keypad row and column scanning, + * -# Write 1's to KPDR[15:8], setting column data to 1's + * -# Configure columns as totem pole outputs(for quick discharging of keypad + * capacitance) + * -# Configure columns as open-drain + * -# Write a single column to 0, others to 1. + * -# Sample row inputs and save data. Multiple key presses can be detected on + * a single column. + * -# Repeat steps the above steps for remaining columns. + * -# Return all columns to 0 in preparation for standby mode. + * -# Clear KPKD and KPKR status bit(s) by writing to a 1, + * Set the KPKR synchronizer chain by writing "1" to KRSS register, + * Clear the KPKD synchronizer chain by writing "1" to KDSC register + * + * @result Number of key pressed/released. + */ +static int mxc_kpp_scan_matrix(void) +{ + unsigned short reg_val; + int col, row; + short scancode = 0; + int keycnt = 0; /* How many keys are still pressed */ + + /* + * wmb() linux kernel function which guarantees orderings in write + * operations + */ + /* wmb(); */ + + /* save cur keypad matrix to prev */ + memcpy(prev_rcmap, cur_rcmap, kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + + /*1. Disable both (depress and release) keypad interrupts.*/ + + /* KDIE has been disabled in mxc_kpp_getc before calling scan matrix. + * KRIE is always disabled in this driver. + */ + + for (col = 0; col < kpp_dev.kpp_cols; col++) { /* Col */ + /* 2. Write 1.s to KPDR[15:8] setting column data to 1.s */ + reg_val = __raw_readw(KPDR); + reg_val |= 0xff00; + __raw_writew(reg_val, KPDR); + + /* + * 3. Configure columns as totem pole outputs(for quick + * discharging of keypad capacitance) + */ + reg_val = __raw_readw(KPCR); + reg_val &= 0x00ff; + __raw_writew(reg_val, KPCR); + + udelay(2); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* + * 4. Configure columns as open-drain + */ + reg_val = __raw_readw(KPCR); + reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8; + __raw_writew(reg_val, KPCR); + + /* + * 5. Write a single column to 0, others to 1. + * 6. Sample row inputs and save data. Multiple key presses + * can be detected on a single column. + * 7. Repeat steps 2 - 6 for remaining columns. + */ + + /* Col bit starts at 8th bit in KPDR */ + reg_val = __raw_readw(KPDR); + reg_val &= ~(1 << (8 + col)); + __raw_writew(reg_val, KPDR); + + /* Delay added to avoid propagating the 0 from column to row + * when scanning. */ + + udelay(5); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* Read row input */ + reg_val = __raw_readw(KPDR); + for (row = 0; row < kpp_dev.kpp_rows; row++) { /* sample row */ + if (TEST_BIT(reg_val, row) == 0) { + cur_rcmap[row] = BITSET(cur_rcmap[row], col); + keycnt++; + } + } + } + + /* + * 8. Return all columns to 0 in preparation for standby mode. + * 9. Clear KPKD and KPKR status bit(s) by writing to a .1., + * set the KPKR synchronizer chain by writing "1" to KRSS register, + * clear the KPKD synchronizer chain by writing "1" to KDSC register + */ + reg_val = 0x00; + __raw_writew(reg_val, KPDR); + reg_val = __raw_readw(KPDR); + reg_val = __raw_readw(KPSR); + reg_val |= KBD_STAT_KPKD | KBD_STAT_KPKR | KBD_STAT_KRSS | + KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* Check key press status change */ + + /* + * prev_rcmap array will contain the previous status of the keypad + * matrix. cur_rcmap array will contains the present status of the + * keypad matrix. If a bit is set in the array, that (row, col) bit is + * pressed, else it is not pressed. + * + * XORing these two variables will give us the change in bit for + * particular row and column. If a bit is set in XOR output, then that + * (row, col) has a change of status from the previous state. From + * the diff variable the key press and key release of row and column + * are found out. + * + * If the key press is determined then scancode for key pressed + * can be generated using the following statement: + * scancode = ((row * 8) + col); + * + * If the key release is determined then scancode for key release + * can be generated using the following statement: + * scancode = ((row * 8) + col) + MXC_KEYRELEASE; + */ + for (row = 0; row < kpp_dev.kpp_rows; row++) { + unsigned char diff; + + /* + * Calculate the change in the keypad row status + */ + diff = prev_rcmap[row] ^ cur_rcmap[row]; + + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((diff >> col) & 0x1) { + /* There is a status change on col */ + if ((prev_rcmap[row] & BITSET(0, col)) == 0) { + /* + * Previous state is 0, so now + * a key is pressed + */ + scancode = + ((row * kpp_dev.kpp_cols) + + col); + KPress = 1; + kpp_dev.iKeyState = KStateUp; + + KPP_PRINTF("Press (%d, %d) scan=%d " + "Kpress=%d\n", + row, col, scancode, KPress); + press_scancode[row][col] = + (short)scancode; + } else { + /* + * Previous state is not 0, so + * now a key is released + */ + scancode = + (row * kpp_dev.kpp_cols) + + col + MXC_KEYRELEASE; + KPress = 0; + kpp_dev.iKeyState = KStateDown; + + KPP_PRINTF + ("Release (%d, %d) scan=%d Kpress=%d\n", + row, col, scancode, KPress); + release_scancode[row][col] = + (short)scancode; + keycnt++; + } + } + } + } + + return keycnt; +} + +static int mxc_kpp_reset(void) +{ + unsigned short reg_val; + int i; + + /* + * Stop scanning and wait for interrupt. + * Enable press interrupt and disable release interrupt. + */ + __raw_writew(0x00FF, KPDR); + reg_val = __raw_readw(KPSR); + reg_val |= (KBD_STAT_KPKR | KBD_STAT_KPKD); + reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* + * No more keys pressed... make sure unwanted key codes are + * not given upstairs + */ + for (i = 0; i < kpp_dev.kpp_rows; i++) { + memset(press_scancode[i], -1, + sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols); + memset(release_scancode[i], -1, + sizeof(release_scancode[0][0]) * + kpp_dev.kpp_cols); + } + + return 0; +} + +int mxc_kpp_getc(struct kpp_key_info **key_info) +{ + int col, row; + int key_cnt; + unsigned short reg_val; + short scancode = 0; + int index = 0; + struct kpp_key_info *keyi; + + reg_val = __raw_readw(KPSR); + + if (reg_val & KBD_STAT_KPKD) { + /* + * Disable key press(KDIE status bit) interrupt + */ + reg_val &= ~KBD_STAT_KDIE; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + key_cnt = mxc_kpp_scan_matrix(); + } else { + return 0; + } + + if (key_cnt <= 0) + return 0; + + *key_info = keyi = + (struct kpp_key_info *)malloc + (sizeof(struct kpp_key_info) * key_cnt); + + /* + * This switch case statement is the + * implementation of state machine of debounc + * logic for key press/release. + * The explaination of state machine is as + * follows: + * + * KStateUp State: + * This is in intial state of the state machine + * this state it checks for any key presses. + * The key press can be checked using the + * variable KPress. If KPress is set, then key + * press is identified and switches the to + * KStateFirstDown state for key press to + * debounce. + * + * KStateFirstDown: + * After debounce delay(10ms), if the KPress is + * still set then pass scancode generated to + * input device and change the state to + * KStateDown, else key press debounce is not + * satisfied so change the state to KStateUp. + * + * KStateDown: + * In this state it checks for any key release. + * If KPress variable is cleared, then key + * release is indicated and so, switch the + * state to KStateFirstUp else to state + * KStateDown. + * + * KStateFirstUp: + * After debounce delay(10ms), if the KPress is + * still reset then pass the key release + * scancode to input device and change + * the state to KStateUp else key release is + * not satisfied so change the state to + * KStateDown. + */ + + for (row = 0; row < kpp_dev.kpp_rows; row++) { + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((press_scancode[row][col] != -1)) { + /* Still Down, so add scancode */ + scancode = + press_scancode[row][col]; + + keyi[index].val = mxckpd_keycodes[scancode]; + keyi[index++].evt = KDepress; + + KPP_PRINTF("KStateFirstDown: scan=%d val=%d\n", + scancode, mxckpd_keycodes[scancode]); + if (index >= key_cnt) + goto key_detect; + + kpp_dev.iKeyState = KStateDown; + press_scancode[row][col] = -1; + } + } + } + + for (row = 0; row < kpp_dev.kpp_rows; row++) { + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((release_scancode[row][col] != -1)) { + scancode = + release_scancode[row][col]; + scancode = + scancode - MXC_KEYRELEASE; + + keyi[index].val = mxckpd_keycodes[scancode]; + keyi[index++].evt = KRelease; + + KPP_PRINTF("KStateFirstUp: scan=%d val=%d\n", + scancode, mxckpd_keycodes[scancode]); + if (index >= key_cnt) + goto key_detect; + + kpp_dev.iKeyState = KStateUp; + release_scancode[row][col] = -1; + } + } + } + +key_detect: + mxc_kpp_reset(); + return key_cnt; +} + +/*! + * This function is called to free the allocated memory for local arrays + */ +static void mxc_kpp_free_allocated(void) +{ + int i; + + if (press_scancode) { + for (i = 0; i < kpp_dev.kpp_rows; i++) { + if (press_scancode[i]) + free(press_scancode[i]); + } + free(press_scancode); + } + + if (release_scancode) { + for (i = 0; i < kpp_dev.kpp_rows; i++) { + if (release_scancode[i]) + free(release_scancode[i]); + } + free(release_scancode); + } + + if (cur_rcmap) + free(cur_rcmap); + + if (prev_rcmap) + free(prev_rcmap); +} + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration. Otherwise returns + * specific error code. + */ +int mxc_kpp_init(void) +{ + int i; + int retval; + unsigned int reg_val; + + kpp_dev.kpp_cols = CONFIG_MXC_KPD_COLMAX; + kpp_dev.kpp_rows = CONFIG_MXC_KPD_ROWMAX; + + /* clock and IOMUX configuration for keypad */ + setup_mxc_kpd(); + + /* Configure keypad */ + + /* Enable number of rows in keypad (KPCR[7:0]) + * Configure keypad columns as open-drain (KPCR[15:8]) + * + * Configure the rows/cols in KPP + * LSB nibble in KPP is for 8 rows + * MSB nibble in KPP is for 8 cols + */ + reg_val = __raw_readw(KPCR); + reg_val |= (1 << kpp_dev.kpp_rows) - 1; /* LSB */ + reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8; /* MSB */ + __raw_writew(reg_val, KPCR); + + /* Write 0's to KPDR[15:8] */ + reg_val = __raw_readw(KPDR); + reg_val &= 0x00ff; + __raw_writew(reg_val, KPDR); + + /* Configure columns as output, + * rows as input (KDDR[15:0]) */ + reg_val = __raw_readw(KDDR); + reg_val |= 0xff00; + reg_val &= 0xff00; + __raw_writew(reg_val, KDDR); + + /* Clear the KPKD Status Flag + * and Synchronizer chain. */ + reg_val = __raw_readw(KPSR); + reg_val &= ~(KBD_STAT_KPKR | KBD_STAT_KPKD); + reg_val |= KBD_STAT_KPKD; + reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + /* Set the KDIE control bit, and clear the KRIE + * control bit (avoid false release events). */ + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + mxckpd_keycodes = mxc_key_mapping; + mxckpd_keycodes_size = kpp_dev.kpp_cols * kpp_dev.kpp_rows; + + if ((mxckpd_keycodes == (void *)0) + || (mxckpd_keycodes_size == 0)) { + retval = -ENODEV; + goto err; + } + + /* allocate required memory */ + press_scancode = (short **)malloc(kpp_dev.kpp_rows * sizeof(press_scancode[0])); + release_scancode = (short **)malloc(kpp_dev.kpp_rows * sizeof(release_scancode[0])); + + if (!press_scancode || !release_scancode) { + retval = -ENOMEM; + goto err; + } + + for (i = 0; i < kpp_dev.kpp_rows; i++) { + press_scancode[i] = (short *)malloc(kpp_dev.kpp_cols + * sizeof(press_scancode[0][0])); + release_scancode[i] = + (short *)malloc(kpp_dev.kpp_cols * sizeof(release_scancode[0][0])); + + if (!press_scancode[i] || !release_scancode[i]) { + retval = -ENOMEM; + goto err; + } + } + + cur_rcmap = + (unsigned short *)malloc(kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + prev_rcmap = + (unsigned short *)malloc(kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + + if (!cur_rcmap || !prev_rcmap) { + retval = -ENOMEM; + goto err; + } + + for (i = 0; i < kpp_dev.kpp_rows; i++) { + memset(press_scancode[i], -1, + sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols); + memset(release_scancode[i], -1, + sizeof(release_scancode[0][0]) * kpp_dev.kpp_cols); + } + memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + memset(prev_rcmap, 0, kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + + return 0; + +err: + mxc_kpp_free_allocated(); + return retval; +} diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 9649b705895..14b5a03c9a0 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -24,4 +24,11 @@ config TEGRA_HSP This enables support for the NVIDIA Tegra HSP Hw module, which implements doorbells, mailboxes, semaphores, and shared interrupts. +config IMX_MU + bool "Enable i.MX MU support" + depends on DM_MAILBOX + help + Enable support for i.MX Messaging Unit for communication with other + processors on the SoC + endmenu diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 155dbeb0994..75cd456678d 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_DM_MAILBOX) += mailbox-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o +obj-$(CONFIG_IMX_MU) += imx-mu.o diff --git a/drivers/mailbox/imx-mu.c b/drivers/mailbox/imx-mu.c new file mode 100644 index 00000000000..d08f9d1500d --- /dev/null +++ b/drivers/mailbox/imx-mu.c @@ -0,0 +1,191 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +#define NUM_MU_CHANNELS 4 +#define NUM_MU_FLAGS 4 +#define NUM_MU_GIP 4 + +#define mu_rr(x) (0x10 + (x * 0x4)) +#define mu_tr(x) (x * 0x4) +#define MU_SR_OFFSET 0x20 +#define MU_CR_OFFSET 0x24 +#define CHAN_TE_MASK(x) (0x00100000 << (x)) +#define CHAN_RF_MASK(x) (0x01000000 << (x)) +#define MU_CR_INT_MSK 0xFFF00000 +#define MU_FLGS_MSK 0x00000007 +#define MU_GIP_MSK 0xF0000000 + + + +/* This driver only exposes the status bits to keep with the + * polling methodology of u-boot. + */ + +DECLARE_GLOBAL_DATA_PTR; + +struct imx_mu_mbox { + fdt_addr_t base; + + /* use pointers to channel as a way to reserve channels */ + void *channels[NUM_MU_CHANNELS]; + bool flags[NUM_MU_FLAGS]; + + /* TODO add support for the reading/setting of flags to + * B side of MU + */ +}; + + +/* check that the channel is open or owned by caller */ +static int mu_check_channel(struct mbox_chan *chan) +{ + struct imx_mu_mbox *mailbox = dev_get_priv(chan->dev); + + /* use id as number of channel within mbox only */ + if ((chan->id < 0) || (chan->id >= NUM_MU_CHANNELS)) { + debug("nxp mu id out of range: %lu\n", chan->id); + return -EINVAL; + } + if (mailbox->channels[chan->id] != NULL) { + /* if reserved check that caller owns */ + if (mailbox->channels[chan->id] == chan) + return 1; /* caller owns the channel */ + + return -EACCES; + } + return 0;/* channel empty */ +} + +static int mu_chan_request(struct mbox_chan *chan) +{ + struct imx_mu_mbox *mailbox = dev_get_priv(chan->dev); + + debug("%s(chan=%p)\n", __func__, chan); + + int status = mu_check_channel(chan); + if (status < 0) { + debug("channel not available :%d\n", status); + return -EPERM; + } + mailbox->channels[chan->id] = chan; + + return 0; +} +/* currently not dynamically allocated + * only change pointer back to NULL */ +static int mu_chan_free(struct mbox_chan *chan) +{ + struct imx_mu_mbox *mailbox = dev_get_priv(chan->dev); + int status = mu_check_channel(chan); + + debug("%s(chan=%p)\n", __func__, chan); + if (status <= 0) { /* check that the channel is also not empty */ + debug("mu_chan_free() failed exit code: %d\n", status); + return status; + } + /*if you own channel and channel is NOT empty */ + mailbox->channels[chan->id] = NULL; + + return 0; +} + +static int mu_send(struct mbox_chan *chan, const void *data) +{ + struct imx_mu_mbox *mbox = dev_get_priv(chan->dev); + int status = mu_check_channel(chan); + uint32_t val = *((uint32_t *)data); + + debug("%s(chan=%p, data=%p)\n", __func__, chan, data); + if (status < 1) { + debug("mu_send() failed. mu_chan_status is :%d\n", status); + return -EPERM; + } + + /*check if transmit register is empty */ + if (!(readl(mbox->base+MU_SR_OFFSET) & CHAN_TE_MASK(chan->id))) + return -EBUSY; + + /* send out on transmit register*/ + writel(val, mbox->base + mu_tr(chan->id)); + return 0; +} + +static int mu_recv(struct mbox_chan *chan, void *data) +{ + struct imx_mu_mbox *mbox = dev_get_priv(chan->dev); + int status = mu_check_channel(chan); + uint32_t *buffer = data; + + debug("%s(chan=%p, data=%p)\n", __func__, chan, data); + + if (status < 1) + return -EPERM; /* return if channel isnt owned */ + + if (readl(mbox->base + MU_SR_OFFSET) & CHAN_RF_MASK(chan->id)) + return -ENODATA; + + *buffer = readl(mu_rr(chan->id)); + + return 0; +} + +static int imx_mu_bind(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +static int imx_mu_probe(struct udevice *dev) +{ + struct imx_mu_mbox *mbox = dev_get_priv(dev); + uint32_t val; + debug("%s(dev=%p)\n", __func__, dev); + + /* get address from device tree */ + mbox->base = dev_get_addr(dev); + if (mbox->base == FDT_ADDR_T_NONE) + return -ENODEV; + + val = readl(mbox->base + MU_CR_OFFSET); + val = val & ~MU_CR_INT_MSK;/* disable all interrupts */ + val = val & ~MU_FLGS_MSK; /* clear all flags */ + + writel(val, mbox->base + MU_CR_OFFSET); + + val = readl(mbox->base + MU_SR_OFFSET); + val = val | MU_GIP_MSK; /* clear any pending GIP */ + writel(val, mbox->base + MU_SR_OFFSET); + + return 0; +} + +static const struct udevice_id imx_mu_ids[] = { + { .compatible = "nxp,imx-mu" }, + { } +}; + +struct mbox_ops imx_mu_mbox_ops = { + .request = mu_chan_request, + .free = mu_chan_free, + .send = mu_send, + .recv = mu_recv, +}; + +U_BOOT_DRIVER(imx_mu) = { + .name = "imx-mu", + .id = UCLASS_MAILBOX, + .of_match = imx_mu_ids, + .bind = imx_mu_bind, + .probe = imx_mu_probe, + .priv_auto_alloc_size = sizeof(struct imx_mu_mbox), + .ops = &imx_mu_mbox_ops, +}; diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c index 822ae5b45e5..e149bf5dca4 100644 --- a/drivers/mailbox/mailbox-uclass.c +++ b/drivers/mailbox/mailbox-uclass.c @@ -100,13 +100,29 @@ int mbox_free(struct mbox_chan *chan) return ops->free(chan); } -int mbox_send(struct mbox_chan *chan, const void *data) +int mbox_send(struct mbox_chan *chan, const void *data, ulong timeout_us) { struct mbox_ops *ops = mbox_dev_ops(chan->dev); + ulong start_time; + int ret; debug("%s(chan=%p, data=%p)\n", __func__, chan, data); - return ops->send(chan, data); + start_time = timer_get_us(); + /* + * Account for partial us ticks, but if timeout_us is 0, ensure we + * still don't wait at all. + */ + if (timeout_us) + timeout_us++; + + for (;;) { + ret = ops->send(chan, data); + if (ret != -EBUSY) + return ret; + if ((timer_get_us() - start_time) >= timeout_us) + return -ETIMEDOUT; + } } int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index d774569cbc2..0b49d964bbe 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -119,6 +119,13 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config IMX_M4_MU + bool "Enable i.MX MU Driver to communicate with Cortex M4" + depends on MISC + help + If you say Y here to enable Message Unit driver to work with + Cortex M4 core on AMP Freescale i.MX processors. + config NUVOTON_NCT6102D bool "Enable Nuvoton NCT6102D Super I/O driver" help diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index e8d598cd47e..f56aaa2d294 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_IMX_M4_MU) += imx_m4_mu.o endif obj-$(CONFIG_FSL_IIM) += fsl_iim.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o diff --git a/drivers/misc/imx_m4_mu.c b/drivers/misc/imx_m4_mu.c new file mode 100644 index 00000000000..237ab33425e --- /dev/null +++ b/drivers/misc/imx_m4_mu.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct mu_type { + u32 tr[4]; + u32 rr[4]; + u32 sr; + u32 cr; +}; + +struct imx_m4_mu { + struct mu_type *base; +}; + +#define MU_CR_GIE_MASK 0xF0000000u +#define MU_CR_RIE_MASK 0xF000000u +#define MU_CR_GIR_MASK 0xF0000u +#define MU_CR_TIE_MASK 0xF00000u +#define MU_CR_F_MASK 0x7u +#define MU_SR_TE0_MASK BIT(23) +#define MU_SR_RF0_MASK BIT(27) +#define MU_TR_COUNT 4 +#define MU_RR_COUNT 4 + +static inline void mu_hal_init(struct mu_type *base) +{ + /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ + clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK | + MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK); +} + +static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg) +{ + u32 mask = MU_SR_TE0_MASK >> reg_index; + u32 val; + int ret; + + assert(reg_index < MU_TR_COUNT); + + debug("sendmsg sr 0x%x\n", readl(&base->sr)); + + /* Wait TX register to be empty. */ + ret = readl_poll_timeout(&base->sr, val, val & mask, 10000); + if (ret < 0) { + debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + debug("tr[%d] 0x%x\n",reg_index, msg); + + writel(msg, &base->tr[reg_index]); + + return 0; +} + +static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg) +{ + u32 mask = MU_SR_RF0_MASK >> reg_index; + u32 val; + int ret; + + assert(reg_index < MU_TR_COUNT); + + debug("receivemsg sr 0x%x\n", readl(&base->sr)); + + /* Wait RX register to be full. */ + ret = readl_poll_timeout(&base->sr, val, val & mask, 10000); + if (ret < 0) { + debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + *msg = readl(&base->rr[reg_index]); + + debug("rr[%d] 0x%x\n",reg_index, *msg); + + return 0; +} + +static int mu_hal_poll_receive(struct mu_type *base, ulong rx_timeout) +{ + u32 mask = MU_SR_RF0_MASK; + u32 val; + int ret; + + debug("receivemsg sr 0x%x\n", readl(&base->sr)); + + /* Wait RX register to be full. */ + ret = readl_poll_timeout(&base->sr, val, val & mask, rx_timeout); + if (ret < 0) { + debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + return 0; +} + +static int imx_m4_mu_read(struct mu_type *base, void *data) +{ + union imx_m4_msg *msg = (union imx_m4_msg *)data; + int ret; + u8 count = 0; + + if (!msg) + return -EINVAL; + + /* Read 4 words */ + while (count < 4) { + ret = mu_hal_receivemsg(base, count % MU_RR_COUNT, + &msg->data[count]); + if (ret) + return ret; + count++; + } + + return 0; +} + +static int imx_m4_mu_write(struct mu_type *base, void *data) +{ + union imx_m4_msg *msg = (union imx_m4_msg *)data; + int ret; + u8 count = 0; + + if (!msg) + return -EINVAL; + + /* Write 4 words */ + while (count < 4) { + ret = mu_hal_sendmsg(base, count % MU_TR_COUNT, + msg->data[count]); + if (ret) + return ret; + count++; + } + + return 0; +} + +/* + * Note the function prototype use msgid as the 2nd parameter, here + * we take it as no_resp. + */ +static int imx_m4_mu_call(struct udevice *dev, int resp_timeout, void *tx_msg, + int tx_size, void *rx_msg, int rx_size) +{ + struct imx_m4_mu *priv = dev_get_priv(dev); + int ret; + + if (resp_timeout < 0) + return -EINVAL; + + if (tx_msg) { + ret = imx_m4_mu_write(priv->base, tx_msg); + if (ret) + return ret; + } + + if (rx_msg) { + if (resp_timeout) { + ret = mu_hal_poll_receive(priv->base, resp_timeout); + if (ret) + return ret; + } + + ret = imx_m4_mu_read(priv->base, rx_msg); + if (ret) + return ret; + } + + return 0; +} + +static int imx_m4_mu_probe(struct udevice *dev) +{ + struct imx_m4_mu *priv = dev_get_priv(dev); + fdt_addr_t addr; + + debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = (struct mu_type *)addr; + + debug("mu base 0x%lx\n", (ulong)priv->base); + + /* U-Boot not enable interrupts, so need to enable RX interrupts */ + mu_hal_init(priv->base); + + return 0; +} + +static int imx_m4_mu_remove(struct udevice *dev) +{ + return 0; +} + +static int imx_m4_mu_bind(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +static struct misc_ops imx_m4_mu_ops = { + .call = imx_m4_mu_call, +}; + +static const struct udevice_id imx_m4_mu_ids[] = { + { .compatible = "fsl,imx-m4-mu" }, + { } +}; + +U_BOOT_DRIVER(imx_m4_mu) = { + .name = "imx_m4_mu", + .id = UCLASS_MISC, + .of_match = imx_m4_mu_ids, + .probe = imx_m4_mu_probe, + .bind = imx_m4_mu_bind, + .remove = imx_m4_mu_remove, + .ops = &imx_m4_mu_ops, + .priv_auto_alloc_size = sizeof(struct imx_m4_mu), +}; diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 8662e82cfa1..ff856a3e38c 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -35,7 +35,7 @@ #define BM_OUT_STATUS_DED 0x00000400 #define BM_OUT_STATUS_LOCKED 0x00000800 #define BM_OUT_STATUS_PROGFAIL 0x00001000 -#elif defined(CONFIG_MX8M) +#elif defined(CONFIG_IMX8M) #define BM_CTRL_ADDR 0x000000ff #else #define BM_CTRL_ADDR 0x0000007f @@ -81,7 +81,7 @@ #elif defined(CONFIG_MX7ULP) #define FUSE_BANK_SIZE 0x80 #define FUSE_BANKS 31 -#elif defined(CONFIG_MX8M) +#elif defined(CONFIG_IMX8M) #define FUSE_BANK_SIZE 0x40 #define FUSE_BANKS 64 #else @@ -299,7 +299,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; #ifdef CONFIG_MX7 u32 addr = bank; -#elif defined CONFIG_MX8M +#elif defined CONFIG_IMX8M u32 addr = bank << 2 | word; #else u32 addr; @@ -322,6 +322,11 @@ int fuse_sense(u32 bank, u32 word, u32 *val) struct ocotp_regs *regs; int ret; + if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) { + printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__); + return -EPERM; + } + ret = prepare_read(®s, bank, word, val, __func__); if (ret) return ret; @@ -355,13 +360,16 @@ static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word, /* Only bank 0 and 1 are redundancy mode, others are ECC mode */ if (bank != 0 && bank != 1) { - ret = fuse_sense(bank, word, &val); - if (ret) - return ret; - - if (val != 0) { - printf("mxc_ocotp: The word has been programmed, no more write\n"); - return -EPERM; + if ((soc_rev() < CHIP_REV_2_0) || + ((soc_rev() >= CHIP_REV_2_0) && bank != 9 && bank != 10 && bank != 28)) { + ret = fuse_sense(bank, word, &val); + if (ret) + return ret; + + if (val != 0) { + printf("mxc_ocotp: The word has been programmed, no more write\n"); + return -EPERM; + } } } #endif diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 5f67e336dba..c4df67d511d 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -104,6 +104,19 @@ config SPL_MMC_UHS_SUPPORT cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus frequency can go up to 208MHz (SDR104) +config MMC_HS400_ES_SUPPORT + bool "enable HS400 Enhanced Strobe support" + help + The HS400 Enhanced Strobe mode is support by some eMMC. The bus frequency is up to + 200MHz. This mode does not tune the IO. + +config MMC_HS400_SUPPORT + bool "enable HS400 support" + select MMC_HS200_SUPPORT + help + The HS400 mode is support by some eMMC. The bus frequency is up to + 200MHz. This mode requires tuning the IO. + config MMC_HS200_SUPPORT bool "enable HS200 support" help diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 6018f84307d..cb454d55b15 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -24,6 +24,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -258,7 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, int timeout; struct fsl_esdhc *regs = priv->esdhc_regs; #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) dma_addr_t addr; #endif uint wml_value; @@ -272,7 +273,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->dest)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -296,13 +297,20 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); return -ETIMEDOUT; } + } else { +#ifdef CONFIG_DM_GPIO + if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) { + printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); + return -ETIMEDOUT; + } +#endif } esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, wml_value << 16); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->src)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -368,7 +376,7 @@ static void check_and_invalidate_dcache_range unsigned size = roundup(ARCH_DMA_MINALIGN, data->blocks*data->blocksize); #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) dma_addr_t addr; addr = virt_to_phys((void *)(data->dest)); @@ -478,9 +486,9 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { - int timeout = 6000; + int timeout = 62000; - /* Poll on DATA0 line for cmd with busy signal for 600 ms */ + /* Poll on DATA0 line for cmd with busy signal for 6200 ms */ while (timeout > 0 && !(esdhc_read32(®s->prsstat) & PRSSTAT_DAT0)) { udelay(100); @@ -584,18 +592,31 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) #else int pre_div = 2; #endif - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; int sdhc_clk = priv->sdhc_clk; uint clk; + /* + * For ddr mode, usdhc need to enable DDR mode first, after select + * this DDR mode, usdhc will automatically divide the usdhc clock + */ + if (mmc->ddr_mode) { + writel(readl(®s->mixctrl) | MIX_CTRL_DDREN, ®s->mixctrl); + sdhc_clk >>= 1; + } + if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min; - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) - pre_div *= 2; + if (sdhc_clk / 16 > clock) { + for (; pre_div < 256; pre_div *= 2) + if ((sdhc_clk / pre_div) <= (clock * 16)) + break; + } else + pre_div = 1; - while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) - div++; + for (div = 1; div <= 16; div++) + if ((sdhc_clk / (div * pre_div)) <= clock) + break; pre_div >>= 1; div -= 1; @@ -663,6 +684,8 @@ static int esdhc_change_pinstate(struct udevice *dev) break; case UHS_SDR104: case MMC_HS_200: + case MMC_HS_400: + case MMC_HS_400_ES: ret = pinctrl_select_state(dev, "state_200mhz"); break; default: @@ -690,6 +713,33 @@ static void esdhc_reset_tuning(struct mmc *mmc) } } +static void esdhc_set_strobe_dll(struct mmc *mmc) +{ + struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); + struct fsl_esdhc *regs = priv->esdhc_regs; + u32 v; + + if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { + writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl); + + /* + * enable strobe dll ctrl and adjust the delay target + * for the uSDHC loopback read clock + */ + v = ESDHC_STROBE_DLL_CTRL_ENABLE | + (priv->strobe_dll_delay_target << + ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); + writel(v, ®s->strobe_dllctrl); + /* wait 1us to make sure strobe dll status register stable */ + mdelay(1); + v = readl(®s->strobe_dllstat); + if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) + pr_warn("HS400 strobe DLL status REF not lock!\n"); + if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) + pr_warn("HS400 strobe DLL status SLV not lock!\n"); + } +} + static int esdhc_set_timing(struct mmc *mmc) { struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); @@ -703,6 +753,13 @@ static int esdhc_set_timing(struct mmc *mmc) case MMC_LEGACY: case SD_LEGACY: esdhc_reset_tuning(mmc); + writel(mixctrl, ®s->mixctrl); + break; + case MMC_HS_400: + case MMC_HS_400_ES: + mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN; + writel(mixctrl, ®s->mixctrl); + esdhc_set_strobe_dll(mmc); break; case MMC_HS: case MMC_HS_52: @@ -1244,6 +1301,14 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) return ret; } +#ifdef CONFIG_MX6 + if (mx6_esdhc_fused(cfg->esdhc_base)) { + printf("ESDHC@0x%lx is fused, disable it\n", cfg->esdhc_base); + free(priv); + return -ENODEV; + } +#endif + ret = fsl_esdhc_init(priv, plat); if (ret) { debug("%s init failure\n", __func__); @@ -1372,6 +1437,13 @@ static int fsl_esdhc_probe(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; +#ifdef CONFIG_MX6 + if (mx6_esdhc_fused(addr)) { + printf("ESDHC@0x%lx is fused, disable it\n", addr); + return -ENODEV; + } +#endif + priv->esdhc_regs = (struct fsl_esdhc *)addr; priv->dev = dev; priv->mode = -1; @@ -1407,14 +1479,15 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif } - priv->wp_enable = 1; - + if (dev_read_prop(dev, "fsl,wp-controller", NULL)) { + priv->wp_enable = 1; + } else { + priv->wp_enable = 0; #ifdef CONFIG_DM_GPIO - ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, + gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); - if (ret) - priv->wp_enable = 0; #endif + } priv->vs18_enable = 0; @@ -1439,7 +1512,7 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif if (fdt_get_property(fdt, node, "no-1-8-v", NULL)) - priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200); + priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES); /* * TODO: @@ -1488,7 +1561,6 @@ static int fsl_esdhc_get_cd(struct udevice *dev) { struct fsl_esdhc_priv *priv = dev_get_priv(dev); - return true; return esdhc_getcd_common(priv); } @@ -1509,6 +1581,19 @@ static int fsl_esdhc_set_ios(struct udevice *dev) return esdhc_set_ios_common(priv, &plat->mmc); } +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) +static void fsl_esdhc_set_enhanced_strobe(struct udevice *dev) +{ + struct fsl_esdhc_priv *priv = dev_get_priv(dev); + struct fsl_esdhc *regs = priv->esdhc_regs; + u32 m; + + m = readl(®s->mixctrl); + m |= MIX_CTRL_HS400_ES; + writel(m, ®s->mixctrl); +} +#endif + static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, @@ -1516,6 +1601,9 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { #ifdef MMC_SUPPORTS_TUNING .execute_tuning = fsl_esdhc_execute_tuning, #endif +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) + .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe, +#endif }; #endif @@ -1527,6 +1615,15 @@ static struct esdhc_soc_data usdhc_imx7d_data = { MMC_MODE_HS_52MHz | MMC_MODE_HS, }; +static struct esdhc_soc_data usdhc_imx8qm_data = { + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 + | ESDHC_FLAG_HS400 |ESDHC_FLAG_HS400_ES, + .caps = UHS_CAPS | MMC_MODE_HS400 | MMC_MODE_HS400_ES | + MMC_MODE_HS200 | MMC_MODE_DDR_52MHz | + MMC_MODE_HS_52MHz | MMC_MODE_HS, +}; + static const struct udevice_id fsl_esdhc_ids[] = { { .compatible = "fsl,imx6ul-usdhc", }, { .compatible = "fsl,imx6sx-usdhc", }, @@ -1534,6 +1631,7 @@ static const struct udevice_id fsl_esdhc_ids[] = { { .compatible = "fsl,imx6q-usdhc", }, { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, { .compatible = "fsl,imx7ulp-usdhc", }, + { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,esdhc", }, { /* sentinel */ } }; diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index a3536b15ae6..cf628a8b254 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -123,6 +123,21 @@ int mmc_execute_tuning(struct mmc *mmc, uint opcode) } #endif +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) +void dm_mmc_set_enhanced_strobe(struct udevice *dev) +{ + struct dm_mmc_ops *ops = mmc_get_ops(dev); + + if (ops->set_enhanced_strobe) + ops->set_enhanced_strobe(dev); +} + +void mmc_set_enhanced_strobe(struct mmc *mmc) +{ + dm_mmc_set_enhanced_strobe(mmc->dev); +} +#endif + int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg) { int val; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c9308933003..85762b82e0a 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -169,6 +169,8 @@ const char *mmc_mode_name(enum bus_mode mode) [MMC_HS_52] = "MMC High Speed (52MHz)", [MMC_DDR_52] = "MMC DDR52 (52MHz)", [MMC_HS_200] = "HS200 (200MHz)", + [MMC_HS_400] = "HS400 (200MHz)", + [MMC_HS_400_ES] = "HS400ES (200MHz)", }; if (mode >= MMC_MODES_END) @@ -193,6 +195,8 @@ static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode) [UHS_DDR50] = 50000000, [UHS_SDR104] = 208000000, [MMC_HS_200] = 200000000, + [MMC_HS_400] = 200000000, + [MMC_HS_400_ES] = 200000000, }; if (mode == MMC_LEGACY) @@ -744,7 +748,8 @@ static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) return err; } -int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) +static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, + bool send_status) { struct mmc_cmd cmd; int timeout = 1000; @@ -760,20 +765,31 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) while (retries > 0) { ret = mmc_send_cmd(mmc, &cmd, NULL); - /* Waiting for the ready status */ - if (!ret) { - ret = mmc_send_status(mmc, timeout); - return ret; + if (ret) { + retries--; + continue; + } + + if (!send_status) { + mdelay(50); + return 0; } - retries--; + /* Waiting for the ready status */ + return mmc_send_status(mmc, timeout); } return ret; } -static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode) +int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) +{ + return __mmc_switch(mmc, set, index, value, true); +} + +static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode, + bool hsdowngrade) { int err; int speed_bits; @@ -790,6 +806,16 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode) case MMC_HS_200: speed_bits = EXT_CSD_TIMING_HS200; break; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + case MMC_HS_400: + speed_bits = EXT_CSD_TIMING_HS400; + break; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) + case MMC_HS_400_ES: + speed_bits = EXT_CSD_TIMING_HS400; + break; #endif case MMC_LEGACY: speed_bits = EXT_CSD_TIMING_LEGACY; @@ -797,11 +823,26 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode) default: return -EINVAL; } - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, - speed_bits); + + err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, + speed_bits, !hsdowngrade); if (err) return err; +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + /* + * In case the eMMC is in HS200/HS400 mode and we are downgrading + * to HS mode, the card clock are still running much faster than + * the supported HS mode clock, so we can not reliably read out + * Extended CSD. Reconfigure the controller to run at HS mode. + */ + if (hsdowngrade) { + mmc_select_mode(mmc, MMC_HS); + mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); + } +#endif + if ((mode == MMC_HS) || (mode == MMC_HS_52)) { /* Now check to see that it worked */ err = mmc_send_ext_csd(mmc, test_csd); @@ -837,7 +878,7 @@ static int mmc_get_capabilities(struct mmc *mmc) mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; - cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f; + cardtype = ext_csd[EXT_CSD_CARD_TYPE]; mmc->cardtype = cardtype; #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) @@ -845,6 +886,12 @@ static int mmc_get_capabilities(struct mmc *mmc) EXT_CSD_CARD_TYPE_HS200_1_8V)) { mmc->card_caps |= MMC_MODE_HS200; } +#endif +#if (CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)) + if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V | + EXT_CSD_CARD_TYPE_HS400_1_8V)) { + mmc->card_caps |= MMC_MODE_HS400; + } #endif if (cardtype & EXT_CSD_CARD_TYPE_52) { if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) @@ -854,6 +901,11 @@ static int mmc_get_capabilities(struct mmc *mmc) if (cardtype & EXT_CSD_CARD_TYPE_26) mmc->card_caps |= MMC_MODE_HS; +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) + if (ext_csd[EXT_CSD_STROBE_SUPPORT] && (mmc->card_caps & MMC_MODE_HS400)) + mmc->card_caps |= MMC_MODE_HS400_ES; +#endif + return 0; } @@ -1689,7 +1741,7 @@ static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps) #if CONFIG_IS_ENABLED(MMC_WRITE) err = sd_read_ssr(mmc); - if (!err) + if (err) pr_warn("unable to read ssr\n"); #endif if (!err) @@ -1748,6 +1800,13 @@ static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, u32 card_mask = 0; switch (mode) { + case MMC_HS_400_ES: + case MMC_HS_400: + if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS400_1_8V) + card_mask |= MMC_SIGNAL_VOLTAGE_180; + if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS400_1_2V) + card_mask |= MMC_SIGNAL_VOLTAGE_120; + break; case MMC_HS_200: if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V) card_mask |= MMC_SIGNAL_VOLTAGE_180; @@ -1787,6 +1846,19 @@ static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, #endif static const struct mode_width_tuning mmc_modes_by_pref[] = { +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) + { + .mode = MMC_HS_400_ES, + .widths = MMC_MODE_8BIT, + }, +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + { + .mode = MMC_HS_400, + .widths = MMC_MODE_8BIT | MMC_MODE_4BIT, + .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200 + }, +#endif #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) { .mode = MMC_HS_200, @@ -1830,6 +1902,98 @@ static const struct ext_csd_bus_width { {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1}, }; +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) +static int mmc_select_hs400(struct mmc *mmc) +{ + int err; + + /* Set timing to HS200 for tuning */ + err = mmc_set_card_speed(mmc, MMC_HS_200, false); + if (err) + return err; + + /* configure the bus mode (host) */ + mmc_select_mode(mmc, MMC_HS_200); + mmc_set_clock(mmc, mmc->tran_speed, false); + + /* execute tuning if needed */ + err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200); + if (err) { + debug("tuning failed\n"); + return err; + } + + /* Set back to HS */ + mmc_set_card_speed(mmc, MMC_HS, true); + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, + EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG); + if (err) + return err; + + err = mmc_set_card_speed(mmc, MMC_HS_400, false); + if (err) + return err; + + mmc_select_mode(mmc, MMC_HS_400); + err = mmc_set_clock(mmc, mmc->tran_speed, false); + if (err) + return err; + + return 0; +} +#else +static int mmc_select_hs400(struct mmc *mmc) +{ + return -ENOTSUPP; +} +#endif + +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) +#if !CONFIG_IS_ENABLED(DM_MMC) +static void mmc_set_enhanced_strobe(struct mmc *mmc) +{ + return; +} +#endif + +static int mmc_select_hs400es(struct mmc *mmc) +{ + int err; + + err = mmc_set_card_speed(mmc, MMC_HS, true); + if (err) + return err; + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8 | + EXT_CSD_DDR_FLAG | EXT_CSD_BUS_WIDTH_STROBE); + if (err) { + printf("switch to bus width for hs400 failed\n"); + return err; + } + /* TODO: driver strength */ + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400 | (0 << EXT_CSD_DRV_STR_SHIFT)); + if (err) { + printf("switch to hs400 failed\n"); + return err; + } + + mmc_select_mode(mmc, MMC_HS_400_ES); + mmc_set_clock(mmc, mmc->tran_speed, false); + mmc_set_enhanced_strobe(mmc); + + return 0; +} + +#else +static int mmc_select_hs400es(struct mmc *mmc) +{ + return -ENOTSUPP; +} +#endif + #define for_each_supported_width(caps, ddr, ecbv) \ for (ecbv = ext_csd_bus_width;\ ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\ @@ -1859,6 +2023,18 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) return -ENOTSUPP; } +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + /* + * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode + * before doing anything else, since a transition from either of + * the HS200/HS400 mode directly to legacy mode is not supported. + */ + if (mmc->selected_mode == MMC_HS_200 || + mmc->selected_mode == MMC_HS_400) + mmc_set_card_speed(mmc, MMC_HS, true); + else +#endif mmc_set_clock(mmc, mmc->legacy_speed, false); for_each_mmc_mode_by_pref(card_caps, mwt) { @@ -1883,37 +2059,50 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) goto error; mmc_set_bus_width(mmc, bus_width(ecbw->cap)); - /* configure the bus speed (card) */ - err = mmc_set_card_speed(mmc, mwt->mode); - if (err) - goto error; - - /* - * configure the bus width AND the ddr mode (card) - * The host side will be taken care of in the next step - */ - if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, - EXT_CSD_BUS_WIDTH, - ecbw->ext_csd_bits); + if (mwt->mode == MMC_HS_400) { + err = mmc_select_hs400(mmc); + if (err) + goto error; + } else if (mwt->mode == MMC_HS_400_ES) { + err = mmc_select_hs400es(mmc); + if (err) + goto error; + } else { + /* configure the bus speed (card) */ + err = mmc_set_card_speed(mmc, mwt->mode, false); if (err) goto error; - } - /* configure the bus mode (host) */ - mmc_select_mode(mmc, mwt->mode); - mmc_set_clock(mmc, mmc->tran_speed, false); + /* + * configure the bus width AND the ddr mode + * (card). The host side will be taken care + * of in the next step + */ + if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { + err = mmc_switch(mmc, + EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, + ecbw->ext_csd_bits); + if (err) + goto error; + } + + /* configure the bus mode (host) */ + mmc_select_mode(mmc, mwt->mode); + mmc_set_clock(mmc, mmc->tran_speed, false); #ifdef MMC_SUPPORTS_TUNING - /* execute tuning if needed */ - if (mwt->tuning) { - err = mmc_execute_tuning(mmc, mwt->tuning); - if (err) { - pr_debug("tuning failed\n"); - goto error; + /* execute tuning if needed */ + if (mwt->tuning) { + err = mmc_execute_tuning(mmc, + mwt->tuning); + if (err) { + pr_debug("tuning failed\n"); + goto error; + } } - } #endif + } /* do a transfer to check the configuration */ err = mmc_read_and_compare_ext_csd(mmc); diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c index 0b6b6222bdc..c062d6868a4 100644 --- a/drivers/mmc/rpmb.c +++ b/drivers/mmc/rpmb.c @@ -40,12 +40,6 @@ #define RPMB_ERR_CNT_EXPIRED 0x80 #define RPMB_ERR_MSK 0x7 -/* Sizes of RPMB data frame */ -#define RPMB_SZ_STUFF 196 -#define RPMB_SZ_MAC 32 -#define RPMB_SZ_DATA 256 -#define RPMB_SZ_NONCE 16 - #define SHA256_BLOCK_SIZE 64 /* Error messages */ @@ -60,20 +54,6 @@ static const char * const rpmb_err_msg[] = { "Authentication key not yet programmed", }; - -/* Structure of RPMB data frame. */ -struct s_rpmb { - unsigned char stuff[RPMB_SZ_STUFF]; - unsigned char mac[RPMB_SZ_MAC]; - unsigned char data[RPMB_SZ_DATA]; - unsigned char nonce[RPMB_SZ_NONCE]; - unsigned int write_counter; - unsigned short address; - unsigned short block_count; - unsigned short result; - unsigned short request; -}; - static int mmc_set_blockcount(struct mmc *mmc, unsigned int blockcount, bool is_rel_write) { @@ -87,7 +67,7 @@ static int mmc_set_blockcount(struct mmc *mmc, unsigned int blockcount, return mmc_send_cmd(mmc, &cmd, NULL); } -static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, +int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, unsigned int count, bool is_rel_write) { struct mmc_cmd cmd = {0}; @@ -107,7 +87,7 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, cmd.resp_type = MMC_RSP_R1b; data.src = (const char *)s; - data.blocks = 1; + data.blocks = count; data.blocksize = MMC_MAX_BLOCK_LEN; data.flags = MMC_DATA_WRITE; @@ -120,14 +100,14 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, } return 0; } -static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, - unsigned short expected) +int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, + unsigned int count, unsigned short expected) { struct mmc_cmd cmd = {0}; struct mmc_data data; int ret; - ret = mmc_set_blockcount(mmc, 1, false); + ret = mmc_set_blockcount(mmc, count, false); if (ret) { #ifdef CONFIG_MMC_RPMB_TRACE printf("%s:mmc_set_blockcount-> %d\n", __func__, ret); @@ -139,7 +119,7 @@ static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, cmd.resp_type = MMC_RSP_R1; data.dest = (char *)s; - data.blocks = 1; + data.blocks = count; data.blocksize = MMC_MAX_BLOCK_LEN; data.flags = MMC_DATA_READ; @@ -151,7 +131,7 @@ static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, return -1; } /* Check the response and the status */ - if (be16_to_cpu(s->request) != expected) { + if (expected && be16_to_cpu(s->request) != expected) { #ifdef CONFIG_MMC_RPMB_TRACE printf("%s:response= %x\n", __func__, be16_to_cpu(s->request)); @@ -178,7 +158,7 @@ static int mmc_rpmb_status(struct mmc *mmc, unsigned short expected) return -1; /* Read the result */ - return mmc_rpmb_response(mmc, rpmb_frame, expected); + return mmc_rpmb_response(mmc, rpmb_frame, 1, expected); } static void rpmb_hmac(unsigned char *key, unsigned char *buff, int len, unsigned char *output) @@ -236,7 +216,7 @@ int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *pcounter) return -1; /* Read the result */ - ret = mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_WCOUNTER); + ret = mmc_rpmb_response(mmc, rpmb_frame, 1, RPMB_RESP_WCOUNTER); if (ret) return ret; @@ -272,7 +252,7 @@ int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, break; /* Read the result */ - if (mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_READ_DATA)) + if (mmc_rpmb_response(mmc, rpmb_frame, 1, RPMB_RESP_READ_DATA)) break; /* Check the HMAC if key is provided */ diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index a820af61cee..a5872edbdf9 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -149,6 +149,13 @@ config NAND_MXS This enables NAND driver for the NAND flash controller on the MXS processors. +config NAND_MXS_BCH_LEGACY_GEO + bool "Keep using legacy bch geometry for MXS NAND driver" + depends on NAND_MXS + help + Users can use legacy bch geometry in u-boot by enabling this configuration. + NOTICE: the feature must be enabled/disabled in both u-boot and kernel. + config NAND_ZYNQ bool "Support for Zynq Nand controller" select SYS_NAND_SELF_INIT diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 9f7d9d6ff7a..06f1b3f38ce 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -72,6 +72,7 @@ else # minimal SPL drivers obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o +obj-y += nand_ids.o obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index bed9b65ef40..e2df50f791b 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -7,8 +7,9 @@ * Based on code from LTIB: * Freescale GPMI NFC NAND Flash Driver * - * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -30,7 +31,7 @@ #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 -#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2 #else #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0 @@ -46,6 +47,11 @@ #define MXS_NAND_BCH_TIMEOUT 10000 +int bbm_chunk; +int ecc_strength; +bool large_oob_flag; +bool ecc_for_meta; + struct mxs_nand_info { int cur_chip; @@ -76,27 +82,35 @@ struct nand_ecclayout fake_ecc_layout; static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE; static int galois_field = 13; +static uint8_t scan_ff_pattern[] = { 0xff }; +static struct nand_bbt_descr gpmi_bbt_descr = { + .options = 0, + .offs = 0, + .len = 1, + .pattern = scan_ff_pattern +}; + /* * Cache management functions */ #ifndef CONFIG_SYS_DCACHE_OFF static void mxs_nand_flush_data_buf(struct mxs_nand_info *info) { - uint32_t addr = (uint32_t)info->data_buf; + uint32_t addr = (uintptr_t)info->data_buf; flush_dcache_range(addr, addr + info->data_buf_size); } static void mxs_nand_inval_data_buf(struct mxs_nand_info *info) { - uint32_t addr = (uint32_t)info->data_buf; + uint32_t addr = (uintptr_t)info->data_buf; invalidate_dcache_range(addr, addr + info->data_buf_size); } static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) { - uint32_t addr = (uint32_t)info->cmd_buf; + uint32_t addr = (uintptr_t)info->cmd_buf; flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE); } @@ -137,7 +151,8 @@ static void mxs_nand_return_dma_descs(struct mxs_nand_info *info) static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size) { - return page_data_size / chunk_data_size; + int tmp = page_data_size / chunk_data_size; + return ecc_for_meta ? tmp + 1 : tmp; } static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength) @@ -150,32 +165,113 @@ static uint32_t mxs_nand_aux_status_offset(void) return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3; } -static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, - uint32_t page_oob_size) +/* + * For some large oob NAND chip( the oob larger than data chunk), combined meta + * with chunk0 style bch layout might override the bbm with ecc data. The + * function checked if bbm can be in the data chunk. If it is true, chunk_num + * indicate the chunk number that bbm located. + * + */ +static bool mxs_nand_bbm_in_data_chunk(struct mtd_info *mtd, int gf_len, + int *chunk_num) +{ + int i, j; + int meta = MXS_NAND_METADATA_SIZE; + + i = (mtd->writesize * 8 - meta * 8) / + (gf_len * ecc_strength + + chunk_data_size * 8); + + j = (mtd->writesize * 8 - meta * 8) % + (gf_len * ecc_strength + + chunk_data_size * 8); + + if (j < chunk_data_size * 8) { + *chunk_num = i+1; + return true; + } + + return false; +} + +/* + * the work flow about how to set the ecc layout + * + * 1. if ecc_strength_ds>max_soc_ecc, quit + * 2. if ecc_strength_ds>0 and ecc_stride_ds>0, + * if ecc_stride_ds > oob, go to large_oob branch + * else go to normal branch + * 3. if either ecc_stride_ds<=0 or ecc_stride_ds<=0, quit + * + */ +static int mxs_nand_get_ecc_strength(struct mtd_info *mtd) { - int ecc_strength; + struct nand_chip *chip = mtd_to_nand(mtd); + uint32_t page_oob_size = mtd->oobsize; + int meta = MXS_NAND_METADATA_SIZE; int max_ecc_strength_supported; /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ - if (is_mx6sx() || is_mx7()) + if (is_mx6sx() || is_mx7() || is_imx8() || is_imx8m()) max_ecc_strength_supported = 62; else max_ecc_strength_supported = 40; - /* - * Determine the ECC layout with the formula: - * ECC bits per chunk = (total page spare data bits) / - * (bits per ECC level) / (chunks per page) - * where: - * total page spare data bits = - * (page oob size - meta data size) * (bits per byte) - */ - ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8) - / (galois_field * - mxs_nand_ecc_chunk_cnt(page_data_size)); + if (chip->ecc_strength_ds > max_ecc_strength_supported) { + printf("cannot support the NAND, ecc too weak\n"); + return -EINVAL; + } - return min(round_down(ecc_strength, 2), max_ecc_strength_supported); -} + if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) && + !(page_oob_size > 1024)) { + printf("cannot support the NAND, missing necessary info\n"); + return -EINVAL; + } + + /* set some parameters according to NAND chip parameters */ + chunk_data_size = chip->ecc_step_ds; + if (1024 == chunk_data_size) + galois_field = 14; + if (chunk_data_size < page_oob_size) + large_oob_flag = true; + + if (large_oob_flag) { + /* start from the minimum ecc NAND chips required */ + ecc_strength = chip->ecc_strength_ds; + while (!(ecc_strength > max_ecc_strength_supported)) { + if (mxs_nand_bbm_in_data_chunk(mtd, + galois_field, + &bbm_chunk)) + break; + ecc_strength += 2; + } + /* + * if all supported ecc cannot satisfy the bbm + * requirement, change * the ecc layout to meta + * with ecc type. + * + */ + if (ecc_strength > max_ecc_strength_supported) { + ecc_strength = chip->ecc_strength_ds; + ecc_for_meta = true; + /* calculate in which chunk bbm located */ + bbm_chunk = (mtd->writesize * 8 - meta * 8 - + galois_field * ecc_strength) / + (galois_field * ecc_strength + + chunk_data_size * 8) + 1; + } + } else { + ecc_strength = chip->ecc_strength_ds; + ecc_strength += ecc_strength & 1; +#if defined(CONFIG_NAND_MXS_BCH_LEGACY_GEO) + ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8) + /(galois_field * mxs_nand_ecc_chunk_cnt(mtd->writesize)); + ecc_strength += ecc_strength & 1; + ecc_strength = min(ecc_strength, MXS_NAND_MAX_ECC_STRENGTH); +#endif + } + return 0; +}; static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, uint32_t ecc_strength) @@ -196,8 +292,13 @@ static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, /* Compute the bit offset of the block mark within the physical page. */ block_mark_bit_offset = page_data_size * 8; - /* Subtract the metadata bits. */ - block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8; + if (ecc_for_meta) + /* Subtract the metadata bits and ecc bits. */ + block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8 + + chunk_ecc_size_in_bits; + else + /* Subtract the metadata bits. */ + block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8; /* * Compute the chunk number (starting at zero) in which the block mark @@ -228,15 +329,11 @@ static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd) { - uint32_t ecc_strength; - ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize); return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3; } static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd) { - uint32_t ecc_strength; - ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize); return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7; } @@ -557,6 +654,45 @@ static uint8_t mxs_nand_read_byte(struct mtd_info *mtd) return buf; } +static bool mxs_nand_erased_page(struct mtd_info *mtd, struct nand_chip *nand, + uint8_t *buf, int chunk, int page) +{ + int gf_len = galois_field; + unsigned int flip_bits = 0, flip_bits_noecc = 0; + unsigned int threshold; + unsigned int ecc_chunkn_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE; + unsigned int base = ecc_chunkn_size * chunk; + uint32_t *dma_buf = (uint32_t *)buf; + int i; + + threshold = gf_len / 2; + if (threshold > ecc_strength) + threshold = ecc_strength; + + for (i = 0; i < ecc_chunkn_size; i++) { + flip_bits += hweight8(~buf[base + i]); + if (flip_bits > threshold) + return false; + } + + nand->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + nand->read_buf(mtd, buf, mtd->writesize); + + for (i = 0; i < mtd->writesize / 4; i++) { + flip_bits_noecc += hweight32(~dma_buf[i]); + if (flip_bits_noecc > threshold) + return false; + } + + mtd->ecc_stats.corrected += flip_bits; + + memset(buf, 0xff, mtd->writesize); + + printf("The page(%d) is an erased page(%d,%d,%d,%d).\n", page, chunk, threshold, flip_bits, flip_bits_noecc); + + return true; +} + /* * Read a page from NAND. */ @@ -566,10 +702,12 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, { struct mxs_nand_info *nand_info = nand_get_controller_data(nand); struct mxs_dma_desc *d; + struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; uint32_t corrected = 0, failed = 0; uint8_t *status; int i, ret; + int flag = 0; /* Compile the DMA descriptor - wait for ready. */ d = mxs_nand_get_dma_desc(nand_info); @@ -659,6 +797,8 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, goto rtn; } + mxs_nand_return_dma_descs(nand_info); + /* Invalidate caches */ mxs_nand_inval_data_buf(nand_info); @@ -671,10 +811,18 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, if (status[i] == 0x00) continue; - if (status[i] == 0xff) + if (status[i] == 0xff) { + if (is_mx6dqp() || is_mx7() || + is_mx6ul() || is_imx8() || is_imx8m()) + if (readl(&bch_regs->hw_bch_debug1)) + flag = 1; continue; + } if (status[i] == 0xfe) { + if (mxs_nand_erased_page(mtd, nand, + nand_info->data_buf, i, page)) + break; failed++; continue; } @@ -701,6 +849,9 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, memcpy(buf, nand_info->data_buf, mtd->writesize); + if (flag) + memset(buf, 0xff, mtd->writesize); + rtn: mxs_nand_return_dma_descs(nand_info); @@ -992,15 +1143,10 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd) struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; uint32_t tmp; - if (mtd->oobsize > MXS_NAND_CHUNK_DATA_CHUNK_SIZE) { - galois_field = 14; - chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 2; - } - if (mtd->oobsize > chunk_data_size) { - printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", chunk_data_size); - return -EINVAL; - } + + /* calculate ecc_strength, bbm_chunk, eec_for meta, if necessary */ + mxs_nand_get_ecc_strength(mtd); /* Configure BCH and set NFC geometry */ mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); @@ -1009,22 +1155,33 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd) tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET; - tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1) + tmp |= (ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET; - tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; - tmp |= (14 == galois_field ? 1 : 0) << - BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET; + if (!ecc_for_meta) + tmp |= chunk_data_size + >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; + else + /* set data0 size as 0 */ + tmp &= ~BCH_FLASHLAYOUT0_DATA0_SIZE_MASK; + tmp |= (14 == galois_field ? 1 : 0) + << BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET; writel(tmp, &bch_regs->hw_bch_flash0layout0); tmp = (mtd->writesize + mtd->oobsize) << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET; - tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1) + tmp |= (ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET; tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; tmp |= (14 == galois_field ? 1 : 0) << BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET; writel(tmp, &bch_regs->hw_bch_flash0layout1); + /* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */ + if (is_mx6dqp() || is_mx7() || + is_mx6ul() || is_imx8() || is_imx8m()) + writel(BCH_MODE_ERASE_THRESHOLD(ecc_strength), + &bch_regs->hw_bch_mode); + /* Set *all* chip selects to use layout 0 */ writel(0, &bch_regs->hw_bch_layoutselect); @@ -1097,6 +1254,13 @@ int mxs_nand_init(struct mxs_nand_info *info) (struct mxs_bch_regs *)MXS_BCH_BASE; int i = 0, j, ret = 0; +#ifdef CONFIG_MX6 + if (check_module_fused(MX6_MODULE_GPMI)) { + printf("NAND GPMI@0x%x is fused, disable it\n", MXS_GPMI_BASE); + return -EPERM; + } +#endif + info->desc = malloc(sizeof(struct mxs_dma_desc *) * MXS_NAND_DMA_DESCRIPTOR_COUNT); if (!info->desc) { @@ -1183,6 +1347,8 @@ int board_nand_init(struct nand_chip *nand) nand_set_controller_data(nand, nand_info); nand->options |= NAND_NO_SUBPAGE_WRITE; + nand->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; + nand->badblock_pattern = &gpmi_bbt_descr; nand->cmd_ctrl = mxs_nand_cmd_ctrl; diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c index 910f76dd9d4..e25f34ea0d5 100644 --- a/drivers/mtd/nand/mxs_nand_spl.c +++ b/drivers/mtd/nand/mxs_nand_spl.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2014 Gateworks Corporation + * Copyright 2019 NXP * Author: Tim Harvey * * SPDX-License-Identifier: GPL-2.0+ @@ -7,6 +8,7 @@ #include #include #include +#include static struct mtd_info *mtd; static struct nand_chip nand_chip; @@ -37,6 +39,12 @@ static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, if (command == NAND_CMD_READ0) { chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE); chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); + } else if (command == NAND_CMD_RNDOUT) { + /* No ready / busy check necessary */ + chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, + NAND_NCE | NAND_CLE); + chip->cmd_ctrl(mtd, NAND_CMD_NONE, + NAND_NCE); } /* wait for nand ready */ @@ -49,13 +57,140 @@ static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, } } -static int mxs_flash_ident(struct mtd_info *mtd) +static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) { - register struct nand_chip *chip = mtd_to_nand(mtd); int i; + while (len--) { + crc ^= *p++ << 8; + for (i = 0; i < 8; i++) + crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); + } + + return crc; +} + +/* Parse the Extended Parameter Page. */ +static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, + struct nand_chip *chip, struct nand_onfi_params *p) +{ + struct onfi_ext_param_page *ep; + struct onfi_ext_section *s; + struct onfi_ext_ecc_info *ecc; + uint8_t *cursor; + int ret = -EINVAL; + int len; + int i; + + len = le16_to_cpu(p->ext_param_page_length) * 16; + ep = malloc(len); + if (!ep) { + printf("can't malloc memory 0x%x\n", len); + return -ENOMEM; + } + + /* Send our own NAND_CMD_PARAM. */ + chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); + + /* Use the Change Read Column command to skip the ONFI param pages. */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, + sizeof(*p) * p->num_of_param_pages , -1); + + /* Read out the Extended Parameter Page. */ + chip->read_buf(mtd, (uint8_t *)ep, len); + if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) + != le16_to_cpu(ep->crc))) { + printf("fail in the CRC.\n"); + goto ext_out; + } + + /* + * Check the signature. + * Do not strictly follow the ONFI spec, maybe changed in future. + */ + if (strncmp((char *)ep->sig, "EPPS", 4)) { + printf("The signature is invalid.\n"); + goto ext_out; + } + + /* find the ECC section. */ + cursor = (uint8_t *)(ep + 1); + for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { + s = ep->sections + i; + if (s->type == ONFI_SECTION_TYPE_2) + break; + cursor += s->length * 16; + } + if (i == ONFI_EXT_SECTION_MAX) { + printf("We can not find the ECC section.\n"); + goto ext_out; + } + + /* get the info we want. */ + ecc = (struct onfi_ext_ecc_info *)cursor; + + if (!ecc->codeword_size) { + printf("Invalid codeword size\n"); + goto ext_out; + } + + chip->ecc_strength_ds = ecc->ecc_bits; + chip->ecc_step_ds = 1 << ecc->codeword_size; + ret = 0; + +ext_out: + free(ep); + return ret; +} + +/* Extract the bits of per cell from the 3rd byte of the extended ID */ +static int nand_get_bits_per_cell(u8 cellinfo) +{ + int bits; + + bits = cellinfo & NAND_CI_CELLTYPE_MSK; + bits >>= NAND_CI_CELLTYPE_SHIFT; + return bits + 1; +} + +static inline bool is_full_id_nand(struct nand_flash_dev *type) +{ + return type->id_len; +} + +static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, + struct nand_flash_dev *type, u8 *id_data, int *busw) +{ + if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { + mtd->writesize = type->pagesize; + mtd->erasesize = type->erasesize; + mtd->oobsize = type->oobsize; + + chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->chipsize = (uint64_t)type->chipsize << 20; + chip->options |= type->options; + chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); + chip->ecc_step_ds = NAND_ECC_STEP(type); + chip->onfi_timing_mode_default = + type->onfi_timing_mode_default; + + *busw = type->options & NAND_BUSWIDTH_16; + + if (!mtd->name) + mtd->name = type->name; + + return true; + } + return false; +} + +static int mxs_flash_ident(struct mtd_info *mtd, struct nand_flash_dev *type) +{ + register struct nand_chip *chip = mtd_to_nand(mtd); + int i, val; u8 mfg_id, dev_id; u8 id_data[8]; struct nand_onfi_params *p = &chip->onfi_params; + int busw = 0; /* Reset the chip */ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); @@ -77,6 +212,18 @@ static int mxs_flash_ident(struct mtd_info *mtd) } debug("0x%02x:0x%02x ", mfg_id, dev_id); + if (!type) + type = nand_flash_ids; + + for (; type->name != NULL; type++) { + if (is_full_id_nand(type)) { + if (find_full_id_nand(mtd, chip, type, id_data, &busw)) + goto ident_done; + } else if (dev_id == type->dev_id) { + break; + } + } + /* read ONFI */ chip->onfi_version = 0; chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); @@ -101,10 +248,44 @@ static int mxs_flash_ident(struct mtd_info *mtd) chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; chip->badblockbits = 8; - debug("erasesize=%d (>>%d)\n", mtd->erasesize, chip->phys_erase_shift); - debug("writesize=%d (>>%d)\n", mtd->writesize, chip->page_shift); + /* Check version */ + val = le16_to_cpu(p->revision); + if (val & (1 << 5)) + chip->onfi_version = 23; + else if (val & (1 << 4)) + chip->onfi_version = 22; + else if (val & (1 << 3)) + chip->onfi_version = 21; + else if (val & (1 << 2)) + chip->onfi_version = 20; + else if (val & (1 << 1)) + chip->onfi_version = 10; + + if (!chip->onfi_version) { + printf("unsupported ONFI version: %d\n", val); + return 0; + } + + if (p->ecc_bits != 0xff) { + chip->ecc_strength_ds = p->ecc_bits; + chip->ecc_step_ds = 512; + } else if (chip->onfi_version >= 21 && + (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { + + if (nand_flash_detect_ext_param_page(mtd, chip, p)) + printf("Failed to detect ONFI extended param page\n"); + } else { + printf("Could not retrieve ONFI ECC requirements\n"); + } + +ident_done: + chip->page_shift = ffs(mtd->writesize) - 1; + chip->phys_erase_shift = ffs(mtd->erasesize) - 1; + debug("ecc_strength_ds %u, ecc_step_ds %u\n", chip->ecc_strength_ds, chip->ecc_step_ds); + debug("erasesize=%x (>>%d)\n", mtd->erasesize, chip->phys_erase_shift); + debug("writesize=%x (>>%d)\n", mtd->writesize, chip->page_shift); debug("oobsize=%d\n", mtd->oobsize); - debug("chipsize=%lld\n", chip->chipsize); + debug("chipsize=%llx\n", chip->chipsize); return 0; } @@ -153,7 +334,7 @@ static int mxs_nand_init(void) nand_chip.numchips = 1; /* identify flash device */ - if (mxs_flash_ident(mtd)) { + if (mxs_flash_ident(mtd, NULL)) { printf("Failed to identify\n"); return -1; } @@ -175,23 +356,40 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) unsigned int page; unsigned int nand_page_per_block; unsigned int sz = 0; + uint8_t *page_buf = NULL; + uint32_t page_off; if (mxs_nand_init()) return -ENODEV; + chip = mtd_to_nand(mtd); + + page_buf = malloc(mtd->writesize); + if (!page_buf) + return -ENOMEM; + page = offs >> chip->page_shift; + page_off = offs & (mtd->writesize - 1); nand_page_per_block = mtd->erasesize / mtd->writesize; - debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page); + debug("%s offset:0x%08x len:%d page:%x\n", __func__, offs, size, page); - size = roundup(size, mtd->writesize); - while (sz < size) { - if (mxs_read_page_ecc(mtd, buf, page) < 0) + while (size) { + if (mxs_read_page_ecc(mtd, page_buf, page) < 0) return -1; - sz += mtd->writesize; + + if (size > (mtd->writesize - page_off)) + sz = (mtd->writesize - page_off); + else + sz = size; + + memcpy(buf, page_buf + page_off, sz); + offs += mtd->writesize; page++; - buf += mtd->writesize; + buf += (mtd->writesize - page_off); + page_off = 0; + size -= sz; /* * Check if we have crossed a block boundary, and if so @@ -205,12 +403,16 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) while (is_badblock(mtd, offs, 1)) { page = page + nand_page_per_block; /* Check i we've reached the end of flash. */ - if (page >= mtd->size >> chip->page_shift) + if (page >= mtd->size >> chip->page_shift) { + free(page_buf); return -ENOMEM; + } } } } + free(page_buf); + return 0; } diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 6ba255d676b..9163e21e91a 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -42,6 +42,13 @@ config SPI_FLASH_BAR Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SPI_FLASH_4BYTES_ADDR + bool "SPI flash 4bytes (32) address mode support" + depends on SPI_FLASH && !SPI_FLASH_BAR + help + Enable the SPI flash 4bytes extend address mode support to access the flash + which has size > 16MiB. + config SF_DUAL_FLASH bool "SPI DUAL flash memory support" depends on SPI_FLASH diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index fcda0234121..6e0cfb5539e 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o obj-$(CONFIG_SPL_SPI_SUNXI) += sunxi_spi_spl.o endif diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 839cdbe1b0f..9bdbe166df5 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -33,6 +33,7 @@ enum spi_nor_option_flags { /* CFI Manufacture ID's */ #define SPI_FLASH_CFI_MFR_SPANSION 0x01 #define SPI_FLASH_CFI_MFR_STMICRO 0x20 +#define SPI_FLASH_CFI_MFR_MICRON 0x2C #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 #define SPI_FLASH_CFI_MFR_SST 0xbf #define SPI_FLASH_CFI_MFR_WINBOND 0xef @@ -63,6 +64,14 @@ enum spi_nor_option_flags { #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR +#define CMD_READ_ARRAY_FAST_4B 0x0c +#define CMD_PAGE_PROGRAM_4B 0x12 +#define CMD_ERASE_64K_4B 0xdc +#define CMD_ERASE_4K_4B 0x21 +#define CMD_EN4B 0xB7 +#endif + /* Bank addr access commands */ #ifdef CONFIG_SPI_FLASH_BAR # define CMD_BANKADDR_BRWR 0x17 diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 294d9f9d79c..de35707948b 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -30,6 +30,17 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR +static void spi_flash_addr_4b(u32 addr, u8 *cmd) +{ + /* cmd[0] is actual command */ + cmd[1] = addr >> 24; + cmd[2] = addr >> 16; + cmd[3] = addr >> 8; + cmd[4] = addr >> 0; +} +#endif + static int read_sr(struct spi_flash *flash, u8 *rs) { int ret; @@ -314,8 +325,8 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { - u32 erase_size, erase_addr; - u8 cmd[SPI_FLASH_CMD_LEN]; + u32 erase_size, erase_addr, cmd_len; + u8 cmd[SPI_FLASH_CMD_LEN + 1]; int ret = -1; erase_size = flash->erase_size; @@ -346,11 +357,19 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) return ret; #endif spi_flash_addr(erase_addr, cmd); + cmd_len = SPI_FLASH_CMD_LEN; + +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR + if (flash->size > SPI_FLASH_16MB_BOUN) { + spi_flash_addr_4b(erase_addr, cmd); + cmd_len = SPI_FLASH_CMD_LEN + 1; + } +#endif debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], erase_addr); - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); + ret = spi_flash_write_common(flash, cmd, cmd_len, NULL, 0); if (ret < 0) { debug("SF: erase failed\n"); break; @@ -373,8 +392,8 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, struct spi_slave *spi = flash->spi; unsigned long byte_addr, page_size; u32 write_addr; - size_t chunk_len, actual; - u8 cmd[SPI_FLASH_CMD_LEN]; + size_t chunk_len, actual, cmd_len; + u8 cmd[SPI_FLASH_CMD_LEN + 1]; int ret = -1; page_size = flash->page_size; @@ -408,11 +427,19 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, spi->max_write_size - sizeof(cmd)); spi_flash_addr(write_addr, cmd); + cmd_len = SPI_FLASH_CMD_LEN; + +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR + if (flash->size > SPI_FLASH_16MB_BOUN) { + spi_flash_addr_4b(write_addr, cmd); + cmd_len = SPI_FLASH_CMD_LEN + 1; + } +#endif debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), + ret = spi_flash_write_common(flash, cmd, cmd_len, buf + actual, chunk_len); if (ret < 0) { debug("SF: write failed\n"); @@ -489,6 +516,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, } cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR + if (flash->size > SPI_FLASH_16MB_BOUN) + cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte + 1; +#endif + cmd = calloc(1, cmdsz); if (!cmd) { debug("SF: Failed to allocate cmd\n"); @@ -521,6 +553,12 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, spi_flash_addr(read_addr, cmd); +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR + if (flash->size > SPI_FLASH_16MB_BOUN) { + spi_flash_addr_4b(read_addr, cmd); + read_len = len; /* Not care remain len for current bank */ + } +#endif ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); if (ret < 0) { debug("SF: read failed\n"); @@ -939,6 +977,7 @@ static int set_quad_mode(struct spi_flash *flash, #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: + case SPI_FLASH_CFI_MFR_MICRON: debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info)); return 0; #endif @@ -949,6 +988,13 @@ static int set_quad_mode(struct spi_flash *flash, } } +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR +static int enter_4bytes_addr(struct spi_flash *flash) +{ + return spi_flash_cmd(flash->spi, CMD_EN4B, NULL, 0); +} +#endif + #if CONFIG_IS_ENABLED(OF_CONTROL) int spi_flash_decode_fdt(struct spi_flash *flash) { @@ -1026,6 +1072,7 @@ int spi_flash_scan(struct spi_flash *flash) #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) /* NOR protection support for STmicro/Micron chips and similar */ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO || + JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MICRON || JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) { flash->flash_lock = stm_lock; flash->flash_unlock = stm_unlock; @@ -1086,6 +1133,21 @@ int spi_flash_scan(struct spi_flash *flash) /* Go for default supported write cmd */ flash->write_cmd = CMD_PAGE_PROGRAM; +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR + if (flash->size > SPI_FLASH_16MB_BOUN) { + flash->read_cmd = CMD_READ_ARRAY_FAST_4B; + flash->write_cmd = CMD_PAGE_PROGRAM_4B; + + if (flash->erase_cmd == CMD_ERASE_4K) + flash->erase_cmd = CMD_ERASE_4K_4B; + else + flash->erase_cmd = CMD_ERASE_64K_4B; + + enter_4bytes_addr(flash); + } +#endif + + /* Set the quad enable bit - only for quad commands */ if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || @@ -1147,13 +1209,13 @@ int spi_flash_scan(struct spi_flash *flash) puts("\n"); #endif -#ifndef CONFIG_SPI_FLASH_BAR +#if !defined(CONFIG_SPI_FLASH_BAR) && !defined(CONFIG_SPI_FLASH_4BYTES_ADDR) if (((flash->dual_flash == SF_SINGLE_FLASH) && (flash->size > SPI_FLASH_16MB_BOUN)) || ((flash->dual_flash > SF_SINGLE_FLASH) && (flash->size > SPI_FLASH_16MB_BOUN << 1))) { puts("SF: Warning - Only lower 16MiB accessible,"); - puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); + puts(" Full access #define CONFIG_SPI_FLASH_BAR or #define CONFIG_SPI_FLASH_4BYTES_ADDR\n"); } #endif diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index b789219e4e4..9121332a594 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -63,8 +63,10 @@ const struct spi_flash_info spi_flash_ids[] = { {"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) }, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ + {"gd25q16c", INFO(0xc84015, 0x0, 64 * 1024, 32, SECT_4K) }, {"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, {"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, + {"gd25lq16", INFO(0xc86015, 0x0, 64 * 1024, 32, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ {"is25lq040b", INFO(0x9d4013, 0x0, 64 * 1024, 8, 0) }, @@ -88,6 +90,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"mx25u1635e", INFO(0xc22535, 0x0, 64 * 1024, 32, SECT_4K) }, {"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, {"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) }, + {"mx25r6435f", INFO(0xc22817, 0x0, 64 * 1024, 128, RD_FULL | SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ {"s25fl008a", INFO(0x010213, 0x0, 64 * 1024, 16, 0) }, @@ -137,7 +140,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"n25q1024a", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"mt25qu02g", INFO(0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"mt25ql02g", INFO(0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"mt35xu512g", INFO6(0x2c5b1a, 0x104100, 128 * 1024, 512, E_FSR | SECT_4K) }, + {"mt35xu512g", INFO6(0x2c5b1a, 0x104100, 128 * 1024, 512, E_FSR) }, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ {"sst25vf040b", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index de1947ccc17..c4cbe34798e 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -147,9 +147,20 @@ config ETHOC help This MAC is present in OpenRISC and Xtensa XTFPGA boards. +config FEC_MXC_SHARE_MDIO + bool "Share the MDIO bus for FEC controller" + depends on FEC_MXC + +config FEC_MXC_MDIO_BASE + hex "MDIO base address for the FEC controller" + depends on FEC_MXC_SHARE_MDIO + help + This specifies the MDIO registers base address. It is used when + two FEC controllers share MDIO bus. + config FEC_MXC bool "FEC Ethernet controller" - depends on MX5 || MX6 + depends on MX5 || MX6 || MX7 help This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors. diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index ff7ad91116c..cc23aeacf5c 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -24,6 +24,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -563,8 +564,8 @@ static int fec_init(struct eth_device *dev, bd_t *bd) writel(0x00000000, &fec->eth->gaddr1); writel(0x00000000, &fec->eth->gaddr2); - /* Do not access reserved register */ - if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) { + /* Do not access reserved register for i.MX6UL/6ULL/i.MX8/i.MX8M */ + if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) { /* clear MIB RAM */ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) writel(0, i); @@ -806,7 +807,16 @@ static int fec_recv(struct eth_device *dev) uint16_t bd_status; ulong addr, size, end; int i; + +#ifdef CONFIG_DM_ETH + *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE); + if (*packetp == 0) { + printf("%s: error allocating packetp\n", __func__); + return -ENOMEM; + } +#else ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); +#endif /* Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); @@ -882,8 +892,13 @@ static int fec_recv(struct eth_device *dev) #ifdef CONFIG_FEC_MXC_SWAP_PACKET swap_packet((uint32_t *)addr, frame_length); #endif + +#ifdef CONFIG_DM_ETH + memcpy(*packetp, (char *)addr, frame_length); +#else memcpy(buff, (char *)addr, frame_length); net_process_received_packet(buff, frame_length); +#endif len = frame_length; } else { if (bd_status & FEC_RBD_ERR) @@ -997,18 +1012,9 @@ static void fec_free_descs(struct fec_priv *fec) free(fec->tbd_base); } -#ifdef CONFIG_DM_ETH -struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id) -#else -struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) -#endif +struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) { -#ifdef CONFIG_DM_ETH - struct fec_priv *priv = dev_get_priv(dev); - struct ethernet_regs *eth = priv->eth; -#else - struct ethernet_regs *eth = (struct ethernet_regs *)(ulong)base_addr; -#endif + struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; struct mii_dev *bus; int ret; @@ -1032,6 +1038,10 @@ struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) return bus; } +__weak void init_clk_fec(int index) +{ +} + #ifndef CONFIG_DM_ETH #ifdef CONFIG_PHYLIB int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, @@ -1140,17 +1150,25 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) #endif int ret; -#ifdef CONFIG_MX28 +#ifdef CONFIG_MX6 + if (mx6_enet_fused(addr)) { + printf("Ethernet@0x%x is fused, disable it\n", addr); + return -2; + } +#endif + +#ifdef CONFIG_FEC_MXC_MDIO_BASE /* * The i.MX28 has two ethernet interfaces, but they are not equal. * Only the first one can access the MDIO bus. */ - base_mii = MXS_ENET0_BASE; + base_mii = CONFIG_FEC_MXC_MDIO_BASE; #else base_mii = addr; #endif + init_clk_fec(dev_id); debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); - bus = fec_get_miibus(base_mii, dev_id); + bus = fec_get_miibus((ulong)base_mii, dev_id); if (!bus) return -ENOMEM; #ifdef CONFIG_PHYLIB @@ -1201,10 +1219,19 @@ static int fecmxc_read_rom_hwaddr(struct udevice *dev) return fec_get_hwaddr(priv->dev_id, pdata->enetaddr); } +static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + if (packet) + free(packet); + + return 0; +} + static const struct eth_ops fecmxc_ops = { .start = fecmxc_init, .send = fecmxc_send, .recv = fecmxc_recv, + .free_pkt = fecmxc_free_pkt, .stop = fecmxc_halt, .write_hwaddr = fecmxc_set_hwaddr, .read_rom_hwaddr = fecmxc_read_rom_hwaddr, @@ -1236,10 +1263,17 @@ static int fecmxc_probe(struct udevice *dev) struct eth_pdata *pdata = dev_get_platdata(dev); struct fec_priv *priv = dev_get_priv(dev); struct mii_dev *bus = NULL; - int dev_id = -1; uint32_t start; int ret; +#ifdef CONFIG_MX6 + if (mx6_enet_fused((uint32_t)priv->eth)) { + printf("Ethernet@0x%x is fused, disable it\n", (uint32_t)priv->eth); + return -ENODEV; + } +#endif + init_clk_fec(dev->seq); + ret = fec_alloc_descs(priv); if (ret) return ret; @@ -1257,9 +1291,13 @@ static int fecmxc_probe(struct udevice *dev) } fec_reg_setup(priv); - priv->dev_id = (dev_id == -1) ? 0 : dev_id; - bus = fec_get_miibus(dev, dev_id); + priv->dev_id = dev->seq; +#ifdef CONFIG_FEC_MXC_MDIO_BASE + bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq); +#else + bus = fec_get_miibus((ulong)priv->eth, dev->seq); +#endif if (!bus) { ret = -ENOMEM; goto err_mii; @@ -1274,12 +1312,11 @@ static int fecmxc_probe(struct udevice *dev) return 0; -err_timeout: - free(priv->phydev); err_phy: mdio_unregister(bus); free(bus); err_mii: +err_timeout: fec_free_descs(priv); return ret; } @@ -1325,6 +1362,10 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev) static const struct udevice_id fecmxc_ids[] = { { .compatible = "fsl,imx6q-fec" }, + { .compatible = "fsl,imx6sl-fec" }, + { .compatible = "fsl,imx6sx-fec" }, + { .compatible = "fsl,imx6ul-fec" }, + { .compatible = "fsl,imx7d-fec" }, { } }; diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 8fbab462a43..c23c2877e1d 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o obj-$(CONFIG_PCI_MSC01) += pci_msc01.o obj-$(CONFIG_PCIE_IMX) += pcie_imx.o +obj-$(CONFIG_PCIE_IMX8X) += pcie_imx8x.o pcie_imx8qm.o obj-$(CONFIG_FTPCI100) += pci_ftpci100.o obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index ef66a1d3f4e..b3024b37a70 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -3,6 +3,8 @@ * * Copyright (C) 2013 Marek Vasut * + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * * Based on upstream Linux kernel driver: * pci-imx6.c: Sean Cross * pcie-designware.c: Jingoo Han @@ -93,6 +95,43 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C +#ifdef DEBUG + +#ifdef DEBUG_STRESS_WR /* warm-reset stress tests */ +#define SNVS_LPGRP 0x020cc068 +#endif + +#define DBGF(x...) printf(x) + +static void print_regs(int contain_pcie_reg) +{ + u32 val; + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + val = readl(&iomuxc_regs->gpr[1]); + DBGF("GPR01 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[1], val); + val = readl(&iomuxc_regs->gpr[5]); + DBGF("GPR05 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[5], val); + val = readl(&iomuxc_regs->gpr[8]); + DBGF("GPR08 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[8], val); + val = readl(&iomuxc_regs->gpr[12]); + DBGF("GPR12 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[12], val); + val = readl(&ccm_regs->analog_pll_enet); + DBGF("PLL06 a:0x%08x v:0x%08x\n", (u32)&ccm_regs->analog_pll_enet, val); + val = readl(&ccm_regs->ana_misc1); + DBGF("MISC1 a:0x%08x v:0x%08x\n", (u32)&ccm_regs->ana_misc1, val); + if (contain_pcie_reg) { + val = readl(MX6_DBI_ADDR + 0x728); + DBGF("dbr0 offset 0x728 %08x\n", val); + val = readl(MX6_DBI_ADDR + 0x72c); + DBGF("dbr1 offset 0x72c %08x\n", val); + } +} +#else +#define DBGF(x...) +static void print_regs(int contain_pcie_reg) {} +#endif + /* * PHY access functions */ @@ -384,7 +423,7 @@ static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d, ret = imx_pcie_addr_valid(d); if (ret) { *val = 0xffffffff; - return 0; + return ret; } va_address = get_bus_address(d, where); @@ -447,6 +486,7 @@ static int imx6_pcie_assert_core_reset(bool prepare_for_boot) setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); /* Power up PCIe PHY */ setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); + pcie_power_up(); #else /* * If the bootloader already enabled the link we need some special @@ -489,7 +529,9 @@ static int imx6_pcie_init_phy(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; +#ifndef DEBUG clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); +#endif clrsetbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_DEVICE_TYPE_MASK, @@ -643,6 +685,24 @@ static int imx_pcie_link_up(void) while (!imx6_pcie_link_up()) { udelay(10); count++; + if (count == 1000) { + print_regs(1); + /* link down, try reset ep, and re-try link here */ + DBGF("pcie link is down, reset ep, then retry!\n"); + imx6_pcie_toggle_reset(); + continue; + } +#ifdef DEBUG + else if (count >= 2000) { + print_regs(1); + /* link is down, stop here */ + setenv("bootcmd", "sleep 2;"); + DBGF("pcie link is down, stop here!\n"); + clrbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_APPS_LTSSM_ENABLE); + return -EINVAL; + } +#endif if (count >= 4000) { #ifdef CONFIG_PCI_SCAN_SHOW puts("PCI: pcie phy link never came up\n"); @@ -650,6 +710,8 @@ static int imx_pcie_link_up(void) debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0), readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1)); + clrbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_APPS_LTSSM_ENABLE); return -EINVAL; } } @@ -663,6 +725,10 @@ void imx_pcie_init(void) static struct pci_controller pcc; struct pci_controller *hose = &pcc; int ret; +#ifdef DEBUG_STRESS_WR + u32 dbg_reg_addr = SNVS_LPGRP; + u32 dbg_reg = readl(dbg_reg_addr) + 1; +#endif memset(&pcc, 0, sizeof(pcc)); @@ -697,7 +763,15 @@ void imx_pcie_init(void) if (!ret) { pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); +#ifdef DEBUG_STRESS_WR + dbg_reg += 1<<16; +#endif } +#ifdef DEBUG_STRESS_WR + writel(dbg_reg, dbg_reg_addr); + DBGF("PCIe Successes/Attempts: %d/%d\n", + dbg_reg >> 16, dbg_reg & 0xffff); +#endif } void imx_pcie_remove(void) diff --git a/drivers/pci/pcie_imx8qm.c b/drivers/pci/pcie_imx8qm.c new file mode 100644 index 00000000000..edac842d622 --- /dev/null +++ b/drivers/pci/pcie_imx8qm.c @@ -0,0 +1,297 @@ +/* + * + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include + +void pcie_ctrlx2_rst(void) +{ + /* gpio config */ + /* dir wakeup input clkreq and pereset output */ + writel(0x2d, HSIO_GPIO_BASE_ADDR + 0x4); + writel(0x24, HSIO_GPIO_BASE_ADDR + 0x0); /* do pereset 1 */ + + clrbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_BUTTON_RST_N); + clrbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_PERST_N); + clrbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_POWER_UP_RST_N); + udelay(10); + setbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_BUTTON_RST_N); + setbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_PERST_N); + setbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_POWER_UP_RST_N); +} + +void pcie_ctrlx1_rst(void) +{ + /* gpio config */ + /* dir wakeup input clkreq and pereset output */ + writel(0x2d, HSIO_GPIO_BASE_ADDR + 0x4); + writel(0x24, HSIO_GPIO_BASE_ADDR + 0x0); /* do pereset 1 */ + + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_BUTTON_RST_N); + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_BUTTON_RST_N); + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_PERST_N); + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_PERST_N); + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_POWER_UP_RST_N); + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_POWER_UP_RST_N); +} + +int pcie_ctrla_init_rc(int lane) +{ + u32 val, i = 0; + + setbits_le32(HW_PHYX2_CTRL0_ADDR, HW_PHYX2_CTRL0_APB_RSTN_0 + | HW_PHYX2_CTRL0_APB_RSTN_1); /* APB_RSTN_0/1 */ + + clrbits_le32(HW_PCIEX2_CTRL0_ADDR, HW_PCIEX2_CTRL0_DEVICE_TYPE_MASK); + setbits_le32(HW_PCIEX2_CTRL0_ADDR, HW_PCIEX2_CTRL0_DEVICE_TYPE_RC); + + if (lane == 1) { + /* + * bit 0 rx ena. bit 11 fast_init. + * bit12 PHY_X1_EPCS_SEL 1. + * bit13 phy_ab_select 1. + */ + setbits_le32(HW_MISC_CTRL0_ADDR, HW_MISC_CTRL0_IOB_RXENA + | HW_MISC_CTRL0_PHY_X1_EPCS_SEL + | HW_MISC_CTRL0_PCIE_AB_SELECT); + /* pipe_ln2lk = 1001 */ + clrbits_le32(HW_PHYX2_CTRL0_ADDR, + HW_PHYX2_CTRL0_PIPE_LN2LK_MASK); + setbits_le32(HW_PHYX2_CTRL0_ADDR, HW_PHYX2_CTRL0_PIPE_LN2LK_3 + | HW_PHYX2_CTRL0_PIPE_LN2LK_0); + for (i = 0; i < 100; i++) { + val = readl(HW_PHYX2_STTS0_ADDR); + val &= HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK; + if (val == HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK) + break; + udelay(10); + } + + if (val != HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK) { + printf("TX PLL is not locked.\n"); + return -ENODEV; + } + setbits_le32(GPR_LPCG_PHYX2APB_0_APB, BIT(1)); + /* Set the link_capable to be lane1 */ + clrbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_EN_MASK); + setbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_LANE1); + clrbits_le32(PORT0_GEN2_CTRL, PORT_GEN2_CTRL_NUM_LANES_MASK); + setbits_le32(PORT0_GEN2_CTRL, PORT_GEN2_CTRL_NUM_LANES_1); + } else if (lane == 2) { + /* + * bit 0 rx ena. bit 11 fast_init. + * bit12 PHY_X1_EPCS_SEL 1. + */ + setbits_le32(HW_MISC_CTRL0_ADDR, HW_MISC_CTRL0_IOB_RXENA + | HW_MISC_CTRL0_PHY_X1_EPCS_SEL); + /* pipe_ln2lk = 0011 */ + clrbits_le32(HW_PHYX2_CTRL0_ADDR, + HW_PHYX2_CTRL0_PIPE_LN2LK_MASK); + setbits_le32(HW_PHYX2_CTRL0_ADDR, HW_PHYX2_CTRL0_PIPE_LN2LK_1 + | HW_PHYX2_CTRL0_PIPE_LN2LK_0); + for (i = 0; i < 100; i++) { + val = readl(HW_PHYX2_STTS0_ADDR); + val &= (HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK | HW_PHYX2_STTS0_LANE1_TX_PLL_LOCK); + if (val == (HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK | HW_PHYX2_STTS0_LANE1_TX_PLL_LOCK)) + break; + udelay(10); + } + + if (val != (HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK | HW_PHYX2_STTS0_LANE1_TX_PLL_LOCK)) { + printf("TX PLL is not locked.\n"); + return -ENODEV; + } + setbits_le32(GPR_LPCG_PHYX2APB_0_APB, BIT(1) + BIT(5)); + /* Set the link_capable to be lane2 */ + clrbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_EN_MASK); + setbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_LANE2); + clrbits_le32(PORT0_GEN2_CTRL, PORT_GEN2_CTRL_NUM_LANES_MASK); + setbits_le32(PORT0_GEN2_CTRL, PORT_GEN2_CTRL_NUM_LANES_2); + } else { + printf("%s %d lane %d is invalid.\n", __func__, __LINE__, lane); + } + + /* bit19 PM_REQ_CORE_RST of pciex2_stts0 should be cleared. */ + for (i = 0; i < 100; i++) { + val = readl(HW_PCIEX2_STTS0_ADDR); + if ((val & HW_PCIEX2_STTS0_PM_REQ_CORE_RST) == 0) + break; + udelay(10); + } + + if ((val & HW_PCIEX2_STTS0_PM_REQ_CORE_RST) != 0) + printf("ERROR PM_REQ_CORE_RST is set.\n"); + + /* DBI_RO_WR_EN =1 to write PF0_SPCIE_CAP_OFF_0CH_REG */ + writel(0x1, PORT0_MISC_CONTROL_1); + writel(0x35353535, PF0_SPCIE_CAP_OFF_0CH_REG); /* set preset not golden */ + setbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_FAST_LNK); + setbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_APP_LTSSM_ENABLE); + + do { + udelay(100); + val = readl(PORT0_LINK_DEBUG1); + } while (((val & PORT_LINK_DEBUG1_LINK_UP) == 0) && (i++ < 100)); + + if ((val & PORT_LINK_DEBUG1_LINK_UP) == PORT_LINK_DEBUG1_LINK_UP) + printf("[%s] LNK UP %x\r\n", __func__, val); + else { + printf("[%s] LNK DOWN %x\r\n", __func__, val); + clrbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_APP_LTSSM_ENABLE); + return -ENODEV; + } + + clrbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_FAST_LNK); + + val = readl(PF0_LINK_CONTROL_LINK_STATUS_REG); + printf("[%s] PCIe GEN[%d] Lane[%d] is up.\n", __func__, + (val >> 16) & 0xF, (val >> 20) & 0x3F); + + /* EQ phase 3 finish + * wait_read_check(LINK_CONTROL2_LINK_STATUS2_REG,BIT(17),BIT(17),1000); + */ + /* make sure that pciea is L0 state now */ + for (i = 0; i < 100; i++) { + val = readl(HW_PCIEX2_STTS0_ADDR); + if ((val & 0x3f) == 0x11) + break; + udelay(10); + } + + if ((val & 0x3f) != 0x11) + printf("can't return back to L0 state.\n"); + + writel(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, + PF0_TYPE1_STATUS_COMMAND_REG); + printf("pcie ctrla initialization is finished.\n"); + + return 0; +} + +int pcie_ctrlb_sata_phy_init_rc(void) +{ + u32 val, i = 0; + + setbits_le32(HW_PHYX1_CTRL0_ADDR, HW_PHYX1_CTRL0_APB_RSTN); /* APB_RSTN */ + + clrbits_le32(HW_PCIEX1_CTRL0_ADDR, HW_PCIEX1_CTRL0_DEVICE_TYPE_MASK); + setbits_le32(HW_PCIEX1_CTRL0_ADDR, HW_PCIEX1_CTRL0_DEVICE_TYPE_RC); + + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_BUTTON_RST_N); + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_PERST_N); + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_PERST_N); + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_POWER_UP_RST_N); + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_POWER_UP_RST_N); + + /* + * bit 0 rx ena. bit 11 fast_init. + * bit13 phy_ab_select 1. + */ + setbits_le32(HW_MISC_CTRL0_ADDR, HW_MISC_CTRL0_IOB_RXENA); + clrbits_le32(HW_MISC_CTRL0_ADDR, HW_MISC_CTRL0_PHY_X1_EPCS_SEL); + + /* pipe_ln2lk = 0011 */ + clrbits_le32(HW_PHYX1_CTRL0_ADDR, + HW_PHYX1_CTRL0_PIPE_LN2LK_MASK); + setbits_le32(HW_PHYX1_CTRL0_ADDR, HW_PHYX1_CTRL0_PIPE_LN2LK_1 + | HW_PHYX2_CTRL0_PIPE_LN2LK_0); + for (i = 0; i < 100; i++) { + val = readl(HW_PHYX1_STTS0_ADDR); + val &= HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK; + if (val == HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK) + break; + udelay(10); + } + + if (val != HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK) { + printf("TX PLL is not locked.\n"); + return -ENODEV; + } + + setbits_le32(GPR_LPCG_PHYX1_APB, BIT(1)); + + /* bit19 PM_REQ_CORE_RST of pciex1_stts0 should be cleared. */ + for (i = 0; i < 100; i++) { + val = readl(HW_PCIEX1_STTS0_ADDR); + if ((val & HW_PCIEX1_STTS0_PM_REQ_CORE_RST) == 0) + break; + udelay(10); + } + + if ((val & HW_PCIEX1_STTS0_PM_REQ_CORE_RST) != 0) + printf("ERROR PM_REQ_CORE_RST is set.\n"); + + /* DBI_RO_WR_EN =1 to write PF1_SPCIE_CAP_OFF_0CH_REG */ + writel(0x1, PORT1_MISC_CONTROL_1); + writel(0x35353535, PF1_SPCIE_CAP_OFF_0CH_REG); /* set preset not golden */ + setbits_le32(PORT1_LINK_CTRL, PORT_LINK_CTRL_LNK_FAST_LNK); + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_APP_LTSSM_ENABLE); + + do { + udelay(100); + val = readl(PORT1_LINK_DEBUG1); + } while (((val & PORT_LINK_DEBUG1_LINK_UP) == 0) && (i++ < 100)); + + if ((val & PORT_LINK_DEBUG1_LINK_UP) == PORT_LINK_DEBUG1_LINK_UP) { + printf("[%s] LNK UP %x\r\n", __func__, val); + } else { + printf("[%s] LNK DOWN %x\r\n", __func__, val); + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_APP_LTSSM_ENABLE); + return -ENODEV; + } + clrbits_le32(PORT1_LINK_CTRL, PORT_LINK_CTRL_LNK_FAST_LNK); + + val = readl(PF1_LINK_CONTROL_LINK_STATUS_REG); + printf("[%s] PCIe GEN[%d] Lane[%d] is up.\n", __func__, + (val >> 16) & 0xF, (val >> 20) & 0x3F); + + /* EQ phase 3 finish + * wait_read_check(LINK_CONTROL2_LINK_STATUS2_REG,BIT(17),BIT(17),1000); + */ + /* make sure that pcieb is L0 state now */ + for (i = 0; i < 100; i++) { + val = readl(HW_PCIEX1_STTS0_ADDR); + if ((val & 0x3f) == 0x11) + break; + udelay(10); + } + + if ((val & 0x3f) != 0x11) { + printf("can't return back to L0 state.\n"); + return -ENODEV; + } + + writel(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, + PF1_TYPE1_STATUS_COMMAND_REG); + + return 0; +} + +DECLARE_GLOBAL_DATA_PTR; +void mx8qxp_pcie_init(void) +{ + pcie_ctrlx1_rst(); + if (!pcie_ctrlb_sata_phy_init_rc()) + mx8x_pcie_ctrlb_setup_regions(); +} + +void mx8qm_pcie_init(void) +{ + pcie_ctrlx2_rst(); + if (!pcie_ctrla_init_rc(1)) + mx8x_pcie_ctrla_setup_regions(); + +#ifdef CONFIG_IMX_PCIEB + pcie_ctrlx1_rst(); + if (!pcie_ctrlb_sata_phy_init_rc()) + mx8x_pcie_ctrlb_setup_regions(); +#endif +} diff --git a/drivers/pci/pcie_imx8x.c b/drivers/pci/pcie_imx8x.c new file mode 100644 index 00000000000..01f9a7deac9 --- /dev/null +++ b/drivers/pci/pcie_imx8x.c @@ -0,0 +1,224 @@ +/* + * + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void mx8x_pcie_controller_reset(sc_ipc_t ipc, u32 scr) +{ + sc_err_t err; + int i; + + err = sc_misc_set_control(ipc, scr, SC_C_PCIE_G_RST, 1); + if (err != SC_ERR_NONE) + printf("SC_R_PCIE G_RST failed! (error = %d)\n", err); + for (i = 0; i < 200; i = i + 1) + asm("nop"); + + err = sc_misc_set_control(ipc, scr, SC_C_PCIE_G_RST, 0); + if (err != SC_ERR_NONE) + printf("SC_R_PCIE G_RST failed! (error = %d)\n", err); + + err = sc_misc_set_control(ipc, scr, SC_C_PCIE_PERST, 1); + if (err != SC_ERR_NONE) + printf("SC_R_PCIE PCIE_RST failed! (error = %d)\n", err); + + err = sc_misc_set_control(ipc, scr, SC_C_PCIE_BUTTON_RST, 1); + if (err != SC_ERR_NONE) + printf("SC_R_PCIE BUTTON_RST failed! (error = %d)\n", err); +} + +static void pcie_mapping_region(u32 index, u32 direction, u32 type, + u32 addr, u32 size, u32 target_l, u32 target_h) +{ + /* Select a iATU and configure its direction */ + pcie_writel(index | direction, PCIE0_ATU_VIEWPORT); + setbits_le32(PCIE0_ATU_CR1, type); + + /* Set memory address and size */ + pcie_writel(addr, PCIE0_ATU_LOWER_BASE); + pcie_writel(0, PCIE0_ATU_UPPER_BASE); + pcie_writel((addr + size - 1), PCIE0_ATU_LIMIT); + + pcie_writel(target_l, PCIE0_ATU_LOWER_TARGET); + pcie_writel(target_h, PCIE0_ATU_UPPER_TARGET); + + /* Enable this iATU */ + setbits_le32(PCIE0_ATU_CR2, PCIE_ATU_ENABLE); +} + +static void pcie_ctrlb_mapping_region(u32 index, u32 direction, u32 type, + u32 addr, u32 size, u32 target_l, u32 target_h) +{ + /* Select a iATU and configure its direction */ + pcie_writel(index | direction, PCIE1_ATU_VIEWPORT); + setbits_le32(PCIE1_ATU_CR1, type); + + /* Set memory address and size */ + pcie_writel(addr, PCIE1_ATU_LOWER_BASE); + pcie_writel(0, PCIE1_ATU_UPPER_BASE); + pcie_writel((addr + size - 1), PCIE1_ATU_LIMIT); + + pcie_writel(target_l, PCIE1_ATU_LOWER_TARGET); + pcie_writel(target_h, PCIE1_ATU_UPPER_TARGET); + + /* Enable this iATU */ + setbits_le32(PCIE1_ATU_CR2, PCIE_ATU_ENABLE); +} + +/* CFG Space --> 0x40000000 + * 1st Region --> 0x41000000 + * 2nd Region --> 0x42000000 + * ... + */ +void mx8x_pcie_ctrla_setup_regions(void) +{ + u32 i, cmd; + u32 val, index; + u32 is_32bit; + u32 type, size; + u64 size64; + const u32 region_types[] = { + PCIE_ATU_TYPE_MEM, + PCIE_ATU_TYPE_IO, + }; + + cmd = PCI_COMMAND_MASTER; + + pcie_mapping_region(0, PCIE_ATU_REGION_OUTBOUND, PCIE_ATU_TYPE_CFG0, + PCIEA_CFG_PCI_BASE, PCIE_CFG_MEM_SIZE, 0, 0); + + index = 1; + udelay(1000); + + for (i = 0; i < 6; i++) { + val = pcie_readl(PCIEA_CFG_CPU_BASE + 0x10 + i * 4); + printf("#### [%d] val=%X addr=%X\r\n ", i, val, + PCIEA_CFG_CPU_BASE + 0x10 + i * 4); + if (!val) + continue; + type = region_types[val & 0x1]; + is_32bit = ((val & 0x4) == 0); + pcie_writel(0xFFFFFFFF, PCIEA_CFG_CPU_BASE + 0x10 + i * 4); + size = pcie_readl(PCIEA_CFG_CPU_BASE + 0x10 + i * 4); + size = 0xFFFFFFFF - (size & ~0xF) + 1; + if (is_32bit) { + pcie_mapping_region(index, PCIE_ATU_REGION_OUTBOUND, + type, PCIEA_CFG_PCI_BASE + + index * 0x1000000, size, + index * 0x1000000, 0); + val = (val & 0xF) + index * 0x1000000; + pcie_writel(val, (PCIEA_CFG_CPU_BASE + 0x10 + i * 4)); + } else { + pcie_writel(0xFFFFFFFF, (PCIEA_CFG_CPU_BASE + 0x10 + + i * 4 + 4)); + size64 = pcie_readl(PCIEA_CFG_CPU_BASE + + 0x10 + i * 4 + 4); + size64 = 0xFFFFFFFF - size64; + size64 <<= 32; + size64 |= size; + size64++; + pcie_mapping_region(index, PCIE_ATU_REGION_OUTBOUND, + type, PCIEA_CFG_PCI_BASE + + index * 0x1000000, size64, + index * 0x1000000, 0); + val = (val & 0xF) + index * 0x1000000; + pcie_writel(val, (PCIEA_CFG_CPU_BASE + 0x10 + i * 4)); + pcie_writel(0, (PCIEA_CFG_CPU_BASE + 0x10 + i * 4 + 4)); + i++; + } + + index++; + + if (type == PCIE_ATU_TYPE_MEM) + cmd |= PCI_COMMAND_MEMORY; + else + cmd |= PCI_COMMAND_IO; + } + + pcie_writel(cmd, PCIEA_CFG_CPU_BASE + 4); +} + +/* CFG Space --> 0x80000000 + * 1st Region --> 0x81000000 + * 2nd Region --> 0x82000000 + * ... + */ +void mx8x_pcie_ctrlb_setup_regions(void) +{ + u32 i, cmd; + u32 val, index; + u32 is_32bit; + u32 type, size; + u64 size64; + const u32 region_types[] = { + PCIE_ATU_TYPE_MEM, + PCIE_ATU_TYPE_IO, + }; + + cmd = PCI_COMMAND_MASTER; + + pcie_ctrlb_mapping_region(0, PCIE_ATU_REGION_OUTBOUND, PCIE_ATU_TYPE_CFG0, + PCIEB_CFG_PCI_BASE, PCIE_CFG_MEM_SIZE, 0, 0); + + index = 1; + udelay(1000); + + for (i = 0; i < 6; i++) { + val = pcie_readl(PCIEB_CFG_CPU_BASE + 0x10 + i * 4); + printf("#### [%d] val=%X addr=%X\r\n ", i, val, + PCIEB_CFG_CPU_BASE + 0x10 + i * 4); + if (!val) + continue; + type = region_types[val & 0x1]; + is_32bit = ((val & 0x4) == 0); + pcie_writel(0xFFFFFFFF, PCIEB_CFG_CPU_BASE + 0x10 + i * 4); + size = pcie_readl(PCIEB_CFG_CPU_BASE + 0x10 + i * 4); + size = 0xFFFFFFFF - (size & ~0xF) + 1; + if (is_32bit) { + pcie_ctrlb_mapping_region(index, PCIE_ATU_REGION_OUTBOUND, + type, PCIEB_CFG_PCI_BASE + + index * 0x1000000, size, + index * 0x1000000, 0); + val = (val & 0xF) + index * 0x1000000; + pcie_writel(val, (PCIEB_CFG_CPU_BASE + 0x10 + i * 4)); + } else { + pcie_writel(0xFFFFFFFF, (PCIEB_CFG_CPU_BASE + 0x10 + + i * 4 + 4)); + size64 = pcie_readl(PCIEB_CFG_CPU_BASE + + 0x10 + i * 4 + 4); + size64 = 0xFFFFFFFF - size64; + size64 <<= 32; + size64 |= size; + size64++; + pcie_ctrlb_mapping_region(index, PCIE_ATU_REGION_OUTBOUND, + type, PCIEB_CFG_PCI_BASE + + index * 0x1000000, size64, + index * 0x1000000, 0); + val = (val & 0xF) + index * 0x1000000; + pcie_writel(val, (PCIEB_CFG_CPU_BASE + 0x10 + i * 4)); + pcie_writel(0, (PCIEB_CFG_CPU_BASE + 0x10 + i * 4 + 4)); + i++; + } + + index++; + + if (type == PCIE_ATU_TYPE_MEM) + cmd |= PCI_COMMAND_MEMORY; + else + cmd |= PCI_COMMAND_IO; + } + + pcie_writel(cmd, PCIEB_CFG_CPU_BASE + 4); +} + diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index b668359a0bf..d85fb29a314 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -1,6 +1,9 @@ config PINCTRL_IMX bool +config PINCTRL_IMX_SCU + bool + config PINCTRL_IMX5 bool "IMX5 pinctrl driver" depends on ARCH_MX5 && PINCTRL_FULL @@ -56,3 +59,32 @@ config PINCTRL_IMX7ULP is different from the linux one, this is a simple implementation, only parses the 'fsl,pins' property and configure related registers. + +config PINCTRL_IMX8M + bool "IMX8M pinctrl driver" + depends on ARCH_IMX8M && PINCTRL_FULL + select DEVRES + select PINCTRL_IMX + help + Say Y here to enable the imx8m pinctrl driver + + This provides a simple pinctrl driver for i.MX8M SoC familiy. + This feature depends on device tree configuration. This driver + is different from the linux one, this is a simple implementation, + only parses the 'fsl,pins' property and configure related + registers. + +config PINCTRL_IMX8 + bool "IMX8 pinctrl driver" + depends on ARCH_IMX8 && PINCTRL_FULL + select DEVRES + select PINCTRL_IMX + select PINCTRL_IMX_SCU + help + Say Y here to enable the imx8 pinctrl driver + + This provides a simple pinctrl driver for i.MX8 SoC familiy. + This feature depends on device tree configuration. This driver + is different from the linux one, this is a simple implementation, + only parses the 'fsl,pins' property and configure related + registers. diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index c7639483769..f8c232c9e0d 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -3,3 +3,6 @@ obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o +obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o +obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o +obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 32cbac963f7..c09b0d6f094 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Peng Fan + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -23,13 +24,16 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) const struct fdt_property *prop; u32 *pin_data; int npins, size, pin_size; - int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val; + int mux_reg, conf_reg, input_reg; + u32 input_val, mux_mode, config_val; u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0; int i, j = 0; dev_dbg(dev, "%s: %s\n", __func__, config->name); - if (info->flags & SHARE_MUX_CONF_REG) + if (info->flags & IMX8_USE_SCU) + pin_size = SHARE_IMX8_PIN_SIZE; + else if (info->flags & SHARE_MUX_CONF_REG) pin_size = SHARE_FSL_PIN_SIZE; else pin_size = FSL_PIN_SIZE; @@ -59,112 +63,116 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) npins = size / pin_size; - /* - * Refer to linux documentation for details: - * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt - */ - for (i = 0; i < npins; i++) { - mux_reg = pin_data[j++]; - - if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) - mux_reg = -1; - - if (info->flags & SHARE_MUX_CONF_REG) { - conf_reg = mux_reg; - } else { - conf_reg = pin_data[j++]; - if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg) - conf_reg = -1; - } + if (info->flags & IMX8_USE_SCU) { + imx_pinctrl_scu_process_pins(info, pin_data, npins); + } else { + /* + * Refer to linux documentation for details: + * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt + */ + for (i = 0; i < npins; i++) { + mux_reg = pin_data[j++]; - if ((mux_reg == -1) || (conf_reg == -1)) { - dev_err(dev, "Error mux_reg or conf_reg\n"); - devm_kfree(dev, pin_data); - return -EINVAL; - } + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) + mux_reg = -1; - input_reg = pin_data[j++]; - mux_mode = pin_data[j++]; - input_val = pin_data[j++]; - config_val = pin_data[j++]; + if (info->flags & SHARE_MUX_CONF_REG) { + conf_reg = mux_reg; + } else { + conf_reg = pin_data[j++]; + if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg) + conf_reg = -1; + } - dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, " - "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n", - mux_reg, conf_reg, input_reg, mux_mode, input_val, - config_val); + if ((mux_reg == -1) || (conf_reg == -1)) { + dev_err(dev, "Error mux_reg or conf_reg\n"); + devm_kfree(dev, pin_data); + return -EINVAL; + } - if (config_val & IMX_PAD_SION) - mux_mode |= IOMUXC_CONFIG_SION; + input_reg = pin_data[j++]; + mux_mode = pin_data[j++]; + input_val = pin_data[j++]; + config_val = pin_data[j++]; - config_val &= ~IMX_PAD_SION; + dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, " + "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n", + mux_reg, conf_reg, input_reg, mux_mode, input_val, + config_val); - /* Set Mux */ - if (info->flags & SHARE_MUX_CONF_REG) { - clrsetbits_le32(info->base + mux_reg, info->mux_mask, - mux_mode << mux_shift); - } else { - writel(mux_mode, info->base + mux_reg); - } + if (config_val & IMX_PAD_SION) + mux_mode |= IOMUXC_CONFIG_SION; - dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg, - mux_mode); + config_val &= ~IMX_PAD_SION; - /* - * Set select input - * - * If the select input value begins with 0xff, it's a quirky - * select input and the value should be interpreted as below. - * 31 23 15 7 0 - * | 0xff | shift | width | select | - * It's used to work around the problem that the select - * input for some pin is not implemented in the select - * input register but in some general purpose register. - * We encode the select input value, width and shift of - * the bit field into input_val cell of pin function ID - * in device tree, and then decode them here for setting - * up the select input bits in general purpose register. - */ + /* Set Mux */ + if (info->flags & SHARE_MUX_CONF_REG) { + clrsetbits_le32(info->base + mux_reg, info->mux_mask, + mux_mode << mux_shift); + } else { + writel(mux_mode, info->base + mux_reg); + } + + dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg, + mux_mode); - if (input_val >> 24 == 0xff) { - u32 val = input_val; - u8 select = val & 0xff; - u8 width = (val >> 8) & 0xff; - u8 shift = (val >> 16) & 0xff; - u32 mask = ((1 << width) - 1) << shift; - /* - * The input_reg[i] here is actually some IOMUXC general - * purpose register, not regular select input register. - */ - val = readl(info->base + input_reg); - val &= ~mask; - val |= select << shift; - writel(val, info->base + input_reg); - } else if (input_reg) { /* - * Regular select input register can never be at offset - * 0, and we only print register value for regular case. + * Set select input + * + * If the select input value begins with 0xff, it's a quirky + * select input and the value should be interpreted as below. + * 31 23 15 7 0 + * | 0xff | shift | width | select | + * It's used to work around the problem that the select + * input for some pin is not implemented in the select + * input register but in some general purpose register. + * We encode the select input value, width and shift of + * the bit field into input_val cell of pin function ID + * in device tree, and then decode them here for setting + * up the select input bits in general purpose register. */ - if (info->input_sel_base) - writel(input_val, info->input_sel_base + - input_reg); - else - writel(input_val, info->base + input_reg); - - dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n", - input_reg, input_val); - } - /* Set config */ - if (!(config_val & IMX_NO_PAD_CTL)) { - if (info->flags & SHARE_MUX_CONF_REG) { - clrsetbits_le32(info->base + conf_reg, - ~info->mux_mask, config_val); - } else { - writel(config_val, info->base + conf_reg); + if (input_val >> 24 == 0xff) { + u32 val = input_val; + u8 select = val & 0xff; + u8 width = (val >> 8) & 0xff; + u8 shift = (val >> 16) & 0xff; + u32 mask = ((1 << width) - 1) << shift; + /* + * The input_reg[i] here is actually some IOMUXC general + * purpose register, not regular select input register. + */ + val = readl(info->base + input_reg); + val &= ~mask; + val |= select << shift; + writel(val, info->base + input_reg); + } else if (input_reg) { + /* + * Regular select input register can never be at offset + * 0, and we only print register value for regular case. + */ + if (info->input_sel_base) + writel(input_val, info->input_sel_base + + input_reg); + else + writel(input_val, info->base + input_reg); + + dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n", + input_reg, input_val); } - dev_dbg(dev, "write config: offset 0x%x val 0x%x\n", - conf_reg, config_val); + /* Set config */ + if (!(config_val & IMX_NO_PAD_CTL)) { + if (info->flags & SHARE_MUX_CONF_REG) { + clrsetbits_le32(info->base + conf_reg, + (~info->mux_mask), config_val); + } else { + writel(config_val, info->base + conf_reg); + } + + dev_dbg(dev, "write config: offset 0x%x val 0x%x\n", + conf_reg, config_val); + } } } @@ -194,6 +202,9 @@ int imx_pinctrl_probe(struct udevice *dev, priv->dev = dev; priv->info = info; + if (info->flags & IMX8_USE_SCU) + return 0; + addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg", &size); @@ -239,6 +250,9 @@ int imx_pinctrl_remove(struct udevice *dev) struct imx_pinctrl_priv *priv = dev_get_priv(dev); struct imx_pinctrl_soc_info *info = priv->info; + if (info->flags & IMX8_USE_SCU) + return 0; + if (info->input_sel_base) unmap_sysmem(info->input_sel_base); if (info->base) diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h index a26ba854c13..22b7a1d823a 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.h +++ b/drivers/pinctrl/nxp/pinctrl-imx.h @@ -41,13 +41,27 @@ extern const struct pinctrl_ops imx_pinctrl_ops; #define FSL_PIN_SIZE 24 #define SHARE_FSL_PIN_SIZE 20 +/* Each pin on imx8qm/qxp consists of 2 u32 PIN_FUNC_ID and 1 u32 CONFIG */ +#define SHARE_IMX8_PIN_SIZE 12 + #define SHARE_MUX_CONF_REG 0x1 #define ZERO_OFFSET_VALID 0x2 #define CONFIG_IBE_OBE 0x4 +#define IMX8_USE_SCU 0x8 #define IOMUXC_CONFIG_SION (0x1 << 4) int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info); int imx_pinctrl_remove(struct udevice *dev); + +#ifdef CONFIG_PINCTRL_IMX_SCU +int imx_pinctrl_scu_process_pins(struct imx_pinctrl_soc_info *info, u32 *pin_data, int npins); +#else +static inline int imx_pinctrl_scu_process_pins(struct imx_pinctrl_soc_info *info, u32 *pin_data, int npins) +{ + return 0; +} +#endif + #endif /* __DRIVERS_PINCTRL_IMX_H */ diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c new file mode 100644 index 00000000000..3afd826faca --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8.c @@ -0,0 +1,43 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include "pinctrl-imx.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct imx_pinctrl_soc_info imx8_pinctrl_soc_info = { + .flags = IMX8_USE_SCU, +}; + +static int imx8_pinctrl_probe(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + + info->base = (void *)gd->arch.ipc_channel_handle; + return imx_pinctrl_probe(dev, info); +} + +static const struct udevice_id imx8_pinctrl_match[] = { + { .compatible = "fsl,imx8qm-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info }, + { .compatible = "fsl,imx8qxp-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx8_pinctrl) = { + .name = "imx8_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(imx8_pinctrl_match), + .probe = imx8_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), + .ops = &imx_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c new file mode 100644 index 00000000000..8217342014f --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c @@ -0,0 +1,38 @@ + +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-imx.h" + +static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info; + +static int imx8mq_pinctrl_probe(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + + return imx_pinctrl_probe(dev, info); +} + +static const struct udevice_id imx8m_pinctrl_match[] = { + { .compatible = "fsl,imx8mq-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, + { .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx8mq_pinctrl) = { + .name = "imx8mq-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(imx8m_pinctrl_match), + .probe = imx8mq_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), + .ops = &imx_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c b/drivers/pinctrl/nxp/pinctrl-scu.c new file mode 100644 index 00000000000..9df486be569 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-scu.c @@ -0,0 +1,76 @@ +/* + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "pinctrl-imx.h" + +#define PADRING_IFMUX_EN_SHIFT 31 +#define PADRING_IFMUX_EN_MASK (1 << 31) +#define PADRING_GP_EN_SHIFT 30 +#define PADRING_GP_EN_MASK (1 << 30) +#define PADRING_IFMUX_SHIFT 27 +#define PADRING_IFMUX_MASK (0x7 << 27) + + +static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info *info, + unsigned int pin_id, unsigned int mux, unsigned int val) +{ + sc_err_t err = SC_ERR_NONE; + sc_ipc_t ipcHndl = (sc_ipc_t)info->base; + + /* + * Mux should be done in pmx set, but we do not have a good api + * to handle that in scfw, so config it in pad conf func + */ + + if (ipcHndl == 0) { + printf("IPC handle not initialized!\n"); + return -EIO; + } + + if (!sc_rm_is_pad_owned(ipcHndl, pin_id)) { + debug("Pad[%u] is not owned by curr partition\n", pin_id); + return -EPERM; + } + + val |= PADRING_IFMUX_EN_MASK; + val |= PADRING_GP_EN_MASK; + val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK; + + err = sc_pad_set(ipcHndl, pin_id, val); + + if (err != SC_ERR_NONE) + return -EIO; + + return 0; +} + + +int imx_pinctrl_scu_process_pins(struct imx_pinctrl_soc_info *info, u32 *pin_data, int npins) +{ + int pin_id, mux, config_val; + int i, j = 0; + int ret; + + /* + * Refer to linux documentation for details: + * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt + */ + for (i = 0; i < npins; i++) { + pin_id = pin_data[j++]; + mux = pin_data[j++]; + config_val = pin_data[j++]; + + ret = imx_pinconf_scu_set(info, pin_id, mux, config_val); + if (ret && ret != -EPERM) + printf("Set pin %d, mux %d, val %d, error\n", pin_id, mux, config_val); + } + + return 0; +} diff --git a/drivers/power/axp152.c b/drivers/power/axp152.c index c4b3fe58a66..a27dee4327a 100644 --- a/drivers/power/axp152.c +++ b/drivers/power/axp152.c @@ -6,8 +6,26 @@ */ #include #include -#include +#include #include +#include + +#define AXP152_I2C_ADDR 0x32 + +static int pmic_bus_init(void) +{ + return 0; +} + +static int pmic_bus_read(u8 reg, u8 *data) +{ + return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); +} + +static int pmic_bus_write(u8 reg, u8 data) +{ + return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1); +} static u8 axp152_mvolt_to_target(int mvolt, int min, int max, int div) { @@ -19,6 +37,14 @@ static u8 axp152_mvolt_to_target(int mvolt, int min, int max, int div) return (mvolt - min) / div; } +int axp_set_dcdc1(enum axp152_dcdc1_voltages volt) +{ + if (volt < AXP152_DCDC1_1V7 || volt > AXP152_DCDC1_3V5) + return -EINVAL; + + return pmic_bus_write(AXP152_DCDC1_VOLTAGE, volt); +} + int axp_set_dcdc2(unsigned int mvolt) { int rc; @@ -54,17 +80,79 @@ int axp_set_dcdc4(unsigned int mvolt) return pmic_bus_write(AXP152_DCDC4_VOLTAGE, target); } -int axp_set_aldo2(unsigned int mvolt) +int axp_set_ldo0(enum axp152_ldo0_volts volt, enum axp152_ldo0_curr_limit curr_limit) +{ + u8 target = curr_limit | (volt << 4) | (1 << 7); + + return pmic_bus_write(AXP152_LDO0_VOLTAGE, target); +} + +int axp_disable_ldo0(void) +{ + int ret; + u8 target; + + ret = pmic_bus_read(AXP152_LDO0_VOLTAGE, &target); + if (ret) + return ret; + + target &= ~(1 << 7); + + return pmic_bus_write(AXP152_LDO0_VOLTAGE, target); +} + +int axp_set_ldo1(unsigned int mvolt) +{ + u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 100); + + return pmic_bus_write(AXP152_LDO1_VOLTAGE, target); +} + + +int axp_set_ldo2(unsigned int mvolt) { u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 100); return pmic_bus_write(AXP152_LDO2_VOLTAGE, target); } +int axp_set_aldo1(enum axp152_aldo_voltages volt) +{ + u8 val; + int ret; + + ret = pmic_bus_read(AXP152_ALDO1_ALDO2_VOLTAGE, &val); + if (ret) + return ret; + + val |= (volt << 4); + return pmic_bus_write(AXP152_ALDO1_ALDO2_VOLTAGE, val); +} + +int axp_set_aldo2(enum axp152_aldo_voltages volt) +{ + u8 val; + int ret; + + ret = pmic_bus_read(AXP152_ALDO1_ALDO2_VOLTAGE, &val); + if (ret) + return ret; + + val |= volt; + return pmic_bus_write(AXP152_ALDO1_ALDO2_VOLTAGE, val); +} + +int axp_set_power_output(int val) +{ + return pmic_bus_write(AXP152_POWER_CONTROL, val); +} + int axp_init(void) { u8 ver; int rc; + int ret; + u8 reg; rc = pmic_bus_init(); if (rc) @@ -77,7 +165,24 @@ int axp_init(void) if (ver != 0x05) return -EINVAL; - return 0; + /* Set the power off sequence to `reverse of power on sequence` */ + ret = pmic_bus_read(AXP152_SHUTDOWN, ®); + if (ret) + return ret; + reg |= AXP152_POWEROFF_SEQ; + ret = pmic_bus_write(AXP152_SHUTDOWN, reg); + if (ret) + return ret; + + + /* Enable the power recovery */ + ret = pmic_bus_read(AXP152_POWER_RECOVERY, ®); + if (ret) + return ret; + reg |= AXP152_POWER_RECOVERY_EN; + ret = pmic_bus_write(AXP152_POWER_RECOVERY, reg); + return ret; + } int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 7cfa7614987..2a72642a26e 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -31,4 +31,10 @@ config TEGRA186_POWER_DOMAIN Enable support for manipulating Tegra's on-SoC power domains via IPC requests to the BPMP (Boot and Power Management Processor). +config IMX8_POWER_DOMAIN + bool "Enable i.MX8 power domain driver" + depends on ARCH_IMX8 + help + Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC + requests to the SCU. endmenu diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index c7d76444020..c6ad7ff4470 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o +obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o diff --git a/drivers/power/domain/imx8-power-domain.c b/drivers/power/domain/imx8-power-domain.c new file mode 100644 index 00000000000..5f3769d7664 --- /dev/null +++ b/drivers/power/domain/imx8-power-domain.c @@ -0,0 +1,304 @@ +/* + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct imx8_power_domain_priv { + bool state_on; +}; + +static int imx8_power_domain_request(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return 0; +} + +static int imx8_power_domain_free(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return 0; +} + +static int imx8_power_domain_on(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx8_power_domain_platdata *pdata; + struct imx8_power_domain_priv *ppriv; + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + sc_err_t ret; + + struct power_domain parent_domain; + struct udevice *parent = dev_get_parent(dev); + + /* Need to power on parent node first */ + if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) { + parent_domain.dev = parent; + imx8_power_domain_on(&parent_domain); + } + + pdata = (struct imx8_power_domain_platdata *)dev_get_platdata(dev); + ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev); + + debug("%s(power_domain=%s) resource_id %d\n", __func__, dev->name, pdata->resource_id); + + /* Already powered on */ + if (ppriv->state_on) + return 0; + + if (pdata->resource_id != SC_R_NONE) { + if (!sc_rm_is_resource_owned(ipcHndl, pdata->resource_id)) + printf("%s [%d] not owned by curr partition\n", dev->name, pdata->resource_id); + + ret = sc_pm_set_resource_power_mode(ipcHndl, pdata->resource_id, SC_PM_PW_MODE_ON); + if (ret) { + printf("Error: %s Power up failed! (error = %d)\n", dev->name, ret); + return -EIO; + } + } + + ppriv->state_on = true; + debug("%s is powered on\n", dev->name); + + return 0; +} + +static int imx8_power_domain_off_node(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct udevice *child; + struct imx8_power_domain_priv *ppriv; + struct imx8_power_domain_priv *child_ppriv; + struct imx8_power_domain_platdata *pdata; + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + sc_err_t ret; + + ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev); + pdata = (struct imx8_power_domain_platdata *)dev_get_platdata(dev); + + debug("%s, %s, state_on %d\n", __func__, dev->name, ppriv->state_on); + + /* Already powered off */ + if (!ppriv->state_on) + return 0; + + /* Check if all subnodes are off */ + for (device_find_first_child(dev, &child); + child; + device_find_next_child(&child)) { + + if (device_active(child)) { + child_ppriv = (struct imx8_power_domain_priv *)dev_get_priv(child); + if (child_ppriv->state_on) + return -EPERM; + } + } + + if (pdata->resource_id != SC_R_NONE) { + ret = sc_pm_set_resource_power_mode(ipcHndl, pdata->resource_id, SC_PM_PW_MODE_OFF); + if (ret) { + if (!sc_rm_is_resource_owned(ipcHndl, pdata->resource_id)) { + printf("%s not owned by curr partition %d\n", dev->name, pdata->resource_id); + return 0; + } + printf("Error: %s Power off failed! (error = %d)\n", dev->name, ret); + return -EIO; + } + } + + ppriv->state_on = false; + debug("%s is powered off\n", dev->name); + + return 0; +} + +static int imx8_power_domain_off_parentnodes(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct udevice *parent = dev_get_parent(dev); + struct udevice *child; + struct imx8_power_domain_priv *ppriv; + struct imx8_power_domain_priv *child_ppriv; + struct imx8_power_domain_platdata *pdata; + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + sc_err_t ret; + struct power_domain parent_pd; + + if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) { + pdata = (struct imx8_power_domain_platdata *)dev_get_platdata(parent); + ppriv = (struct imx8_power_domain_priv *)dev_get_priv(parent); + + debug("%s, %s, state_on %d\n", __func__, parent->name, ppriv->state_on); + + /* Already powered off */ + if (!ppriv->state_on) + return 0; + + /* Check if all sibling nodes are off. If yes, power off parent */ + for (device_find_first_child(parent, &child); + child; + device_find_next_child(&child)) { + + if (device_active(child)) { + child_ppriv = (struct imx8_power_domain_priv *)dev_get_priv(child); + if (child_ppriv->state_on) { /* Find a power on sibling */ + debug("sibling %s, state_on %d\n", child->name, child_ppriv->state_on); + return 0; + } + } + + } + + /* power off parent */ + if (pdata->resource_id != SC_R_NONE) { + ret = sc_pm_set_resource_power_mode(ipcHndl, pdata->resource_id, SC_PM_PW_MODE_OFF); + if (ret) { + printf("Error: %s Power off failed! (error = %d)\n", parent->name, ret); + return -EIO; + } + } + + ppriv->state_on = false; + debug("%s is powered off\n", parent->name); + + parent_pd.dev = parent; + imx8_power_domain_off_parentnodes(&parent_pd); + } + + return 0; + +} + +static int imx8_power_domain_off(struct power_domain *power_domain) +{ + int ret; + debug("%s(power_domain=%p)\n", __func__, power_domain); + + /* Turn off the node */ + ret = imx8_power_domain_off_node(power_domain); + if (ret) { + debug("Can't power off the node of dev %s, ret = %d\n", + power_domain->dev->name, ret); + return ret; + } + + /* Turn off parent nodes, if sibling nodes are all off */ + ret = imx8_power_domain_off_parentnodes(power_domain); + if (ret) { + printf("Error: Failed to power off parent nodes of dev %s, ret = %d\n", + power_domain->dev->name, ret); + return ret; + } + + return 0; +} + +static int imx8_power_domain_of_xlate(struct power_domain *power_domain, + struct ofnode_phandle_args *args) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + /* Do nothing to the xlate, since we don't have args used */ + + return 0; +} + +static int imx8_power_domain_bind(struct udevice *dev) +{ + int offset; + const char *name; + int ret = 0; + + debug("%s(dev=%p)\n", __func__, dev); + + offset = dev_of_offset(dev); + for (offset = fdt_first_subnode(gd->fdt_blob, offset); + offset > 0; + offset = fdt_next_subnode(gd->fdt_blob, offset)) { + + /* Bind the subnode to this driver */ + name = fdt_get_name(gd->fdt_blob, offset, NULL); + + ret = device_bind_with_driver_data(dev, dev->driver, name, + dev->driver_data, offset_to_ofnode(offset), NULL); + + if (ret == -ENODEV) + printf("Driver '%s' refuses to bind\n", dev->driver->name); + + if (ret) + printf("Error binding driver '%s': %d\n", dev->driver->name, + ret); + } + + return 0; +} + +static int imx8_power_domain_probe(struct udevice *dev) +{ + struct imx8_power_domain_priv *ppriv; + + debug("%s(dev=%s)\n", __func__, dev->name); + + ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev); + + /* Set default to power off */ + if (ppriv) + ppriv->state_on = false; + + return 0; +} + +static int imx8_power_domain_ofdata_to_platdata(struct udevice *dev) +{ + int reg; + struct imx8_power_domain_platdata *pdata = dev_get_platdata(dev); + + reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1); + if (reg == -1) { + debug("%s: Invalid resource id %d\n", __func__, reg); + return -EINVAL; + } + pdata->resource_id = (sc_rsrc_t)reg; + + debug("%s resource_id %d\n", __func__, pdata->resource_id); + + return 0; +} + +static const struct udevice_id imx8_power_domain_ids[] = { + { .compatible = "nxp,imx8-pd" }, + { } +}; + +struct power_domain_ops imx8_power_domain_ops = { + .request = imx8_power_domain_request, + .free = imx8_power_domain_free, + .on = imx8_power_domain_on, + .off = imx8_power_domain_off, + .of_xlate = imx8_power_domain_of_xlate, +}; + +U_BOOT_DRIVER(imx8_power_domain) = { + .name = "imx8_power_domain", + .id = UCLASS_POWER_DOMAIN, + .of_match = imx8_power_domain_ids, + .bind = imx8_power_domain_bind, + .probe = imx8_power_domain_probe, + .ofdata_to_platdata = imx8_power_domain_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct imx8_power_domain_platdata), + .priv_auto_alloc_size = sizeof(struct imx8_power_domain_priv), + .ops = &imx8_power_domain_ops, +}; diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index 1847a492a37..ddb365742d9 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -3,11 +3,12 @@ * * SPDX-License-Identifier: GPL-2.0 */ - #include #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -31,6 +32,46 @@ static int power_domain_of_xlate_default(struct power_domain *power_domain, return 0; } +int power_domain_lookup_name(const char *name, struct power_domain *power_domain) +{ + struct udevice *dev; + struct power_domain_ops *ops; + int ret; + + debug("%s(power_domain=%p name=%s)\n", __func__, power_domain, name); + + ret = uclass_find_device_by_name(UCLASS_POWER_DOMAIN, name, &dev); + if (!ret) { + /* Probe the dev */ + device_probe(dev); + ops = power_domain_dev_ops(dev); + + power_domain->dev = dev; + if (ops->of_xlate) + ret = ops->of_xlate(power_domain, NULL); + else + ret = power_domain_of_xlate_default(power_domain, NULL); + if (ret) { + debug("of_xlate() failed: %d\n", ret); + return ret; + } + + ret = ops->request(power_domain); + if (ret) { + debug("ops->request() failed: %d\n", ret); + return ret; + } + + debug("%s ok: %s\n", __func__, dev->name); + + return 0; + } + + printf("%s fail: %s, ret = %d\n", __func__, name, ret); + return -EINVAL; +} + + int power_domain_get(struct udevice *dev, struct power_domain *power_domain) { struct ofnode_phandle_args args; diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 5d49c93f32a..4cf72173182 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -48,6 +48,13 @@ config PMIC_AS3722 interface and is designs to cover most of the power managementment required for a tablets or laptop. +config DM_PMIC_BD71837 + bool "Enable Driver Model for PMIC BD71837" + depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC BD71837. The driver implements read/write operations. + config DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index fc19fdc701c..2a885b0af2a 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -5,10 +5,11 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_DM_PMIC) += pmic-uclass.o +obj-$(CONFIG_$(SPL_)DM_PMIC) += pmic-uclass.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o +obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_PMIC_ACT8846) += act8846.o @@ -30,6 +31,7 @@ obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o +obj-$(CONFIG_POWER_BD71837) += pmic_bd71837.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c new file mode 100644 index 00000000000..936f47b8407 --- /dev/null +++ b/drivers/power/pmic/bd71837.c @@ -0,0 +1,90 @@ +/* + * Copyright 2018 NXP * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct pmic_child_info pmic_children_info[] = { + /* buck */ + { .prefix = "b", .driver = BD71837_REGULATOR_DRIVER}, + /* ldo */ + { .prefix = "l", .driver = BD71837_REGULATOR_DRIVER}, + { }, +}; + +static int bd71837_reg_count(struct udevice *dev) +{ + return BD71837_REG_NUM; +} + +static int bd71837_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + if (dm_i2c_write(dev, reg, buff, len)) { + pr_err("write error to device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int bd71837_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + if (dm_i2c_read(dev, reg, buff, len)) { + pr_err("read error from device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int bd71837_bind(struct udevice *dev) +{ + int children; + ofnode regulators_node; + + regulators_node = dev_read_subnode(dev, "regulators"); + if (!ofnode_valid(regulators_node)) { + debug("%s: %s regulators subnode not found!", __func__, + dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + + /* Always return success for this device */ + return 0; +} + +static struct dm_pmic_ops bd71837_ops = { + .reg_count = bd71837_reg_count, + .read = bd71837_read, + .write = bd71837_write, +}; + +static const struct udevice_id bd71837_ids[] = { + { .compatible = "rohm,bd71837", .data = 0x4b, }, + { } +}; + +U_BOOT_DRIVER(pmic_bd71837) = { + .name = "bd71837 pmic", + .id = UCLASS_PMIC, + .of_match = bd71837_ids, + .bind = bd71837_bind, + .ops = &bd71837_ops, +}; diff --git a/drivers/power/pmic/pmic_bd71837.c b/drivers/power/pmic/pmic_bd71837.c new file mode 100644 index 00000000000..74195ccae89 --- /dev/null +++ b/drivers/power/pmic/pmic_bd71837.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static const char bd71837_name[] = "BD71837"; +int power_bd71837_init (unsigned char bus) { + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = bd71837_name; + p->interface = PMIC_I2C; + p->number_of_regs = BD71837_REG_NUM; + p->hw.i2c.addr = 0x4b; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + printf("power_bd71837_init\n"); + + return 0; +} diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index f7873ad27af..2a1ab3be88a 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o -obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_PFUZE100) += pfuze100.o obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index 97b4a98bf0b..c33737113de 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2015 Samsung Electronics + * Copyright 2017 NXP * * Przemyslaw Marczak * @@ -19,6 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; struct fixed_regulator_platdata { struct gpio_desc gpio; /* GPIO for regulator enable control */ unsigned int startup_delay_us; + unsigned int off_on_delay_us; }; static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) @@ -53,6 +55,8 @@ static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) /* Get optional ramp up delay */ dev_pdata->startup_delay_us = dev_read_u32_default(dev, "startup-delay-us", 0); + dev_pdata->off_on_delay_us = dev_read_u32_default(dev, + "off-on-delay-us", 0); return 0; } @@ -126,6 +130,10 @@ static int fixed_regulator_set_enable(struct udevice *dev, bool enable) udelay(dev_pdata->startup_delay_us); debug("%s: done\n", __func__); + if (!enable && dev_pdata->off_on_delay_us) { + udelay(dev_pdata->off_on_delay_us); + } + return 0; } diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 93e602e0ee0..e52a7e0f637 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -643,4 +643,10 @@ config SYS_SDMR depends on MPC8XX_CONS default 0 +config XEN_DEBUG_SERIAL + bool "XEN debug serial support" + depends on XEN + help + This is not pv console, it needs CONFIG_VERBOSE_DEBUG in XEN. + endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index cac9a8b3121..bc03fd5a93e 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_MSM_SERIAL) += serial_msm.o obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o +obj-$(CONFIG_XEN_DEBUG_SERIAL) += serial_xen.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 9891c20656f..482b8119523 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -182,8 +182,17 @@ static void _serial_putc(struct udevice *dev, char ch) static void _serial_puts(struct udevice *dev, const char *str) { - while (*str) - _serial_putc(dev, *str++); + struct dm_serial_ops *ops = serial_get_ops(dev); + int err; + + if (ops->puts) { + do { + err = ops->puts(dev, str); + } while (err == -EAGAIN); + } else { + while (*str) + _serial_putc(dev, *str++); + } } static int __serial_getc(struct udevice *dev) @@ -416,7 +425,7 @@ static int serial_post_probe(struct udevice *dev) return 0; memset(&sdev, '\0', sizeof(sdev)); - strncpy(sdev.name, dev->name, sizeof(sdev.name)); + strncpy(sdev.name, dev->name, sizeof(sdev.name) - 1); sdev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_DM; sdev.priv = dev; sdev.putc = serial_stub_putc; diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index cc4bdcb8346..6c9c58e8f56 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -136,6 +136,8 @@ serial_initfunc(ml2_serial_initialize); serial_initfunc(mpc85xx_serial_initialize); serial_initfunc(mpc8xx_serial_initialize); serial_initfunc(mxc_serial_initialize); +serial_initfunc(xen_serial_initialize); +serial_initfunc(serial_lpuart_initialize); serial_initfunc(mxs_auart_initialize); serial_initfunc(ns16550_serial_initialize); serial_initfunc(oc_serial_initialize); @@ -150,6 +152,7 @@ serial_initfunc(sconsole_serial_initialize); serial_initfunc(sh_serial_initialize); serial_initfunc(stm32_serial_initialize); serial_initfunc(uartlite_serial_initialize); +serial_initfunc(xen_debug_serial_initialize); serial_initfunc(zynq_serial_initialize); /** @@ -223,6 +226,8 @@ void serial_initialize(void) mpc85xx_serial_initialize(); mpc8xx_serial_initialize(); mxc_serial_initialize(); + xen_serial_initialize(); + serial_lpuart_initialize(); mxs_auart_initialize(); ns16550_serial_initialize(); oc_serial_initialize(); @@ -237,6 +242,7 @@ void serial_initialize(void) sh_serial_initialize(); stm32_serial_initialize(); uartlite_serial_initialize(); + xen_debug_serial_initialize(); zynq_serial_initialize(); serial_assign(default_serial_console()->name); diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 536d30f66a0..a8177806e19 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -41,10 +41,16 @@ #define CTRL_TE (1 << 19) #define CTRL_RE (1 << 18) +#define FIFO_RXFLUSH (1 << 14) +#define FIFO_TXFLUSH (1 << 15) +#define FIFO_TXSIZE_MASK 0x70 +#define FIFO_TXSIZE_OFF 4 +#define FIFO_RXSIZE_MASK 0x7 +#define FIFO_RXSIZE_OFF 0 #define FIFO_TXFE 0x80 -#define FIFO_RXFE 0x40 +#define FIFO_RXFE 0x08 -#define WATER_TXWATER_OFF 1 +#define WATER_TXWATER_OFF 0 #define WATER_RXWATER_OFF 16 DECLARE_GLOBAL_DATA_PTR; @@ -55,7 +61,8 @@ DECLARE_GLOBAL_DATA_PTR; enum lpuart_devtype { DEV_VF610 = 1, DEV_LS1021A, - DEV_MX7ULP + DEV_MX7ULP, + DEV_IMX8 }; struct lpuart_serial_platdata { @@ -94,13 +101,6 @@ u32 __weak get_lpuart_clk(void) return CONFIG_SYS_CLK_FREQ; } -static bool is_lpuart32(struct udevice *dev) -{ - struct lpuart_serial_platdata *plat = dev->platdata; - - return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG; -} - static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat, int baudrate) { @@ -314,19 +314,29 @@ static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat) static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat) { struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg; - u32 ctrl; + u32 val, tx_fifo_size; - lpuart_read32(plat->flags, &base->ctrl, &ctrl); - ctrl &= ~CTRL_RE; - ctrl &= ~CTRL_TE; - lpuart_write32(plat->flags, &base->ctrl, ctrl); + lpuart_read32(plat->flags, &base->ctrl, &val); + val &= ~CTRL_RE; + val &= ~CTRL_TE; + lpuart_write32(plat->flags, &base->ctrl, val); lpuart_write32(plat->flags, &base->modir, 0); - lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); + + lpuart_read32(plat->flags, &base->fifo, &val); + tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF; + if (tx_fifo_size > 1) + tx_fifo_size = tx_fifo_size >> 1; /* Set the TX water to half of FIFO size */ + + /* Set RX water to 0, to be triggered by any receive data */ + lpuart_write32(plat->flags, &base->water, (tx_fifo_size << WATER_TXWATER_OFF)); + + val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH); /* Enable TX and RX FIFO */ + lpuart_write32(plat->flags, &base->fifo, val); lpuart_write32(plat->flags, &base->match, 0); - if (plat->devtype == DEV_MX7ULP) { + if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) { _lpuart32_serial_setbrg_7ulp(plat, gd->baudrate); } else { /* provide data bits, parity, stop bit, etc */ @@ -338,12 +348,113 @@ static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat) return 0; } +#ifndef CONFIG_DM_SERIAL + +#ifndef CONFIG_SERIAL_LPUART_BASE +#error "define CONFIG_SERIAL_LPUART_BASE to use the MXC UART driver" +#endif + +#define lpuart_base ((struct mxc_uart *)CONFIG_SERIAL_LPUART_BASE) + +struct lpuart_serial_platdata lpuart_serial_data = { + .reg = lpuart_base, + .devtype = DEV_IMX8, + .flags = LPUART_FLAG_REGMAP_32BIT_REG, +}; + +static void serial_lpuart_setbrg(void) +{ + struct lpuart_serial_platdata *plat = &lpuart_serial_data; + + if (plat->flags & LPUART_FLAG_REGMAP_32BIT_REG) { + if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) + _lpuart32_serial_setbrg_7ulp(plat, gd->baudrate); + else + _lpuart32_serial_setbrg(plat, gd->baudrate); + } else { + _lpuart_serial_setbrg(plat, gd->baudrate); + } + +} + +static int serial_lpuart_init(void) +{ + struct lpuart_serial_platdata *plat = &lpuart_serial_data; + + if (plat->flags & LPUART_FLAG_REGMAP_32BIT_REG) + return _lpuart32_serial_init(plat); + else + return _lpuart_serial_init(plat); + + return 0; +} + +static int serial_lpuart_getc(void) +{ + struct lpuart_serial_platdata *plat = &lpuart_serial_data; + + if (plat->flags & LPUART_FLAG_REGMAP_32BIT_REG) + return _lpuart32_serial_getc(plat); + + return _lpuart_serial_getc(plat); +} + +static void serial_lpuart_putc(const char c) +{ + struct lpuart_serial_platdata *plat = &lpuart_serial_data; + + if (plat->flags & LPUART_FLAG_REGMAP_32BIT_REG) + _lpuart32_serial_putc(plat, c); + else + _lpuart_serial_putc(plat, c); +} + +static int serial_lpuart_tstc(void) +{ + struct lpuart_serial_platdata *plat = &lpuart_serial_data; + + if (plat->flags & LPUART_FLAG_REGMAP_32BIT_REG) + return _lpuart32_serial_tstc(plat); + + return _lpuart_serial_tstc(plat); +} + +static struct serial_device serial_lpuart_drv = { + .name = "serial_lpuart", + .start = serial_lpuart_init, + .stop = NULL, + .setbrg = serial_lpuart_setbrg, + .putc = serial_lpuart_putc, + .puts = default_serial_puts, + .getc = serial_lpuart_getc, + .tstc = serial_lpuart_tstc, +}; + +__weak struct serial_device *default_serial_console(void) +{ + return &serial_lpuart_drv; +} + +void serial_lpuart_initialize(void) +{ + serial_register(&serial_lpuart_drv); +} + +#else /* CONFIG_DM_SERIAL */ + +static bool is_lpuart32(struct udevice *dev) +{ + struct lpuart_serial_platdata *plat = dev->platdata; + + return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG; +} + static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) { struct lpuart_serial_platdata *plat = dev->platdata; if (is_lpuart32(dev)) { - if (plat->devtype == DEV_MX7ULP) + if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) _lpuart32_serial_setbrg_7ulp(plat, baudrate); else _lpuart32_serial_setbrg(plat, baudrate); @@ -398,6 +509,7 @@ static int lpuart_serial_pending(struct udevice *dev, bool input) return __raw_readb(®->us1) & US1_TDRE ? 0 : 1; } + static int lpuart_serial_probe(struct udevice *dev) { struct lpuart_serial_platdata *plat = dev->platdata; @@ -428,6 +540,8 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) plat->devtype = DEV_MX7ULP; else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) plat->devtype = DEV_VF610; + else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart")) + plat->devtype = DEV_IMX8; return 0; } @@ -445,6 +559,8 @@ static const struct udevice_id lpuart_serial_ids[] = { { .compatible = "fsl,imx7ulp-lpuart", .data = LPUART_FLAG_REGMAP_32BIT_REG }, { .compatible = "fsl,vf610-lpuart"}, + { .compatible = "fsl,imx8qm-lpuart", + .data = LPUART_FLAG_REGMAP_32BIT_REG }, { } }; @@ -458,3 +574,5 @@ U_BOOT_DRIVER(serial_lpuart) = { .ops = &lpuart_serial_ops, .flags = DM_FLAG_PRE_RELOC, }; + +#endif diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index cce80a8559e..552952ef46c 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -212,12 +212,27 @@ static void mxc_serial_putc(const char c) WATCHDOG_RESET(); } -/* Test whether a character is in the RX buffer */ +/* + * Test whether a character is in the RX buffer + */ +static int one_time_rx_line_always_low_workaround_needed = 1; static int mxc_serial_tstc(void) { /* If receive fifo is empty, return false */ if (readl(&mxc_base->ts) & UTS_RXEMPTY) return 0; + + /* Empty RX FIFO if receiver is stuck because of RXD line being low */ + if (one_time_rx_line_always_low_workaround_needed) { + one_time_rx_line_always_low_workaround_needed = 0; + if (!(readl(&mxc_base->sr2) & USR2_RDR)) { + while (!(readl(&mxc_base->ts) & UTS_RXEMPTY)) { + (void) readl(&mxc_base->rxd); + } + return 0; + } + } + return 1; } diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c new file mode 100644 index 00000000000..f20765c3061 --- /dev/null +++ b/drivers/serial/serial_xen.c @@ -0,0 +1,244 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DM_SERIAL +struct xen_uart_priv { + struct xencons_interface *intf; + u32 evtchn; + int vtermno; + struct hvc_struct *hvc; + grant_ref_t gntref; +}; + +int xen_serial_setbrg(struct udevice *dev, int baudrate) +{ + return 0; +} + +static int xen_serial_probe(struct udevice *dev) +{ + struct xen_uart_priv *priv = dev_get_priv(dev); + u64 v = 0; + unsigned long gfn; + int r; + + r = hvm_get_parameter(HVM_PARAM_CONSOLE_EVTCHN, &v); + if (r < 0 || v == 0) + return r; + + priv->evtchn = v; + + r = hvm_get_parameter(HVM_PARAM_CONSOLE_PFN, &v); + if (r < 0 || v == 0) + return -ENODEV; + + gfn = v; + + priv->intf = (struct xencons_interface *)(gfn << XEN_PAGE_SHIFT); + if (!priv->intf) + return -EINVAL; + + return 0; +} + +static int xen_serial_pending(struct udevice *dev, bool input) +{ + struct xen_uart_priv *priv = dev_get_priv(dev); + struct xencons_interface *intf = priv->intf; + + if (!input || intf->in_cons == intf->in_prod) + return 0; + + return 1; +} + +static int xen_serial_getc(struct udevice *dev) +{ + struct xen_uart_priv *priv = dev_get_priv(dev); + struct xencons_interface *intf = priv->intf; + XENCONS_RING_IDX cons; + char c; + + while (intf->in_cons == intf->in_prod) { + mb(); /* wait */ + } + + cons = intf->in_cons; + mb(); /* get pointers before reading ring */ + + c = intf->in[MASK_XENCONS_IDX(cons++, intf->in)]; + + mb(); /* read ring before consuming */ + intf->in_cons = cons; + + notify_remote_via_evtchn(priv->evtchn); + + return c; +} + +static int __write_console(struct udevice *dev, const char *data, int len) +{ + struct xen_uart_priv *priv = dev_get_priv(dev); + struct xencons_interface *intf = priv->intf; + XENCONS_RING_IDX cons, prod; + int sent = 0; + + cons = intf->out_cons; + prod = intf->out_prod; + mb(); /* Update pointer */ + + WARN_ON((prod - cons) > sizeof(intf->out)); + + while ((sent < len) && ((prod - cons) < sizeof(intf->out))) + intf->out[MASK_XENCONS_IDX(prod++, intf->out)] = data[sent++]; + + mb(); /* Update data before pointer */ + intf->out_prod = prod; + + if (sent) + notify_remote_via_evtchn(priv->evtchn); + + if (data[sent - 1] == '\n') + serial_puts("\r"); + + return sent; +} + +static int write_console(struct udevice *dev, const char *data, int len) +{ + /* + * Make sure the whole buffer is emitted, polling if + * necessary. We don't ever want to rely on the hvc daemon + * because the most interesting console output is when the + * kernel is crippled. + */ + while (len) { + int sent = __write_console(dev, data, len); + + data += sent; + len -= sent; + + if (unlikely(len)) + HYPERVISOR_sched_op(SCHEDOP_yield, NULL); + } + + return 0; +} + +static int xen_serial_puts(struct udevice *dev, const char *str) +{ + write_console(dev, str, strlen(str)); + + return 0; +} + +static int xen_serial_putc(struct udevice *dev, const char ch) +{ + write_console(dev, &ch, 1); + + return 0; +} + +static const struct dm_serial_ops xen_serial_ops = { + .puts = xen_serial_puts, + .putc = xen_serial_putc, + .getc = xen_serial_getc, + .pending = xen_serial_pending, +}; + +static const struct udevice_id xen_serial_ids[] = { + { .compatible = "xen,xen" }, + { } +}; + +U_BOOT_DRIVER(serial_xen) = { + .name = "serial_xen", + .id = UCLASS_SERIAL, + .of_match = xen_serial_ids, + .priv_auto_alloc_size = sizeof(struct xen_uart_priv), + .probe = xen_serial_probe, + .ops = &xen_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; +#else +static void xen_serial_putc(const char c) +{ + (void)HYPERVISOR_console_io(CONSOLEIO_write, 1, &c); +} + +static void xen_serial_puts(const char *str) +{ + (void)HYPERVISOR_console_io(CONSOLEIO_write, strlen(str), str); +} + +static int xen_serial_tstc(void) +{ + return 0; +} + +static int xen_serial_init(void) +{ +} + +static void xen_serial_setbrg(void) +{ +} + +static struct serial_device xen_serial_drv = { + .name = "xen_serial", + .start = xen_serial_init, + .stop = NULL, + .setbrg = xen_serial_setbrg, + .getc = NULL, + .putc = xen_serial_putc, + .puts = xen_serial_puts, + .tstc = xen_serial_tstc, +}; + +__weak struct serial_device *default_serial_console(void) +{ + return &xen_serial_drv; +} + +#endif + +#ifdef CONFIG_DEBUG_UART_XEN +void _debug_uart_init(void) +{ +} + +void _debug_uart_putc(int ch) +{ + /* If \n, also do \r */ + if (ch == '\n') + serial_putc('\r'); + + (void)HYPERVISOR_console_io(CONSOLEIO_write, 1, &ch); + + return; +} + +DEBUG_UART_FUNCS + +#endif diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 235a8c7d73a..ba8e7ccf1bb 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -225,6 +225,13 @@ config FSL_ESPI access the SPI interface and SPI NOR flash on platforms embedding this Freescale eSPI IP core. +config FSL_FSPI + bool "Freescale FlexSPI driver" + help + Enable the Freescale FlexSPI (FSPI) driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Freescale IP core. + config FSL_QSPI bool "Freescale QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4b6000fd9a0..683c62686f9 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o +obj-$(CONFIG_FSL_FSPI) += fsl_fspi.o obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o diff --git a/drivers/spi/fsl_fspi.c b/drivers/spi/fsl_fspi.c new file mode 100644 index 00000000000..460d284401c --- /dev/null +++ b/drivers/spi/fsl_fspi.c @@ -0,0 +1,1381 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "fsl_fspi.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define RX_BUFFER_SIZE 0x200 +#define TX_BUFFER_SIZE 0x400 +#define AHB_BUFFER_SIZE 0x800 + +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR +#define OFFSET_BITS_MASK GENMASK(31, 0) +#else +#define OFFSET_BITS_MASK GENMASK(23, 0) +#endif + +#define FLASH_STATUS_WEL 0x02 + +/* SEQID */ +#define SEQID_READ 0 +#define SEQID_WREN 1 +#define SEQID_FAST_READ 2 +#define SEQID_RDSR 3 +#define SEQID_SE 4 +#define SEQID_CHIP_ERASE 5 +#define SEQID_PP 6 +#define SEQID_RDID 7 +#define SEQID_BE_4K 8 +#ifdef CONFIG_SPI_FLASH_BAR +#define SEQID_BRRD 9 +#define SEQID_BRWR 10 +#define SEQID_RDEAR 11 +#define SEQID_WREAR 12 +#endif +#define SEQID_RDEVCR 13 +#define SEQID_WREVCR 14 +#define SEQID_QUAD_OUTPUT 15 +#define SEQID_RDFSR 16 +#define SEQID_EN4B 17 + + +/* FSPI CMD */ +#define FSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ +#define FSPI_CMD_RDSR 0x05 /* Read status register */ +#define FSPI_CMD_WREN 0x06 /* Write enable */ +#define FSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ +#define FSPI_CMD_READ 0x03 /* Read data bytes */ +#define FSPI_CMD_BE_4K 0x20 /* 4K erase */ +#define FSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define FSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define FSPI_CMD_RDID 0x9f /* Read JEDEC ID */ + +/* Used for Micron, winbond and Macronix flashes */ +#define FSPI_CMD_WREAR 0xc5 /* EAR register write */ +#define FSPI_CMD_RDEAR 0xc8 /* EAR reigster read */ + +/* Used for Spansion flashes only. */ +#define FSPI_CMD_BRRD 0x16 /* Bank register read */ +#define FSPI_CMD_BRWR 0x17 /* Bank register write */ + +/* 4-byte address FSPI CMD - used on Spansion and some Macronix flashes */ +#define FSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ +#define FSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */ +#define FSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ +#define FSPI_CMD_BE_4K_4B 0x21 /* 4K erase */ + +#define FSPI_CMD_RD_EVCR 0x65 /* Read EVCR register */ +#define FSPI_CMD_WR_EVCR 0x61 /* Write EVCR register */ + +#define FSPI_CMD_EN4B 0xB7 + +/* 1-1-4 READ CMD */ +#define FSPI_CMD_QUAD_OUTPUT 0x6b +#define FSPI_CMD_DDR_QUAD_OUTPUT 0x6d + +/* read flag status register */ +#define FSPI_CMD_RDFSR 0x70 + +/* fsl_fspi_platdata flags */ +#define FSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) + +/* default SCK frequency, unit: HZ */ +#define FSL_FSPI_DEFAULT_SCK_FREQ 50000000 + +/* FSPI max chipselect signals number */ +#define FSL_FSPI_MAX_CHIPSELECT_NUM 4 + +#ifdef CONFIG_DM_SPI +/** + * struct fsl_fspi_platdata - platform data for NXP FSPI + * + * @flags: Flags for FSPI FSPI_FLAG_... + * @speed_hz: Default SCK frequency + * @reg_base: Base address of FSPI registers + * @amba_base: Base address of FSPI memory mapping + * @amba_total_size: size of FSPI memory mapping + * @flash_num: Number of active slave devices + * @num_chipselect: Number of FSPI chipselect signals + */ +struct fsl_fspi_platdata { + u32 flags; + u32 speed_hz; + u32 reg_base; + u32 amba_base; + u32 amba_total_size; + u32 flash_num; + u32 num_chipselect; +}; +#endif + +/** + * struct fsl_fspi_priv - private data for NXP FSPI + * + * @flags: Flags for FSPI FSPI_FLAG_... + * @bus_clk: FSPI input clk frequency + * @speed_hz: Default SCK frequency + * @cur_seqid: current LUT table sequence id + * @sf_addr: flash access offset + * @amba_base: Base address of FSPI memory mapping of every CS + * @amba_total_size: size of FSPI memory mapping + * @cur_amba_base: Base address of FSPI memory mapping of current CS + * @flash_num: Number of active slave devices + * @num_chipselect: Number of FSPI chipselect signals + * @regs: Point to FSPI register structure for I/O access + */ +struct fsl_fspi_priv { + u32 flags; + u32 bus_clk; + u32 speed_hz; + u32 cur_seqid; + u32 sf_addr; + u32 amba_base[FSL_FSPI_MAX_CHIPSELECT_NUM]; + u32 amba_total_size; + u32 cur_amba_base; + u32 flash_num; + u32 num_chipselect; + struct fsl_fspi_regs *regs; +}; + +#ifndef CONFIG_DM_SPI +struct fsl_fspi { + struct spi_slave slave; + struct fsl_fspi_priv priv; +}; +#endif + +static u32 fspi_read32(u32 flags, u32 *addr) +{ + return flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ? + in_be32(addr) : in_le32(addr); +} + +static void fspi_write32(u32 flags, u32 *addr, u32 val) +{ + flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ? + out_be32(addr, val) : out_le32(addr, val); +} + +/* FSPI support swapping the flash read/write data + * in hardware + */ +static inline u32 fspi_endian_xchg(u32 data) +{ + return data; +} + +static void fspi_set_lut(struct fsl_fspi_priv *priv) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 lut_base; + + /* Unlock the LUT */ + fspi_write32(priv->flags, ®s->lutkey, FLEXSPI_LUTKEY_VALUE); + fspi_write32(priv->flags, ®s->lutcr, FLEXSPI_LCKER_UNLOCK); + + /* READ */ + lut_base = SEQID_READ * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(FSPI_CMD_READ) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], + OPRND0(0) | PAD0(LUT_PAD1) | + INSTR0(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Write Enable */ + lut_base = SEQID_WREN * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_WREN) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Fast Read */ + lut_base = SEQID_FAST_READ * 4; +#ifdef CONFIG_SPI_FLASH_BAR + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(FSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#else + if (FSL_FSPI_FLASH_SIZE <= SZ_16M) + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(FSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(FSPI_CMD_FAST_READ_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | + OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | + INSTR1(LUT_ADDR)); +#endif + fspi_write32(priv->flags, ®s->lut[lut_base + 1], + OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) | + OPRND1(0) | PAD1(LUT_PAD1) | + INSTR1(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Read Status */ + lut_base = SEQID_RDSR * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_RDSR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Erase a sector */ + lut_base = SEQID_SE * 4; +#ifdef CONFIG_SPI_FLASH_BAR + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_SE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#else + if (FSL_FSPI_FLASH_SIZE <= SZ_16M) + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(FSPI_CMD_SE) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(FSPI_CMD_SE_4B) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#endif + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Erase the whole chip */ + lut_base = SEQID_CHIP_ERASE * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(FSPI_CMD_CHIP_ERASE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Page Program */ + lut_base = SEQID_PP * 4; +#ifdef CONFIG_SPI_FLASH_BAR + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_PP) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#else + if (FSL_FSPI_FLASH_SIZE <= SZ_16M) + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(FSPI_CMD_PP) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(FSPI_CMD_PP_4B) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#endif + fspi_write32(priv->flags, ®s->lut[lut_base + 1], + OPRND0(0) | + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* READ ID */ + lut_base = SEQID_RDID * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_RDID) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* SUB SECTOR 4K ERASE */ + lut_base = SEQID_BE_4K * 4; +#ifdef CONFIG_SPI_FLASH_BAR + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_BE_4K) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#else + if (FSL_FSPI_FLASH_SIZE <= SZ_16M) + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_BE_4K) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_BE_4K_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#endif + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + +#ifdef CONFIG_SPI_FLASH_BAR + /* + * BRRD BRWR RDEAR WREAR are all supported, because it is hard to + * dynamically check whether to set BRRD BRWR or RDEAR WREAR during + * initialization. + */ + lut_base = SEQID_BRRD * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_BRRD) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + lut_base = SEQID_BRWR * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_BRWR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + lut_base = SEQID_RDEAR * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_RDEAR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + lut_base = SEQID_WREAR * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_WREAR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); +#endif + lut_base = SEQID_RDEVCR * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_RD_EVCR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + lut_base = SEQID_WREVCR * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_WR_EVCR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + +#ifdef CONFIG_FSPI_QUAD_SUPPORT + /* QUAD OUTPUT READ */ + lut_base = SEQID_QUAD_OUTPUT * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(FSPI_CMD_DDR_QUAD_OUTPUT) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR_DDR)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], + OPRND0(0xc) | PAD0(LUT_PAD4) | + INSTR0(LUT_DUMMY_DDR) | OPRND1(0) | + PAD1(LUT_PAD4) | INSTR1(LUT_READ_DDR)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); +#endif + + /* Read Flag Status */ + lut_base = SEQID_RDFSR * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_RDFSR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Enter 4 bytes address mode */ + lut_base = SEQID_EN4B * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_EN4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Lock the LUT */ + fspi_write32(priv->flags, ®s->lutkey, FLEXSPI_LUTKEY_VALUE); + fspi_write32(priv->flags, ®s->lutcr, FLEXSPI_LCKER_LOCK); +} + +#if defined(CONFIG_SYS_FSL_FSPI_AHB) +/* + * If we have changed the content of the flash by writing or erasing, + * we need to invalidate the AHB buffer. If we do not do so, we may read out + * the wrong data. The spec tells us reset the AHB domain and Serial Flash + * domain at the same time. + */ +static inline void fspi_ahb_invalid(struct fsl_fspi_priv *priv) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 reg; + + reg = fspi_read32(priv->flags, ®s->mcr0); + reg |= FLEXSPI_MCR0_SWRST_MASK; + fspi_write32(priv->flags, ®s->mcr0, reg); + + /* + * The minimum delay : 1 AHB + 2 SFCK clocks. + * Delay 1 us is enough. + */ + while ((fspi_read32(priv->flags, ®s->mcr0) & 1)) + ; +} + +#define FSPI_AHB_BASE_ADDR 0x08000000 +/* Read out the data from the AHB buffer. */ +static inline void fspi_ahb_read(struct fsl_fspi_priv *priv, u8 *rxbuf, int len) +{ + /* Read out the data directly from the AHB buffer. */ + memcpy(rxbuf, (u8 *)(0x08000000 + (uintptr_t)priv->sf_addr) , len); + +} + +/* + * There are two different ways to read out the data from the flash: + * the "IP Command Read" and the "AHB Command Read". + * + * The IC guy suggests we use the "AHB Command Read" which is faster + * then the "IP Command Read". (What's more is that there is a bug in + * the "IP Command Read" in the Vybrid.) + * + * After we set up the registers for the "AHB Command Read", we can use + * the memcpy to read the data directly. A "missed" access to the buffer + * causes the controller to clear the buffer, and use the sequence pointed + * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash. + */ +static void fspi_init_ahb_read(struct fsl_fspi_priv *priv) +{ + struct fsl_fspi_regs *regs = priv->regs; + int i; + + /* AHB configuration for access buffer 0~7 .*/ + for (i = 0; i < 7; i++) + fspi_write32(priv->flags, ®s->ahbrxbuf0cr0 + i, 0); + + /* + * Set ADATSZ with the maximum AHB buffer size to improve the read + * performance + */ + fspi_write32(priv->flags, ®s->ahbrxbuf7cr0, AHB_BUFFER_SIZE / 8 | + FLEXSPI_AHBRXBUF0CR7_PREF_MASK); + + fspi_write32(priv->flags, ®s->ahbcr, FLEXSPI_AHBCR_PREF_EN_MASK); + /* + * Set the default lut sequence for AHB Read. + * Parallel mode is disabled. + */ +#ifdef CONFIG_FSPI_QUAD_SUPPORT + fspi_write32(priv->flags, ®s->flsha1cr2, SEQID_QUAD_OUTPUT); +#else + fspi_write32(priv->flags, ®s->flsha1cr2, SEQID_FAST_READ); +#endif + +} +#endif + +#ifdef CONFIG_SPI_FLASH_BAR +/* Bank register read/write, EAR register read/write */ +static void fspi_op_rdbank(struct fsl_fspi_priv *priv, u8 *rxbuf, u32 len) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 data, seqid; + + /* invalid the RXFIFO first */ + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, priv->cur_amba_base); + + if (priv->cur_seqid == FSPI_CMD_BRRD) + seqid = SEQID_BRRD; + else + seqid = SEQID_RDEAR; + + fspi_write32(priv->flags, ®s->ipcr1, + (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | len); + + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + while (1) { + data = fspi_read32(priv->flags, ®s->rfdr[0]); + memcpy(rxbuf, &data, len); + break; + } + + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPRXWA_MASK); + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); + +} +#endif + +static void fspi_op_rdevcr(struct fsl_fspi_priv *priv, u8 *rxbuf, u32 len) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 data; + + /* invalid the RXFIFO first */ + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, priv->cur_amba_base); + + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_RDEVCR << FLEXSPI_IPCR1_SEQID_SHIFT) | len); + + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + while (1) { + data = fspi_read32(priv->flags, ®s->rfdr[0]); + memcpy(rxbuf, &data, len); + break; + } + + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPRXWA_MASK); + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); + +} + +static void fspi_op_wrevcr(struct fsl_fspi_priv *priv, u8 *txbuf, u32 len) +{ + struct fsl_fspi_regs *regs = priv->regs; + + /* invalid the TXFIFO first */ + fspi_write32(priv->flags, ®s->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, priv->cur_amba_base); + + /* Wait for TXFIFO empty*/ + while (!(fspi_read32(priv->flags, ®s->intr) & FLEXSPI_INTR_IPTXWE_MASK)) + ; + + /* write the data to TXFIFO */ + memcpy(®s->tfdr, txbuf, len); + + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPTXWE_MASK); + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_WREVCR << FLEXSPI_IPCR1_SEQID_SHIFT) | len); + + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + /* invalid the TXFIFO first */ + fspi_write32(priv->flags, ®s->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); + +} + +static void fspi_op_rdid(struct fsl_fspi_priv *priv, u32 *rxbuf, u32 len) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 data, size; + int i; + + /* invalid the RXFIFO first */ + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, priv->cur_amba_base); + + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_RDID << FLEXSPI_IPCR1_SEQID_SHIFT) | len); + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + i = 0; + while ((RX_BUFFER_SIZE >= len) && (len > 0)) { + data = fspi_read32(priv->flags, ®s->rfdr[i]); + size = (len < 4) ? len : 4; + memcpy(rxbuf, &data, size); + len -= size; + rxbuf++; + i++; + } + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPRXWA_MASK); + + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); +} + +#ifndef CONFIG_SYS_FSL_FSPI_AHB +/* If not use AHB read, read data from ip interface */ +static void fspi_op_read(struct fsl_fspi_priv *priv, u32 *rxbuf, u32 len) +{ + struct fsl_fspi_regs *regs = priv->regs; + int i, size, rx_size; + u32 to_or_from; + + to_or_from = priv->sf_addr + priv->cur_amba_base; + + /* invalid the RXFIFO */ + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + + while (len > 0) { + WATCHDOG_RESET(); + + fspi_write32(priv->flags, ®s->ipcr0, to_or_from); + + rx_size = (len > RX_BUFFER_SIZE) ? + RX_BUFFER_SIZE : len; + +#ifdef CONFIG_FSPI_QUAD_SUPPORT + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_QUAD_OUTPUT << FLEXSPI_IPCR1_SEQID_SHIFT) | + rx_size); +#else + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_FAST_READ << FLEXSPI_IPCR1_SEQID_SHIFT) | + rx_size); +#endif + + to_or_from += rx_size; + len -= rx_size; + + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + size = rx_size / 8; + for (i = 0; i < size; ++i) { + /* Wait for RXFIFO available*/ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPRXWA_MASK)) + ; + + memcpy(rxbuf, ®s->rfdr, 8); + rxbuf += 2; + + /* move the FIFO pointer */ + fspi_write32(priv->flags, ®s->intr, + FLEXSPI_INTR_IPRXWA_MASK); + } + + size = rx_size % 8; + + if (size) { + /* Wait for data filled*/ + while (!(fspi_read32(priv->flags, ®s->iprxfsts) + & FLEXSPI_IPRXFSTS_FILL_MASK)) + ; + memcpy(rxbuf, ®s->rfdr, size); + } + + /* invalid the RXFIFO */ + fspi_write32(priv->flags, ®s->iprxfcr, + FLEXSPI_IPRXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, + FLEXSPI_INTR_IPCMDDONE_MASK); + } + +} +#endif + +static void fspi_op_write(struct fsl_fspi_priv *priv, u8 *txbuf, u32 len) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 seqid; + int i, size, tx_size; + u32 to_or_from = 0; + + /* invalid the TXFIFO first */ + fspi_write32(priv->flags, ®s->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, priv->cur_amba_base); + + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_WREN << FLEXSPI_IPCR1_SEQID_SHIFT) | 0); + + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); + + /* invalid the TXFIFO first */ + fspi_write32(priv->flags, ®s->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK); + + to_or_from = priv->sf_addr + priv->cur_amba_base; + + while (len > 0) { + + /* Default is page programming */ + seqid = SEQID_PP; +#ifdef CONFIG_SPI_FLASH_BAR + if (priv->cur_seqid == FSPI_CMD_BRWR) + seqid = SEQID_BRWR; + else if (priv->cur_seqid == FSPI_CMD_WREAR) + seqid = SEQID_WREAR; +#endif + + + fspi_write32(priv->flags, ®s->ipcr0, to_or_from); + + tx_size = (len > TX_BUFFER_SIZE) ? + TX_BUFFER_SIZE : len; + + to_or_from += tx_size; + len -= tx_size; + + size = tx_size / 8; + for (i = 0; i < size; i++) { + /* Wait for TXFIFO empty*/ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPTXWE_MASK)) + ; + + memcpy(®s->tfdr, txbuf, 8); + txbuf += 8; + fspi_write32(priv->flags, ®s->intr, + FLEXSPI_INTR_IPTXWE_MASK); + } + + size = tx_size % 8; + if (size) { + /* Wait for TXFIFO empty*/ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPTXWE_MASK)) + ; + + memcpy(®s->tfdr, txbuf, size); + fspi_write32(priv->flags, ®s->intr, + FLEXSPI_INTR_IPTXWE_MASK); + } + + fspi_write32(priv->flags, ®s->ipcr1, + (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | tx_size); + + + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + /* invalid the TXFIFO first */ + fspi_write32(priv->flags, ®s->iptxfcr, + FLEXSPI_IPTXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, + FLEXSPI_INTR_IPCMDDONE_MASK); + } +} + +static void fspi_op_rdsr(struct fsl_fspi_priv *priv, void *rxbuf, u32 len) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 data; + + /* invalid the RXFIFO first */ + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, priv->cur_amba_base); + + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_RDSR << FLEXSPI_IPCR1_SEQID_SHIFT) | len); + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + data = fspi_read32(priv->flags, ®s->rfdr[0]); + memcpy(rxbuf, &data, len); + + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPRXWA_MASK); + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); +} + +static void fspi_op_rdfsr(struct fsl_fspi_priv *priv, void *rxbuf, u32 len) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 data; + + /* invalid the RXFIFO first */ + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, priv->cur_amba_base); + + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_RDFSR << FLEXSPI_IPCR1_SEQID_SHIFT) | len); + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + data = fspi_read32(priv->flags, ®s->rfdr[0]); + memcpy(rxbuf, &data, len); + + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPRXWA_MASK); + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); +} + +static void fspi_op_erase(struct fsl_fspi_priv *priv) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 to_or_from = 0; + + to_or_from = priv->sf_addr + priv->cur_amba_base; + + fspi_write32(priv->flags, ®s->ipcr0, to_or_from); + + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_WREN << FLEXSPI_IPCR1_SEQID_SHIFT) | 0); + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); + + if (priv->cur_seqid == FSPI_CMD_SE || priv->cur_seqid == FSPI_CMD_SE_4B) { + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_SE << FLEXSPI_IPCR1_SEQID_SHIFT) | 0); + } else if (priv->cur_seqid == FSPI_CMD_BE_4K || priv->cur_seqid == FSPI_CMD_BE_4K_4B) { + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_BE_4K << FLEXSPI_IPCR1_SEQID_SHIFT) | 0); + } + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); +} + +static void fspi_op_enter_4bytes(struct fsl_fspi_priv *priv) +{ + struct fsl_fspi_regs *regs = priv->regs; + + /* invalid the TXFIFO first */ + fspi_write32(priv->flags, ®s->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, priv->cur_amba_base); + + fspi_write32(priv->flags, ®s->ipcr1, + (SEQID_EN4B << FLEXSPI_IPCR1_SEQID_SHIFT) | 0); + + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); + + +} + +int fspi_xfer(struct fsl_fspi_priv *priv, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + u32 bytes = DIV_ROUND_UP(bitlen, 8); + static u32 wr_sfaddr; + u32 txbuf = 0; + + if (dout) { + if (flags & SPI_XFER_BEGIN) { + priv->cur_seqid = *(u8 *)dout; +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR + if (FSL_FSPI_FLASH_SIZE > SZ_16M) + dout = (u8 *)dout + 1; +#endif + memcpy(&txbuf, dout, 4); + } + + if (flags == SPI_XFER_END) { + if (priv->cur_seqid == FSPI_CMD_WR_EVCR) { + fspi_op_wrevcr(priv, (u8 *)dout, bytes); + return 0; + } + priv->sf_addr = wr_sfaddr; + fspi_op_write(priv, (u8 *)dout, bytes); + return 0; + } + + if (priv->cur_seqid == FSPI_CMD_QUAD_OUTPUT || + priv->cur_seqid == FSPI_CMD_FAST_READ || + priv->cur_seqid == FSPI_CMD_FAST_READ_4B) { + priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; + } else if ((priv->cur_seqid == FSPI_CMD_SE) || + (priv->cur_seqid == FSPI_CMD_BE_4K) || + (priv->cur_seqid == FSPI_CMD_SE_4B) || + (priv->cur_seqid == FSPI_CMD_BE_4K_4B)) { + priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; + fspi_op_erase(priv); + } else if (priv->cur_seqid == FSPI_CMD_PP || + priv->cur_seqid == FSPI_CMD_PP_4B) { + wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; + } else if (priv->cur_seqid == FSPI_CMD_WR_EVCR) { + wr_sfaddr = 0; + } else if ((priv->cur_seqid == FSPI_CMD_BRWR) || + (priv->cur_seqid == FSPI_CMD_WREAR)) { +#ifdef CONFIG_SPI_FLASH_BAR + wr_sfaddr = 0; +#endif + } else if (priv->cur_seqid == FSPI_CMD_EN4B) { + fspi_op_enter_4bytes(priv); + } + } + + if (din) { + if (priv->cur_seqid == FSPI_CMD_QUAD_OUTPUT || + priv->cur_seqid == FSPI_CMD_FAST_READ || + priv->cur_seqid == FSPI_CMD_FAST_READ_4B) { +#ifdef CONFIG_SYS_FSL_FSPI_AHB + fspi_ahb_read(priv, din, bytes); +#else + fspi_op_read(priv, din, bytes); +#endif + } else if (priv->cur_seqid == FSPI_CMD_RDID) + fspi_op_rdid(priv, din, bytes); + else if (priv->cur_seqid == FSPI_CMD_RDSR) + fspi_op_rdsr(priv, din, bytes); + else if (priv->cur_seqid == FSPI_CMD_RDFSR) + fspi_op_rdfsr(priv, din, bytes); + else if (priv->cur_seqid == FSPI_CMD_RD_EVCR) + fspi_op_rdevcr(priv, din, bytes); +#ifdef CONFIG_SPI_FLASH_BAR + else if ((priv->cur_seqid == FSPI_CMD_BRRD) || + (priv->cur_seqid == FSPI_CMD_RDEAR)) { + priv->sf_addr = 0; + fspi_op_rdbank(priv, din, bytes); + } +#endif + } + +#ifdef CONFIG_SYS_FSL_FSPI_AHB + if ((priv->cur_seqid == FSPI_CMD_SE) || + (priv->cur_seqid == FSPI_CMD_SE_4B) || + (priv->cur_seqid == FSPI_CMD_PP) || + (priv->cur_seqid == FSPI_CMD_PP_4B) || + (priv->cur_seqid == FSPI_CMD_BE_4K) || + (priv->cur_seqid == FSPI_CMD_BE_4K_4B) || + (priv->cur_seqid == FSPI_CMD_WREAR) || + (priv->cur_seqid == FSPI_CMD_BRWR)) + fspi_ahb_invalid(priv); +#endif + + return 0; +} + +void fspi_module_disable(struct fsl_fspi_priv *priv, u8 disable) +{ + u32 mcr_val; + + mcr_val = fspi_read32(priv->flags, &priv->regs->mcr0); + if (disable) + mcr_val |= FLEXSPI_MCR0_MDIS_MASK; + else + mcr_val &= ~FLEXSPI_MCR0_MDIS_MASK; + fspi_write32(priv->flags, &priv->regs->mcr0, mcr_val); +} + +void fspi_cfg_smpr(struct fsl_fspi_priv *priv, u32 clear_bits, u32 set_bits) +{ + return; +#if 0 + u32 smpr_val; + + smpr_val = fspi_read32(priv->flags, &priv->regs->smpr); + smpr_val &= ~clear_bits; + smpr_val |= set_bits; + fspi_write32(priv->flags, &priv->regs->smpr, smpr_val); +#endif +} + +__weak void init_clk_fspi(int index) +{ +} + +#ifndef CONFIG_DM_SPI +static unsigned long spi_bases[] = { + FSPI0_BASE_ADDR, +}; + +static unsigned long amba_bases[] = { + FSPI0_AMBA_BASE, +}; + +static inline struct fsl_fspi *to_fspi_spi(struct spi_slave *slave) +{ + return container_of(slave, struct fsl_fspi, slave); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_fspi *fspi; + struct fsl_fspi_regs *regs; + u32 total_size; + + if (bus >= ARRAY_SIZE(spi_bases)) + return NULL; + + if (cs >= FSL_FSPI_FLASH_NUM) + return NULL; + + fspi = spi_alloc_slave(struct fsl_fspi, bus, cs); + if (!fspi) + return NULL; + +#ifdef CONFIG_SYS_FSL_FSPI_BE + fspi->priv.flags |= FSPI_FLAG_REGMAP_ENDIAN_BIG; +#endif + + init_clk_fspi(bus); + + regs = (struct fsl_fspi_regs *)spi_bases[bus]; + fspi->priv.regs = regs; + /* + * According cs, use different amba_base to choose the + * corresponding flash devices. + * + * If not, only one flash device is used even if passing + * different cs using `sf probe` + */ + fspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_FSPI_FLASH_SIZE; + + fspi->slave.max_write_size = TX_BUFFER_SIZE; + +#ifdef CONFIG_FSPI_QUAD_SUPPORT + fspi->slave.mode |= SPI_RX_QUAD; +#endif + + fspi_write32(fspi->priv.flags, ®s->mcr0, + FLEXSPI_MCR0_SWRST_MASK); + do { + udelay(1); + } while (0x1 & fspi_read32(fspi->priv.flags, ®s->mcr0)); + + /* Disable the module */ + fspi_module_disable(&fspi->priv, 1); + + /* Enable the module and set to proper value*/ + fspi_write32(fspi->priv.flags, ®s->mcr0, + 0xFFFF0000); + + total_size = FSL_FSPI_FLASH_SIZE * FSL_FSPI_FLASH_NUM >> 10; + /* + * Any read access to non-implemented addresses will provide + * undefined results. + * + * In case single die flash devices, TOP_ADDR_MEMA2 and + * TOP_ADDR_MEMB2 should be initialized/programmed to + * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, + * setting the size of these devices to 0. This would ensure + * that the complete memory map is assigned to only one flash device. + */ + fspi_write32(fspi->priv.flags, ®s->flsha1cr0, + total_size); + fspi_write32(fspi->priv.flags, ®s->flsha2cr0, + 0); + fspi_write32(fspi->priv.flags, ®s->flshb1cr0, + 0); + fspi_write32(fspi->priv.flags, ®s->flshb2cr0, + 0); + + fspi_set_lut(&fspi->priv); + +#ifdef CONFIG_SYS_FSL_FSPI_AHB + fspi_init_ahb_read(&fspi->priv); +#endif + + fspi_module_disable(&fspi->priv, 0); + + return &fspi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct fsl_fspi *fspi = to_fspi_spi(slave); + + free(fspi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Nothing to do */ +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct fsl_fspi *fspi = to_fspi_spi(slave); + + return fspi_xfer(&fspi->priv, bitlen, dout, din, flags); +} + +void spi_init(void) +{ + /* Nothing to do */ +} +#else +static int fsl_fspi_child_pre_probe(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + + slave->max_write_size = TX_BUFFER_SIZE; + +#ifdef CONFIG_FSPI_QUAD_SUPPORT + slave->mode |= SPI_RX_QUAD; +#endif + + return 0; +} + +static int fsl_fspi_probe(struct udevice *bus) +{ + u32 total_size; + struct fsl_fspi_platdata *plat = dev_get_platdata(bus); + struct fsl_fspi_priv *priv = dev_get_priv(bus); + struct dm_spi_bus *dm_spi_bus; + + init_clk_fspi(bus->seq); + + dm_spi_bus = bus->uclass_priv; + + dm_spi_bus->max_hz = plat->speed_hz; + + priv->regs = (struct fsl_fspi_regs *)(uintptr_t)plat->reg_base; + priv->flags = plat->flags; + + priv->speed_hz = plat->speed_hz; + priv->amba_base[0] = plat->amba_base; + priv->amba_total_size = plat->amba_total_size; + priv->flash_num = plat->flash_num; + priv->num_chipselect = plat->num_chipselect; + + fspi_write32(priv->flags, &priv->regs->mcr0, + FLEXSPI_MCR0_SWRST_MASK); + do { + udelay(1); + } while (0x1 & fspi_read32(priv->flags, &priv->regs->mcr0)); + + /* Disable the module */ + fspi_module_disable(priv, 1); + + /* Enable the module and set to proper value*/ + fspi_write32(priv->flags, &priv->regs->mcr0, + 0xFFFF0000); + + /* Reset the DLL register to default value */ + fspi_write32(priv->flags, &priv->regs->dllacr, 0x0100); + fspi_write32(priv->flags, &priv->regs->dllbcr, 0x0100); + + /* Flash Size in KByte */ + total_size = FSL_FSPI_FLASH_SIZE * FSL_FSPI_FLASH_NUM >> 10; + + /* + * Any read access to non-implemented addresses will provide + * undefined results. + * + * In case single die flash devices, TOP_ADDR_MEMA2 and + * TOP_ADDR_MEMB2 should be initialized/programmed to + * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, + * setting the size of these devices to 0. This would ensure + * that the complete memory map is assigned to only one flash device. + */ + + fspi_write32(priv->flags, &priv->regs->flsha1cr0, + total_size); + fspi_write32(priv->flags, &priv->regs->flsha2cr0, + 0); + fspi_write32(priv->flags, &priv->regs->flshb1cr0, + 0); + fspi_write32(priv->flags, &priv->regs->flshb2cr0, + 0); + + fspi_set_lut(priv); + +#ifdef CONFIG_SYS_FSL_FSPI_AHB + fspi_init_ahb_read(priv); +#endif + + fspi_module_disable(priv, 0); + + return 0; +} + +static int fsl_fspi_ofdata_to_platdata(struct udevice *bus) +{ + struct fdt_resource res_regs, res_mem; + struct fsl_fspi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = ofnode_to_offset(bus->node); + int ret, flash_num = 0, subnode; + + if (fdtdec_get_bool(blob, node, "big-endian")) + plat->flags |= FSPI_FLAG_REGMAP_ENDIAN_BIG; + + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", + "FlexSPI", &res_regs); + if (ret) { + debug("Error: can't get regs base addresses(ret = %d)!\n", ret); + return -ENOMEM; + } + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", + "FlexSPI-memory", &res_mem); + if (ret) { + debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret); + return -ENOMEM; + } + + /* Count flash numbers */ + fdt_for_each_subnode(subnode, blob, node) + ++flash_num; + + if (flash_num == 0) { + debug("Error: Missing flashes!\n"); + return -ENODEV; + } + + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + FSL_FSPI_DEFAULT_SCK_FREQ); + plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs", + FSL_FSPI_MAX_CHIPSELECT_NUM); + + plat->reg_base = res_regs.start; + plat->amba_base = 0; + plat->amba_total_size = res_mem.end - res_mem.start + 1; + plat->flash_num = flash_num; + + debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n", + __func__, + plat->reg_base, + plat->amba_base, + plat->amba_total_size, + plat->speed_hz, + plat->flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le" + ); + + return 0; +} + +static int fsl_fspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct fsl_fspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + return fspi_xfer(priv, bitlen, dout, din, flags); +} + +static int fsl_fspi_claim_bus(struct udevice *dev) +{ + struct fsl_fspi_priv *priv; + struct udevice *bus; + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + bus = dev->parent; + priv = dev_get_priv(bus); + + priv->cur_amba_base = + priv->amba_base[0] + FSL_FSPI_FLASH_SIZE * slave_plat->cs; + + return 0; +} + +static int fsl_fspi_release_bus(struct udevice *dev) +{ + return 0; +} + +static int fsl_fspi_set_speed(struct udevice *bus, uint speed) +{ + /* Nothing to do */ + return 0; +} + +static int fsl_fspi_set_mode(struct udevice *bus, uint mode) +{ + /* Nothing to do */ + return 0; +} + +static const struct dm_spi_ops fsl_fspi_ops = { + .claim_bus = fsl_fspi_claim_bus, + .release_bus = fsl_fspi_release_bus, + .xfer = fsl_fspi_xfer, + .set_speed = fsl_fspi_set_speed, + .set_mode = fsl_fspi_set_mode, +}; + +static const struct udevice_id fsl_fspi_ids[] = { + { .compatible = "fsl,imx8qm-flexspi" }, + { } +}; + +U_BOOT_DRIVER(fsl_fspi) = { + .name = "fsl_fspi", + .id = UCLASS_SPI, + .of_match = fsl_fspi_ids, + .ops = &fsl_fspi_ops, + .ofdata_to_platdata = fsl_fspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct fsl_fspi_platdata), + .priv_auto_alloc_size = sizeof(struct fsl_fspi_priv), + .probe = fsl_fspi_probe, + .child_pre_probe = fsl_fspi_child_pre_probe, +}; +#endif diff --git a/drivers/spi/fsl_fspi.h b/drivers/spi/fsl_fspi.h new file mode 100644 index 00000000000..21327362ede --- /dev/null +++ b/drivers/spi/fsl_fspi.h @@ -0,0 +1,353 @@ +/* + * Copyright 2017 NXP + * + * Register definitions for NXP FLEXSPI + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_FSPI_H_ +#define _FSL_FSPI_H_ + +struct fsl_fspi_regs { + u32 mcr0; + u32 mcr1; + u32 mcr2; + u32 ahbcr; + u32 inten; + u32 intr; + u32 lutkey; + u32 lutcr; + u32 ahbrxbuf0cr0; + u32 ahbrxbuf1cr0; + u32 ahbrxbuf2cr0; + u32 ahbrxbuf3cr0; + u32 ahbrxbuf4cr0; + u32 ahbrxbuf5cr0; + u32 ahbrxbuf6cr0; + u32 ahbrxbuf7cr0; + u32 ahbrxbuf0cr1; + u32 ahbrxbuf1cr1; + u32 ahbrxbuf2cr1; + u32 ahbrxbuf3cr1; + u32 ahbrxbuf4cr1; + u32 ahbrxbuf5cr1; + u32 ahbrxbuf6cr1; + u32 ahbrxbuf7cr1; + u32 flsha1cr0; + u32 flsha2cr0; + u32 flshb1cr0; + u32 flshb2cr0; + u32 flsha1cr1; + u32 flsha2cr1; + u32 flshb1cr1; + u32 flshb2cr1; + u32 flsha1cr2; + u32 flsha2cr2; + u32 flshb1cr2; + u32 flshb2cr2; + u32 flshcr3; + u32 flshcr4; + u32 flshcr5; + u32 flshcr6; + u32 ipcr0; + u32 ipcr1; + u32 ipcr2; + u32 ipcr3; + u32 ipcmd; + u32 dlpr; + u32 iprxfcr; + u32 iptxfcr; + u32 dllacr; + u32 dllbcr; + u32 soccr; + u32 misccr2; + u32 misccr3; + u32 misccr4; + u32 misccr5; + u32 misccr6; + u32 sts0; + u32 sts1; + u32 sts2; + u32 ahbspndsts; + u32 iprxfsts; + u32 iptxfsts; + u32 rsvd[2]; + u32 rfdr[32]; + u32 tfdr[32]; + u32 lut[128]; +}; + +/* The registers */ +#define FLEXSPI_MCR0_AHB_TIMEOUT_SHIFT 24 +#define FLEXSPI_MCR0_AHB_TIMEOUT_MASK (0xFF << FLEXSPI_MCR0_IP_TIMOUT_SHIFT) +#define FLEXSPI_MCR0_IP_TIMOEUT_SHIFT 16 +#define FLEXSPI_MCR0_IP_TIMOEUT_MASK (0xFF << FLEXSPI_MCR0_IP_TIMOUT_SHIFT) +#define FLEXSPI_MCR0_TSTMD_SHIFT 15 +#define FLEXSPI_MCR0_TSTMD_MASK (1 << FLEXSPI_MCR0_TSTMD_SHIFT) +#define FLEXSPI_MCR0_LEARN_EN_SHIFT 14 +#define FLEXSPI_MCR0_LEARN_EN_MASK (1 << FLEXSPI_MCR0_DDR_EN_SHIFT) +#define FLEXSPI_MCR0_SCRFRUN_EN_SHIFT 13 +#define FLEXSPI_MCR0_SCRFRUN_EN_MASK (1 << FLEXSPI_MCR0_DDR_EN_SHIFT) +#define FLEXSPI_MCR0_COTCOMB_EN_SHIFT 12 +#define FLEXSPI_MCR0_OCTCOMB_EN_MASK (1 << FLEXSPI_MCR0_OCTCOMB_EN_SHIFT) +#define FLEXSPI_MCR0_HSEN_SHIFT 11 +#define FLEXSPI_MCR0_HSEN_MASK (1 << FLEXSPI_HSEN_SHIFT) +#define FLEXSPI_MCR0_SERCLKDIV_SHIFT 8 +#define FLEXSPI_MCR0_SERCLKDIV_MASK (7 << FLEXSPI_MCR0_SERCLKDIV_SHIFT) +#define FLEXSPI_MCR0_ATDF_EN_SHIFT 7 +#define FLEXSPI_MCR0_ATDF_EN_MASK (1 << FLEXSPI_MCR0_ATDF_EN_SHIFT) +#define FLEXSPI_MCR0_ARDF_EN_SHIFT 6 +#define FLEXSPI_MCR0_ARDF_EN_MASK (1 << FLEXSPI_MCR0_ARDF_EN_SHIFT) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT 4 +#define FLEXSPI_MCR0_RXCLKSRC_MASK (3 << FLEXSPI_MCR0_RXCLKSRC_SHIFT) +#define FLEXSPI_MCR0_END_CFG_SHIFT 2 +#define FLEXSPI_MCR0_END_CFG_MASK (3 << FLEXSPI_MCR0_END_CFG_SHIFT) +#define FLEXSPI_MCR0_MDIS_SHIFT 1 +#define FLEXSPI_MCR0_MDIS_MASK (1 << FLEXSPI_MCR0_MDIS_SHIFT) +#define FLEXSPI_MCR0_SWRST_SHIFT 0 +#define FLEXSPI_MCR0_SWRST_MASK (1 << FLEXSPI_MCR0_SWRST_SHIFT) + +#define FLEXSPI_MCR1_SEQ_TIMEOUT_SHIFT 16 +#define FLEXSPI_MCR1_SEQ_TIMEOUT_MASK (0xFFFF << FLEXSPI_MCR1_SEQ_TIMEOUT_SHIFT) +#define FLEXSPI_MCR1_AHB_TIMEOUT_SHIFT 0 +#define FLEXSPI_MCR1_AHB_TIMEOUT_MASK (0xFFFF << FLEXSPI_MCR1_SEQ_TIMEOUT_SHIFT) + +#define FLEXSPI_MCR2_IDLE_WAIT_SHIFT 24 +#define FLEXSPI_MCR2_IDLE_WAIT_MASK (0xFF << FLEXSPI_MCR2_IDLE_WAIT_SHIFT) +#define FLEXSPI_MCR2_SAMEFLASH_SHIFT 15 +#define FLEXSPI_MCR2_SAMEFLASH_MASK (1 << FLEXSPI_MCR2_SAMEFLASH_SHIFT) +#define FLEXSPI_MCR2_CLRLRPHS_SHIFT 14 +#define FLEXSPI_MCR2_CLRLRPHS_MASK (1 << FLEXSPI_MCR2_CLRLRPHS_SHIFT) +#define FLEXSPI_MCR2_ABRDATSZ_SHIFT 8 +#define FLEXSPI_MCR2_ABRDATSZ_MASK (1 << FLEXSPI_MCR2_ABRDATSZ_SHIFT) +#define FLEXSPI_MCR2_ABRLEARN_SHIFT 7 +#define FLEXSPI_MCR2_ABRLEARN_MASK (1 << FLEXSPI_MCR2_ABRLEARN_SHIFT) +#define FLEXSPI_MCR2_ABR_READ_SHIFT 6 +#define FLEXSPI_MCR2_ABR_READ_MASK (1 << FLEXSPI_MCR2_ABR_READ_SHIFT) +#define FLEXSPI_MCR2_ABRWRITE_SHIFT 5 +#define FLEXSPI_MCR2_ABRWRITE_MASK (1 << FLEXSPI_MCR2_ABRWRITE_SHIFT) +#define FLEXSPI_MCR2_ABRDUMMY_SHIFT 4 +#define FLEXSPI_MCR2_ABRDUMMY_MASK (1 << FLEXSPI_MCR2_ABRDUMMY_SHIFT) +#define FLEXSPI_MCR2_ABR_MODE_SHIFT 3 +#define FLEXSPI_MCR2_ABR_MODE_MASK (1 << FLEXSPI_MCR2_ABR_MODE_SHIFT) +#define FLEXSPI_MCR2_ABRCADDR_SHIFT 2 +#define FLEXSPI_MCR2_ABRCADDR_MASK (1 << FLEXSPI_MCR2_ABRCADDR_SHIFT) +#define FLEXSPI_MCR2_ABRRADDR_SHIFT 1 +#define FLEXSPI_MCR2_ABRRADDR_MASK (1 << FLEXSPI_MCR2_ABRRADDR_SHIFT) +#define FLEXSPI_MCR2_ABR_CMD_SHIFT 0 +#define FLEXSPI_MCR2_ABR_CMD_MASK (1 << FLEXSPI_MCR2_ABR_CMD_SHIFT) + +#define FLEXSPI_AHBCR_PREF_EN_SHIFT 5 +#define FLEXSPI_AHBCR_PREF_EN_MASK (1 << FLEXSPI_AHBCR_PREF_EN_SHIFT) +#define FLEXSPI_AHBCR_BUFF_EN_SHIFT 4 +#define FLEXSPI_AHBCR_BUFF_EN_MASK (1 << FLEXSPI_AHBCR_BUFF_EN_SHIFT) +#define FLEXSPI_AHBCR_CACH_EN_SHIFT 3 +#define FLEXSPI_AHBCR_CACH_EN_MASK (1 << FLEXSPI_AHBCR_CACH_EN_SHIFT) +#define FLEXSPI_AHBCR_CLRTXBUF_SHIFT 2 +#define FLEXSPI_AHBCR_CLRTXBUF_MASK (1 << FLEXSPI_AHBCR_CLRTXBUF_SHIFT) +#define FLEXSPI_AHBCR_CLRRXBUF_SHIFT 1 +#define FLEXSPI_AHBCR_CLRRXBUF_MASK (1 << FLEXSPI_AHBCR_CLRRXBUF_SHIFT) +#define FLEXSPI_AHBCR_PAR_EN_SHIFT 0 +#define FLEXSPI_AHBCR_PAR_EN_MASK (1 << FLEXSPI_AHBCR_PAR_EN_SHIFT) + +#define FLEXSPI_INTEN_SCLKSBWR_SHIFT 9 +#define FLEXSPI_INTEN_SCLKSBWR_MASK (1 << FLEXSPI_INTEN_SCLKSBWR_SHIFT) +#define FLEXSPI_INTEN_SCLKSBRD_SHIFT 8 +#define FLEXSPI_INTEN_SCLKSBRD_MASK (1 << FLEXSPI_INTEN_SCLKSBRD_SHIFT) +#define FLEXSPI_INTEN_DATALRNFL_SHIFT 7 +#define FLEXSPI_INTEN_DATALRNFL_MASK (1 << FLEXSPI_INTEN_DATALRNFL_SHIFT) +#define FLEXSPI_INTEN_IPTXWE_SHIFT 6 +#define FLEXSPI_INTEN_IPTXWE_MASK (1 << FLEXSPI_INTEN_IPTXWE_SHIFT) +#define FLEXSPI_INTEN_IPRXWA_SHIFT 5 +#define FLEXSPI_INTEN_IPRXWA_MASK (1 << FLEXSPI_INTEN_IPRXWA_SHIFT) +#define FLEXSPI_INTEN_AHBCMDERR_SHIFT 4 +#define FLEXSPI_INTEN_AHBCMDERR_MASK (1 << FLEXSPI_INTEN_AHBCMDERR_SHIFT) +#define FLEXSPI_INTEN_IPCMDERR_SHIFT 3 +#define FLEXSPI_INTEN_IPCMDERR_MASK (1 << FLEXSPI_INTEN_IPCMDERR_SHIFT) +#define FLEXSPI_INTEN_AHBCMDGE_SHIFT 2 +#define FLEXSPI_INTEN_AHBCMDGE_MASK (1 << FLEXSPI_INTEN_AHBCMDGE_SHIFT) +#define FLEXSPI_INTEN_IPCMDGE_SHIFT 1 +#define FLEXSPI_INTEN_IPCMDGE_MASK (1 << FLEXSPI_INTEN_IPCMDGE_SHIFT) +#define FLEXSPI_INTEN_IPCMDDONE_SHIFT 0 +#define FLEXSPI_INTEN_IPCMDDONE_MASK (1 << FLEXSPI_INTEN_IPCMDDONE_SHIFT) + +#define FLEXSPI_INTR_SCLKSBWR_SHIFT 9 +#define FLEXSPI_INTR_SCLKSBWR_MASK (1 << FLEXSPI_INTR_SCLKSBWR_SHIFT) +#define FLEXSPI_INTR_SCLKSBRD_SHIFT 8 +#define FLEXSPI_INTR_SCLKSBRD_MASK (1 << FLEXSPI_INTR_SCLKSBRD_SHIFT) +#define FLEXSPI_INTR_DATALRNFL_SHIFT 7 +#define FLEXSPI_INTR_DATALRNFL_MASK (1 << FLEXSPI_INTR_DATALRNFL_SHIFT) +#define FLEXSPI_INTR_IPTXWE_SHIFT 6 +#define FLEXSPI_INTR_IPTXWE_MASK (1 << FLEXSPI_INTR_IPTXWE_SHIFT) +#define FLEXSPI_INTR_IPRXWA_SHIFT 5 +#define FLEXSPI_INTR_IPRXWA_MASK (1 << FLEXSPI_INTR_IPRXWA_SHIFT) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT 4 +#define FLEXSPI_INTR_AHBCMDERR_MASK (1 << FLEXSPI_INTR_AHBCMDERR_SHIFT) +#define FLEXSPI_INTR_IPCMDERR_SHIFT 3 +#define FLEXSPI_INTR_IPCMDERR_MASK (1 << FLEXSPI_INTR_IPCMDERR_SHIFT) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT 2 +#define FLEXSPI_INTR_AHBCMDGE_MASK (1 << FLEXSPI_INTR_AHBCMDGE_SHIFT) +#define FLEXSPI_INTR_IPCMDGE_SHIFT 1 +#define FLEXSPI_INTR_IPCMDGE_MASK (1 << FLEXSPI_INTR_IPCMDGE_SHIFT) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT 0 +#define FLEXSPI_INTR_IPCMDDONE_MASK (1 << FLEXSPI_INTR_IPCMDDONE_SHIFT) + +#define FLEXSPI_LUTKEY_VALUE 0x5AF05AF0 + +#define FLEXSPI_LCKER_LOCK 0x1 +#define FLEXSPI_LCKER_UNLOCK 0x2 + +#define FLEXSPI_BUFXCR_INVALID_MSTRID 0xe +#define FLEXSPI_AHBRXBUF0CR7_PREF_SHIFT 31 +#define FLEXSPI_AHBRXBUF0CR7_PREF_MASK (1 << FLEXSPI_AHBRXBUF0CR7_PREF_SHIFT) + +#define FLEXSPI_BUFXCR1_MSID_SHIFT 0 +#define FLEXSPI_BUFXCR1_MSID_MASK (0xF << FLEXSPI_BUFXCR1_MSID_SHIFT) +#define FLEXSPI_BUFXCR1_PRIO_SHIFT 8 +#define FLEXSPI_BUFXCR1_PRIO_MASK (0x7 << FLEXSPI_BUFXCR1_PRIO_SHIFT) + +#define FLEXSPI_FLSHXCR0_SZ_SHIFT 10 +#define FLEXSPI_FLSHXCR0_SZ_MASK (0x3FFFFF << FLEXSPI_FLSHXCR0_SZ_SHIFT) + +#define FLEXSPI_FLSHXCR1_CSINTR_SHIFT 16 +#define FLEXSPI_FLSHXCR1_CSINTR_MASK (0xFFFF << FLEXSPI_FLSHXCR0_CSINTR_SHIFT) +#define FLEXSPI_FLSHXCR1_CAS_SHIFT 11 +#define FLEXSPI_FLSHXCR1_CAS_MASK (0xF << FLEXSPI_FLSHXCR0_CAS_SHIFT) +#define FLEXSPI_FLSHXCR1_WA_SHIFT 10 +#define FLEXSPI_FLSHXCR1_WA_MASK (1 << FLEXSPI_FLSHXCR0_WA_SHIFT) +#define FLEXSPI_FLSHXCR1_TCSH_SHIFT 5 +#define FLEXSPI_FLSHXCR1_TCSH_MASK (0x1F << FLEXSPI_FLSHXCR0_TCSH_SHIFT) +#define FLEXSPI_FLSHXCR1_TCSS_SHIFT 0 +#define FLEXSPI_FLSHXCR1_TCSS_MASK (0x1F << FLEXSPI_FLSHXCR0_TCSS_SHIFT) + +#define FLEXSPI_FLSHXCR2_CLRINSP_SHIFT 24 +#define FLEXSPI_FLSHXCR2_CLRINSP_MASK (1 << FLEXSPI_FLSHXCR2_CLRINSP_SHIFT) +#define FLEXSPI_FLSHXCR2_AWRWAIT_SHIFT 16 +#define FLEXSPI_FLSHXCR2_AWRWAIT_MASK (0xFF << FLEXSPI_FLSHXCR2_AWRWAIT_SHIFT) +#define FLEXSPI_FLSHXCR2_AWRSEQN_SHIFT 13 +#define FLEXSPI_FLSHXCR2_AWRSEQN_MASK (0x7 << FLEXSPI_FLSHXCR2_AWRSEQN_SHIFT) +#define FLEXSPI_FLSHXCR2_AWRSEQI_SHIFT 8 +#define FLEXSPI_FLSHXCR2_AWRSEQI_MASK (0xF << FLEXSPI_FLSHXCR2_AWRSEQI_SHIFT) +#define FLEXSPI_FLSHXCR2_ARDSEQN_SHIFT 5 +#define FLEXSPI_FLSHXCR2_ARDSEQN_MASK (0x7 << FLEXSPI_FLSHXCR2_ARDSEQN_SHIFT) +#define FLEXSPI_FLSHXCR2_ARDSEQI_SHIFT 0 +#define FLEXSPI_FLSHXCR2_ARDSEQI_MASK (0xF << FLEXSPI_FLSHXCR2_ARDSEQI_SHIFT) + + +#define FLEXSPI_IPCR1_IPAREN_SHIFT 31 +#define FLEXSPI_IPCR1_IPAREN_MASK (1 << FLEXSPI_IPCR1_IPAREN_SHIFT) +#define FLEXSPI_IPCR1_SEQNUM_SHIFT 24 +#define FLEXSPI_IPCR1_SEQNUM_MASK (0xF << FLEXSPI_IPCR1_SEQNUM_SHIFT) +#define FLEXSPI_IPCR1_SEQID_SHIFT 16 +#define FLEXSPI_IPCR1_SEQID_MASK (0xF << FLEXSPI_IPCR1_SEQID_SHIFT) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT 0 +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFF << FLEXSPI_IPCR1_IDATSZ_SHIFT) + +#define FLEXSPI_IPCMD_TRG_SHIFT 0 +#define FLEXSPI_IPCMD_TRG_MASK (1 << FLEXSPI_IPCMD_TRG_SHIFT) + +#define FLEXSPI_IPRXFCR_CLR_SHIFT 0 +#define FLEXSPI_IPRXFCR_CLR_MASK (1 << FLEXSPI_IPRXFCR_CLR_SHIFT) +#define FLEXSPI_IPRXFCR_DMA_EN_SHIFT 1 +#define FLEXSPI_IPRXFCR_DMA_EN_MASK (1 << FLEXSPI_IPRXFCR_DMA_EN_SHIFT) +#define FLEXSPI_IPRXFCR_WMRK_SHIFT 2 +#define FLEXSPI_IPRXFCR_WMRK_MASK (0x1F << FLEXSPI_IPRXFCR_WMRK_SHIFT) + +#define FLEXSPI_IPTXFCR_CLR_SHIFT 0 +#define FLEXSPI_IPTXFCR_CLR_MASK (1 << FLEXSPI_IPTXFCR_CLR_SHIFT) +#define FLEXSPI_IPTXFCR_DMA_EN_SHIFT 1 +#define FLEXSPI_IPTXFCR_DMA_EN_MASK (1 << FLEXSPI_IPTXFCR_DMA_EN_SHIFT) +#define FLEXSPI_IPTXFCR_WMRK_SHIFT 2 +#define FLEXSPI_IPTXFCR_WMRK_MASK (0x1F << FLEXSPI_IPTXFCR_WMRK_SHIFT) + +#define FLEXSPI_STS0_DLPHA_SHIFT 9 +#define FLEXSPI_STS0_DLPHA_MASK (0x1F << FLEXSPI_STS0_DLPHA_SHIFT) +#define FLEXSPI_STS0_DLPHB_SHIFT 4 +#define FLEXSPI_STS0_DLPHB_MASK (0x1F << FLEXSPI_STS0_DLPHB_SHIFT) +#define FLEXSPI_STS0_CMD_SRC_SHIFT 2 +#define FLEXSPI_STS0_CMD_SRC_MASK (3 << FLEXSPI_STS0_CMD_SRC_SHIFT) +#define FLEXSPI_STS0_ARB_BUSY_SHIFT 1 +#define FLEXSPI_STS0_ARB_BUSY_MASK (1 << FLEXSPI_STS0_ARB_BUSY_SHIFT) +#define FLEXSPI_STS0_SEQ_BUSY_SHIFT 0 +#define FLEXSPI_STS0_SEQ_BUSY_MASK (1 << FLEXSPI_STS0_SEQ_BUSY_SHIFT) + +#define FLEXSPI_STS1_IP_ERRCD_SHIFT 24 +#define FLEXSPI_STS1_IP_ERRCD_MASK (0xF << FLEXSPI_STS1_IP_ERRCD_SHIFT) +#define FLEXSPI_STS1_IP_ERRID_SHIFT 16 +#define FLEXSPI_STS1_IP_ERRID_MASK (0xF << FLEXSPI_STS1_IP_ERRID_SHIFT) +#define FLEXSPI_STS1_AHB_ERRCD_SHIFT 8 +#define FLEXSPI_STS1_AHB_ERRCD_MASK (0xF << FLEXSPI_STS1_AHB_ERRCD_SHIFT) +#define FLEXSPI_STS1_AHB_ERRID_SHIFT 0 +#define FLEXSPI_STS1_AHB_ERRID_MASK (0xF << FLEXSPI_STS1_AHB_ERRID_SHIFT) + +#define FLEXSPI_AHBSPNST_DATLFT_SHIFT 16 +#define FLEXSPI_AHBSPNST_DATLFT_MASK (0xFFFF << FLEXSPI_AHBSPNST_DATLFT_SHIFT) +#define FLEXSPI_AHBSPNST_BUFID_SHIFT 1 +#define FLEXSPI_AHBSPNST_BUFID_MASK (7 << FLEXSPI_AHBSPNST_BUFID_SHIFT) +#define FLEXSPI_AHBSPNST_ACTIVE_SHIFT 0 +#define FLEXSPI_AHBSPNST_ACTIVE_MASK (1 << FLEXSPI_AHBSPNST_ACTIVE_SHIFT) + +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT 16 +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT 0 +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFF << FLEXSPI_IPRXFSTS_FILL_SHIFT) + +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT 16 +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT 0 +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFF << FLEXSPI_IPTXFSTS_FILL_SHIFT) + +/* register map end */ + +#define OPRND0_SHIFT 0 +#define OPRND0(x) ((x) << OPRND0_SHIFT) +#define PAD0_SHIFT 8 +#define PAD0(x) ((x) << PAD0_SHIFT) +#define INSTR0_SHIFT 10 +#define INSTR0(x) ((x) << INSTR0_SHIFT) +#define OPRND1_SHIFT 16 +#define OPRND1(x) ((x) << OPRND1_SHIFT) +#define PAD1_SHIFT 24 +#define PAD1(x) ((x) << PAD1_SHIFT) +#define INSTR1_SHIFT 26 +#define INSTR1(x) ((x) << INSTR1_SHIFT) + +#define LUT_STOP 0x00 +#define LUT_CMD 0x01 +#define LUT_ADDR 0x02 +#define LUT_CADDR_SDR 0x03 +#define LUT_MODE 0x04 +#define LUT_MODE2 0x05 +#define LUT_MODE4 0x06 +#define LUT_MODE8 0x07 +#define LUT_WRITE 0x08 +#define LUT_READ 0x09 +#define LUT_LEARN_SDR 0x0A +#define LUT_DATSZ_SDR 0x0B +#define LUT_DUMMY 0x0C +#define LUT_DUMMY_RWDS_SDR 0x0D +#define LUT_JMP_ON_CS 0x1F +#define LUT_CMD_DDR 0x21 +#define LUT_ADDR_DDR 0x22 +#define LUT_CADDR_DDR 0x23 +#define LUT_MODE_DDR 0x24 +#define LUT_MODE2_DDR 0x25 +#define LUT_MODE4_DDR 0x26 +#define LUT_MODE8_DDR 0x27 +#define LUT_WRITE_DDR 0x28 +#define LUT_READ_DDR 0x29 +#define LUT_LEARN_DDR 0x2A +#define LUT_DATSZ_DDR 0x2B +#define LUT_DUMMY_DDR 0x2C +#define LUT_DUMMY_RWDS_DDR 0x2D + +#define LUT_PAD1 0 +#define LUT_PAD2 1 +#define LUT_PAD4 2 +#define LUT_PAD8 3 + +#define ADDR24BIT 0x18 +#define ADDR32BIT 0x20 + +#endif /* _FSL_FSPI_H_ */ diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 5dc69a68657..939956bcc30 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -16,12 +16,13 @@ #include #include #include "fsl_qspi.h" +#include DECLARE_GLOBAL_DATA_PTR; #define RX_BUFFER_SIZE 0x80 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D) + defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D) || defined(CONFIG_IMX8M) #define TX_BUFFER_SIZE 0x200 #else #define TX_BUFFER_SIZE 0x40 @@ -48,6 +49,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif #define SEQID_WRAR 13 #define SEQID_RDAR 14 +#define SEQID_RDFSR 15 /* QSPI CMD */ #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ @@ -58,6 +60,7 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ #define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */ +#define QSPI_CMD_FLAG_SR 0x70 /* Read FLAG STATUS*/ /* Used for Micron, winbond and Macronix flashes */ #define QSPI_CMD_WREAR 0xc5 /* EAR register write */ @@ -220,6 +223,15 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv) qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + /* Read Flag Status */ + lut_base = SEQID_RDFSR * 4; + qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_FLAG_SR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + /* Erase a sector */ lut_base = SEQID_SE * 4; #ifdef CONFIG_SPI_FLASH_BAR @@ -270,7 +282,7 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv) PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #endif #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D) + defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D) || defined(CONFIG_IMX8M) /* * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly. * So, Use IDATSZ in IPCR to determine the size and here set 0. @@ -395,7 +407,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr); /* Read out the data directly from the AHB buffer. */ @@ -404,6 +416,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) qspi_write32(priv->flags, ®s->mcr, mcr_reg); } +#ifndef CONFIG_MX7ULP static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) { u32 reg, reg2; @@ -425,7 +438,14 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) reg |= BIT(29); qspi_write32(priv->flags, ®s->mcr, reg); + + /* Enable the TDH to 1 for i.mx6ul and mx7d, it is reserved on other platforms */ + reg = qspi_read32(priv->flags, ®s->flshcr); + reg &= ~(BIT(17)); + reg |= BIT(16); + qspi_write32(priv->flags, ®s->flshcr, reg); } +#endif /* * There are two different ways to read out the data from the flash: @@ -448,8 +468,13 @@ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv) qspi_write32(priv->flags, ®s->buf0cr, QSPI_BUFXCR_INVALID_MSTRID); qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID); qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID); +#ifdef CONFIG_MX7ULP + qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK | + (0x10 << QSPI_BUF3CR_ADATSZ_SHIFT)); +#else qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK | (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT)); +#endif /* We only use the buffer3 */ qspi_write32(priv->flags, ®s->buf0ind, 0); @@ -463,8 +488,10 @@ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv) qspi_write32(priv->flags, ®s->bfgencr, SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT); +#ifndef CONFIG_MX7ULP /*Enable DDR Mode*/ qspi_enable_ddr_mode(priv); +#endif } #endif @@ -478,7 +505,7 @@ static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); @@ -523,7 +550,7 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); @@ -569,7 +596,7 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); to_or_from = priv->sf_addr + priv->cur_amba_base; @@ -621,7 +648,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); status_reg = 0; @@ -696,7 +723,7 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); @@ -724,6 +751,40 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) qspi_write32(priv->flags, ®s->mcr, mcr_reg); } +static void qspi_op_rdfsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) +{ + struct fsl_qspi_regs *regs = priv->regs; + u32 mcr_reg, reg, data; + + mcr_reg = qspi_read32(priv->flags, ®s->mcr); + qspi_write32(priv->flags, ®s->mcr, + QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + mcr_reg); + qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); + + qspi_write32(priv->flags, ®s->ipcr, + (SEQID_RDFSR << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) + ; + + while (1) { + reg = qspi_read32(priv->flags, ®s->rbsr); + if (reg & QSPI_RBSR_RDBFL_MASK) { + data = qspi_read32(priv->flags, ®s->rbdr[0]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, len); + qspi_write32(priv->flags, ®s->mcr, + qspi_read32(priv->flags, ®s->mcr) | + QSPI_MCR_CLR_RXF_MASK); + break; + } + } + + qspi_write32(priv->flags, ®s->mcr, mcr_reg); +} + static void qspi_op_erase(struct fsl_qspi_priv *priv) { struct fsl_qspi_regs *regs = priv->regs; @@ -733,7 +794,7 @@ static void qspi_op_erase(struct fsl_qspi_priv *priv) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); to_or_from = priv->sf_addr + priv->cur_amba_base; @@ -809,6 +870,8 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, qspi_op_rdid(priv, din, bytes); else if (priv->cur_seqid == QSPI_CMD_RDSR) qspi_op_rdsr(priv, din, bytes); + else if (priv->cur_seqid == QSPI_CMD_FLAG_SR) + qspi_op_rdfsr(priv, din, bytes); #ifdef CONFIG_SPI_FLASH_BAR else if ((priv->cur_seqid == QSPI_CMD_BRRD) || (priv->cur_seqid == QSPI_CMD_RDEAR)) { @@ -882,6 +945,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (bus >= ARRAY_SIZE(spi_bases)) return NULL; +#ifdef CONFIG_MX6 + if (mx6_qspi_fused(spi_bases[bus])) { + printf("QSPI@0x%lx is fused, disable it\n", spi_bases[bus]); + return NULL; + } +#endif + if (cs >= FSL_QSPI_FLASH_NUM) return NULL; @@ -909,7 +979,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr); /* Set endianness to LE for i.mx */ - if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)) + if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7) || IS_ENABLED(CONFIG_MX7ULP)) mcr_val = QSPI_MCR_END_CFD_LE; qspi_write32(qspi->priv.flags, ®s->mcr, @@ -921,6 +991,18 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; + +#if defined(CONFIG_MX7ULP) + /* + * mx7ulp QSPI controller does not support parallel mode, it only has port A. + * To support dual die flash and single die flash, we set flash 1 size to CS0 area, + * set flash2 size to CS1 area. + */ + qspi_write32(qspi->priv.flags, ®s->sfa1ad, + FSL_QSPI_FLASH_SIZE | amba_bases[bus]); + qspi_write32(qspi->priv.flags, ®s->sfa2ad, + total_size | amba_bases[bus]); +#else /* * Any read access to non-implemented addresses will provide * undefined results. @@ -939,6 +1021,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, total_size | amba_bases[bus]); qspi_write32(qspi->priv.flags, ®s->sfb2ad, total_size | amba_bases[bus]); +#endif qspi_set_lut(&qspi->priv); @@ -999,6 +1082,13 @@ static int fsl_qspi_probe(struct udevice *bus) struct dm_spi_bus *dm_spi_bus; int i, ret; +#ifdef CONFIG_MX6 + if (mx6_qspi_fused(plat->reg_base)) { + printf("QSPI@0x%lx is fused, disable it\n", plat->reg_base); + return -ENODEV; + } +#endif + dm_spi_bus = bus->uclass_priv; dm_spi_bus->max_hz = plat->speed_hz; @@ -1032,7 +1122,7 @@ static int fsl_qspi_probe(struct udevice *bus) mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); /* Set endianness to LE for i.mx */ - if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)) + if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7) || IS_ENABLED(CONFIG_MX7ULP)) mcr_val = QSPI_MCR_END_CFD_LE; qspi_write32(priv->flags, &priv->regs->mcr, @@ -1241,6 +1331,7 @@ static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,imx6sx-qspi" }, { .compatible = "fsl,imx6ul-qspi" }, { .compatible = "fsl,imx7d-qspi" }, + { .compatible = "fsl,imx7ulp-qspi" }, { } }; diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 41f0cfcd6b7..1af2b6bd37e 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -1,6 +1,8 @@ /* * Copyright (C) 2008, Guennadi Liakhovetski * + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,6 +16,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -225,8 +228,8 @@ int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen, u32 ts; int status; - debug("%s: bitlen %d dout 0x%x din 0x%x\n", - __func__, bitlen, (u32)dout, (u32)din); + debug("%s: bitlen %d dout 0x%lx din 0x%lx\n", + __func__, bitlen, (ulong)dout, (ulong)din); mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | @@ -450,6 +453,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } +#ifdef CONFIG_MX6 + if (mx6_ecspi_fused(spi_bases[bus])) { + printf("ECSPI@0x%lx is fused, disable it\n", spi_bases[bus]); + return NULL; + } +#endif + mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); if (!mxcs) { puts("mxc_spi: SPI Slave not allocated !\n"); @@ -505,7 +515,7 @@ static int mxc_spi_probe(struct udevice *bus) return -EINVAL; } - plat->base = dev_get_addr(bus); + plat->base = devfdt_get_addr(bus); if (plat->base == FDT_ADDR_T_NONE) return -ENODEV; diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index a71b9be5fb5..985fd911797 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -17,10 +17,28 @@ config IMX_THERMAL cpufreq is used as the cooling device to throttle CPUs when the passive trip is crossed. +config IMX_SC_THERMAL + bool "Temperature sensor driver for NXP i.MX8 QM/QXP" + depends on ARCH_IMX8 + help + Support for Temperature sensors on Freescale i.MX8 QM/QXP. + It supports one critical trip point and one passive trip point. The + boot is hold to the cool device to throttle CPUs when the passive trip + is crossed + config TI_DRA7_THERMAL bool "Temperature sensor driver for TI dra7xx SOCs" help Enable thermal support for for the Texas Instruments DRA752 SoC family. The driver supports reading CPU temperature. +config NXP_TMU + bool "Thermal Management Unit driver for NXP i.MX8M" + depends on ARCH_IMX8M + help + Support for Temperature sensors on NXP i.MX8M. + It supports one critical trip point and one passive trip point. The + boot is hold to the cool device to throttle CPUs when the passive trip + is crossed + endif # if DM_THERMAL diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index f6271a533bc..27ef3915b13 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -7,4 +7,6 @@ obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o +obj-$(CONFIG_IMX_SC_THERMAL) += imx_sc_thermal.o obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o +obj-$(CONFIG_NXP_TMU) += nxp_tmu.o diff --git a/drivers/thermal/imx_sc_thermal.c b/drivers/thermal/imx_sc_thermal.c new file mode 100644 index 00000000000..7a5dfa35a05 --- /dev/null +++ b/drivers/thermal/imx_sc_thermal.c @@ -0,0 +1,205 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct imx_sc_thermal_plat { + int critical; + int alert; + int polling_delay; + int id; + bool zone_node; +}; + +static int read_temperature(struct udevice *dev, int *temp) +{ + sc_err_t sciErr; + int16_t celsius; + int8_t tenths; + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + + sc_rsrc_t *sensor_rsrc = + (sc_rsrc_t *)dev_get_driver_data(dev); + + struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); + + if (!temp) + return -EINVAL; + + sciErr = sc_misc_get_temp(ipcHndl, sensor_rsrc[pdata->id], SC_C_TEMP, &celsius, &tenths); + if (sciErr) { + printf("Error: get temperature failed! (error = %d)\n", sciErr); + return -EIO; + } + + *temp = celsius * 1000 + tenths * 100; + + return 0; +} + +int imx_sc_thermal_get_temp(struct udevice *dev, int *temp) +{ + struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); + int cpu_tmp = 0; + int ret; + + ret = read_temperature(dev, &cpu_tmp); + if (ret) + return ret; + + while (cpu_tmp >= pdata->alert) { + printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)", + cpu_tmp, pdata->alert, pdata->critical); + puts(" waiting...\n"); + mdelay(pdata->polling_delay); + ret = read_temperature(dev, &cpu_tmp); + if (ret) + return ret; + } + + *temp = cpu_tmp / 1000; + + return 0; +} + +static const struct dm_thermal_ops imx_sc_thermal_ops = { + .get_temp = imx_sc_thermal_get_temp, +}; + +static int imx_sc_thermal_probe(struct udevice *dev) +{ + debug("%s dev name %s\n", __func__, dev->name); + return 0; +} + +static int imx_sc_thermal_bind(struct udevice *dev) +{ + int reg, ret; + int offset; + const char *name; + const void *prop; + + struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); + + debug("%s dev name %s\n", __func__, dev->name); + + prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "compatible", NULL); + if (!prop) + return 0; + else + pdata->zone_node = 1; + + reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "tsens-num", 0); + if (reg == 0) { + printf("%s: no temp sensor number provided!\n", __func__); + return -EINVAL; + } + + offset = fdt_subnode_offset(gd->fdt_blob, 0, "thermal-zones"); + fdt_for_each_subnode(offset, gd->fdt_blob, offset) { + /* Bind the subnode to this driver */ + name = fdt_get_name(gd->fdt_blob, offset, NULL); + + ret = device_bind_with_driver_data(dev, dev->driver, name, + dev->driver_data, offset_to_ofnode(offset), NULL); + if (ret) + printf("Error binding driver '%s': %d\n", dev->driver->name, + ret); + } + return 0; +} + +static int imx_sc_thermal_ofdata_to_platdata(struct udevice *dev) +{ + int ret; + int trips_np; + + struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); + struct fdtdec_phandle_args args; + + debug("%s dev name %s\n", __func__, dev->name); + + if (pdata->zone_node) + return 0; + + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev), "thermal-sensors", + "#thermal-sensor-cells", + 0, 0, &args); + if (ret) + return ret; + + if (args.node != dev_of_offset(dev->parent)) + return -EFAULT; + + if (args.args_count >= 1) + pdata->id = args.args[0]; + else + pdata->id = 0; + + debug("args.args_count %d, id %d\n", args.args_count, pdata->id); + + pdata->polling_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "polling-delay", 1000); + + trips_np = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev), "trips"); + fdt_for_each_subnode(trips_np, gd->fdt_blob, trips_np) { + const char *type; + type = fdt_getprop(gd->fdt_blob, trips_np, "type", NULL); + if (type) { + if (strcmp(type, "critical") == 0) + pdata->critical = fdtdec_get_int(gd->fdt_blob, trips_np, "temperature", 85); + else if (strcmp(type, "passive") == 0) + pdata->alert = fdtdec_get_int(gd->fdt_blob, trips_np, "temperature", 80); + } + } + + debug("id %d polling_delay %d, critical %d, alert %d\n", + pdata->id, pdata->polling_delay, pdata->critical, pdata->alert); + + return 0; +} + +static const sc_rsrc_t imx8qm_sensor_rsrc[] = { + SC_R_A53, SC_R_A72, SC_R_GPU_0_PID0, SC_R_GPU_1_PID0, + SC_R_DRC_0, SC_R_DRC_1, SC_R_VPU_PID0, SC_R_PMIC_0, + SC_R_PMIC_1, SC_R_PMIC_2, +}; + +static const sc_rsrc_t imx8qxp_sensor_rsrc[] = { + SC_R_SYSTEM, SC_R_DRC_0, SC_R_PMIC_0, + SC_R_PMIC_1, SC_R_PMIC_2, +}; + +static const struct udevice_id imx_sc_thermal_ids[] = { + { .compatible = "nxp,imx8qm-sc-tsens", .data = (ulong)&imx8qm_sensor_rsrc, }, + { .compatible = "nxp,imx8qxp-sc-tsens", .data = (ulong)&imx8qxp_sensor_rsrc, }, + { } +}; + +U_BOOT_DRIVER(imx_sc_thermal) = { + .name = "imx_sc_thermal", + .id = UCLASS_THERMAL, + .ops = &imx_sc_thermal_ops, + .of_match = imx_sc_thermal_ids, + .bind = imx_sc_thermal_bind, + .probe = imx_sc_thermal_probe, + .ofdata_to_platdata = imx_sc_thermal_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct imx_sc_thermal_plat), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/thermal/nxp_tmu.c b/drivers/thermal/nxp_tmu.c new file mode 100644 index 00000000000..c170c9857bd --- /dev/null +++ b/drivers/thermal/nxp_tmu.c @@ -0,0 +1,407 @@ +/* + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SITES_MAX 16 +#define FLAGS_VER2 0x1 + +#define TMR_DISABLE 0x0 +#define TMR_ME 0x80000000 +#define TMR_ALPF 0x0c000000 +#define TMTMIR_DEFAULT 0x00000002 +#define TIER_DISABLE 0x0 + +#define TER_EN 0x80000000 +#define TER_ALPF 0x3 + +/* + * NXP TMU Registers + */ +struct nxp_tmu_site_regs { + u32 tritsr; /* Immediate Temperature Site Register */ + u32 tratsr; /* Average Temperature Site Register */ + u8 res0[0x8]; +}; + +struct nxp_tmu_regs { + u32 tmr; /* Mode Register */ + u32 tsr; /* Status Register */ + u32 tmtmir; /* Temperature measurement interval Register */ + u8 res0[0x14]; + u32 tier; /* Interrupt Enable Register */ + u32 tidr; /* Interrupt Detect Register */ + u32 tiscr; /* Interrupt Site Capture Register */ + u32 ticscr; /* Interrupt Critical Site Capture Register */ + u8 res1[0x10]; + u32 tmhtcrh; /* High Temperature Capture Register */ + u32 tmhtcrl; /* Low Temperature Capture Register */ + u8 res2[0x8]; + u32 tmhtitr; /* High Temperature Immediate Threshold */ + u32 tmhtatr; /* High Temperature Average Threshold */ + u32 tmhtactr; /* High Temperature Average Crit Threshold */ + u8 res3[0x24]; + u32 ttcfgr; /* Temperature Configuration Register */ + u32 tscfgr; /* Sensor Configuration Register */ + u8 res4[0x78]; + struct nxp_tmu_site_regs site[SITES_MAX]; + u8 res5[0x9f8]; + u32 ipbrr0; /* IP Block Revision Register 0 */ + u32 ipbrr1; /* IP Block Revision Register 1 */ + u8 res6[0x310]; + u32 ttr0cr; /* Temperature Range 0 Control Register */ + u32 ttr1cr; /* Temperature Range 1 Control Register */ + u32 ttr2cr; /* Temperature Range 2 Control Register */ + u32 ttr3cr; /* Temperature Range 3 Control Register */ +}; + +struct nxp_tmu_regs_v2 { + u32 ter; /* TMU enable Register */ + u32 tsr; /* Status Register */ + u32 tier; /* Interrupt enable register */ + u32 tidr; /* Interrupt detect register */ + u32 tmhtitr; /* Monitor high temperature immediate threshold register */ + u32 tmhtatr; /* Monitor high temperature average threshold register */ + u32 tmhtactr; /* TMU monitor high temperature average critical threshold register */ + u32 tscr; /* Sensor value capture register */ + u32 tritsr; /* Report immediate temperature site register 0 */ + u32 tratsr; /* Report average temperature site register 0 */ + u32 tasr; /* Amplifier setting register */ + u32 ttmc; /* Test MUX control */ + u32 tcaliv; +}; + +union tmu_regs { + struct nxp_tmu_regs regs_v1; + struct nxp_tmu_regs_v2 regs_v2; +}; + +struct nxp_tmu_plat { + int critical; + int alert; + int polling_delay; + int id; + bool zone_node; + union tmu_regs *regs; +}; + +static int read_temperature(struct udevice *dev, int *temp) +{ + struct nxp_tmu_plat *pdata = dev_get_platdata(dev); + ulong drv_data = dev_get_driver_data(dev); + u32 val; + u32 retry = 10; + u32 valid = 0; + + do { + mdelay(100); + retry--; + + if (drv_data & FLAGS_VER2) { + val = readl(&pdata->regs->regs_v2.tritsr); + + /* Check if TEMP is in valid range, the V bit in TRITSR + * only reflects the RAW uncalibrated data + */ + valid = ((val & 0xff) < 10 || (val & 0xff) > 125) ? 0 : 1; + } else { + val = readl(&pdata->regs->regs_v1.site[pdata->id].tritsr); + valid = val & 0x80000000; + } + } while (!valid && retry > 0); + + if (retry > 0) { + *temp = (val & 0xff) * 1000; + return 0; + } else { + return -EINVAL; + } +} + +int nxp_tmu_get_temp(struct udevice *dev, int *temp) +{ + struct nxp_tmu_plat *pdata = dev_get_platdata(dev); + int cpu_tmp = 0; + int ret; + + ret = read_temperature(dev, &cpu_tmp); + if (ret) { + printf("invalid data\n"); + return ret; + } + + while (cpu_tmp >= pdata->alert) { + printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)", + cpu_tmp, pdata->alert, pdata->critical); + puts(" waiting...\n"); + mdelay(pdata->polling_delay); + ret = read_temperature(dev, &cpu_tmp); + if (ret) { + printf("invalid data\n"); + return ret; + } + } + + *temp = cpu_tmp / 1000; + + return 0; +} + +static const struct dm_thermal_ops nxp_tmu_ops = { + .get_temp = nxp_tmu_get_temp, +}; + +static int nxp_tmu_calibration(struct udevice *dev) +{ + int i, val, len, ret; + u32 range[4]; + const fdt32_t *calibration; + struct nxp_tmu_plat *pdata = dev_get_platdata(dev); + ulong drv_data = dev_get_driver_data(dev); + + debug("%s\n", __func__); + + if (drv_data & FLAGS_VER2) + return 0; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), + "fsl,tmu-range", range, 4); + if (ret) { + printf("TMU: missing calibration range, ret = %d.\n", ret); + return ret; + } + + /* Init temperature range registers */ + writel(range[0], &pdata->regs->regs_v1.ttr0cr); + writel(range[1], &pdata->regs->regs_v1.ttr1cr); + writel(range[2], &pdata->regs->regs_v1.ttr2cr); + writel(range[3], &pdata->regs->regs_v1.ttr3cr); + + calibration = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), + "fsl,tmu-calibration", &len); + if (calibration == NULL || len % 8) { + printf("TMU: invalid calibration data.\n"); + return -ENODEV; + } + + for (i = 0; i < len; i += 8, calibration += 2) { + val = fdt32_to_cpu(*calibration); + writel(val, &pdata->regs->regs_v1.ttcfgr); + val = fdt32_to_cpu(*(calibration + 1)); + writel(val, &pdata->regs->regs_v1.tscfgr); + } + + return 0; +} + +void __weak nxp_tmu_arch_init(void *reg_base) +{ + return; +} + +static void nxp_tmu_init(struct udevice *dev) +{ + struct nxp_tmu_plat *pdata = dev_get_platdata(dev); + ulong drv_data = dev_get_driver_data(dev); + + debug("%s\n", __func__); + + if (drv_data & FLAGS_VER2) { + /* Disable monitoring */ + writel(0x0, &pdata->regs->regs_v2.ter); + + /* Disable interrupt, using polling instead */ + writel(0x0, &pdata->regs->regs_v2.tier); + } else { + /* Disable monitoring */ + writel(TMR_DISABLE, &pdata->regs->regs_v1.tmr); + + /* Disable interrupt, using polling instead */ + writel(TIER_DISABLE, &pdata->regs->regs_v1.tier); + + /* Set update_interval */ + writel(TMTMIR_DEFAULT, &pdata->regs->regs_v1.tmtmir); + } + + nxp_tmu_arch_init((void *)pdata->regs); +} + +static int nxp_tmu_enable_msite(struct udevice *dev) +{ + struct nxp_tmu_plat *pdata = dev_get_platdata(dev); + ulong drv_data = dev_get_driver_data(dev); + u32 reg; + + debug("%s\n", __func__); + + if (!pdata->regs) + return -EIO; + + if (drv_data & FLAGS_VER2) { + reg = readl(&pdata->regs->regs_v2.ter); + reg &= ~TER_EN; + writel(reg, &pdata->regs->regs_v2.ter); + + reg &= ~TER_ALPF; + reg |= 0x1; + writel(reg, &pdata->regs->regs_v2.ter); + + /* Enable monitor */ + reg |= TER_EN; + writel(reg, &pdata->regs->regs_v2.ter); + } else { + /* Clear the ME before setting MSITE and ALPF*/ + reg = readl(&pdata->regs->regs_v1.tmr); + reg &= ~TMR_ME; + writel(reg, &pdata->regs->regs_v1.tmr); + + reg |= 1 << (15 - pdata->id); + reg |= TMR_ALPF; + writel(reg, &pdata->regs->regs_v1.tmr); + + /* Enable ME */ + reg |= TMR_ME; + writel(reg, &pdata->regs->regs_v1.tmr); + } + + return 0; +} + +static int nxp_tmu_probe(struct udevice *dev) +{ + struct nxp_tmu_plat *pdata = dev_get_platdata(dev); + + debug("%s dev name %s\n", __func__, dev->name); + + if (pdata->zone_node) { + nxp_tmu_init(dev); + nxp_tmu_calibration(dev); + } else { + nxp_tmu_enable_msite(dev); + } + + return 0; +} + +static int nxp_tmu_bind(struct udevice *dev) +{ + int ret; + int offset; + const char *name; + const void *prop; + + struct nxp_tmu_plat *pdata = dev_get_platdata(dev); + + debug("%s dev name %s\n", __func__, dev->name); + + prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "compatible", NULL); + if (!prop) + return 0; + else + pdata->zone_node = 1; + + offset = fdt_subnode_offset(gd->fdt_blob, 0, "thermal-zones"); + fdt_for_each_subnode(offset, gd->fdt_blob, offset) { + /* Bind the subnode to this driver */ + name = fdt_get_name(gd->fdt_blob, offset, NULL); + + ret = device_bind_with_driver_data(dev, dev->driver, name, + dev->driver_data, offset_to_ofnode(offset), NULL); + if (ret) + printf("Error binding driver '%s': %d\n", dev->driver->name, + ret); + } + return 0; +} + +static int nxp_tmu_ofdata_to_platdata(struct udevice *dev) +{ + int ret; + int trips_np; + + struct nxp_tmu_plat *pdata = dev_get_platdata(dev); + struct fdtdec_phandle_args args; + + debug("%s dev name %s\n", __func__, dev->name); + + if (pdata->zone_node) { + pdata->regs = (union tmu_regs *)fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg"); + + if ((fdt_addr_t)pdata->regs == FDT_ADDR_T_NONE) + return -EINVAL; + return 0; + } else { + struct nxp_tmu_plat *p_parent_data = dev_get_platdata(dev->parent); + if (p_parent_data->zone_node) + pdata->regs = p_parent_data->regs; + } + + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev), "thermal-sensors", + "#thermal-sensor-cells", + 0, 0, &args); + if (ret) + return ret; + + if (args.node != dev_of_offset(dev->parent)) + return -EFAULT; + + if (args.args_count >= 1) + pdata->id = args.args[0]; + else + pdata->id = 0; + + debug("args.args_count %d, id %d\n", args.args_count, pdata->id); + + pdata->polling_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "polling-delay", 1000); + + trips_np = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev), "trips"); + fdt_for_each_subnode(trips_np, gd->fdt_blob, trips_np) { + const char *type; + type = fdt_getprop(gd->fdt_blob, trips_np, "type", NULL); + if (type) { + if (strcmp(type, "critical") == 0) + pdata->critical = fdtdec_get_int(gd->fdt_blob, trips_np, "temperature", 85); + else if (strcmp(type, "passive") == 0) + pdata->alert = fdtdec_get_int(gd->fdt_blob, trips_np, "temperature", 80); + } + } + + debug("id %d polling_delay %d, critical %d, alert %d\n", + pdata->id, pdata->polling_delay, pdata->critical, pdata->alert); + + return 0; +} + +static const struct udevice_id nxp_tmu_ids[] = { + { .compatible = "fsl,imx8mq-tmu", }, + { .compatible = "fsl,imx8mm-tmu", .data=FLAGS_VER2, }, + { } +}; + +U_BOOT_DRIVER(nxp_tmu) = { + .name = "nxp_tmu", + .id = UCLASS_THERMAL, + .ops = &nxp_tmu_ops, + .of_match = nxp_tmu_ids, + .bind = nxp_tmu_bind, + .probe = nxp_tmu_probe, + .ofdata_to_platdata = nxp_tmu_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct nxp_tmu_plat), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 4fbe172e05c..161d5696cde 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -51,6 +51,8 @@ source "drivers/usb/host/Kconfig" source "drivers/usb/dwc3/Kconfig" +source "drivers/usb/cdns3/Kconfig" + source "drivers/usb/musb/Kconfig" source "drivers/usb/musb-new/Kconfig" diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig new file mode 100644 index 00000000000..3f0a26336f0 --- /dev/null +++ b/drivers/usb/cdns3/Kconfig @@ -0,0 +1,27 @@ +config USB_CDNS3 + tristate "Cadence USB3 Dual-Role Controller" + depends on (USB && USB_GADGET) + help + Say Y here if your system has a cadence USB3 dual-role controller. + It supports: dual-role switch Host-only, and Peripheral-only. + + When compiled dynamically, the module will be called cdns3.ko. + +if USB_CDNS3 + +config USB_CDNS3_GADGET + bool "Cadence USB3 device controller" + depends on USB_GADGET + select USB_GADGET_DUALSPEED + help + Say Y here to enable device controller functionality of the + cadence usb3 driver. + +config USB_CDNS3_GADGET_FORCE_HIGHSPEED + bool "Force USB2 for Cadence USB3 device controller" + depends on USB_CDNS3_GADGET + help + Say Y here to force the Cadence USB3 device controller to be + USB 2.0 even if connects to USB3 host port. + +endif diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile new file mode 100644 index 00000000000..c7a04e6948a --- /dev/null +++ b/drivers/usb/cdns3/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_USB_CDNS3) += cdns3.o + +cdns3-y := core.o +cdns3-$(CONFIG_USB_CDNS3_GADGET) += gadget.o diff --git a/drivers/usb/cdns3/cdns3-nxp-reg-def.h b/drivers/usb/cdns3/cdns3-nxp-reg-def.h new file mode 100644 index 00000000000..37f709f701c --- /dev/null +++ b/drivers/usb/cdns3/cdns3-nxp-reg-def.h @@ -0,0 +1,160 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DRIVERS_USB_CDNS3_NXP_H +#define __DRIVERS_USB_CDNS3_NXP_H + +#define USB3_CORE_CTRL1 0x00 +#define USB3_CORE_CTRL2 0x04 +#define USB3_INT_REG 0x08 +#define USB3_CORE_STATUS 0x0c +#define XHCI_DEBUG_LINK_ST 0x10 +#define XHCI_DEBUG_BUS 0x14 +#define USB3_SSPHY_CTRL1 0x40 +#define USB3_SSPHY_CTRL2 0x44 +#define USB3_SSPHY_STATUS 0x4c +#define USB2_PHY_CTRL1 0x50 +#define USB2_PHY_CTRL2 0x54 +#define USB2_PHY_STATUS 0x5c + +/* Register bits definition */ + +/* USB3_CORE_CTRL1 */ +#define SW_RESET_MASK (0x3f << 26) +#define PWR_SW_RESET (1 << 31) +#define APB_SW_RESET (1 << 30) +#define AXI_SW_RESET (1 << 29) +#define RW_SW_RESET (1 << 28) +#define PHY_SW_RESET (1 << 27) +#define PHYAHB_SW_RESET (1 << 26) +#define ALL_SW_RESET (PWR_SW_RESET | APB_SW_RESET | AXI_SW_RESET | \ + RW_SW_RESET | PHY_SW_RESET | PHYAHB_SW_RESET) +#define OC_DISABLE (1 << 9) +#define MDCTRL_CLK_SEL (1 << 7) +#define MODE_STRAP_MASK (0x7) +#define DEV_MODE (1 << 2) +#define HOST_MODE (1 << 1) +#define OTG_MODE (1 << 0) + +/* USB3_INT_REG */ +#define CLK_125_REQ (1 << 29) +#define LPM_CLK_REQ (1 << 28) +#define DEVU3_WAEKUP_EN (1 << 14) +#define OTG_WAKEUP_EN (1 << 12) +#define DEV_INT_EN (3 << 8) /* DEV INT b9:8 */ +#define HOST_INT1_EN (1 << 0) /* HOST INT b7:0 */ + +/* USB3_CORE_STATUS */ +#define MDCTRL_CLK_STATUS (1 << 15) +#define DEV_POWER_ON_READY (1 << 13) +#define HOST_POWER_ON_READY (1 << 12) + +/* USB3_SSPHY_STATUS */ +#define PHY_REFCLK_REQ (1 << 0) + + +/* PHY register definition */ +#define PHY_PMA_CMN_CTRL1 (0xC800 * 4) +#define TB_ADDR_CMN_DIAG_HSCLK_SEL (0x01e0 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR (0x0084 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR (0x0085 * 4) +#define TB_ADDR_CMN_PLL0_INTDIV (0x0094 * 4) +#define TB_ADDR_CMN_PLL0_FRACDIV (0x0095 * 4) +#define TB_ADDR_CMN_PLL0_HIGH_THR (0x0096 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL1 (0x0098 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL2 (0x0099 * 4) +#define TB_ADDR_CMN_PLL0_DSM_DIAG (0x0097 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_OVRD (0x01c2 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD (0x01c0 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD (0x01c1 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE (0x01C5 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE (0x01C6 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG (0x01C7 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE (0x01c4 * 4) +#define TB_ADDR_CMN_PSM_CLK_CTRL (0x0061 * 4) +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR (0x40ea * 4) +#define TB_ADDR_XCVR_PSM_RCTRL (0x4001 * 4) +#define TB_ADDR_TX_PSC_A0 (0x4100 * 4) +#define TB_ADDR_TX_PSC_A1 (0x4101 * 4) +#define TB_ADDR_TX_PSC_A2 (0x4102 * 4) +#define TB_ADDR_TX_PSC_A3 (0x4103 * 4) +#define TB_ADDR_TX_DIAG_ECTRL_OVRD (0x41f5 * 4) +#define TB_ADDR_TX_PSC_CAL (0x4106 * 4) +#define TB_ADDR_TX_PSC_RDY (0x4107 * 4) +#define TB_ADDR_RX_PSC_A0 (0x8000 * 4) +#define TB_ADDR_RX_PSC_A1 (0x8001 * 4) +#define TB_ADDR_RX_PSC_A2 (0x8002 * 4) +#define TB_ADDR_RX_PSC_A3 (0x8003 * 4) +#define TB_ADDR_RX_PSC_CAL (0x8006 * 4) +#define TB_ADDR_RX_PSC_RDY (0x8007 * 4) +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 (0x4058 * 4) +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 * 4) +#define TB_ADDR_RX_SLC_CU_ITER_TMR (0x80e3 * 4) +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR (0x8090 * 4) +#define TB_ADDR_RX_SAMP_DAC_CTRL (0x8058 * 4) +#define TB_ADDR_RX_DIAG_SIGDET_TUNE (0x81dc * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 (0x81df * 4) +#define TB_ADDR_RX_DIAG_BS_TM (0x81f5 * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL1 (0x81d3 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 (0x81c7 * 4) +#define TB_ADDR_RX_DIAG_ILL_E_TRIM0 (0x81c2 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 (0x81c1 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 (0x81c9 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM3 (0x81f8 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM4 (0x81f9 * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE (0x81dd * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL3 (0x81d5 * 4) +#define TB_ADDR_RX_DIAG_SC2C_DELAY (0x81e1 * 4) +#define TB_ADDR_RX_REE_VGA_GAIN_NODFE (0x81bf * 4) +#define TB_ADDR_XCVR_PSM_CAL_TMR (0x4002 * 4) +#define TB_ADDR_XCVR_PSM_A0BYP_TMR (0x4004 * 4) +#define TB_ADDR_XCVR_PSM_A0IN_TMR (0x4003 * 4) +#define TB_ADDR_XCVR_PSM_A1IN_TMR (0x4005 * 4) +#define TB_ADDR_XCVR_PSM_A2IN_TMR (0x4006 * 4) +#define TB_ADDR_XCVR_PSM_A3IN_TMR (0x4007 * 4) +#define TB_ADDR_XCVR_PSM_A4IN_TMR (0x4008 * 4) +#define TB_ADDR_XCVR_PSM_A5IN_TMR (0x4009 * 4) +#define TB_ADDR_XCVR_PSM_A0OUT_TMR (0x400a * 4) +#define TB_ADDR_XCVR_PSM_A1OUT_TMR (0x400b * 4) +#define TB_ADDR_XCVR_PSM_A2OUT_TMR (0x400c * 4) +#define TB_ADDR_XCVR_PSM_A3OUT_TMR (0x400d * 4) +#define TB_ADDR_XCVR_PSM_A4OUT_TMR (0x400e * 4) +#define TB_ADDR_XCVR_PSM_A5OUT_TMR (0x400f * 4) +#define TB_ADDR_TX_RCVDET_EN_TMR (0x4122 * 4) +#define TB_ADDR_TX_RCVDET_ST_TMR (0x4123 * 4) +#define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR (0x40f2 * 4) +#define TB_ADDR_TX_RCVDETSC_CTRL (0x4124 * 4) + +/* Register bits definition */ + +/* TB_ADDR_TX_RCVDETSC_CTRL */ +#define RXDET_IN_P3_32KHZ (1 << 0) + +/* OTG registers definition */ +#define OTGSTS 0x4 +#define OTGREFCLK 0xc + +/* Register bits definition */ +/* OTGSTS */ +#define OTG_NRDY (1 << 11) +/* OTGREFCLK */ +#define OTG_STB_CLK_SWITCH_EN (1 << 31) + +/* xHCI registers definition */ +#define XECP_PORT_CAP_REG 0x8000 +#define XECP_PM_PMCSR 0x8018 +#define XECP_AUX_CTRL_REG1 0x8120 + +/* Register bits definition */ +/* XECP_PORT_CAP_REG */ +#define LPM_2_STB_SWITCH_EN (1 << 25) + +/* XECP_AUX_CTRL_REG1 */ +#define CFG_RXDET_P3_EN (1 << 15) + +/* XECP_PM_PMCSR */ +#define PS_D0 (1 << 0) +#endif /* __DRIVERS_USB_CDNS3_NXP_H */ diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c new file mode 100644 index 00000000000..8495fec7ea3 --- /dev/null +++ b/drivers/usb/cdns3/core.c @@ -0,0 +1,374 @@ +/* + * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/ + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "linux-compat.h" +#include "cdns3-nxp-reg-def.h" +#include "core.h" +#include "gadget-export.h" + +static LIST_HEAD(cdns3_list); + +/* Need SoC level to implement the clock */ +__weak int cdns3_enable_clks(int index) +{ + return 0; +} + +__weak int cdns3_disable_clks(int index) +{ + return 0; +} + +static void cdns3_usb_phy_init(void __iomem *regs) +{ + u32 value; + + pr_debug("begin of %s\n", __func__); + + writel(0x0830, regs + PHY_PMA_CMN_CTRL1); + writel(0x10, regs + TB_ADDR_CMN_DIAG_HSCLK_SEL); + writel(0x00F0, regs + TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR); + writel(0x0018, regs + TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR); + writel(0x00D0, regs + TB_ADDR_CMN_PLL0_INTDIV); + writel(0x4aaa, regs + TB_ADDR_CMN_PLL0_FRACDIV); + writel(0x0034, regs + TB_ADDR_CMN_PLL0_HIGH_THR); + writel(0x1ee, regs + TB_ADDR_CMN_PLL0_SS_CTRL1); + writel(0x7F03, regs + TB_ADDR_CMN_PLL0_SS_CTRL2); + writel(0x0020, regs + TB_ADDR_CMN_PLL0_DSM_DIAG); + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_OVRD); + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD); + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD); + writel(0x0007, regs + TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE); + writel(0x0027, regs + TB_ADDR_CMN_DIAG_PLL0_CP_TUNE); + writel(0x0008, regs + TB_ADDR_CMN_DIAG_PLL0_LF_PROG); + writel(0x0022, regs + TB_ADDR_CMN_DIAG_PLL0_TEST_MODE); + writel(0x000a, regs + TB_ADDR_CMN_PSM_CLK_CTRL); + writel(0x139, regs + TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR); + writel(0xbefc, regs + TB_ADDR_XCVR_PSM_RCTRL); + + writel(0x7799, regs + TB_ADDR_TX_PSC_A0); + writel(0x7798, regs + TB_ADDR_TX_PSC_A1); + writel(0x509b, regs + TB_ADDR_TX_PSC_A2); + writel(0x3, regs + TB_ADDR_TX_DIAG_ECTRL_OVRD); + writel(0x509b, regs + TB_ADDR_TX_PSC_A3); + writel(0x2090, regs + TB_ADDR_TX_PSC_CAL); + writel(0x2090, regs + TB_ADDR_TX_PSC_RDY); + + writel(0xA6FD, regs + TB_ADDR_RX_PSC_A0); + writel(0xA6FD, regs + TB_ADDR_RX_PSC_A1); + writel(0xA410, regs + TB_ADDR_RX_PSC_A2); + writel(0x2410, regs + TB_ADDR_RX_PSC_A3); + + writel(0x23FF, regs + TB_ADDR_RX_PSC_CAL); + writel(0x2010, regs + TB_ADDR_RX_PSC_RDY); + + writel(0x0020, regs + TB_ADDR_TX_TXCC_MGNLS_MULT_000); + writel(0x00ff, regs + TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY); + writel(0x0002, regs + TB_ADDR_RX_SLC_CU_ITER_TMR); + writel(0x0013, regs + TB_ADDR_RX_SIGDET_HL_FILT_TMR); + writel(0x0000, regs + TB_ADDR_RX_SAMP_DAC_CTRL); + writel(0x1004, regs + TB_ADDR_RX_DIAG_SIGDET_TUNE); + writel(0x4041, regs + TB_ADDR_RX_DIAG_LFPSDET_TUNE2); + writel(0x0480, regs + TB_ADDR_RX_DIAG_BS_TM); + writel(0x8006, regs + TB_ADDR_RX_DIAG_DFE_CTRL1); + writel(0x003f, regs + TB_ADDR_RX_DIAG_ILL_IQE_TRIM4); + writel(0x543f, regs + TB_ADDR_RX_DIAG_ILL_E_TRIM0); + writel(0x543f, regs + TB_ADDR_RX_DIAG_ILL_IQ_TRIM0); + writel(0x0000, regs + TB_ADDR_RX_DIAG_ILL_IQE_TRIM6); + writel(0x8000, regs + TB_ADDR_RX_DIAG_RXFE_TM3); + writel(0x0003, regs + TB_ADDR_RX_DIAG_RXFE_TM4); + writel(0x2408, regs + TB_ADDR_RX_DIAG_LFPSDET_TUNE); + writel(0x05ca, regs + TB_ADDR_RX_DIAG_DFE_CTRL3); + writel(0x0258, regs + TB_ADDR_RX_DIAG_SC2C_DELAY); + writel(0x1fff, regs + TB_ADDR_RX_REE_VGA_GAIN_NODFE); + + writel(0x02c6, regs + TB_ADDR_XCVR_PSM_CAL_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A0BYP_TMR); + writel(0x02c6, regs + TB_ADDR_XCVR_PSM_A0IN_TMR); + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A1IN_TMR); + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A2IN_TMR); + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A3IN_TMR); + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A4IN_TMR); + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A5IN_TMR); + + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A0OUT_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A1OUT_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A2OUT_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A3OUT_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A4OUT_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A5OUT_TMR); + + /* Change rx detect parameter */ + writel(0x960, regs + TB_ADDR_TX_RCVDET_EN_TMR); + writel(0x01e0, regs + TB_ADDR_TX_RCVDET_ST_TMR); + writel(0x0090, regs + TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR); + + /* RXDET_IN_P3_32KHZ, Receiver detect slow clock enable */ + value = readl(regs + TB_ADDR_TX_RCVDETSC_CTRL); + value |= RXDET_IN_P3_32KHZ; + writel(value, regs + TB_ADDR_TX_RCVDETSC_CTRL); + + udelay(10); + + pr_debug("end of %s\n", __func__); +} + +static void cdns3_reset_core(struct cdns3 *cdns) +{ + u32 value; + + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1); + value |= ALL_SW_RESET; + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1); + udelay(1); +} + +static void cdns3_set_role(struct cdns3 *cdns, enum cdns3_roles role) +{ + u32 value; + int timeout_us = 100000; + + if (role == CDNS3_ROLE_END) + return; + + /* Wait clk value */ + value = readl(cdns->none_core_regs + USB3_SSPHY_STATUS); + writel(value, cdns->none_core_regs + USB3_SSPHY_STATUS); + udelay(1); + value = readl(cdns->none_core_regs + USB3_SSPHY_STATUS); + while ((value & 0xf0000000) != 0xf0000000 && timeout_us-- > 0) { + value = readl(cdns->none_core_regs + USB3_SSPHY_STATUS); + dev_dbg(cdns->dev, "clkvld:0x%x\n", value); + udelay(1); + } + + if (timeout_us <= 0) + dev_err(cdns->dev, "wait clkvld timeout\n"); + + /* Set all Reset bits */ + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1); + value |= ALL_SW_RESET; + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1); + udelay(1); + + if (role == CDNS3_ROLE_HOST) { + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1); + value = (value & ~MODE_STRAP_MASK) | HOST_MODE | OC_DISABLE; + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1); + value &= ~PHYAHB_SW_RESET; + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1); + mdelay(1); + cdns3_usb_phy_init(cdns->phy_regs); + /* Force B Session Valid as 1 */ + writel(0x0060, cdns->phy_regs + 0x380a4); + mdelay(1); + + value = readl(cdns->none_core_regs + USB3_INT_REG); + value |= HOST_INT1_EN; + writel(value, cdns->none_core_regs + USB3_INT_REG); + + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1); + value &= ~ALL_SW_RESET; + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1); + + dev_dbg(cdns->dev, "wait xhci_power_on_ready\n"); + + value = readl(cdns->none_core_regs + USB3_CORE_STATUS); + timeout_us = 100000; + while (!(value & HOST_POWER_ON_READY) && timeout_us-- > 0) { + value = readl(cdns->none_core_regs + USB3_CORE_STATUS); + udelay(1); + } + + if (timeout_us <= 0) + dev_err(cdns->dev, "wait xhci_power_on_ready timeout\n"); + + mdelay(1); + + dev_dbg(cdns->dev, "switch to host role successfully\n"); + } else { /* gadget mode */ + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1); + value = (value & ~MODE_STRAP_MASK) | DEV_MODE; + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1); + value &= ~PHYAHB_SW_RESET; + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1); + + cdns3_usb_phy_init(cdns->phy_regs); + /* Force B Session Valid as 1 */ + writel(0x0060, cdns->phy_regs + 0x380a4); + value = readl(cdns->none_core_regs + USB3_INT_REG); + value |= DEV_INT_EN; + writel(value, cdns->none_core_regs + USB3_INT_REG); + + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1); + value &= ~ALL_SW_RESET; + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1); + + dev_dbg(cdns->dev, "wait gadget_power_on_ready\n"); + + value = readl(cdns->none_core_regs + USB3_CORE_STATUS); + timeout_us = 100000; + while (!(value & DEV_POWER_ON_READY) && timeout_us-- > 0) { + value = readl(cdns->none_core_regs + USB3_CORE_STATUS); + udelay(1); + } + + if (timeout_us <= 0) + dev_err(cdns->dev, + "wait gadget_power_on_ready timeout\n"); + + mdelay(1); + + dev_dbg(cdns->dev, "switch to gadget role successfully\n"); + } +} + +static enum cdns3_roles cdns3_get_role(struct cdns3 *cdns) +{ + return cdns->roles[CDNS3_ROLE_HOST] + ? CDNS3_ROLE_HOST + : CDNS3_ROLE_GADGET; +} + +/** + * cdns3_core_init_role - initialize role of operation + * @cdns: Pointer to cdns3 structure + * + * Returns 0 on success otherwise negative errno + */ +static int cdns3_core_init_role(struct cdns3 *cdns, enum usb_dr_mode dr_mode) +{ + cdns->role = CDNS3_ROLE_END; + if (dr_mode == USB_DR_MODE_UNKNOWN) + dr_mode = USB_DR_MODE_OTG; + + /* Currently, only support gadget mode */ + if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { + dev_err(cdns->dev, "doesn't support host and OTG, only for gadget\n"); + return -EPERM; + } + + if (dr_mode == USB_DR_MODE_PERIPHERAL) { + if (cdns3_gadget_init(cdns)) + dev_info(cdns->dev, "doesn't support gadget\n"); + } + + if (!cdns->roles[CDNS3_ROLE_HOST] && !cdns->roles[CDNS3_ROLE_GADGET]) { + dev_err(cdns->dev, "no supported roles\n"); + return -ENODEV; + } + + return 0; +} + +static void cdns3_remove_roles(struct cdns3 *cdns) +{ + /* Only support gadget */ + cdns3_gadget_remove(cdns); +} + +int cdns3_uboot_init(struct cdns3_device *cdns3_dev) +{ + struct device *dev = NULL; + struct cdns3 *cdns; + int ret; + + cdns = devm_kzalloc(dev, sizeof(*cdns), GFP_KERNEL); + if (!cdns) + return -ENOMEM; + + cdns->dev = dev; + + /* + * Request memory region + * region-0: nxp wrap registers + * region-1: xHCI + * region-2: Peripheral + * region-3: PHY registers + * region-4: OTG registers + */ + cdns->none_core_regs = (void __iomem *)cdns3_dev->none_core_base; + cdns->xhci_regs = (void __iomem *)cdns3_dev->xhci_base; + cdns->dev_regs = (void __iomem *)cdns3_dev->dev_base; + cdns->phy_regs = (void __iomem *)cdns3_dev->phy_base; + cdns->otg_regs = (void __iomem *)cdns3_dev->otg_base; + cdns->index = cdns3_dev->index; + + ret = cdns3_enable_clks(cdns->index); + if (ret) + return ret; + + ret = cdns3_core_init_role(cdns, cdns3_dev->dr_mode); + if (ret) + goto err1; + + cdns->role = cdns3_get_role(cdns); + dev_dbg(dev, "the init role is %d\n", cdns->role); + cdns3_set_role(cdns, cdns->role); + ret = cdns3_role_start(cdns, cdns->role); + if (ret) { + dev_err(dev, "can't start %s role\n", cdns3_role(cdns)->name); + goto err2; + } + + dev_dbg(dev, "Cadence USB3 core: probe succeed\n"); + + list_add_tail(&cdns->list, &cdns3_list); + + return 0; + +err2: + cdns3_remove_roles(cdns); +err1: + cdns3_disable_clks(cdns->index); + + /* For u-boot, need to free the memory manually here. */ + if (cdns != NULL) + free(cdns); + + return ret; +} + +void cdns3_uboot_exit(int index) +{ + struct cdns3 *cdns; + + list_for_each_entry(cdns, &cdns3_list, list) { + if (cdns->index != index) + continue; + + cdns3_role_stop(cdns); + cdns3_remove_roles(cdns); + cdns3_reset_core(cdns); + cdns3_disable_clks(index); + + list_del(&cdns->list); + kfree(cdns); + break; + } +} + +void cdns3_uboot_handle_interrupt(int index) +{ + struct cdns3 *cdns = NULL; + + list_for_each_entry(cdns, &cdns3_list, list) { + if (cdns->index != index) + continue; + + cdns3_role_irq_handler(cdns); + break; + } +} diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h new file mode 100644 index 00000000000..3c933474862 --- /dev/null +++ b/drivers/usb/cdns3/core.h @@ -0,0 +1,117 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DRIVERS_USB_CDNS3_CORE_H +#define __DRIVERS_USB_CDNS3_CORE_H + +struct cdns3; +enum cdns3_roles { + CDNS3_ROLE_HOST = 0, + CDNS3_ROLE_GADGET, + CDNS3_ROLE_END, +}; + +/** + * struct cdns3_role_driver - host/gadget role driver + * @start: start this role + * @stop: stop this role + * @suspend: suspend callback for this role + * @resume: resume callback for this role + * @irq: irq handler for this role + * @name: role name string (host/gadget) + */ +struct cdns3_role_driver { + int (*start)(struct cdns3 *); + void (*stop)(struct cdns3 *); + int (*suspend)(struct cdns3 *, bool do_wakeup); + int (*resume)(struct cdns3 *, bool hibernated); + int (*irq)(struct cdns3 *); + const char *name; +}; + +#define CDNS3_NUM_OF_CLKS 5 +/** + * struct cdns3 - Representation of Cadence USB3 DRD controller. + * @dev: pointer to Cadence device struct + * @xhci_regs: pointer to base of xhci registers + * @xhci_res: the resource for xhci + * @dev_regs: pointer to base of dev registers + * @none_core_regs: pointer to base of nxp wrapper registers + * @phy_regs: pointer to base of phy registers + * @otg_regs: pointer to base of otg registers + * @irq: irq number for controller + * @roles: array of supported roles for this controller + * @role: current role + * @host_dev: the child host device pointer for cdns3 core + * @gadget_dev: the child gadget device pointer for cdns3 core + * @usbphy: usbphy for this controller + * @cdns3_clks: Clock pointer array for cdns3 core + * @extcon: Type-C extern connector + * @extcon_nb: notifier block for Type-C extern connector + * @role_switch_wq: work queue item for role switch + * @in_lpm: the controller in low power mode + * @wakeup_int: the wakeup interrupt + */ +struct cdns3 { + struct device *dev; + void __iomem *xhci_regs; + struct resource *xhci_res; + struct usbss_dev_register_block_type __iomem *dev_regs; + void __iomem *none_core_regs; + void __iomem *phy_regs; + void __iomem *otg_regs; + int irq; + struct cdns3_role_driver *roles[CDNS3_ROLE_END]; + enum cdns3_roles role; + struct device *host_dev; + struct device *gadget_dev; + struct clk *cdns3_clks[CDNS3_NUM_OF_CLKS]; + + int index; + struct list_head list; +}; + +static inline struct cdns3_role_driver *cdns3_role(struct cdns3 *cdns) +{ + WARN_ON(cdns->role >= CDNS3_ROLE_END || !cdns->roles[cdns->role]); + return cdns->roles[cdns->role]; +} + +static inline int cdns3_role_start(struct cdns3 *cdns, enum cdns3_roles role) +{ + if (role >= CDNS3_ROLE_END) + return 0; + + if (!cdns->roles[role]) + return -ENXIO; + + cdns->role = role; + return cdns->roles[role]->start(cdns); +} + +static inline void cdns3_role_stop(struct cdns3 *cdns) +{ + enum cdns3_roles role = cdns->role; + + if (role == CDNS3_ROLE_END) + return; + + cdns->roles[role]->stop(cdns); + cdns->role = CDNS3_ROLE_END; +} + +static inline void cdns3_role_irq_handler(struct cdns3 *cdns) +{ + enum cdns3_roles role = cdns->role; + + if (role == CDNS3_ROLE_END) + return; + + cdns->roles[role]->irq(cdns); +} + + +#endif /* __DRIVERS_USB_CDNS3_CORE_H */ diff --git a/drivers/usb/cdns3/dev-regs-macro.h b/drivers/usb/cdns3/dev-regs-macro.h new file mode 100644 index 00000000000..3077c267156 --- /dev/null +++ b/drivers/usb/cdns3/dev-regs-macro.h @@ -0,0 +1,887 @@ +/* + * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __REG_USBSS_DEV_ADDR_MAP_MACRO_H__ +#define __REG_USBSS_DEV_ADDR_MAP_MACRO_H__ + + +/* macros for BlueprintGlobalNameSpace::USB_CONF */ +#ifndef __USB_CONF_MACRO__ +#define __USB_CONF_MACRO__ + +/* macros for field CFGRST */ +#define USB_CONF__CFGRST__MASK 0x00000001U +#define USB_CONF__CFGSET__MASK 0x00000002U +#define USB_CONF__USB3DIS__MASK 0x00000008U +#define USB_CONF__DEVEN__MASK 0x00004000U +#define USB_CONF__DEVDS__MASK 0x00008000U +#define USB_CONF__L1EN__MASK 0x00010000U +#define USB_CONF__L1DS__MASK 0x00020000U +#define USB_CONF__CLK2OFFDS__MASK 0x00080000U +#define USB_CONF__U1EN__MASK 0x01000000U +#define USB_CONF__U1DS__MASK 0x02000000U +#define USB_CONF__U2EN__MASK 0x04000000U +#define USB_CONF__U2DS__MASK 0x08000000U +#endif /* __USB_CONF_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_conf */ +#ifndef __USB_STS_MACRO__ +#define __USB_STS_MACRO__ + +/* macros for field CFGSTS */ +#define USB_STS__CFGSTS__MASK 0x00000001U +#define USB_STS__USBSPEED__READ(src) (((uint32_t)(src) & 0x00000070U) >> 4) + +/* macros for field ENDIAN_MIRROR */ +#define USB_STS__LPMST__READ(src) (((uint32_t)(src) & 0x000c0000U) >> 18) + +/* macros for field USB2CONS */ +#define USB_STS__U1ENS__MASK 0x01000000U +#define USB_STS__U2ENS__MASK 0x02000000U +#define USB_STS__LST__READ(src) (((uint32_t)(src) & 0x3c000000U) >> 26) + +/* macros for field DMAOFF */ +#endif /* __USB_STS_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_sts */ +#ifndef __USB_CMD_MACRO__ +#define __USB_CMD_MACRO__ + +/* macros for field SET_ADDR */ +#define USB_CMD__SET_ADDR__MASK 0x00000001U +#define USB_CMD__STMODE 0x00000200U +#define USB_CMD__TMODE_SEL(x) (x << 10) +#define USB_CMD__FADDR__WRITE(src) (((uint32_t)(src) << 1) & 0x000000feU) +#endif /* __USB_CMD_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_cmd */ +#ifndef __USB_ITPN_MACRO__ +#define __USB_ITPN_MACRO__ + +/* macros for field ITPN */ +#endif /* __USB_ITPN_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_iptn */ +#ifndef __USB_LPM_MACRO__ +#define __USB_LPM_MACRO__ + +/* macros for field HIRD */ +#endif /* __USB_LPM_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_lpm */ +#ifndef __USB_IEN_MACRO__ +#define __USB_IEN_MACRO__ + +/* macros for field CONIEN */ +#define USB_IEN__CONIEN__MASK 0x00000001U +#define USB_IEN__DISIEN__MASK 0x00000002U +#define USB_IEN__UWRESIEN__MASK 0x00000004U +#define USB_IEN__UHRESIEN__MASK 0x00000008U +#define USB_IEN__U3EXTIEN__MASK 0x00000020U +#define USB_IEN__CON2IEN__MASK 0x00010000U +#define USB_IEN__U2RESIEN__MASK 0x00040000U +#define USB_IEN__L2ENTIEN__MASK 0x00100000U +#define USB_IEN__L2EXTIEN__MASK 0x00200000U +#endif /* __USB_IEN_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_ien */ +#ifndef __USB_ISTS_MACRO__ +#define __USB_ISTS_MACRO__ + +/* macros for field CONI */ +#define USB_ISTS__CONI__SHIFT 0 +#define USB_ISTS__DISI__SHIFT 1 +#define USB_ISTS__UWRESI__SHIFT 2 +#define USB_ISTS__UHRESI__SHIFT 3 +#define USB_ISTS__U3EXTI__SHIFT 5 +#define USB_ISTS__CON2I__SHIFT 16 +#define USB_ISTS__DIS2I__SHIFT 17 +#define USB_ISTS__DIS2I__MASK 0x00020000U +#define USB_ISTS__U2RESI__SHIFT 18 +#define USB_ISTS__L2ENTI__SHIFT 20 +#define USB_ISTS__L2EXTI__SHIFT 21 +#endif /* __USB_ISTS_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_ists */ +#ifndef __EP_SEL_MACRO__ +#define __EP_SEL_MACRO__ + +/* macros for field EPNO */ +#endif /* __EP_SEL_MACRO__ */ + + +/* macros for usbss_dev_register_block.ep_sel */ +#ifndef __EP_TRADDR_MACRO__ +#define __EP_TRADDR_MACRO__ + +/* macros for field TRADDR */ +#define EP_TRADDR__TRADDR__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#endif /* __EP_TRADDR_MACRO__ */ + + +/* macros for usbss_dev_register_block.ep_traddr */ +#ifndef __EP_CFG_MACRO__ +#define __EP_CFG_MACRO__ + +/* macros for field ENABLE */ +#define EP_CFG__ENABLE__MASK 0x00000001U +#define EP_CFG__EPTYPE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000006U) +#define EP_CFG__MAXBURST__WRITE(src) (((uint32_t)(src) << 8) & 0x00000f00U) +#define EP_CFG__MAXPKTSIZE__WRITE(src) (((uint32_t)(src) << 16) & 0x07ff0000U) +#define EP_CFG__BUFFERING__WRITE(src) (((uint32_t)(src) << 27) & 0xf8000000U) +#endif /* __EP_CFG_MACRO__ */ + + +/* macros for usbss_dev_register_block.ep_cfg */ +#ifndef __EP_CMD_MACRO__ +#define __EP_CMD_MACRO__ + +/* macros for field EPRST */ +#define EP_CMD__EPRST__MASK 0x00000001U +#define EP_CMD__SSTALL__MASK 0x00000002U +#define EP_CMD__CSTALL__MASK 0x00000004U +#define EP_CMD__ERDY__MASK 0x00000008U +#define EP_CMD__REQ_CMPL__MASK 0x00000020U +#define EP_CMD__DRDY__MASK 0x00000040U +#define EP_CMD__DFLUSH__MASK 0x00000080U +#endif /* __EP_CMD_MACRO__ */ + + +/* macros for usbss_dev_register_block.ep_cmd */ +#ifndef __EP_STS_MACRO__ +#define __EP_STS_MACRO__ + +/* macros for field SETUP */ +#define EP_STS__SETUP__MASK 0x00000001U +#define EP_STS__STALL__MASK 0x00000002U +#define EP_STS__IOC__MASK 0x00000004U +#define EP_STS__ISP__MASK 0x00000008U +#define EP_STS__DESCMIS__MASK 0x00000010U +#define EP_STS__TRBERR__MASK 0x00000080U +#define EP_STS__NRDY__MASK 0x00000100U +#define EP_STS__DBUSY__MASK 0x00000200U +#define EP_STS__OUTSMM__MASK 0x00004000U +#define EP_STS__ISOERR__MASK 0x00008000U +#endif /* __EP_STS_MACRO__ */ + + +/* macros for usbss_dev_register_block.ep_sts */ +#ifndef __EP_STS_SID_MACRO__ +#define __EP_STS_SID_MACRO__ + +/* macros for field SID */ +#endif /* __EP_STS_SID_MACRO__ */ + + +/* macros for usbss_dev_register_block.ep_sts_sid */ +#ifndef __EP_STS_EN_MACRO__ +#define __EP_STS_EN_MACRO__ + +/* macros for field SETUPEN */ +#define EP_STS_EN__SETUPEN__MASK 0x00000001U +#define EP_STS_EN__DESCMISEN__MASK 0x00000010U +#define EP_STS_EN__TRBERREN__MASK 0x00000080U +#endif /* __EP_STS_EN_MACRO__ */ + + +/* macros for usbss_dev_register_block.ep_sts_en */ +#ifndef __DRBL_MACRO__ +#define __DRBL_MACRO__ + +/* macros for field DRBL0O */ +#endif /* __DRBL_MACRO__ */ + + +/* macros for usbss_dev_register_block.drbl */ +#ifndef __EP_IEN_MACRO__ +#define __EP_IEN_MACRO__ + +/* macros for field EOUTEN0 */ +#define EP_IEN__EOUTEN0__MASK 0x00000001U +#define EP_IEN__EINEN0__MASK 0x00010000U +#endif /* __EP_IEN_MACRO__ */ + + +/* macros for usbss_dev_register_block.ep_ien */ +#ifndef __EP_ISTS_MACRO__ +#define __EP_ISTS_MACRO__ + +/* macros for field EOUT0 */ +#define EP_ISTS__EOUT0__MASK 0x00000001U +#define EP_ISTS__EIN0__MASK 0x00010000U +#endif /* __EP_ISTS_MACRO__ */ + + +/* macros for usbss_dev_register_block.ep_ists */ +#ifndef __USB_PWR_MACRO__ +#define __USB_PWR_MACRO__ + +/* macros for field PSO_EN */ +#endif /* __USB_PWR_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_pwr */ +#ifndef __USB_CONF2_MACRO__ +#define __USB_CONF2_MACRO__ + +/* macros for field AHB_RETRY_EN */ +#endif /* __USB_CONF2_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_conf2 */ +#ifndef __USB_CAP1_MACRO__ +#define __USB_CAP1_MACRO__ + +/* macros for field SFR_TYPE */ +#endif /* __USB_CAP1_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_cap1 */ +#ifndef __USB_CAP2_MACRO__ +#define __USB_CAP2_MACRO__ + +/* macros for field ACTUAL_MEM_SIZE */ +#endif /* __USB_CAP2_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_cap2 */ +#ifndef __USB_CAP3_MACRO__ +#define __USB_CAP3_MACRO__ + +/* macros for field EPOUT_N */ +#endif /* __USB_CAP3_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_cap3 */ +#ifndef __USB_CAP4_MACRO__ +#define __USB_CAP4_MACRO__ + +/* macros for field EPOUTI_N */ +#endif /* __USB_CAP4_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_cap4 */ +#ifndef __USB_CAP5_MACRO__ +#define __USB_CAP5_MACRO__ + +/* macros for field EPOUTI_N */ +#endif /* __USB_CAP5_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_cap5 */ +#ifndef __USB_CAP6_MACRO__ +#define __USB_CAP6_MACRO__ + +/* macros for field VERSION */ +#endif /* __USB_CAP6_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_cap6 */ +#ifndef __USB_CPKT1_MACRO__ +#define __USB_CPKT1_MACRO__ + +/* macros for field CPKT1 */ +#endif /* __USB_CPKT1_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_cpkt1 */ +#ifndef __USB_CPKT2_MACRO__ +#define __USB_CPKT2_MACRO__ + +/* macros for field CPKT2 */ +#endif /* __USB_CPKT2_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_cpkt2 */ +#ifndef __USB_CPKT3_MACRO__ +#define __USB_CPKT3_MACRO__ + +/* macros for field CPKT3 */ +#endif /* __USB_CPKT3_MACRO__ */ + + +/* macros for usbss_dev_register_block.usb_cpkt3 */ +#ifndef __CFG_REG1_MACRO__ +#define __CFG_REG1_MACRO__ + +/* macros for field DEBOUNCER_CNT */ +#endif /* __CFG_REG1_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg1 */ +#ifndef __DBG_LINK1_MACRO__ +#define __DBG_LINK1_MACRO__ + +/* macros for field LFPS_MIN_DET_U1_EXIT */ +#define DBG_LINK1__LFPS_MIN_GEN_U1_EXIT__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define DBG_LINK1__LFPS_MIN_GEN_U1_EXIT_SET__MASK 0x02000000U +#endif /* __DBG_LINK1_MACRO__ */ + + +/* macros for usbss_dev_register_block.dbg_link1 */ +#ifndef __DBG_LINK2_MACRO__ +#define __DBG_LINK2_MACRO__ + +/* macros for field RXEQTR_AVAL */ +#endif /* __DBG_LINK2_MACRO__ */ + + +/* macros for usbss_dev_register_block.dbg_link2 */ +#ifndef __CFG_REG4_MACRO__ +#define __CFG_REG4_MACRO__ + +/* macros for field RXDETECT_QUIET_TIMEOUT */ +#endif /* __CFG_REG4_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg4 */ +#ifndef __CFG_REG5_MACRO__ +#define __CFG_REG5_MACRO__ + +/* macros for field U3_HDSK_FAIL_TIMEOUT */ +#endif /* __CFG_REG5_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg5 */ +#ifndef __CFG_REG6_MACRO__ +#define __CFG_REG6_MACRO__ + +/* macros for field SSINACTIVE_QUIET_TIMEOUT */ +#endif /* __CFG_REG6_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg6 */ +#ifndef __CFG_REG7_MACRO__ +#define __CFG_REG7_MACRO__ + +/* macros for field POLLING_LFPS_TIMEOUT */ +#endif /* __CFG_REG7_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg7 */ +#ifndef __CFG_REG8_MACRO__ +#define __CFG_REG8_MACRO__ + +/* macros for field POLLING_ACTIVE_TIMEOUT */ +#endif /* __CFG_REG8_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg8 */ +#ifndef __CFG_REG9_MACRO__ +#define __CFG_REG9_MACRO__ + +/* macros for field POLLING_IDLE_TIMEOUT */ +#endif /* __CFG_REG9_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg9 */ +#ifndef __CFG_REG10_MACRO__ +#define __CFG_REG10_MACRO__ + +/* macros for field POLLING_CONF_TIMEOUT */ +#endif /* __CFG_REG10_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg10 */ +#ifndef __CFG_REG11_MACRO__ +#define __CFG_REG11_MACRO__ + +/* macros for field RECOVERY_ACTIVE_TIMEOUT */ +#endif /* __CFG_REG11_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg11 */ +#ifndef __CFG_REG12_MACRO__ +#define __CFG_REG12_MACRO__ + +/* macros for field RECOVERY_CONF_TIMEOUT */ +#endif /* __CFG_REG12_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg12 */ +#ifndef __CFG_REG13_MACRO__ +#define __CFG_REG13_MACRO__ + +/* macros for field RECOVERY_IDLE_TIMEOUT */ +#endif /* __CFG_REG13_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg13 */ +#ifndef __CFG_REG14_MACRO__ +#define __CFG_REG14_MACRO__ + +/* macros for field HOTRESET_ACTIVE_TIMEOUT */ +#endif /* __CFG_REG14_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg14 */ +#ifndef __CFG_REG15_MACRO__ +#define __CFG_REG15_MACRO__ + +/* macros for field HOTRESET_EXIT_TIMEOUT */ +#endif /* __CFG_REG15_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg15 */ +#ifndef __CFG_REG16_MACRO__ +#define __CFG_REG16_MACRO__ + +/* macros for field LFPS_PING_REPEAT */ +#endif /* __CFG_REG16_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg16 */ +#ifndef __CFG_REG17_MACRO__ +#define __CFG_REG17_MACRO__ + +/* macros for field PENDING_HP_TIMEOUT */ +#endif /* __CFG_REG17_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg17 */ +#ifndef __CFG_REG18_MACRO__ +#define __CFG_REG18_MACRO__ + +/* macros for field CREDIT_HP_TIMEOUT */ +#endif /* __CFG_REG18_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg18 */ +#ifndef __CFG_REG19_MACRO__ +#define __CFG_REG19_MACRO__ + +/* macros for field LUP_TIMEOUT */ +#endif /* __CFG_REG19_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg19 */ +#ifndef __CFG_REG20_MACRO__ +#define __CFG_REG20_MACRO__ + +/* macros for field LDN_TIMEOUT */ +#endif /* __CFG_REG20_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg20 */ +#ifndef __CFG_REG21_MACRO__ +#define __CFG_REG21_MACRO__ + +/* macros for field PM_LC_TIMEOUT */ +#endif /* __CFG_REG21_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg21 */ +#ifndef __CFG_REG22_MACRO__ +#define __CFG_REG22_MACRO__ + +/* macros for field PM_ENTRY_TIMEOUT */ +#endif /* __CFG_REG22_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg22 */ +#ifndef __CFG_REG23_MACRO__ +#define __CFG_REG23_MACRO__ + +/* macros for field UX_EXIT_TIMEOUT */ +#endif /* __CFG_REG23_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg23 */ +#ifndef __CFG_REG24_MACRO__ +#define __CFG_REG24_MACRO__ + +/* macros for field LFPS_DET_RESET_MIN */ +#endif /* __CFG_REG24_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg24 */ +#ifndef __CFG_REG25_MACRO__ +#define __CFG_REG25_MACRO__ + +/* macros for field LFPS_DET_RESET_MAX */ +#endif /* __CFG_REG25_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg25 */ +#ifndef __CFG_REG26_MACRO__ +#define __CFG_REG26_MACRO__ + +/* macros for field LFPS_DET_POLLING_MIN */ +#endif /* __CFG_REG26_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg26 */ +#ifndef __CFG_REG27_MACRO__ +#define __CFG_REG27_MACRO__ + +/* macros for field LFPS_DET_POLLING_MAX */ +#endif /* __CFG_REG27_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg27 */ +#ifndef __CFG_REG28_MACRO__ +#define __CFG_REG28_MACRO__ + +/* macros for field LFPS_DET_PING_MIN */ +#endif /* __CFG_REG28_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg28 */ +#ifndef __CFG_REG29_MACRO__ +#define __CFG_REG29_MACRO__ + +/* macros for field LFPS_DET_PING_MAX */ +#endif /* __CFG_REG29_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg29 */ +#ifndef __CFG_REG30_MACRO__ +#define __CFG_REG30_MACRO__ + +/* macros for field LFPS_DET_U1EXIT_MIN */ +#endif /* __CFG_REG30_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg30 */ +#ifndef __CFG_REG31_MACRO__ +#define __CFG_REG31_MACRO__ + +/* macros for field LFPS_DET_U1EXIT_MAX */ +#endif /* __CFG_REG31_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg31 */ +#ifndef __CFG_REG32_MACRO__ +#define __CFG_REG32_MACRO__ + +/* macros for field LFPS_DET_U2EXIT_MIN */ +#endif /* __CFG_REG32_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg32 */ +#ifndef __CFG_REG33_MACRO__ +#define __CFG_REG33_MACRO__ + +/* macros for field LFPS_DET_U2EXIT_MAX */ +#endif /* __CFG_REG33_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg33 */ +#ifndef __CFG_REG34_MACRO__ +#define __CFG_REG34_MACRO__ + +/* macros for field LFPS_DET_U3EXIT_MIN */ +#endif /* __CFG_REG34_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg34 */ +#ifndef __CFG_REG35_MACRO__ +#define __CFG_REG35_MACRO__ + +/* macros for field LFPS_DET_U3EXIT_MAX */ +#endif /* __CFG_REG35_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg35 */ +#ifndef __CFG_REG36_MACRO__ +#define __CFG_REG36_MACRO__ + +/* macros for field LFPS_GEN_PING */ +#endif /* __CFG_REG36_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg36 */ +#ifndef __CFG_REG37_MACRO__ +#define __CFG_REG37_MACRO__ + +/* macros for field LFPS_GEN_POLLING */ +#endif /* __CFG_REG37_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg37 */ +#ifndef __CFG_REG38_MACRO__ +#define __CFG_REG38_MACRO__ + +/* macros for field LFPS_GEN_U1EXIT */ +#endif /* __CFG_REG38_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg38 */ +#ifndef __CFG_REG39_MACRO__ +#define __CFG_REG39_MACRO__ + +/* macros for field LFPS_GEN_U3EXIT */ +#endif /* __CFG_REG39_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg39 */ +#ifndef __CFG_REG40_MACRO__ +#define __CFG_REG40_MACRO__ + +/* macros for field LFPS_MIN_GEN_U1EXIT */ +#endif /* __CFG_REG40_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg40 */ +#ifndef __CFG_REG41_MACRO__ +#define __CFG_REG41_MACRO__ + +/* macros for field LFPS_MIN_GEN_U2EXIT */ +#endif /* __CFG_REG41_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg41 */ +#ifndef __CFG_REG42_MACRO__ +#define __CFG_REG42_MACRO__ + +/* macros for field LFPS_POLLING_REPEAT */ +#endif /* __CFG_REG42_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg42 */ +#ifndef __CFG_REG43_MACRO__ +#define __CFG_REG43_MACRO__ + +/* macros for field LFPS_POLLING_MAX_TREPEAT */ +#endif /* __CFG_REG43_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg43 */ +#ifndef __CFG_REG44_MACRO__ +#define __CFG_REG44_MACRO__ + +/* macros for field LFPS_POLLING_MIN_TREPEAT */ +#endif /* __CFG_REG44_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg44 */ +#ifndef __CFG_REG45_MACRO__ +#define __CFG_REG45_MACRO__ + +/* macros for field ITP_WAKEUP_TIMEOUT */ +#endif /* __CFG_REG45_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg45 */ +#ifndef __CFG_REG46_MACRO__ +#define __CFG_REG46_MACRO__ + +/* macros for field TSEQ_QUANTITY */ +#endif /* __CFG_REG46_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg46 */ +#ifndef __CFG_REG47_MACRO__ +#define __CFG_REG47_MACRO__ + +/* macros for field ERDY_TIMEOUT_CNT */ +#endif /* __CFG_REG47_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg47 */ +#ifndef __CFG_REG48_MACRO__ +#define __CFG_REG48_MACRO__ + +/* macros for field TWTRSTFS_J_CNT */ +#endif /* __CFG_REG48_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg48 */ +#ifndef __CFG_REG49_MACRO__ +#define __CFG_REG49_MACRO__ + +/* macros for field TUCH_CNT */ +#endif /* __CFG_REG49_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg49 */ +#ifndef __CFG_REG50_MACRO__ +#define __CFG_REG50_MACRO__ + +/* macros for field TWAITCHK_CNT */ +#endif /* __CFG_REG50_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg50 */ +#ifndef __CFG_REG51_MACRO__ +#define __CFG_REG51_MACRO__ + +/* macros for field TWTFS_CNT */ +#endif /* __CFG_REG51_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg51 */ +#ifndef __CFG_REG52_MACRO__ +#define __CFG_REG52_MACRO__ + +/* macros for field TWTREV_CNT */ +#endif /* __CFG_REG52_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg52 */ +#ifndef __CFG_REG53_MACRO__ +#define __CFG_REG53_MACRO__ + +/* macros for field TWTRSTHS_CNT */ +#endif /* __CFG_REG53_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg53 */ +#ifndef __CFG_REG54_MACRO__ +#define __CFG_REG54_MACRO__ + +/* macros for field TWTRSM_CNT */ +#endif /* __CFG_REG54_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg54 */ +#ifndef __CFG_REG55_MACRO__ +#define __CFG_REG55_MACRO__ + +/* macros for field TDRSMUP_CNT */ +#endif /* __CFG_REG55_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg55 */ +#ifndef __CFG_REG56_MACRO__ +#define __CFG_REG56_MACRO__ + +/* macros for field TOUTHS_CNT */ +#endif /* __CFG_REG56_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg56 */ +#ifndef __CFG_REG57_MACRO__ +#define __CFG_REG57_MACRO__ + +/* macros for field LFPS_DEB_WIDTH */ +#endif /* __CFG_REG57_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg57 */ +#ifndef __CFG_REG58_MACRO__ +#define __CFG_REG58_MACRO__ + +/* macros for field LFPS_GEN_U2EXIT */ +#endif /* __CFG_REG58_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg58 */ +#ifndef __CFG_REG59_MACRO__ +#define __CFG_REG59_MACRO__ + +/* macros for field LFPS_MIN_GEN_U3EXIT */ +#endif /* __CFG_REG59_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg59 */ +#ifndef __CFG_REG60_MACRO__ +#define __CFG_REG60_MACRO__ + +/* macros for field PORT_CONFIG_TIMEOUT */ +#endif /* __CFG_REG60_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg60 */ +#ifndef __CFG_REG61_MACRO__ +#define __CFG_REG61_MACRO__ + +/* macros for field LFPS_POL_LFPS_TO_RXEQ */ +#endif /* __CFG_REG61_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg61 */ +#ifndef __CFG_REG62_MACRO__ +#define __CFG_REG62_MACRO__ + +/* macros for field PHY_TX_LATENCY */ +#endif /* __CFG_REG62_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg62 */ +#ifndef __CFG_REG63_MACRO__ +#define __CFG_REG63_MACRO__ + +/* macros for field U2_INACTIVITY_TMOUT */ +#endif /* __CFG_REG63_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg63 */ +#ifndef __CFG_REG64_MACRO__ +#define __CFG_REG64_MACRO__ + +/* macros for field TFILTSE0 */ +#endif /* __CFG_REG64_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg64 */ +#ifndef __CFG_REG65_MACRO__ +#define __CFG_REG65_MACRO__ + +/* macros for field TFILT */ +#endif /* __CFG_REG65_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg65 */ +#ifndef __CFG_REG66_MACRO__ +#define __CFG_REG66_MACRO__ + +/* macros for field TWTRSTFS_SE0 */ +#endif /* __CFG_REG66_MACRO__ */ + + +/* macros for usbss_dev_register_block.cfg_reg66 */ +#ifndef __DMA_AXI_CTRL_MACRO__ +#define __DMA_AXI_CTRL_MACRO__ + +/* macros for field MAWPROT */ +#endif /* __DMA_AXI_CTRL_MACRO__ */ + + +/* macros for usbss_dev_register_block.dma_axi_ctrl */ +#ifndef __DMA_AXI_ID_MACRO__ +#define __DMA_AXI_ID_MACRO__ + +/* macros for field MAW_ID */ +#endif /* __DMA_AXI_ID_MACRO__ */ + + +/* macros for usbss_dev_register_block.dma_axi_id */ +#ifndef __DMA_AXI_CAP_MACRO__ +#define __DMA_AXI_CAP_MACRO__ + +/* macros for field RESERVED0 */ +#endif /* __DMA_AXI_CAP_MACRO__ */ + + +/* macros for usbss_dev_register_block.dma_axi_cap */ +#ifndef __DMA_AXI_CTRL0_MACRO__ +#define __DMA_AXI_CTRL0_MACRO__ + +/* macros for field B_MAX */ +#endif /* __DMA_AXI_CTRL0_MACRO__ */ + + +/* macros for usbss_dev_register_block.dma_axi_ctrl0 */ +#ifndef __DMA_AXI_CTRL1_MACRO__ +#define __DMA_AXI_CTRL1_MACRO__ + +/* macros for field ROT */ +#endif /* __DMA_AXI_CTRL1_MACRO__ */ + + +/* macros for usbss_dev_register_block.dma_axi_ctrl1 */ +#endif /* __REG_USBSS_DEV_ADDR_MAP_MACRO_H__ */ diff --git a/drivers/usb/cdns3/dev-regs-map.h b/drivers/usb/cdns3/dev-regs-map.h new file mode 100644 index 00000000000..25040c1c52c --- /dev/null +++ b/drivers/usb/cdns3/dev-regs-map.h @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __REG_USBSS_DEV_ADDR_MAP_H__ +#define __REG_USBSS_DEV_ADDR_MAP_H__ + +#include "dev-regs-macro.h" + +struct usbss_dev_register_block_type { + uint32_t usb_conf; /* 0x0 - 0x4 */ + uint32_t usb_sts; /* 0x4 - 0x8 */ + uint32_t usb_cmd; /* 0x8 - 0xc */ + uint32_t usb_iptn; /* 0xc - 0x10 */ + uint32_t usb_lpm; /* 0x10 - 0x14 */ + uint32_t usb_ien; /* 0x14 - 0x18 */ + uint32_t usb_ists; /* 0x18 - 0x1c */ + uint32_t ep_sel; /* 0x1c - 0x20 */ + uint32_t ep_traddr; /* 0x20 - 0x24 */ + uint32_t ep_cfg; /* 0x24 - 0x28 */ + uint32_t ep_cmd; /* 0x28 - 0x2c */ + uint32_t ep_sts; /* 0x2c - 0x30 */ + uint32_t ep_sts_sid; /* 0x30 - 0x34 */ + uint32_t ep_sts_en; /* 0x34 - 0x38 */ + uint32_t drbl; /* 0x38 - 0x3c */ + uint32_t ep_ien; /* 0x3c - 0x40 */ + uint32_t ep_ists; /* 0x40 - 0x44 */ + uint32_t usb_pwr; /* 0x44 - 0x48 */ + uint32_t usb_conf2; /* 0x48 - 0x4c */ + uint32_t usb_cap1; /* 0x4c - 0x50 */ + uint32_t usb_cap2; /* 0x50 - 0x54 */ + uint32_t usb_cap3; /* 0x54 - 0x58 */ + uint32_t usb_cap4; /* 0x58 - 0x5c */ + uint32_t usb_cap5; /* 0x5c - 0x60 */ + uint32_t PAD2_73; /* 0x60 - 0x64 */ + uint32_t usb_cpkt1; /* 0x64 - 0x68 */ + uint32_t usb_cpkt2; /* 0x68 - 0x6c */ + uint32_t usb_cpkt3; /* 0x6c - 0x70 */ + char pad__0[0x90]; /* 0x70 - 0x100 */ + uint32_t PAD2_78; /* 0x100 - 0x104 */ + uint32_t dbg_link1; /* 0x104 - 0x108 */ + uint32_t PAD2_80; /* 0x108 - 0x10c */ + uint32_t PAD2_81; /* 0x10c - 0x110 */ + uint32_t PAD2_82; /* 0x110 - 0x114 */ + uint32_t PAD2_83; /* 0x114 - 0x118 */ + uint32_t PAD2_84; /* 0x118 - 0x11c */ + uint32_t PAD2_85; /* 0x11c - 0x120 */ + uint32_t PAD2_86; /* 0x120 - 0x124 */ + uint32_t PAD2_87; /* 0x124 - 0x128 */ + uint32_t PAD2_88; /* 0x128 - 0x12c */ + uint32_t PAD2_89; /* 0x12c - 0x130 */ + uint32_t PAD2_90; /* 0x130 - 0x134 */ + uint32_t PAD2_91; /* 0x134 - 0x138 */ + uint32_t PAD2_92; /* 0x138 - 0x13c */ + uint32_t PAD2_93; /* 0x13c - 0x140 */ + uint32_t PAD2_94; /* 0x140 - 0x144 */ + uint32_t PAD2_95; /* 0x144 - 0x148 */ + uint32_t PAD2_96; /* 0x148 - 0x14c */ + uint32_t PAD2_97; /* 0x14c - 0x150 */ + uint32_t PAD2_98; /* 0x150 - 0x154 */ + uint32_t PAD2_99; /* 0x154 - 0x158 */ + uint32_t PAD2_100; /* 0x158 - 0x15c */ + uint32_t PAD2_101; /* 0x15c - 0x160 */ + uint32_t PAD2_102; /* 0x160 - 0x164 */ + uint32_t PAD2_103; /* 0x164 - 0x168 */ + uint32_t PAD2_104; /* 0x168 - 0x16c */ + uint32_t PAD2_105; /* 0x16c - 0x170 */ + uint32_t PAD2_106; /* 0x170 - 0x174 */ + uint32_t PAD2_107; /* 0x174 - 0x178 */ + uint32_t PAD2_108; /* 0x178 - 0x17c */ + uint32_t PAD2_109; /* 0x17c - 0x180 */ + uint32_t PAD2_110; /* 0x180 - 0x184 */ + uint32_t PAD2_111; /* 0x184 - 0x188 */ + uint32_t PAD2_112; /* 0x188 - 0x18c */ + char pad__1[0x20]; /* 0x18c - 0x1ac */ + uint32_t PAD2_114; /* 0x1ac - 0x1b0 */ + uint32_t PAD2_115; /* 0x1b0 - 0x1b4 */ + uint32_t PAD2_116; /* 0x1b4 - 0x1b8 */ + uint32_t PAD2_117; /* 0x1b8 - 0x1bc */ + uint32_t PAD2_118; /* 0x1bc - 0x1c0 */ + uint32_t PAD2_119; /* 0x1c0 - 0x1c4 */ + uint32_t PAD2_120; /* 0x1c4 - 0x1c8 */ + uint32_t PAD2_121; /* 0x1c8 - 0x1cc */ + uint32_t PAD2_122; /* 0x1cc - 0x1d0 */ + uint32_t PAD2_123; /* 0x1d0 - 0x1d4 */ + uint32_t PAD2_124; /* 0x1d4 - 0x1d8 */ + uint32_t PAD2_125; /* 0x1d8 - 0x1dc */ + uint32_t PAD2_126; /* 0x1dc - 0x1e0 */ + uint32_t PAD2_127; /* 0x1e0 - 0x1e4 */ + uint32_t PAD2_128; /* 0x1e4 - 0x1e8 */ + uint32_t PAD2_129; /* 0x1e8 - 0x1ec */ + uint32_t PAD2_130; /* 0x1ec - 0x1f0 */ + uint32_t PAD2_131; /* 0x1f0 - 0x1f4 */ + uint32_t PAD2_132; /* 0x1f4 - 0x1f8 */ + uint32_t PAD2_133; /* 0x1f8 - 0x1fc */ + uint32_t PAD2_134; /* 0x1fc - 0x200 */ + uint32_t PAD2_135; /* 0x200 - 0x204 */ + uint32_t PAD2_136; /* 0x204 - 0x208 */ + uint32_t PAD2_137; /* 0x208 - 0x20c */ + uint32_t PAD2_138; /* 0x20c - 0x210 */ + uint32_t PAD2_139; /* 0x210 - 0x214 */ + uint32_t PAD2_140; /* 0x214 - 0x218 */ + uint32_t PAD2_141; /* 0x218 - 0x21c */ + uint32_t PAD2_142; /* 0x21c - 0x220 */ + uint32_t PAD2_143; /* 0x220 - 0x224 */ + uint32_t PAD2_144; /* 0x224 - 0x228 */ + char pad__2[0xd8]; /* 0x228 - 0x300 */ + uint32_t dma_axi_ctrl; /* 0x300 - 0x304 */ + uint32_t PAD2_147; /* 0x304 - 0x308 */ + uint32_t PAD2_148; /* 0x308 - 0x30c */ + uint32_t PAD2_149; /* 0x30c - 0x310 */ + uint32_t PAD2_150; /* 0x310 - 0x314 */ +}; + +#endif /* __REG_USBSS_DEV_ADDR_MAP_H__ */ diff --git a/drivers/usb/cdns3/gadget-export.h b/drivers/usb/cdns3/gadget-export.h new file mode 100644 index 00000000000..e75a17e1dd7 --- /dev/null +++ b/drivers/usb/cdns3/gadget-export.h @@ -0,0 +1,27 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CDNS3_GADGET_EXPORT_H +#define __CDNS3_GADGET_EXPORT_H + +#ifdef CONFIG_USB_CDNS3_GADGET + +int cdns3_gadget_init(struct cdns3 *cdns); +void cdns3_gadget_remove(struct cdns3 *cdns); +#else + +static inline int cdns3_gadget_init(struct cdns3 *cdns) +{ + return -ENXIO; +} + +static inline void cdns3_gadget_remove(struct cdns3 *cdns) +{ +} + +#endif + +#endif /* __CDNS3_GADGET_EXPORT_H */ diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c new file mode 100644 index 00000000000..0cc4add48c6 --- /dev/null +++ b/drivers/usb/cdns3/gadget.c @@ -0,0 +1,2316 @@ +/* + * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/ + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "linux-compat.h" +#include "core.h" +#include "gadget-export.h" +#include "gadget.h" +#include "io.h" + +/*-------------------------------------------------------------------------*/ +/* Function declarations */ + +static void select_ep(struct usb_ss_dev *usb_ss, u32 ep); +static int usb_ss_allocate_trb_pool(struct usb_ss_endpoint *usb_ss_ep); +static void cdns_ep_stall_flush(struct usb_ss_endpoint *usb_ss_ep); +static void cdns_ep0_config(struct usb_ss_dev *usb_ss); +static void cdns_gadget_unconfig(struct usb_ss_dev *usb_ss); +static void cdns_ep0_run_transfer(struct usb_ss_dev *usb_ss, + dma_addr_t dma_addr, unsigned int length, int erdy); +static int cdns_ep_run_transfer(struct usb_ss_endpoint *usb_ss_ep); +static int cdns_get_setup_ret(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req); +static int cdns_req_ep0_set_address(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req); +static int cdns_req_ep0_get_status(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req); +static int cdns_req_ep0_handle_feature(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req, int set); +static int cdns_req_ep0_set_sel(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req); +static int cdns_req_ep0_set_isoch_delay(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req); +static int cdns_req_ep0_set_configuration(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req); +static int cdns_ep0_standard_request(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req); +static void cdns_ep0_setup_phase(struct usb_ss_dev *usb_ss); +static int cdns_check_ep_interrupt_proceed(struct usb_ss_endpoint *usb_ss_ep); +static void cdns_check_ep0_interrupt_proceed(struct usb_ss_dev *usb_ss, + int dir); +static void cdns_check_usb_interrupt_proceed(struct usb_ss_dev *usb_ss, + u32 usb_ists); +#ifdef CDNS_THREADED_IRQ_HANDLING +static irqreturn_t cdns_irq_handler(int irq, void *_usb_ss); +#endif +static int usb_ss_gadget_ep0_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc); +static int usb_ss_gadget_ep0_disable(struct usb_ep *ep); +static int usb_ss_gadget_ep0_set_halt(struct usb_ep *ep, int value); +static int usb_ss_gadget_ep0_queue(struct usb_ep *ep, + struct usb_request *request, gfp_t gfp_flags); +static int usb_ss_gadget_ep_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc); +static int usb_ss_gadget_ep_disable(struct usb_ep *ep); +static struct usb_request *usb_ss_gadget_ep_alloc_request(struct usb_ep *ep, + gfp_t gfp_flags); +static void usb_ss_gadget_ep_free_request(struct usb_ep *ep, + struct usb_request *request); +static int usb_ss_gadget_ep_queue(struct usb_ep *ep, + struct usb_request *request, gfp_t gfp_flags); +static int usb_ss_gadget_ep_dequeue(struct usb_ep *ep, + struct usb_request *request); +static int usb_ss_gadget_ep_set_halt(struct usb_ep *ep, int value); +static int usb_ss_gadget_ep_set_wedge(struct usb_ep *ep); +static int usb_ss_gadget_get_frame(struct usb_gadget *gadget); +static int usb_ss_gadget_wakeup(struct usb_gadget *gadget); +static int usb_ss_gadget_set_selfpowered(struct usb_gadget *gadget, + int is_selfpowered); +static int usb_ss_gadget_pullup(struct usb_gadget *gadget, int is_on); +static int usb_ss_gadget_udc_start(struct usb_gadget *gadget, + struct usb_gadget_driver *driver); +static int usb_ss_gadget_udc_stop(struct usb_gadget *gadget); +static int usb_ss_init_ep(struct usb_ss_dev *usb_ss); +static int usb_ss_init_ep0(struct usb_ss_dev *usb_ss); +static void __cdns3_gadget_start(struct usb_ss_dev *usb_ss); +static void cdns_prepare_setup_packet(struct usb_ss_dev *usb_ss); +static void cdns_ep_config(struct usb_ss_endpoint *usb_ss_ep); + +static const char *const speed_names[] = { + [USB_SPEED_UNKNOWN] = "UNKNOWN", + [USB_SPEED_LOW] = "low-speed", + [USB_SPEED_FULL] = "full-speed", + [USB_SPEED_HIGH] = "high-speed", + [USB_SPEED_WIRELESS] = "wireless", + [USB_SPEED_SUPER] = "super-speed", +}; + +const char *usb_speed_string(enum usb_device_speed speed) +{ + if (speed < 0 || speed >= ARRAY_SIZE(speed_names)) + speed = USB_SPEED_UNKNOWN; + return speed_names[speed]; +} + +static struct usb_endpoint_descriptor cdns3_gadget_ep0_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bmAttributes = USB_ENDPOINT_XFER_CONTROL, +}; + +static u32 gadget_readl(struct usb_ss_dev *usb_ss, uint32_t __iomem *reg) +{ + return cdns_readl(reg); +} + +static void gadget_writel(struct usb_ss_dev *usb_ss, + uint32_t __iomem *reg, u32 value) +{ + cdns_writel(reg, value); +} + +/** + * next_request - returns next request from list + * @list: list containing requests + * + * Returns request or NULL if no requests in list + */ +static struct usb_request *next_request(struct list_head *list) +{ + if (list_empty(list)) + return NULL; + return list_first_entry(list, struct usb_request, list); +} + +/** + * select_ep - selects endpoint + * @usb_ss: extended gadget object + * @ep: endpoint address + */ +static void select_ep(struct usb_ss_dev *usb_ss, u32 ep) +{ + if (!usb_ss || !usb_ss->regs) { + dev_err(&usb_ss->dev, "Failed to select endpoint!\n"); + return; + } + + gadget_writel(usb_ss, &usb_ss->regs->ep_sel, ep); +} + +/** + * usb_ss_allocate_trb_pool - Allocates TRB's pool for selected endpoint + * @usb_ss_ep: extended endpoint object + * + * Function will return 0 on success or -ENOMEM on allocation error + */ +static int usb_ss_allocate_trb_pool(struct usb_ss_endpoint *usb_ss_ep) +{ + if (usb_ss_ep->trb_pool) + return 0; + + usb_ss_ep->trb_pool = dma_alloc_coherent( + sizeof(struct usb_ss_trb) * USB_SS_TRBS_NUM, + (unsigned long *)&usb_ss_ep->trb_pool_dma); + + if (!usb_ss_ep->trb_pool) { + dev_err(&(usb_ss_ep->usb_ss->dev), + "Failed to allocate TRB pool for endpoint %s\n", + usb_ss_ep->name); + return -ENOMEM; + } + + memset(usb_ss_ep->trb_pool, 0, sizeof(struct usb_ss_trb) * USB_SS_TRBS_NUM); + + return 0; +} + +/** + * cdns_ep_stall_flush - Stalls and flushes selected endpoint + * @usb_ss_ep: extended endpoint object + * + * Endpoint must be selected before call to this function + */ +static void cdns_ep_stall_flush(struct usb_ss_endpoint *usb_ss_ep) +{ + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__DFLUSH__MASK | EP_CMD__ERDY__MASK | + EP_CMD__SSTALL__MASK); + + /* wait for DFLUSH cleared */ + while (gadget_readl(usb_ss, + &usb_ss->regs->ep_cmd) & EP_CMD__DFLUSH__MASK) + ; + + usb_ss_ep->stalled_flag = 1; +} + +/** + * cdns_ep0_config - Configures default endpoint + * @usb_ss: extended gadget object + * + * Functions sets parameters: maximal packet size and enables interrupts + */ +static void cdns_ep0_config(struct usb_ss_dev *usb_ss) +{ + u32 max_packet_size = 0; + + switch (usb_ss->gadget.speed) { + case USB_SPEED_UNKNOWN: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_0; + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_0; + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(0); + break; + + case USB_SPEED_LOW: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_8; + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_8; + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); + break; + + case USB_SPEED_FULL: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_64; + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_64; + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); + break; + + case USB_SPEED_HIGH: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_64; + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_64; + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); + break; + + case USB_SPEED_WIRELESS: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_64; + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_64; + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); + break; + + case USB_SPEED_SUPER: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_512; + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_512; + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); + break; + } + + /* init ep out */ + select_ep(usb_ss, USB_DIR_OUT); + + gadget_writel(usb_ss, &usb_ss->regs->ep_cfg, + EP_CFG__ENABLE__MASK | + EP_CFG__MAXPKTSIZE__WRITE(max_packet_size)); + gadget_writel(usb_ss, &usb_ss->regs->ep_sts_en, + EP_STS_EN__SETUPEN__MASK | + EP_STS_EN__DESCMISEN__MASK | + EP_STS_EN__TRBERREN__MASK); + + /* init ep in */ + select_ep(usb_ss, USB_DIR_IN); + + gadget_writel(usb_ss, &usb_ss->regs->ep_cfg, + EP_CFG__ENABLE__MASK | + EP_CFG__MAXPKTSIZE__WRITE(max_packet_size)); + gadget_writel(usb_ss, &usb_ss->regs->ep_sts_en, + EP_STS_EN__SETUPEN__MASK | + EP_STS_EN__TRBERREN__MASK); + + cdns_prepare_setup_packet(usb_ss); +} + +/** + * cdns_gadget_unconfig - Unconfigures device controller + * @usb_ss: extended gadget object + */ +static void cdns_gadget_unconfig(struct usb_ss_dev *usb_ss) +{ + /* RESET CONFIGURATION */ + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, + USB_CONF__CFGRST__MASK); + + usb_ss->hw_configured_flag = 0; +} + +/** + * cdns_ep0_run_transfer - Do transfer on default endpoint hardware + * @usb_ss: extended gadget object + * @dma_addr: physical address where data is/will be stored + * @length: data length + * @erdy: set it to 1 when ERDY packet should be sent - + * exit from flow control state + */ +static void cdns_ep0_run_transfer(struct usb_ss_dev *usb_ss, + dma_addr_t dma_addr, unsigned int length, int erdy) +{ + usb_ss->trb_ep0[0] = TRB_SET_DATA_BUFFER_POINTER(dma_addr); + usb_ss->trb_ep0[1] = TRB_SET_TRANSFER_LENGTH((u32)length); + usb_ss->trb_ep0[2] = TRB_SET_CYCLE_BIT | + TRB_SET_INT_ON_COMPLETION | TRB_TYPE_NORMAL; + + cdns_flush_cache((uintptr_t)usb_ss->trb_ep0, 20); + cdns_flush_cache((uintptr_t)dma_addr, length); + + dev_dbg(&usb_ss->dev, "DRBL(%02X)\n", + usb_ss->ep0_data_dir ? USB_DIR_IN : USB_DIR_OUT); + + select_ep(usb_ss, usb_ss->ep0_data_dir + ? USB_DIR_IN : USB_DIR_OUT); + + gadget_writel(usb_ss, &usb_ss->regs->ep_traddr, + EP_TRADDR__TRADDR__WRITE(usb_ss->trb_ep0_dma)); + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__DRDY__MASK); /* drbl */ + + if (erdy) + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK); +} + +/** + * cdns_ep_run_transfer - Do transfer on no-default endpoint hardware + * @usb_ss_ep: extended endpoint object + * + * Returns zero on success or negative value on failure + */ +static int cdns_ep_run_transfer(struct usb_ss_endpoint *usb_ss_ep) +{ + dma_addr_t trb_dma; + struct usb_request *request = next_request(&usb_ss_ep->request_list); + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + struct usb_ss_trb *trb; + + if (request == NULL) + return -EINVAL; + + dev_dbg(&usb_ss->dev, "DRBL(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); + + usb_ss_ep->hw_pending_flag = 1; + trb_dma = request->dma; + + /* must allocate buffer aligned to 8 */ + if (request->dma % ADDR_MODULO_8) { + memcpy(usb_ss_ep->cpu_addr, request->buf, request->length); + trb_dma = usb_ss_ep->dma_addr; + } + + cdns_flush_cache((uintptr_t)trb_dma, request->length); + + trb = usb_ss_ep->trb_pool; + + /* fill TRB */ + trb->offset0 = trb_dma; + + trb->offset4 = TRB_SET_BURST_LENGTH(16) | + TRB_SET_TRANSFER_LENGTH(request->length); + + trb->offset8 = TRB_SET_CYCLE_BIT + | TRB_SET_INT_ON_COMPLETION + | TRB_SET_INT_ON_SHORT_PACKET + | TRB_TYPE_NORMAL; + + cdns_flush_cache((uintptr_t)trb, sizeof(struct usb_ss_trb)); + + /* arm transfer on selected endpoint */ + select_ep(usb_ss_ep->usb_ss, + usb_ss_ep->endpoint.desc->bEndpointAddress); + + gadget_writel(usb_ss, &usb_ss->regs->ep_traddr, + EP_TRADDR__TRADDR__WRITE(usb_ss_ep->trb_pool_dma)); + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__DRDY__MASK); /* DRDY */ + return 0; +} + +/** + * cdns_get_setup_ret - Returns status of handling setup packet + * Setup is handled by gadget driver + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * + * Returns zero on success or negative value on failure + */ +static int cdns_get_setup_ret(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) +{ + int ret; + + spin_unlock(&usb_ss->lock); + usb_ss->setup_pending = 1; + ret = usb_ss->gadget_driver->setup(&usb_ss->gadget, ctrl_req); + usb_ss->setup_pending = 0; + spin_lock(&usb_ss->lock); + return ret; +} + +static void cdns_prepare_setup_packet(struct usb_ss_dev *usb_ss) +{ + usb_ss->ep0_data_dir = 0; + cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, 8, 0); +} + +/** + * cdns_req_ep0_set_address - Handling of SET_ADDRESS standard USB request + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * + * Returns 0 if success, error code on error + */ +static int cdns_req_ep0_set_address(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) +{ + enum usb_device_state device_state = usb_ss->gadget.state; + u32 reg; + u32 addr; + + addr = le16_to_cpu(ctrl_req->wValue); + + if (addr > DEVICE_ADDRESS_MAX) { + dev_err(&usb_ss->dev, + "Device address (%d) cannot be greater than %d\n", + addr, DEVICE_ADDRESS_MAX); + return -EINVAL; + } + + if (device_state == USB_STATE_CONFIGURED) { + dev_err(&usb_ss->dev, "USB device already configured\n"); + return -EINVAL; + } + + reg = gadget_readl(usb_ss, &usb_ss->regs->usb_cmd); + + gadget_writel(usb_ss, &usb_ss->regs->usb_cmd, reg + | USB_CMD__FADDR__WRITE(addr) + | USB_CMD__SET_ADDR__MASK); + + usb_gadget_set_state(&usb_ss->gadget, + (addr ? USB_STATE_ADDRESS : USB_STATE_DEFAULT)); + + cdns_prepare_setup_packet(usb_ss); + + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK); + return 0; +} + +/** + * cdns_req_ep0_get_status - Handling of GET_STATUS standard USB request + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * + * Returns 0 if success, error code on error + */ +static int cdns_req_ep0_get_status(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) +{ + u16 usb_status = 0; + unsigned int length = 2; + u32 recip = ctrl_req->bRequestType & USB_RECIP_MASK; + u32 reg; + + switch (recip) { + case USB_RECIP_DEVICE: + reg = gadget_readl(usb_ss, &usb_ss->regs->usb_sts); + + if (reg & USB_STS__U1ENS__MASK) + usb_status |= 1uL << USB_DEV_STAT_U1_ENABLED; + + if (reg & USB_STS__U2ENS__MASK) + usb_status |= 1uL << USB_DEV_STAT_U2_ENABLED; + + if (usb_ss->wake_up_flag) + usb_status |= 1uL << USB_DEVICE_REMOTE_WAKEUP; + + /* self powered */ + usb_status |= 1uL << USB_DEVICE_SELF_POWERED; + break; + + case USB_RECIP_INTERFACE: + return cdns_get_setup_ret(usb_ss, ctrl_req); + + case USB_RECIP_ENDPOINT: + /* check if endpoint is stalled */ + select_ep(usb_ss, ctrl_req->wIndex); + if (gadget_readl(usb_ss, &usb_ss->regs->ep_sts) + & EP_STS__STALL__MASK) + usb_status = 1; + break; + + default: + return -EINVAL; + } + + *(u16 *)usb_ss->setup = cpu_to_le16(usb_status); + + usb_ss->actual_ep0_request = NULL; + cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, length, 1); + return 0; +} + +/** + * cdns_req_ep0_handle_feature - + * Handling of GET/SET_FEATURE standard USB request + * + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * @set: must be set to 1 for SET_FEATURE request + * + * Returns 0 if success, error code on error + */ +static int cdns_req_ep0_handle_feature(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req, int set) +{ + u32 recip = ctrl_req->bRequestType & USB_RECIP_MASK; + struct usb_ss_endpoint *usb_ss_ep; + u32 reg; + u8 tmode = 0; + + switch (recip) { + case USB_RECIP_DEVICE: + + switch (ctrl_req->wValue) { + case USB_DEVICE_U1_ENABLE: + if (usb_ss->gadget.state != USB_STATE_CONFIGURED) + return -EINVAL; + if (usb_ss->gadget.speed != USB_SPEED_SUPER) + return -EINVAL; + + reg = gadget_readl(usb_ss, &usb_ss->regs->usb_conf); + if (set) + /* set U1EN */ + reg |= USB_CONF__U1EN__MASK; + else + /* set U1 disable */ + reg |= USB_CONF__U1DS__MASK; + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, reg); + break; + + case USB_DEVICE_U2_ENABLE: + if (usb_ss->gadget.state != USB_STATE_CONFIGURED) + return -EINVAL; + if (usb_ss->gadget.speed != USB_SPEED_SUPER) + return -EINVAL; + + reg = gadget_readl(usb_ss, &usb_ss->regs->usb_conf); + if (set) + /* set U2EN */ + reg |= USB_CONF__U2EN__MASK; + else + /* set U2 disable */ + reg |= USB_CONF__U2DS__MASK; + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, reg); + break; + + case USB_DEVICE_A_ALT_HNP_SUPPORT: + break; + + case USB_DEVICE_A_HNP_SUPPORT: + break; + + case USB_DEVICE_B_HNP_ENABLE: + if (!usb_ss->gadget.b_hnp_enable && set) + usb_ss->gadget.b_hnp_enable = 1; + break; + + case USB_DEVICE_REMOTE_WAKEUP: + usb_ss->wake_up_flag = !!set; + break; + + case USB_DEVICE_TEST_MODE: + if (usb_ss->gadget.state != USB_STATE_CONFIGURED) + return -EINVAL; + if (usb_ss->gadget.speed != USB_SPEED_HIGH && + usb_ss->gadget.speed != USB_SPEED_FULL) + return -EINVAL; + if (ctrl_req->wLength != 0 || + ctrl_req->bRequestType & USB_DIR_IN) { + dev_err(&usb_ss->dev, "req is error\n"); + return -EINVAL; + } + tmode = le16_to_cpu(ctrl_req->wIndex) >> 8; + switch (tmode) { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + reg = gadget_readl(usb_ss, + &usb_ss->regs->usb_cmd); + tmode -= 1; + reg |= USB_CMD__STMODE | + USB_CMD__TMODE_SEL(tmode); + gadget_writel(usb_ss, &usb_ss->regs->usb_cmd, + reg); + dev_info(&usb_ss->dev, + "set test mode, val=0x%x", reg); + break; + default: + return -EINVAL; + } + break; + + default: + return -EINVAL; + } + break; + + case USB_RECIP_INTERFACE: + return cdns_get_setup_ret(usb_ss, ctrl_req); + + case USB_RECIP_ENDPOINT: + select_ep(usb_ss, ctrl_req->wIndex); + + if (set) { + /* set stall */ + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__SSTALL__MASK); + + /* handle non zero endpoint software endpoint */ + if (ctrl_req->wIndex & 0x7F) { + usb_ss_ep = usb_ss->eps[CAST_EP_ADDR_TO_INDEX( + ctrl_req->wIndex)]; + usb_ss_ep->stalled_flag = 1; + } + } else { + struct usb_request *request; + + if (ctrl_req->wIndex & 0x7F) { + if (usb_ss->eps[CAST_EP_ADDR_TO_INDEX( + ctrl_req->wIndex)]->wedge_flag) + goto jmp_wedge; + } + + /* clear stall */ + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__CSTALL__MASK | EP_CMD__EPRST__MASK); + /* wait for EPRST cleared */ + while (gadget_readl(usb_ss, &usb_ss->regs->ep_cmd) + & EP_CMD__EPRST__MASK) + ; + + /* handle non zero endpoint software endpoint */ + if (ctrl_req->wIndex & 0x7F) { + usb_ss_ep = usb_ss->eps[CAST_EP_ADDR_TO_INDEX( + ctrl_req->wIndex)]; + usb_ss_ep->stalled_flag = 0; + + request = next_request( + &usb_ss_ep->request_list); + if (request) + cdns_ep_run_transfer(usb_ss_ep); + } + } +jmp_wedge: + select_ep(usb_ss, 0x00); + break; + + default: + return -EINVAL; + } + + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK); + + return 0; +} + +/** + * cdns_req_ep0_set_sel - Handling of SET_SEL standard USB request + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * + * Returns 0 if success, error code on error + */ +static int cdns_req_ep0_set_sel(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) +{ + if (usb_ss->gadget.state < USB_STATE_ADDRESS) + return -EINVAL; + + if (ctrl_req->wLength != 6) { + dev_err(&usb_ss->dev, "Set SEL should be 6 bytes, got %d\n", + ctrl_req->wLength); + return -EINVAL; + } + + usb_ss->ep0_data_dir = 0; + usb_ss->actual_ep0_request = NULL; + cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, 6, 1); + + return 0; +} + +/** + * cdns_req_ep0_set_isoch_delay - + * Handling of GET_ISOCH_DELAY standard USB request + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * + * Returns 0 if success, error code on error + */ +static int cdns_req_ep0_set_isoch_delay(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) +{ + if (ctrl_req->wIndex || ctrl_req->wLength) + return -EINVAL; + + usb_ss->isoch_delay = ctrl_req->wValue; + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK); + return 0; +} + +/** + * cdns_req_ep0_set_configuration - Handling of SET_CONFIG standard USB request + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * + * Returns 0 if success, 0x7FFF on deferred status stage, error code on error + */ +static int cdns_req_ep0_set_configuration(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) +{ + enum usb_device_state device_state = usb_ss->gadget.state; + u32 config = le16_to_cpu(ctrl_req->wValue); + struct usb_ep *ep; + struct usb_ss_endpoint *usb_ss_ep, *temp_ss_ep; + int i, result = 0; + + switch (device_state) { + case USB_STATE_ADDRESS: + /* Configure non-control EPs */ + list_for_each_entry_safe(usb_ss_ep, temp_ss_ep, + &usb_ss->ep_match_list, ep_match_pending_list) { + cdns_ep_config(usb_ss_ep); + list_del(&usb_ss_ep->ep_match_pending_list); + } + + list_for_each_entry(ep, &(usb_ss->gadget.ep_list), ep_list) { + usb_ss_ep = to_usb_ss_ep(ep); + if (usb_ss_ep->used) + cdns_ep_config(usb_ss_ep); + } + +#ifdef CDNS_THREADED_IRQ_HANDLING + usb_ss->ep_ien = gadget_readl(usb_ss, &usb_ss->regs->ep_ien) + | EP_IEN__EOUTEN0__MASK | EP_IEN__EINEN0__MASK; +#endif + result = cdns_get_setup_ret(usb_ss, ctrl_req); + + if (result != 0) + return result; + + if (config) { + if (!usb_ss->hw_configured_flag) { + /* SET CONFIGURATION */ + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, + USB_CONF__CFGSET__MASK); + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | + EP_CMD__REQ_CMPL__MASK); + /* wait until configuration set */ + while (!(gadget_readl(usb_ss, + &usb_ss->regs->usb_sts) + & USB_STS__CFGSTS__MASK)) + ; + usb_ss->hw_configured_flag = 1; + + list_for_each_entry(ep, + &usb_ss->gadget.ep_list, + ep_list) { + if (to_usb_ss_ep(ep)->enabled) + cdns_ep_run_transfer( + to_usb_ss_ep(ep)); + } + } + + usb_gadget_set_state(&usb_ss->gadget, + USB_STATE_CONFIGURED); + + } else { + cdns_gadget_unconfig(usb_ss); + for (i = 0; i < usb_ss->ep_nums; i++) + usb_ss->eps[i]->enabled = 0; + usb_gadget_set_state(&usb_ss->gadget, + USB_STATE_ADDRESS); + } + break; + + case USB_STATE_CONFIGURED: + result = cdns_get_setup_ret(usb_ss, ctrl_req); + if (!config && !result) { + cdns_gadget_unconfig(usb_ss); + for (i = 0; i < usb_ss->ep_nums; i++) + usb_ss->eps[i]->enabled = 0; + usb_gadget_set_state(&usb_ss->gadget, + USB_STATE_ADDRESS); + } + break; + + default: + result = -EINVAL; + } + + return result; +} + +/** + * cdns_ep0_standard_request - Handling standard USB requests + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * + * Returns 0 if success, error code on error + */ +static int cdns_ep0_standard_request(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) +{ + switch (ctrl_req->bRequest) { + case USB_REQ_SET_ADDRESS: + return cdns_req_ep0_set_address(usb_ss, ctrl_req); + case USB_REQ_SET_CONFIGURATION: + return cdns_req_ep0_set_configuration(usb_ss, ctrl_req); + case USB_REQ_GET_STATUS: + return cdns_req_ep0_get_status(usb_ss, ctrl_req); + case USB_REQ_CLEAR_FEATURE: + return cdns_req_ep0_handle_feature(usb_ss, ctrl_req, 0); + case USB_REQ_SET_FEATURE: + return cdns_req_ep0_handle_feature(usb_ss, ctrl_req, 1); + case USB_REQ_SET_SEL: + return cdns_req_ep0_set_sel(usb_ss, ctrl_req); + case USB_REQ_SET_ISOCH_DELAY: + return cdns_req_ep0_set_isoch_delay(usb_ss, ctrl_req); + default: + return cdns_get_setup_ret(usb_ss, ctrl_req); + } +} + +/** + * cdns_ep0_setup_phase - Handling setup USB requests + * @usb_ss: extended gadget object + */ +static void cdns_ep0_setup_phase(struct usb_ss_dev *usb_ss) +{ + int result; + struct usb_ctrlrequest *ctrl_req = + (struct usb_ctrlrequest *)usb_ss->setup; + + if ((ctrl_req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) + result = cdns_ep0_standard_request(usb_ss, ctrl_req); + else + result = cdns_get_setup_ret(usb_ss, ctrl_req); + + if (result != 0 && result != USB_GADGET_DELAYED_STATUS) { + dev_dbg(&usb_ss->dev, "STALL(00) %d\n", result); + + /* set_stall on ep0 */ + select_ep(usb_ss, 0x00); + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__SSTALL__MASK); + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK); + return; + } +} + +/** + * cdns_check_ep_interrupt_proceed - Processes interrupt related to endpoint + * @usb_ss_ep: extended endpoint object + * + * Returns 0 + */ +static int cdns_check_ep_interrupt_proceed(struct usb_ss_endpoint *usb_ss_ep) +{ + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + struct usb_request *request; + u32 ep_sts_reg; + + select_ep(usb_ss, usb_ss_ep->address); + ep_sts_reg = gadget_readl(usb_ss, &usb_ss->regs->ep_sts); + + dev_dbg(&usb_ss->dev, "EP_STS: %08X\n", ep_sts_reg); + + if (ep_sts_reg & EP_STS__TRBERR__MASK) { + gadget_writel(usb_ss, + &usb_ss->regs->ep_sts, EP_STS__TRBERR__MASK); + + dev_dbg(&usb_ss->dev, "TRBERR(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); + } + + if (ep_sts_reg & EP_STS__ISOERR__MASK) { + gadget_writel(usb_ss, + &usb_ss->regs->ep_sts, EP_STS__ISOERR__MASK); + dev_dbg(&usb_ss->dev, "ISOERR(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); + } + + if (ep_sts_reg & EP_STS__OUTSMM__MASK) { + gadget_writel(usb_ss, &usb_ss->regs->ep_sts, + EP_STS__OUTSMM__MASK); + dev_dbg(&usb_ss->dev, "OUTSMM(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); + } + + if (ep_sts_reg & EP_STS__NRDY__MASK) { + gadget_writel(usb_ss, + &usb_ss->regs->ep_sts, EP_STS__NRDY__MASK); + dev_dbg(&usb_ss->dev, "NRDY(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); + } + + if ((ep_sts_reg & EP_STS__IOC__MASK) + || (ep_sts_reg & EP_STS__ISP__MASK)) { + cdns_flush_cache((uintptr_t)usb_ss_ep->trb_pool, sizeof(struct usb_ss_trb)); + + gadget_writel(usb_ss, &usb_ss->regs->ep_sts, + EP_STS__IOC__MASK | EP_STS__ISP__MASK); + + /* get just completed request */ + request = next_request(&usb_ss_ep->request_list); + usb_gadget_unmap_request(&usb_ss->gadget, request, + usb_ss_ep->endpoint.desc->bEndpointAddress + & ENDPOINT_DIR_MASK); + + request->status = 0; + request->actual = + le32_to_cpu(((u32 *)usb_ss_ep->trb_pool)[1]) + & ACTUAL_TRANSFERRED_BYTES_MASK; + + dev_dbg(&usb_ss->dev, "IOC(%02X) %d\n", + usb_ss_ep->endpoint.desc->bEndpointAddress, + request->actual); + + list_del(&request->list); + + usb_ss_ep->hw_pending_flag = 0; + if (request->complete) { + spin_unlock(&usb_ss->lock); + usb_gadget_giveback_request(&usb_ss_ep->endpoint, + request); + spin_lock(&usb_ss->lock); + } + + /* handle deferred STALL */ + if (usb_ss_ep->stalled_flag) { + cdns_ep_stall_flush(usb_ss_ep); + return 0; + } + + /* exit if hardware transfer already started */ + if (usb_ss_ep->hw_pending_flag) + return 0; + + /* if any request queued run it! */ + if (!list_empty(&usb_ss_ep->request_list)) + cdns_ep_run_transfer(usb_ss_ep); + } + + if (ep_sts_reg & EP_STS__DESCMIS__MASK) { + gadget_writel(usb_ss, + &usb_ss->regs->ep_sts, EP_STS__DESCMIS__MASK); + dev_dbg(&usb_ss->dev, "DESCMIS(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); + } + + return 0; +} + +/** + * cdns_check_ep0_interrupt_proceed - Processes interrupt related to endpoint 0 + * @usb_ss: extended gadget object + * @dir: 1 for IN direction, 0 for OUT direction + */ +static void cdns_check_ep0_interrupt_proceed(struct usb_ss_dev *usb_ss, int dir) +{ + u32 ep_sts_reg; + int i; + + select_ep(usb_ss, 0 | (dir ? USB_DIR_IN : USB_DIR_OUT)); + ep_sts_reg = gadget_readl(usb_ss, &usb_ss->regs->ep_sts); + + dev_dbg(&usb_ss->dev, "EP_STS: %08X\n", ep_sts_reg); + + if ((ep_sts_reg & EP_STS__SETUP__MASK) && (dir == 0)) { + cdns_flush_cache((uintptr_t)usb_ss->setup, 8); + + dev_dbg(&usb_ss->dev, "SETUP(%02X)\n", 0x00); + + gadget_writel(usb_ss, &usb_ss->regs->ep_sts, + EP_STS__SETUP__MASK | + EP_STS__IOC__MASK | EP_STS__ISP__MASK); + + dev_dbg(&usb_ss->dev, "SETUP: "); + for (i = 0; i < 8; i++) + dev_dbg(&usb_ss->dev, "%02X ", usb_ss->setup[i]); + dev_dbg(&usb_ss->dev, "\nSTATE: %d\n", usb_ss->gadget.state); + usb_ss->ep0_data_dir = usb_ss->setup[0] & USB_DIR_IN; + cdns_ep0_setup_phase(usb_ss); + ep_sts_reg &= ~(EP_STS__SETUP__MASK | + EP_STS__IOC__MASK | + EP_STS__ISP__MASK); + } + + if (ep_sts_reg & EP_STS__TRBERR__MASK) { + gadget_writel(usb_ss, + &usb_ss->regs->ep_sts, EP_STS__TRBERR__MASK); + dev_dbg(&usb_ss->dev, "TRBERR(%02X)\n", + dir ? USB_DIR_IN : USB_DIR_OUT); + } + + if (ep_sts_reg & EP_STS__DESCMIS__MASK) { + gadget_writel(usb_ss, + &usb_ss->regs->ep_sts, EP_STS__DESCMIS__MASK); + + dev_dbg(&usb_ss->dev, "DESCMIS(%02X)\n", + dir ? USB_DIR_IN : USB_DIR_OUT); + + if (dir == 0 && !usb_ss->setup_pending) { + usb_ss->ep0_data_dir = 0; + cdns_ep0_run_transfer(usb_ss, + usb_ss->setup_dma, 8, 0); + } + } + + if ((ep_sts_reg & EP_STS__IOC__MASK) || + (ep_sts_reg & EP_STS__ISP__MASK)) { + cdns_flush_cache((uintptr_t)usb_ss->trb_ep0, 20); + + gadget_writel(usb_ss, + &usb_ss->regs->ep_sts, EP_STS__IOC__MASK); + if (usb_ss->actual_ep0_request) { + usb_gadget_unmap_request(&usb_ss->gadget, + usb_ss->actual_ep0_request, + usb_ss->ep0_data_dir); + + usb_ss->actual_ep0_request->actual = + le32_to_cpu((usb_ss->trb_ep0)[1]) + & ACTUAL_TRANSFERRED_BYTES_MASK; + + dev_dbg(&usb_ss->dev, "IOC(%02X) %d\n", + dir ? USB_DIR_IN : USB_DIR_OUT, + usb_ss->actual_ep0_request->actual); + list_del_init(&usb_ss->actual_ep0_request->list); + } + + if (usb_ss->actual_ep0_request && + usb_ss->actual_ep0_request->complete) { + spin_unlock(&usb_ss->lock); + usb_ss->actual_ep0_request->complete(usb_ss->gadget.ep0, + usb_ss->actual_ep0_request); + spin_lock(&usb_ss->lock); + } + cdns_prepare_setup_packet(usb_ss); + gadget_writel(usb_ss, + &usb_ss->regs->ep_cmd, EP_CMD__REQ_CMPL__MASK); + } +} + +/** + * cdns_check_usb_interrupt_proceed - Processes interrupt related to device + * @usb_ss: extended gadget object + * @usb_ists: bitmap representation of device's reported interrupts + * (usb_ists register value) + */ +static void cdns_check_usb_interrupt_proceed(struct usb_ss_dev *usb_ss, + u32 usb_ists) +{ + int interrupt_bit = ffs(usb_ists) - 1; + int speed; + u32 val; + + dev_dbg(&usb_ss->dev, "USB interrupt detected\n"); + + switch (interrupt_bit) { + case USB_ISTS__CON2I__SHIFT: + /* FS/HS Connection detected */ + dev_dbg(&usb_ss->dev, + "[Interrupt] FS/HS Connection detected\n"); + val = gadget_readl(usb_ss, &usb_ss->regs->usb_sts); + speed = USB_STS__USBSPEED__READ(val); + if (speed == USB_SPEED_WIRELESS) + speed = USB_SPEED_SUPER; + dev_dbg(&usb_ss->dev, "Speed value: %s (%d), usbsts:0x%x\n", + usb_speed_string(speed), speed, val); + usb_ss->gadget.speed = speed; + usb_ss->is_connected = 1; + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_POWERED); + cdns_ep0_config(usb_ss); + break; + + case USB_ISTS__CONI__SHIFT: + /* SS Connection detected */ + dev_dbg(&usb_ss->dev, "[Interrupt] SS Connection detected\n"); + val = gadget_readl(usb_ss, &usb_ss->regs->usb_sts); + speed = USB_STS__USBSPEED__READ(val); + if (speed == USB_SPEED_WIRELESS) + speed = USB_SPEED_SUPER; + dev_dbg(&usb_ss->dev, "Speed value: %s (%d), usbsts:0x%x\n", + usb_speed_string(speed), speed, val); + usb_ss->gadget.speed = speed; + usb_ss->is_connected = 1; + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_POWERED); + cdns_ep0_config(usb_ss); + break; + + case USB_ISTS__DIS2I__SHIFT: + case USB_ISTS__DISI__SHIFT: + /* SS Disconnection detected */ + val = gadget_readl(usb_ss, &usb_ss->regs->usb_sts); + dev_dbg(&usb_ss->dev, + "[Interrupt] Disconnection detected: usbsts:0x%x\n", + val); + if (usb_ss->gadget_driver && + usb_ss->gadget_driver->disconnect) { + spin_unlock(&usb_ss->lock); + usb_ss->gadget_driver->disconnect(&usb_ss->gadget); + spin_lock(&usb_ss->lock); + } + usb_ss->gadget.speed = USB_SPEED_UNKNOWN; + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_NOTATTACHED); + usb_ss->is_connected = 0; + cdns_gadget_unconfig(usb_ss); + break; + + case USB_ISTS__L2ENTI__SHIFT: + dev_dbg(&usb_ss->dev, + "[Interrupt] Device suspended\n"); + break; + + case USB_ISTS__L2EXTI__SHIFT: + dev_dbg(&usb_ss->dev, "[Interrupt] L2 exit detected\n"); + /* + * Exit from standby mode + * on L2 exit (Suspend in HS/FS or SS) + */ + break; + case USB_ISTS__U3EXTI__SHIFT: + /* + * Exit from standby mode + * on U3 exit (Suspend in HS/FS or SS) + */ + dev_dbg(&usb_ss->dev, "[Interrupt] U3 exit detected\n"); + break; + + /* resets cases */ + case USB_ISTS__UWRESI__SHIFT: + case USB_ISTS__UHRESI__SHIFT: + case USB_ISTS__U2RESI__SHIFT: + dev_dbg(&usb_ss->dev, "[Interrupt] Reset detected\n"); + speed = USB_STS__USBSPEED__READ( + gadget_readl(usb_ss, &usb_ss->regs->usb_sts)); + if (speed == USB_SPEED_WIRELESS) + speed = USB_SPEED_SUPER; + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_DEFAULT); + usb_ss->gadget.speed = speed; + cdns_gadget_unconfig(usb_ss); + cdns_ep0_config(usb_ss); + break; + default: + break; + } + + /* Clear interrupt bit */ + gadget_writel(usb_ss, &usb_ss->regs->usb_ists, (1uL << interrupt_bit)); +} + +#ifdef CDNS_THREADED_IRQ_HANDLING +static irqreturn_t cdns_irq_handler(int irq, void *_usb_ss) +{ + struct usb_ss_dev *usb_ss = _usb_ss; + + usb_ss->usb_ien = gadget_readl(usb_ss, &usb_ss->regs->usb_ien); + usb_ss->ep_ien = gadget_readl(usb_ss, &usb_ss->regs->ep_ien); + + if (!gadget_readl(usb_ss, &usb_ss->regs->usb_ists) && + !gadget_readl(usb_ss, &usb_ss->regs->ep_ists)) { + dev_dbg(&usb_ss->dev, "--BUBBLE INTERRUPT 0 !!!\n"); + if (gadget_readl(usb_ss, &usb_ss->regs->usb_sts) & + USB_STS__CFGSTS__MASK) + return IRQ_HANDLED; + return IRQ_NONE; + } + + gadget_writel(usb_ss, &usb_ss->regs->usb_ien, 0); + gadget_writel(usb_ss, &usb_ss->regs->ep_ien, 0); + + gadget_readl(usb_ss, &usb_ss->regs->dma_axi_ctrl); + return IRQ_WAKE_THREAD; +} +#endif + +/** + * cdns_irq_handler - irq line interrupt handler + * @cdns: cdns3 instance + * + * Returns IRQ_HANDLED when interrupt raised by USBSS_DEV, + * IRQ_NONE when interrupt raised by other device connected + * to the irq line + */ +static int cdns_irq_handler_thread(struct cdns3 *cdns) +{ + struct usb_ss_dev *usb_ss = + container_of(cdns->gadget_dev, struct usb_ss_dev, dev); + u32 reg; + int ret = IRQ_NONE; + unsigned long flags; + + spin_lock_irqsave(&usb_ss->lock, flags); + + /* check USB device interrupt */ + reg = gadget_readl(usb_ss, &usb_ss->regs->usb_ists); + if (reg) { + dev_dbg(&usb_ss->dev, "usb_ists: %08X\n", reg); + cdns_check_usb_interrupt_proceed(usb_ss, reg); + ret = IRQ_HANDLED; + } + + /* check endpoint interrupt */ + reg = gadget_readl(usb_ss, &usb_ss->regs->ep_ists); + if (reg != 0) { + dev_dbg(&usb_ss->dev, "ep_ists: %08X\n", reg); + } else { + if (gadget_readl(usb_ss, &usb_ss->regs->usb_sts) & + USB_STS__CFGSTS__MASK) + ret = IRQ_HANDLED; + goto irqend; + } + + /* handle default endpoint OUT */ + if (reg & EP_ISTS__EOUT0__MASK) { + cdns_check_ep0_interrupt_proceed(usb_ss, 0); + ret = IRQ_HANDLED; + } + + /* handle default endpoint IN */ + if (reg & EP_ISTS__EIN0__MASK) { + cdns_check_ep0_interrupt_proceed(usb_ss, 1); + ret = IRQ_HANDLED; + } + + /* check if interrupt from non default endpoint, if no exit */ + reg &= ~(EP_ISTS__EOUT0__MASK | EP_ISTS__EIN0__MASK); + if (!reg) + goto irqend; + + do { + unsigned int bit_pos = ffs(reg); + u32 bit_mask = 1 << (bit_pos - 1); + + dev_dbg(&usb_ss->dev, "Interrupt on index: %d bitmask %08X\n", + CAST_EP_REG_POS_TO_INDEX(bit_pos), bit_mask); + cdns_check_ep_interrupt_proceed( + usb_ss->eps[CAST_EP_REG_POS_TO_INDEX(bit_pos)]); + reg &= ~bit_mask; + ret = IRQ_HANDLED; + } while (reg); + +irqend: + + spin_unlock_irqrestore(&usb_ss->lock, flags); +#ifdef CDNS_THREADED_IRQ_HANDLING + local_irq_save(flags); + gadget_writel(usb_ss, &usb_ss->regs->usb_ien, usb_ss->usb_ien); + gadget_writel(usb_ss, &usb_ss->regs->ep_ien, usb_ss->ep_ien); + local_irq_restore(flags); +#endif + return ret; +} + +/** + * usb_ss_gadget_ep0_enable + * Function shouldn't be called by gadget driver, + * endpoint 0 is allways active + */ +static int usb_ss_gadget_ep0_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc) +{ + return -EINVAL; +} + +/** + * usb_ss_gadget_ep0_disable + * Function shouldn't be called by gadget driver, + * endpoint 0 is allways active + */ +static int usb_ss_gadget_ep0_disable(struct usb_ep *ep) +{ + return -EINVAL; +} + +/** + * usb_ss_gadget_ep0_set_halt + * @ep: pointer to endpoint zero object + * @value: 1 for set stall, 0 for clear stall + * + * Returns 0 + */ +static int usb_ss_gadget_ep0_set_halt(struct usb_ep *ep, int value) +{ + /* TODO */ + return 0; +} + +/** + * usb_ss_gadget_ep0_queue Transfer data on endpoint zero + * @ep: pointer to endpoint zero object + * @request: pointer to request object + * @gfp_flags: gfp flags + * + * Returns 0 on success, error code elsewhere + */ +static int usb_ss_gadget_ep0_queue(struct usb_ep *ep, + struct usb_request *request, gfp_t gfp_flags) +{ + int ret; + unsigned long flags; + int erdy_sent = 0; + /* get extended endpoint */ + struct usb_ss_endpoint *usb_ss_ep = + to_usb_ss_ep(ep); + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + + dev_dbg(&usb_ss->dev, "QUEUE(%02X) %d\n", + usb_ss->ep0_data_dir ? USB_DIR_IN : USB_DIR_OUT, + request->length); + + /* send STATUS stage */ + if (request->length == 0 && request->zero == 0) { + spin_lock_irqsave(&usb_ss->lock, flags); + select_ep(usb_ss, 0x00); + if (!usb_ss->hw_configured_flag) { + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, + USB_CONF__CFGSET__MASK); /* SET CONFIGURATION */ + cdns_prepare_setup_packet(usb_ss); + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK); + /* wait until configuration set */ + while (!(gadget_readl(usb_ss, &usb_ss->regs->usb_sts) + & USB_STS__CFGSTS__MASK)) + ; + erdy_sent = 1; + usb_ss->hw_configured_flag = 1; + + list_for_each_entry(ep, + &usb_ss->gadget.ep_list, + ep_list) { + if (to_usb_ss_ep(ep)->enabled) + cdns_ep_run_transfer( + to_usb_ss_ep(ep)); + } + } + if (!erdy_sent) + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK); + if (request->complete) + request->complete(usb_ss->gadget.ep0, request); + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; + } + + spin_lock_irqsave(&usb_ss->lock, flags); + ret = usb_gadget_map_request(&usb_ss->gadget, request, + usb_ss->ep0_data_dir); + if (ret) { + dev_err(&usb_ss->dev, "failed to map request\n"); + return -EINVAL; + } + + usb_ss->actual_ep0_request = request; + cdns_ep0_run_transfer(usb_ss, request->dma, request->length, 1); + list_add_tail(&request->list, &usb_ss_ep->request_list); + spin_unlock_irqrestore(&usb_ss->lock, flags); + + return 0; +} + +/** + * cdns_ep_config Configure hardware endpoint + * @usb_ss_ep: extended endpoint object + */ +static void cdns_ep_config(struct usb_ss_endpoint *usb_ss_ep) +{ + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + u32 ep_cfg = 0; + u32 max_packet_size = 0; + u32 bEndpointAddress = usb_ss_ep->num | usb_ss_ep->dir; + u32 interrupt_mask = 0; + bool is_iso_ep = (usb_ss_ep->type == USB_ENDPOINT_XFER_ISOC); + + dev_dbg(&usb_ss->dev, "%s: %s addr=0x%x, speed %d, is_iso_ep %d\n", __func__, + usb_ss_ep->name, bEndpointAddress, usb_ss->gadget.speed, is_iso_ep); + + if (is_iso_ep) { + ep_cfg = EP_CFG__EPTYPE__WRITE(USB_ENDPOINT_XFER_ISOC); + interrupt_mask = INTERRUPT_MASK; + } else { + ep_cfg = EP_CFG__EPTYPE__WRITE(USB_ENDPOINT_XFER_BULK); + } + + switch (usb_ss->gadget.speed) { + case USB_SPEED_UNKNOWN: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_0; + break; + + case USB_SPEED_LOW: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_8; + break; + + case USB_SPEED_FULL: + max_packet_size = (is_iso_ep ? + ENDPOINT_MAX_PACKET_SIZE_1023 : + ENDPOINT_MAX_PACKET_SIZE_64); + break; + + case USB_SPEED_HIGH: + max_packet_size = (is_iso_ep ? + ENDPOINT_MAX_PACKET_SIZE_1024 : + ENDPOINT_MAX_PACKET_SIZE_512); + break; + + case USB_SPEED_WIRELESS: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_512; + break; + + case USB_SPEED_SUPER: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_1024; + break; + } + + ep_cfg |= EP_CFG__MAXPKTSIZE__WRITE(max_packet_size); + + if (is_iso_ep) { + ep_cfg |= EP_CFG__BUFFERING__WRITE(1); + ep_cfg |= EP_CFG__MAXBURST__WRITE(0); + } else { + ep_cfg |= EP_CFG__BUFFERING__WRITE(3); + ep_cfg |= EP_CFG__MAXBURST__WRITE(15); + } + + select_ep(usb_ss, bEndpointAddress); + gadget_writel(usb_ss, &usb_ss->regs->ep_cfg, ep_cfg); + gadget_writel(usb_ss, &usb_ss->regs->ep_sts_en, + EP_STS_EN__TRBERREN__MASK | interrupt_mask); + + /* enable interrupt for selected endpoint */ + ep_cfg = gadget_readl(usb_ss, &usb_ss->regs->ep_ien); + ep_cfg |= CAST_EP_ADDR_TO_BIT_POS(bEndpointAddress); + gadget_writel(usb_ss, &usb_ss->regs->ep_ien, ep_cfg); +} + +/** + * usb_ss_gadget_ep_enable Enable endpoint + * @ep: endpoint object + * @desc: endpoint descriptor + * + * Returns 0 on success, error code elsewhere + */ +static int usb_ss_gadget_ep_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc) +{ + struct usb_ss_endpoint *usb_ss_ep; + struct usb_ss_dev *usb_ss; + unsigned long flags; + int ret; + u32 ep_cfg; + + usb_ss_ep = to_usb_ss_ep(ep); + usb_ss = usb_ss_ep->usb_ss; + + if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { + dev_err(&usb_ss->dev, "usb-ss: invalid parameters\n"); + return -EINVAL; + } + + if (!desc->wMaxPacketSize) { + dev_err(&usb_ss->dev, "usb-ss: missing wMaxPacketSize\n"); + return -EINVAL; + } + + ret = usb_ss_allocate_trb_pool(usb_ss_ep); + if (ret) + return ret; + + if (!usb_ss_ep->cpu_addr) { + usb_ss_ep->cpu_addr = dma_alloc_coherent(4096, + (unsigned long *)&usb_ss_ep->dma_addr); + + if (!usb_ss_ep->cpu_addr) + return -ENOMEM; + } + + dev_dbg(&usb_ss->dev, "Enabling endpoint: %s, addr=0x%x\n", + ep->name, desc->bEndpointAddress); + spin_lock_irqsave(&usb_ss->lock, flags); + select_ep(usb_ss, desc->bEndpointAddress); + ep_cfg = gadget_readl(usb_ss, &usb_ss->regs->ep_cfg); + ep_cfg |= EP_CFG__ENABLE__MASK; + gadget_writel(usb_ss, &usb_ss->regs->ep_cfg, ep_cfg); + + usb_ss_ep->enabled = 1; + ep->desc = desc; + usb_ss_ep->hw_pending_flag = 0; + spin_unlock_irqrestore(&usb_ss->lock, flags); + + return 0; +} + +static int usb_ss_gadget_match_ep(struct usb_gadget *gadget, + struct usb_ep *ep, + struct usb_endpoint_descriptor *desc) +{ + struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget); + struct usb_ss_endpoint *usb_ss_ep; + unsigned long flags; + + usb_ss_ep = to_usb_ss_ep(ep); + + dev_dbg(&usb_ss->dev, "match endpoint: %s\n", usb_ss_ep->name); + + u8 num = simple_strtoul(&ep->name[2], NULL, 10); + + spin_lock_irqsave(&usb_ss->lock, flags); + usb_ss_ep->num = num; + usb_ss_ep->used = true; + usb_ss_ep->endpoint.desc = desc; + usb_ss_ep->dir = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT; + usb_ss_ep->type = usb_endpoint_type(desc); + usb_ss_ep->address = desc->bEndpointAddress; + spin_unlock_irqrestore(&usb_ss->lock, flags); + + return 1; +} + +static void usb_ss_free_trb_pool(struct usb_ss_endpoint *usb_ss_ep) +{ + if (usb_ss_ep->trb_pool) { + dma_free_coherent(usb_ss_ep->trb_pool); + usb_ss_ep->trb_pool = NULL; + } + + if (usb_ss_ep->cpu_addr) { + dma_free_coherent(usb_ss_ep->cpu_addr); + usb_ss_ep->cpu_addr = NULL; + } +} + +/** + * usb_ss_gadget_ep_disable Disable endpoint + * @ep: endpoint object + * + * Returns 0 on success, error code elsewhere + */ +static int usb_ss_gadget_ep_disable(struct usb_ep *ep) +{ + struct usb_ss_endpoint *usb_ss_ep; + struct usb_ss_dev *usb_ss; + unsigned long flags; + int ret = 0; + struct usb_request *request; + u32 ep_cfg; + + if (!ep) { + pr_debug("usb-ss: invalid parameters\n"); + return -EINVAL; + } + + usb_ss_ep = to_usb_ss_ep(ep); + usb_ss = usb_ss_ep->usb_ss; + + spin_lock_irqsave(&usb_ss->lock, flags); + if (!usb_ss->start_gadget) { + dev_dbg(&usb_ss->dev, + "Disabling endpoint at disconnection: %s\n", ep->name); + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; + } + + dev_dbg(&usb_ss->dev, + "Disabling endpoint: %s\n", ep->name); + + while (!list_empty(&usb_ss_ep->request_list)) { + + request = next_request(&usb_ss_ep->request_list); + usb_gadget_unmap_request(&usb_ss->gadget, request, + ep->desc->bEndpointAddress & USB_DIR_IN); + request->status = -ESHUTDOWN; + list_del(&request->list); + spin_unlock(&usb_ss->lock); + usb_gadget_giveback_request(ep, request); + spin_lock(&usb_ss->lock); + } + + select_ep(usb_ss, ep->desc->bEndpointAddress); + ep_cfg = gadget_readl(usb_ss, &usb_ss->regs->ep_cfg); + ep_cfg &= ~EP_CFG__ENABLE__MASK; + gadget_writel(usb_ss, &usb_ss->regs->ep_cfg, ep_cfg); + ep->desc = NULL; + usb_ss_ep->enabled = 0; + + spin_unlock_irqrestore(&usb_ss->lock, flags); + + return ret; +} + +/** + * usb_ss_gadget_ep_alloc_request Allocates request + * @ep: endpoint object associated with request + * @gfp_flags: gfp flags + * + * Returns allocated request address, NULL on allocation error + */ +static struct usb_request *usb_ss_gadget_ep_alloc_request(struct usb_ep *ep, + gfp_t gfp_flags) +{ + struct usb_request *request; + + request = kzalloc(sizeof(struct usb_request), gfp_flags); + if (!request) + return NULL; + + return request; +} + +/** + * usb_ss_gadget_ep_free_request Free memory occupied by request + * @ep: endpoint object associated with request + * @request: request to free memory + */ +static void usb_ss_gadget_ep_free_request(struct usb_ep *ep, + struct usb_request *request) +{ + kfree(request); +} + +/** + * usb_ss_gadget_ep_queue Transfer data on endpoint + * @ep: endpoint object + * @request: request object + * @gfp_flags: gfp flags + * + * Returns 0 on success, error code elsewhere + */ +static int usb_ss_gadget_ep_queue(struct usb_ep *ep, + struct usb_request *request, gfp_t gfp_flags) +{ + struct usb_ss_endpoint *usb_ss_ep = + to_usb_ss_ep(ep); + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + unsigned long flags; + int ret = 0; + int empty_list = 0; + + spin_lock_irqsave(&usb_ss->lock, flags); + + request->actual = 0; + request->status = -EINPROGRESS; + + dev_dbg(&usb_ss->dev, + "Queuing endpoint: %s\n", usb_ss_ep->name); + + dev_dbg(&usb_ss->dev, "QUEUE(%02X) %d\n", + ep->desc->bEndpointAddress, request->length); + + ret = usb_gadget_map_request(&usb_ss->gadget, request, + ep->desc->bEndpointAddress & USB_DIR_IN); + + if (ret) { + spin_unlock_irqrestore(&usb_ss->lock, flags); + return ret; + } + + empty_list = list_empty(&usb_ss_ep->request_list); + list_add_tail(&request->list, &usb_ss_ep->request_list); + + if (!usb_ss->hw_configured_flag) { + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; + } + + if (empty_list) { + if (!usb_ss_ep->stalled_flag) + cdns_ep_run_transfer(usb_ss_ep); + } + spin_unlock_irqrestore(&usb_ss->lock, flags); + + return ret; +} + +/** + * usb_ss_gadget_ep_dequeue Remove request from transfer queue + * @ep: endpoint object associated with request + * @request: request object + * + * Returns 0 on success, error code elsewhere + */ +static int usb_ss_gadget_ep_dequeue(struct usb_ep *ep, + struct usb_request *request) +{ + struct usb_ss_endpoint *usb_ss_ep = + to_usb_ss_ep(ep); + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + struct usb_request *req, *req_temp; + unsigned long flags; + + spin_lock_irqsave(&usb_ss->lock, flags); + if (!usb_ss->start_gadget) { + dev_dbg(&usb_ss->dev, + "DEQUEUE at disconnection: %s\n", ep->name); + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; + } + dev_dbg(&usb_ss->dev, "DEQUEUE(%02X) %d\n", + usb_ss_ep->address, request->length); + + list_for_each_entry_safe(req, req_temp, + &usb_ss_ep->request_list, list) { + if (request == req) { + request->status = -ECONNRESET; + usb_gadget_unmap_request(&usb_ss->gadget, request, + usb_ss_ep->address & USB_DIR_IN); + list_del_init(&request->list); + if (request->complete) { + spin_unlock(&usb_ss->lock); + usb_gadget_giveback_request + (&usb_ss_ep->endpoint, request); + spin_lock(&usb_ss->lock); + } + break; + } + } + + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; +} + +/** + * usb_ss_gadget_ep_set_halt Sets/clears stall on selected endpoint + * @ep: endpoint object to set/clear stall on + * @value: 1 for set stall, 0 for clear stall + * + * Returns 0 on success, error code elsewhere + */ +static int usb_ss_gadget_ep_set_halt(struct usb_ep *ep, int value) +{ + struct usb_ss_endpoint *usb_ss_ep = + to_usb_ss_ep(ep); + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + unsigned long flags; + + /* return error when endpoint disabled */ + if (!usb_ss_ep->enabled) + return -EPERM; + + /* if actual transfer is pending defer setting stall on this endpoint */ + if (usb_ss_ep->hw_pending_flag && value) { + usb_ss_ep->stalled_flag = 1; + return 0; + } + + dev_dbg(&usb_ss->dev, "HALT(%02X) %d\n", usb_ss_ep->address, value); + + spin_lock_irqsave(&usb_ss->lock, flags); + + select_ep(usb_ss, ep->desc->bEndpointAddress); + if (value) { + cdns_ep_stall_flush(usb_ss_ep); + } else { + /* + * TODO: + * epp->wedgeFlag = 0; + */ + usb_ss_ep->wedge_flag = 0; + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__CSTALL__MASK | EP_CMD__EPRST__MASK); + /* wait for EPRST cleared */ + while (gadget_readl(usb_ss, + &usb_ss->regs->ep_cmd) & EP_CMD__EPRST__MASK) + ; + usb_ss_ep->stalled_flag = 0; + } + usb_ss_ep->hw_pending_flag = 0; + + spin_unlock_irqrestore(&usb_ss->lock, flags); + + return 0; +} + +/** + * usb_ss_gadget_ep_set_wedge Set wedge on selected endpoint + * @ep: endpoint object + * + * Returns 0 + */ +static int usb_ss_gadget_ep_set_wedge(struct usb_ep *ep) +{ + struct usb_ss_endpoint *usb_ss_ep = to_usb_ss_ep(ep); + struct usb_ss_dev __maybe_unused *usb_ss = usb_ss_ep->usb_ss; + + dev_dbg(&usb_ss->dev, "WEDGE(%02X)\n", usb_ss_ep->address); + usb_ss_gadget_ep_set_halt(ep, 1); + usb_ss_ep->wedge_flag = 1; + return 0; +} + +static const struct usb_ep_ops usb_ss_gadget_ep0_ops = { + .enable = usb_ss_gadget_ep0_enable, + .disable = usb_ss_gadget_ep0_disable, + .alloc_request = usb_ss_gadget_ep_alloc_request, + .free_request = usb_ss_gadget_ep_free_request, + .queue = usb_ss_gadget_ep0_queue, + .dequeue = usb_ss_gadget_ep_dequeue, + .set_halt = usb_ss_gadget_ep0_set_halt, + .set_wedge = usb_ss_gadget_ep_set_wedge, +}; + +static const struct usb_ep_ops usb_ss_gadget_ep_ops = { + .enable = usb_ss_gadget_ep_enable, + .disable = usb_ss_gadget_ep_disable, + .alloc_request = usb_ss_gadget_ep_alloc_request, + .free_request = usb_ss_gadget_ep_free_request, + .queue = usb_ss_gadget_ep_queue, + .dequeue = usb_ss_gadget_ep_dequeue, + .set_halt = usb_ss_gadget_ep_set_halt, + .set_wedge = usb_ss_gadget_ep_set_wedge, +}; + +/** + * usb_ss_gadget_get_frame Returns number of actual ITP frame + * @gadget: gadget object + * + * Returns number of actual ITP frame + */ +static int usb_ss_gadget_get_frame(struct usb_gadget *gadget) +{ + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget); + + dev_dbg(&usb_ss->dev, "usb_ss_gadget_get_frame\n"); + return gadget_readl(usb_ss, &usb_ss->regs->usb_iptn); +} + +static int usb_ss_gadget_wakeup(struct usb_gadget *gadget) +{ + struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget); + + dev_dbg(&usb_ss->dev, "usb_ss_gadget_wakeup\n"); + return 0; +} + +static int usb_ss_gadget_set_selfpowered(struct usb_gadget *gadget, + int is_selfpowered) +{ + struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget); + + dev_dbg(&usb_ss->dev, "usb_ss_gadget_set_selfpowered: %d\n", + is_selfpowered); + return 0; +} + +static int usb_ss_gadget_pullup(struct usb_gadget *gadget, int is_on) +{ + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget); + + if (!usb_ss->start_gadget) + return 0; + + dev_dbg(&usb_ss->dev, "usb_ss_gadget_pullup: %d\n", is_on); + + if (is_on) + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, + USB_CONF__DEVEN__MASK); + else + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, + USB_CONF__DEVDS__MASK); + + return 0; +} + +/** + * usb_ss_gadget_udc_start Gadget start + * @gadget: gadget object + * @driver: driver which operates on this gadget + * + * Returns 0 on success, error code elsewhere + */ +static int usb_ss_gadget_udc_start(struct usb_gadget *gadget, + struct usb_gadget_driver *driver) +{ + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget); + unsigned long flags; + + if (usb_ss->gadget_driver) { + dev_err(&usb_ss->dev, "%s is already bound\n", + usb_ss->gadget.name); + return -EBUSY; + } + + dev_dbg(&usb_ss->dev, "%s begins\n", __func__); + + spin_lock_irqsave(&usb_ss->lock, flags); + usb_ss->gadget_driver = driver; + if (!usb_ss->start_gadget) { + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; + } + + __cdns3_gadget_start(usb_ss); + spin_unlock_irqrestore(&usb_ss->lock, flags); + dev_dbg(&usb_ss->dev, "%s ends\n", __func__); + + return 0; +} + +/** + * usb_ss_gadget_udc_stop Stops gadget + * @gadget: gadget object + * + * Returns 0 + */ +static int usb_ss_gadget_udc_stop(struct usb_gadget *gadget) +{ + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget); + struct usb_ep *ep; + struct usb_ss_endpoint *usb_ss_ep; + int i; + u32 bEndpointAddress; + + usb_ss->gadget_driver = NULL; + if (!usb_ss->start_gadget) + return 0; + + list_for_each_entry(ep, &usb_ss->gadget.ep_list, ep_list) { + usb_ss_ep = to_usb_ss_ep(ep); + bEndpointAddress = usb_ss_ep->num | usb_ss_ep->dir; + usb_ss_ep->used = false; + select_ep(usb_ss, bEndpointAddress); + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd, + EP_CMD__EPRST__MASK); + while (gadget_readl(usb_ss, &usb_ss->regs->ep_cmd) + & EP_CMD__EPRST__MASK) + ; + } + + /* disable interrupt for device */ + gadget_writel(usb_ss, &usb_ss->regs->usb_ien, 0); + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, USB_CONF__DEVDS__MASK); + + for (i = 0; i < usb_ss->ep_nums ; i++) + usb_ss_free_trb_pool(usb_ss->eps[i]); + + return 0; +} + +static const struct usb_gadget_ops usb_ss_gadget_ops = { + .get_frame = usb_ss_gadget_get_frame, + .wakeup = usb_ss_gadget_wakeup, + .set_selfpowered = usb_ss_gadget_set_selfpowered, + .pullup = usb_ss_gadget_pullup, + .udc_start = usb_ss_gadget_udc_start, + .udc_stop = usb_ss_gadget_udc_stop, + .match_ep = usb_ss_gadget_match_ep, + +}; + +/** + * usb_ss_init_ep Initializes software endpoints of gadget + * @usb_ss: extended gadget object + * + * Returns 0 on success, error code elsewhere + */ +static int usb_ss_init_ep(struct usb_ss_dev *usb_ss) +{ + struct usb_ss_endpoint *usb_ss_ep; + u32 ep_enabled_reg, iso_ep_reg, bulk_ep_reg; + int i; + int ep_reg_pos, ep_dir, ep_number; + int found_endpoints = 0; + + /* Read it from USB_CAP3 to USB_CAP5 */ + ep_enabled_reg = 0x00ff00ff; + iso_ep_reg = 0x00fe00fe; + bulk_ep_reg = 0x00fe00fe; + + dev_dbg(&usb_ss->dev, "Initializing non-zero endpoints\n"); + dev_dbg(&usb_ss->dev, + "ep_enabled_reg: 0x%x, iso_ep_reg: 0x%x, bulk_ep_reg:0x%x\n", + ep_enabled_reg, iso_ep_reg, bulk_ep_reg); + + for (i = 0; i < USB_SS_ENDPOINTS_MAX_COUNT; i++) { + ep_number = (i / 2) + 1; + ep_dir = i % 2; + ep_reg_pos = (16 * ep_dir) + ep_number; + + if (!(ep_enabled_reg & (1uL << ep_reg_pos))) + continue; + + /* create empty endpoint object */ + usb_ss_ep = devm_kzalloc(&usb_ss->dev, sizeof(*usb_ss_ep), + GFP_KERNEL); + if (!usb_ss_ep) + return -ENOMEM; + + /* set parent of endpoint object */ + usb_ss_ep->usb_ss = usb_ss; + + /* set index of endpoint in endpoints container */ + usb_ss->eps[found_endpoints++] = usb_ss_ep; + + /* set name of endpoint */ + snprintf(usb_ss_ep->name, sizeof(usb_ss_ep->name), "ep%d%s", + ep_number, !!ep_dir ? "in" : "out"); + usb_ss_ep->endpoint.name = usb_ss_ep->name; + dev_dbg(&usb_ss->dev, "Initializing endpoint: %s\n", + usb_ss_ep->name); + + usb_ep_set_maxpacket_limit(&usb_ss_ep->endpoint, + ENDPOINT_MAX_PACKET_LIMIT); + usb_ss_ep->endpoint.max_streams = ENDPOINT_MAX_STREAMS; + usb_ss_ep->endpoint.ops = &usb_ss_gadget_ep_ops; + if (ep_dir) + usb_ss_ep->caps.dir_in = 1; + else + usb_ss_ep->caps.dir_out = 1; + + /* check endpoint type */ + if (iso_ep_reg & (1uL << ep_reg_pos)) + usb_ss_ep->caps.type_iso = 1; + + if (bulk_ep_reg & (1uL << ep_reg_pos)) { + usb_ss_ep->caps.type_bulk = 1; + usb_ss_ep->caps.type_int = 1; + usb_ss_ep->endpoint.maxburst = 15; + } + + list_add_tail(&usb_ss_ep->endpoint.ep_list, + &usb_ss->gadget.ep_list); + INIT_LIST_HEAD(&usb_ss_ep->request_list); + INIT_LIST_HEAD(&usb_ss_ep->ep_match_pending_list); + } + usb_ss->ep_nums = found_endpoints; + return 0; +} + +/** + * usb_ss_init_ep0 Initializes software endpoint 0 of gadget + * @usb_ss: extended gadget object + * + * Returns 0 on success, error code elsewhere + */ +static int usb_ss_init_ep0(struct usb_ss_dev *usb_ss) +{ + struct usb_ss_endpoint *ep0; + + dev_dbg(&usb_ss->dev, "Initializing EP0\n"); + ep0 = devm_kzalloc(&usb_ss->dev, sizeof(struct usb_ss_endpoint), + GFP_KERNEL); + + if (!ep0) + return -ENOMEM; + + /* fill CDNS fields */ + ep0->usb_ss = usb_ss; + sprintf(ep0->name, "ep0"); + + /* fill linux fields */ + ep0->endpoint.ops = &usb_ss_gadget_ep0_ops; + ep0->endpoint.maxburst = 1; + usb_ep_set_maxpacket_limit(&ep0->endpoint, ENDPOINT0_MAX_PACKET_LIMIT); + ep0->address = 0; + ep0->enabled = 1; + ep0->caps.type_control = 1; + ep0->caps.dir_in = 1; + ep0->caps.dir_out = 1; + ep0->endpoint.name = ep0->name; + ep0->endpoint.desc = &cdns3_gadget_ep0_desc; + usb_ss->gadget.ep0 = &ep0->endpoint; + INIT_LIST_HEAD(&ep0->request_list); + + return 0; +} + +static void cdns3_gadget_release(struct device *dev) +{ + struct usb_ss_dev *usb_ss = container_of(dev, struct usb_ss_dev, dev); + + kfree(usb_ss); +} + +static int __cdns3_gadget_init(struct cdns3 *cdns) +{ + struct usb_ss_dev *usb_ss; + int ret; + struct device *dev; + + usb_ss = kzalloc(sizeof(*usb_ss), GFP_KERNEL); + if (!usb_ss) + return -ENOMEM; + + dev = &usb_ss->dev; + dev->release = cdns3_gadget_release; + dev->parent = cdns->dev; + dev_set_name(dev, "gadget-cdns3-dev"); + cdns->gadget_dev = dev; + usb_ss->sysdev = cdns->dev; + ret = device_register(dev); + if (ret) + goto err1; + + usb_ss->regs = cdns->dev_regs; + + /* fill gadget fields */ + usb_ss->gadget.ops = &usb_ss_gadget_ops; +#ifdef CONFIG_USB_CDNS3_GADGET_FORCE_HIGHSPEED + usb_ss->gadget.max_speed = USB_SPEED_HIGH; +#else + usb_ss->gadget.max_speed = USB_SPEED_SUPER; +#endif + usb_ss->gadget.speed = USB_SPEED_UNKNOWN; + usb_ss->gadget.name = "cdns3-gadget"; + usb_ss->is_connected = 0; + spin_lock_init(&usb_ss->lock); + + usb_ss->in_standby_mode = 1; + + /* initialize endpoint container */ + INIT_LIST_HEAD(&usb_ss->gadget.ep_list); + INIT_LIST_HEAD(&usb_ss->ep_match_list); + ret = usb_ss_init_ep0(usb_ss); + if (ret) { + dev_err(dev, "Failed to create endpoint 0\n"); + ret = -ENOMEM; + goto err2; + } + + ret = usb_ss_init_ep(usb_ss); + if (ret) { + dev_err(dev, "Failed to create non zero endpoints\n"); + ret = -ENOMEM; + goto err2; + } + + /* allocate memory for default endpoint TRB */ + usb_ss->trb_ep0 = (u32 *)dma_alloc_coherent(20, (unsigned long *)&usb_ss->trb_ep0_dma); + if (!usb_ss->trb_ep0) { + dev_err(dev, "Failed to allocate memory for ep0 TRB\n"); + ret = -ENOMEM; + goto err2; + } + + /* allocate memory for setup packet buffer */ + usb_ss->setup = (u8 *)dma_alloc_coherent(8, (unsigned long *)&usb_ss->setup_dma); + if (!usb_ss->setup) { + dev_err(dev, "Failed to allocate memory for SETUP buffer\n"); + ret = -ENOMEM; + goto err3; + } + + /* add USB gadget device */ + ret = usb_add_gadget_udc(&usb_ss->dev, &usb_ss->gadget); + if (ret < 0) { + dev_err(dev, "Failed to register USB device controller\n"); + goto err4; + } + + return 0; + +err4: + dma_free_coherent(usb_ss->setup); +err3: + dma_free_coherent(usb_ss->trb_ep0); +err2: +err1: + cdns->gadget_dev = NULL; + + return ret; +} + +/** + * cdns3_gadget_remove: parent must call this to remove UDC + * + * cdns: cdns3 instance + * + */ +void cdns3_gadget_remove(struct cdns3 *cdns) +{ + struct usb_ss_dev *usb_ss; + + if (!cdns->roles[CDNS3_ROLE_GADGET]) + return; + + usb_ss = container_of(cdns->gadget_dev, struct usb_ss_dev, dev); + usb_del_gadget_udc(&usb_ss->gadget); + dma_free_coherent(usb_ss->setup); + dma_free_coherent(usb_ss->trb_ep0); + device_unregister(cdns->gadget_dev); + cdns->gadget_dev = NULL; +} + +static void __cdns3_gadget_start(struct usb_ss_dev *usb_ss) +{ + u32 usb_conf_reg = 0; + + /* configure endpoint 0 hardware */ + cdns_ep0_config(usb_ss); + + /* enable interrupts for endpoint 0 (in and out) */ + gadget_writel(usb_ss, &usb_ss->regs->ep_ien, + EP_IEN__EOUTEN0__MASK | EP_IEN__EINEN0__MASK); + + /* enable interrupt for device */ + gadget_writel(usb_ss, &usb_ss->regs->usb_ien, + USB_IEN__U2RESIEN__MASK + | USB_ISTS__DIS2I__MASK + | USB_IEN__CON2IEN__MASK + | USB_IEN__UHRESIEN__MASK + | USB_IEN__UWRESIEN__MASK + | USB_IEN__DISIEN__MASK + | USB_IEN__CONIEN__MASK + | USB_IEN__U3EXTIEN__MASK + | USB_IEN__L2ENTIEN__MASK + | USB_IEN__L2EXTIEN__MASK); + + usb_conf_reg = USB_CONF__CLK2OFFDS__MASK | + USB_CONF__L1DS__MASK; + if (usb_ss->gadget.max_speed == USB_SPEED_HIGH) + usb_conf_reg |= USB_CONF__USB3DIS__MASK; + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, usb_conf_reg); + + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, + USB_CONF__U1DS__MASK + | USB_CONF__U2DS__MASK + /* + * TODO: + * | USB_CONF__L1EN__MASK + */ + ); + + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, USB_CONF__DEVEN__MASK); + + gadget_writel(usb_ss, &usb_ss->regs->dbg_link1, + DBG_LINK1__LFPS_MIN_GEN_U1_EXIT_SET__MASK | + DBG_LINK1__LFPS_MIN_GEN_U1_EXIT__WRITE(0x3C)); +} + +static int cdns3_gadget_start(struct cdns3 *cdns) +{ + struct usb_ss_dev *usb_ss = container_of(cdns->gadget_dev, + struct usb_ss_dev, dev); + unsigned long flags; + + dev_dbg(&usb_ss->dev, "%s begins\n", __func__); + + pm_runtime_get_sync(cdns->dev); + spin_lock_irqsave(&usb_ss->lock, flags); + usb_ss->start_gadget = 1; + if (!usb_ss->gadget_driver) { + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; + } + + __cdns3_gadget_start(usb_ss); + usb_ss->in_standby_mode = 0; + spin_unlock_irqrestore(&usb_ss->lock, flags); + dev_dbg(&usb_ss->dev, "%s ends\n", __func__); + + return 0; +} + +static void __cdns3_gadget_stop(struct cdns3 *cdns) +{ + struct usb_ss_dev *usb_ss; + unsigned long flags; + + usb_ss = container_of(cdns->gadget_dev, struct usb_ss_dev, dev); + if (usb_ss->gadget_driver) + usb_ss->gadget_driver->disconnect(&usb_ss->gadget); + usb_gadget_disconnect(&usb_ss->gadget); + spin_lock_irqsave(&usb_ss->lock, flags); + /* disable interrupt for device */ + gadget_writel(usb_ss, &usb_ss->regs->usb_ien, 0); + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, USB_CONF__DEVDS__MASK); + usb_ss->start_gadget = 0; + spin_unlock_irqrestore(&usb_ss->lock, flags); +} + +static void cdns3_gadget_stop(struct cdns3 *cdns) +{ + if (cdns->role == CDNS3_ROLE_GADGET) + __cdns3_gadget_stop(cdns); +} + +/** + * cdns3_gadget_init - initialize device structure + * + * cdns: cdns3 instance + * + * This function initializes the gadget. + */ +int cdns3_gadget_init(struct cdns3 *cdns) +{ + struct cdns3_role_driver *rdrv; + + rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL); + if (!rdrv) + return -ENOMEM; + + rdrv->start = cdns3_gadget_start; + rdrv->stop = cdns3_gadget_stop; + rdrv->irq = cdns_irq_handler_thread; + rdrv->name = "gadget"; + cdns->roles[CDNS3_ROLE_GADGET] = rdrv; + return __cdns3_gadget_init(cdns); +} diff --git a/drivers/usb/cdns3/gadget.h b/drivers/usb/cdns3/gadget.h new file mode 100644 index 00000000000..fdb6e511dc6 --- /dev/null +++ b/drivers/usb/cdns3/gadget.h @@ -0,0 +1,221 @@ +/* + * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __DRIVERS_CDNS3_GADGET +#define __DRIVERS_CDNS3_GADGET + +#include "dev-regs-map.h" + +#if IS_ENABLED(CONFIG_USB_CDNS_MISC) +#include "cdns_misc.h" +#endif + +#define gadget_to_usb_ss(g) \ + (container_of(g, struct usb_ss_dev, gadget)) + +#define to_usb_ss_ep(ep) \ + (container_of(ep, struct usb_ss_endpoint, endpoint)) + +#define ep_to_usb_ss_ep(ep) \ + (container_of(ep, struct usb_ss_endpoint, endpoint)) + +/*-------------------------------------------------------------------------*/ +/* TRB macros */ + +/* Common TRB fields */ +#define TRB_SET_CYCLE_BIT 1uL +#define TRB_SET_CHAIN_BIT 0x10 + +/* offset 0 */ +#define TRB_DATA_BUFFER_POINTER_MASK 0xFFFFFFFF +#define TRB_SET_DATA_BUFFER_POINTER(p) (p & TRB_DATA_BUFFER_POINTER_MASK) + +/* offset 4 */ +#define TRB_TRANSFER_LENGTH_MASK 0x1FFFF +#define TRB_SET_TRANSFER_LENGTH(l) (l & TRB_TRANSFER_LENGTH_MASK) + +#define TRB_BURST_LENGTH_MASK 0xFF +#define TRB_SET_BURST_LENGTH(l) ((l & TRB_BURST_LENGTH_MASK) << 24) + +/* offset 8 */ +#define TRB_SET_INT_ON_SHORT_PACKET 0x04 +#define TRB_SET_FIFO_MODE 0x08 +#define TRB_SET_INT_ON_COMPLETION 0x20 + +#define TRB_TYPE_NORMAL 0x400 + +#define TRB_STREAM_ID_MASK 0xFFFF +#define TRB_SET_STREAM_ID(sid) ((sid & TRB_STREAM_ID_MASK) << 16) + +/*-------------------------------------------------------------------------*/ +/* Driver numeric constants */ + + +#define DEVICE_ADDRESS_MAX 127 + +/* Endpoint init values */ +#ifdef CONFIG_USB_CDNS3_GADGET_FORCE_HIGHSPEED +#define ENDPOINT_MAX_PACKET_LIMIT 512 +#else +#define ENDPOINT_MAX_PACKET_LIMIT 1024 +#endif + +#define ENDPOINT_MAX_STREAMS 15 + +#define ENDPOINT0_MAX_PACKET_LIMIT 512 + +/* All endpoints except EP0 */ +#define USB_SS_ENDPOINTS_MAX_COUNT 30 + +#define USB_SS_TRBS_NUM 32 + +/* Standby mode */ +#define STB_CLK_SWITCH_DONE_MASK 0x200 +#define STB_CLK_SWITCH_EN_MASK 0x100 +#define STB_CLK_SWITCH_EN_SHIFT 8 + +#define ENDPOINT_MAX_PACKET_SIZE_0 0 +#define ENDPOINT_MAX_PACKET_SIZE_8 8 +#define ENDPOINT_MAX_PACKET_SIZE_64 64 +#define ENDPOINT_MAX_PACKET_SIZE_512 512 +#define ENDPOINT_MAX_PACKET_SIZE_1023 1023 +#define ENDPOINT_MAX_PACKET_SIZE_1024 1024 + +#define SS_LINK_STATE_U3 3 +#define FSHS_LPM_STATE_L2 2 + +#define ADDR_MODULO_8 8 + +#define INTERRUPT_MASK 0xFFFFFFFF + +#define ACTUAL_TRANSFERRED_BYTES_MASK 0x1FFFF + +#define ENDPOINT_DIR_MASK 0x80 + +/*-------------------------------------------------------------------------*/ + +/** + * IS_REG_REQUIRING_ACTIVE_REF_CLOCK - Macro checks if desired + * register requires active clock, it involves such registers as: + * EP_CFG, EP_TR_ADDR, EP_CMD, EP_SEL, USB_CONF + * @usb_ss: extended gadget object + * @reg: register address + */ +#define IS_REG_REQUIRING_ACTIVE_REF_CLOCK(usb_ss, reg) (!reg || \ + (reg >= &usb_ss->regs->ep_sel && reg <= &usb_ss->regs->ep_cmd)) + +/** + * CAST_EP_REG_POS_TO_INDEX - Macro converts bit position of ep_ists register to + * index of endpoint object in usb_ss_dev.eps[] container + * @i: bit position of endpoint for which endpoint object is required + * + * Remember that endpoint container doesn't contain default endpoint + */ +#define CAST_EP_REG_POS_TO_INDEX(i) (((i) / 16) + ((((i) % 16) - 2) * 2)) + +/** + * CAST_EP_ADDR_TO_INDEX - Macro converts endpoint address to + * index of endpoint object in usb_ss_dev.eps[] container + * @ep_addr: endpoint address for which endpoint object is required + * + * Remember that endpoint container doesn't contain default endpoint + */ +#define CAST_EP_ADDR_TO_INDEX(ep_addr) \ + (((ep_addr & 0x7F) - 1) + ((ep_addr & 0x80) ? 1 : 0)) + +/** + * CAST_EP_ADDR_TO_BIT_POS - Macro converts endpoint address to + * bit position in ep_ists register + * @ep_addr: endpoint address for which bit position is required + * + * Remember that endpoint container doesn't contain default endpoint + */ +#define CAST_EP_ADDR_TO_BIT_POS(ep_addr) \ + (((uint32_t)1 << (ep_addr & 0x7F)) << ((ep_addr & 0x80) ? 16 : 0)) + + +#define CAST_INDEX_TO_EP_ADDR(index) \ + ((index / 2 + 1) | ((index % 2) ? 0x80 : 0x00)) + +/*-------------------------------------------------------------------------*/ +/* Used structs */ + +struct usb_ss_trb { + u32 offset0; + u32 offset4; + u32 offset8; +}; + +struct usb_ss_dev; + +struct usb_ep_caps { + unsigned type_control:1; + unsigned type_iso:1; + unsigned type_bulk:1; + unsigned type_int:1; + unsigned dir_in:1; + unsigned dir_out:1; +}; + +struct usb_ss_endpoint { + struct usb_ep endpoint; + struct list_head request_list; + struct list_head ep_match_pending_list; + + struct usb_ss_trb *trb_pool; + dma_addr_t trb_pool_dma; + + struct usb_ss_dev *usb_ss; + char name[20]; + int hw_pending_flag; + int stalled_flag; + int wedge_flag; + void *cpu_addr; + dma_addr_t dma_addr; + u8 dir; + u8 num; + u8 type; + u8 address; + bool used; + bool enabled; + struct usb_ep_caps caps; +}; + +struct usb_ss_dev { + struct device dev; + struct usbss_dev_register_block_type __iomem *regs; + + struct usb_gadget gadget; + struct usb_gadget_driver *gadget_driver; + + dma_addr_t setup_dma; + dma_addr_t trb_ep0_dma; + u32 *trb_ep0; + u8 *setup; + + struct usb_ss_endpoint *eps[USB_SS_ENDPOINTS_MAX_COUNT]; + int ep_nums; + struct usb_request *actual_ep0_request; + int ep0_data_dir; + int hw_configured_flag; + int wake_up_flag; + u16 isoch_delay; + spinlock_t lock; + + unsigned is_connected:1; + unsigned in_standby_mode:1; + + u32 usb_ien; + u32 ep_ien; + int setup_pending; + struct device *sysdev; + bool start_gadget; /* The device mode is enabled */ + struct list_head ep_match_list; +}; + +#define OTG_STS_SELECTOR 0xF000 /* OTG status selector */ + +#endif /* __DRIVERS_CDNS3_GADGET */ diff --git a/drivers/usb/cdns3/io.h b/drivers/usb/cdns3/io.h new file mode 100644 index 00000000000..7702d884bde --- /dev/null +++ b/drivers/usb/cdns3/io.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/ + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __DRIVERS_USB_CDNS_IO_H +#define __DRIVERS_USB_CDNS_IO_H + +#include + +static inline u32 cdns_readl(uint32_t __iomem *reg) +{ + u32 value = 0; + + value = readl(reg); + return value; +} + +static inline void cdns_writel(uint32_t __iomem *reg, u32 value) +{ + writel(value, reg); +} + +static inline void cdns_flush_cache(uintptr_t addr, int length) +{ + flush_dcache_range(addr, addr + ROUND(length, ARCH_DMA_MINALIGN)); +} + +#endif /* __DRIVERS_USB_CDNS_IO_H */ diff --git a/drivers/usb/cdns3/linux-compat.h b/drivers/usb/cdns3/linux-compat.h new file mode 100644 index 00000000000..773de930c46 --- /dev/null +++ b/drivers/usb/cdns3/linux-compat.h @@ -0,0 +1,19 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#ifndef __CDNS3_LINUX_COMPAT__ +#define __CDNS3_LINUX_COMPAT__ + +#define WARN(val, format, arg...) debug(format, ##arg) +#define dev_WARN(dev, format, arg...) debug(format, ##arg) + +static inline void *devm_kzalloc(struct device *dev, unsigned int size, + unsigned int flags) +{ + return kzalloc(size, flags); +} +#endif diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 87b9c87edf6..8390c28d04f 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -395,6 +395,25 @@ static void dwc3_phy_setup(struct dwc3 *dwc) mdelay(100); } +void dwc3_set_suspend_clk(struct dwc3 *dwc) +{ + u32 reg; + + /* + * DWC3_GCTL.PWRDNSCALE: The USB3 suspend_clk input replaces + * pipe3_rx_pclk as a clock source to a small part of the USB3 + * core that operates when the SS PHY is in its lowest power + * (P3) state, and therefore does not provide a clock. + * The Power Down Scale field specifies how many suspend_clk + * periods fit into a 16 kHz clock period. When performing the + * division, round up the remainder. + */ + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~(DWC3_GCTL_PWRDNSCALE(0x1fff)); + reg |= DWC3_GCTL_PWRDNSCALE(dwc->power_down_scale); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + /** * dwc3_core_init - Low-level initialization of DWC3 Core * @dwc: Pointer to our controller context structure @@ -443,6 +462,9 @@ static int dwc3_core_init(struct dwc3 *dwc) if (ret) goto err0; + if (dwc->power_down_scale) + dwc3_set_suspend_clk(dwc); + reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg &= ~DWC3_GCTL_SCALEDOWN_MASK; @@ -672,6 +694,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) if (dwc3_dev->tx_de_emphasis) tx_de_emphasis = dwc3_dev->tx_de_emphasis; + dwc->power_down_scale = dwc3_dev->power_down_scale; + /* default to superspeed if no maximum_speed passed */ if (dwc->maximum_speed == USB_SPEED_UNKNOWN) dwc->maximum_speed = USB_SPEED_SUPER; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 72d2fcdd3f4..030a471be31 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -643,6 +643,7 @@ struct dwc3_scratchpad_array { * @dr_mode: requested mode of operation * @dcfg: saved contents of DCFG register * @gctl: saved contents of GCTL register + * @power_down_scale: 16KHz clock periods for suspend_clk * @isoch_delay: wValue from Set Isochronous Delay request; * @u2sel: parameter from Set SEL request. * @u2pel: parameter from Set SEL request. @@ -763,6 +764,7 @@ struct dwc3 { enum dwc3_ep0_state ep0state; enum dwc3_link_state link_state; + u16 power_down_scale; u16 isoch_delay; u16 u2sel; u16 u2pel; diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index e61d98046fc..84548b89d1d 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -391,7 +391,6 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc, u32 recip; u32 wValue; u32 wIndex; - u32 reg; int ret; enum usb_device_state state; @@ -415,27 +414,12 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc, return -EINVAL; if (dwc->speed != DWC3_DSTS_SUPERSPEED) return -EINVAL; - - reg = dwc3_readl(dwc->regs, DWC3_DCTL); - if (set) - reg |= DWC3_DCTL_INITU1ENA; - else - reg &= ~DWC3_DCTL_INITU1ENA; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); break; - case USB_DEVICE_U2_ENABLE: if (state != USB_STATE_CONFIGURED) return -EINVAL; if (dwc->speed != DWC3_DSTS_SUPERSPEED) return -EINVAL; - - reg = dwc3_readl(dwc->regs, DWC3_DCTL); - if (set) - reg |= DWC3_DCTL_INITU2ENA; - else - reg &= ~DWC3_DCTL_INITU2ENA; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); break; case USB_DEVICE_LTM_ENABLE: @@ -539,7 +523,6 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) enum usb_device_state state = dwc->gadget.state; u32 cfg; int ret; - u32 reg; dwc->start_config_issued = false; cfg = le16_to_cpu(ctrl->wValue); @@ -563,14 +546,6 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); - /* - * Enable transition to U1/U2 state when - * nothing is pending from application. - */ - reg = dwc3_readl(dwc->regs, DWC3_DCTL); - reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); - dwc3_writel(dwc->regs, DWC3_DCTL, reg); - dwc->resize_fifos = true; dev_dbg(dwc->dev, "resize FIFOs flag SET"); } diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index e065c5aeb38..28c40d237d5 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -968,8 +968,8 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) * so HACK the request length */ if (dep->direction == 0 && - req->request.length < dep->endpoint.maxpacket) - req->request.length = dep->endpoint.maxpacket; + req->request.length < usb_endpoint_maxp(dep->endpoint.desc)) + req->request.length = usb_endpoint_maxp(dep->endpoint.desc); /* * We only add to our list of requests now and @@ -1481,7 +1481,7 @@ static int dwc3_gadget_start(struct usb_gadget *g, if (dwc->revision < DWC3_REVISION_220A) { reg |= DWC3_DCFG_SUPERSPEED; } else { - switch (dwc->maximum_speed) { + switch (dwc->gadget.max_speed) { case USB_SPEED_LOW: reg |= DWC3_DSTS_LOWSPEED; break; @@ -1605,7 +1605,12 @@ static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, } else { int ret; - usb_ep_set_maxpacket_limit(&dep->endpoint, 512); + if (dwc->maximum_speed >= USB_SPEED_SUPER) + usb_ep_set_maxpacket_limit(&dep->endpoint, + 1024); + else + usb_ep_set_maxpacket_limit(&dep->endpoint, + 512); dep->endpoint.max_streams = 15; dep->endpoint.ops = &dwc3_gadget_ep_ops; list_add_tail(&dep->endpoint.ep_list, @@ -2558,6 +2563,7 @@ static irqreturn_t dwc3_interrupt(int irq, void *_dwc) int dwc3_gadget_init(struct dwc3 *dwc) { int ret; + u32 reg; dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req), (unsigned long *)&dwc->ctrl_req_addr); @@ -2591,7 +2597,7 @@ int dwc3_gadget_init(struct dwc3 *dwc) } dwc->gadget.ops = &dwc3_gadget_ops; - dwc->gadget.max_speed = USB_SPEED_SUPER; + dwc->gadget.max_speed = dwc->maximum_speed; dwc->gadget.speed = USB_SPEED_UNKNOWN; dwc->gadget.name = "dwc3-gadget"; @@ -2616,6 +2622,10 @@ int dwc3_gadget_init(struct dwc3 *dwc) goto err4; } + reg = dwc3_readl(dwc->regs, DWC3_DCTL); + reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA); + dwc3_writel(dwc->regs, DWC3_DCTL, reg); + return 0; err4: diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 6825e6b5434..6a04bd57307 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -115,6 +115,10 @@ config USB_GADGET_VBUS_DRAW This value will be used except for system-specific gadget drivers that have more specific information. +config SDP_LOADADDR + hex "Default load address at SDP_WRITE and SDP_JUMP" + default 0 + # Selected by UDC drivers that support high-speed operation. config USB_GADGET_DUALSPEED bool diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 748366fb9f0..a76737ae8a0 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -5,6 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +ccflags-y += -I./lib/avb + obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o @@ -29,6 +31,8 @@ obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o obj-$(CONFIG_DFU_OVER_USB) += f_dfu.o obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o +obj-$(CONFIG_FASTBOOT_LOCK) += fastboot_lock_unlock.o +obj-$(CONFIG_BCB_SUPPORT) += command.o bcb.o obj-$(CONFIG_USB_FUNCTION_SDP) += f_sdp.o obj-$(CONFIG_USB_FUNCTION_ROCKUSB) += f_rockusb.o endif diff --git a/drivers/usb/gadget/bcb.c b/drivers/usb/gadget/bcb.c new file mode 100644 index 00000000000..645bc88a418 --- /dev/null +++ b/drivers/usb/gadget/bcb.c @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "bcb.h" +#define ALIGN_BYTES 64 /*armv7 cache line need 64 bytes aligned */ + +static ulong get_block_size(char *ifname, int dev) +{ + struct blk_desc *dev_desc = NULL; + + dev_desc = blk_get_dev(ifname, dev); + if (dev_desc == NULL) { + printf("Block device %s %d not supported\n", ifname, dev); + return 0; + } + + return dev_desc->blksz; +} + +static int do_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *ep; + struct blk_desc *dev_desc = NULL; + int dev; + int part = 0; + disk_partition_t part_info; + ulong offset = 0u; + ulong limit = 0u; + void *addr; + uint blk; + uint cnt; + + if (argc != 6) { + cmd_usage(cmdtp); + return 1; + } + + dev = (int)simple_strtoul(argv[2], &ep, 16); + if (*ep) { + if (*ep != ':') { + printf("Invalid block device %s\n", argv[2]); + return 1; + } + part = (int)simple_strtoul(++ep, NULL, 16); + } + + dev_desc = blk_get_dev(argv[1], dev); + if (dev_desc == NULL) { + printf("Block device %s %d not supported\n", argv[1], dev); + return 1; + } + + addr = (void *)simple_strtoul(argv[3], NULL, 16); + blk = simple_strtoul(argv[4], NULL, 16); + cnt = simple_strtoul(argv[5], NULL, 16); + + if (part != 0) { + if (part_get_info(dev_desc, part, &part_info)) { + printf("Cannot find partition %d\n", part); + return 1; + } + offset = part_info.start; + limit = part_info.size; + } else { + /* Largest address not available in block_dev_desc_t. */ + limit = ~0; + } + + if (cnt + blk > limit) { + printf("Write out of range\n"); + return 1; + } + + if (blk_dwrite(dev_desc, offset + blk, cnt, addr) != cnt) { + printf("Error writing blocks\n"); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + write, 6, 0, do_write, + "write binary data to a partition", + " addr blk# cnt" +); + +int bcb_rw_block(bool bread, char **ppblock, + uint *pblksize, char *pblock_write, uint offset, uint size) +{ + int ret; + char *argv[6]; + char addr_str[20]; + char cnt_str[8]; + char devpart_str[8]; + char block_begin_str[8]; + ulong blk_size = 0; + uint blk_begin = 0; + uint blk_end = 0; + uint block_cnt = 0; + char *p_block = NULL; + unsigned int mmc_id; + + if (bread && ((ppblock == NULL) || (pblksize == NULL))) + return -1; + + if (!bread && (pblock_write == NULL)) + return -1; + + mmc_id = mmc_get_env_dev(); + blk_size = get_block_size("mmc", mmc_id); + if (blk_size == 0) { + printf("bcb_rw_block, get_block_size return 0\n"); + return -1; + } + + blk_begin = offset/blk_size; + blk_end = (offset + size)/blk_size; + block_cnt = 1 + (blk_end - blk_begin); + + sprintf(devpart_str, "0x%x:0x%x", mmc_id, + fastboot_flash_find_index(FASTBOOT_PARTITION_MISC)); + sprintf(block_begin_str, "0x%x", blk_begin); + sprintf(cnt_str, "0x%x", block_cnt); + + argv[0] = "rw"; /* not care */ + argv[1] = "mmc"; + argv[2] = devpart_str; + argv[3] = addr_str; + argv[4] = block_begin_str; + argv[5] = cnt_str; + + if (bread) { + p_block = (char *)memalign(ALIGN_BYTES, blk_size * block_cnt); + if (NULL == p_block) { + printf("bcb_rw_block, memalign %d bytes failed\n", + (int)(blk_size * block_cnt)); + return -1; + } + sprintf(addr_str, "0x%x", (unsigned int)(uintptr_t)p_block); + ret = do_raw_read(NULL, 0, 6, argv); + if (ret) { + free(p_block); + printf("do_raw_read failed, ret %d\n", ret); + return -1; + } + + *ppblock = p_block; + *pblksize = (uint)blk_size; + } else { + sprintf(addr_str, "0x%x", (unsigned int)(uintptr_t)pblock_write); + ret = do_write(NULL, 0, 6, argv); + if (ret) { + printf("do_write failed, ret %d\n", ret); + return -1; + } + } + return 0; +} diff --git a/drivers/usb/gadget/bcb.h b/drivers/usb/gadget/bcb.h new file mode 100644 index 00000000000..b5a2491014a --- /dev/null +++ b/drivers/usb/gadget/bcb.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef BCB_H +#define BCB_H +#include +#include + +#define FASTBOOT_BCB_CMD "bootonce-bootloader" +#ifdef CONFIG_ANDROID_RECOVERY +#define RECOVERY_BCB_CMD "boot-recovery" +#endif +/* keep same as bootable/recovery/bootloader.h */ +struct bootloader_message { + char command[32]; + char status[32]; + char recovery[768]; + + /* The 'recovery' field used to be 1024 bytes. It has only ever + been used to store the recovery command line, so 768 bytes + should be plenty. We carve off the last 256 bytes to store the + stage string (for multistage packages) and possible future + expansion. */ + char stage[32]; + + /* The 'reserved' field used to be 224 bytes when it was initially + carved off from the 1024-byte recovery field. Bump it up to + 1184-byte so that the entire bootloader_message struct rounds up + to 2048-byte. + */ + char reserved[1184]; +}; + +struct bootloader_message_ab { + struct bootloader_message message; + char slot_suffix[32]; + + /* Round up the entire struct to 4096-byte. */ + char reserved[2016]; +}; + +/* start from bootloader_message_ab.slot_suffix[BOOTCTRL_IDX] */ +#define BOOTCTRL_IDX 0 +#define MISC_COMMAND_IDX 0 +#define BOOTCTRL_OFFSET \ + (u32)(&(((struct bootloader_message_ab *)0)->slot_suffix[BOOTCTRL_IDX])) +#define MISC_COMMAND \ + (u32)(uintptr_t)(&(((struct bootloader_message *)0)->command[MISC_COMMAND_IDX])) +int bcb_rw_block(bool bread, char **ppblock, + uint *pblksize, char *pblock_write, uint offset, uint size); + +int bcb_write_command(char *bcb_command); +int bcb_read_command(char *command); + +#endif diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 05c01ce5d6e..5e038382298 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -139,6 +139,7 @@ static struct ci_drv controller = { .name = "ci_udc", .ops = &ci_udc_ops, .is_dualspeed = 1, + .max_speed = USB_SPEED_HIGH, }, }; @@ -329,6 +330,7 @@ static int ci_ep_enable(struct usb_ep *ep, num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (desc->bEndpointAddress & USB_DIR_IN) != 0; ci_ep->desc = desc; + ep->desc = desc; if (num) { int max = get_unaligned_le16(&desc->wMaxPacketSize); @@ -351,6 +353,7 @@ static int ci_ep_disable(struct usb_ep *ep) struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); ci_ep->desc = NULL; + ep->desc = NULL; return 0; } @@ -1006,8 +1009,6 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) return -EINVAL; if (!driver->bind || !driver->setup || !driver->disconnect) return -EINVAL; - if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) - return -EINVAL; #ifdef CONFIG_DM_USB ret = usb_setup_ehci_gadget(&controller.ctrl); @@ -1044,6 +1045,13 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) free(controller.items_mem); free(controller.epts); +#ifdef CONFIG_DM_USB + usb_remove_ehci_gadget(&controller.ctrl); +#else + usb_lowlevel_stop(0); + controller.ctrl = NULL; +#endif + return 0; } diff --git a/drivers/usb/gadget/command.c b/drivers/usb/gadget/command.c new file mode 100644 index 00000000000..e9f7d291735 --- /dev/null +++ b/drivers/usb/gadget/command.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include "bcb.h" + +int bcb_read_command(char *command) +{ + int ret = 0; + char *p_block = NULL; + uint offset_in_block = 0; + uint blk_size = 0; + + if (command == NULL) + return -1; + + ret = bcb_rw_block(true, &p_block, &blk_size, NULL, MISC_COMMAND, 32); + if (ret) { + printf("read_bootctl, bcb_rw_block read failed\n"); + return -1; + } + + offset_in_block = MISC_COMMAND%blk_size; + memcpy(command, p_block + offset_in_block, 32); + free(p_block); + + return 0; +} +int bcb_write_command(char *bcb_command) +{ + int ret = 0; + char *p_block = NULL; + uint offset_in_block = 0; + uint blk_size = 0; + + if (bcb_command == NULL) + return -1; + + + ret = bcb_rw_block(true, &p_block, &blk_size, NULL, MISC_COMMAND, 32); + if (ret) { + printf("write_bootctl, bcb_rw_block read failed\n"); + return -1; + } + + offset_in_block = MISC_COMMAND%blk_size; + memcpy(p_block + offset_in_block, bcb_command, 32); + + ret = bcb_rw_block(false, NULL, NULL, p_block, MISC_COMMAND, 32); + if (ret) { + free(p_block); + printf("write_bootctl, bcb_rw_block write failed\n"); + return -1; + } + + free(p_block); + return 0; +} diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index d0ee7847b98..5efb15bd9d7 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -10,10 +10,31 @@ #include #include +#include "u_os_desc.h" #define USB_BUFSIZ 4096 static struct usb_composite_driver *composite; +static struct usb_configuration *os_desc_config; + +/* Microsoft OS String Descriptor */ +static char qw_sign_buf[OS_STRING_QW_SIGN_LEN / 2] = {'M', 'S', 'F', 'T', '1', '0', '0'}; + +/** + * struct usb_os_string - represents OS String to be reported by a gadget + * @bLength: total length of the entire descritor, always 0x12 + * @bDescriptorType: USB_DT_STRING + * @qwSignature: the OS String proper + * @bMS_VendorCode: code used by the host for subsequent requests + * @bPad: not used, must be zero + */ +struct usb_os_string { + __u8 bLength; + __u8 bDescriptorType; + __u8 qwSignature[OS_STRING_QW_SIGN_LEN]; + __u8 bMS_VendorCode; + __u8 bPad; +} __packed; /** * usb_add_function() - add a function to a configuration @@ -57,6 +78,8 @@ int usb_add_function(struct usb_configuration *config, config->fullspeed = 1; if (!config->highspeed && function->hs_descriptors) config->highspeed = 1; + if (!config->superspeed && function->ss_descriptors) + config->superspeed = 1; done: if (value) @@ -192,7 +215,9 @@ static int config_buf(struct usb_configuration *config, /* add each function's descriptors */ list_for_each_entry(f, &config->functions, list) { - if (speed == USB_SPEED_HIGH) + if (speed == USB_SPEED_SUPER) + descriptors = f->ss_descriptors; + else if (speed == USB_SPEED_HIGH) descriptors = f->hs_descriptors; else descriptors = f->descriptors; @@ -218,8 +243,11 @@ static int config_desc(struct usb_composite_dev *cdev, unsigned w_value) u8 type = w_value >> 8; int hs = 0; struct usb_configuration *c; + struct list_head *pos; - if (gadget_is_dualspeed(gadget)) { + if (gadget_is_superspeed(gadget)) { + speed = gadget->speed; + } else if (gadget_is_dualspeed(gadget)) { if (gadget->speed == USB_SPEED_HIGH) hs = 1; if (type == USB_DT_OTHER_SPEED_CONFIG) @@ -229,8 +257,24 @@ static int config_desc(struct usb_composite_dev *cdev, unsigned w_value) } w_value &= 0xff; - list_for_each_entry(c, &cdev->configs, list) { - if (speed == USB_SPEED_HIGH) { + + pos = &cdev->configs; + c = cdev->os_desc_config; + if (c) + goto check_config; + + while ((pos = pos->next) != &cdev->configs) { + c = list_entry(pos, typeof(*c), list); + + /* skip OS Descriptors config which is handled separately */ + if (c == cdev->os_desc_config) + continue; + +check_config: + if (speed == USB_SPEED_SUPER) { + if (!c->superspeed) + continue; + } else if (speed == USB_SPEED_HIGH) { if (!c->highspeed) continue; } else { @@ -249,8 +293,12 @@ static int count_configs(struct usb_composite_dev *cdev, unsigned type) struct usb_gadget *gadget = cdev->gadget; unsigned count = 0; int hs = 0; + int ss = 0; struct usb_configuration *c; + if (gadget->speed == USB_SPEED_SUPER) + ss = 1; + if (gadget_is_dualspeed(gadget)) { if (gadget->speed == USB_SPEED_HIGH) hs = 1; @@ -259,7 +307,10 @@ static int count_configs(struct usb_composite_dev *cdev, unsigned type) } list_for_each_entry(c, &cdev->configs, list) { /* ignore configs that won't work at this speed */ - if (hs) { + if (ss) { + if (!c->superspeed) + continue; + } else if (hs) { if (!c->highspeed) continue; } else { @@ -271,6 +322,78 @@ static int count_configs(struct usb_composite_dev *cdev, unsigned type) return count; } +/** + * bos_desc() - prepares the BOS descriptor. + * @cdev: pointer to usb_composite device to generate the bos + * descriptor for + * + * This function generates the BOS (Binary Device Object) + * descriptor and its device capabilities descriptors. The BOS + * descriptor should be supported by a SuperSpeed device. + */ +static int bos_desc(struct usb_composite_dev *cdev) +{ + struct usb_ext_cap_descriptor *usb_ext; + struct usb_dcd_config_params dcd_config_params; + struct usb_bos_descriptor *bos = cdev->req->buf; + + bos->bLength = USB_DT_BOS_SIZE; + bos->bDescriptorType = USB_DT_BOS; + + bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE); + bos->bNumDeviceCaps = 0; + + /* + * A SuperSpeed device shall include the USB2.0 extension descriptor + * and shall support LPM when operating in USB2.0 HS mode. + */ + usb_ext = cdev->req->buf + le16_to_cpu(bos->wTotalLength); + bos->bNumDeviceCaps++; + bos->wTotalLength = cpu_to_le16(le16_to_cpu(bos->wTotalLength) + + USB_DT_USB_EXT_CAP_SIZE); + usb_ext->bLength = USB_DT_USB_EXT_CAP_SIZE; + usb_ext->bDescriptorType = USB_DT_DEVICE_CAPABILITY; + usb_ext->bDevCapabilityType = USB_CAP_TYPE_EXT; + usb_ext->bmAttributes = cpu_to_le32(USB_LPM_SUPPORT | USB_BESL_SUPPORT); + + /* + * The Superspeed USB Capability descriptor shall be implemented by all + * SuperSpeed devices. + */ + if (gadget_is_superspeed(cdev->gadget)) { + struct usb_ss_cap_descriptor *ss_cap; + + ss_cap = cdev->req->buf + le16_to_cpu(bos->wTotalLength); + bos->bNumDeviceCaps++; + bos->wTotalLength = cpu_to_le16(le16_to_cpu(bos->wTotalLength) + + USB_DT_USB_SS_CAP_SIZE); + ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE; + ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; + ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE; + ss_cap->bmAttributes = 0; /* LTM is not supported yet */ + ss_cap->wSpeedSupported = cpu_to_le16(USB_LOW_SPEED_OPERATION | + USB_FULL_SPEED_OPERATION | + USB_HIGH_SPEED_OPERATION | + USB_5GBPS_OPERATION); + ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION; + + /* Get Controller configuration */ + if (cdev->gadget->ops->get_config_params) { + cdev->gadget->ops->get_config_params( + &dcd_config_params); + } else { + dcd_config_params.bU1devExitLat = + USB_DEFAULT_U1_DEV_EXIT_LAT; + dcd_config_params.bU2DevExitLat = + cpu_to_le16(USB_DEFAULT_U2_DEV_EXIT_LAT); + } + ss_cap->bU1devExitLat = dcd_config_params.bU1devExitLat; + ss_cap->bU2DevExitLat = dcd_config_params.bU2DevExitLat; + } + + return le16_to_cpu(bos->wTotalLength); +} + static void device_qual(struct usb_composite_dev *cdev) { struct usb_qualifier_descriptor *qual = cdev->req->buf; @@ -343,6 +466,9 @@ static int set_config(struct usb_composite_dev *cdev, case USB_SPEED_HIGH: speed = "high"; break; + case USB_SPEED_SUPER: + speed = "super"; + break; default: speed = "?"; break; @@ -367,7 +493,9 @@ static int set_config(struct usb_composite_dev *cdev, * function's setup callback instead of the current * configuration's setup callback. */ - if (gadget->speed == USB_SPEED_HIGH) + if (gadget->speed == USB_SPEED_SUPER) + descriptors = f->ss_descriptors; + else if (gadget->speed == USB_SPEED_HIGH) descriptors = f->hs_descriptors; else descriptors = f->descriptors; @@ -447,8 +575,9 @@ int usb_add_config(struct usb_composite_dev *cdev, list_del(&config->list); config->cdev = NULL; } else { - debug("cfg %d/%p speeds:%s%s\n", + debug("cfg %d/%p speeds:%s%s%s\n", config->bConfigurationValue, config, + config->superspeed ? " super" : "", config->highspeed ? " high" : "", config->fullspeed ? (gadget_is_dualspeed(cdev->gadget) @@ -465,8 +594,24 @@ int usb_add_config(struct usb_composite_dev *cdev, } } + /* + * If one function of config is not super speed capable, + * force the gadget to be high speed so controller driver + * can init HW to be USB 2.0 + */ + if (gadget_is_superspeed(cdev->gadget)) { + list_for_each_entry(f, &config->functions, list) { + if (!f->ss_descriptors) + cdev->gadget->max_speed = + USB_SPEED_HIGH; + } + } + usb_ep_autoconfig_reset(cdev->gadget); + os_desc_config = config; + cdev->os_desc_config = os_desc_config; + done: if (status) debug("added config '%s'/%u --> %d\n", config->label, @@ -566,6 +711,16 @@ static int get_string(struct usb_composite_dev *cdev, return s->bLength; } + if (cdev->use_os_string && language == 0 && id == OS_STRING_IDX) { + struct usb_os_string *b = buf; + b->bLength = sizeof(*b); + b->bDescriptorType = USB_DT_STRING; + memcpy(&b->qwSignature, cdev->qw_sign, sizeof(b->qwSignature)); + b->bMS_VendorCode = cdev->b_vendor_code; + b->bPad = 0; + return sizeof(*b); + } + /* * Otherwise, look up and return a specified string. String IDs * are device-scoped, so we look up each string table we're told @@ -689,6 +844,156 @@ static void composite_setup_complete(struct usb_ep *ep, struct usb_request *req) req->status, req->actual, req->length); } +static int count_ext_compat(struct usb_configuration *c) +{ + int i, res; + + res = 0; + for (i = 0; i < c->next_interface_id; ++i) { + struct usb_function *f; + int j; + + f = c->interface[i]; + for (j = 0; j < f->os_desc_n; ++j) { + struct usb_os_desc *d; + + if (i != f->os_desc_table[j].if_id) + continue; + d = f->os_desc_table[j].os_desc; + if (d && d->ext_compat_id) + ++res; + } + } + BUG_ON(res > 255); + return res; +} + +static void fill_ext_compat(struct usb_configuration *c, u8 *buf) +{ + int i, count; + + count = 16; + for (i = 0; i < c->next_interface_id; ++i) { + struct usb_function *f; + int j; + + f = c->interface[i]; + for (j = 0; j < f->os_desc_n; ++j) { + struct usb_os_desc *d; + + if (i != f->os_desc_table[j].if_id) + continue; + d = f->os_desc_table[j].os_desc; + if (d && d->ext_compat_id) { + *buf++ = i; + *buf++ = 0x01; + memcpy(buf, d->ext_compat_id, 16); + buf += 22; + } else { + ++buf; + *buf = 0x01; + buf += 23; + } + count += 24; + if (count >= 4096) + return; + } + } +} + +static int count_ext_prop(struct usb_configuration *c, int interface) +{ + struct usb_function *f; + int j; + + f = c->interface[interface]; + for (j = 0; j < f->os_desc_n; ++j) { + struct usb_os_desc *d; + + if (interface != f->os_desc_table[j].if_id) + continue; + d = f->os_desc_table[j].os_desc; + if (d && d->ext_compat_id) + return d->ext_prop_count; + } + return 0; +} + +static int len_ext_prop(struct usb_configuration *c, int interface) +{ + struct usb_function *f; + struct usb_os_desc *d; + int j, res; + + res = 10; /* header length */ + f = c->interface[interface]; + for (j = 0; j < f->os_desc_n; ++j) { + if (interface != f->os_desc_table[j].if_id) + continue; + d = f->os_desc_table[j].os_desc; + if (d) + return min(res + d->ext_prop_len, 4096); + } + return res; +} + +static int fill_ext_prop(struct usb_configuration *c, int interface, u8 *buf) +{ + struct usb_function *f; + struct usb_os_desc *d; + struct usb_os_desc_ext_prop *ext_prop; + int j, count, n, ret; + u8 *start = buf; + + f = c->interface[interface]; + for (j = 0; j < f->os_desc_n; ++j) { + if (interface != f->os_desc_table[j].if_id) + continue; + d = f->os_desc_table[j].os_desc; + if (d) + list_for_each_entry(ext_prop, &d->ext_prop, entry) { + /* 4kB minus header length */ + n = buf - start; + if (n >= 4086) + return 0; + + count = ext_prop->data_len + + ext_prop->name_len + 14; + if (count > 4086 - n) + return -EINVAL; + usb_ext_prop_put_size(buf, count); + usb_ext_prop_put_type(buf, ext_prop->type); + ret = usb_ext_prop_put_name(buf, ext_prop->name, + ext_prop->name_len); + if (ret < 0) + return ret; + switch (ext_prop->type) { + case USB_EXT_PROP_UNICODE: + case USB_EXT_PROP_UNICODE_ENV: + case USB_EXT_PROP_UNICODE_LINK: + usb_ext_prop_put_unicode(buf, ret, + ext_prop->data, + ext_prop->data_len); + break; + case USB_EXT_PROP_BINARY: + usb_ext_prop_put_binary(buf, ret, + ext_prop->data, + ext_prop->data_len); + break; + case USB_EXT_PROP_LE32: + /* not implemented */ + case USB_EXT_PROP_BE32: + /* not implemented */ + default: + return -EINVAL; + } + buf += count; + } + } + + return 0; +} + /* * The setup() callback implements all the ep0 functionality that's * not handled lower down, in hardware or the hardware driver(like @@ -738,18 +1043,26 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) count_configs(cdev, USB_DT_DEVICE); cdev->desc.bMaxPacketSize0 = cdev->gadget->ep0->maxpacket; + if (gadget->speed >= USB_SPEED_SUPER) { + cdev->desc.bcdUSB = cpu_to_le16(0x0310); + cdev->desc.bMaxPacketSize0 = 9; + } else { + cdev->desc.bcdUSB = cpu_to_le16(0x0200); + } value = min(w_length, (u16) sizeof cdev->desc); memcpy(req->buf, &cdev->desc, value); break; case USB_DT_DEVICE_QUALIFIER: - if (!gadget_is_dualspeed(gadget)) + if (!gadget_is_dualspeed(gadget) || + gadget->speed >= USB_SPEED_SUPER) break; device_qual(cdev); value = min_t(int, w_length, sizeof(struct usb_qualifier_descriptor)); break; case USB_DT_OTHER_SPEED_CONFIG: - if (!gadget_is_dualspeed(gadget)) + if (!gadget_is_dualspeed(gadget) || + gadget->speed >= USB_SPEED_SUPER) break; case USB_DT_CONFIG: @@ -765,11 +1078,15 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) break; case USB_DT_BOS: /* - * The USB compliance test (USB 2.0 Command Verifier) - * issues this request. We should not run into the - * default path here. But return for now until - * the superspeed support is added. + * Super speed connection should support BOS, and + * USB compliance test (USB 2.0 Command Verifier) + * also issues this request, return for now for + * USB 2.0 connection. */ + if (gadget->speed >= USB_SPEED_SUPER) { + value = bos_desc(cdev); + value = min(w_length, (u16)value); + } break; default: goto unknown; @@ -834,6 +1151,91 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) break; default: unknown: + /* + * OS descriptors handling + */ + if (cdev->use_os_string && cdev->os_desc_config && + (ctrl->bRequestType & USB_TYPE_VENDOR) && + ctrl->bRequest == cdev->b_vendor_code) { + struct usb_configuration *os_desc_cfg; + u8 *buf; + int interface; + int count = 0; + + buf = req->buf; + os_desc_cfg = cdev->os_desc_config; + memset(buf, 0, w_length); + buf[5] = 0x01; + switch (ctrl->bRequestType & USB_RECIP_MASK) { + case USB_RECIP_DEVICE: + if (w_index != 0x4 || (w_value >> 8)) + break; + buf[6] = w_index; + if (w_length == 0x10) { + /* Number of ext compat interfaces */ + count = count_ext_compat(os_desc_cfg); + buf[8] = count; + count *= 24; /* 24 B/ext compat desc */ + count += 16; /* header */ + put_unaligned_le32(count, buf); + value = w_length; + } else { + /* "extended compatibility ID"s */ + count = count_ext_compat(os_desc_cfg); + buf[8] = count; + count *= 24; /* 24 B/ext compat desc */ + count += 16; /* header */ + put_unaligned_le32(count, buf); + buf += 16; + fill_ext_compat(os_desc_cfg, buf); + value = w_length; + } + break; + case USB_RECIP_INTERFACE: + if (w_index != 0x5 || (w_value >> 8)) + break; + interface = w_value & 0xFF; + buf[6] = w_index; + if (w_length == 0x0A) { + count = count_ext_prop(os_desc_cfg, + interface); + put_unaligned_le16(count, buf + 8); + count = len_ext_prop(os_desc_cfg, + interface); + put_unaligned_le32(count, buf); + + value = w_length; + } else { + count = count_ext_prop(os_desc_cfg, + interface); + put_unaligned_le16(count, buf + 8); + count = len_ext_prop(os_desc_cfg, + interface); + put_unaligned_le32(count, buf); + buf += 10; + value = fill_ext_prop(os_desc_cfg, + interface, buf); + if (value < 0) + return value; + + value = w_length; + } + break; + } + + if (value >= 0) { + req->length = value; + req->zero = value < w_length; + value = usb_ep_queue(gadget->ep0, req, GFP_KERNEL); + if (value < 0) { + debug("ep_queue --> %d\n", value); + req->status = 0; + composite_setup_complete(gadget->ep0, req); + } + } + return value; + } + debug("non-core control req%02x.%02x v%04x i%04x l%d\n", ctrl->bRequestType, ctrl->bRequest, w_value, w_index, w_length); @@ -1000,6 +1402,15 @@ static int composite_bind(struct usb_gadget *gadget) sizeof(struct usb_device_descriptor)); cdev->desc.bMaxPacketSize0 = gadget->ep0->maxpacket; + if (cdev->use_os_string) { + /* TODO: Do we want to pass this via platform? */ + cdev->b_vendor_code = 0x40; + + /* Microsoft OS String Descriptor */ + utf8_to_utf16le(qw_sign_buf, (__le16 *)cdev->qw_sign, + OS_STRING_QW_SIGN_LEN / 2); + } + debug("%s: ready\n", composite->name); return 0; @@ -1047,7 +1458,7 @@ composite_resume(struct usb_gadget *gadget) } static struct usb_gadget_driver composite_driver = { - .speed = USB_SPEED_HIGH, + .speed = USB_SPEED_SUPER, .bind = composite_bind, .unbind = composite_unbind, diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c index 6d6dbcb09c0..27a682a0d3e 100644 --- a/drivers/usb/gadget/epautoconf.c +++ b/drivers/usb/gadget/epautoconf.c @@ -170,6 +170,10 @@ static int ep_matches( size = 64; put_unaligned(cpu_to_le16(size), &desc->wMaxPacketSize); } + + if (gadget->ops->match_ep) + return gadget->ops->match_ep(gadget, ep, desc); + return 1; } @@ -261,6 +265,7 @@ struct usb_ep *usb_ep_autoconfig( ep = find_ep(gadget, "ep1-bulk"); if (ep && ep_matches(gadget, ep, desc)) return ep; +#ifndef CONFIG_SPL_BUILD } else if (gadget_is_dwc3(gadget)) { const char *name = NULL; /* @@ -283,6 +288,7 @@ struct usb_ep *usb_ep_autoconfig( ep = find_ep(gadget, name); if (ep && ep_matches(gadget, ep, desc)) return ep; +#endif } /* Second, look at endpoints until an unclaimed one looks usable */ diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 7acffb6c87e..f06cd6dc1c0 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -8,11 +8,15 @@ * Copyright 2014 Linaro, Ltd. * Rob Herring * + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include +#include #include #include #include @@ -21,15 +25,78 @@ #include #include #include +#include "../lib/avb/fsl/utils.h" #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV #include #endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#define ATAP_UUID_SIZE 32 +#define ATAP_UUID_STR_SIZE ((ATAP_UUID_SIZE*2) + 1) + +extern int armv7_init_nonsec(void); +extern void trusty_os_init(void); +#include +#endif + #ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV #include #endif +#ifdef CONFIG_FSL_FASTBOOT +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif + +#ifdef CONFIG_BCB_SUPPORT +#include "bcb.h" +#endif + +#ifdef CONFIG_AVB_SUPPORT +#include +#include +#endif + +#ifdef CONFIG_ANDROID_THINGS_SUPPORT +#include +#include +#include "../lib/avb/fsl/fsl_avbkey.h" +#include "../arch/arm/include/asm/mach-imx/hab.h" +#endif + +#ifdef CONFIG_FASTBOOT_LOCK +#include "fastboot_lock_unlock.h" +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#include "u-boot/sha256.h" +#endif + #define FASTBOOT_VERSION "0.4" +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) +#define FASTBOOT_COMMON_VAR_NUM 14 +#else +#define FASTBOOT_COMMON_VAR_NUM 13 +#endif + +#define FASTBOOT_VAR_YES "yes" +#define FASTBOOT_VAR_NO "no" #define FASTBOOT_INTERFACE_CLASS 0xff #define FASTBOOT_INTERFACE_SUB_CLASS 0x42 #define FASTBOOT_INTERFACE_PROTOCOL 0x03 @@ -39,18 +106,120 @@ #define TX_ENDPOINT_MAXIMUM_PACKET_SIZE (0x0040) #define EP_BUFFER_SIZE 4096 + +#ifdef CONFIG_FSL_FASTBOOT + +#define ANDROID_GPT_OFFSET 0 +#define ANDROID_GPT_SIZE 0x100000 +#define ANDROID_GPT_END 0x4400 + +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +struct fastboot_device_info fastboot_firmwareinfo; +#endif + +#if defined (CONFIG_ARCH_IMX8) || defined (CONFIG_ARCH_IMX8M) +#define DST_DECOMPRESS_LEN 1024*1024*32 +#endif + +#endif + +#ifdef CONFIG_ANDROID_THINGS_SUPPORT +#define FDT_PART_NAME "oem_bootloader" +#else +#define FDT_PART_NAME "dtbo" +#endif + +#define MEK_8QM_EMMC 0 + /* * EP_BUFFER_SIZE must always be an integral multiple of maxpacket size * (64 or 512 or 1024), else we break on certain controllers like DWC3 * that expect bulk OUT requests to be divisible by maxpacket size. */ +/* Offset (in u32's) of start and end fields in the zImage header. */ +#define ZIMAGE_START_ADDR 10 +#define ZIMAGE_END_ADDR 11 + +/* common variables of fastboot getvar command */ +char *fastboot_common_var[FASTBOOT_COMMON_VAR_NUM] = { + "version", + "version-bootloader", + "version-baseband", + "product", + "secure", + "max-download-size", + "erase-block-size", + "logical-block-size", + "unlocked", + "off-mode-charge", + "battery-voltage", + "variant", + "battery-soc-ok", +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) + "baseboard_id" +#endif +}; + +/* at-vboot-state variable list */ +#ifdef CONFIG_AVB_ATX +#define AT_VBOOT_STATE_VAR_NUM 6 +extern struct imx_sec_config_fuse_t const imx_sec_config_fuse; +extern int fuse_read(u32 bank, u32 word, u32 *val); + +char *fastboot_at_vboot_state_var[AT_VBOOT_STATE_VAR_NUM] = { + "bootloader-locked", + "bootloader-min-versions", + "avb-perm-attr-set", + "avb-locked", + "avb-unlock-disabled", + "avb-min-versions" +}; +#endif + +/* Boot metric variables */ +boot_metric metrics = { + .bll_1 = 0, + .ble_1 = 0, + .kl = 0, + .kd = 0, + .avb = 0, + .odt = 0, + .sw = 0 +}; + +typedef struct usb_req usb_req; +struct usb_req { + struct usb_request *in_req; + usb_req *next; +}; + struct f_fastboot { struct usb_function usb_function; /* IN/OUT EP's and corresponding requests */ struct usb_ep *in_ep, *out_ep; struct usb_request *in_req, *out_req; + usb_req *front, *rear; +}; + +static char fb_ext_prop_name[] = "DeviceInterfaceGUID"; +static char fb_ext_prop_data[] = "{4866319A-F4D6-4374-93B9-DC2DEB361BA9}"; + +static struct usb_os_desc_ext_prop fb_ext_prop = { + .type = 1, /* NUL-terminated Unicode String (REG_SZ) */ + .name = fb_ext_prop_name, + .data = fb_ext_prop_data, +}; + +/* 16 bytes of "Compatible ID" and "Subcompatible ID" */ +static char fb_cid[16] = {'W', 'I', 'N', 'U', 'S', 'B'}; +static struct usb_os_desc fb_os_desc = { + .ext_compat_id = fb_cid, +}; + +static struct usb_os_desc_table fb_os_desc_table = { + .os_desc = &fb_os_desc, }; static inline struct f_fastboot *func_to_fastboot(struct usb_function *f) @@ -118,12 +287,48 @@ static struct usb_descriptor_header *fb_hs_function[] = { NULL, }; +/* Super speed */ +static struct usb_endpoint_descriptor ss_ep_in = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = cpu_to_le16(1024), +}; + +static struct usb_endpoint_descriptor ss_ep_out = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = cpu_to_le16(1024), +}; + +static struct usb_ss_ep_comp_descriptor fb_ss_bulk_comp_desc = { + .bLength = sizeof(fb_ss_bulk_comp_desc), + .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, +}; + +static struct usb_descriptor_header *fb_ss_function[] = { + (struct usb_descriptor_header *)&interface_desc, + (struct usb_descriptor_header *)&ss_ep_in, + (struct usb_descriptor_header *)&fb_ss_bulk_comp_desc, + (struct usb_descriptor_header *)&ss_ep_out, + (struct usb_descriptor_header *)&fb_ss_bulk_comp_desc, + NULL, +}; + static struct usb_endpoint_descriptor * fb_ep_desc(struct usb_gadget *g, struct usb_endpoint_descriptor *fs, - struct usb_endpoint_descriptor *hs) + struct usb_endpoint_descriptor *hs, + struct usb_endpoint_descriptor *ss) { + if (gadget_is_superspeed(g) && g->speed >= USB_SPEED_SUPER) + return ss; + if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH) return hs; + return fs; } @@ -153,251 +358,3774 @@ static int strcmp_l1(const char *s1, const char *s2); static char *fb_response_str; -void fastboot_fail(const char *reason) -{ - strncpy(fb_response_str, "FAIL\0", 5); - strncat(fb_response_str, reason, FASTBOOT_RESPONSE_LEN - 4 - 1); -} +#ifdef CONFIG_FSL_FASTBOOT -void fastboot_okay(const char *reason) -{ - strncpy(fb_response_str, "OKAY\0", 5); - strncat(fb_response_str, reason, FASTBOOT_RESPONSE_LEN - 4 - 1); -} +#ifndef TRUSTY_OS_MMC_BLKS +#define TRUSTY_OS_MMC_BLKS 0x7FF +#endif +#ifndef TEE_HWPARTITION_ID +#define TEE_HWPARTITION_ID 2 +#endif -static void fastboot_complete(struct usb_ep *ep, struct usb_request *req) -{ - int status = req->status; - if (!status) - return; - printf("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual); -} +#define FASTBOOT_PARTITION_ALL "all" -static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) +#define ANDROID_MBR_OFFSET 0 +#define ANDROID_MBR_SIZE 0x200 +#define ANDROID_BOOTLOADER_SIZE 0x400000 + +#define MMC_SATA_BLOCK_SIZE 512 +#define FASTBOOT_FBPARTS_ENV_MAX_LEN 1024 +/* To support the Android-style naming of flash */ +#define MAX_PTN 32 +struct fastboot_ptentry g_ptable[MAX_PTN]; +unsigned int g_pcount; +struct fastboot_device_info fastboot_devinfo = {0xff, 0xff}; + + +enum { + PTN_GPT_INDEX = 0, + PTN_TEE_INDEX, +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT + PTN_M4_OS_INDEX, +#endif + PTN_ALL_INDEX, + PTN_BOOTLOADER_INDEX, +}; +static unsigned int download_bytes_unpadded; + +static struct cmd_fastboot_interface interface = { + .rx_handler = NULL, + .reset_handler = NULL, + .product_name = NULL, + .serial_no = NULL, + .nand_block_size = 0, + .transfer_buffer = (unsigned char *)0xffffffff, + .transfer_buffer_size = 0, +}; + +int read_from_partition_multi(const char* partition, + int64_t offset, size_t num_bytes, void* buffer, size_t* out_num_read) { - int id; - struct usb_gadget *gadget = c->cdev->gadget; - struct f_fastboot *f_fb = func_to_fastboot(f); - const char *s; + struct fastboot_ptentry *pte; + unsigned char *bdata; + unsigned char *out_buf = (unsigned char *)buffer; + unsigned char *dst, *dst64 = NULL; + unsigned long blksz; + unsigned long s, cnt; + size_t num_read = 0; + lbaint_t part_start, part_end, bs, be, bm, blk_num; + margin_pos_t margin; + struct blk_desc *fs_dev_desc = NULL; + int dev_no; + int ret; - /* DYNAMIC interface numbers assignments */ - id = usb_interface_id(c, f); - if (id < 0) - return id; - interface_desc.bInterfaceNumber = id; + assert(buffer != NULL && out_num_read != NULL); - id = usb_string_id(c->cdev); - if (id < 0) - return id; - fastboot_string_defs[0].id = id; - interface_desc.iInterface = id; + dev_no = mmc_get_env_dev(); + if ((fs_dev_desc = blk_get_dev("mmc", dev_no)) == NULL) { + printf("mmc device not found\n"); + return -1; + } - f_fb->in_ep = usb_ep_autoconfig(gadget, &fs_ep_in); - if (!f_fb->in_ep) - return -ENODEV; - f_fb->in_ep->driver_data = c->cdev; + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + printf("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return -1; + } - f_fb->out_ep = usb_ep_autoconfig(gadget, &fs_ep_out); - if (!f_fb->out_ep) - return -ENODEV; - f_fb->out_ep->driver_data = c->cdev; + blksz = fs_dev_desc->blksz; + part_start = pte->start; + part_end = pte->start + pte->length - 1; - f->descriptors = fb_fs_function; + if (get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, true)) + return -1; - if (gadget_is_dualspeed(gadget)) { - /* Assume endpoint addresses are the same for both speeds */ - hs_ep_in.bEndpointAddress = fs_ep_in.bEndpointAddress; - hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress; - /* copy HS descriptors */ - f->hs_descriptors = fb_hs_function; + bs = (lbaint_t)margin.blk_start; + be = (lbaint_t)margin.blk_end; + s = margin.start; + bm = margin.multi; + + /* alloc a blksz mem */ + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) { + printf("Failed to allocate memory!\n"); + return -1; } - s = env_get("serial#"); - if (s) - g_dnl_set_serialnumber((char *)s); + /* support multi blk read */ + while (bs <= be) { + if (!s && bm > 1) { + dst = out_buf; + dst64 = PTR_ALIGN(out_buf, 64); /* for mmc blk read alignment */ + if (dst64 != dst) { + dst = dst64; + bm--; + } + blk_num = bm; + cnt = bm * blksz; + bm = 0; /* no more multi blk */ + } else { + blk_num = 1; + cnt = blksz - s; + if (num_read + cnt > num_bytes) + cnt = num_bytes - num_read; + dst = bdata; + } + if (blk_dread(fs_dev_desc, bs, blk_num, dst) != blk_num) { + ret = -1; + goto fail; + } - return 0; + if (dst == bdata) + memcpy(out_buf, bdata + s, cnt); + else if (dst == dst64) + memcpy(out_buf, dst, cnt); /* internal copy */ + + s = 0; + bs += blk_num; + num_read += cnt; + out_buf += cnt; + } + *out_num_read = num_read; + ret = 0; + +fail: + free(bdata); + return ret; } -static void fastboot_unbind(struct usb_configuration *c, struct usb_function *f) +static void save_env(struct fastboot_ptentry *ptn, + char *var, char *val) { - memset(fastboot_func, 0, sizeof(*fastboot_func)); + env_set(var, val); + env_save(); } -static void fastboot_disable(struct usb_function *f) +/* When save = 0, just parse. The input is unchanged + When save = 1, parse and do the save. The input is changed */ +static int parse_env(void *ptn, char *err_string, int save, int debug) { - struct f_fastboot *f_fb = func_to_fastboot(f); + int ret = 1; + unsigned int sets = 0; + unsigned int comment_start = 0; + char *var = NULL; + char *var_end = NULL; + char *val = NULL; + char *val_end = NULL; + unsigned int i; - usb_ep_disable(f_fb->out_ep); - usb_ep_disable(f_fb->in_ep); + char *buff = (char *)interface.transfer_buffer; + unsigned int size = download_bytes_unpadded; - if (f_fb->out_req) { - free(f_fb->out_req->buf); - usb_ep_free_request(f_fb->out_ep, f_fb->out_req); - f_fb->out_req = NULL; - } - if (f_fb->in_req) { - free(f_fb->in_req->buf); - usb_ep_free_request(f_fb->in_ep, f_fb->in_req); - f_fb->in_req = NULL; - } -} + /* The input does not have to be null terminated. + This will cause a problem in the corner case + where the last line does not have a new line. + Put a null after the end of the input. -static struct usb_request *fastboot_start_ep(struct usb_ep *ep) -{ - struct usb_request *req; + WARNING : Input buffer is assumed to be bigger + than the size of the input */ + if (save) + buff[size] = 0; - req = usb_ep_alloc_request(ep, 0); - if (!req) - return NULL; + for (i = 0; i < size; i++) { - req->length = EP_BUFFER_SIZE; - req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, EP_BUFFER_SIZE); - if (!req->buf) { - usb_ep_free_request(ep, req); - return NULL; - } + if (NULL == var) { - memset(req->buf, 0, req->length); - return req; -} + /* + * Check for comments, comment ok only on + * mostly empty lines + */ + if (buff[i] == '#') + comment_start = 1; -static int fastboot_set_alt(struct usb_function *f, - unsigned interface, unsigned alt) -{ - int ret; - struct usb_composite_dev *cdev = f->config->cdev; - struct usb_gadget *gadget = cdev->gadget; - struct f_fastboot *f_fb = func_to_fastboot(f); - const struct usb_endpoint_descriptor *d; + if (comment_start) { + if ((buff[i] == '\r') || + (buff[i] == '\n')) { + comment_start = 0; + } + } else { + if (!((buff[i] == ' ') || + (buff[i] == '\t') || + (buff[i] == '\r') || + (buff[i] == '\n'))) { + /* + * Normal whitespace before the + * variable + */ + var = &buff[i]; + } + } - debug("%s: func: %s intf: %d alt: %d\n", - __func__, f->name, interface, alt); + } else if (((NULL == var_end) || (NULL == val)) && + ((buff[i] == '\r') || (buff[i] == '\n'))) { - d = fb_ep_desc(gadget, &fs_ep_out, &hs_ep_out); - ret = usb_ep_enable(f_fb->out_ep, d); - if (ret) { - puts("failed to enable out ep\n"); - return ret; - } + /* This is the case when a variable + is unset. */ - f_fb->out_req = fastboot_start_ep(f_fb->out_ep); - if (!f_fb->out_req) { - puts("failed to alloc out req\n"); - ret = -EINVAL; - goto err; - } - f_fb->out_req->complete = rx_handler_command; + if (save) { + /* Set the var end to null so the + normal string routines will work - d = fb_ep_desc(gadget, &fs_ep_in, &hs_ep_in); - ret = usb_ep_enable(f_fb->in_ep, d); - if (ret) { - puts("failed to enable in ep\n"); - goto err; - } + WARNING : This changes the input */ + buff[i] = '\0'; - f_fb->in_req = fastboot_start_ep(f_fb->in_ep); - if (!f_fb->in_req) { - puts("failed alloc req in\n"); - ret = -EINVAL; - goto err; - } - f_fb->in_req->complete = fastboot_complete; + save_env(ptn, var, val); - ret = usb_ep_queue(f_fb->out_ep, f_fb->out_req, 0); - if (ret) - goto err; + if (debug) + printf("Unsetting %s\n", var); + } - return 0; -err: - fastboot_disable(f); - return ret; -} + /* Clear the variable so state is parse is back + to initial. */ + var = NULL; + var_end = NULL; + sets++; + } else if (NULL == var_end) { + if ((buff[i] == ' ') || + (buff[i] == '\t')) + var_end = &buff[i]; + } else if (NULL == val) { + if (!((buff[i] == ' ') || + (buff[i] == '\t'))) + val = &buff[i]; + } else if (NULL == val_end) { + if ((buff[i] == '\r') || + (buff[i] == '\n')) { + /* look for escaped cr or ln */ + if ('\\' == buff[i - 1]) { + /* check for dos */ + if ((buff[i] == '\r') && + (buff[i+1] == '\n')) + buff[i + 1] = ' '; + buff[i - 1] = buff[i] = ' '; + } else { + val_end = &buff[i]; + } + } + } else { + sprintf(err_string, "Internal Error"); -static int fastboot_add(struct usb_configuration *c) -{ - struct f_fastboot *f_fb = fastboot_func; - int status; + if (debug) + printf("Internal error at %s %d\n", + __FILE__, __LINE__); + return 1; + } + /* Check if a var / val pair is ready */ + if (NULL != val_end) { + if (save) { + /* Set the end's with nulls so + normal string routines will + work. - debug("%s: cdev: 0x%p\n", __func__, c->cdev); + WARNING : This changes the input */ + *var_end = '\0'; + *val_end = '\0'; - if (!f_fb) { - f_fb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_fb)); - if (!f_fb) - return -ENOMEM; + save_env(ptn, var, val); - fastboot_func = f_fb; - memset(f_fb, 0, sizeof(*f_fb)); + if (debug) + printf("Setting %s %s\n", var, val); + } + + /* Clear the variable so state is parse is back + to initial. */ + var = NULL; + var_end = NULL; + val = NULL; + val_end = NULL; + + sets++; + } } - f_fb->usb_function.name = "f_fastboot"; - f_fb->usb_function.bind = fastboot_bind; - f_fb->usb_function.unbind = fastboot_unbind; - f_fb->usb_function.set_alt = fastboot_set_alt; - f_fb->usb_function.disable = fastboot_disable; - f_fb->usb_function.strings = fastboot_strings; + /* Corner case + Check for the case that no newline at end of the input */ + if ((NULL != var) && + (NULL == val_end)) { + if (save) { + /* case of val / val pair */ + if (var_end) + *var_end = '\0'; + /* else case handled by setting 0 past + the end of buffer. + Similar for val_end being null */ + save_env(ptn, var, val); - status = usb_add_function(c, &f_fb->usb_function); - if (status) { - free(f_fb); - fastboot_func = f_fb; + if (debug) { + if (var_end) + printf("Trailing Setting %s %s\n", var, val); + else + printf("Trailing Unsetting %s\n", var); + } + } + sets++; } + /* Did we set anything ? */ + if (0 == sets) + sprintf(err_string, "No variables set"); + else + ret = 0; - return status; + return ret; } -DECLARE_GADGET_BIND_CALLBACK(usb_dnl_fastboot, fastboot_add); -static int fastboot_tx_write(const char *buffer, unsigned int buffer_size) +static int saveenv_to_ptn(struct fastboot_ptentry *ptn, char *err_string) { - struct usb_request *in_req = fastboot_func->in_req; - int ret; + int ret = 1; + int save = 0; + int debug = 0; - memcpy(in_req->buf, buffer, buffer_size); - in_req->length = buffer_size; + /* err_string is only 32 bytes + Initialize with a generic error message. */ + sprintf(err_string, "%s", "Unknown Error"); + + /* Parse the input twice. + Only save to the enviroment if the entire input if correct */ + save = 0; + if (0 == parse_env(ptn, err_string, save, debug)) { + save = 1; + ret = parse_env(ptn, err_string, save, debug); + } + return ret; +} + +static int get_block_size(void); +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +static void process_flash_sf(const char *cmdbuf) +{ + int blksz = 0; + blksz = get_block_size(); + + if (download_bytes) { + struct fastboot_ptentry *ptn; + ptn = fastboot_flash_find_ptn(cmdbuf); + if (ptn == 0) { + fastboot_fail("partition does not exist"); + fastboot_flash_dump_ptn(); + } else if ((download_bytes > ptn->length * blksz)) { + fastboot_fail("image too large for partition"); + /* TODO : Improve check for yaffs write */ + } else { + int ret; + char sf_command[128]; + /* Normal case */ + /* Probe device */ + sprintf(sf_command, "sf probe"); + ret = run_command(sf_command, 0); + if (ret){ + fastboot_fail("Probe sf failed"); + return; + } + /* Erase */ + sprintf(sf_command, "sf erase 0x%x 0x%x", ptn->start * blksz, /*start*/ + ptn->length * blksz /*size*/); + ret = run_command(sf_command, 0); + if (ret) { + fastboot_fail("Erasing sf failed"); + return; + } + /* Write image */ + sprintf(sf_command, "sf write 0x%x 0x%x 0x%x", + (unsigned int)(ulong)interface.transfer_buffer, /* source */ + ptn->start * blksz, /* start */ + download_bytes /*size*/); + printf("sf write '%s'\n", ptn->name); + ret = run_command(sf_command, 0); + if (ret){ + fastboot_fail("Writing sf failed"); + return; + } + printf("sf write finished '%s'\n", ptn->name); + fastboot_okay(""); + } + } else { + fastboot_fail("no image downloaded"); + } +} + +#ifdef CONFIG_ARCH_IMX8M +/* Check if the mcu image is built for running from TCM */ +static bool is_tcm_image(unsigned char *image_addr) +{ + u32 stack; + + stack = *(u32 *)image_addr; + + if ((stack != (u32)ANDROID_MCU_FIRMWARE_HEADER_STACK)) { + printf("Please flash mcu firmware images for running from TCM\n"); + return false; + } else + return true; +} + +static int do_bootmcu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret; + size_t out_num_read; + void *m4_base_addr = (void *)M4_BOOTROM_BASE_ADDR; + char command[32]; + + ret = read_from_partition_multi(FASTBOOT_MCU_FIRMWARE_PARTITION, + 0, ANDROID_MCU_FIRMWARE_SIZE, (void *)m4_base_addr, &out_num_read); + if ((ret != 0) || (out_num_read != ANDROID_MCU_FIRMWARE_SIZE)) { + printf("Read M4 images failed!\n"); + return 1; + } else { + printf("run command: 'bootaux 0x%x'\n",(unsigned int)(ulong)m4_base_addr); + + sprintf(command, "bootaux 0x%x", (unsigned int)(ulong)m4_base_addr); + ret = run_command(command, 0); + if (ret) { + printf("run 'bootaux' command failed!\n"); + return 1; + } + } + return 0; +} + +U_BOOT_CMD( + bootmcu, 1, 0, do_bootmcu, + "boot mcu images\n", + "boot mcu images from 'm4_os' partition, only support images run from TCM" +); +#endif +#endif /* CONFIG_FLASH_MCUFIRMWARE_SUPPORT */ + +static ulong bootloader_mmc_offset(void) +{ + if (is_imx8m() || (is_imx8() && is_soc_rev(CHIP_REV_A))) + return 0x8400; + else if (is_imx8qm()) { + if (MEK_8QM_EMMC == fastboot_devinfo.dev_id) + /* target device is eMMC boot0 partition, bootloader offset is 0x0 */ + return 0x0; + else + /* target device is SD card, bootloader offset is 0x8000 */ + return 0x8000; + } + else if (is_imx8()) + return 0x8000; + else + return 0x400; +} + +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) || defined(CONFIG_FASTBOOT_STORAGE_SATA) +static int is_raw_partition(struct fastboot_ptentry *ptn) +{ +#ifdef CONFIG_ANDROID_AB_SUPPORT + if (ptn && (!strncmp(ptn->name, FASTBOOT_PARTITION_BOOTLOADER, + strlen(FASTBOOT_PARTITION_BOOTLOADER)) || + !strncmp(ptn->name, FASTBOOT_PARTITION_GPT, + strlen(FASTBOOT_PARTITION_GPT)) || + !strncmp(ptn->name, FASTBOOT_PARTITION_BOOT_A, + strlen(FASTBOOT_PARTITION_BOOT_A)) || + !strncmp(ptn->name, FASTBOOT_PARTITION_BOOT_B, + strlen(FASTBOOT_PARTITION_BOOT_B)) || +#ifdef CONFIG_FASTBOOT_LOCK + !strncmp(ptn->name, FASTBOOT_PARTITION_FBMISC, + strlen(FASTBOOT_PARTITION_FBMISC)) || +#endif + !strncmp(ptn->name, FASTBOOT_PARTITION_MISC, + strlen(FASTBOOT_PARTITION_MISC)))) { +#else + if (ptn && (!strncmp(ptn->name, FASTBOOT_PARTITION_BOOTLOADER, + strlen(FASTBOOT_PARTITION_BOOTLOADER)) || + !strncmp(ptn->name, FASTBOOT_PARTITION_BOOT, + strlen(FASTBOOT_PARTITION_BOOT)) || +#ifdef CONFIG_FASTBOOT_LOCK + !strncmp(ptn->name, FASTBOOT_PARTITION_FBMISC, + strlen(FASTBOOT_PARTITION_FBMISC)) || +#endif + !strncmp(ptn->name, FASTBOOT_PARTITION_MISC, + strlen(FASTBOOT_PARTITION_MISC)))) { +#endif + printf("support sparse flash partition for %s\n", ptn->name); + return 1; + } else + return 0; +} + +static lbaint_t mmc_sparse_write(struct sparse_storage *info, + lbaint_t blk, lbaint_t blkcnt, const void *buffer) +{ +#define SPARSE_FILL_BUF_SIZE (2 * 1024 * 1024) + + + struct blk_desc *dev_desc = (struct blk_desc *)info->priv; + ulong ret = 0; + void *data; + int fill_buf_num_blks, cnt; + + if ((unsigned long)buffer & (CONFIG_SYS_CACHELINE_SIZE - 1)) { + + fill_buf_num_blks = SPARSE_FILL_BUF_SIZE / info->blksz; + + data = memalign(CONFIG_SYS_CACHELINE_SIZE, fill_buf_num_blks * info->blksz); + + while (blkcnt) { + + if (blkcnt > fill_buf_num_blks) + cnt = fill_buf_num_blks; + else + cnt = blkcnt; + + memcpy(data, buffer, cnt * info->blksz); + + ret += blk_dwrite(dev_desc, blk, cnt, data); + + blk += cnt; + blkcnt -= cnt; + buffer = (void *)((unsigned long)buffer + cnt * info->blksz); + + } + + free(data); + } else { + ret = blk_dwrite(dev_desc, blk, blkcnt, buffer); + } + + return ret; +} + +static lbaint_t mmc_sparse_reserve(struct sparse_storage *info, + lbaint_t blk, lbaint_t blkcnt) +{ + return blkcnt; +} + +/*judge wether the gpt image and bootloader image are overlay*/ +bool bootloader_gpt_overlay(void) +{ + return (g_ptable[PTN_GPT_INDEX].partition_id == g_ptable[PTN_BOOTLOADER_INDEX].partition_id && + bootloader_mmc_offset() < ANDROID_GPT_END); +} + +int write_backup_gpt(void) +{ + int mmc_no = 0; + struct mmc *mmc; + struct blk_desc *dev_desc; + + mmc_no = fastboot_devinfo.dev_id; + mmc = find_mmc_device(mmc_no); + if (mmc == NULL) { + printf("invalid mmc device\n"); + return -1; + } + dev_desc = blk_get_dev("mmc", mmc_no); + if (dev_desc == NULL) { + printf("Can't get Block device MMC %d\n", + mmc_no); + return -ENODEV; + } + + /* write backup get partition */ + if (write_backup_gpt_partitions(dev_desc, interface.transfer_buffer)) { + printf("writing GPT image fail\n"); + return -1; + } + + printf("flash backup gpt image successfully\n"); + return 0; +} +static int get_fastboot_target_dev(char *mmc_dev, struct fastboot_ptentry *ptn) +{ + int dev = 0; + struct mmc *target_mmc; + + /* Support flash bootloader to mmc 'target_ubootdev' devices, if the + * 'target_ubootdev' env is not set just flash bootloader to current + * mmc device. + */ + if ((!strncmp(ptn->name, FASTBOOT_PARTITION_BOOTLOADER, + sizeof(FASTBOOT_PARTITION_BOOTLOADER))) && + (env_get("target_ubootdev"))) { + dev = simple_strtoul(env_get("target_ubootdev"), NULL, 10); + + /* if target_ubootdev is set, it must be that users want to change + * fastboot device, then fastboot environment need to be updated */ + fastboot_setup(); + + target_mmc = find_mmc_device(dev); + if ((target_mmc == NULL) || mmc_init(target_mmc)) { + printf("MMC card init failed!\n"); + return -1; + } else { + printf("Flash target is mmc%d\n", dev); + if (target_mmc->part_config != MMCPART_NOAVAILABLE) + sprintf(mmc_dev, "mmc dev %x %x", dev, /*slot no*/ + FASTBOOT_MMC_BOOT_PARTITION_ID/*part no*/); + else + sprintf(mmc_dev, "mmc dev %x", dev); + } + } else if (ptn->partition_id != FASTBOOT_MMC_NONE_PARTITION_ID) + sprintf(mmc_dev, "mmc dev %x %x", + fastboot_devinfo.dev_id, /*slot no*/ + ptn->partition_id /*part no*/); + else + sprintf(mmc_dev, "mmc dev %x", + fastboot_devinfo.dev_id /*slot no*/); + return 0; +} +static void process_flash_mmc(const char *cmdbuf) +{ + if (download_bytes) { + struct fastboot_ptentry *ptn; + + /* Next is the partition name */ + ptn = fastboot_flash_find_ptn(cmdbuf); + if (ptn == NULL) { + fastboot_fail("partition does not exist"); + fastboot_flash_dump_ptn(); + } else if ((download_bytes > + ptn->length * MMC_SATA_BLOCK_SIZE) && + !(ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_ENV)) { + printf("Image too large for the partition\n"); + fastboot_fail("image too large for partition"); + } else if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_ENV) { + /* Since the response can only be 64 bytes, + there is no point in having a large error message. */ + char err_string[32]; + if (saveenv_to_ptn(ptn, &err_string[0])) { + printf("savenv '%s' failed : %s\n", ptn->name, err_string); + fastboot_fail(err_string); + } else { + printf("partition '%s' saveenv-ed\n", ptn->name); + fastboot_okay(""); + } + } else { + unsigned int temp; + + char blk_dev[128]; + char blk_write[128]; + int blkret; + + printf("writing to partition '%s'\n", ptn->name); + /* Get target flash device. */ + if (get_fastboot_target_dev(blk_dev, ptn) != 0) + return; + + if (!is_raw_partition(ptn) && + is_sparse_image(interface.transfer_buffer)) { + int dev_no = 0; + struct mmc *mmc; + struct blk_desc *dev_desc; + disk_partition_t info; + struct sparse_storage sparse; + + dev_no = fastboot_devinfo.dev_id; + + printf("sparse flash target is %s:%d\n", + fastboot_devinfo.type == DEV_SATA ? "sata" : "mmc", + dev_no); + if (fastboot_devinfo.type == DEV_MMC) { + mmc = find_mmc_device(dev_no); + if (mmc && mmc_init(mmc)) + printf("MMC card init failed!\n"); + } + + dev_desc = blk_get_dev(fastboot_devinfo.type == DEV_SATA ? "sata" : "mmc", dev_no); + if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { + printf("** Block device %s %d not supported\n", + fastboot_devinfo.type == DEV_SATA ? "sata" : "mmc", + dev_no); + return; + } + + if( strncmp(ptn->name, FASTBOOT_PARTITION_ALL, + strlen(FASTBOOT_PARTITION_ALL)) == 0) { + info.blksz = dev_desc->blksz; + info.size = dev_desc->lba; + info.start = 0; + } else { + + if (part_get_info(dev_desc, + ptn->partition_index, &info)) { + printf("Bad partition index:%d for partition:%s\n", + ptn->partition_index, ptn->name); + return; + } + } + printf("writing to partition '%s' for sparse, buffer size %d\n", + ptn->name, download_bytes); + + sparse.blksz = info.blksz; + sparse.start = info.start; + sparse.size = info.size; + sparse.write = mmc_sparse_write; + sparse.reserve = mmc_sparse_reserve; + printf("Flashing sparse image at offset " LBAFU "\n", + sparse.start); + + sparse.priv = dev_desc; + write_sparse_image(&sparse, ptn->name, interface.transfer_buffer, + download_bytes); + + } else { + /* Will flash images in below case: + * 1. Is not gpt partition. + * 2. Is gpt partition but no overlay detected. + * */ + if (strncmp(ptn->name, "gpt", 3) || !bootloader_gpt_overlay()) { + /* block count */ + if (strncmp(ptn->name, "gpt", 3) == 0) { + temp = (ANDROID_GPT_END + + MMC_SATA_BLOCK_SIZE - 1) / + MMC_SATA_BLOCK_SIZE; + } else { + temp = (download_bytes + + MMC_SATA_BLOCK_SIZE - 1) / + MMC_SATA_BLOCK_SIZE; + } + + sprintf(blk_write, "%s write 0x%x 0x%x 0x%x", + fastboot_devinfo.type == DEV_SATA ? "sata" : "mmc", + (unsigned int)(uintptr_t)interface.transfer_buffer, /*source*/ + ptn->start, /*dest*/ + temp /*length*/); + + printf("Initializing '%s'\n", ptn->name); + + blkret = run_command(blk_dev, 0); + if (blkret) + fastboot_fail("Init of BLK device failed"); + else + fastboot_okay(""); + + printf("Writing '%s'\n", ptn->name); + if (run_command(blk_write, 0)) { + printf("Writing '%s' FAILED!\n", ptn->name); + fastboot_fail("Write partition failed"); + } else { + printf("Writing '%s' DONE!\n", ptn->name); + fastboot_okay(""); + } + } + /* Write backup gpt image */ + if (strncmp(ptn->name, "gpt", 3) == 0) { + if (write_backup_gpt()) + fastboot_fail("write backup GPT image fail"); + else + fastboot_okay(""); + + /* will force scan the device, + * so dev_desc can be re-inited + * with the latest data */ + run_command(blk_dev, 0); + } + } + } + } else { + fastboot_fail("no image downloaded"); + } +} + +#endif + +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) +static void process_erase_mmc(const char *cmdbuf, char *response) +{ + int mmc_no = 0; + lbaint_t blks, blks_start, blks_size, grp_size; + struct mmc *mmc; + struct blk_desc *dev_desc; + struct fastboot_ptentry *ptn; + disk_partition_t info; + + ptn = fastboot_flash_find_ptn(cmdbuf); + if ((ptn == NULL) || (ptn->flags & FASTBOOT_PTENTRY_FLAGS_UNERASEABLE)) { + sprintf(response, "FAILpartition does not exist or uneraseable"); + fastboot_flash_dump_ptn(); + return; + } + + mmc_no = fastboot_devinfo.dev_id; + printf("erase target is MMC:%d\n", mmc_no); + + mmc = find_mmc_device(mmc_no); + if ((mmc == NULL) || mmc_init(mmc)) { + printf("MMC card init failed!\n"); + return; + } + + dev_desc = blk_get_dev("mmc", mmc_no); + if (NULL == dev_desc) { + printf("Block device MMC %d not supported\n", + mmc_no); + sprintf(response, "FAILnot valid MMC card"); + return; + } + + if (part_get_info(dev_desc, + ptn->partition_index, &info)) { + printf("Bad partition index:%d for partition:%s\n", + ptn->partition_index, ptn->name); + sprintf(response, "FAILerasing of MMC card"); + return; + } + + /* Align blocks to erase group size to avoid erasing other partitions */ + grp_size = mmc->erase_grp_size; + blks_start = (info.start + grp_size - 1) & ~(grp_size - 1); + if (info.size >= grp_size) + blks_size = (info.size - (blks_start - info.start)) & + (~(grp_size - 1)); + else + blks_size = 0; + + printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n", + blks_start, blks_start + blks_size); + + blks = blk_derase(dev_desc, blks_start, blks_size); + if (blks != blks_size) { + printf("failed erasing from device %d", dev_desc->devnum); + sprintf(response, "FAILerasing of MMC card"); + return; + } + + printf("........ erased " LBAFU " bytes from '%s'\n", + blks_size * info.blksz, cmdbuf); + sprintf(response, "OKAY"); + + return; +} +#endif + +#if defined(CONFIG_FASTBOOT_STORAGE_SATA) +static void process_erase_sata(const char *cmdbuf, char *response) +{ + return; +} +#endif + +static void rx_process_erase(const char *cmdbuf, char *response) +{ + switch (fastboot_devinfo.type) { +#if defined(CONFIG_FASTBOOT_STORAGE_SATA) + case DEV_SATA: + process_erase_sata(cmdbuf, response); + break; +#endif +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) + case DEV_MMC: + process_erase_mmc(cmdbuf, response); + break; +#endif + default: + printf("Not support flash command for current device %d\n", + fastboot_devinfo.type); + sprintf(response, + "FAILfailed to flash device"); + break; + } +} + +static void rx_process_flash(const char *cmdbuf) +{ +/* Check if we need to flash mcu firmware */ +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT + if (!strncmp(cmdbuf, FASTBOOT_MCU_FIRMWARE_PARTITION, + sizeof(FASTBOOT_MCU_FIRMWARE_PARTITION))) { + switch (fastboot_firmwareinfo.type) { + case DEV_SF: + process_flash_sf(cmdbuf); + break; +#ifdef CONFIG_ARCH_IMX8M + case DEV_MMC: + if (is_tcm_image(interface.transfer_buffer)) + process_flash_mmc(cmdbuf); + break; +#endif + default: + printf("Don't support flash firmware\n"); + } + return; + } +#endif + /* Normal case */ + switch (fastboot_devinfo.type) { +#if defined(CONFIG_FASTBOOT_STORAGE_SATA) + case DEV_SATA: + process_flash_mmc(cmdbuf); + break; +#endif +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) + case DEV_MMC: + process_flash_mmc(cmdbuf); + break; +#endif + default: + printf("Not support flash command for current device %d\n", + fastboot_devinfo.type); + fastboot_fail("failed to flash device"); + break; + } +} + + +static void parameters_setup(void) +{ + interface.nand_block_size = 0; + interface.transfer_buffer = + (unsigned char *)env_get_ulong("fastboot_buffer", 16, CONFIG_FASTBOOT_BUF_ADDR); + interface.transfer_buffer_size = + CONFIG_FASTBOOT_BUF_SIZE; +} + +static int _fastboot_setup_dev(int *switched) +{ + char *fastboot_env; + struct fastboot_device_info devinfo;; + fastboot_env = env_get("fastboot_dev"); + + if (fastboot_env) { + if (!strcmp(fastboot_env, "sata")) { + devinfo.type = DEV_SATA; + devinfo.dev_id = 0; +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) + } else if (!strncmp(fastboot_env, "mmc", 3)) { + devinfo.type = DEV_MMC; + if(env_get("target_ubootdev")) + devinfo.dev_id = simple_strtoul(env_get("target_ubootdev"), NULL, 10); + else + devinfo.dev_id = mmc_get_env_dev(); +#endif + } else { + return 1; + } + } else { + return 1; + } +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT + /* For imx7ulp, flash m4 images directly to spi nor-flash, M4 will + * run automatically after powered on. For imx8mq, flash m4 images to + * physical partition 'm4_os', m4 will be kicked off by A core. */ + fastboot_firmwareinfo.type = ANDROID_MCU_FRIMWARE_DEV_TYPE; +#endif + + if (switched) { + if (devinfo.type != fastboot_devinfo.type || devinfo.dev_id != fastboot_devinfo.dev_id) + *switched = 1; + else + *switched = 0; + } + + fastboot_devinfo.type = devinfo.type; + fastboot_devinfo.dev_id = devinfo.dev_id; + + return 0; +} + +#if defined(CONFIG_FASTBOOT_STORAGE_SATA) \ + || defined(CONFIG_FASTBOOT_STORAGE_MMC) +/** + @mmc_dos_partition_index: the partition index in mbr. + @mmc_partition_index: the boot partition or user partition index, + not related to the partition table. + */ +static int _fastboot_parts_add_ptable_entry(int ptable_index, + int mmc_dos_partition_index, + int mmc_partition_index, + const char *name, + const char *fstype, + struct blk_desc *dev_desc, + struct fastboot_ptentry *ptable) +{ + disk_partition_t info; + + if (part_get_info(dev_desc, + mmc_dos_partition_index, &info)) { + debug("Bad partition index:%d for partition:%s\n", + mmc_dos_partition_index, name); + return -1; + } + ptable[ptable_index].start = info.start; + ptable[ptable_index].length = info.size; + ptable[ptable_index].partition_id = mmc_partition_index; + ptable[ptable_index].partition_index = mmc_dos_partition_index; + strncpy(ptable[ptable_index].name, (const char *)info.name, + sizeof(ptable[ptable_index].name) - 1); + +#ifdef CONFIG_PARTITION_UUIDS + strcpy(ptable[ptable_index].uuid, (const char *)info.uuid); +#endif +#ifdef CONFIG_ANDROID_AB_SUPPORT + if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM_A) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM_B) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_OEM_A) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_A) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_OEM_B) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_B) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA)) +#else + if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_DEVICE) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_CACHE)) +#endif + strcpy(ptable[ptable_index].fstype, "ext4"); + else + strcpy(ptable[ptable_index].fstype, "raw"); + return 0; +} + +static int _fastboot_parts_load_from_ptable(void) +{ + int i; +#ifdef CONFIG_CMD_SATA + int sata_device_no; +#endif + + /* mmc boot partition: -1 means no partition, 0 user part., 1 boot part. + * default is no partition, for emmc default user part, except emmc*/ + int boot_partition = FASTBOOT_MMC_NONE_PARTITION_ID; + int user_partition = FASTBOOT_MMC_NONE_PARTITION_ID; + + struct mmc *mmc; + struct blk_desc *dev_desc; + struct fastboot_ptentry ptable[MAX_PTN]; + + /* sata case in env */ + if (fastboot_devinfo.type == DEV_SATA) { +#ifdef CONFIG_CMD_SATA + puts("flash target is SATA\n"); + if (sata_initialize()) + return -1; + sata_device_no = CONFIG_FASTBOOT_SATA_NO; + if (sata_device_no >= CONFIG_SYS_SATA_MAX_DEVICE) { + printf("Unknown SATA(%d) device for fastboot\n", + sata_device_no); + return -1; + } + dev_desc = sata_get_dev(sata_device_no); +#else /*! CONFIG_CMD_SATA*/ + puts("SATA isn't buildin\n"); + return -1; +#endif /*! CONFIG_CMD_SATA*/ + } else if (fastboot_devinfo.type == DEV_MMC) { + int mmc_no = 0; + mmc_no = fastboot_devinfo.dev_id; + + printf("flash target is MMC:%d\n", mmc_no); + mmc = find_mmc_device(mmc_no); + + if (mmc == NULL) { + printf("invalid mmc device %d\n", mmc_no); + return -1; + } + + /* Force to init mmc */ + mmc->has_init = 0; + if (mmc_init(mmc)) + printf("MMC card init failed!\n"); + + dev_desc = blk_get_dev("mmc", mmc_no); + if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { + printf("** Block device MMC %d not supported\n", + mmc_no); + return -1; + } + + /* multiple boot paritions for eMMC 4.3 later */ + if (mmc->part_config != MMCPART_NOAVAILABLE) { + boot_partition = FASTBOOT_MMC_BOOT_PARTITION_ID; + user_partition = FASTBOOT_MMC_USER_PARTITION_ID; + } + } else { + printf("Can't setup partition table on this device %d\n", + fastboot_devinfo.type); + return -1; + } + + memset((char *)ptable, 0, + sizeof(struct fastboot_ptentry) * (MAX_PTN)); + /* GPT */ + strcpy(ptable[PTN_GPT_INDEX].name, FASTBOOT_PARTITION_GPT); + ptable[PTN_GPT_INDEX].start = ANDROID_GPT_OFFSET / dev_desc->blksz; + ptable[PTN_GPT_INDEX].length = ANDROID_GPT_SIZE / dev_desc->blksz; + ptable[PTN_GPT_INDEX].partition_id = user_partition; + ptable[PTN_GPT_INDEX].flags = FASTBOOT_PTENTRY_FLAGS_UNERASEABLE; + strcpy(ptable[PTN_GPT_INDEX].fstype, "raw"); + +#ifndef CONFIG_ARM64 + /* Trusty OS */ + strcpy(ptable[PTN_TEE_INDEX].name, FASTBOOT_PARTITION_TEE); + ptable[PTN_TEE_INDEX].start = 0; + ptable[PTN_TEE_INDEX].length = TRUSTY_OS_MMC_BLKS; + ptable[PTN_TEE_INDEX].partition_id = TEE_HWPARTITION_ID; + strcpy(ptable[PTN_TEE_INDEX].fstype, "raw"); +#endif + + /* Add m4_os partition if we support mcu firmware image flash */ +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT + strcpy(ptable[PTN_M4_OS_INDEX].name, FASTBOOT_MCU_FIRMWARE_PARTITION); + ptable[PTN_M4_OS_INDEX].start = ANDROID_MCU_FIRMWARE_START / dev_desc->blksz; + ptable[PTN_M4_OS_INDEX].length = ANDROID_MCU_FIRMWARE_SIZE / dev_desc->blksz; + ptable[PTN_M4_OS_INDEX].flags = FASTBOOT_PTENTRY_FLAGS_UNERASEABLE; + ptable[PTN_M4_OS_INDEX].partition_id = user_partition; + strcpy(ptable[PTN_M4_OS_INDEX].fstype, "raw"); +#endif + + strcpy(ptable[PTN_ALL_INDEX].name, FASTBOOT_PARTITION_ALL); + ptable[PTN_ALL_INDEX].start = 0; + ptable[PTN_ALL_INDEX].length = dev_desc->lba; + ptable[PTN_ALL_INDEX].partition_id = user_partition; + strcpy(ptable[PTN_ALL_INDEX].fstype, "device"); + + /* Bootloader */ + strcpy(ptable[PTN_BOOTLOADER_INDEX].name, FASTBOOT_PARTITION_BOOTLOADER); + ptable[PTN_BOOTLOADER_INDEX].start = + bootloader_mmc_offset() / dev_desc->blksz; + ptable[PTN_BOOTLOADER_INDEX].length = + ANDROID_BOOTLOADER_SIZE / dev_desc->blksz; + ptable[PTN_BOOTLOADER_INDEX].partition_id = boot_partition; + ptable[PTN_BOOTLOADER_INDEX].flags = FASTBOOT_PTENTRY_FLAGS_UNERASEABLE; + strcpy(ptable[PTN_BOOTLOADER_INDEX].fstype, "raw"); + + int tbl_idx; + int part_idx = 1; + int ret; + for (tbl_idx = PTN_BOOTLOADER_INDEX + 1; tbl_idx < MAX_PTN; tbl_idx++) { + ret = _fastboot_parts_add_ptable_entry(tbl_idx, + part_idx++, + user_partition, + NULL, + NULL, + dev_desc, ptable); + if (ret) + break; + } + for (i = 0; i < tbl_idx; i++) + fastboot_flash_add_ptn(&ptable[i]); + + return 0; +} +#endif /*CONFIG_FASTBOOT_STORAGE_SATA || CONFIG_FASTBOOT_STORAGE_MMC*/ + +static void _fastboot_load_partitions(void) +{ + g_pcount = 0; +#if defined(CONFIG_FASTBOOT_STORAGE_SATA) \ + || defined(CONFIG_FASTBOOT_STORAGE_MMC) + _fastboot_parts_load_from_ptable(); +#endif +} + +/* + * Android style flash utilties */ +void fastboot_flash_add_ptn(struct fastboot_ptentry *ptn) +{ + if (g_pcount < MAX_PTN) { + memcpy(g_ptable + g_pcount, ptn, sizeof(struct fastboot_ptentry)); + g_pcount++; + } +} + +void fastboot_flash_dump_ptn(void) +{ + unsigned int n; + for (n = 0; n < g_pcount; n++) { + struct fastboot_ptentry *ptn = g_ptable + n; + printf("idx %d, ptn %d name='%s' start=%d len=%d\n", + n, ptn->partition_index, ptn->name, ptn->start, ptn->length); + } +} + + +struct fastboot_ptentry *fastboot_flash_find_ptn(const char *name) +{ + unsigned int n; + + for (n = 0; n < g_pcount; n++) { + /* Make sure a substring is not accepted */ + if (strlen(name) == strlen(g_ptable[n].name)) { + if (0 == strcmp(g_ptable[n].name, name)) + return g_ptable + n; + } + } + + return 0; +} + +int fastboot_flash_find_index(const char *name) +{ + struct fastboot_ptentry *ptentry = fastboot_flash_find_ptn(name); + if (ptentry == NULL) { + printf("cannot get the partion info for %s\n",name); + fastboot_flash_dump_ptn(); + return -1; + } + return ptentry->partition_index; +} + +struct fastboot_ptentry *fastboot_flash_get_ptn(unsigned int n) +{ + if (n < g_pcount) + return g_ptable + n; + else + return 0; +} + +unsigned int fastboot_flash_get_ptn_count(void) +{ + return g_pcount; +} + +#ifdef CONFIG_FSL_FASTBOOT +void board_fastboot_setup(void) +{ +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) + static char boot_dev_part[32]; + u32 dev_no; +#endif + switch (get_boot_device()) { +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) + case SD1_BOOT: + case SD2_BOOT: + case SD3_BOOT: + case SD4_BOOT: + case MMC1_BOOT: + case MMC2_BOOT: + case MMC3_BOOT: + case MMC4_BOOT: + dev_no = mmc_get_env_dev(); + sprintf(boot_dev_part,"mmc%d",dev_no); + if (!env_get("fastboot_dev")) + env_set("fastboot_dev", boot_dev_part); + sprintf(boot_dev_part, "boota mmc%d", dev_no); + if (!env_get("bootcmd")) + env_set("bootcmd", boot_dev_part); + break; + case USB_BOOT: + printf("Detect USB boot. Will enter fastboot mode!\n"); + if (!env_get("bootcmd")) + env_set("bootcmd", "fastboot 0"); + break; +#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ + default: + if (!env_get("bootcmd")) + printf("unsupported boot devices\n"); + break; + } + + /* add soc type into bootargs */ + if (is_mx6dqp()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6qp"); + } else if (is_mx6dq()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6q"); + } else if (is_mx6sdl()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6dl"); + } else if (is_mx6sx()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6sx"); + } else if (is_mx6sl()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6sl"); + } else if (is_mx6ul()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6ul"); + } else if (is_mx7()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx7d"); + } else if (is_mx7ulp()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx7ulp"); + } else if (is_imx8qm()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx8qm"); + } else if (is_imx8qxp()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx8qxp"); + } else if (is_imx8mq()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx8mq"); + } else if (is_imx8mm()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx8mm"); + } +} + +#ifdef CONFIG_ANDROID_RECOVERY +void board_recovery_setup(void) +{ +/* boot from current mmc with avb verify */ +#ifdef CONFIG_AVB_SUPPORT + if (!env_get("bootcmd_android_recovery")) + env_set("bootcmd_android_recovery", "boota recovery"); +#else +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) + static char boot_dev_part[32]; + u32 dev_no; +#endif + int bootdev = get_boot_device(); + switch (bootdev) { +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) + case SD1_BOOT: + case SD2_BOOT: + case SD3_BOOT: + case SD4_BOOT: + case MMC1_BOOT: + case MMC2_BOOT: + case MMC3_BOOT: + case MMC4_BOOT: + dev_no = mmc_get_env_dev(); + sprintf(boot_dev_part,"boota mmc%d recovery",dev_no); + if (!env_get("bootcmd_android_recovery")) + env_set("bootcmd_android_recovery", boot_dev_part); + break; +#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ + default: + printf("Unsupported bootup device for recovery: dev: %d\n", + bootdev); + return; + } +#endif /* CONFIG_AVB_SUPPORT */ + printf("setup env for recovery..\n"); + env_set("bootcmd", env_get("bootcmd_android_recovery")); +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +#if defined(CONFIG_AVB_SUPPORT) && defined(CONFIG_MMC) +static AvbABOps fsl_avb_ab_ops = { + .read_ab_metadata = fsl_read_ab_metadata, + .write_ab_metadata = fsl_write_ab_metadata, + .ops = NULL +}; +#ifdef CONFIG_AVB_ATX +static AvbAtxOps fsl_avb_atx_ops = { + .ops = NULL, + .read_permanent_attributes = fsl_read_permanent_attributes, + .read_permanent_attributes_hash = fsl_read_permanent_attributes_hash, +#ifdef CONFIG_IMX_TRUSTY_OS + .set_key_version = fsl_write_rollback_index_rpmb, +#else + .set_key_version = fsl_set_key_version, +#endif + .get_random = fsl_get_random +}; +#endif +static AvbOps fsl_avb_ops = { + .ab_ops = &fsl_avb_ab_ops, +#ifdef CONFIG_AVB_ATX + .atx_ops = &fsl_avb_atx_ops, +#endif + .read_from_partition = fsl_read_from_partition_multi, + .write_to_partition = fsl_write_to_partition, +#ifdef CONFIG_AVB_ATX + .validate_vbmeta_public_key = avb_atx_validate_vbmeta_public_key, +#else + .validate_vbmeta_public_key = fsl_validate_vbmeta_public_key_rpmb, +#endif + .read_rollback_index = fsl_read_rollback_index_rpmb, + .write_rollback_index = fsl_write_rollback_index_rpmb, + .read_is_device_unlocked = fsl_read_is_device_unlocked, + .get_unique_guid_for_partition = fsl_get_unique_guid_for_partition, + .get_size_of_partition = fsl_get_size_of_partition +}; +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#ifdef CONFIG_ARM64 +void tee_setup(void) +{ + trusty_ipc_init(); +} + +#else +extern bool tos_flashed; + +void tee_setup(void) +{ + /* load tee from boot1 of eMMC. */ + int mmcc = mmc_get_env_dev(); + struct blk_desc *dev_desc = NULL; + + struct mmc *mmc; + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("boota: cannot find '%d' mmc device\n", mmcc); + goto fail; + } + + dev_desc = blk_get_dev("mmc", mmcc); + if (NULL == dev_desc) { + printf("** Block device MMC %d not supported\n", mmcc); + goto fail; + } + + /* below was i.MX mmc operation code */ + if (mmc_init(mmc)) { + printf("mmc%d init failed\n", mmcc); + goto fail; + } + + struct fastboot_ptentry *tee_pte; + char *tee_ptn = FASTBOOT_PARTITION_TEE; + tee_pte = fastboot_flash_find_ptn(tee_ptn); + mmc_switch_part(mmc, TEE_HWPARTITION_ID); + if (!tee_pte) { + printf("boota: cannot find tee partition!\n"); + fastboot_flash_dump_ptn(); + } + + if (blk_dread(dev_desc, tee_pte->start, + tee_pte->length, (void *)TRUSTY_OS_ENTRY) < 0) { + printf("Failed to load tee."); + } + mmc_switch_part(mmc, FASTBOOT_MMC_USER_PARTITION_ID); + + tos_flashed = false; + if(!valid_tos()) { + printf("TOS not flashed! Will enter TOS recovery mode. Everything will be wiped!\n"); + fastboot_wipe_all(); + run_command("fastboot 0", 0); + goto fail; + } +#ifdef NON_SECURE_FASTBOOT + armv7_init_nonsec(); + trusty_os_init(); + trusty_ipc_init(); +#endif + +fail: + return; + +} +#endif /* CONFIG_ARM64 */ +#endif /* CONFIG_IMX_TRUSTY_OS */ + +void fastboot_setup(void) +{ + int sw, ret; +#ifdef CONFIG_USB_GADGET + struct tag_serialnr serialnr; + char serial[17]; + + get_board_serial(&serialnr); + sprintf(serial, "%08x%08x", serialnr.high, serialnr.low); + g_dnl_set_serialnumber(serial); +#endif + /*execute board relevant initilizations for preparing fastboot */ + board_fastboot_setup(); + + /*get the fastboot dev*/ + ret = _fastboot_setup_dev(&sw); + + /*load partitions information for the fastboot dev*/ + if (!ret && sw) + _fastboot_load_partitions(); + + parameters_setup(); +#ifdef CONFIG_AVB_SUPPORT + fsl_avb_ab_ops.ops = &fsl_avb_ops; +#ifdef CONFIG_AVB_ATX + fsl_avb_atx_ops.ops = &fsl_avb_ops; +#endif +#endif +} + +/* Write the bcb with fastboot bootloader commands */ +static void enable_fastboot_command(void) +{ +#ifdef CONFIG_BCB_SUPPORT + char fastboot_command[32] = {0}; + strncpy(fastboot_command, FASTBOOT_BCB_CMD, 31); + bcb_write_command(fastboot_command); +#endif +} + +/* Get the Boot mode from BCB cmd or Key pressed */ +static FbBootMode fastboot_get_bootmode(void) +{ + int boot_mode = BOOTMODE_NORMAL; +#ifdef CONFIG_ANDROID_RECOVERY + if(is_recovery_key_pressing()) { + boot_mode = BOOTMODE_RECOVERY_KEY_PRESSED; + return boot_mode; + } +#endif +#ifdef CONFIG_BCB_SUPPORT + int ret = 0; + char command[32]; + ret = bcb_read_command(command); + if (ret < 0) { + printf("read command failed\n"); + return boot_mode; + } + if (!strcmp(command, FASTBOOT_BCB_CMD)) { + boot_mode = BOOTMODE_FASTBOOT_BCB_CMD; + } +#ifdef CONFIG_ANDROID_RECOVERY + else if (!strcmp(command, RECOVERY_BCB_CMD)) { + boot_mode = BOOTMODE_RECOVERY_BCB_CMD; + } +#endif + + /* Clean the mode once its read out, + no matter what in the mode string */ + memset(command, 0, 32); + bcb_write_command(command); +#endif + return boot_mode; +} + +#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT +/* Setup booargs for taking the system parition as ramdisk */ +static void fastboot_setup_system_boot_args(const char *slot, bool append_root) +{ + const char *system_part_name = NULL; + if(slot == NULL) + return; + if(!strncmp(slot, "_a", strlen("_a")) || !strncmp(slot, "boot_a", strlen("boot_a"))) { + system_part_name = FASTBOOT_PARTITION_SYSTEM_A; + } + else if(!strncmp(slot, "_b", strlen("_b")) || !strncmp(slot, "boot_b", strlen("boot_b"))) { + system_part_name = FASTBOOT_PARTITION_SYSTEM_B; + } else { + printf("slot invalid!\n"); + return; + } + struct fastboot_ptentry *ptentry = fastboot_flash_find_ptn(system_part_name); + if(ptentry != NULL) { + char bootargs_3rd[ANDR_BOOT_ARGS_SIZE]; +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) + if (append_root) { + u32 dev_no = mmc_map_to_kernel_blk(mmc_get_env_dev()); + sprintf(bootargs_3rd, "skip_initramfs root=/dev/mmcblk%dp%d", + dev_no, + ptentry->partition_index); + } else { + sprintf(bootargs_3rd, "skip_initramfs"); + } + strcat(bootargs_3rd, " rootwait"); + env_set("bootargs_3rd", bootargs_3rd); +#endif + } else { + printf("Can't find partition: %s\n", system_part_name); + fastboot_flash_dump_ptn(); + } +} +#endif +/* export to lib_arm/board.c */ +void fastboot_run_bootmode(void) +{ + FbBootMode boot_mode = fastboot_get_bootmode(); + switch(boot_mode){ + case BOOTMODE_FASTBOOT_BCB_CMD: + /* Make the boot into fastboot mode*/ + puts("Fastboot: Got bootloader commands!\n"); + run_command("fastboot 0", 0); + break; +#ifdef CONFIG_ANDROID_RECOVERY + case BOOTMODE_RECOVERY_BCB_CMD: + case BOOTMODE_RECOVERY_KEY_PRESSED: + /* Make the boot into recovery mode */ + puts("Fastboot: Got Recovery key pressing or recovery commands!\n"); + board_recovery_setup(); + break; +#endif + default: + /* skip special mode boot*/ + puts("Fastboot: Normal\n"); + break; + } +} + +#ifdef CONFIG_CMD_BOOTA + /* Section for Android bootimage format support + * Refer: + * http://android.git.kernel.org/?p=platform/system/core.git;a=blob; + * f=mkbootimg/bootimg.h + */ + +void +bootimg_print_image_hdr(struct andr_img_hdr *hdr) +{ +#ifdef DEBUG + int i; + printf(" Image magic: %s\n", hdr->magic); + + printf(" kernel_size: 0x%x\n", hdr->kernel_size); + printf(" kernel_addr: 0x%x\n", hdr->kernel_addr); + + printf(" rdisk_size: 0x%x\n", hdr->ramdisk_size); + printf(" rdisk_addr: 0x%x\n", hdr->ramdisk_addr); + + printf(" second_size: 0x%x\n", hdr->second_size); + printf(" second_addr: 0x%x\n", hdr->second_addr); + + printf(" tags_addr: 0x%x\n", hdr->tags_addr); + printf(" page_size: 0x%x\n", hdr->page_size); + + printf(" name: %s\n", hdr->name); + printf(" cmdline: %s\n", hdr->cmdline); + + for (i = 0; i < 8; i++) + printf(" id[%d]: 0x%x\n", i, hdr->id[i]); +#endif +} + +#if !defined(CONFIG_AVB_SUPPORT) || !defined(CONFIG_MMC) +static struct andr_img_hdr boothdr __aligned(ARCH_DMA_MINALIGN); +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_AVB_ATX) +static int sha256_concatenation(uint8_t *hash_buf, uint8_t *vbh, uint8_t *image_hash) +{ + if ((hash_buf == NULL) || (vbh == NULL) || (image_hash == NULL)) { + printf("sha256_concatenation: null buffer found!\n"); + return -1; + } + + memcpy(hash_buf, vbh, AVB_SHA256_DIGEST_SIZE); + memcpy(hash_buf + AVB_SHA256_DIGEST_SIZE, + image_hash, AVB_SHA256_DIGEST_SIZE); + sha256_csum_wd((unsigned char *)hash_buf, 2 * AVB_SHA256_DIGEST_SIZE, + (unsigned char *)vbh, CHUNKSZ_SHA256); + + return 0; +} + +/* Since we use fit format to organize the atf, tee, u-boot and u-boot dtb, + * so calculate the hash of fit is enough. + */ +static int vbh_bootloader(uint8_t *image_hash) +{ + char* slot_suffixes[2] = {"_a", "_b"}; + char partition_name[20]; + AvbABData ab_data; + uint8_t *image_buf = NULL; + uint32_t image_size; + size_t image_num_read; + int target_slot; + int ret = 0; + + /* Load A/B metadata and decide which slot we are going to load */ + if (fsl_avb_ab_ops.read_ab_metadata(&fsl_avb_ab_ops, &ab_data) != + AVB_IO_RESULT_OK) { + ret = -1; + goto fail ; + } + target_slot = get_curr_slot(&ab_data); + sprintf(partition_name, "bootloader%s", slot_suffixes[target_slot]); + + /* Read image header to find the image size */ + image_buf = (uint8_t *)malloc(MMC_SATA_BLOCK_SIZE); + if (fsl_avb_ops.read_from_partition(&fsl_avb_ops, partition_name, + 0, MMC_SATA_BLOCK_SIZE, + image_buf, &image_num_read)) { + printf("bootloader image load error!\n"); + ret = -1; + goto fail; + } + image_size = fdt_totalsize((struct image_header *)image_buf); + image_size = (image_size + 3) & ~3; + free(image_buf); + + /* Load full fit image */ + image_buf = (uint8_t *)malloc(image_size); + if (fsl_avb_ops.read_from_partition(&fsl_avb_ops, partition_name, + 0, image_size, + image_buf, &image_num_read)) { + printf("bootloader image load error!\n"); + ret = -1; + goto fail; + } + /* Calculate hash */ + sha256_csum_wd((unsigned char *)image_buf, image_size, + (unsigned char *)image_hash, CHUNKSZ_SHA256); + +fail: + if (image_buf != NULL) + free(image_buf); + return ret; +} + +int vbh_calculate(uint8_t *vbh, AvbSlotVerifyData *avb_out_data) +{ + uint8_t image_hash[AVB_SHA256_DIGEST_SIZE]; + uint8_t hash_buf[2 * AVB_SHA256_DIGEST_SIZE]; + uint8_t* image_buf = NULL; + uint32_t image_size; + size_t image_num_read; + int ret = 0; + + if (vbh == NULL) + return -1; + + /* Initial VBH (VBH0) should be 32 bytes 0 */ + memset(vbh, 0, AVB_SHA256_DIGEST_SIZE); + /* Load and calculate the sha256 hash of spl.bin */ + image_size = (ANDROID_SPL_SIZE + MMC_SATA_BLOCK_SIZE -1) / + MMC_SATA_BLOCK_SIZE; + image_buf = (uint8_t *)malloc(image_size); + if (fsl_avb_ops.read_from_partition(&fsl_avb_ops, + FASTBOOT_PARTITION_BOOTLOADER, + 0, image_size, + image_buf, &image_num_read)) { + printf("spl image load error!\n"); + ret = -1; + goto fail; + } + sha256_csum_wd((unsigned char *)image_buf, image_size, + (unsigned char *)image_hash, CHUNKSZ_SHA256); + /* Calculate VBH1 */ + if (sha256_concatenation(hash_buf, vbh, image_hash)) { + ret = -1; + goto fail; + } + free(image_buf); + + /* Load and calculate hash of bootloader.img */ + if (vbh_bootloader(image_hash)) { + ret = -1; + goto fail; + } + /* Calculate VBH2 */ + if (sha256_concatenation(hash_buf, vbh, image_hash)) { + ret = -1; + goto fail; + } + + /* Calculate the hash of vbmeta.img */ + avb_slot_verify_data_calculate_vbmeta_digest(avb_out_data, + AVB_DIGEST_TYPE_SHA256, + image_hash); + /* Calculate VBH3 */ + if (sha256_concatenation(hash_buf, vbh, image_hash)) { + ret = -1; + goto fail; + } + +fail: + if (image_buf != NULL) + free(image_buf); + return ret; +} +#endif /* CONFIG_DUAL_BOOTLOADER && CONFIG_AVB_ATX */ + +int trusty_setbootparameter(struct andr_img_hdr *hdr, AvbABFlowResult avb_result, + AvbSlotVerifyData *avb_out_data) { +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_AVB_ATX) + uint8_t vbh[AVB_SHA256_DIGEST_SIZE]; +#endif + int ret = 0; + u32 os_ver = hdr->os_version >> 11; + u32 os_ver_km = (((os_ver >> 14) & 0x7F) * 100 + ((os_ver >> 7) & 0x7F)) * 100 + + (os_ver & 0x7F); + u32 os_lvl = hdr->os_version & ((1U << 11) - 1); + u32 os_lvl_km = ((os_lvl >> 4) + 2000) * 100 + (os_lvl & 0x0F); + keymaster_verified_boot_t vbstatus; + FbLockState lock_status = fastboot_get_lock_stat(); + + uint8_t boot_key_hash[AVB_SHA256_DIGEST_SIZE]; +#ifdef CONFIG_AVB_ATX + if (fsl_read_permanent_attributes_hash(&fsl_avb_atx_ops, boot_key_hash)) { + printf("ERROR - failed to read permanent attributes hash for keymaster\n"); + memset(boot_key_hash, 0, AVB_SHA256_DIGEST_SIZE); + } +#else + uint8_t public_key_buf[AVB_MAX_BUFFER_LENGTH]; + if (trusty_read_vbmeta_public_key(public_key_buf, + AVB_MAX_BUFFER_LENGTH) != 0) { + printf("ERROR - failed to read public key for keymaster\n"); + memset(boot_key_hash, 0, AVB_SHA256_DIGEST_SIZE); + } else + sha256_csum_wd((unsigned char *)public_key_buf, AVB_SHA256_DIGEST_SIZE, + (unsigned char *)boot_key_hash, CHUNKSZ_SHA256); +#endif + + bool lock = (lock_status == FASTBOOT_LOCK)? true: false; + if (avb_result == AVB_AB_FLOW_RESULT_OK) + vbstatus = KM_VERIFIED_BOOT_VERIFIED; + else + vbstatus = KM_VERIFIED_BOOT_FAILED; + + /* Calculate VBH */ +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_AVB_ATX) + if (vbh_calculate(vbh, avb_out_data)) { + ret = -1; + goto fail; + } + + trusty_set_boot_params(os_ver_km, os_lvl_km, vbstatus, lock, + boot_key_hash, AVB_SHA256_DIGEST_SIZE, + vbh, AVB_SHA256_DIGEST_SIZE); +#else + trusty_set_boot_params(os_ver_km, os_lvl_km, vbstatus, lock, + boot_key_hash, AVB_SHA256_DIGEST_SIZE, + NULL, 0); +#endif + +fail: + return ret; +} +#endif + +#if defined(CONFIG_AVB_SUPPORT) && defined(CONFIG_MMC) +/* we can use avb to verify Trusty if we want */ +const char *requested_partitions_boot[] = {"boot", FDT_PART_NAME, NULL}; +const char *requested_partitions_recovery[] = {"recovery", FDT_PART_NAME, NULL}; + +static bool is_load_fdt_from_part(void) +{ +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) + if (fastboot_flash_find_ptn("oem_bootloader_a") && + fastboot_flash_find_ptn("oem_bootloader_b")) { +#elif defined(CONFIG_ANDROID_AB_SUPPORT) + if (fastboot_flash_find_ptn("dtbo_a") && + fastboot_flash_find_ptn("dtbo_b")) { +#else + /* for legacy platfrom (imx6/7), we don't support A/B slot. */ + if (fastboot_flash_find_ptn("dtbo")) { +#endif + return true; + } else { + return false; + } +} + +static int find_partition_data_by_name(char* part_name, + AvbSlotVerifyData* avb_out_data, AvbPartitionData** avb_loadpart) +{ + int num = 0; + AvbPartitionData* loadpart = NULL; + + for (num = 0; num < avb_out_data->num_loaded_partitions; num++) { + loadpart = &(avb_out_data->loaded_partitions[num]); + if (!(strncmp(loadpart->partition_name, + part_name, strlen(part_name)))) { + *avb_loadpart = loadpart; + break; + } + } + if (num == avb_out_data->num_loaded_partitions) { + printf("Error! Can't find %s partition from avb partition data!\n", + part_name); + return -1; + } + else + return 0; +} + +int do_boota(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + + ulong addr = 0; + struct andr_img_hdr *hdr = NULL; + void *boot_buf = NULL; + ulong image_size; + u32 avb_metric; + bool check_image_arm64 = false; + bool is_recovery_mode = false; + + AvbABFlowResult avb_result; + AvbSlotVerifyData *avb_out_data = NULL; + AvbPartitionData *avb_loadpart = NULL; + + /* get bootmode, default to boot "boot" */ + if (argc > 1) { + is_recovery_mode = + (strncmp(argv[1], "recovery", sizeof("recovery")) != 0) ? false: true; + if (is_recovery_mode) + printf("Will boot from recovery!\n"); + } + + /* check lock state */ + FbLockState lock_status = fastboot_get_lock_stat(); + if (lock_status == FASTBOOT_LOCK_ERROR) { +#ifdef CONFIG_AVB_ATX + printf("In boota get fastboot lock status error, enter fastboot mode.\n"); + goto fail; +#else + printf("In boota get fastboot lock status error. Set lock status\n"); + fastboot_set_lock_stat(FASTBOOT_LOCK); + lock_status = FASTBOOT_LOCK; +#endif + } + bool allow_fail = (lock_status == FASTBOOT_UNLOCK ? true : false); + avb_metric = get_timer(0); + /* we don't need to verify fdt partition if we don't have it. */ + if (!is_load_fdt_from_part()) { + requested_partitions_boot[1] = NULL; + requested_partitions_recovery[1] = NULL; + } +#ifndef CONFIG_ANDROID_AB_SUPPORT + else if (is_recovery_mode){ + requested_partitions_recovery[1] = NULL; + } +#endif + + /* if in lock state, do avb verify */ +#ifndef CONFIG_DUAL_BOOTLOADER + /* For imx6 on Android, we don't have a/b slot and we want to verify + * boot/recovery with AVB. For imx8 and Android Things we don't have + * recovery and support a/b slot for boot */ +#ifdef CONFIG_ANDROID_AB_SUPPORT + /* we can use avb to verify Trusty if we want */ + avb_result = avb_ab_flow_fast(&fsl_avb_ab_ops, requested_partitions_boot, allow_fail, + AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, &avb_out_data); +#else + if (!is_recovery_mode) { + avb_result = avb_single_flow(&fsl_avb_ab_ops, requested_partitions_boot, allow_fail, + AVB_HASHTREE_ERROR_MODE_RESTART, &avb_out_data); + } else { + avb_result = avb_single_flow(&fsl_avb_ab_ops, requested_partitions_recovery, allow_fail, + AVB_HASHTREE_ERROR_MODE_RESTART, &avb_out_data); + } +#endif +#else /* !CONFIG_DUAL_BOOTLOADER */ + /* We will only verify single one slot which has been selected in SPL */ + avb_result = avb_flow_dual_uboot(&fsl_avb_ab_ops, requested_partitions_boot, allow_fail, + AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, &avb_out_data); + + /* Reboot if current slot is not bootable. */ + if (avb_result == AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS) { + printf("boota: slot verify fail!\n"); + do_reset(NULL, 0, 0, NULL); + } +#endif /* !CONFIG_DUAL_BOOTLOADER */ + + /* get the duration of avb */ + metrics.avb = get_timer(avb_metric); + + if ((avb_result == AVB_AB_FLOW_RESULT_OK) || + (avb_result == AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR)) { + assert(avb_out_data != NULL); + /* We may have more than one partition loaded by AVB, find the boot + * partition first. + */ +#ifdef CONFIG_ANDROID_AB_SUPPORT + if (find_partition_data_by_name("boot", avb_out_data, &avb_loadpart)) + goto fail; +#else + if (!is_recovery_mode) { + if (find_partition_data_by_name("boot", avb_out_data, &avb_loadpart)) + goto fail; + } else { + if (find_partition_data_by_name("recovery", avb_out_data, &avb_loadpart)) + goto fail; + } +#endif + assert(avb_loadpart != NULL); + /* we should use avb_part_data->data as boot image */ + /* boot image is already read by avb */ + hdr = (struct andr_img_hdr *)avb_loadpart->data; + if (android_image_check_header(hdr)) { + printf("boota: bad boot image magic\n"); + goto fail; + } + if (avb_result == AVB_AB_FLOW_RESULT_OK) + printf(" verify OK, boot '%s%s'\n", + avb_loadpart->partition_name, avb_out_data->ab_suffix); + else { + printf(" verify FAIL, state: UNLOCK\n"); + printf(" boot '%s%s' still\n", + avb_loadpart->partition_name, avb_out_data->ab_suffix); + } + char bootargs_sec[ANDR_BOOT_EXTRA_ARGS_SIZE]; + if (lock_status == FASTBOOT_LOCK) { + snprintf(bootargs_sec, sizeof(bootargs_sec), + "androidboot.verifiedbootstate=green androidboot.slot_suffix=%s %s", + avb_out_data->ab_suffix, avb_out_data->cmdline); + } else { + snprintf(bootargs_sec, sizeof(bootargs_sec), + "androidboot.verifiedbootstate=orange androidboot.slot_suffix=%s %s", + avb_out_data->ab_suffix, avb_out_data->cmdline); + } + env_set("bootargs_sec", bootargs_sec); +#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT + if(!is_recovery_mode) { + if(avb_out_data->cmdline != NULL && strstr(avb_out_data->cmdline, "root=")) + fastboot_setup_system_boot_args(avb_out_data->ab_suffix, false); + else + fastboot_setup_system_boot_args(avb_out_data->ab_suffix, true); + } +#endif /* CONFIG_SYSTEM_RAMDISK_SUPPORT */ + image_size = avb_loadpart->data_size; +#if defined (CONFIG_ARCH_IMX8) || defined (CONFIG_ARCH_IMX8M) + /* If we are using uncompressed kernel image, copy it directly to + * hdr->kernel_addr, if we are using compressed lz4 kernel image, + * we need to decompress the kernel image first. */ + if (image_arm64((void *)((ulong)hdr + hdr->page_size))) { + memcpy((void *)(long)hdr->kernel_addr, + (void *)((ulong)hdr + hdr->page_size), hdr->kernel_size); + } else { +#ifdef CONFIG_LZ4 + size_t lz4_len = DST_DECOMPRESS_LEN; + if (ulz4fn((void *)((ulong)hdr + hdr->page_size), + hdr->kernel_size, (void *)(ulong)hdr->kernel_addr, &lz4_len) != 0) { + printf("Decompress kernel fail!\n"); + goto fail; + } +#else /* CONFIG_LZ4 */ + printf("please enable CONFIG_LZ4 if we're using compressed lz4 kernel image!\n"); + goto fail; +#endif /* CONFIG_LZ4 */ + } +#else /* CONFIG_ARCH_IMX8 || CONFIG_ARCH_IMX8M */ + /* copy kernel image and boot header to hdr->kernel_addr - hdr->page_size */ + memcpy((void *)(ulong)(hdr->kernel_addr - hdr->page_size), (void *)hdr, + hdr->page_size + ALIGN(hdr->kernel_size, hdr->page_size)); +#endif /* CONFIG_ARCH_IMX8 || CONFIG_ARCH_IMX8M */ + } else { + /* Fall into fastboot mode if get unacceptable error from avb + * or verify fail in lock state. + */ + if (lock_status == FASTBOOT_LOCK) + printf(" verify FAIL, state: LOCK\n"); + + goto fail; + } + + flush_cache((ulong)load_addr, image_size); + check_image_arm64 = image_arm64((void *)(ulong)hdr->kernel_addr); +#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT + if (is_recovery_mode) + memcpy((void *)(ulong)hdr->ramdisk_addr, (void *)(ulong)hdr + hdr->page_size + + ALIGN(hdr->kernel_size, hdr->page_size), hdr->ramdisk_size); +#else + memcpy((void *)(ulong)hdr->ramdisk_addr, (void *)(ulong)hdr + hdr->page_size + + ALIGN(hdr->kernel_size, hdr->page_size), hdr->ramdisk_size); +#endif +#ifdef CONFIG_OF_LIBFDT + /* load the dtb file */ + u32 fdt_size = 0; + struct dt_table_header *dt_img = NULL; + + if (is_load_fdt_from_part()) { +#ifdef CONFIG_ANDROID_THINGS_SUPPORT + if (find_partition_data_by_name("oem_bootloader", + avb_out_data, &avb_loadpart)) { + goto fail; + } else + dt_img = (struct dt_table_header *)avb_loadpart->data; +#elif defined(CONFIG_ANDROID_AB_SUPPORT) + if (find_partition_data_by_name("dtbo", + avb_out_data, &avb_loadpart)) { + goto fail; + } else + dt_img = (struct dt_table_header *)avb_loadpart->data; +#else + if (is_recovery_mode) { + if (hdr->header_version != 1) { + printf("boota: boot image header version error!\n"); + goto fail; + } + + dt_img = (struct dt_table_header *)((void *)(ulong)hdr + + hdr->page_size + + ALIGN(hdr->kernel_size, hdr->page_size) + + ALIGN(hdr->ramdisk_size, hdr->page_size) + + ALIGN(hdr->second_size, hdr->page_size)); + } else if (find_partition_data_by_name("dtbo", + avb_out_data, &avb_loadpart)) { + goto fail; + } else + dt_img = (struct dt_table_header *)avb_loadpart->data; +#endif + + if (be32_to_cpu(dt_img->magic) != DT_TABLE_MAGIC) { + printf("boota: bad dt table magic %08x\n", + be32_to_cpu(dt_img->magic)); + goto fail; + } else if (!be32_to_cpu(dt_img->dt_entry_count)) { + printf("boota: no dt entries\n"); + goto fail; + } + + struct dt_table_entry *dt_entry; + dt_entry = (struct dt_table_entry *)((ulong)dt_img + + be32_to_cpu(dt_img->dt_entries_offset)); + fdt_size = be32_to_cpu(dt_entry->dt_size); + memcpy((void *)(ulong)hdr->second_addr, (void *)((ulong)dt_img + + be32_to_cpu(dt_entry->dt_offset)), fdt_size); + } else { + if (hdr->second_size && hdr->second_addr) { + memcpy((void *)(ulong)hdr->second_addr, + (void *)(ulong)hdr + hdr->page_size + + ALIGN(hdr->kernel_size, hdr->page_size) + + ALIGN(hdr->ramdisk_size, hdr->page_size), + hdr->second_size); + } + } +#endif /*CONFIG_OF_LIBFDT*/ + + if (check_image_arm64) { + android_image_get_kernel(hdr, 0, NULL, NULL); + addr = hdr->kernel_addr; + } else { + addr = (ulong)(hdr->kernel_addr - hdr->page_size); + } + printf("kernel @ %08x (%d)\n", hdr->kernel_addr, hdr->kernel_size); + printf("ramdisk @ %08x (%d)\n", hdr->ramdisk_addr, hdr->ramdisk_size); +#ifdef CONFIG_OF_LIBFDT + if (is_load_fdt_from_part()) { + if (fdt_size) + printf("fdt @ %08x (%d)\n", hdr->second_addr, fdt_size); + } else { + if (hdr->second_size) + printf("fdt @ %08x (%d)\n", hdr->second_addr, hdr->second_size); + } +#endif /*CONFIG_OF_LIBFDT*/ + + char boot_addr_start[12]; + char ramdisk_addr[25]; + char fdt_addr[12]; + + char *boot_args[] = { NULL, boot_addr_start, ramdisk_addr, fdt_addr}; + if (check_image_arm64) + boot_args[0] = "booti"; + else + boot_args[0] = "bootm"; + + sprintf(boot_addr_start, "0x%lx", addr); + sprintf(ramdisk_addr, "0x%x:0x%x", hdr->ramdisk_addr, hdr->ramdisk_size); + sprintf(fdt_addr, "0x%x", hdr->second_addr); + +/* no need to pass ramdisk addr for normal boot mode when enable CONFIG_SYSTEM_RAMDISK_SUPPORT*/ +#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT + if (!is_recovery_mode) + boot_args[2] = NULL; +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS + /* Trusty keymaster needs some parameters before it work */ + if (trusty_setbootparameter(hdr, avb_result, avb_out_data)) + goto fail; + /* lock the boot status and rollback_idx preventing Linux modify it */ + trusty_lock_boot_state(); + /* put ql-tipc to release resource for Linux */ + trusty_ipc_shutdown(); +#endif + + if (avb_out_data != NULL) + avb_slot_verify_data_free(avb_out_data); + if (boot_buf != NULL) + free(boot_buf); + + if (check_image_arm64) { +#ifdef CONFIG_CMD_BOOTI + do_booti(NULL, 0, 4, boot_args); +#else + debug("please enable CONFIG_CMD_BOOTI when kernel are Image"); +#endif + } else { + do_bootm(NULL, 0, 4, boot_args); + } + + /* This only happens if image is somehow faulty so we start over */ + do_reset(NULL, 0, 0, NULL); + + return 1; + +fail: + /* avb has no recovery */ + if (avb_out_data != NULL) + avb_slot_verify_data_free(avb_out_data); + + return run_command("fastboot 0", 0); +} + +U_BOOT_CMD( + boota, 2, 1, do_boota, + "boota - boot android bootimg \n", + "boot from current mmc with avb verify\n" +); +#else /* CONFIG_AVB_SUPPORT */ +/* boota [ mmc0 | mmc1 [ ] ] */ +int do_boota(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong addr = 0; + char *ptn = "boot"; + int mmcc = -1; + struct andr_img_hdr *hdr = &boothdr; + ulong image_size; + bool check_image_arm64 = false; + int i = 0; + + for (i = 0; i < argc; i++) + printf("%s ", argv[i]); + printf("\n"); + + if (argc < 2) + return -1; + + mmcc = simple_strtoul(argv[1]+3, NULL, 10); + + if (argc > 2) + ptn = argv[2]; + + if (mmcc != -1) { +#ifdef CONFIG_MMC + struct fastboot_ptentry *pte; + struct mmc *mmc; + disk_partition_t info; + struct blk_desc *dev_desc = NULL; + unsigned bootimg_sectors; + + memset((void *)&info, 0 , sizeof(disk_partition_t)); + /* i.MX use MBR as partition table, so this will have + to find the start block and length for the + partition name and register the fastboot pte we + define the partition number of each partition in + config file + */ + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("boota: cannot find '%d' mmc device\n", mmcc); + goto fail; + } + dev_desc = blk_get_dev("mmc", mmcc); + if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { + printf("** Block device MMC %d not supported\n", mmcc); + goto fail; + } + + /* below was i.MX mmc operation code */ + if (mmc_init(mmc)) { + printf("mmc%d init failed\n", mmcc); + goto fail; + } + + pte = fastboot_flash_find_ptn(ptn); + if (!pte) { + printf("boota: cannot find '%s' partition\n", ptn); + fastboot_flash_dump_ptn(); + goto fail; + } + + if (blk_dread(dev_desc, pte->start, + 1, (void *)hdr) < 0) { + printf("boota: mmc failed to read bootimg header\n"); + goto fail; + } + + if (android_image_check_header(hdr)) { + printf("boota: bad boot image magic\n"); + goto fail; + } + + image_size = android_image_get_end(hdr) - (ulong)hdr; + bootimg_sectors = image_size/512; + + if (blk_dread(dev_desc, pte->start, + bootimg_sectors, + (void *)(hdr->kernel_addr - hdr->page_size)) < 0) { + printf("boota: mmc failed to read bootimage\n"); + goto fail; + } + check_image_arm64 = image_arm64((void *)hdr->kernel_addr); +#ifdef CONFIG_FASTBOOT_LOCK + int verifyresult = -1; +#endif + +#ifdef CONFIG_FASTBOOT_LOCK + int lock_status = fastboot_get_lock_stat(); + if (lock_status == FASTBOOT_LOCK_ERROR) { + printf("In boota get fastboot lock status error. Set lock status\n"); + fastboot_set_lock_stat(FASTBOOT_LOCK); + } + display_lock(fastboot_get_lock_stat(), verifyresult); +#endif + /* load the ramdisk file */ + memcpy((void *)hdr->ramdisk_addr, (void *)hdr->kernel_addr + + ALIGN(hdr->kernel_size, hdr->page_size), hdr->ramdisk_size); + +#ifdef CONFIG_OF_LIBFDT + u32 fdt_size = 0; + /* load the dtb file */ + if (hdr->second_addr) { + u32 zimage_size = ((u32 *)hdrload->kernel_addr)[ZIMAGE_END_ADDR] + - ((u32 *)hdrload->kernel_addr)[ZIMAGE_START_ADDR]; + fdt_size = hdrload->kernel_size - zimage_size; + memcpy((void *)(ulong)hdrload->second_addr, + (void*)(ulong)hdrload->kernel_addr + zimage_size, fdt_size); + } +#endif /*CONFIG_OF_LIBFDT*/ + +#else /*! CONFIG_MMC*/ + return -1; +#endif /*! CONFIG_MMC*/ + } else { + printf("boota: parameters is invalid. only support mmcX device\n"); + return -1; + } + + printf("kernel @ %08x (%d)\n", hdr->kernel_addr, hdr->kernel_size); + printf("ramdisk @ %08x (%d)\n", hdr->ramdisk_addr, hdr->ramdisk_size); +#ifdef CONFIG_OF_LIBFDT + if (fdt_size) + printf("fdt @ %08x (%d)\n", hdr->second_addr, fdt_size); +#endif /*CONFIG_OF_LIBFDT*/ + + + char boot_addr_start[12]; + char ramdisk_addr[25]; + char fdt_addr[12]; + char *boot_args[] = { NULL, boot_addr_start, ramdisk_addr, fdt_addr}; + if (check_image_arm64 ) { + addr = hdr->kernel_addr; + boot_args[0] = "booti"; + } else { + addr = hdr->kernel_addr - hdr->page_size; + boot_args[0] = "bootm"; + } + + sprintf(boot_addr_start, "0x%lx", addr); + sprintf(ramdisk_addr, "0x%x:0x%x", hdr->ramdisk_addr, hdr->ramdisk_size); + sprintf(fdt_addr, "0x%x", hdr->second_addr); + if (check_image_arm64) { + android_image_get_kernel(hdr, 0, NULL, NULL); +#ifdef CONFIG_CMD_BOOTI + do_booti(NULL, 0, 4, boot_args); +#else + debug("please enable CONFIG_CMD_BOOTI when kernel are Image"); +#endif + } else { + do_bootm(NULL, 0, 4, boot_args); + } + /* This only happens if image is somehow faulty so we start over */ + do_reset(NULL, 0, 0, NULL); + + return 1; + +fail: +#if defined(CONFIG_FSL_FASTBOOT) + return run_command("fastboot 0", 0); +#else /*! CONFIG_FSL_FASTBOOT*/ + return -1; +#endif /*! CONFIG_FSL_FASTBOOT*/ +} + +U_BOOT_CMD( + boota, 3, 1, do_boota, + "boota - boot android bootimg from memory\n", + "[ | mmc0 | mmc1 | mmc2 | mmcX] []\n " + "- boot application image stored in memory or mmc\n" + "\t'addr' should be the address of boot image " + "which is zImage+ramdisk.img\n" + "\t'mmcX' is the mmc device you store your boot.img, " + "which will read the boot.img from 1M offset('/boot' partition)\n" + "\t 'partition' (optional) is the partition id of your device, " + "if no partition give, will going to 'boot' partition\n" +); +#endif /* CONFIG_AVB_SUPPORT */ +#endif /* CONFIG_CMD_BOOTA */ +#endif + +void fastboot_fail(const char *reason) +{ + strncpy(fb_response_str, "FAIL\0", 5); + strncat(fb_response_str, reason, FASTBOOT_RESPONSE_LEN - 4 - 1); +} + +void fastboot_okay(const char *reason) +{ + strncpy(fb_response_str, "OKAY\0", 5); + strncat(fb_response_str, reason, FASTBOOT_RESPONSE_LEN - 4 - 1); +} + +static void fastboot_fifo_complete(struct usb_ep *ep, struct usb_request *req) +{ + int status = req->status; + usb_req *request; + + if (!status) { + if (fastboot_func->front != NULL) { + request = fastboot_func->front; + fastboot_func->front = fastboot_func->front->next; + usb_ep_free_request(ep, request->in_req); + free(request); + } else { + printf("fail free request\n"); + } + return; + } +} + +static void fastboot_complete(struct usb_ep *ep, struct usb_request *req) +{ + int status = req->status; + if (!status) + return; + printf("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual); +} + +static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) +{ + int id; + struct usb_gadget *gadget = c->cdev->gadget; + struct f_fastboot *f_fb = func_to_fastboot(f); + const char *s; + + /* DYNAMIC interface numbers assignments */ + id = usb_interface_id(c, f); + if (id < 0) + return id; + interface_desc.bInterfaceNumber = id; + + /* Enable OS and Extended Properties Feature Descriptor */ + c->cdev->use_os_string = 1; + f->os_desc_table = &fb_os_desc_table; + f->os_desc_n = 1; + f->os_desc_table->if_id = id; + INIT_LIST_HEAD(&fb_os_desc.ext_prop); + fb_ext_prop.name_len = strlen(fb_ext_prop.name) * 2 + 2; + fb_os_desc.ext_prop_len = 10 + fb_ext_prop.name_len; + fb_os_desc.ext_prop_count = 1; + fb_ext_prop.data_len = strlen(fb_ext_prop.data) * 2 + 2; + fb_os_desc.ext_prop_len += fb_ext_prop.data_len + 4; + list_add_tail(&fb_ext_prop.entry, &fb_os_desc.ext_prop); + + id = usb_string_id(c->cdev); + if (id < 0) + return id; + fastboot_string_defs[0].id = id; + interface_desc.iInterface = id; + + f_fb->in_ep = usb_ep_autoconfig(gadget, &fs_ep_in); + if (!f_fb->in_ep) + return -ENODEV; + f_fb->in_ep->driver_data = c->cdev; + + f_fb->out_ep = usb_ep_autoconfig(gadget, &fs_ep_out); + if (!f_fb->out_ep) + return -ENODEV; + f_fb->out_ep->driver_data = c->cdev; + + f->descriptors = fb_fs_function; + + if (gadget_is_dualspeed(gadget)) { + /* Assume endpoint addresses are the same for both speeds */ + hs_ep_in.bEndpointAddress = fs_ep_in.bEndpointAddress; + hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress; + /* copy HS descriptors */ + f->hs_descriptors = fb_hs_function; + } + + if (gadget_is_superspeed(gadget)) { + ss_ep_in.bEndpointAddress = fs_ep_in.bEndpointAddress; + ss_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress; + f->ss_descriptors = fb_ss_function; + } + + s = env_get("serial#"); + if (s) + g_dnl_set_serialnumber((char *)s); + + return 0; +} + +static void fastboot_unbind(struct usb_configuration *c, struct usb_function *f) +{ + f->os_desc_table = NULL; + list_del(&fb_os_desc.ext_prop); + memset(fastboot_func, 0, sizeof(*fastboot_func)); +} + +static void fastboot_disable(struct usb_function *f) +{ + usb_req *req; + struct f_fastboot *f_fb = func_to_fastboot(f); + + usb_ep_disable(f_fb->out_ep); + usb_ep_disable(f_fb->in_ep); + + if (f_fb->out_req) { + free(f_fb->out_req->buf); + usb_ep_free_request(f_fb->out_ep, f_fb->out_req); + f_fb->out_req = NULL; + } + if (f_fb->in_req) { + free(f_fb->in_req->buf); + usb_ep_free_request(f_fb->in_ep, f_fb->in_req); + + /* disable usb request FIFO */ + while(f_fb->front != NULL) { + req = f_fb->front; + f_fb->front = f_fb->front->next; + free(req->in_req->buf); + usb_ep_free_request(f_fb->in_ep, req->in_req); + free(req); + } + + f_fb->rear = NULL; + f_fb->in_req = NULL; + } +} + +static struct usb_request *fastboot_start_ep(struct usb_ep *ep) +{ + struct usb_request *req; + + req = usb_ep_alloc_request(ep, 0); + if (!req) + return NULL; + + req->length = EP_BUFFER_SIZE; + req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, EP_BUFFER_SIZE); + if (!req->buf) { + usb_ep_free_request(ep, req); + return NULL; + } + + memset(req->buf, 0, req->length); + return req; +} + +static int fastboot_set_alt(struct usb_function *f, + unsigned interface, unsigned alt) +{ + int ret; + struct usb_composite_dev *cdev = f->config->cdev; + struct usb_gadget *gadget = cdev->gadget; + struct f_fastboot *f_fb = func_to_fastboot(f); + const struct usb_endpoint_descriptor *d; + + debug("%s: func: %s intf: %d alt: %d\n", + __func__, f->name, interface, alt); + + d = fb_ep_desc(gadget, &fs_ep_out, &hs_ep_out, &ss_ep_out); + ret = usb_ep_enable(f_fb->out_ep, d); + if (ret) { + puts("failed to enable out ep\n"); + return ret; + } + + f_fb->out_req = fastboot_start_ep(f_fb->out_ep); + if (!f_fb->out_req) { + puts("failed to alloc out req\n"); + ret = -EINVAL; + goto err; + } + f_fb->out_req->complete = rx_handler_command; + + d = fb_ep_desc(gadget, &fs_ep_in, &hs_ep_in, &ss_ep_in); + ret = usb_ep_enable(f_fb->in_ep, d); + if (ret) { + puts("failed to enable in ep\n"); + goto err; + } + + f_fb->in_req = fastboot_start_ep(f_fb->in_ep); + if (!f_fb->in_req) { + puts("failed alloc req in\n"); + ret = -EINVAL; + goto err; + } +#ifdef CONFIG_ANDROID_THINGS_SUPPORT + /* + * fastboot host end implement to get data in one bulk package so need + * large buffer for the "fastboot upload" and "fastboot get_staged". + */ + if (f_fb->in_req->buf) + free(f_fb->in_req->buf); + f_fb->in_req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, EP_BUFFER_SIZE * 32); +#endif + f_fb->in_req->complete = fastboot_complete; + + f_fb->front = f_fb->rear = NULL; + + ret = usb_ep_queue(f_fb->out_ep, f_fb->out_req, 0); + if (ret) + goto err; + + return 0; +err: + fastboot_disable(f); + return ret; +} + +static int fastboot_add(struct usb_configuration *c) +{ + struct f_fastboot *f_fb = fastboot_func; + int status; + + debug("%s: cdev: 0x%p\n", __func__, c->cdev); + + if (!f_fb) { + f_fb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_fb)); + if (!f_fb) + return -ENOMEM; + + fastboot_func = f_fb; + memset(f_fb, 0, sizeof(*f_fb)); + } + + f_fb->usb_function.name = "f_fastboot"; + f_fb->usb_function.bind = fastboot_bind; + f_fb->usb_function.unbind = fastboot_unbind; + f_fb->usb_function.set_alt = fastboot_set_alt; + f_fb->usb_function.disable = fastboot_disable; + f_fb->usb_function.strings = fastboot_strings; + + status = usb_add_function(c, &f_fb->usb_function); + if (status) { + free(f_fb); + fastboot_func = NULL; + } + + return status; +} +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_fastboot, fastboot_add); + +static int fastboot_tx_write_more(const char *buffer) +{ + int ret = 0; + + /* alloc usb request FIFO node */ + usb_req *req = (usb_req *)malloc(sizeof(usb_req)); + if (!req) { + printf("failed alloc usb req!\n"); + return -ENOMEM; + } + + /* usb request node FIFO enquene */ + if ((fastboot_func->front == NULL) && (fastboot_func->rear == NULL)) { + fastboot_func->front = fastboot_func->rear = req; + req->next = NULL; + } else { + fastboot_func->rear->next = req; + fastboot_func->rear = req; + req->next = NULL; + } + + /* alloc in request for current node */ + req->in_req = fastboot_start_ep(fastboot_func->in_ep); + if (!req->in_req) { + printf("failed alloc req in\n"); + fastboot_disable(&(fastboot_func->usb_function)); + return -EINVAL; + } + req->in_req->complete = fastboot_fifo_complete; + + memcpy(req->in_req->buf, buffer, strlen(buffer)); + req->in_req->length = strlen(buffer); + + ret = usb_ep_queue(fastboot_func->in_ep, req->in_req, 0); + if (ret) { + printf("Error %d on queue\n", ret); + return -EINVAL; + } + + ret = 0; + return ret; +} + +static int fastboot_tx_write(const char *buffer, unsigned int buffer_size) +{ + struct usb_request *in_req = fastboot_func->in_req; + int ret; + + memcpy(in_req->buf, buffer, buffer_size); + in_req->length = buffer_size; + + usb_ep_dequeue(fastboot_func->in_ep, in_req); + + ret = usb_ep_queue(fastboot_func->in_ep, in_req, 0); + if (ret) + printf("Error %d on queue\n", ret); + return 0; +} + +static int fastboot_tx_write_str(const char *buffer) +{ + return fastboot_tx_write(buffer, strlen(buffer)); +} + +static void compl_do_reset(struct usb_ep *ep, struct usb_request *req) +{ + do_reset(NULL, 0, 0, NULL); +} + +int __weak fb_set_reboot_flag(void) +{ + return -ENOSYS; +} + +static void cb_reboot(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + if (!strcmp_l1("reboot-bootloader", cmd)) { + if (fb_set_reboot_flag()) { + fastboot_tx_write_str("FAILCannot set reboot flag"); + return; + } + } + fastboot_func->in_req->complete = compl_do_reset; + fastboot_tx_write_str("OKAY"); +} + +static int strcmp_l1(const char *s1, const char *s2) +{ + if (!s1 || !s2) + return -1; + return strncmp(s1, s2, strlen(s1)); +} + +#ifdef CONFIG_FSL_FASTBOOT +static bool is_slotvar(char *cmd) +{ + assert(cmd != NULL); + if (!strcmp_l1("has-slot:", cmd) || + !strcmp_l1("slot-successful:", cmd) || + !strcmp_l1("slot-count", cmd) || + !strcmp_l1("slot-suffixes", cmd) || + !strcmp_l1("current-slot", cmd) || + !strcmp_l1("slot-unbootable:", cmd) || + !strcmp_l1("slot-retry-count:", cmd)) + return true; + return false; +} + +static char *get_serial(void) +{ +#ifdef CONFIG_SERIAL_TAG + struct tag_serialnr serialnr; + static char serial[32]; + get_board_serial(&serialnr); + sprintf(serial, "%08x%08x", serialnr.high, serialnr.low); + return serial; +#else + return NULL; +#endif +} + +#if !defined(PRODUCT_NAME) +#define PRODUCT_NAME "NXP i.MX" +#endif + +#if !defined(VARIANT_NAME) +#define VARIANT_NAME "NXP i.MX" +#endif + +static int get_block_size(void) { + int dev_no = 0; + struct blk_desc *dev_desc; + + dev_no = fastboot_devinfo.dev_id; + dev_desc = blk_get_dev(fastboot_devinfo.type == DEV_SATA ? "sata" : "mmc", dev_no); + if (NULL == dev_desc) { + printf("** Block device %s %d not supported\n", + fastboot_devinfo.type == DEV_SATA ? "sata" : "mmc", + dev_no); + return 0; + } + return dev_desc->blksz; +} + +static bool is_exist(char (*partition_base_name)[16], char *buffer, int count) +{ + int n; + + for (n = 0; n < count; n++) { + if (!strcmp(partition_base_name[n],buffer)) + return true; + } + return false; +} +/*get partition base name from gpt without "_a/_b"*/ +static int get_partition_base_name(char (*partition_base_name)[16]) +{ + int n = 0; + int count = 0; + char *ptr1, *ptr2; + char buffer[20]; + + for (n = 0; n < g_pcount; n++) { + strcpy(buffer,g_ptable[n].name); + ptr1 = strstr(buffer, "_a"); + ptr2 = strstr(buffer, "_b"); + if (ptr1 != NULL) { + *ptr1 = '\0'; + if (!is_exist(partition_base_name,buffer,count)) { + strcpy(partition_base_name[count++],buffer); + } + } else if (ptr2 != NULL) { + *ptr2 = '\0'; + if (!is_exist(partition_base_name,buffer,count)) { + strcpy(partition_base_name[count++],buffer); + } + } else { + strcpy(partition_base_name[count++],buffer); + } + } + return count; +} + +static bool is_slot(void) +{ + char slot_suffix[2][5] = {"_a","_b"}; + int n; + + for (n = 0; n < g_pcount; n++) { + if (strstr(g_ptable[n].name, slot_suffix[0]) || + strstr(g_ptable[n].name, slot_suffix[1])) + return true; + } + return false; +} +#ifdef CONFIG_IMX_TRUSTY_OS +static void uuid_hex2string(uint8_t *uuid, char* buf, uint32_t uuid_len, uint32_t uuid_strlen) { + uint32_t i; + if (!uuid || !buf) + return; + char *cp = buf; + char *buf_end = buf + uuid_strlen; + for (i = 0; i < uuid_len; i++) { + cp += snprintf(cp, buf_end - cp, "%02x", uuid[i]); + } +} +#endif + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) +int get_imx8m_baseboard_id(void); +#endif + +static int get_single_var(char *cmd, char *response) +{ + char *str = cmd; + int chars_left; + const char *s; + struct mmc *mmc; + int mmc_dev_no; + int blksz; + + chars_left = FASTBOOT_RESPONSE_LEN - strlen(response) - 1; + + if ((str = strstr(cmd, "partition-size:"))) { + str +=strlen("partition-size:"); + struct fastboot_ptentry* fb_part; + fb_part = fastboot_flash_find_ptn(str); + if (!fb_part) { + strncat(response, "Wrong partition name.", chars_left); + fastboot_flash_dump_ptn(); + return -1; + } else { + snprintf(response + strlen(response), chars_left, + "0x%llx", + (uint64_t)fb_part->length * get_block_size()); + } + } else if ((str = strstr(cmd, "partition-type:"))) { + str +=strlen("partition-type:"); + struct fastboot_ptentry* fb_part; + fb_part = fastboot_flash_find_ptn(str); + if (!fb_part) { + strncat(response, "Wrong partition name.", chars_left); + fastboot_flash_dump_ptn(); + return -1; + } else { + strncat(response, fb_part->fstype, chars_left); + } + } else if (!strcmp_l1("version-baseband", cmd)) { + strncat(response, "N/A", chars_left); + } else if (!strcmp_l1("version-bootloader", cmd) || + !strcmp_l1("bootloader-version", cmd)) { + strncat(response, U_BOOT_VERSION, chars_left); + } else if (!strcmp_l1("version", cmd)) { + strncat(response, FASTBOOT_VERSION, chars_left); + } else if (!strcmp_l1("battery-voltage", cmd)) { + strncat(response, "0mV", chars_left); + } else if (!strcmp_l1("battery-soc-ok", cmd)) { + strncat(response, "yes", chars_left); + } else if (!strcmp_l1("variant", cmd)) { + strncat(response, VARIANT_NAME, chars_left); + } else if (!strcmp_l1("off-mode-charge", cmd)) { + strncat(response, "1", chars_left); + } else if (!strcmp_l1("downloadsize", cmd) || + !strcmp_l1("max-download-size", cmd)) { + + snprintf(response + strlen(response), chars_left, "0x%x", CONFIG_FASTBOOT_BUF_SIZE); + } else if (!strcmp_l1("erase-block-size", cmd)) { + mmc_dev_no = mmc_get_env_dev(); + mmc = find_mmc_device(mmc_dev_no); + blksz = get_block_size(); + snprintf(response + strlen(response), chars_left, "0x%x", + (blksz * mmc->erase_grp_size)); + } else if (!strcmp_l1("logical-block-size", cmd)) { + blksz = get_block_size(); + snprintf(response + strlen(response), chars_left, "0x%x", blksz); + } else if (!strcmp_l1("serialno", cmd)) { + s = get_serial(); + if (s) + strncat(response, s, chars_left); + else { + strncat(response, "FAILValue not set", chars_left); + return -1; + } + } else if (!strcmp_l1("product", cmd)) { + strncat(response, PRODUCT_NAME, chars_left); + } +#ifdef CONFIG_IMX_TRUSTY_OS + else if(!strcmp_l1("at-attest-uuid", cmd)) { + char *uuid; + char uuid_str[ATAP_UUID_STR_SIZE]; + if (trusty_atap_read_uuid_str(&uuid)) { + printf("ERROR read uuid failed!\n"); + strncat(response, "FAILCannot get uuid!", chars_left); + return -1; + } else { + uuid_hex2string((uint8_t*)uuid, uuid_str,ATAP_UUID_SIZE, ATAP_UUID_STR_SIZE); + strncat(response, uuid_str, chars_left); + trusty_free(uuid); + } + } + else if(!strcmp_l1("at-attest-dh", cmd)) { + strncat(response, "1:P256,2:curve25519", chars_left); + } +#endif +#ifdef CONFIG_FASTBOOT_LOCK + else if (!strcmp_l1("secure", cmd)) { + strncat(response, FASTBOOT_VAR_YES, chars_left); + } else if (!strcmp_l1("unlocked",cmd)){ + int status = fastboot_get_lock_stat(); + if (status == FASTBOOT_UNLOCK) { + strncat(response, FASTBOOT_VAR_YES, chars_left); + } else { + strncat(response, FASTBOOT_VAR_NO, chars_left); + } + } +#else + else if (!strcmp_l1("secure", cmd)) { + strncat(response, FASTBOOT_VAR_NO, chars_left); + } else if (!strcmp_l1("unlocked",cmd)) { + strncat(response, FASTBOOT_VAR_NO, chars_left); + } +#endif + else if (is_slotvar(cmd)) { +#ifdef CONFIG_AVB_SUPPORT + if (get_slotvar_avb(&fsl_avb_ab_ops, cmd, + response + strlen(response), chars_left + 1) < 0) + return -1; +#else + strncat(response, FASTBOOT_VAR_NO, chars_left); +#endif + } +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) + else if (!strcmp_l1("baseboard_id", cmd)) { + int baseboard_id; + + baseboard_id = get_imx8m_baseboard_id(); + if (baseboard_id < 0) { + printf("Get baseboard id failed!\n"); + strncat(response, "Get baseboard id failed!", chars_left); + return -1; + } else + snprintf(response + strlen(response), chars_left, "0x%x", baseboard_id); + } +#endif +#ifdef CONFIG_AVB_ATX + else if (!strcmp_l1("bootloader-locked", cmd)) { + + /* Below is basically copied from is_hab_enabled() */ + struct imx_sec_config_fuse_t *fuse = + (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse; + uint32_t reg; + int ret; + + /* Read the secure boot status from fuse. */ + ret = fuse_read(fuse->bank, fuse->word, ®); + if (ret) { + printf("\nSecure boot fuse read error!\n"); + strncat(response, "Secure boot fuse read error!", chars_left); + return -1; + } + /* Check if the secure boot bit is enabled */ + if ((reg & 0x2000000) == 0x2000000) + strncat(response, "1", chars_left); + else + strncat(response, "0", chars_left); + } else if (!strcmp_l1("bootloader-min-versions", cmd)) { +#ifndef CONFIG_ARM64 + /* We don't support bootloader rbindex protection for + * ARM32(like imx7d) and the format is: "bootloader,tee". */ + strncat(response, "-1,-1", chars_left); + +#elif defined(CONFIG_DUAL_BOOTLOADER) + /* Rbindex protection for bootloader is supported only when the + * 'dual bootloader' feature is enabled. U-boot will get the rbindx + * from RAM which is passed by spl because we can only get the rbindex + * at spl stage. The format in this case is: "spl,atf,tee,u-boot". + */ + struct bl_rbindex_package *bl_rbindex; + uint32_t rbindex; + + bl_rbindex = (struct bl_rbindex_package *)BL_RBINDEX_LOAD_ADDR; + if (!strncmp(bl_rbindex->magic, BL_RBINDEX_MAGIC, + BL_RBINDEX_MAGIC_LEN)) { + rbindex = bl_rbindex->rbindex; + snprintf(response + strlen(response), chars_left, + "-1,%d,%d,%d",rbindex, rbindex, rbindex); + } else { + printf("Error bootloader rbindex magic!\n"); + strncat(response, "Get bootloader rbindex fail!", chars_left); + return -1; + } +#else + /* Return -1 for all partition if 'dual bootloader' feature + * is not enabled */ + strncat(response, "-1,-1,-1,-1", chars_left); +#endif + } else if (!strcmp_l1("avb-perm-attr-set", cmd)) { + if (perm_attr_are_fused()) + strncat(response, "1", chars_left); + else + strncat(response, "0", chars_left); + } else if (!strcmp_l1("avb-locked", cmd)) { + FbLockState status; + + status = fastboot_get_lock_stat(); + if (status == FASTBOOT_LOCK) + strncat(response, "1", chars_left); + else if (status == FASTBOOT_UNLOCK) + strncat(response, "0", chars_left); + else { + printf("Get lock state error!\n"); + strncat(response, "Get lock state failed!", chars_left); + return -1; + } + } else if (!strcmp_l1("avb-unlock-disabled", cmd)) { + if (at_unlock_vboot_is_disabled()) + strncat(response, "1", chars_left); + else + strncat(response, "0", chars_left); + } else if (!strcmp_l1("avb-min-versions", cmd)) { + int i = 0; + /* rbindex location/value can be very large + * number so we reserve enough space here. + */ + char buffer[35]; + uint32_t rbindex_location[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 2]; + uint32_t location; + uint64_t rbindex; + + memset(buffer, '\0', sizeof(buffer)); + + /* Set rbindex locations. */ + for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) + rbindex_location[i] = i; + + /* Set Android Things key version rbindex locations */ + rbindex_location[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS] + = AVB_ATX_PIK_VERSION_LOCATION; + rbindex_location[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 1] + = AVB_ATX_PSK_VERSION_LOCATION; + + /* Read rollback index and set the reponse*/ + for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 2; i++) { + location = rbindex_location[i]; + if (fsl_avb_ops.read_rollback_index(&fsl_avb_ops, + location, &rbindex) + != AVB_IO_RESULT_OK) { + printf("Read rollback index error!\n"); + snprintf(response, sizeof(response), + "INFOread rollback index error when get avb-min-versions"); + return -1; + } + /* Generate the "location:value" pair */ + snprintf(buffer, sizeof(buffer), "%d:%lld", location, rbindex); + if (i != AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 1) + strncat(buffer, ",", strlen(",")); + + if ((chars_left - (int)strlen(buffer)) >= 0) { + strncat(response, buffer, strlen(buffer)); + chars_left -= strlen(buffer); + } else { + strncat(response, buffer, chars_left); + /* reponse buffer is full, send it first */ + fastboot_tx_write_more(response); + /* reset the reponse buffer for next round */ + memset(response, '\0', sizeof(response)); + strncpy(response, "INFO", 5); + /* Copy left strings from 'buffer' to 'response' */ + strncat(response, buffer + chars_left, strlen(buffer)); + chars_left = FASTBOOT_RESPONSE_LEN - + strlen(response) - 1; + } + } + + } +#endif + else { + char envstr[32]; + + snprintf(envstr, sizeof(envstr) - 1, "fastboot.%s", cmd); + s = env_get(envstr); + if (s) { + strncat(response, s, chars_left); + } else { + snprintf(response, chars_left, "FAILunknown variable:%s",cmd); + printf("WARNING: unknown variable: %s\n", cmd); + return -1; + } + } + return 0; +} + +static void cb_getvar(struct usb_ep *ep, struct usb_request *req) +{ + int n = 0; + int status = 0; + int count = 0; + char *cmd = req->buf; + char var_name[FASTBOOT_RESPONSE_LEN]; + char partition_base_name[MAX_PTN][16]; + char slot_suffix[2][5] = {"a","b"}; + char response[FASTBOOT_RESPONSE_LEN]; + + strsep(&cmd, ":"); + if (!cmd) { + pr_err("missing variable"); + fastboot_tx_write_str("FAILmissing var"); + return; + } + + if (!strcmp_l1("all", cmd)) { + + memset(response, '\0', FASTBOOT_RESPONSE_LEN); + + + /* get common variables */ + for (n = 0; n < FASTBOOT_COMMON_VAR_NUM; n++) { + snprintf(response, sizeof(response), "INFO%s:", fastboot_common_var[n]); + get_single_var(fastboot_common_var[n], response); + fastboot_tx_write_more(response); + } + + /* get at-vboot-state variables */ +#ifdef CONFIG_AVB_ATX + for (n = 0; n < AT_VBOOT_STATE_VAR_NUM; n++) { + snprintf(response, sizeof(response), "INFO%s:", fastboot_at_vboot_state_var[n]); + get_single_var(fastboot_at_vboot_state_var[n], response); + fastboot_tx_write_more(response); + } +#endif + /* get partition type */ + for (n = 0; n < g_pcount; n++) { + snprintf(response, sizeof(response), "INFOpartition-type:%s:", g_ptable[n].name); + snprintf(var_name, sizeof(var_name), "partition-type:%s", g_ptable[n].name); + get_single_var(var_name, response); + fastboot_tx_write_more(response); + } + /* get partition size */ + for (n = 0; n < g_pcount; n++) { + snprintf(response, sizeof(response), "INFOpartition-size:%s:", g_ptable[n].name); + snprintf(var_name, sizeof(var_name), "partition-size:%s", g_ptable[n].name); + get_single_var(var_name,response); + fastboot_tx_write_more(response); + } + /* slot related variables */ + if (is_slot()) { + /* get has-slot variables */ + count = get_partition_base_name(partition_base_name); + for (n = 0; n < count; n++) { + snprintf(response, sizeof(response), "INFOhas-slot:%s:", partition_base_name[n]); + snprintf(var_name, sizeof(var_name), "has-slot:%s", partition_base_name[n]); + get_single_var(var_name,response); + fastboot_tx_write_more(response); + } + /* get current slot */ + strncpy(response, "INFOcurrent-slot:", sizeof(response)); + get_single_var("current-slot", response); + fastboot_tx_write_more(response); + /* get slot count */ + strncpy(response, "INFOslot-count:", sizeof(response)); + get_single_var("slot-count", response); + fastboot_tx_write_more(response); + /* get slot-successful variable */ + for (n = 0; n < 2; n++) { + snprintf(response, sizeof(response), "INFOslot-successful:%s:", slot_suffix[n]); + snprintf(var_name, sizeof(var_name), "slot-successful:%s", slot_suffix[n]); + get_single_var(var_name, response); + fastboot_tx_write_more(response); + } + /*get slot-unbootable variable*/ + for (n = 0; n < 2; n++) { + snprintf(response, sizeof(response), "INFOslot-unbootable:%s:", slot_suffix[n]); + snprintf(var_name, sizeof(var_name), "slot-unbootable:%s", slot_suffix[n]); + get_single_var(var_name, response); + fastboot_tx_write_more(response); + } + /*get slot-retry-count variable*/ + for (n = 0; n < 2; n++) { + snprintf(response, sizeof(response), "INFOslot-retry-count:%s:", slot_suffix[n]); + snprintf(var_name, sizeof(var_name), "slot-retry-count:%s", slot_suffix[n]); + get_single_var(var_name, response); + fastboot_tx_write_more(response); + } + } + + strncpy(response, "OKAYDone!", 10); + fastboot_tx_write_more(response); + + return; + } +#ifdef CONFIG_AVB_ATX + else if (!strcmp_l1("at-vboot-state", cmd)) { + /* get at-vboot-state variables */ + for (n = 0; n < AT_VBOOT_STATE_VAR_NUM; n++) { + snprintf(response, sizeof(response), "INFO%s:", fastboot_at_vboot_state_var[n]); + get_single_var(fastboot_at_vboot_state_var[n], response); + fastboot_tx_write_more(response); + } + + strncpy(response, "OKAY", 5); + fastboot_tx_write_more(response); + + return; + } else if ((!strcmp_l1("bootloader-locked", cmd)) || + (!strcmp_l1("bootloader-min-versions", cmd)) || + (!strcmp_l1("avb-perm-attr-set", cmd)) || + (!strcmp_l1("avb-locked", cmd)) || + (!strcmp_l1("avb-unlock-disabled", cmd)) || + (!strcmp_l1("avb-min-versions", cmd))) { + + printf("Can't get this variable alone, get 'at-vboot-state' instead!\n"); + snprintf(response, sizeof(response), + "FAILCan't get this variable alone, get 'at-vboot-state' instead."); + fastboot_tx_write_str(response); + return; + } +#endif + else { + + strncpy(response, "OKAY", 5); + status = get_single_var(cmd, response); + if (status != 0) { + strncpy(response, "FAIL", 5); + } + fastboot_tx_write_str(response); + return; + } +} + +#ifdef CONFIG_FASTBOOT_LOCK + +int do_lock_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + FbLockState status = fastboot_get_lock_stat(); + if (status != FASTBOOT_LOCK_ERROR) { + if (status == FASTBOOT_LOCK) + printf("fastboot lock status: locked.\n"); + else + printf("fastboot lock status: unlocked.\n"); + } else + printf("fastboot lock status error!\n"); + + display_lock(status, -1); + + return 0; + +} + +U_BOOT_CMD( + lock_status, 2, 1, do_lock_status, + "lock_status", + "lock_status"); + +static void wipe_all_userdata(void) +{ + char response[FASTBOOT_RESPONSE_LEN]; + + /* Erase all user data */ + printf("Start userdata wipe process....\n"); + /* Erase /data partition */ + fastboot_wipe_data_partition(); + +#if defined (CONFIG_ANDROID_SUPPORT) || defined (CONFIG_ANDROID_AUTO_SUPPORT) + /* Erase the misc partition. */ + process_erase_mmc(FASTBOOT_PARTITION_MISC, response); +#endif + +#ifndef CONFIG_ANDROID_AB_SUPPORT + /* Erase the cache partition for legacy imx6/7 */ + process_erase_mmc(FASTBOOT_PARTITION_CACHE, response); +#endif + /* The unlock permissive flag is set by user and should be wiped here. */ + set_fastboot_lock_disable(); + + +#if defined(AVB_RPMB) && !defined(CONFIG_IMX_TRUSTY_OS) + printf("Start stored_rollback_index wipe process....\n"); + rbkidx_erase(); + printf("Wipe stored_rollback_index completed.\n"); +#endif + printf("Wipe userdata completed.\n"); +} + +static FbLockState do_fastboot_unlock(bool force) +{ + int status; + + if (fastboot_get_lock_stat() == FASTBOOT_UNLOCK) { + printf("The device is already unlocked\n"); + return FASTBOOT_UNLOCK; + } + if ((fastboot_lock_enable() == FASTBOOT_UL_ENABLE) || force) { + printf("It is able to unlock device. %d\n",fastboot_lock_enable()); + status = fastboot_set_lock_stat(FASTBOOT_UNLOCK); + if (status < 0) + return FASTBOOT_LOCK_ERROR; + + wipe_all_userdata(); + + } else { + printf("It is not able to unlock device."); + return FASTBOOT_LOCK_ERROR; + } + + return FASTBOOT_UNLOCK; +} + +static FbLockState do_fastboot_lock(void) +{ + int status; + + if (fastboot_get_lock_stat() == FASTBOOT_LOCK) { + printf("The device is already locked\n"); + return FASTBOOT_LOCK; + } + status = fastboot_set_lock_stat(FASTBOOT_LOCK); + if (status < 0) + return FASTBOOT_LOCK_ERROR; + + wipe_all_userdata(); + + return FASTBOOT_LOCK; +} + +static bool endswith(char* s, char* subs) { + if (!s || !subs) + return false; + uint32_t len = strlen(s); + uint32_t sublen = strlen(subs); + if (len < sublen) { + return false; + } + if (strncmp(s + len - sublen, subs, sublen)) { + return false; + } + return true; +} + +static void cb_flashing(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[FASTBOOT_RESPONSE_LEN]; + FbLockState status; + FbLockEnableResult result; + if (endswith(cmd, "lock_critical")) { + strcpy(response, "OKAY"); + } +#ifdef CONFIG_AVB_ATX + else if (endswith(cmd, FASTBOOT_AVB_AT_PERM_ATTR)) { + if (avb_atx_fuse_perm_attr(interface.transfer_buffer, download_bytes)) + strcpy(response, "FAILInternal error!"); + else + strcpy(response, "OKAY"); + } else if (endswith(cmd, FASTBOOT_AT_GET_UNLOCK_CHALLENGE)) { + if (avb_atx_get_unlock_challenge(fsl_avb_ops.atx_ops, + interface.transfer_buffer, &download_bytes)) + strcpy(response, "FAILInternal error!"); + else + strcpy(response, "OKAY"); + } else if (endswith(cmd, FASTBOOT_AT_UNLOCK_VBOOT)) { + if (at_unlock_vboot_is_disabled()) { + printf("unlock vboot already disabled, can't unlock the device!\n"); + strcpy(response, "FAILunlock vboot already disabled!."); + } else { +#ifdef CONFIG_AT_AUTHENTICATE_UNLOCK + if (avb_atx_verify_unlock_credential(fsl_avb_ops.atx_ops, + interface.transfer_buffer)) + strcpy(response, "FAILIncorrect unlock credential!"); + else { +#endif + status = do_fastboot_unlock(true); + if (status != FASTBOOT_LOCK_ERROR) + strcpy(response, "OKAY"); + else + strcpy(response, "FAILunlock device failed."); +#ifdef CONFIG_AT_AUTHENTICATE_UNLOCK + } +#endif + } + } else if (endswith(cmd, FASTBOOT_AT_LOCK_VBOOT)) { + if (perm_attr_are_fused()) { + status = do_fastboot_lock(); + if (status != FASTBOOT_LOCK_ERROR) + strcpy(response, "OKAY"); + else + strcpy(response, "FAILlock device failed."); + } else + strcpy(response, "FAILpermanent attributes not fused!"); + } else if (endswith(cmd, FASTBOOT_AT_DISABLE_UNLOCK_VBOOT)) { + /* This command can only be called after 'oem at-lock-vboot' */ + status = fastboot_get_lock_stat(); + if (status == FASTBOOT_LOCK) { + if (at_unlock_vboot_is_disabled()) { + printf("unlock vboot already disabled!\n"); + strcpy(response, "OKAY"); + } + else { + if (!at_disable_vboot_unlock()) + strcpy(response, "OKAY"); + else + strcpy(response, "FAILdisable unlock vboot fail!"); + } + } else + strcpy(response, "FAILplease lock the device first!"); + } +#endif /* CONFIG_AVB_ATX */ +#ifdef CONFIG_ANDROID_THINGS_SUPPORT + else if (endswith(cmd, FASTBOOT_BOOTLOADER_VBOOT_KEY)) { + strcpy(response, "OKAY"); + } +#endif /* CONFIG_ANDROID_THINGS_SUPPORT */ +#ifdef CONFIG_IMX_TRUSTY_OS + else if (endswith(cmd, FASTBOOT_GET_CA_REQ)) { + uint8_t *ca_output; + uint32_t ca_length, cp_length; + if (trusty_atap_get_ca_request(interface.transfer_buffer, download_bytes, + &(ca_output), &ca_length)) { + printf("ERROR get_ca_request failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + cp_length = min((uint32_t)CONFIG_FASTBOOT_BUF_SIZE, ca_length); + memcpy(interface.transfer_buffer, ca_output, cp_length); + download_bytes = ca_length; + strcpy(response, "OKAY"); + } + + } else if (endswith(cmd, FASTBOOT_SET_CA_RESP)) { + if (trusty_atap_set_ca_response(interface.transfer_buffer,download_bytes)) { + printf("ERROR set_ca_response failed!\n"); + strcpy(response, "FAILInternal error!"); + } else + strcpy(response, "OKAY"); + } else if (endswith(cmd, FASTBOOT_SET_RSA_ATTESTATION_KEY)) { + if (trusty_set_attestation_key(interface.transfer_buffer, + download_bytes, + KM_ALGORITHM_RSA)) { + printf("ERROR set rsa attestation key failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Set rsa attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_SET_EC_ATTESTATION_KEY)) { + if (trusty_set_attestation_key(interface.transfer_buffer, + download_bytes, + KM_ALGORITHM_EC)) { + printf("ERROR set ec attestation key failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Set ec attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_APPEND_RSA_ATTESTATION_CERT)) { + if (trusty_append_attestation_cert_chain(interface.transfer_buffer, + download_bytes, + KM_ALGORITHM_RSA)) { + printf("ERROR append rsa attestation cert chain failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Append rsa attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_APPEND_EC_ATTESTATION_CERT)) { + if (trusty_append_attestation_cert_chain(interface.transfer_buffer, + download_bytes, + KM_ALGORITHM_EC)) { + printf("ERROR append ec attestation cert chain failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Append ec attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } +#ifndef CONFIG_AVB_ATX + else if (endswith(cmd, FASTBOOT_SET_RPMB_KEY)) { + if (fastboot_set_rpmb_key(interface.transfer_buffer, download_bytes)) { + printf("ERROR set rpmb key failed!\n"); + strcpy(response, "FAILset rpmb key failed!"); + } else + strcpy(response, "OKAY"); + } else if (endswith(cmd, FASTBOOT_SET_RPMB_RANDOM_KEY)) { + if (fastboot_set_rpmb_random_key()) { + printf("ERROR set rpmb random key failed!\n"); + strcpy(response, "FAILset rpmb random key failed!"); + } else + strcpy(response, "OKAY"); + } else if (endswith(cmd, FASTBOOT_SET_VBMETA_PUBLIC_KEY)) { + if (avb_set_public_key(interface.transfer_buffer, + download_bytes)) + strcpy(response, "FAILcan't set public key!"); + else + strcpy(response, "OKAY"); + } +#endif /* !CONFIG_AVB_ATX */ +#endif /* CONFIG_IMX_TRUSTY_OS */ + else if (endswith(cmd, "unlock_critical")) { + strcpy(response, "OKAY"); + } else if (endswith(cmd, "unlock")) { + printf("flashing unlock.\n"); +#ifdef CONFIG_AVB_ATX + /* We should do nothing here For Android Things which + * enables the authenticated unlock feature. + */ + strcpy(response, "OKAY"); +#else + status = do_fastboot_unlock(false); + if (status != FASTBOOT_LOCK_ERROR) + strcpy(response, "OKAY"); + else + strcpy(response, "FAILunlock device failed."); +#endif + } else if (endswith(cmd, "lock")) { +#ifdef CONFIG_AVB_ATX + /* We should do nothing here For Android Things which + * enables the at-lock-vboot feature. + */ + strcpy(response, "OKAY"); +#else + printf("flashing lock.\n"); + status = do_fastboot_lock(); + if (status != FASTBOOT_LOCK_ERROR) + strcpy(response, "OKAY"); + else + strcpy(response, "FAILlock device failed."); +#endif + } else if (endswith(cmd, "get_unlock_ability")) { + result = fastboot_lock_enable(); + if (result == FASTBOOT_UL_ENABLE) { + fastboot_tx_write_more("INFO1"); + strcpy(response, "OKAY"); + } else if (result == FASTBOOT_UL_DISABLE) { + fastboot_tx_write_more("INFO0"); + strcpy(response, "OKAY"); + } else { + printf("flashing get_unlock_ability fail!\n"); + strcpy(response, "FAILget unlock ability failed."); + } + } else { + printf("Unknown flashing command:%s\n", cmd); + strcpy(response, "FAILcommand not defined"); + } + fastboot_tx_write_more(response); +} + +#endif /* CONFIG_FASTBOOT_LOCK */ + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_FASTBOOT_LOCK +static int partition_table_valid(void) +{ + int status, mmc_no; + struct blk_desc *dev_desc; +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_ARM64) + //Prevent other partition accessing when no TOS flashed. + if (!tos_flashed) + return 0; +#endif + disk_partition_t info; + mmc_no = fastboot_devinfo.dev_id; + dev_desc = blk_get_dev("mmc", mmc_no); + if (dev_desc) + status = part_get_info(dev_desc, 1, &info); + else + status = -1; + return (status == 0); +} +#endif +#endif /* CONFIG_FASTBOOT_LOCK */ + +#ifdef CONFIG_FASTBOOT_FLASH +static void cb_flash(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[FASTBOOT_RESPONSE_LEN]; + + strsep(&cmd, ":"); + if (!cmd) { + pr_err("missing partition name"); + fastboot_tx_write_str("FAILmissing partition name"); + return; + } + + /* initialize the response buffer */ + fb_response_str = response; + + /* Always enable image flash for Android Things. */ +#if defined(CONFIG_FASTBOOT_LOCK) && !defined(CONFIG_AVB_ATX) + int status; + status = fastboot_get_lock_stat(); + + if (status == FASTBOOT_LOCK) { + pr_err("device is LOCKed!\n"); + strcpy(response, "FAIL device is locked."); + fastboot_tx_write_str(response); + return; + + } else if (status == FASTBOOT_LOCK_ERROR) { + pr_err("write lock status into device!\n"); + fastboot_set_lock_stat(FASTBOOT_LOCK); + strcpy(response, "FAILdevice is locked."); + fastboot_tx_write_str(response); + return; + } +#endif + fastboot_fail("no flash device defined"); + + rx_process_flash(cmd); + +#ifdef CONFIG_FASTBOOT_LOCK + if (strncmp(cmd, "gpt", 3) == 0) { + int gpt_valid = 0; + gpt_valid = partition_table_valid(); + /* If gpt is valid, load partitons table into memory. + So if the next command is "fastboot reboot bootloader", + it can find the "misc" partition to r/w. */ + if(gpt_valid) { + _fastboot_load_partitions(); + /* Unlock device if the gpt is valid */ + do_fastboot_unlock(true); + } + } + +#endif + fastboot_tx_write_str(response); +} +#endif + +#ifdef CONFIG_FASTBOOT_FLASH +static void cb_erase(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[FASTBOOT_RESPONSE_LEN]; + + strsep(&cmd, ":"); + if (!cmd) { + pr_err("missing partition name"); + fastboot_tx_write_str("FAILmissing partition name"); + return; + } - usb_ep_dequeue(fastboot_func->in_ep, in_req); + /* initialize the response buffer */ + fb_response_str = response; - ret = usb_ep_queue(fastboot_func->in_ep, in_req, 0); - if (ret) - printf("Error %d on queue\n", ret); - return 0; +#if defined(CONFIG_FASTBOOT_LOCK) && !defined(CONFIG_AVB_ATX) + FbLockState status; + status = fastboot_get_lock_stat(); + if (status == FASTBOOT_LOCK) { + pr_err("device is LOCKed!\n"); + strcpy(response, "FAIL device is locked."); + fastboot_tx_write_str(response); + return; + } else if (status == FASTBOOT_LOCK_ERROR) { + pr_err("write lock status into device!\n"); + fastboot_set_lock_stat(FASTBOOT_LOCK); + strcpy(response, "FAILdevice is locked."); + fastboot_tx_write_str(response); + return; + } +#endif + rx_process_erase(cmd, response); + fastboot_tx_write_str(response); } +#endif -static int fastboot_tx_write_str(const char *buffer) +#ifndef CONFIG_NOT_UUU_BUILD +static void cb_run_uboot_cmd(struct usb_ep *ep, struct usb_request *req) { - return fastboot_tx_write(buffer, strlen(buffer)); + char *cmd = req->buf; + strsep(&cmd, ":"); + if (!cmd) { + pr_err("missing slot suffix\n"); + fastboot_tx_write_str("FAILmissing command"); + return; + } + if(run_command(cmd, 0)) { + fastboot_tx_write_str("FAIL"); + } else { + fastboot_tx_write_str("OKAY"); + /* cmd may impact fastboot related environment*/ + fastboot_setup(); + } + return ; } -static void compl_do_reset(struct usb_ep *ep, struct usb_request *req) +static char g_a_cmd_buff[64]; +static void do_acmd_complete(struct usb_ep *ep, struct usb_request *req) { - do_reset(NULL, 0, 0, NULL); + /* When usb dequeue complete will be called + * Meed status value before call run_command. + * otherwise, host can't get last message. + */ + if(req->status == 0) + run_command(g_a_cmd_buff, 0); } -int __weak fb_set_reboot_flag(void) +static void cb_run_uboot_acmd(struct usb_ep *ep, struct usb_request *req) { - return -ENOSYS; + char *cmd = req->buf; + strsep(&cmd, ":"); + if (!cmd) { + pr_err("missing slot suffix\n"); + fastboot_tx_write_str("FAILmissing command"); + return; + } + strcpy(g_a_cmd_buff, cmd); + fastboot_func->in_req->complete = do_acmd_complete; + fastboot_tx_write_str("OKAY"); } +#endif -static void cb_reboot(struct usb_ep *ep, struct usb_request *req) +#ifdef CONFIG_AVB_SUPPORT +static void cb_set_active_avb(struct usb_ep *ep, struct usb_request *req) { + AvbIOResult ret; + int slot = 0; char *cmd = req->buf; - if (!strcmp_l1("reboot-bootloader", cmd)) { - if (fb_set_reboot_flag()) { - fastboot_tx_write_str("FAILCannot set reboot flag"); - return; - } + + strsep(&cmd, ":"); + if (!cmd) { + pr_err("missing slot suffix\n"); + fastboot_tx_write_str("FAILmissing slot suffix"); + return; } - fastboot_func->in_req->complete = compl_do_reset; - fastboot_tx_write_str("OKAY"); + + slot = slotidx_from_suffix(cmd); + + if (slot < 0) { + fastboot_tx_write_str("FAILerr slot suffix"); + return; + } + + ret = avb_ab_mark_slot_active(&fsl_avb_ab_ops, slot); + if (ret != AVB_IO_RESULT_OK) + fastboot_tx_write_str("avb IO error"); + else + fastboot_tx_write_str("OKAY"); + + return; } +#endif /*CONFIG_AVB_SUPPORT*/ -static int strcmp_l1(const char *s1, const char *s2) +static void cb_reboot_bootloader(struct usb_ep *ep, struct usb_request *req) { - if (!s1 || !s2) - return -1; - return strncmp(s1, s2, strlen(s1)); + enable_fastboot_command(); + fastboot_func->in_req->complete = compl_do_reset; + fastboot_tx_write_str("OKAY"); } +#else /* CONFIG_FSL_FASTBOOT */ + static void cb_getvar(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; @@ -454,11 +4182,92 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) fastboot_tx_write_str(response); } +#ifdef CONFIG_FASTBOOT_FLASH +static void cb_flash(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[FASTBOOT_RESPONSE_LEN]; + + strsep(&cmd, ":"); + if (!cmd) { + pr_err("missing partition name"); + fastboot_tx_write_str("FAILmissing partition name"); + return; + } + + /* initialize the response buffer */ + fb_response_str = response; + + fastboot_fail("no flash device defined"); +#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV + fb_mmc_flash_write(cmd, (void *)CONFIG_FASTBOOT_BUF_ADDR, + download_bytes); +#endif +#ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV + fb_nand_flash_write(cmd, + (void *)CONFIG_FASTBOOT_BUF_ADDR, + download_bytes); +#endif + fastboot_tx_write_str(response); +} +#endif + +static void cb_oem(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; +#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV + if (strncmp("format", cmd + 4, 6) == 0) { + char cmdbuf[32]; + sprintf(cmdbuf, "gpt write mmc %x $partitions", + CONFIG_FASTBOOT_FLASH_MMC_DEV); + if (run_command(cmdbuf, 0)) + fastboot_tx_write_str("FAIL"); + else + fastboot_tx_write_str("OKAY"); + } else +#endif + if (strncmp("unlock", cmd + 4, 8) == 0) { + fastboot_tx_write_str("FAILnot implemented"); + } + else { + fastboot_tx_write_str("FAILunknown oem command"); + } +} + +#ifdef CONFIG_FASTBOOT_FLASH +static void cb_erase(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[FASTBOOT_RESPONSE_LEN]; + + strsep(&cmd, ":"); + if (!cmd) { + pr_err("missing partition name"); + fastboot_tx_write_str("FAILmissing partition name"); + return; + } + + /* initialize the response buffer */ + fb_response_str = response; + + fastboot_fail("no flash device defined"); +#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV + fb_mmc_erase(cmd); +#endif +#ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV + fb_nand_erase(cmd); +#endif + fastboot_tx_write_str(response); +} +#endif + +#endif /* CONFIG_FSL_FASTBOOT*/ + static unsigned int rx_bytes_expected(struct usb_ep *ep) { int rx_remain = download_size - download_bytes; unsigned int rem; - unsigned int maxpacket = ep->maxpacket; + unsigned int maxpacket = usb_endpoint_maxp(ep->desc); if (rx_remain <= 0) return 0; @@ -486,6 +4295,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) const unsigned char *buffer = req->buf; unsigned int buffer_size = req->actual; unsigned int pre_dot_num, now_dot_num; + void * base_addr = (void*)env_get_ulong("fastboot_buffer", 16, CONFIG_FASTBOOT_BUF_ADDR); if (req->status != 0) { printf("Bad status: %d\n", req->status); @@ -495,7 +4305,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) if (buffer_size < transfer_size) transfer_size = buffer_size; - memcpy((void *)CONFIG_FASTBOOT_BUF_ADDR + download_bytes, + memcpy(base_addr + download_bytes, buffer, transfer_size); pre_dot_num = download_bytes / BYTES_PER_DOT; @@ -520,6 +4330,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) strcpy(response, "OKAY"); fastboot_tx_write_str(response); + env_set_hex("fastboot_bytes", download_bytes); printf("\ndownloading of %d bytes finished\n", download_bytes); } else { @@ -530,6 +4341,26 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) usb_ep_queue(ep, req, 0); } +static void cb_upload(struct usb_ep *ep, struct usb_request *req) +{ + char response[FASTBOOT_RESPONSE_LEN]; + + if (!download_bytes || download_bytes > (EP_BUFFER_SIZE * 32)) { + sprintf(response, "FAIL"); + fastboot_tx_write_str(response); + return; + } + + printf("Will upload %d bytes.\n", download_bytes); + snprintf(response, FASTBOOT_RESPONSE_LEN, "DATA%08x", download_bytes); + fastboot_tx_write_more(response); + + fastboot_tx_write((const char *)(interface.transfer_buffer), download_bytes); + + snprintf(response,FASTBOOT_RESPONSE_LEN, "OKAY"); + fastboot_tx_write_more(response); +} + static void cb_download(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; @@ -557,11 +4388,16 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) static void do_bootm_on_complete(struct usb_ep *ep, struct usb_request *req) { char boot_addr_start[12]; +#ifdef CONFIG_FSL_FASTBOOT + char *bootm_args[] = { "boota", boot_addr_start, NULL }; + sprintf(boot_addr_start, "0x%lx", load_addr); +#else char *bootm_args[] = { "bootm", boot_addr_start, NULL }; + sprintf(boot_addr_start, "0x%lx", (long)CONFIG_FASTBOOT_BUF_ADDR); +#endif puts("Booting kernel..\n"); - sprintf(boot_addr_start, "0x%lx", (long)CONFIG_FASTBOOT_BUF_ADDR); do_bootm(NULL, 0, 2, bootm_args); /* This only happens if image is somehow faulty so we start over */ @@ -585,91 +4421,51 @@ static void cb_continue(struct usb_ep *ep, struct usb_request *req) fastboot_tx_write_str("OKAY"); } -#ifdef CONFIG_FASTBOOT_FLASH -static void cb_flash(struct usb_ep *ep, struct usb_request *req) -{ - char *cmd = req->buf; - char response[FASTBOOT_RESPONSE_LEN]; - - strsep(&cmd, ":"); - if (!cmd) { - pr_err("missing partition name"); - fastboot_tx_write_str("FAILmissing partition name"); - return; - } - - /* initialize the response buffer */ - fb_response_str = response; - - fastboot_fail("no flash device defined"); -#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV - fb_mmc_flash_write(cmd, (void *)CONFIG_FASTBOOT_BUF_ADDR, - download_bytes); -#endif -#ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV - fb_nand_flash_write(cmd, - (void *)CONFIG_FASTBOOT_BUF_ADDR, - download_bytes); -#endif - fastboot_tx_write_str(response); -} -#endif - -static void cb_oem(struct usb_ep *ep, struct usb_request *req) -{ - char *cmd = req->buf; -#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV - if (strncmp("format", cmd + 4, 6) == 0) { - char cmdbuf[32]; - sprintf(cmdbuf, "gpt write mmc %x $partitions", - CONFIG_FASTBOOT_FLASH_MMC_DEV); - if (run_command(cmdbuf, 0)) - fastboot_tx_write_str("FAIL"); - else - fastboot_tx_write_str("OKAY"); - } else -#endif - if (strncmp("unlock", cmd + 4, 8) == 0) { - fastboot_tx_write_str("FAILnot implemented"); - } - else { - fastboot_tx_write_str("FAILunknown oem command"); - } -} - -#ifdef CONFIG_FASTBOOT_FLASH -static void cb_erase(struct usb_ep *ep, struct usb_request *req) -{ - char *cmd = req->buf; - char response[FASTBOOT_RESPONSE_LEN]; - - strsep(&cmd, ":"); - if (!cmd) { - pr_err("missing partition name"); - fastboot_tx_write_str("FAILmissing partition name"); - return; - } - - /* initialize the response buffer */ - fb_response_str = response; - - fastboot_fail("no flash device defined"); -#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV - fb_mmc_erase(cmd); -#endif -#ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV - fb_nand_erase(cmd); -#endif - fastboot_tx_write_str(response); -} -#endif - struct cmd_dispatch_info { char *cmd; void (*cb)(struct usb_ep *ep, struct usb_request *req); }; static const struct cmd_dispatch_info cmd_dispatch_info[] = { +#ifdef CONFIG_FSL_FASTBOOT + { + .cmd = "reboot-bootloader", + .cb = cb_reboot_bootloader, + }, + { + .cmd = "upload", + .cb = cb_upload, + }, + { + .cmd = "get_staged", + .cb = cb_upload, + }, +#ifdef CONFIG_FASTBOOT_LOCK + { + .cmd = "flashing", + .cb = cb_flashing, + }, + { + .cmd = "oem", + .cb = cb_flashing, + }, +#endif +#ifdef CONFIG_AVB_SUPPORT + { + .cmd = "set_active", + .cb = cb_set_active_avb, + }, +#endif +#ifndef CONFIG_NOT_UUU_BUILD + { + .cmd = "UCmd:", + .cb = cb_run_uboot_cmd, + }, + { .cmd ="ACmd:", + .cb = cb_run_uboot_acmd, + }, +#endif +#endif { .cmd = "reboot", .cb = cb_reboot, @@ -695,10 +4491,18 @@ static const struct cmd_dispatch_info cmd_dispatch_info[] = { .cb = cb_erase, }, #endif +#ifndef CONFIG_FSL_FASTBOOT { .cmd = "oem", .cb = cb_oem, }, +#endif +#ifdef CONFIG_AVB_ATX + { + .cmd = "stage", + .cb = cb_download, + }, +#endif }; static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) @@ -707,6 +4511,10 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL; int i; + /* init in request FIFO pointer */ + fastboot_func->front = NULL; + fastboot_func->rear = NULL; + if (req->status != 0 || req->length == 0) return; diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index 1ecb92ac6b8..e6d9e5e7703 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -447,6 +447,7 @@ static void set_bulk_out_req_length(struct fsg_common *common, static struct ums *ums; static int ums_count; static struct fsg_common *the_fsg_common; +static unsigned int controller_index = 0; static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep) { @@ -691,7 +692,7 @@ static int sleep_thread(struct fsg_common *common) k = 0; } - usb_gadget_handle_interrupts(0); + usb_gadget_handle_interrupts(controller_index); } common->thread_wakeup_needed = 0; return rc; @@ -2776,10 +2777,11 @@ int fsg_add(struct usb_configuration *c) return fsg_bind_config(c->cdev, c, fsg_common); } -int fsg_init(struct ums *ums_devs, int count) +int fsg_init(struct ums *ums_devs, int count, unsigned int controller_idx) { ums = ums_devs; ums_count = count; + controller_index = controller_idx; return 0; } diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index 43c5cfbb77a..d87877e2a80 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -102,6 +102,7 @@ struct f_sdp { enum sdp_state next_state; u32 dnl_address; u32 dnl_bytes_remaining; + u32 last_dnl_file_bytes; u32 jmp_address; bool always_send_status; u32 error_status; @@ -157,6 +158,16 @@ static struct usb_endpoint_descriptor in_desc = { .bInterval = 1, }; +static struct usb_endpoint_descriptor in_hs_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, /*USB_DT_CS_ENDPOINT*/ + + .bEndpointAddress = 1 | USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_INT, + .wMaxPacketSize = 512, + .bInterval = 1, +}; + static struct usb_descriptor_header *sdp_runtime_descs[] = { (struct usb_descriptor_header *)&sdp_intf_runtime, (struct usb_descriptor_header *)&sdp_hid_desc, @@ -164,6 +175,13 @@ static struct usb_descriptor_header *sdp_runtime_descs[] = { NULL, }; +static struct usb_descriptor_header *sdp_runtime_hs_descs[] = { + (struct usb_descriptor_header *)&sdp_intf_runtime, + (struct usb_descriptor_header *)&sdp_hid_desc, + (struct usb_descriptor_header *)&in_hs_desc, + NULL, +}; + /* This is synchronized with what the SoC implementation reports */ static struct hid_report sdp_hid_report = { .usage_page = { @@ -230,6 +248,18 @@ static struct usb_gadget_strings *sdp_generic_strings[] = { NULL, }; +#ifdef CONFIG_PARSE_CONTAINER +int __weak sdp_load_image_parse_container(struct spl_image_info *spl_image, + unsigned long offset) +{ + return -EINVAL; +} +#endif + +void __weak board_sdp_cleanup(void) +{ +} + static inline void *sdp_ptr(u32 val) { return (void *)(uintptr_t)val; @@ -275,8 +305,9 @@ static void sdp_rx_command_complete(struct usb_ep *ep, struct usb_request *req) sdp->error_status = SDP_WRITE_FILE_COMPLETE; sdp->state = SDP_STATE_RX_FILE_DATA; - sdp->dnl_address = be32_to_cpu(cmd->addr); + sdp->dnl_address = cmd->addr ? be32_to_cpu(cmd->addr) : CONFIG_SDP_LOADADDR; sdp->dnl_bytes_remaining = be32_to_cpu(cmd->cnt); + sdp->last_dnl_file_bytes = sdp->dnl_bytes_remaining; sdp->next_state = SDP_STATE_IDLE; printf("Downloading file of size %d to 0x%08x... ", @@ -302,7 +333,7 @@ static void sdp_rx_command_complete(struct usb_ep *ep, struct usb_request *req) sdp->always_send_status = false; sdp->error_status = 0; - sdp->jmp_address = be32_to_cpu(cmd->addr); + sdp->jmp_address = cmd->addr ? be32_to_cpu(cmd->addr) : CONFIG_SDP_LOADADDR; sdp->state = SDP_STATE_TX_SEC_CONF; sdp->next_state = SDP_STATE_JUMP; break; @@ -483,6 +514,11 @@ static int sdp_bind(struct usb_configuration *c, struct usb_function *f) goto error; } + if (gadget_is_dualspeed(gadget)) { + /* Assume endpoint addresses are the same for both speeds */ + in_hs_desc.bEndpointAddress = in_desc.bEndpointAddress; + } + sdp->in_ep = ep; /* Store IN EP for enabling @ setup */ cdev->req->context = sdp; @@ -520,7 +556,7 @@ static struct usb_request *sdp_start_ep(struct usb_ep *ep) { struct usb_request *req; - req = alloc_ep_req(ep, 64); + req = alloc_ep_req(ep, 65); debug("%s: ep:%p req:%p\n", __func__, ep, req); if (!req) @@ -535,11 +571,15 @@ static int sdp_set_alt(struct usb_function *f, unsigned intf, unsigned alt) { struct f_sdp *sdp = func_to_sdp(f); struct usb_composite_dev *cdev = f->config->cdev; + struct usb_gadget *gadget = cdev->gadget; int result; debug("%s: intf: %d alt: %d\n", __func__, intf, alt); - result = usb_ep_enable(sdp->in_ep, &in_desc); + if (gadget_is_dualspeed(gadget) && gadget->speed == USB_SPEED_HIGH) + result = usb_ep_enable(sdp->in_ep, &in_hs_desc); + else + result = usb_ep_enable(sdp->in_ep, &in_desc); if (result) return result; sdp->in_req = sdp_start_ep(sdp->in_ep); @@ -585,7 +625,7 @@ static int sdp_bind_config(struct usb_configuration *c) memset(sdp_func, 0, sizeof(*sdp_func)); sdp_func->usb_function.name = "sdp"; - sdp_func->usb_function.hs_descriptors = sdp_runtime_descs; + sdp_func->usb_function.hs_descriptors = sdp_runtime_hs_descs; sdp_func->usb_function.descriptors = sdp_runtime_descs; sdp_func->usb_function.bind = sdp_bind; sdp_func->usb_function.unbind = sdp_unbind; @@ -634,6 +674,42 @@ static u32 sdp_jump_imxheader(void *address) return 0; } +static ulong sdp_spl_fit_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf) +{ + memcpy(buf, (void *)sector, count); + + return count; +} + +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_PARSE_CONTAINER +static ulong search_container_header(ulong p, int size) +{ + int i = 0; + uint8_t *hdr; + for (i = 0; i < size; i += 4) { + hdr = (uint8_t *)(p +i); + if (*(hdr + 3) == 0x87 && *hdr == 0 && + (*(hdr + 1) != 0 || *(hdr + 2) != 0)) + return p +i; + } + return 0; +} +#else +static ulong search_fit_header(ulong p, int size) +{ + int i = 0; + for (i = 0; i < size; i += 4) { + if (genimg_get_format((const void *)(p+i)) == IMAGE_FORMAT_FIT) + return p + i; + } + + return 0; +} +#endif +#endif + static void sdp_handle_in_ep(void) { u8 *data = sdp_func->in_req->buf; @@ -686,10 +762,51 @@ static void sdp_handle_in_ep(void) /* If imx header fails, try some U-Boot specific headers */ if (status) { #ifdef CONFIG_SPL_BUILD - /* In SPL, allow jumps to U-Boot images */ + struct image_header *header; struct spl_image_info spl_image = {}; - spl_parse_image_header(&spl_image, - (struct image_header *)sdp_func->jmp_address); + +#ifdef CONFIG_PARSE_CONTAINER + sdp_func->jmp_address = (u32)search_container_header((ulong)sdp_func->jmp_address, + sdp_func->last_dnl_file_bytes); +#else + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) + sdp_func->jmp_address = (u32)search_fit_header((ulong)sdp_func->jmp_address, + sdp_func->last_dnl_file_bytes); +#endif + if (sdp_func->jmp_address == 0) { + panic("Error in search header, failed to jump\n"); + } + + printf("Found header at 0x%08x\n", sdp_func->jmp_address); + + header = (struct image_header *)(ulong)(sdp_func->jmp_address); + + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && + image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + debug("Found FIT\n"); + load.dev = NULL; + load.priv = NULL; + load.filename = NULL; + load.bl_len = 1; + load.read = sdp_spl_fit_read; + spl_load_simple_fit(&spl_image, &load, + sdp_func->jmp_address, + (void *)header); + } else { +#ifdef CONFIG_PARSE_CONTAINER + sdp_load_image_parse_container(&spl_image, + sdp_func->jmp_address); +#else + /* In SPL, allow jumps to U-Boot images */ + spl_parse_image_header(&spl_image, + (struct image_header *)(ulong)(sdp_func->jmp_address)); +#endif + } + + board_sdp_cleanup(); + jump_to_image_no_args(&spl_image); #else /* In U-Boot, allow jumps to scripts */ diff --git a/drivers/usb/gadget/fastboot_lock_unlock.c b/drivers/usb/gadget/fastboot_lock_unlock.c new file mode 100644 index 00000000000..06d21e73b8f --- /dev/null +++ b/drivers/usb/gadget/fastboot_lock_unlock.c @@ -0,0 +1,608 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "fastboot_lock_unlock.h" +#include +#include +#include +#ifdef CONFIG_IMX_TRUSTY_OS +#include +#include +#endif + +#ifdef FASTBOOT_ENCRYPT_LOCK + +#include +#include + +//Encrypted data is 80bytes length. +#define ENDATA_LEN 80 + +#endif + +int fastboot_flash_find_index(const char *name); + +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_ARM64) +#define IVT_HEADER_MAGIC 0xD1 +#define IVT_HDR_LEN 0x20 +#define HAB_MAJ_VER 0x40 +#define HAB_MAJ_MASK 0xF0 + +bool tos_flashed; + +static bool tos_ivt_check(ulong start_addr, int ivt_offset) { + const struct ivt *ivt_initial = NULL; + const uint8_t *start = (const uint8_t *)start_addr; + + if (start_addr & 0x3) { + puts("Error: tos's start address is not 4 byte aligned\n"); + return false; + } + + ivt_initial = (const struct ivt *)(start + ivt_offset); + + const struct ivt_header *ivt_hdr = &ivt_initial->hdr; + + if ((ivt_hdr->magic == IVT_HEADER_MAGIC && \ + (be16_to_cpu(ivt_hdr->length) == IVT_HDR_LEN) && \ + (ivt_hdr->version & HAB_MAJ_MASK) == HAB_MAJ_VER) && \ + (ivt_initial->entry != 0x0) && \ + (ivt_initial->reserved1 == 0x0) && \ + (ivt_initial->self == (uint32_t)ivt_initial) && \ + (ivt_initial->csf != 0x0) && \ + (ivt_initial->reserved2 == 0x0)) { + if (ivt_initial->dcd != 0x0) + return false; + else + return true; + } + + return false; +} + +bool valid_tos() { + /* + * If enabled SECURE_BOOT then use HAB to verify tos. + * Or check the IVT only. + */ + bool valid = false; +#ifdef CONFIG_SECURE_BOOT + if (is_hab_enabled()) { + valid = authenticate_image(TRUSTY_OS_ENTRY, TRUSTY_OS_PADDED_SZ); + } else +#endif + valid = tos_ivt_check(TRUSTY_OS_ENTRY, TRUSTY_OS_PADDED_SZ); + + if (valid) { + tos_flashed = true; + return true; + } else { + tos_flashed = false; + return false; + } +} + +#endif + +#if !defined(FASTBOOT_ENCRYPT_LOCK) || defined(NON_SECURE_FASTBOOT) + +/* + * This will return FASTBOOT_LOCK, FASTBOOT_UNLOCK or FASTBOOT_ERROR + */ +#ifndef CONFIG_IMX_TRUSTY_OS +static FbLockState decrypt_lock_store(unsigned char* bdata) { + if (!strncmp((const char *)bdata, "locked", strlen("locked"))) + return FASTBOOT_LOCK; + else if (!strncmp((const char *)bdata, "unlocked", strlen("unlocked"))) + return FASTBOOT_UNLOCK; + else + return FASTBOOT_LOCK_ERROR; +} +static inline int encrypt_lock_store(FbLockState lock, unsigned char* bdata) { + if (FASTBOOT_LOCK == lock) + strncpy((char *)bdata, "locked", strlen("locked")); + else if (FASTBOOT_UNLOCK == lock) + strncpy((char *)bdata, "unlocked", strlen("unlocked")); + else + return -1; + return 0; +} +#endif +#else + +static int sha1sum(unsigned char* data, int len, unsigned char* output) { + struct hash_algo *algo; + void *buf; + if (hash_lookup_algo("sha1", &algo)) { + printf("error in lookup sha1 algo!\n"); + return -1; + } + buf = map_sysmem((ulong)data, len); + algo->hash_func_ws(buf, len, output, algo->chunk_size); + unmap_sysmem(buf); + + return algo->digest_size; + +} + +static int generate_salt(unsigned char* salt) { + unsigned long time = get_timer(0); + return sha1sum((unsigned char *)&time, sizeof(unsigned long), salt); + +} + +static FbLockState decrypt_lock_store(unsigned char *bdata) { + int p = 0, ret; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, plain_data, ENDATA_LEN); + + caam_open(); + ret = caam_decap_blob((uint32_t)(ulong)plain_data, + (uint32_t)(ulong)bdata + ROUND(ENDATA_LEN, ARCH_DMA_MINALIGN), + ENDATA_LEN); + if (ret != 0) { + printf("Error during blob decap operation: 0x%x\n",ret); + return FASTBOOT_LOCK_ERROR; + } +#ifdef FASTBOOT_LOCK_DEBUG + FB_DEBUG("Decrypt data block are:\n \t=======\t\n"); + for (p = 0; p < ENDATA_LEN; p++) { + FB_DEBUG("0x%2x ", *(bdata + p)); + if (p % 16 == 0) + FB_DEBUG("\n"); + } + FB_DEBUG("\n \t========\t\n"); + for (p = ENDATA_LEN; p < (ENDATA_LEN + ENDATA_LEN + 48 ); p++) { + FB_DEBUG("0x%2x ", *(bdata + p)); + if (p % 16 == 0) + FB_DEBUG("\n"); + } + + FB_DEBUG("\n plain text are:\n"); + for (p = 0; p < ENDATA_LEN; p++) { + FB_DEBUG("0x%2x ", plain_data[p]); + if (p % 16 == 0) + FB_DEBUG("\n"); + } + FB_DEBUG("\n"); +#endif + + for (p = 0; p < ENDATA_LEN-1; p++) { + if (*(bdata+p) != plain_data[p]) { + FB_DEBUG("Verify salt in decrypt error on pointer %d\n", p); + return FASTBOOT_LOCK_ERROR; + } + } + + if (plain_data[ENDATA_LEN - 1] >= FASTBOOT_LOCK_NUM) + return FASTBOOT_LOCK_ERROR; + else + return plain_data[ENDATA_LEN-1]; +} + +static int encrypt_lock_store(FbLockState lock, unsigned char* bdata) { + unsigned int p = 0; + int ret; + int salt_len = generate_salt(bdata); + if (salt_len < 0) + return -1; + + //salt_len cannot be longer than endata block size. + if (salt_len >= ENDATA_LEN) + salt_len = ENDATA_LEN - 1; + + p = ENDATA_LEN - 1; + + //Set lock value + *(bdata + p) = lock; + + caam_open(); + ret = caam_gen_blob((uint32_t)(ulong)bdata, + (uint32_t)(ulong)bdata + ROUND(ENDATA_LEN, ARCH_DMA_MINALIGN), + ENDATA_LEN); + if (ret != 0) { + printf("error in caam_gen_blob:0x%x\n", ret); + return -1; + } + + +#ifdef FASTBOOT_LOCK_DEBUG + int i = 0; + FB_DEBUG("encrypt plain_text:\n"); + for (i = 0; i < ENDATA_LEN; i++) { + FB_DEBUG("0x%2x\t", *(bdata+i)); + if (i % 16 == 0) + printf("\n"); + } + printf("\nto:\n"); + for (i=0; i < ENDATA_LEN + 48; i++) { + FB_DEBUG("0x%2x\t", *(bdata + ENDATA_LEN + i)); + if (i % 16 == 0) + printf("\n"); + } + printf("\n"); + +#endif + //protect value + *(bdata + p) = 0xff; + return 0; +} + +#endif + +static char mmc_dev_part[16]; +static char* get_mmc_part(int part) { + u32 dev_no = mmc_get_env_dev(); + sprintf(mmc_dev_part,"%x:%x",dev_no, part); + return mmc_dev_part; +} + +static inline void set_lock_disable_data(unsigned char* bdata) { + *(bdata + SECTOR_SIZE -1) = 0; +} + +/* + * The enabling value is stored in the last byte of target partition. + */ +static inline unsigned char lock_enable_parse(unsigned char* bdata) { + FB_DEBUG("lock_enable_parse: 0x%x\n", *(bdata + SECTOR_SIZE -1)); + if (*(bdata + SECTOR_SIZE -1) >= FASTBOOT_UL_NUM) + return FASTBOOT_UL_ERROR; + else + return *(bdata + SECTOR_SIZE -1); +} + +static FbLockState g_lockstat = FASTBOOT_UNLOCK; + +#ifdef CONFIG_IMX_TRUSTY_OS +FbLockState fastboot_get_lock_stat(void) { + uint8_t l_status; + int ret; + /* + * If Trusty OS not flashed, then must return + * unlock status to make device been able + * to flash Trusty OS binary. + */ +#ifndef CONFIG_ARM64 + if (!tos_flashed) + return FASTBOOT_UNLOCK; +#endif + ret = trusty_read_lock_state(&l_status); + if (ret < 0) + return g_lockstat; + else + return l_status; + +} + +int fastboot_set_lock_stat(FbLockState lock) { + int ret; + /* + * If Trusty OS not flashed, we must prevent set lock + * status. Due the Trusty IPC won't work here. + */ +#ifndef CONFIG_ARM64 + if (!tos_flashed) + return 0; +#endif + ret = trusty_write_lock_state(lock); + if (ret < 0) { + printf("cannot set lock status due Trusty return %d\n", ret); + return ret; + } + return 0; +} +#else + +/* + * Set status of the lock&unlock to FSL_FASTBOOT_FB_PART + * Currently use the very first Byte of FSL_FASTBOOT_FB_PART + * to store the fastboot lock&unlock status + */ +int fastboot_set_lock_stat(FbLockState lock) { + struct blk_desc *fs_dev_desc; + disk_partition_t fs_partition; + unsigned char *bdata; + int mmc_id; + int status, ret; + + bdata = (unsigned char *)memalign(ARCH_DMA_MINALIGN, SECTOR_SIZE); + if (bdata == NULL) + goto fail2; + memset(bdata, 0, SECTOR_SIZE); + + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_FBMISC); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + ret = -1; + goto fail; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), + &fs_dev_desc, &fs_partition, 1); + if (status < 0) { + printf("%s:error in getdevice partition.\n", __FUNCTION__); + ret = -1; + goto fail; + } + + status = encrypt_lock_store(lock, bdata); + if (status < 0) { + ret = -1; + goto fail; + } + status = blk_dwrite(fs_dev_desc, fs_partition.start, 1, bdata); + if (!status) { + printf("%s:error in block write.\n", __FUNCTION__); + ret = -1; + goto fail; + } + ret = 0; +fail: + free(bdata); + return ret; +fail2: + g_lockstat = lock; + return 0; +} + +FbLockState fastboot_get_lock_stat(void) { + struct blk_desc *fs_dev_desc; + disk_partition_t fs_partition; + unsigned char *bdata; + int mmc_id; + FbLockState ret; + /* uboot used by uuu will boot from USB, always return UNLOCK state */ + if (is_boot_from_usb()) + return g_lockstat; + + bdata = (unsigned char *)memalign(ARCH_DMA_MINALIGN, SECTOR_SIZE); + if (bdata == NULL) + return g_lockstat; + + int status; + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_FBMISC); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + ret = g_lockstat; + goto fail; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), + &fs_dev_desc, &fs_partition, 1); + + if (status < 0) { + printf("%s:error in getdevice partition.\n", __FUNCTION__); + ret = g_lockstat; + goto fail; + } + + status = blk_dread(fs_dev_desc, fs_partition.start, 1, bdata); + if (!status) { + printf("%s:error in block read.\n", __FUNCTION__); + ret = FASTBOOT_LOCK_ERROR; + goto fail; + } + + ret = decrypt_lock_store(bdata); +fail: + free(bdata); + return ret; +} +#endif + + +/* Return the last byte of of FSL_FASTBOOT_PR_DATA + * which is managed by PresistDataService + */ + +#ifdef CONFIG_ENABLE_LOCKSTATUS_SUPPORT +//Brillo has no presist data partition +FbLockEnableResult fastboot_lock_enable(void) { + return FASTBOOT_UL_ENABLE; +} +void set_fastboot_lock_disable(void) { +} +#else +void set_fastboot_lock_disable(void) { + struct blk_desc *fs_dev_desc; + disk_partition_t fs_partition; + unsigned char *bdata; + int mmc_id; + + bdata = (unsigned char *)memalign(ALIGN_BYTES, SECTOR_SIZE); + if (bdata == NULL) + return; + set_lock_disable_data(bdata); + int status; + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_PRDATA); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + goto fail; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), + &fs_dev_desc, &fs_partition, 1); + if (status < 0) { + printf("%s:error in getdevice partition.\n", __FUNCTION__); + goto fail; + } + + lbaint_t target_block = fs_partition.start + fs_partition.size - 1; + status = blk_dwrite(fs_dev_desc, target_block, 1, bdata); + if (!status) { + printf("%s: error in block read\n", __FUNCTION__); + goto fail; + } + +fail: + free(bdata); + return; + +} +FbLockEnableResult fastboot_lock_enable() { + struct blk_desc *fs_dev_desc; + disk_partition_t fs_partition; + unsigned char *bdata; + int mmc_id; + FbLockEnableResult ret; + + bdata = (unsigned char *)memalign(ALIGN_BYTES, SECTOR_SIZE); + if (bdata == NULL) + return FASTBOOT_UL_ERROR; + int status; + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_PRDATA); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + ret = FASTBOOT_UL_ERROR; + goto fail; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), + &fs_dev_desc, &fs_partition, 1); + if (status < 0) { + printf("%s:error in getdevice partition.\n", __FUNCTION__); + ret = FASTBOOT_UL_ERROR; + goto fail; + } + + //The data is stored in the last blcok of this partition. + lbaint_t target_block = fs_partition.start + fs_partition.size - 1; + status = blk_dread(fs_dev_desc, target_block, 1, bdata); + if (!status) { + printf("%s: error in block read\n", __FUNCTION__); + ret = FASTBOOT_UL_ERROR; + goto fail; + } + int i = 0; + FB_DEBUG("\n PRIST last sector is:\n"); + for (i = 0; i < SECTOR_SIZE; i++) { + FB_DEBUG("0x%x ", *(bdata + i)); + if (i % 32 == 0) + FB_DEBUG("\n"); + } + FB_DEBUG("\n"); + ret = lock_enable_parse(bdata); +fail: + free(bdata); + return ret; + +} +#endif + +int display_lock(FbLockState lock, int verify) { + struct stdio_dev *disp; + disp = stdio_get_by_name("vga"); + if (disp != NULL) { + if (lock == FASTBOOT_UNLOCK) { + disp->puts(disp, "\n============= NOTICE ============\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "| Your device is NOT locked. |\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "=================================\n"); + } else { + if (verify == -1) { + disp->puts(disp, "\n============= NOTICE ============\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "| Your device is NOT protected. |\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "=================================\n"); + } else if (verify == 1) { + disp->puts(disp, "\n============= NOTICE ============\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "| Boot verify failed! |\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "=================================\n"); + } + } + return 0; + } else + printf("not found VGA disp console.\n"); + + return -1; + +} + +int fastboot_wipe_data_partition(void) +{ + struct blk_desc *fs_dev_desc; + disk_partition_t fs_partition; + int status; + int mmc_id; + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_DATA); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + return -1; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), &fs_dev_desc, &fs_partition, 1); + if (status < 0) { + printf("error in get device partition for wipe /data\n"); + return -1; + } + status = blk_derase(fs_dev_desc, fs_partition.start , fs_partition.size ); + if (status != fs_partition.size ) { + printf("erase not complete\n"); + return -1; + } + mdelay(2000); + + return 0; +} + +void fastboot_wipe_all(void) { + struct blk_desc *fs_dev_desc; + disk_partition_t fs_partition; + int status; + int mmc_id; + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_GPT); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + return; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), &fs_dev_desc, &fs_partition, 1); + if (status < 0) { + printf("error in get device partition for wipe user partition\n"); + return; + } + status = blk_derase(fs_dev_desc, fs_partition.start , fs_partition.size ); + if (status != fs_partition.size ) { + printf("erase not complete\n"); + return; + } + printf("fastboot wiped all.\n"); +} diff --git a/drivers/usb/gadget/fastboot_lock_unlock.h b/drivers/usb/gadget/fastboot_lock_unlock.h new file mode 100644 index 00000000000..06c69ca88e3 --- /dev/null +++ b/drivers/usb/gadget/fastboot_lock_unlock.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef FASTBOOT_LOCK_UNLOCK_H +#define FASTBOOT_LOCK_UNLOCK_H + +#define ALIGN_BYTES 64 /*armv7 cache line need 64 bytes aligned */ + +//#define FASTBOOT_LOCK_DEBUG +#ifdef CONFIG_FSL_CAAM_KB +#define FASTBOOT_ENCRYPT_LOCK +#endif + +#ifdef FASTBOOT_LOCK_DEBUG +#define FB_DEBUG(format, ...) printf(format, ##__VA_ARGS__) +#else +#define FB_DEBUG(format, ...) +#endif + +typedef enum { + FASTBOOT_UNLOCK, + FASTBOOT_LOCK, + FASTBOOT_LOCK_ERROR, + FASTBOOT_LOCK_NUM +}FbLockState; + +typedef enum { + FASTBOOT_UL_DISABLE, + FASTBOOT_UL_ENABLE, + FASTBOOT_UL_ERROR, + FASTBOOT_UL_NUM +}FbLockEnableResult; + +FbLockState fastboot_get_lock_stat(void); + +int fastboot_set_lock_stat(FbLockState lock); + +int fastboot_wipe_data_partition(void); +void fastboot_wipe_all(void); + +FbLockEnableResult fastboot_lock_enable(void); +void set_fastboot_lock_disable(void); + +int display_lock(FbLockState lock, int verify); + +bool valid_tos(void); +#endif diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index 99d500a6af4..931993fc99e 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -278,6 +278,7 @@ static struct usb_composite_driver g_dnl_driver = { .name = NULL, .dev = &device_desc, .strings = g_dnl_composite_strings, + .max_speed = USB_SPEED_SUPER, .bind = g_dnl_bind, .unbind = g_dnl_unbind, diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index f3207084314..48b9707809d 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -149,6 +149,11 @@ #define gadget_is_dwc3(g) 0 #endif +#ifdef CONFIG_USB_CDNS3_GADGET +#define gadget_is_cdns3(g) (!strcmp("cdns3-gadget", (g)->name)) +#else +#define gadget_is_cdns3(g) 0 +#endif /* @@ -214,5 +219,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x21; else if (gadget_is_fotg210(gadget)) return 0x22; + else if (gadget_is_cdns3(gadget)) + return 0x23; return -ENOENT; } diff --git a/drivers/usb/gadget/u_os_desc.h b/drivers/usb/gadget/u_os_desc.h new file mode 100644 index 00000000000..4dab4814a36 --- /dev/null +++ b/drivers/usb/gadget/u_os_desc.h @@ -0,0 +1,123 @@ +/* + * u_os_desc.h + * + * Utility definitions for "OS Descriptors" support + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Author: Andrzej Pietrasiewicz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __U_OS_DESC_H__ +#define __U_OS_DESC_H__ + +#include + +#define USB_EXT_PROP_DW_SIZE 0 +#define USB_EXT_PROP_DW_PROPERTY_DATA_TYPE 4 +#define USB_EXT_PROP_W_PROPERTY_NAME_LENGTH 8 +#define USB_EXT_PROP_B_PROPERTY_NAME 10 +#define USB_EXT_PROP_DW_PROPERTY_DATA_LENGTH 10 +#define USB_EXT_PROP_B_PROPERTY_DATA 14 + +#define USB_EXT_PROP_RESERVED 0 +#define USB_EXT_PROP_UNICODE 1 +#define USB_EXT_PROP_UNICODE_ENV 2 +#define USB_EXT_PROP_BINARY 3 +#define USB_EXT_PROP_LE32 4 +#define USB_EXT_PROP_BE32 5 +#define USB_EXT_PROP_UNICODE_LINK 6 +#define USB_EXT_PROP_UNICODE_MULTI 7 + +static inline u8 *__usb_ext_prop_ptr(u8 *buf, size_t offset) +{ + return buf + offset; +} + +static inline u8 *usb_ext_prop_size_ptr(u8 *buf) +{ + return __usb_ext_prop_ptr(buf, USB_EXT_PROP_DW_SIZE); +} + +static inline u8 *usb_ext_prop_type_ptr(u8 *buf) +{ + return __usb_ext_prop_ptr(buf, USB_EXT_PROP_DW_PROPERTY_DATA_TYPE); +} + +static inline u8 *usb_ext_prop_name_len_ptr(u8 *buf) +{ + return __usb_ext_prop_ptr(buf, USB_EXT_PROP_W_PROPERTY_NAME_LENGTH); +} + +static inline u8 *usb_ext_prop_name_ptr(u8 *buf) +{ + return __usb_ext_prop_ptr(buf, USB_EXT_PROP_B_PROPERTY_NAME); +} + +static inline u8 *usb_ext_prop_data_len_ptr(u8 *buf, size_t off) +{ + return __usb_ext_prop_ptr(buf, + USB_EXT_PROP_DW_PROPERTY_DATA_LENGTH + off); +} + +static inline u8 *usb_ext_prop_data_ptr(u8 *buf, size_t off) +{ + return __usb_ext_prop_ptr(buf, USB_EXT_PROP_B_PROPERTY_DATA + off); +} + +static inline void usb_ext_prop_put_size(u8 *buf, int dw_size) +{ + put_unaligned_le32(dw_size, usb_ext_prop_size_ptr(buf)); +} + +static inline void usb_ext_prop_put_type(u8 *buf, int type) +{ + put_unaligned_le32(type, usb_ext_prop_type_ptr(buf)); +} + +static inline int usb_ext_prop_put_name(u8 *buf, const char *name, int pnl) +{ + int result; + + put_unaligned_le16(pnl, usb_ext_prop_name_len_ptr(buf)); + memset(usb_ext_prop_name_ptr(buf), 0, 2 * strlen(name)); + result = utf8_to_utf16le(name, (__le16 *)usb_ext_prop_name_ptr(buf), + strlen(name)); + if (result < 0) + return result; + + put_unaligned_le16(0, &buf[USB_EXT_PROP_B_PROPERTY_NAME + pnl - 2]); + + return pnl; +} + +static inline void usb_ext_prop_put_binary(u8 *buf, int pnl, const char *data, + int data_len) +{ + put_unaligned_le32(data_len, usb_ext_prop_data_len_ptr(buf, pnl)); + memcpy(usb_ext_prop_data_ptr(buf, pnl), data, data_len); +} + +static inline int usb_ext_prop_put_unicode(u8 *buf, int pnl, const char *string, + int data_len) +{ + int result; + put_unaligned_le32(data_len, usb_ext_prop_data_len_ptr(buf, pnl)); + memset(usb_ext_prop_data_ptr(buf, pnl), 0, 2 * (data_len >> 1)); + result = utf8_to_utf16le(string, (__le16 *) usb_ext_prop_data_ptr(buf, pnl), + data_len >> 1); + if (result < 0) + return result; + + put_unaligned_le16(0, + &buf[USB_EXT_PROP_B_PROPERTY_DATA + pnl + data_len - 2]); + + return data_len; +} + +#endif /* __U_OS_DESC_H__ */ diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile index 1699ccdf94c..63f09ab28a8 100644 --- a/drivers/usb/gadget/udc/Makefile +++ b/drivers/usb/gadget/udc/Makefile @@ -5,3 +5,4 @@ # obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o +obj-$(CONFIG_USB_CDNS3_GADGET) += udc-core.o diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c index 67e98c065d3..a72e3722359 100644 --- a/drivers/usb/gadget/usbstring.c +++ b/drivers/usb/gadget/usbstring.c @@ -11,79 +11,7 @@ #include #include #include - -#include - - -static int utf8_to_utf16le(const char *s, __le16 *cp, unsigned len) -{ - int count = 0; - u8 c; - u16 uchar; - - /* - * this insists on correct encodings, though not minimal ones. - * BUT it currently rejects legit 4-byte UTF-8 code points, - * which need surrogate pairs. (Unicode 3.1 can use them.) - */ - while (len != 0 && (c = (u8) *s++) != 0) { - if ((c & 0x80)) { - /* - * 2-byte sequence: - * 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx - */ - if ((c & 0xe0) == 0xc0) { - uchar = (c & 0x1f) << 6; - - c = (u8) *s++; - if ((c & 0xc0) != 0x80) - goto fail; - c &= 0x3f; - uchar |= c; - - /* - * 3-byte sequence (most CJKV characters): - * zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx - */ - } else if ((c & 0xf0) == 0xe0) { - uchar = (c & 0x0f) << 12; - - c = (u8) *s++; - if ((c & 0xc0) != 0x80) - goto fail; - c &= 0x3f; - uchar |= c << 6; - - c = (u8) *s++; - if ((c & 0xc0) != 0x80) - goto fail; - c &= 0x3f; - uchar |= c; - - /* no bogus surrogates */ - if (0xd800 <= uchar && uchar <= 0xdfff) - goto fail; - - /* - * 4-byte sequence (surrogate pairs, currently rare): - * 11101110wwwwzzzzyy + 110111yyyyxxxxxx - * = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx - * (uuuuu = wwww + 1) - * FIXME accept the surrogate code points (only) - */ - } else - goto fail; - } else - uchar = c; - put_unaligned_le16(uchar, cp++); - count++; - len--; - } - return count; -fail: - return -1; -} - +#include /** * usb_gadget_get_string - fill out a string descriptor diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 90b2f78ec7d..c9fba77eec5 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -85,6 +85,22 @@ config USB_XHCI_FSL depends on !SPL_NO_USB help Enables support for the on-chip xHCI controller on NXP Layerscape SoCs. + +config USB_XHCI_IMX8 + bool "XHCI support for imx8" + depends on ARCH_IMX8 + default y + help + Enables support for the on-chip xHCI controller on imx8qm and + imx8qxp SoCs. + +config USB_XHCI_IMX8M + bool "XHCI support for imx8M(mscale)" + depends on ARCH_IMX8M + default y + help + Enables support for the on-chip xHCI controller on imx8m(mscale) SoC. + endif # USB_XHCI_HCD config USB_EHCI_HCD @@ -125,14 +141,14 @@ config USB_EHCI_MARVELL config USB_EHCI_MX6 bool "Support for i.MX6 on-chip EHCI USB controller" - depends on ARCH_MX6 + depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMX8 default y ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs. config USB_EHCI_MX7 bool "Support for i.MX7 on-chip EHCI USB controller" - depends on ARCH_MX7 + depends on ARCH_MX7 || IMX8MM default y ---help--- Enables support for the on-chip EHCI controller on i.MX7 SoCs. @@ -145,7 +161,7 @@ config USB_EHCI_OMAP Enables support for the on-chip EHCI controller on OMAP3 and later SoCs. -if USB_EHCI_MX7 +if USB_EHCI_MX7 || USB_EHCI_MX6 config MXC_USB_OTG_HACTIVE bool "USB Power pin high active" diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 7f9ba24cfe7..bce7c612c09 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -60,6 +60,8 @@ obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o +obj-$(CONFIG_USB_XHCI_IMX8) += xhci-imx8.o +obj-$(CONFIG_USB_XHCI_IMX8M) += xhci-imx8m.o # designware obj-$(CONFIG_USB_DWC2) += dwc2.o diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 2c8fc3c4b15..f03dc9df8e0 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -1,6 +1,7 @@ /* * Copyright (c) 2009 Daniel Mack * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -19,8 +20,12 @@ #include #include #include +#include #include "ehci.h" +#if CONFIG_IS_ENABLED(POWER_DOMAIN) +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -60,14 +65,24 @@ DECLARE_GLOBAL_DATA_PTR; #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ +#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6) +#define PLL_USB_PWR_MASK (0x01 << 12) +#define PLL_USB_ENABLE_MASK (0x01 << 13) +#define PLL_USB_BYPASS_MASK (0x01 << 16) +#define PLL_USB_REG_ENABLE_MASK (0x01 << 21) +#define PLL_USB_DIV_SEL_MASK (0x07 << 22) +#define PLL_USB_LOCK_MASK (0x01 << 31) + /* USBCMD */ #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ #define UCMD_RESET (1 << 1) /* controller reset */ -#if defined(CONFIG_MX6) -static const unsigned phy_bases[] = { +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8) +static const ulong phy_bases[] = { USB_PHY0_BASE_ADDR, +#if defined(USB_PHY1_BASE_ADDR) USB_PHY1_BASE_ADDR, +#endif }; static void usb_internal_phy_clock_gate(int index, int on) @@ -84,6 +99,67 @@ static void usb_internal_phy_clock_gate(int index, int on) static void usb_power_config(int index) { +#if defined(CONFIG_MX7ULP) + struct usbphy_regs __iomem *usbphy = + (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR; + + if (index > 0) + return; + + writel(ANADIG_USB2_CHRG_DETECT_EN_B | + ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, + &usbphy->usb1_chrg_detect); + + scg_enable_usb_pll(true); + +#elif defined(CONFIG_IMX8) + struct usbphy_regs __iomem *usbphy = + (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR; + int timeout = 1000000; + + if (index > 0) + return; + + writel(ANADIG_USB2_CHRG_DETECT_EN_B | + ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, + &usbphy->usb1_chrg_detect); + + if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) { + + /* Enable the regulator first */ + writel(PLL_USB_REG_ENABLE_MASK, + &usbphy->usb1_pll_480_ctrl_set); + + /* Wait at least 25us */ + udelay(25); + + /* Enable the power */ + writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set); + + /* Wait lock */ + while (timeout--) { + if (readl(&usbphy->usb1_pll_480_ctrl) & + PLL_USB_LOCK_MASK) + break; + udelay(10); + } + + if (timeout <= 0) { + /* If timeout, we power down the pll */ + writel(PLL_USB_PWR_MASK, + &usbphy->usb1_pll_480_ctrl_clr); + return; + } + } + + /* Clear the bypass */ + writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr); + + /* Enable the PLL clock out to USB */ + writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK), + &usbphy->usb1_pll_480_ctrl_set); + +#else struct anatop_regs __iomem *anatop = (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; void __iomem *chrg_detect; @@ -123,6 +199,8 @@ static void usb_power_config(int index) ANADIG_USB2_PLL_480_CTRL_POWER | ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, pll_480_ctrl_set); + +#endif } /* Return 0 : host node, <>0 : device mode */ @@ -185,6 +263,28 @@ int usb_phy_mode(int port) return USB_INIT_HOST; } +#if defined(CONFIG_MX7ULP) +struct usbnc_regs { + u32 ctrl1; + u32 ctrl2; + u32 reserve0[2]; + u32 hsic_ctrl; +}; +#elif defined(CONFIG_IMX8) +struct usbnc_regs { + u32 ctrl1; + u32 ctrl2; + u32 reserve1[10]; + u32 phy_cfg1; + u32 phy_cfg2; + u32 reserve2; + u32 phy_status; + u32 reserve3[4]; + u32 adp_cfg1; + u32 adp_cfg2; + u32 adp_status; +}; +#else /* Base address for this IP block is 0x02184800 */ struct usbnc_regs { u32 ctrl[4]; /* otg/host1-3 */ @@ -193,7 +293,9 @@ struct usbnc_regs { u32 otg_phy_ctrl_0; u32 uh1_phy_ctrl_0; }; -#elif defined(CONFIG_MX7) +#endif + +#elif defined(CONFIG_USB_EHCI_MX7) struct usbnc_regs { u32 ctrl1; u32 ctrl2; @@ -210,28 +312,20 @@ struct usbnc_regs { static void usb_power_config(int index) { - struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + + struct usbnc_regs *usbnc = (struct usbnc_regs *)(ulong)(USB_BASE_ADDR + (0x10000 * index) + USBNC_OFFSET); void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); - void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); /* * Clear the ACAENB to enable usb_otg_id detection, * otherwise it is the ACA detection enabled. */ clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); - - /* Set power polarity to high active */ -#ifdef CONFIG_MXC_USB_OTG_HACTIVE - setbits_le32(ctrl, UCTRL_PWR_POL); -#else - clrbits_le32(ctrl, UCTRL_PWR_POL); -#endif } int usb_phy_mode(int port) { - struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + + struct usbnc_regs *usbnc = (struct usbnc_regs *)(ulong)(USB_BASE_ADDR + (0x10000 * port) + USBNC_OFFSET); void __iomem *status = (void __iomem *)(&usbnc->phy_status); u32 val; @@ -245,14 +339,33 @@ int usb_phy_mode(int port) } #endif +static void ehci_mx6_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, + uint32_t *reg) +{ + uint32_t result; + int usec = 2000; + + mdelay(50); + + do { + result = ehci_readl(status_reg); + udelay(5); + if (!(result & EHCI_PS_PR)) + break; + usec--; + } while (usec > 0); + + *reg = ehci_readl(status_reg); +} + static void usb_oc_config(int index) { #if defined(CONFIG_MX6) struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET); void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); -#elif defined(CONFIG_MX7) - struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + +#elif defined(CONFIG_USB_EHCI_MX7) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8) + struct usbnc_regs *usbnc = (struct usbnc_regs *)(ulong)(USB_BASE_ADDR + (0x10000 * index) + USBNC_OFFSET); void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); #endif @@ -265,6 +378,13 @@ static void usb_oc_config(int index) #endif setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); + + /* Set power polarity to high active */ +#ifdef CONFIG_MXC_USB_OTG_HACTIVE + setbits_le32(ctrl, UCTRL_PWR_POL); +#else + clrbits_le32(ctrl, UCTRL_PWR_POL); +#endif } /** @@ -316,10 +436,17 @@ int __weak board_ehci_power(int port, int on) int ehci_mx6_common_init(struct usb_ehci *ehci, int index) { int ret; + u32 portsc; enable_usboh3_clk(1); mdelay(1); + portsc = readl(&ehci->portsc); + if (portsc & PORT_PTS_PHCD) { + debug("suspended: portsc %x, enabled it.\n", portsc); + clrbits_le32(&ehci->portsc, PORT_PTS_PHCD); + } + /* Do board specific initialization */ ret = board_ehci_hcd_init(index); if (ret) @@ -328,7 +455,7 @@ int ehci_mx6_common_init(struct usb_ehci *ehci, int index) usb_power_config(index); usb_oc_config(index); -#if defined(CONFIG_MX6) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8) usb_internal_phy_clock_gate(index, 1); usb_phy_enable(index, ehci); #endif @@ -337,31 +464,44 @@ int ehci_mx6_common_init(struct usb_ehci *ehci, int index) } #ifndef CONFIG_DM_USB +static const struct ehci_ops mx6_ehci_ops = { + .powerup_fixup = ehci_mx6_powerup_fixup, +}; + int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { enum usb_init_type type; #if defined(CONFIG_MX6) u32 controller_spacing = 0x200; -#elif defined(CONFIG_MX7) +#elif defined(CONFIG_USB_EHCI_MX7) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8) u32 controller_spacing = 0x10000; #endif - struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + + struct usb_ehci *ehci = (struct usb_ehci *)(ulong)(USB_BASE_ADDR + (controller_spacing * index)); int ret; if (index > 3) return -EINVAL; +#if defined(CONFIG_MX6) + if (mx6_usb_fused((u32)ehci)) { + printf("USB@0x%x is fused, disable it\n", (u32)ehci); + return -ENODEV; + } +#endif + ret = ehci_mx6_common_init(ehci, index); if (ret) return ret; + ehci_set_controller_priv(index, NULL, &mx6_ehci_ops); + type = board_usb_phy_mode(index); if (hccr && hcor) { - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t)*hccr + + *hccr = (struct ehci_hccr *)((ulong)&ehci->caplength); + *hcor = (struct ehci_hcor *)((ulong)*hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); } @@ -386,11 +526,14 @@ int ehci_hcd_stop(int index) return 0; } #else +#define USB_INIT_UNKNOWN (USB_INIT_DEVICE + 1) + struct ehci_mx6_priv_data { struct ehci_ctrl ctrl; struct usb_ehci *ehci; struct udevice *vbus_supply; enum usb_init_type init_type; + void *__iomem phy_base; int portnr; }; @@ -401,6 +544,12 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) struct usb_ehci *ehci = priv->ehci; int ret; + ret = board_usb_init(priv->portnr, priv->init_type); + if (ret) { + printf("Failed to initialize board for USB\n"); + return ret; + } + ret = ehci_mx6_common_init(priv->ehci, priv->portnr); if (ret) return ret; @@ -428,23 +577,71 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) } static const struct ehci_ops mx6_ehci_ops = { - .init_after_reset = mx6_init_after_reset + .powerup_fixup = ehci_mx6_powerup_fixup, + .init_after_reset = mx6_init_after_reset }; +/** + * board_ehci_usb_phy_mode - override usb phy mode + * @port: usb host/otg port + * + * Target board specific, override usb_phy_mode. + * When usb-otg is used as usb host port, iomux pad usb_otg_id can be + * left disconnected in this case usb_phy_mode will not be able to identify + * the phy mode that usb port is used. + * Machine file overrides board_usb_phy_mode. + * When the extcon property is set in DTB, machine must provide this function, otherwise + * it will default return HOST. + * + * Return: USB_INIT_DEVICE or USB_INIT_HOST + */ +int __weak board_ehci_usb_phy_mode(struct udevice *dev) +{ + return USB_INIT_HOST; +} + static int ehci_usb_phy_mode(struct udevice *dev) { - struct usb_platdata *plat = dev_get_platdata(dev); - void *__iomem addr = (void *__iomem)devfdt_get_addr(dev); + struct ehci_mx6_priv_data *priv = dev_get_priv(dev); void *__iomem phy_ctrl, *__iomem phy_status; + u32 val; + + if (is_mx6() || is_mx7ulp() || is_imx8()) { + phy_ctrl = (void __iomem *)(priv->phy_base + USBPHY_CTRL); + val = readl(phy_ctrl); + + if (val & USBPHY_CTRL_OTG_ID) + priv->init_type = USB_INIT_DEVICE; + else + priv->init_type = USB_INIT_HOST; + } else if (is_mx7() || is_imx8mm()) { + phy_status = (void __iomem *)(priv->phy_base + + USBNC_PHY_STATUS_OFFSET); + val = readl(phy_status); + + if (val & USBNC_PHYSTATUS_ID_DIG) + priv->init_type = USB_INIT_DEVICE; + else + priv->init_type = USB_INIT_HOST; + } else { + return -EINVAL; + } + + return 0; +} + +static int ehci_get_usb_phy(struct udevice *dev) +{ + struct ehci_mx6_priv_data *priv = dev_get_priv(dev); + void *__iomem addr = (void *__iomem)devfdt_get_addr(dev); const void *blob = gd->fdt_blob; int offset = dev_of_offset(dev), phy_off; - u32 val; /* * About fsl,usbphy, Refer to * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt. */ - if (is_mx6()) { + if (is_mx6() || is_mx7ulp() || is_imx8()) { phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy"); @@ -456,22 +653,20 @@ static int ehci_usb_phy_mode(struct udevice *dev) if ((fdt_addr_t)addr == FDT_ADDR_T_NONE) return -EINVAL; - phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL); - val = readl(phy_ctrl); + /* Need to power on the PHY before access it */ +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + struct udevice phy_dev; + struct power_domain pd; - if (val & USBPHY_CTRL_OTG_ID) - plat->init_type = USB_INIT_DEVICE; - else - plat->init_type = USB_INIT_HOST; - } else if (is_mx7()) { - phy_status = (void __iomem *)(addr + - USBNC_PHY_STATUS_OFFSET); - val = readl(phy_status); - - if (val & USBNC_PHYSTATUS_ID_DIG) - plat->init_type = USB_INIT_DEVICE; - else - plat->init_type = USB_INIT_HOST; + phy_dev.node = offset_to_ofnode(phy_off); + if (!power_domain_get(&phy_dev, &pd)) { + if (power_domain_on(&pd)) + return -EINVAL; + } +#endif + priv->phy_base = addr; + } else if (is_mx7() || is_imx8mm()) { + priv->phy_base = addr; } else { return -EINVAL; } @@ -482,23 +677,36 @@ static int ehci_usb_phy_mode(struct udevice *dev) static int ehci_usb_ofdata_to_platdata(struct udevice *dev) { struct usb_platdata *plat = dev_get_platdata(dev); + struct ehci_mx6_priv_data *priv = dev_get_priv(dev); const char *mode; + const struct fdt_property *extcon; mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL); if (mode) { if (strcmp(mode, "peripheral") == 0) - plat->init_type = USB_INIT_DEVICE; + priv->init_type = USB_INIT_DEVICE; else if (strcmp(mode, "host") == 0) - plat->init_type = USB_INIT_HOST; + priv->init_type = USB_INIT_HOST; else if (strcmp(mode, "otg") == 0) - return ehci_usb_phy_mode(dev); + priv->init_type = USB_INIT_UNKNOWN; else return -EINVAL; + } else { + extcon = fdt_get_property(gd->fdt_blob, dev_of_offset(dev), + "extcon", NULL); + if (extcon) + priv->init_type = board_ehci_usb_phy_mode(dev); + else + priv->init_type = USB_INIT_UNKNOWN; + } - return 0; + if (priv->init_type != USB_INIT_UNKNOWN && priv->init_type != plat->init_type) { + debug("Request USB type is %u, board forced type is %u\n", + plat->init_type, priv->init_type); + return -ENODEV; } - return ehci_usb_phy_mode(dev); + return 0; } static int ehci_usb_probe(struct udevice *dev) @@ -511,22 +719,50 @@ static int ehci_usb_probe(struct udevice *dev) struct ehci_hcor *hcor; int ret; +#if defined(CONFIG_MX6) + if (mx6_usb_fused((u32)ehci)) { + printf("USB@0x%x is fused, disable it\n", (u32)ehci); + return -ENODEV; + } +#endif + priv->ehci = ehci; priv->portnr = dev->seq; - priv->init_type = type; + + /* Init usb board level according to the requested init type */ + ret = board_usb_init(priv->portnr, type); + if (ret) { + printf("Failed to initialize board for USB\n"); + return ret; + } ret = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_supply); if (ret) debug("%s: No vbus supply\n", dev->name); + ret = ehci_get_usb_phy(dev); + if (ret) { + debug("%s: fail to get USB PHY base\n", dev->name); + return ret; + } + ret = ehci_mx6_common_init(ehci, priv->portnr); if (ret) return ret; + /* If the init_type is unknown due to it is not forced in DTB, we use USB ID to detect */ + if (priv->init_type == USB_INIT_UNKNOWN) { + ret = ehci_usb_phy_mode(dev); + if (ret) + return ret; + if (priv->init_type != type) + return -ENODEV; + } + if (priv->vbus_supply) { ret = regulator_set_enable(priv->vbus_supply, - (type == USB_INIT_DEVICE) ? + (priv->init_type == USB_INIT_DEVICE) ? false : true); if (ret) { puts("Error enabling VBUS supply\n"); @@ -542,13 +778,25 @@ static int ehci_usb_probe(struct udevice *dev) mdelay(10); - hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - hcor = (struct ehci_hcor *)((uint32_t)hccr + + hccr = (struct ehci_hccr *)((ulong)&ehci->caplength); + hcor = (struct ehci_hcor *)((ulong)hccr + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type); } +int ehci_usb_remove(struct udevice *dev) +{ + struct ehci_mx6_priv_data *priv = dev_get_priv(dev); + struct usb_platdata *plat = dev_get_platdata(dev); + + ehci_deregister(dev); + + plat->init_type = 0; /* Clean the requested usb type to host mode */ + + return board_usb_cleanup(dev->seq, priv->init_type); +} + static const struct udevice_id mx6_usb_ids[] = { { .compatible = "fsl,imx27-usb" }, { } @@ -560,7 +808,7 @@ U_BOOT_DRIVER(usb_mx6) = { .of_match = mx6_usb_ids, .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, .probe = ehci_usb_probe, - .remove = ehci_deregister, + .remove = ehci_usb_remove, .ops = &ehci_usb_ops, .platdata_auto_alloc_size = sizeof(struct usb_platdata), .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data), diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 4e40f4bc3d2..2979212c9fc 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -405,6 +405,24 @@ int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp) return 0; } +int usb_remove_ehci_gadget(struct ehci_ctrl **ctlrp) +{ + struct udevice *dev; + int ret; + + /* Find the old device and remove it */ + ret = uclass_find_device_by_seq(UCLASS_USB, 0, true, &dev); + if (ret) + return ret; + ret = device_remove(dev, DM_REMOVE_NORMAL); + if (ret) + return ret; + + *ctlrp = NULL; + + return 0; +} + /* returns 0 if no match, 1 if match */ static int usb_match_device(const struct usb_device_descriptor *desc, const struct usb_device_id *id) diff --git a/drivers/usb/host/xhci-imx8.c b/drivers/usb/host/xhci-imx8.c new file mode 100644 index 00000000000..3065060e152 --- /dev/null +++ b/drivers/usb/host/xhci-imx8.c @@ -0,0 +1,270 @@ +/* + * Copyright 2017 NXP + * + * NXP i.MX8 USB HOST xHCI Controller (Cadence IP) + * + * Author: Peter Chen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "xhci.h" +#include +#include +#include +#include + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +/* According to UG CH 3.1.1 Bring-up Sequence */ +static void imx_usb3_phy_init(void) +{ + writel(0x0830, PHY_PMA_CMN_CTRL1); + writel(0x10, TB_ADDR_CMN_DIAG_HSCLK_SEL); + writel(0x00F0, TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR); + writel(0x0018, TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR); + writel(0x00D0, TB_ADDR_CMN_PLL0_INTDIV); + writel(0x4aaa, TB_ADDR_CMN_PLL0_FRACDIV); + writel(0x0034, TB_ADDR_CMN_PLL0_HIGH_THR); + writel(0x1ee, TB_ADDR_CMN_PLL0_SS_CTRL1); + writel(0x7F03, TB_ADDR_CMN_PLL0_SS_CTRL2); + writel(0x0020, TB_ADDR_CMN_PLL0_DSM_DIAG); + writel(0x0000, TB_ADDR_CMN_DIAG_PLL0_OVRD); + writel(0x0000, TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD); + writel(0x0000, TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD); + writel(0x0007, TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE); + writel(0x0027, TB_ADDR_CMN_DIAG_PLL0_CP_TUNE); + writel(0x0008, TB_ADDR_CMN_DIAG_PLL0_LF_PROG); + writel(0x0022, TB_ADDR_CMN_DIAG_PLL0_TEST_MODE); + writel(0x000a, TB_ADDR_CMN_PSM_CLK_CTRL); + writel(0x139, TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR); + writel(0xbefc, TB_ADDR_XCVR_PSM_RCTRL); + + writel(0x7799, TB_ADDR_TX_PSC_A0); + writel(0x7798, TB_ADDR_TX_PSC_A1); + writel(0x509b, TB_ADDR_TX_PSC_A2); + writel(0x3, TB_ADDR_TX_DIAG_ECTRL_OVRD); + writel(0x5098, TB_ADDR_TX_PSC_A3); + writel(0x2090, TB_ADDR_TX_PSC_CAL); + writel(0x2090, TB_ADDR_TX_PSC_RDY); + + writel(0xA6FD, TB_ADDR_RX_PSC_A0); + writel(0xA6FD, TB_ADDR_RX_PSC_A1); + writel(0xA410, TB_ADDR_RX_PSC_A2); + writel(0x2410, TB_ADDR_RX_PSC_A3); + + writel(0x23FF, TB_ADDR_RX_PSC_CAL); + writel(0x2010, TB_ADDR_RX_PSC_RDY); + + writel(0x0020, TB_ADDR_TX_TXCC_MGNLS_MULT_000); + writel(0x00ff, TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY); + writel(0x0002, TB_ADDR_RX_SLC_CU_ITER_TMR); + writel(0x0013, TB_ADDR_RX_SIGDET_HL_FILT_TMR); + writel(0x0000, TB_ADDR_RX_SAMP_DAC_CTRL); + writel(0x1004, TB_ADDR_RX_DIAG_SIGDET_TUNE); + writel(0x4041, TB_ADDR_RX_DIAG_LFPSDET_TUNE2); + writel(0x0480, TB_ADDR_RX_DIAG_BS_TM); + writel(0x8006, TB_ADDR_RX_DIAG_DFE_CTRL1); + writel(0x003f, TB_ADDR_RX_DIAG_ILL_IQE_TRIM4); + writel(0x543f, TB_ADDR_RX_DIAG_ILL_E_TRIM0); + writel(0x543f, TB_ADDR_RX_DIAG_ILL_IQ_TRIM0); + writel(0x0000, TB_ADDR_RX_DIAG_ILL_IQE_TRIM6); + writel(0x8000, TB_ADDR_RX_DIAG_RXFE_TM3); + writel(0x0003, TB_ADDR_RX_DIAG_RXFE_TM4); + writel(0x2408, TB_ADDR_RX_DIAG_LFPSDET_TUNE); + writel(0x05ca, TB_ADDR_RX_DIAG_DFE_CTRL3); + writel(0x0258, TB_ADDR_RX_DIAG_SC2C_DELAY); + writel(0x1fff, TB_ADDR_RX_REE_VGA_GAIN_NODFE); + + writel(0x02c6, TB_ADDR_XCVR_PSM_CAL_TMR); + writel(0x0002, TB_ADDR_XCVR_PSM_A0BYP_TMR); + writel(0x02c6, TB_ADDR_XCVR_PSM_A0IN_TMR); + writel(0x0010, TB_ADDR_XCVR_PSM_A1IN_TMR); + writel(0x0010, TB_ADDR_XCVR_PSM_A2IN_TMR); + writel(0x0010, TB_ADDR_XCVR_PSM_A3IN_TMR); + writel(0x0010, TB_ADDR_XCVR_PSM_A4IN_TMR); + writel(0x0010, TB_ADDR_XCVR_PSM_A5IN_TMR); + + writel(0x0002, TB_ADDR_XCVR_PSM_A0OUT_TMR); + writel(0x0002, TB_ADDR_XCVR_PSM_A1OUT_TMR); + writel(0x0002, TB_ADDR_XCVR_PSM_A2OUT_TMR); + writel(0x0002, TB_ADDR_XCVR_PSM_A3OUT_TMR); + writel(0x0002, TB_ADDR_XCVR_PSM_A4OUT_TMR); + writel(0x0002, TB_ADDR_XCVR_PSM_A5OUT_TMR); + + /* Change rx detect parameter */ + writel(0x960, TB_ADDR_TX_RCVDET_EN_TMR); + writel(0x01e0, TB_ADDR_TX_RCVDET_ST_TMR); + writel(0x0090, TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR); + + udelay(10); + + /* force rx detect */ +/* writel(0xc000, TB_ADDR_TX_RCVDET_OVRD); */ +} + +void imx8_xhci_init(void) +{ + u32 tmp_data; + + tmp_data = readl(USB3_SSPHY_STATUS); + writel(tmp_data, USB3_SSPHY_STATUS); + tmp_data = readl(USB3_SSPHY_STATUS); + while ((tmp_data & 0xf0000000) != 0xf0000000) { + printf("clkvld is incorrect = 0x%x\n", tmp_data); + udelay(10); + tmp_data = readl(USB3_SSPHY_STATUS); + } + + tmp_data = readl(USB3_CORE_CTRL1); + tmp_data = (tmp_data & 0xfffffff8) | 0x202; + writel(tmp_data, USB3_CORE_CTRL1); + tmp_data &= ~0x04000000; /* clear PHY apb reset */ + writel(tmp_data, USB3_CORE_CTRL1); + imx_usb3_phy_init(); + + tmp_data = readl(USB3_CORE_CTRL1); + tmp_data &= ~0xfc000000; /* clear all sw_rst */ + writel(tmp_data, USB3_CORE_CTRL1); + + debug("wait xhci_power_on_ready\n"); + tmp_data = readl(USB3_CORE_STATUS); + while (!(tmp_data & 0x1000)) + tmp_data = readl(USB3_CORE_STATUS); + + debug("xhci_power_on_ready\n"); + + tmp_data = readl(USBSTS); + debug("waiting CNR 0x%x\n", tmp_data); + while (tmp_data & 0x800) + tmp_data = readl(USBSTS); + + debug("check CNR has finished\n"); +} + +void imx8_xhci_reset(void) +{ + /* Set CORE ctrl to default value, that all rst are hold */ + writel(0xfc000001, USB3_CORE_CTRL1); +} + + +#ifdef CONFIG_DM_USB +static int xhci_imx8_probe(struct udevice *dev) +{ + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + + int ret = 0; + int len; + + /* Need to power on the PHY before access it */ +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + struct udevice phy_dev; + struct power_domain pd; + const void *blob = gd->fdt_blob; + int offset = dev_of_offset(dev), phy_off; + + phy_off = fdtdec_lookup_phandle(blob, + offset, + "fsl,usbphy"); + if (phy_off < 0) + return -EINVAL; + + phy_dev.node = offset_to_ofnode(phy_off); + if (!power_domain_get(&phy_dev, &pd)) { + if (power_domain_on(&pd)) + return -EINVAL; + } +#endif + + ret = board_usb_init(dev->seq, USB_INIT_HOST); + if (ret != 0) { + printf("Failed to initialize board for USB\n"); + return ret; + } + + init_clk_usb3(dev->seq); + + imx8_xhci_init(); + + hccr = (struct xhci_hccr *)HCIVERSION_CAPLENGTH; + len = HC_LENGTH(xhci_readl(&hccr->cr_capbase)); + hcor = (struct xhci_hcor *)((uintptr_t) hccr + len); + + printf("XHCI-imx8 init hccr 0x%p and hcor 0x%p hc_length %d\n", + (uint32_t *)hccr, (uint32_t *)hcor, len); + + return xhci_register(dev, hccr, hcor); +} + +static int xhci_imx8_remove(struct udevice *dev) +{ + int ret = xhci_deregister(dev); + if (!ret) + imx8_xhci_reset(); + + board_usb_cleanup(dev->seq, USB_INIT_HOST); + + return ret; +} + +static const struct udevice_id xhci_usb_ids[] = { + { .compatible = "fsl,imx8-usb3", }, + { } +}; + +U_BOOT_DRIVER(xhci_imx8) = { + .name = "xhci_imx8", + .id = UCLASS_USB, + .of_match = xhci_usb_ids, + .probe = xhci_imx8_probe, + .remove = xhci_imx8_remove, + .ops = &xhci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct xhci_ctrl), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#else +int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, + struct xhci_hcor **ret_hcor) +{ + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + int len, ret; + + ret = board_usb_init(index, USB_INIT_HOST); + if (ret != 0) { + printf("Failed to initialize board for USB\n"); + return ret; + } + + init_clk_usb3(index); + + imx8_xhci_init(); + + hccr = (struct xhci_hccr *)HCIVERSION_CAPLENGTH; + len = HC_LENGTH(xhci_readl(&hccr->cr_capbase)); + hcor = (struct xhci_hcor *)((uintptr_t) hccr + len); + + printf("XHCI-imx8 init hccr 0x%p and hcor 0x%p hc_length %d\n", + (uint32_t *)hccr, (uint32_t *)hcor, len); + + *ret_hccr = hccr; + *ret_hcor = hcor; + + return 0; +} + +void xhci_hcd_stop(int index) +{ + imx8_xhci_reset(); + + board_usb_cleanup(index, USB_INIT_HOST); +} +#endif diff --git a/drivers/usb/host/xhci-imx8m.c b/drivers/usb/host/xhci-imx8m.c new file mode 100644 index 00000000000..bba84873fa7 --- /dev/null +++ b/drivers/usb/host/xhci-imx8m.c @@ -0,0 +1,216 @@ +/* + * Copyright 2017 NXP + * + * FSL i.MX8M USB HOST xHCI Controller + * + * Author: Jun Li + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "xhci.h" + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +#define USBMIX_PHY_OFFSET 0xF0040 + +#define PHY_CTRL0_REF_SSP_EN BIT(2) + +#define PHY_CTRL1_RESET BIT(0) +#define PHY_CTRL1_ATERESET BIT(3) +#define PHY_CTRL1_VDATSRCENB0 BIT(19) +#define PHY_CTRL1_VDATDETENB0 BIT(20) + +#define PHY_CTRL2_TXENABLEN0 BIT(8) + +struct imx8m_usbmix { + u32 phy_ctrl0; + u32 phy_ctrl1; + u32 phy_ctrl2; + u32 phy_ctrl3; +}; + +struct imx8m_xhci { + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; + struct imx8m_usbmix *usbmix_reg; +}; + +struct imx8m_usbctrl_data { + u32 usb_id; + unsigned long ctr_addr; +}; +static struct imx8m_xhci imx8m_xhci; +static struct imx8m_usbctrl_data ctr_data[] = { + {0, USB1_BASE_ADDR}, + {1, USB2_BASE_ADDR}, +}; + +static void imx8m_usb_phy_init(struct imx8m_usbmix *usbmix_reg) +{ + u32 reg; + + reg = readl(&usbmix_reg->phy_ctrl1); + reg &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0); + reg |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET; + writel(reg, &usbmix_reg->phy_ctrl1); + + reg = readl(&usbmix_reg->phy_ctrl0); + reg |= PHY_CTRL0_REF_SSP_EN; + writel(reg, &usbmix_reg->phy_ctrl0); + + reg = readl(&usbmix_reg->phy_ctrl2); + reg |= PHY_CTRL2_TXENABLEN0; + writel(reg, &usbmix_reg->phy_ctrl2); + + reg = readl(&usbmix_reg->phy_ctrl1); + reg &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET); + writel(reg, &usbmix_reg->phy_ctrl1); +} + +static void imx8m_xhci_set_suspend_clk(struct dwc3 *dwc3_reg) +{ + u32 reg; + + /* Set suspend_clk to be 32KHz */ + reg = readl(&dwc3_reg->g_ctl); + reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); + reg |= DWC3_GCTL_PWRDNSCALE(2); + + writel(reg, &dwc3_reg->g_ctl); +} + +static int imx8m_xhci_core_init(struct imx8m_xhci *imx8m_xhci) +{ + int ret = 0; + + imx8m_usb_phy_init(imx8m_xhci->usbmix_reg); + + ret = dwc3_core_init(imx8m_xhci->dwc3_reg); + if (ret) { + debug("%s:failed to initialize core\n", __func__); + return ret; + } + + imx8m_xhci_set_suspend_clk(imx8m_xhci->dwc3_reg); + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(imx8m_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */ + dwc3_set_fladj(imx8m_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT); + + return ret; +} + +#ifdef CONFIG_DM_USB +static int xhci_imx8m_probe(struct udevice *dev) +{ + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + struct imx8m_xhci *ctx = &imx8m_xhci; + int ret = 0; + + ctx->hcd = (struct xhci_hccr *)(ctr_data[dev->seq].ctr_addr); + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); + ctx->usbmix_reg = (struct imx8m_usbmix *)((char *)(ctx->hcd) + + USBMIX_PHY_OFFSET); + + ret = board_usb_init(ctr_data[dev->seq].usb_id, USB_INIT_HOST); + if (ret != 0) { + imx8m_usb_power(ctr_data[dev->seq].usb_id, false); + puts("Failed to initialize board for imx8m USB\n"); + return ret; + } + + ret = imx8m_xhci_core_init(ctx); + if (ret < 0) { + puts("Failed to initialize imx8m xhci\n"); + return ret; + } + + hccr = (struct xhci_hccr *)ctx->hcd; + hcor = (struct xhci_hcor *)((uintptr_t) hccr + + HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); + + debug("imx8m-xhci: init hccr %lx and hcor %lx hc_length %lx\n", + (uintptr_t)hccr, (uintptr_t)hcor, + (uintptr_t)HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); + + return xhci_register(dev, hccr, hcor); +} + +static int xhci_imx8m_remove(struct udevice *dev) +{ + int ret = xhci_deregister(dev); + + board_usb_cleanup(dev->seq, USB_INIT_HOST); + + return ret; +} + +static const struct udevice_id xhci_usb_ids[] = { + { .compatible = "fsl, imx8mq-dwc3", }, + { } +}; + +U_BOOT_DRIVER(xhci_imx8m) = { + .name = "xhci_imx8m", + .id = UCLASS_USB, + .of_match = xhci_usb_ids, + .probe = xhci_imx8m_probe, + .remove = xhci_imx8m_remove, + .ops = &xhci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct xhci_ctrl), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +#else +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + struct imx8m_xhci *ctx = &imx8m_xhci; + int ret = 0; + + ctx->hcd = (struct xhci_hccr *)(ctr_data[index].ctr_addr); + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); + ctx->usbmix_reg = (struct imx8m_usbmix *)((char *)(ctx->hcd) + + USBMIX_PHY_OFFSET); + + ret = board_usb_init(ctr_data[index].usb_id, USB_INIT_HOST); + if (ret != 0) { + imx8m_usb_power(ctr_data[index].usb_id, false); + puts("Failed to initialize board for imx8m USB\n"); + return ret; + } + + ret = imx8m_xhci_core_init(ctx); + if (ret < 0) { + puts("Failed to initialize imx8m xhci\n"); + return ret; + } + + *hccr = (struct xhci_hccr *)ctx->hcd; + *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + debug("imx8m-xhci: init hccr %lx and hcor %lx hc_length %lx\n", + (uintptr_t)*hccr, (uintptr_t)*hcor, + (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + return ret; +} + +void xhci_hcd_stop(int index) +{ + board_usb_cleanup(ctr_data[index].usb_id, USB_INIT_HOST); +} +#endif diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 0582a9be40a..2f6abbf4480 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -370,6 +370,8 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) ctrl->dcbaa->dev_context_ptrs[0] = cpu_to_le64((uintptr_t)scratchpad->sp_array); + xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[0], sizeof(__le64)); + page_size = xhci_readl(&hcor->or_pagesize) & 0xffff; for (i = 0; i < 16; i++) { if ((0x1 & page_size) != 0) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2fc0defcd0d..57d21d625aa 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -513,6 +513,70 @@ config VIDEO_IPUV3 This enables framebuffer driver for i.MX processors working on the IPUv3(Image Processing Unit) internal graphic processor. +config VIDEO_IMXDPUV1 + bool "i.MX DPU V1 display support" + default n + depends on VIDEO && IMX8 + help + Support for IMXDPU V1 display controller for i.MX8 processors. + +config VIDEO_IMXDCSS + bool "i.MX8 DCSS display support" + default n + depends on VIDEO && IMX8M + help + Support for DCSS display controller for i.MX8 processors. + +config VIDEO_IMX_HDP_LOAD + bool "i.MX8 HDMI/DP firmware loading" + default n + depends on VIDEO && IMX8QM + help + Support for HDMI/DP firmware loading for i.MX8QM processors. The + firmware is copied from system memory to the HDMI/DP IRAM and + DRAM memory. + +config VIDEO_IMX8_HDMI + bool "i.MX8 HDMI Splash screen" + default n + depends on VIDEO && IMX8M + help + Support for HDMI i.MX8 processors. + +config IMX_MIPI_DSI_BRIDGE + bool + help + Enable MIPI DSI bridge interface for display controller. + +config IMX_NORTHWEST_MIPI_DSI + bool "i.MX northwest's MIPI DSI" + default n + select IMX_MIPI_DSI_BRIDGE + depends on VIDEO && MX7ULP + help + Support for i.MX7ULP MIPI DSI controller. + +config IMX_SEC_MIPI_DSI + bool "i.MX Samsung's MIPI DSI" + default n + select IMX_MIPI_DSI_BRIDGE + depends on VIDEO && (IMX8MM || MX7) + help + Support for i.MX7 and i.MX8MM MIPI DSI controller. + +config MXC_EPDC + bool "i.MX EPDC support" + depends on LCD && (MX7 || MX6) + help + This enable the E-ink EPD panel controller support for i.MX processors + +config WAVEFORM_BUF_SIZE + bool "The buffer size allocated for i.MX EPDC waveform file" + depends on MXC_EPDC + help + Set the buffer size for loading waveform file. + + config CFB_CONSOLE bool "Enable colour frame buffer console" depends on VIDEO diff --git a/drivers/video/Makefile b/drivers/video/Makefile index dfafe08fc50..d0d484c15ff 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o +obj-$(CONFIG_VIDEO_IMXDPUV1) += imxdpuv1.o obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o @@ -57,6 +58,18 @@ obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ obj-${CONFIG_EXYNOS_FB} += exynos/ obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/ obj-${CONFIG_VIDEO_STM32} += stm32/ +obj-$(CONFIG_MXC_EPDC) += mxc_epdc_fb.o +obj-$(CONFIG_VIDEO_VADC) += mxc_vadc.o +obj-$(CONFIG_VIDEO_CSI) += mxc_csi.o +obj-$(CONFIG_VIDEO_PXP) += mxc_pxp.o +obj-$(CONFIG_VIDEO_GIS) += mxc_gis.o +obj-$(CONFIG_IMX_NORTHWEST_MIPI_DSI) += mipi_dsi_northwest.o +obj-$(CONFIG_IMX_SEC_MIPI_DSI) += sec_mipi_dsim.o +obj-$(CONFIG_IMX_MIPI_DSI_BRIDGE) += imx_mipi_dsi_bridge.o +obj-$(CONFIG_HX8363) += hx8363_wvga.o +obj-$(CONFIG_RM67191) += rm67191.o +obj-$(CONFIG_RM68200) += rm68200.o obj-y += bridge/ obj-y += sunxi/ +obj-y += imx/ diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 0b258970620..917a5a95c58 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1177,7 +1177,7 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, y = __le32_to_cpu(img->header.height) - 1; ncolors = __le32_to_cpu(img->header.colors_used); bpp = VIDEO_PIXEL_SIZE; - fbp = (unsigned char *) ((unsigned int) video_fb_address + + fbp = (unsigned char *) ((unsigned long) video_fb_address + (y + yoff) * VIDEO_LINE_LEN + xoff * bpp); @@ -1232,7 +1232,7 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, x = 0; y--; fbp = (unsigned char *) - ((unsigned int) video_fb_address + + ((unsigned long) video_fb_address + (y + yoff) * VIDEO_LINE_LEN + xoff * bpp); continue; @@ -1245,7 +1245,7 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, x += bm[2]; y -= bm[3]; fbp = (unsigned char *) - ((unsigned int) video_fb_address + + ((unsigned long) video_fb_address + (y + yoff) * VIDEO_LINE_LEN + xoff * bpp); bm += 4; @@ -2020,7 +2020,7 @@ static int cfg_video_init(void) if (pGD == NULL) return -1; - video_fb_address = (void *) VIDEO_FB_ADRS; + video_fb_address = (void *)(unsigned long) VIDEO_FB_ADRS; cfb_do_flush_cache = cfb_fb_is_in_dram() && dcache_status(); diff --git a/drivers/video/hx8363_wvga.c b/drivers/video/hx8363_wvga.c new file mode 100644 index 00000000000..05f60612ddb --- /dev/null +++ b/drivers/video/hx8363_wvga.c @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define HX8363_TWO_DATA_LANE (0x2) +#define HX8363_MAX_DPHY_CLK (800) +#define HX8363_CMD_GETHXID (0xF4) +#define HX8363_CMD_GETHXID_LEN (0x4) +#define HX8363_ID (0x84) +#define HX8363_ID_MASK (0xFF) + + +#define CHECK_RETCODE(ret) \ +do { \ + if (ret < 0) { \ + printf("%s ERR: ret:%d, line:%d.\n", \ + __func__, ret, __LINE__); \ + return ret; \ + } \ +} while (0) + +static void parse_variadic(int n, u8 *buf, ...) +{ + int i = 0; + va_list args; + + if (unlikely(!n)) + return; + + va_start(args, buf); + + for (i = 0; i < n; i++) + buf[i + 1] = (u8)va_arg(args, int); + + va_end(args); +} + +#define TC358763_DCS_write_1A_nP(n, addr, ...) { \ + int err; \ + \ + buf[0] = addr; \ + parse_variadic(n, buf, ##__VA_ARGS__); \ + \ + if (n >= 2) \ + err = imx_mipi_dsi_bridge_pkt_write( \ + MIPI_DSI_DCS_LONG_WRITE, (u8 *)buf, n + 1); \ + else if (n == 1) \ + err = imx_mipi_dsi_bridge_pkt_write( \ + MIPI_DSI_DCS_SHORT_WRITE_PARAM, (u8 *)buf, 0); \ + else if (n == 0) { \ + buf[1] = 0; \ + err = imx_mipi_dsi_bridge_pkt_write( \ + MIPI_DSI_DCS_SHORT_WRITE, (u8 *)buf, 0); \ + } \ + CHECK_RETCODE(err); \ +} + +#define TC358763_DCS_write_1A_0P(addr) \ + TC358763_DCS_write_1A_nP(0, addr) + +#define TC358763_DCS_write_1A_1P(addr, ...) \ + TC358763_DCS_write_1A_nP(1, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_2P(addr, ...) \ + TC358763_DCS_write_1A_nP(2, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_3P(addr, ...) \ + TC358763_DCS_write_1A_nP(3, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_5P(addr, ...) \ + TC358763_DCS_write_1A_nP(5, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_6P(addr, ...) \ + TC358763_DCS_write_1A_nP(6, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_7P(addr, ...) \ + TC358763_DCS_write_1A_nP(7, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_12P(addr, ...) \ + TC358763_DCS_write_1A_nP(12, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_13P(addr, ...) \ + TC358763_DCS_write_1A_nP(13, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_14P(addr, ...) \ + TC358763_DCS_write_1A_nP(14, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_19P(addr, ...) \ + TC358763_DCS_write_1A_nP(19, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_34P(addr, ...) \ + TC358763_DCS_write_1A_nP(34, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_127P(addr, ...) \ + TC358763_DCS_write_1A_nP(127, addr, __VA_ARGS__) + + +int mipid_hx8363_lcd_setup(struct mipi_dsi_client_dev *panel_dev) +{ + u8 buf[DSI_CMD_BUF_MAXSIZE]; + + debug("MIPI DSI LCD HX8363 setup.\n"); + + TC358763_DCS_write_1A_3P(0xB9, 0xFF, 0x83, 0x63);/* SET password */ + + TC358763_DCS_write_1A_19P(0xB1, 0x01, 0x00, 0x44, 0x08, 0x01, 0x10, 0x10, 0x36, + 0x3E, 0x1A, 0x1A, 0x40, 0x12, 0x00, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6);/* Set Power */ + TC358763_DCS_write_1A_2P(0xB2, 0x08, 0x03);/* Set DISP */ + TC358763_DCS_write_1A_7P(0xB4, 0x02, 0x18, 0x9C, 0x08, 0x18, 0x04, 0x6C); + TC358763_DCS_write_1A_1P(0xB6, 0x00);/* Set VCOM */ + TC358763_DCS_write_1A_1P(0xCC, 0x0B);/* Set Panel */ + TC358763_DCS_write_1A_34P(0xE0, 0x0E, 0x15, 0x19, 0x30, 0x31, 0x3F, 0x27, 0x3C, 0x88, 0x8F, 0xD1, 0xD5, 0xD7, 0x16, 0x16, + 0x0C, 0x1E, 0x0E, 0x15, 0x19, 0x30, 0x31, 0x3F, 0x27, 0x3C, 0x88, 0x8F, + 0xD1, 0xD5, 0xD7, 0x16, 0x16, 0x0C, 0x1E); + mdelay(5); + + TC358763_DCS_write_1A_1P(0x3A, 0x77);/* 24bit */ + TC358763_DCS_write_1A_14P(0xBA, 0x11, 0x00, 0x56, 0xC6, 0x10, 0x89, 0xFF, 0x0F, 0x32, 0x6E, 0x04, 0x07, 0x9A, 0x92); + TC358763_DCS_write_1A_0P(0x21); + + TC358763_DCS_write_1A_0P(0x11); + mdelay(10); + + TC358763_DCS_write_1A_0P(0x29); + mdelay(120); + + return 0; +} + +static struct mipi_dsi_client_driver hx8363_drv = { + .name = "HX8363_WVGA", + .dsi_client_setup = mipid_hx8363_lcd_setup, +}; + +void hx8363_init(void) +{ + imx_mipi_dsi_bridge_add_client_driver(&hx8363_drv); +} diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile new file mode 100644 index 00000000000..fe72d611647 --- /dev/null +++ b/drivers/video/imx/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2017-2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +UBOOTINCLUDE += -I$(srctree)/drivers/video/imx/hdp +obj-$(CONFIG_VIDEO_IMX_HDP_LOAD) += hdp_load.o hdprx_load.o hdp/ +obj-$(CONFIG_VIDEO_IMX8_HDMI) += hdp.o imx8_hdmi.o hdp/ diff --git a/drivers/video/imx/hdp.c b/drivers/video/imx/hdp.c new file mode 100644 index 00000000000..2f946ed2872 --- /dev/null +++ b/drivers/video/imx/hdp.c @@ -0,0 +1,46 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int do_hdp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + if (argc < 2) + return 0; + + if (strncmp(argv[1], "colorbar", 8) == 0) { + GraphicDevice *gdev; + struct video_mode_settings *vm; + + gdev = imx8m_get_gd(); + vm = imx8m_get_gmode(); + imx8m_show_gmode(); + + imx8m_create_color_bar( + (void *)((uint64_t)gdev->frameAdrs), + vm); + printf("colorbar test\n"); + } else if (strncmp(argv[1], "stop", 4) == 0) { + imx8_hdmi_disable(); + printf("stopping hdmi\n"); + } else { + printf("test error argc %d\n", argc); + } + + return 0; +} +/***************************************************/ + +U_BOOT_CMD( + hdp, CONFIG_SYS_MAXARGS, 1, do_hdp, + "hdmi/dp display test commands", + "[] ...\n" + "colorbar - display a colorbar pattern\n" + ); diff --git a/drivers/video/imx/hdp/API_AFE.c b/drivers/video/imx/hdp/API_AFE.c new file mode 100644 index 00000000000..7b778cd3d58 --- /dev/null +++ b/drivers/video/imx/hdp/API_AFE.c @@ -0,0 +1,115 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AFE.c + * + ****************************************************************************** + */ + +#include "address.h" +#include "API_AFE.h" +#include "util.h" +#ifndef __UBOOT__ +#include +#endif + +void afe_write(unsigned int offset, unsigned short val) +{ +#ifdef EXTERNAL_AFE + cdn_phapb_write(offset << 2, val); +#else + CDN_API_STATUS sts; + + sts = cdn_api_general_write_register_blocking( + ADDR_AFE + (offset << 2), val); + + if (sts != CDN_OK) { + printf("CDN_API_General_Write_Register_blocking(0x%.8X, 0x%.8X) returned %d\n", + offset, + val, + (int)sts); + } +#endif +} + +unsigned short afe_read(unsigned int offset) +{ + GENERAL_READ_REGISTER_RESPONSE resp; + +#ifdef EXTERNAL_AFE + cdn_phapb_read(offset << 2, &resp.val); +#else + CDN_API_STATUS sts; + + sts = cdn_api_general_read_register_blocking( + ADDR_AFE + (offset << 2), &resp); + + if (sts != CDN_OK) { + printf("CDN_API_General_Read_Register_blocking(0x%.8X) returned %d\n", + offset, + (int)sts); + } +#endif + return resp.val; +} + +void set_field_value(reg_field_t *reg_field, u32 value) +{ + u8 length; + u32 max_value; + u32 trunc_val; + length = (reg_field->msb - reg_field->lsb + 1); + + max_value = (1 << length) - 1; + if (value > max_value) { + trunc_val = value; + trunc_val &= (1 << length) - 1; + printf("set_field_value() Error! Specified value (0x%0X) exceeds field capacity - it will by truncated to 0x%0X (%0d-bit field - max value: %0d dec)\n", + value, trunc_val, length, max_value); + } else { + reg_field->value = value; + } +} + +int set_reg_value(reg_field_t reg_field) +{ + return reg_field.value << reg_field.lsb; +} diff --git a/drivers/video/imx/hdp/API_AFE.h b/drivers/video/imx/hdp/API_AFE.h new file mode 100644 index 00000000000..2ebdfb32260 --- /dev/null +++ b/drivers/video/imx/hdp/API_AFE.h @@ -0,0 +1,99 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AFE.h + * + ****************************************************************************** + */ + +#ifndef API_AFE_H_ +#define API_AFE_H_ +#include "util.h" + +typedef enum { + AFE_LINK_RATE_1_6 = 0x6, /* 1.62 Gb/s */ + AFE_LINK_RATE_2_1 = 0x8, /* 2.16 Gb/s */ + AFE_LINK_RATE_2_4 = 0x9, /* 2.43 Gb/s */ + AFE_LINK_RATE_2_7 = 0xA, /* 2.70 Gb/s */ + AFE_LINK_RATE_3_2 = 0xC, /* 3.24 Gb/s */ + AFE_LINK_RATE_4_3 = 0x10, /* 4.32 Gb/s */ + AFE_LINK_RATE_5_4 = 0x14, /* 5.40 Gb/s */ + AFE_LINK_RATE_8_1 = 0x1E, /* 8.10 Gb/s */ +} ENUM_AFE_LINK_RATE; + +/* Some of the PHY programming sequences */ +/* depend on the reference clock frequency. */ +/* Variable of this type is used to control */ +/* the programming flow. */ +typedef enum { + REFCLK_24MHZ, + REFCLK_27MHZ +} REFCLK_FREQ; + +typedef enum { + CLK_RATIO_1_1, + CLK_RATIO_5_4, + CLK_RATIO_3_2, + CLK_RATIO_2_1, + CLK_RATIO_1_2, + CLK_RATIO_5_8, + CLK_RATIO_3_4 +} clk_ratio_t; + +typedef struct { + u32 value; + u8 lsb; + u8 msb; +} reg_field_t; + +unsigned char AFE_check_rate_supported(ENUM_AFE_LINK_RATE rate); +void afe_write(unsigned int offset, unsigned short val); +unsigned short afe_read(unsigned int offset); +void AFE_init(int num_lanes, ENUM_AFE_LINK_RATE link_rate); +void AFE_power(int num_lanes, ENUM_AFE_LINK_RATE link_rate); + +/*extern int cdn_phapb_read(unsigned int addr, unsigned int *value);*/ +/*extern int cdn_phapb_write(unsigned int addr, unsigned int value);*/ +void set_field_value(reg_field_t *reg_field, u32 value); +int set_reg_value(reg_field_t reg_field); + +#endif + diff --git a/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.c b/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.c new file mode 100644 index 00000000000..933ecfa8d43 --- /dev/null +++ b/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.c @@ -0,0 +1,1863 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AFE_t28hpc_hdmitx.c + * + ****************************************************************************** + */ + +#include "API_AFE_t28hpc_hdmitx.h" +#include "API_AFE.h" +#include "externs.h" + +#ifndef DEBUG +static inline void write16(uint32_t addr, uint16_t val) +{ + afe_write(addr, val); +} + +static inline uint16_t read16(uint32_t addr) +{ + return afe_read(addr); +} +#else +#define write16(addr, val) __write16(addr, val, __LINE__) +static inline void __write16(uint32_t addr, uint16_t val, int line) +{ + afe_write(addr, val); + debug("write16():%4d Writting value 0x%04X at address 0x%05X (0x%04X)\n", + line, val, (0x20000 * 4) + (addr << 2), addr); +} +#define read16(addr) __read16(addr, __LINE__) +static inline uint16_t __read16(uint32_t addr, int line) +{ + debug("read16():%5d Reading from address 0x%05X (0x%04X)\n", + line, (0x20000 * 4) + (addr << 2), addr); + return afe_read(addr); +} + +#endif + +static char inside(u32 value, u32 left_sharp_corner, + u32 right_sharp_corner) +{ + if (value < left_sharp_corner) + return false; + if (value > right_sharp_corner) + return false; + return true; +} + +void aux_cfg_t28hpc(void) +{ + write16(0x5025, 0x0001); + + write16(0x5024, 36); + + write16(0x5021, 0x0100); + write16(0x5021, 0x0300); + write16(0x5026, 0x0000); + write16(0x5020, 0x2008); + write16(0x5020, 0x2018); + write16(0x5020, 0xA018); + write16(0x5021, 0x030C); + write16(0x5029, 0x0000); + write16(0x5027, 0x4001); + write16(0x5020, 0xA098); + write16(0x5020, 0xA198); + write16(0x5021, 0x030D); + write16(0x5021, 0x030F); +} + +int phy_cfg_t28hpc(int num_lanes, VIC_MODES vic_mode, int bpp, + VIC_PXL_ENCODING_FORMAT format, bool pixel_clk_from_phy) +{ + const int phy_reset_workaround = 1; + unsigned int vco_freq; + unsigned char k; + uint32_t reg_val; + uint32_t pixel_freq_khz = vic_table[vic_mode][PIXEL_FREQ_KHZ]; + uint32_t character_clock_ratio_num = 1; + uint32_t character_clock_ratio_den = 1; + uint32_t character_freq_khz; + const unsigned int refclk_freq_khz = 27000; + unsigned int ftemp, ftemp2; + + clk_ratio_t clk_ratio = 0; + reg_field_t cmnda_pll0_hs_sym_div_sel; + reg_field_t cmnda_pll0_ip_div; + reg_field_t cmnda_pll0_fb_div_low; + reg_field_t cmnda_pll0_fb_div_high; + reg_field_t cmn_ref_clk_dig_div; + reg_field_t divider_scaler; + reg_field_t cmnda_hs_clk_0_sel; + reg_field_t cmnda_hs_clk_1_sel; + reg_field_t tx_subrate; + reg_field_t voltage_to_current_coarse; + reg_field_t voltage_to_current; + reg_field_t ndac_ctrl; + reg_field_t pmos_ctrl; + reg_field_t ptat_ndac_ctrl; + reg_field_t charge_pump_gain; + reg_field_t vco_ring_select; + reg_field_t pll_feedback_divider_total; + reg_field_t cmnda_pll0_pxdiv_high; + reg_field_t cmnda_pll0_pxdiv_low; + reg_field_t coarse_code; + reg_field_t v2i_code; + reg_field_t vco_cal_code; + + cmnda_pll0_fb_div_high.value = 0x00A; + ftemp = pixel_freq_khz; + + debug(" VIC %d, pixel clock %u kHz\n", vic_mode, ftemp); + + /* Set field position */ + cmnda_pll0_hs_sym_div_sel.msb = 9; + cmnda_pll0_hs_sym_div_sel.lsb = 8; + cmnda_pll0_ip_div.msb = 7; + cmnda_pll0_ip_div.lsb = 0; + cmnda_pll0_fb_div_low.msb = 9; + cmnda_pll0_fb_div_low.lsb = 0; + cmnda_pll0_fb_div_high.msb = 9; + cmnda_pll0_fb_div_high.lsb = 0; + cmn_ref_clk_dig_div.msb = 13; + cmn_ref_clk_dig_div.lsb = 12; + divider_scaler.msb = 14; + divider_scaler.lsb = 12; + cmnda_hs_clk_0_sel.msb = 1; + cmnda_hs_clk_0_sel.lsb = 0; + cmnda_hs_clk_1_sel.msb = 1; + cmnda_hs_clk_1_sel.lsb = 0; + tx_subrate.msb = 2; + tx_subrate.lsb = 0; + voltage_to_current_coarse.msb = 2; + voltage_to_current_coarse.lsb = 0; + voltage_to_current.msb = 5; + voltage_to_current.lsb = 4; + ndac_ctrl.msb = 11; + ndac_ctrl.lsb = 8; + pmos_ctrl.msb = 7; + pmos_ctrl.lsb = 0; + ptat_ndac_ctrl.msb = 5; + ptat_ndac_ctrl.lsb = 0; + charge_pump_gain.msb = 8; + charge_pump_gain.lsb = 0; + vco_ring_select.msb = 12; + vco_ring_select.lsb = 12; + pll_feedback_divider_total.msb = 9; + pll_feedback_divider_total.lsb = 0; + cmnda_pll0_pxdiv_high.msb = 9; + cmnda_pll0_pxdiv_high.lsb = 0; + cmnda_pll0_pxdiv_low.msb = 9; + cmnda_pll0_pxdiv_low.lsb = 0; + coarse_code.msb = 7; + coarse_code.lsb = 0; + v2i_code.msb = 3; + v2i_code.lsb = 0; + vco_cal_code.msb = 8; + vco_cal_code.lsb = 0; + + if (phy_reset_workaround) { + /* register PHY_PMA_ISOLATION_CTRL */ + write16(0xC81F, 0xD000); /* enable PHY iso mode only for CMN */ + /* register PHY_PMA_ISO_PLL_CTRL1 */ + reg_val = read16(0xC812); + reg_val &= 0xFF00; + reg_val |= 0x0012; + /* set pll0_clk_datart1_div/pll0_clk_datart0_div dividers */ + write16(0xC812, reg_val); + /* register PHY_ISO_CMN_CTRL */ + /* assert PHY reset from isolation register */ + write16(0xC010, 0x0000); + /* register PHY_PMA_ISO_CMN_CTRL */ + write16(0xC810, 0x0000); /* assert PMA CMN reset */ + /* register XCVR_DIAG_BIDI_CTRL */ + for (k = 0; k < num_lanes; k++) + write16(0x40E8 | (k << 9), 0x00FF); + } + /*--------------------------------------------------------------- + * Describing Task phy_cfg_hdp + * --------------------------------------------------------------*/ + /* register PHY_PMA_CMN_CTRL1 */ + reg_val = read16(0xC800); + reg_val &= 0xFFF7; + reg_val |= 0x0008; + write16(0xC800, reg_val); + + /* register CMN_DIAG_PLL0_TEST_MODE */ + write16(0x01C4, 0x0020); + /* register CMN_PSM_CLK_CTRL */ + write16(0x0061, 0x0016); + + switch (format) { + case YCBCR_4_2_2: + clk_ratio = CLK_RATIO_1_1; + character_clock_ratio_num = 1; + character_clock_ratio_den = 1; + break; + case YCBCR_4_2_0: + switch (bpp) { + case 8: + clk_ratio = CLK_RATIO_1_2; + character_clock_ratio_num = 1; + character_clock_ratio_den = 2; + break; + case 10: + clk_ratio = CLK_RATIO_5_8; + character_clock_ratio_num = 5; + character_clock_ratio_den = 8; + break; + case 12: + clk_ratio = CLK_RATIO_3_4; + character_clock_ratio_num = 3; + character_clock_ratio_den = 4; + break; + case 16: + clk_ratio = CLK_RATIO_1_1; + character_clock_ratio_num = 1; + character_clock_ratio_den = 1; + break; + default: + debug("Invalid ColorDepth\n"); + } + break; + + default: + switch (bpp) { + /* Assume RGB */ + case 10: + clk_ratio = CLK_RATIO_5_4; + character_clock_ratio_num = 5; + character_clock_ratio_den = 4; + break; + case 12: + clk_ratio = CLK_RATIO_3_2; + character_clock_ratio_num = 3; + character_clock_ratio_den = 2; + break; + case 16: + clk_ratio = CLK_RATIO_2_1; + character_clock_ratio_num = 2; + character_clock_ratio_den = 1; + break; + default: + clk_ratio = CLK_RATIO_1_1; + character_clock_ratio_num = 1; + character_clock_ratio_den = 1; + } + } + + character_freq_khz = pixel_freq_khz * + character_clock_ratio_num / character_clock_ratio_den; + ftemp = pixel_freq_khz; + ftemp2 = character_freq_khz; + debug("Pixel clock frequency: %u kHz, character clock frequency: %u, color depth is %0d-bit.\n", + ftemp, ftemp2, bpp); + if (pixel_clk_from_phy == 0) { + /* ----------------------------------------------------------- + * Describing Task phy_cfg_hdmi_pll0_0pt5736 (Clock is input) + * -----------------------------------------------------------*/ + + /* register CMN_PLL0_VCOCAL_INIT_TMR */ + write16(0x0084, 0x0064); + /* register CMN_PLL0_VCOCAL_ITER_TMR */ + write16(0x0085, 0x000A); + /* register PHY_HDP_CLK_CTL */ + reg_val = read16(0xC009); + reg_val &= 0x00FF; + reg_val |= 0x1200; + write16(0xC009, reg_val); + + switch (clk_ratio) { + case CLK_RATIO_1_1: + if (inside(pixel_freq_khz, 340000, 600000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x3C); + set_field_value(&cmnda_pll0_fb_div_low, 0x24A); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x06); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 600); + } else if (inside(pixel_freq_khz, 170000, 340000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x22); + set_field_value(&cmnda_pll0_fb_div_low, 0x146); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x07); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 340); + } else if (inside(pixel_freq_khz, 85000, 170000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + set_field_value(&cmnda_pll0_ip_div, 0x11); + set_field_value(&cmnda_pll0_fb_div_low, 0x146); + set_field_value(&cmn_ref_clk_dig_div, 0x00); + set_field_value(÷r_scaler, 0x07); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 340); + } else if (inside(pixel_freq_khz, 42500, 85000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + set_field_value(&cmnda_pll0_ip_div, 0x08); + set_field_value(&cmnda_pll0_fb_div_low, 0x132); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 320); + } else if (inside(pixel_freq_khz, 25000, 42500)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + set_field_value(&cmnda_pll0_ip_div, 0x05); + set_field_value(&cmnda_pll0_fb_div_low, 0x182); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 400); + } else { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } + break; + + case CLK_RATIO_5_4: + if (inside(pixel_freq_khz, 272000, 480000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x30); + set_field_value(&cmnda_pll0_fb_div_low, 0x24A); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x05); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 600); + } else if (inside(pixel_freq_khz, 136000, 272000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x1A); + set_field_value(&cmnda_pll0_fb_div_low, 0x137); + set_field_value(&cmn_ref_clk_dig_div, 0x02); + set_field_value(÷r_scaler, 0x04); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 325); + } else if (inside(pixel_freq_khz, 68000, 136000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + set_field_value(&cmnda_pll0_ip_div, 0x0D); + set_field_value(&cmnda_pll0_fb_div_low, 0x137); + set_field_value(&cmn_ref_clk_dig_div, 0x02); + set_field_value(÷r_scaler, 0x02); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 325); + } else if (inside(pixel_freq_khz, 34000, 68000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + set_field_value(&cmnda_pll0_ip_div, 0x06); + set_field_value(&cmnda_pll0_fb_div_low, 0x11E); + set_field_value(&cmn_ref_clk_dig_div, 0x02); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 300); + } else if (inside(pixel_freq_khz, 25000, 34000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmnda_pll0_fb_div_low, 0x182); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 400); + } else { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } + break; + case CLK_RATIO_3_2: + if (inside(pixel_freq_khz, 226000, 400000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x28); + set_field_value(&cmnda_pll0_fb_div_low, 0x24A); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x04); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 600); + } else if (inside(pixel_freq_khz, 113000, 226000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x16); + set_field_value(&cmnda_pll0_fb_div_low, 0x13C); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x05); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 330); + } else if (inside(pixel_freq_khz, 56000, 113000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + set_field_value(&cmnda_pll0_ip_div, 0x0B); + set_field_value(&cmnda_pll0_fb_div_low, 0x13C); + set_field_value(&cmn_ref_clk_dig_div, 0x00); + set_field_value(÷r_scaler, 0x05); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 330); + } else if (inside(pixel_freq_khz, 28000, 56000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + set_field_value(&cmnda_pll0_ip_div, 0x06); + set_field_value(&cmnda_pll0_fb_div_low, 0x15A); + set_field_value(&cmn_ref_clk_dig_div, 0x02); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 360); + } else if (inside(pixel_freq_khz, 25000, 28000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmnda_pll0_fb_div_low, 0x15A); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 360); + } else { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } + break; + case CLK_RATIO_2_1: + if (inside(pixel_freq_khz, 170000, 300000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x22); + set_field_value(&cmnda_pll0_fb_div_low, 0x29A); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x06); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 680); + } else if (inside(pixel_freq_khz, 85000, 170000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x11); + set_field_value(&cmnda_pll0_fb_div_low, 0x146); + set_field_value(&cmn_ref_clk_dig_div, 0x00); + set_field_value(÷r_scaler, 0x07); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 340); + } else if (inside(pixel_freq_khz, 42500, 85000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + set_field_value(&cmnda_pll0_ip_div, 0x08); + set_field_value(&cmnda_pll0_fb_div_low, 0x132); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 320); + } else if (inside(pixel_freq_khz, 25000, 42500)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + set_field_value(&cmnda_pll0_ip_div, 0x05); + set_field_value(&cmnda_pll0_fb_div_low, 0x182); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 400); + } else { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } + break; + case CLK_RATIO_1_2: + if (!(inside(pixel_freq_khz, 594000, 594000))) { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } else { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + set_field_value(&cmnda_pll0_ip_div, 0x3C); + set_field_value(&cmnda_pll0_fb_div_low, 0x24A); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x06); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 600); + } + break; + case CLK_RATIO_5_8: + if (!(inside(pixel_freq_khz, 594000, 594000))) { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } else { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x3C); + set_field_value(&cmnda_pll0_fb_div_low, 0x169); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x06); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 375); + } + break; + case CLK_RATIO_3_4: + if (!(inside(pixel_freq_khz, 594000, 594000))) { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } else { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x3C); + set_field_value(&cmnda_pll0_fb_div_low, 0x1B4); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x06); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 450); + } + break; + } + vco_freq = + pixel_freq_khz * pll_feedback_divider_total.value / + cmnda_pll0_ip_div.value; + ftemp = vco_freq; + debug("VCO frequency is %u kHz\n", ftemp); + + if (inside(vco_freq, 1700000, 2000000)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x09); + set_field_value(&ptat_ndac_ctrl, 0x09); + switch (pll_feedback_divider_total.value) { + case 300: + set_field_value(&charge_pump_gain, 0x82); + break; + case 320: + set_field_value(&charge_pump_gain, 0x83); + break; + case 325: + set_field_value(&charge_pump_gain, 0x83); + break; + case 330: + set_field_value(&charge_pump_gain, 0x84); + break; + case 340: + set_field_value(&charge_pump_gain, 0x84); + break; + case 360: + set_field_value(&charge_pump_gain, 0x86); + break; + case 400: + set_field_value(&charge_pump_gain, 0xA2); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 2000000, 2400000)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x09); + set_field_value(&ptat_ndac_ctrl, 0x09); + switch (pll_feedback_divider_total.value) { + case 300: + set_field_value(&charge_pump_gain, 0x47); + break; + case 320: + set_field_value(&charge_pump_gain, 0x4B); + break; + case 325: + set_field_value(&charge_pump_gain, 0x4C); + break; + case 330: + set_field_value(&charge_pump_gain, 0x80); + break; + case 340: + set_field_value(&charge_pump_gain, 0x81); + break; + case 360: + set_field_value(&charge_pump_gain, 0x82); + break; + case 400: + set_field_value(&charge_pump_gain, 0x84); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 2400000, 2800000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 300: + set_field_value(&charge_pump_gain, 0x43); + break; + case 320: + set_field_value(&charge_pump_gain, 0x45); + break; + case 325: + set_field_value(&charge_pump_gain, 0x45); + break; + case 330: + set_field_value(&charge_pump_gain, 0x45); + break; + case 340: + set_field_value(&charge_pump_gain, 0x86); + break; + case 360: + set_field_value(&charge_pump_gain, 0x4A); + break; + case 400: + set_field_value(&charge_pump_gain, 0x81); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 2800000, 3400000)) { + set_field_value(&voltage_to_current_coarse, 0x06); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 300: + set_field_value(&charge_pump_gain, 0x3D); + break; + case 320: + set_field_value(&charge_pump_gain, 0x41); + break; + case 325: + set_field_value(&charge_pump_gain, 0x41); + break; + case 330: + set_field_value(&charge_pump_gain, 0x41); + break; + case 340: + set_field_value(&charge_pump_gain, 0x42); + break; + case 360: + set_field_value(&charge_pump_gain, 0x43); + break; + case 400: + set_field_value(&charge_pump_gain, 0x46); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 3400000, 3900000)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + switch (pll_feedback_divider_total.value) { + case 375: + set_field_value(&charge_pump_gain, 0x41); + break; + case 600: + set_field_value(&charge_pump_gain, 0x82); + break; + case 680: + set_field_value(&charge_pump_gain, 0x85); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 3900000, 4500000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + switch (pll_feedback_divider_total.value) { + case 450: + set_field_value(&charge_pump_gain, 0x41); + break; + case 600: + set_field_value(&charge_pump_gain, 0x4B); + break; + case 680: + set_field_value(&charge_pump_gain, 0x82); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 4500000, 5200000)) { + set_field_value(&voltage_to_current_coarse, 0x06); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 600: + set_field_value(&charge_pump_gain, 0x45); + break; + case 680: + set_field_value(&charge_pump_gain, 0x4A); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 5200000, 6000000)) { + set_field_value(&voltage_to_current_coarse, 0x07); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 600: + set_field_value(&charge_pump_gain, 0x42); + break; + case 680: + set_field_value(&charge_pump_gain, 0x45); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else + debug("VCO frequency %u kHz is outside of the supported range\n", + ftemp); + + /* register CMN_DIAG_PLL0_INCLK_CTRL */ + reg_val = set_reg_value(cmnda_pll0_hs_sym_div_sel); + reg_val |= set_reg_value(cmnda_pll0_ip_div); + write16(0x01CA, reg_val); + /* register CMN_DIAG_PLL0_FBL_OVRD */ + reg_val = set_reg_value(cmnda_pll0_fb_div_low); + reg_val |= (1 << 15); + write16(0x01C1, reg_val); + /* register PHY_PMA_CMN_CTRL1 */ + reg_val = read16(0xC800); + reg_val &= 0xCFFF; + reg_val |= set_reg_value(cmn_ref_clk_dig_div); + write16(0xC800, reg_val); + /* register CMN_CDIAG_REFCLK_CTRL */ + reg_val = read16(0x0062); + reg_val &= 0x8FFF; + reg_val |= set_reg_value(divider_scaler); + reg_val |= 0x00C0; + write16(0x0062, reg_val); + /* register CMN_DIAG_HSCLK_SEL */ + reg_val = read16(0x01E0); + reg_val &= 0xFF00; + reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 0; + reg_val |= (cmnda_hs_clk_1_sel.value >> 1) << 4; + write16(0x01E0, reg_val); + + /* register XCVR_DIAG_HSCLK_SEL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x40E1 | (k << 9)); + reg_val &= 0xCFFF; + reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 12; + write16(0x40E1 | (k << 9), reg_val); + } + + /* register TX_DIAG_TX_CTRL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x41E0 | (k << 9)); + reg_val &= 0xFF3F; + reg_val |= (tx_subrate.value >> 1) << 6; + write16(0x41E0 | (k << 9), reg_val); + } + + /* register CMN_PLLSM0_USER_DEF_CTRL */ + reg_val = set_reg_value(vco_ring_select); + write16(0x002F, reg_val); + /* register CMN_DIAG_PLL0_OVRD */ + write16(0x01C2, 0x0000); + /* register CMN_DIAG_PLL0_FBH_OVRD */ + reg_val = set_reg_value(cmnda_pll0_fb_div_high); + reg_val |= (1 << 15); + write16(0x01C0, reg_val); + /* register CMN_DIAG_PLL0_V2I_TUNE */ + reg_val = set_reg_value(voltage_to_current_coarse); + reg_val |= set_reg_value(voltage_to_current); + write16(0x01C5, reg_val); + /* register CMN_DIAG_PLL0_PTATIS_TUNE1 */ + reg_val = set_reg_value(pmos_ctrl); + reg_val |= set_reg_value(ndac_ctrl); + write16(0x01C8, reg_val); + /* register CMN_DIAG_PLL0_PTATIS_TUNE2 */ + reg_val = set_reg_value(ptat_ndac_ctrl); + write16(0x01C9, reg_val); + /* register CMN_DIAG_PLL0_CP_TUNE */ + reg_val = set_reg_value(charge_pump_gain); + write16(0x01C6, reg_val); + /* register CMN_DIAG_PLL0_LF_PROG */ + write16(0x01C7, 0x0008); + + /* register XCVR_DIAG_PLLDRC_CTRL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x40E0 | (k << 9)); + reg_val &= 0xBFFF; + write16(0x40E0 | (k << 9), reg_val); + } + + } else { + /* Describing task phy_cfg_hdmi_pll0_0pt099_ver2 + (Clock is OUTPUT) */ + if (inside(pixel_freq_khz, 27000, 27000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 240); + set_field_value(&cmnda_pll0_fb_div_low, 0xBC); + set_field_value(&cmnda_pll0_fb_div_high, 0x30); + set_field_value(&cmnda_pll0_pxdiv_low, 0x26); + set_field_value(&cmnda_pll0_pxdiv_high, 0x26); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 300); + set_field_value(&cmnda_pll0_fb_div_low, 0x0EC); + set_field_value(&cmnda_pll0_fb_div_high, 0x03C); + set_field_value(&cmnda_pll0_pxdiv_low, 0x030); + set_field_value(&cmnda_pll0_pxdiv_high, 0x030); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 360); + set_field_value(&cmnda_pll0_fb_div_low, 0x11C); + set_field_value(&cmnda_pll0_fb_div_high, 0x048); + set_field_value(&cmnda_pll0_pxdiv_low, 0x03A); + set_field_value(&cmnda_pll0_pxdiv_high, 0x03A); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 240); + set_field_value(&cmnda_pll0_fb_div_low, 0x0BC); + set_field_value(&cmnda_pll0_fb_div_high, 0x030); + set_field_value(&cmnda_pll0_pxdiv_low, 0x026); + set_field_value(&cmnda_pll0_pxdiv_high, 0x026); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 54000, 54000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 480); + set_field_value(&cmnda_pll0_fb_div_low, 0x17C); + set_field_value(&cmnda_pll0_fb_div_high, 0x060); + set_field_value(&cmnda_pll0_pxdiv_low, 0x026); + set_field_value(&cmnda_pll0_pxdiv_high, 0x026); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 400); + set_field_value(&cmnda_pll0_fb_div_low, 0x13C); + set_field_value(&cmnda_pll0_fb_div_high, 0x050); + set_field_value(&cmnda_pll0_pxdiv_low, 0x017); + set_field_value(&cmnda_pll0_pxdiv_high, 0x017); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 480); + set_field_value(&cmnda_pll0_fb_div_low, 0x17C); + set_field_value(&cmnda_pll0_fb_div_high, 0x060); + set_field_value(&cmnda_pll0_pxdiv_low, 0x01C); + set_field_value(&cmnda_pll0_pxdiv_high, 0x01C); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 240); + set_field_value(&cmnda_pll0_fb_div_low, 0x0bc); + set_field_value(&cmnda_pll0_fb_div_high, 0x030); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 74250, 74250)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x026); + set_field_value(&cmnda_pll0_pxdiv_high, 0x026); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 550); + set_field_value(&cmnda_pll0_fb_div_low, 0x1b4); + set_field_value(&cmnda_pll0_fb_div_high, 0x06e); + set_field_value(&cmnda_pll0_pxdiv_low, 0x017); + set_field_value(&cmnda_pll0_pxdiv_high, 0x017); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x01c); + set_field_value(&cmnda_pll0_pxdiv_high, 0x01c); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 330); + set_field_value(&cmnda_pll0_fb_div_low, 0x104); + set_field_value(&cmnda_pll0_fb_div_high, 0x042); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 99000, 99000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 440); + set_field_value(&cmnda_pll0_fb_div_low, 0x15c); + set_field_value(&cmnda_pll0_fb_div_high, 0x058); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 275); + set_field_value(&cmnda_pll0_fb_div_low, 0x0d8); + set_field_value(&cmnda_pll0_fb_div_high, 0x037); + set_field_value(&cmnda_pll0_pxdiv_low, 0x00b); + set_field_value(&cmnda_pll0_pxdiv_high, 0x00a); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 330); + set_field_value(&cmnda_pll0_fb_div_low, 0x104); + set_field_value(&cmnda_pll0_fb_div_high, 0x042); + set_field_value(&cmnda_pll0_pxdiv_low, 0x00d); + set_field_value(&cmnda_pll0_pxdiv_high, 0x00d); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 440); + set_field_value(&cmnda_pll0_fb_div_low, 0x15c); + set_field_value(&cmnda_pll0_fb_div_high, 0x058); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 148500, 148500)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 550); + set_field_value(&cmnda_pll0_fb_div_low, 0x1b4); + set_field_value(&cmnda_pll0_fb_div_high, 0x06e); + set_field_value(&cmnda_pll0_pxdiv_low, 0x00b); + set_field_value(&cmnda_pll0_pxdiv_high, 0x00a); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 495); + set_field_value(&cmnda_pll0_fb_div_low, 0x188); + set_field_value(&cmnda_pll0_fb_div_high, 0x063); + set_field_value(&cmnda_pll0_pxdiv_low, 0x00d); + set_field_value(&cmnda_pll0_pxdiv_high, 0x00d); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 198000, 198000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 220); + set_field_value(&cmnda_pll0_fb_div_low, 0x0ac); + set_field_value(&cmnda_pll0_fb_div_high, 0x02c); + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 550); + set_field_value(&cmnda_pll0_fb_div_low, 0x1b4); + set_field_value(&cmnda_pll0_fb_div_high, 0x06e); + set_field_value(&cmnda_pll0_pxdiv_low, 0x00b); + set_field_value(&cmnda_pll0_pxdiv_high, 0x00a); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 330); + set_field_value(&cmnda_pll0_fb_div_low, 0x104); + set_field_value(&cmnda_pll0_fb_div_high, 0x042); + set_field_value(&cmnda_pll0_pxdiv_low, 0x006); + set_field_value(&cmnda_pll0_pxdiv_high, 0x005); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 440); + set_field_value(&cmnda_pll0_fb_div_low, 0x15c); + set_field_value(&cmnda_pll0_fb_div_high, 0x058); + set_field_value(&cmnda_pll0_pxdiv_low, 0x008); + set_field_value(&cmnda_pll0_pxdiv_high, 0x008); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 297000, 297000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 330); + set_field_value(&cmnda_pll0_fb_div_low, 0x104); + set_field_value(&cmnda_pll0_fb_div_high, 0x042); + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 495); + set_field_value(&cmnda_pll0_fb_div_low, 0x188); + set_field_value(&cmnda_pll0_fb_div_high, 0x063); + set_field_value(&cmnda_pll0_pxdiv_low, 0x006); + set_field_value(&cmnda_pll0_pxdiv_high, 0x005); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x008); + set_field_value(&cmnda_pll0_pxdiv_high, 0x008); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + default: + ftemp = pixel_freq_khz; + debug("This pixel clock frequency (%u kHz) is not supported with this (%0d-bit) color depth.\n", + ftemp, bpp); + } + } else if (inside(pixel_freq_khz, 594000, 594000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_1_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_5_8: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 550); + set_field_value(&cmnda_pll0_fb_div_low, 0x1b4); + set_field_value(&cmnda_pll0_fb_div_high, 0x06e); + /* does not matter - pixel clock delivered to + controller from SoC */ + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + /* does not matter - pixel clock delivered to + controller from SoC */ + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_3_4: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 495); + set_field_value(&cmnda_pll0_fb_div_low, 0x188); + set_field_value(&cmnda_pll0_fb_div_high, 0x063); + /* does not matter - pixel clock delivered to + controller from SoC */ + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + /* does not matter - pixel clock delivered to + controller from SoC */ + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + default: + debug("This pixel clock frequency (%d KHz) is not supported with this (%0d-bit) color depth.\n", + pixel_freq_khz, bpp); + } + } else { + ftemp = pixel_freq_khz; + debug("This pixel clock frequency (%u kHz) is not supported.\n", + ftemp); + } + + vco_freq = + refclk_freq_khz * pll_feedback_divider_total.value / + cmnda_pll0_ip_div.value; + ftemp = vco_freq; + debug("VCO frequency is %u kHz\n", ftemp); + + if (inside(vco_freq, 1980000, 1980000)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x09); + set_field_value(&ptat_ndac_ctrl, 0x09); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 160); + set_field_value(&v2i_code, 5); + set_field_value(&vco_cal_code, 183); + } else if (inside(vco_freq, 2160000, 2160000)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x09); + set_field_value(&ptat_ndac_ctrl, 0x09); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 166); + set_field_value(&v2i_code, 6); + set_field_value(&vco_cal_code, 208); + } else if (inside(vco_freq, 2475000, 2475000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 167); + set_field_value(&v2i_code, 6); + set_field_value(&vco_cal_code, 209); + } else if (inside(vco_freq, 2700000, 2700000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 300: + set_field_value(&charge_pump_gain, 0x042); + break; + case 400: + set_field_value(&charge_pump_gain, 0x04c); + break; + } + set_field_value(&coarse_code, 188); + set_field_value(&v2i_code, 6); + set_field_value(&vco_cal_code, 225); + } else if (inside(vco_freq, 2970000, 2970000)) { + set_field_value(&voltage_to_current_coarse, 0x06); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 183); + set_field_value(&v2i_code, 6); + set_field_value(&vco_cal_code, 225); + } else if (inside(vco_freq, 3240000, 3240000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 360: + set_field_value(&charge_pump_gain, 0x042); + break; + case 480: + set_field_value(&charge_pump_gain, 0x04c); + break; + } + set_field_value(&coarse_code, 203); + set_field_value(&v2i_code, 7); + set_field_value(&vco_cal_code, 256); + } else if (inside(vco_freq, 3712500, 3712500)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + set_field_value(&charge_pump_gain, 0x04c); + set_field_value(&coarse_code, 212); + set_field_value(&v2i_code, 7); + set_field_value(&vco_cal_code, 257); + } else if (inside(vco_freq, 3960000, 3960000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 184); + set_field_value(&v2i_code, 6); + set_field_value(&vco_cal_code, 226); + } else if (inside(vco_freq, 4320000, 4320000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 205); + set_field_value(&v2i_code, 7); + set_field_value(&vco_cal_code, 258); + } else if (inside(vco_freq, 4455000, 4455000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + switch (pll_feedback_divider_total.value) { + case 495: + set_field_value(&charge_pump_gain, 0x042); + break; + case 660: + set_field_value(&charge_pump_gain, 0x04c); + break; + } + set_field_value(&coarse_code, 219); + set_field_value(&v2i_code, 7); + set_field_value(&vco_cal_code, 272); + } else if (inside(vco_freq, 4950000, 4950000)) { + set_field_value(&voltage_to_current_coarse, 0x06); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 213); + set_field_value(&v2i_code, 7); + set_field_value(&vco_cal_code, 258); + } else if (inside(vco_freq, 5940000, 5940000)) { + set_field_value(&voltage_to_current_coarse, 0x07); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 244); + set_field_value(&v2i_code, 8); + set_field_value(&vco_cal_code, 292); + } else { + ftemp = vco_freq; + debug("Current vco_freq (%u kHz) is not supported.\n", + ftemp); + } + + /* register CMN_PLL0_VCOCAL_INIT_TMR */ + write16(0x0084, 0x0064); + /* register CMN_PLL0_VCOCAL_ITER_TMR */ + write16(0x0085, 0x000A); + /* register PHY_HDP_CLK_CTL */ + reg_val = read16(0xC009); + reg_val &= 0x00FF; + reg_val |= 0x2 << 8; + reg_val |= 0x1 << 12; + write16(0xC009, reg_val); + /* register CMN_DIAG_PLL0_INCLK_CTRL */ + reg_val = set_reg_value(cmnda_pll0_ip_div); + reg_val |= set_reg_value(cmnda_pll0_hs_sym_div_sel); + write16(0x01CA, reg_val); + /* register CMN_DIAG_PLL0_FBH_OVRD */ + reg_val = set_reg_value(cmnda_pll0_fb_div_high); + reg_val |= (1 << 15); + write16(0x01C0, reg_val); + /* register CMN_DIAG_PLL0_FBL_OVRD */ + reg_val = set_reg_value(cmnda_pll0_fb_div_low); + reg_val |= (1 << 15); + write16(0x01C1, reg_val); + /* register CMN_DIAG_PLL0_PXL_DIVL */ + reg_val = set_reg_value(cmnda_pll0_pxdiv_low); + write16(0x01CC, reg_val); + /* register CMN_DIAG_PLL0_PXL_DIVH */ + reg_val = set_reg_value(cmnda_pll0_pxdiv_high); + reg_val |= (1 << 15); + write16(0x01CB, reg_val); + + /* register TX_DIAG_TX_CTRL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x41E0 | (k << 9)); + reg_val &= 0xFF3F; + reg_val |= (tx_subrate.value >> 1) << 6; + write16(0x41E0 | (k << 9), reg_val); + } + + /* register PHY_PMA_CMN_CTRL1 */ + reg_val = read16(0xC800); + reg_val &= 0xCFFF; + reg_val |= set_reg_value(cmn_ref_clk_dig_div); + write16(0xC800, reg_val); + /* register CMN_CDIAG_REFCLK_CTRL */ + reg_val = read16(0x0062); + reg_val &= 0x8FFF; + reg_val |= set_reg_value(divider_scaler); + reg_val |= 0x00C0; + write16(0x0062, reg_val); + /* register CMN_DIAG_HSCLK_SEL */ + reg_val = read16(0x01E0); + reg_val &= 0xFF00; + reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 0; + reg_val |= (cmnda_hs_clk_1_sel.value >> 1) << 4; + write16(0x01E0, reg_val); + /* register CMN_PLLSM0_USER_DEF_CTRL */ + reg_val = set_reg_value(vco_ring_select); + write16(0x002F, reg_val); + + /* register XCVR_DIAG_HSCLK_SEL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x40E1 | (k << 9)); + reg_val &= 0xCFFF; + reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 12; + write16(0x40E1 | (k << 9), reg_val); + } + + /* register CMN_DIAG_PLL0_OVRD */ + write16(0x01C2, 0x0000); + /* register CMN_DIAG_PLL0_V2I_TUNE */ + reg_val = set_reg_value(voltage_to_current_coarse); + reg_val |= set_reg_value(voltage_to_current); + write16(0x01C5, reg_val); + /* register CMN_DIAG_PLL0_PTATIS_TUNE1 */ + reg_val = set_reg_value(pmos_ctrl); + reg_val |= set_reg_value(ndac_ctrl); + write16(0x01C8, reg_val); + /* register CMN_DIAG_PLL0_PTATIS_TUNE2 */ + reg_val = set_reg_value(ptat_ndac_ctrl); + write16(0x01C9, reg_val); + /* register CMN_PLL0_VCOCAL_START */ + reg_val = read16(0x0081); + reg_val &= 0xFE00; + reg_val |= set_reg_value(vco_cal_code); + write16(0x0081, reg_val); + /* register CMN_DIAG_PLL0_CP_TUNE */ + reg_val = set_reg_value(charge_pump_gain); + write16(0x01C6, reg_val); + /* register CMN_DIAG_PLL0_LF_PROG */ + write16(0x01C7, 0x0008); + + /* register XCVR_DIAG_PLLDRC_CTRL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x40E0 | (k << 9)); + reg_val &= 0xBFFF; + write16(0x40E0 | (k << 9), reg_val); + } + } + + /* Back to task phy_cfg_hdp */ + + /* register PHY_PMA_CMN_CTRL1 */ + reg_val = read16(0xC800); + reg_val &= 0xFF8F; + /* for differential clock on the refclk_p and refclk_m + * off chip pins: PHY_PMA_CMN_CTRL1[6:4]=3'b000 */ + reg_val |= 0x0000; + write16(0xC800, reg_val); + + /* register CMN_DIAG_ACYA */ + write16(0x01FF, 0x0100); + + if (phy_reset_workaround) { + /* register PHY_ISO_CMN_CTRL */ + write16(0xC010, 0x0001); /* Deassert PHY reset */ + /* register PHY_PMA_ISO_CMN_CTRL */ + write16(0xC810, 0x0003); + for (k = 0; k < num_lanes; k++) { + /* register XCVR_PSM_RCTRL */ + write16(0x4001 | (k << 9), 0xFEFC); + } + /* register PHY_PMA_ISO_CMN_CTRL + * Assert cmn_macro_pwr_en*/ + write16(0xC810, 0x0013); + + /* PHY_PMA_ISO_CMN_CTRL + * wait for cmn_macro_pwr_en_ack*/ + while (!(read16(0xC810) & (1 << 5))) + ; + + /* PHY_PMA_CMN_CTRL1 wait for cmn_ready */ + while (!(read16(0xC800) & (1 << 0))) + ; + } else { + for (k = 0; k < num_lanes; k++) { + /* register XCVR_PSM_RCTRL */ + write16(0x4001 | (k << 9), 0xBEFC); + } + } + for (k = 0; k < num_lanes; k++) { + /* register TX_PSC_A0 */ + write16(0x4100 | (k << 9), 0x6791); + /* register TX_PSC_A1 */ + write16(0x4101 | (k << 9), 0x6790); + /* register TX_PSC_A2 */ + write16(0x4102 | (k << 9), 0x0090); + /* register TX_PSC_A3 */ + write16(0x4103 | (k << 9), 0x0090); + /* register RX_PSC_CAL */ + reg_val = read16(0x8006 | (k << 9)); + reg_val &= 0xFFBB; + write16(0x8006 | (k << 9), reg_val); + reg_val = read16(0x8000 | (k << 9)); + reg_val &= 0xFFBB; + write16(0x8000 | (k << 9), reg_val); + } + + /* End of task phy_cfg_hdp */ + /* register PHY_HDP_MODE_CTL */ + write16(0xC008, 0x0004); + + aux_cfg_t28hpc(); + return character_freq_khz; +} + +int hdmi_tx_t28hpc_power_config_seq(int num_lanes) +{ + unsigned char k; + + /* Configure the power state. + * register TX_DIAG_ACYA */ + for (k = 0; k < num_lanes; k++) { + /* register XCVR_PSM_CAL_TMR */ + write16(0x41FF | (k << 9), 0x0001); + } + + /* register PHY_DP_MODE_CTL */ + while (!(read16(0xC008) & (1 << 6))) + ; + + /* PHY_DP_MODE_CTL */ + write16(0xC008, (((0x0F << num_lanes) & 0x0F) << 12) | 0x0101); + + /* PHY_DP_MODE_CTL */ + while (!(read16(0xC008) & (1 << 4))) + ; + + return 0; +} diff --git a/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.h b/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.h new file mode 100644 index 00000000000..756c1d577e1 --- /dev/null +++ b/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.h @@ -0,0 +1,64 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AFE_t28hpc_hdmitx.h + * + ****************************************************************************** + */ + +#ifndef API_AFE_T28HPC_HDMITX_H_ +#define API_AFE_T28HPC_HDMITX_H_ + +#ifndef __UBOOT__ +#include +#include +#else +#include +#endif +#include "vic_table.h" +#include "API_AFE.h" +#include "externs.h" + +int phy_cfg_t28hpc(int num_lanes, VIC_MODES vic_mode, int bpp, + VIC_PXL_ENCODING_FORMAT format, bool pixel_clk_from_phy); +int hdmi_tx_t28hpc_power_config_seq(int num_lanes); + +#endif diff --git a/drivers/video/imx/hdp/API_AVI.c b/drivers/video/imx/hdp/API_AVI.c new file mode 100644 index 00000000000..d9346f23758 --- /dev/null +++ b/drivers/video/imx/hdp/API_AVI.c @@ -0,0 +1,191 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AVI.c + * + ****************************************************************************** + */ + +#include "API_AVI.h" +#include "API_Infoframe.h" + +CDN_API_STATUS cdn_api_set_avi(VIC_MODES vic_mode, + VIC_PXL_ENCODING_FORMAT color_mode, + BT_TYPE itu_ver) +{ + unsigned int active_slot = vic_table[vic_mode][H_BLANK]; + unsigned int line_width = vic_table[vic_mode][H_TOTAL]; + unsigned int hactive = line_width - active_slot + 1; + unsigned int vactive = vic_table[vic_mode][V_ACTIVE] + 1; + + unsigned int hactive_l = hactive - 256 * ((unsigned int)hactive / 256); + unsigned int hactive_h = hactive / 256; + unsigned int vactive_l = vactive - 256 * ((unsigned int)vactive / 256); + unsigned int vactive_h = vactive / 256; + + /* unsigned int packet; */ + + unsigned int packet_type = 0x82; + unsigned int packet_version = 0x2; + unsigned int packet_len = 0xd; + unsigned int packet_y = 0; + unsigned int packet_c = 0; + unsigned int packet_r = 0; + unsigned int packet_vic = 0; + unsigned int packet_pr = 0; + unsigned int packet_buf[18 / sizeof(unsigned int)]; + unsigned char *packet = (unsigned char *)&packet_buf[0]; + unsigned int packet_hb0 = 0; + unsigned int packet_hb1 = 0; + unsigned int packet_hb2 = 0; + unsigned int packet_pb0 = 0; + unsigned int packet_pb1 = 0; + unsigned int packet_pb2 = 0; + unsigned int packet_pb3 = 0; + unsigned int packet_pb4 = 0; + unsigned int packet_pb5 = 0; + unsigned int packet_pb6 = 0; + unsigned int packet_pb7 = 0; + unsigned int packet_pb8 = 0; + unsigned int packet_pb9 = 0; + unsigned int packet_pb10 = 0; + unsigned int packet_pb11 = 0; + unsigned int packet_pb12 = 0; + unsigned int packet_pb13 = 0; + unsigned int pb1_13_chksum = 0; + unsigned int packet_chksum = 0; + + if (color_mode == PXL_RGB) + packet_y = 0; + else if (color_mode == YCBCR_4_4_4) + packet_y = 2; + else if (color_mode == YCBCR_4_2_2) + packet_y = 1; + else if (color_mode == YCBCR_4_2_0) + packet_y = 3; + + /* Colorimetry: Nodata=0 IT601=1 ITU709=2 */ + if (itu_ver == BT_601) + packet_c = 1; + else if (itu_ver == BT_709) + packet_c = 2; + else + packet_c = 0; + + unsigned int packet_a0 = 1; + unsigned int packet_b = 0; + unsigned int packet_s = 0; + unsigned int packet_sc = 0; /* Picture Scaling */ + + /* Active Format Aspec Ratio: Same As Picture = 0x8 4:3(Center)=0x9 + 16:9=0xA 14:9=0xB */ + packet_r = vic_table[vic_mode][VIC_R3_0]; + /* Aspect Ratio: Nodata=0 4:3=1 16:9=2 */ + unsigned int packet_m = 0; + /* Quantization Range Default=0 Limited Range=0x1 FullRange=0x2 + Reserved 0x3 */ + unsigned int packet_q = 0; + /* Quantization Range 0=Limited Range FullRange=0x1 Reserved 0x3/2 */ + unsigned int packet_yq = 0; + /* Extended Colorimetry xvYCC601=0x0 xvYCC709=1 All other Reserved */ + unsigned int packet_ec = 0; + /*IT content nodata=0 ITcontent=1 */ + unsigned int packet_it = 0; + /* Video Code (CEA) */ + packet_vic = vic_table[vic_mode][VIC]; + /* Pixel Repetition 0 ... 9 (1-10) */ + packet_pr = vic_table[vic_mode][VIC_PR]; + /* Content Type */ + unsigned int packet_cn = 0; + + packet_hb0 = packet_type; + packet_hb1 = packet_version; + packet_hb2 = packet_len; + + packet_pb1 = 32 * packet_y + 16 * packet_a0 + 4 * packet_b + packet_s; + packet_pb2 = 64 * packet_c + 16 * packet_m + packet_r; + packet_pb3 = + 128 * packet_it + 16 * packet_ec + 4 * packet_q + packet_sc; + packet_pb4 = packet_vic; + packet_pb5 = 64 * packet_yq + 16 * packet_cn + packet_pr; + packet_pb6 = 0; + packet_pb7 = 0; + packet_pb8 = vactive_l; + packet_pb9 = vactive_h; + packet_pb10 = 0; + packet_pb11 = 0; + packet_pb12 = hactive_l; + packet_pb13 = hactive_h; + + pb1_13_chksum = + (packet_hb0 + packet_hb1 + packet_hb2 + packet_pb1 + + packet_pb2 + packet_pb3 + packet_pb4 + packet_pb5 + + packet_pb6 + packet_pb7 + packet_pb8 + packet_pb9 + + packet_pb10 + packet_pb11 + packet_pb12 + packet_pb13); + packet_chksum = + 256 - (pb1_13_chksum - + 256 * ((unsigned int)pb1_13_chksum / 256)); + packet_pb0 = packet_chksum; + + packet[0] = 0; + packet[1] = packet_hb0; + packet[2] = packet_hb1; + packet[3] = packet_hb2; + packet[4] = packet_pb0; + packet[5] = packet_pb1; + packet[6] = packet_pb2; + packet[7] = packet_pb3; + packet[8] = packet_pb4; + packet[9] = packet_pb5; + packet[10] = packet_pb6; + packet[11] = packet_pb7; + packet[12] = packet_pb8; + packet[13] = packet_pb9; + packet[14] = packet_pb10; + packet[15] = packet_pb11; + packet[16] = packet_pb12; + packet[17] = packet_pb13; + + cdn_api_infoframeset(0, packet_len, + (unsigned int *)&packet[0], packet_type); + + return CDN_OK; +} /* End API */ diff --git a/drivers/video/imx/hdp/API_AVI.h b/drivers/video/imx/hdp/API_AVI.h new file mode 100644 index 00000000000..435ba3f9f8f --- /dev/null +++ b/drivers/video/imx/hdp/API_AVI.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AVI.h + * + ****************************************************************************** + */ + +#ifndef API_AVI_H_ +#define API_AVI_H_ + +#include "vic_table.h" +#include "API_General.h" + +CDN_API_STATUS cdn_api_set_avi( + VIC_MODES vic_mode, + VIC_PXL_ENCODING_FORMAT color_mode, + BT_TYPE itu_ver); + +#endif /*API_AVI_H_ */ + diff --git a/drivers/video/imx/hdp/API_General.c b/drivers/video/imx/hdp/API_General.c new file mode 100644 index 00000000000..4f08c2be742 --- /dev/null +++ b/drivers/video/imx/hdp/API_General.c @@ -0,0 +1,511 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copyright 2017-2018 NXP + * + ****************************************************************************** + * + * API_General.c + * + ****************************************************************************** + */ + +#include "API_General.h" +#include "util.h" +#ifndef __UBOOT__ +#include +#endif +#include "address.h" +#include "apb_cfg.h" +#include "opcodes.h" +#include "general_handler.h" +#include "externs.h" +#ifndef __UBOOT__ +#include +#endif + +extern state_struct state; + +void cdn_api_init(void) +{ + memset(&state, 0, sizeof(state_struct)); +} + +CDN_API_STATUS hdp_rx_loadfirmware(unsigned char *imem, int imemsize, + unsigned char *dmem, int dmemsize) +{ + int i; + for (i = 0; i < imemsize; i += 4) + if (hdp_rx_apb_write(ADDR_IMEM + i, + (unsigned int)imem[i] << 0 | + (unsigned int)imem[i + 1] << 8 | + (unsigned int)imem[i + 2] << 16 | + (unsigned int)imem[i + 3] << 24)) + return CDN_ERR; + for (i = 0; i < dmemsize; i += 4) + if (hdp_rx_apb_write(ADDR_DMEM + i, + (unsigned int)dmem[i] << 0 | + (unsigned int)dmem[i + 1] << 8 | + (unsigned int)dmem[i + 2] << 16 | + (unsigned int)dmem[i + 3] << 24)) + return CDN_ERR; + return CDN_OK; +} + +CDN_API_STATUS cdn_api_loadfirmware(unsigned char *imem, int imemsize, + unsigned char *dmem, int dmemsize) +{ + int i; + for (i = 0; i < imemsize; i += 4) + if (cdn_apb_write(ADDR_IMEM + i, + (unsigned int)imem[i] << 0 | + (unsigned int)imem[i + 1] << 8 | + (unsigned int)imem[i + 2] << 16 | + (unsigned int)imem[i + 3] << 24)) + return CDN_ERR; + for (i = 0; i < dmemsize; i += 4) + if (cdn_apb_write(ADDR_DMEM + i, + (unsigned int)dmem[i] << 0 | + (unsigned int)dmem[i + 1] << 8 | + (unsigned int)dmem[i + 2] << 16 | + (unsigned int)dmem[i + 3] << 24)) + return CDN_ERR; + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_test_echo(unsigned int val, + CDN_BUS_TYPE bus_type) +{ + CDN_API_STATUS ret; + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + state.bus_type = bus_type; + state.rxenable = 1; + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO, + 1, 4, val); + return CDN_STARTED; + } + if (state.txenable && !internal_mbox_tx_process().txend) + return CDN_BSY; + if (state.rxenable && !internal_mbox_rx_process().rxend) + return CDN_BSY; + ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO); + if (ret != CDN_OK) { + state.running = 0; + return ret; + } + state.running = 0; + if (val != internal_betoi(state.rxbuffer + INTERNAL_CMD_HEAD_SIZE, 4)) + return CDN_ERR; + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_test_echo_blocking(unsigned int val, + CDN_BUS_TYPE bus_type) +{ + internal_block_function(cdn_api_general_test_echo(val, bus_type)); +} + +CDN_API_STATUS cdn_api_general_test_echo_ext(uint8_t const *msg, uint8_t *resp, + uint16_t num_bytes, + CDN_BUS_TYPE bus_type) +{ + CDN_API_STATUS ret; + + if (!msg || !resp) + return CDN_ERR; + + if ((num_bytes > GENERAL_TEST_ECHO_MAX_PAYLOAD) || + (num_bytes < GENERAL_TEST_ECHO_MIN_PAYLOAD)) + return CDN_ERR; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + + state.bus_type = bus_type; + state.rxenable = 1; + + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO, + 1, -num_bytes, msg); + + return CDN_STARTED; + } + + if (state.txenable && !internal_mbox_tx_process().txend) + return CDN_BSY; + + if (state.rxenable && !internal_mbox_rx_process().rxend) + return CDN_BSY; + + ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO); + + if (ret != CDN_OK) { + state.running = 0; + return ret; + } + + state.running = 0; + + memcpy(resp, state.rxbuffer + INTERNAL_CMD_HEAD_SIZE, num_bytes); + + if (memcmp(msg, resp, num_bytes) != 0) + return CDN_ERR; + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_test_echo_ext_blocking(uint8_t const *msg, + uint8_t *resp, + uint16_t num_bytes, + CDN_BUS_TYPE bus_type) +{ + internal_block_function(cdn_api_general_test_echo_ext + (msg, resp, num_bytes, bus_type) + ); +} + +CDN_API_STATUS cdn_api_general_getcurversion(unsigned short *ver, + unsigned short *verlib) +{ + unsigned int vh, vl, vlh, vll; + if (cdn_apb_read(VER_L << 2, &vl)) + return CDN_ERR; + if (cdn_apb_read(VER_H << 2, &vh)) + return CDN_ERR; + if (cdn_apb_read(VER_LIB_L_ADDR << 2, &vll)) + return CDN_ERR; + if (cdn_apb_read(VER_LIB_H_ADDR << 2, &vlh)) + return CDN_ERR; + *ver = F_VER_MSB_RD(vh) << 8 | F_VER_LSB_RD(vl); + *verlib = F_SW_LIB_VER_H_RD(vlh) << 8 | F_SW_LIB_VER_L_RD(vll); + return CDN_OK; +} + +CDN_API_STATUS cdn_api_get_event(uint32_t *events) +{ + uint32_t evt[4] = { 0 }; + + if (!events) { + printf("events pointer is NULL!\n"); + return CDN_ERR; + } + + if (cdn_apb_read(SW_EVENTS0 << 2, &evt[0]) || + cdn_apb_read(SW_EVENTS1 << 2, &evt[1]) || + cdn_apb_read(SW_EVENTS2 << 2, &evt[2]) || + cdn_apb_read(SW_EVENTS3 << 2, &evt[3])) { + printf("Failed to read events registers.\n"); + return CDN_ERR; + } + + *events = (evt[0] & 0xFF) + | ((evt[1] & 0xFF) << 8) + | ((evt[2] & 0xFF) << 16) + | ((evt[3] & 0xFF) << 24); + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_get_debug_reg_val(uint16_t *val) +{ + uint32_t dbg[2] = { 0 }; + + if (!val) { + printf("val pointer is NULL!\n"); + return CDN_ERR; + } + + if (cdn_apb_read(SW_DEBUG_L << 2, &dbg[0]) || + cdn_apb_read(SW_DEBUG_H << 2, &dbg[1])) { + printf("Failed to read debug registers.\n"); + return CDN_ERR; + } + + *val = (uint16_t) ((dbg[0] & 0xFF) | ((dbg[1] & 0xFF) << 8)); + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_checkalive(void) +{ + unsigned int alive, newalive; + uint8_t retries_left = 10; + + if (cdn_apb_read(KEEP_ALIVE << 2, &alive)) + return CDN_ERR; + + while (retries_left--) { + udelay(1); + + if (cdn_apb_read(KEEP_ALIVE << 2, &newalive)) + return CDN_ERR; + + if (alive == newalive) + continue; + + return CDN_OK; + } + + printf("%s: keep-alive counter did not increment for 10us...\n", __func__); + + return CDN_BSY; +} + +CDN_API_STATUS cdn_api_checkalive_blocking(void) +{ + internal_block_function(cdn_api_checkalive()); +} + +CDN_API_STATUS cdn_api_maincontrol(unsigned char mode, unsigned char *resp) +{ + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + state.bus_type = CDN_BUS_TYPE_APB; + state.rxenable = 1; + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, + GENERAL_MAIN_CONTROL, 1, 1, mode); + return CDN_STARTED; + } + INTERNAL_PROCESS_MESSAGES; + internal_opcode_ok_or_return(MB_MODULE_ID_GENERAL, + GENERAL_MAIN_CONTROL_RESP); + internal_readmsg(1, 1, resp); + return CDN_OK; +} + +CDN_API_STATUS cdn_api_maincontrol_blocking(unsigned char mode, + unsigned char *resp) +{ + internal_block_function(cdn_api_maincontrol(mode, resp)); +} + +CDN_API_STATUS cdn_api_apbconf(uint8_t dpcd_bus_sel, uint8_t dpcd_bus_lock, + uint8_t hdcp_bus_sel, uint8_t hdcp_bus_lock, + uint8_t capb_bus_sel, uint8_t capb_bus_lock, + uint8_t *dpcd_resp, uint8_t *hdcp_resp, + uint8_t *capb_resp) +{ + uint8_t resp; + uint8_t set = 0; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + + state.bus_type = CDN_BUS_TYPE_APB; + state.rxenable = 1; + + set |= (dpcd_bus_sel) + ? (1 << GENERAL_BUS_SETTINGS_DPCD_BUS_BIT) + : 0; + set |= (dpcd_bus_lock) + ? (1 << GENERAL_BUS_SETTINGS_DPCD_BUS_LOCK_BIT) + : 0; + set |= (hdcp_bus_sel) + ? (1 << GENERAL_BUS_SETTINGS_HDCP_BUS_BIT) + : 0; + set |= (hdcp_bus_lock) + ? (1 << GENERAL_BUS_SETTINGS_HDCP_BUS_LOCK_BIT) + : 0; + set |= (capb_bus_sel) + ? (1 << GENERAL_BUS_SETTINGS_CAPB_OWNER_BIT) + : 0; + set |= (capb_bus_lock) + ? (1 << GENERAL_BUS_SETTINGS_CAPB_OWNER_LOCK_BIT) + : 0; + + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, + GENERAL_BUS_SETTINGS, 1, 1, set); + + return CDN_STARTED; + } + + INTERNAL_PROCESS_MESSAGES; + internal_opcode_ok_or_return(MB_MODULE_ID_GENERAL, + GENERAL_BUS_SETTINGS_RESP); + + /* Read one one-byte response */ + internal_readmsg(1, 1, &resp); + + *dpcd_resp = + (resp & (1 << GENERAL_BUS_SETTINGS_RESP_DPCD_BUS_BIT)) ? 1 : 0; + *hdcp_resp = + (resp & (1 << GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT)) ? 1 : 0; + *capb_resp = + (resp & (1 << GENERAL_BUS_SETTINGS_RESP_CAPB_OWNER_BIT)) ? 1 : 0; + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_apbconf_blocking(uint8_t dpcd_bus_sel, + uint8_t dpcd_bus_lock, + uint8_t hdcp_bus_sel, + uint8_t hdcp_bus_lock, + uint8_t capb_bus_sel, + uint8_t capb_bus_lock, + uint8_t *dpcd_resp, + uint8_t *hdcp_resp, + uint8_t *capb_resp) +{ + internal_block_function(cdn_api_apbconf(dpcd_bus_sel, dpcd_bus_lock, + hdcp_bus_sel, hdcp_bus_lock, + capb_bus_sel, capb_bus_lock, + dpcd_resp, hdcp_resp, + capb_resp)); +} + +CDN_API_STATUS cdn_api_setclock(unsigned char mhz) +{ + return cdn_apb_write(SW_CLK_H << 2, mhz); +} + +CDN_API_STATUS cdn_api_general_read_register(unsigned int addr, + GENERAL_READ_REGISTER_RESPONSE + *resp) +{ + CDN_API_STATUS ret; + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, + GENERAL_READ_REGISTER, 1, 4, addr); + state.bus_type = CDN_BUS_TYPE_APB; + state.rxenable = 1; + return CDN_STARTED; + } + INTERNAL_PROCESS_MESSAGES; + ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, + GENERAL_READ_REGISTER_RESP); + if (ret != CDN_OK) + return ret; + internal_readmsg(2, 4, &resp->addr, 4, &resp->val); + return CDN_OK; +} + +CDN_API_STATUS +cdn_api_general_read_register_blocking(unsigned int addr, + GENERAL_READ_REGISTER_RESPONSE *resp) +{ + internal_block_function(cdn_api_general_read_register(addr, resp)); +} + +CDN_API_STATUS cdn_api_general_write_register(unsigned int addr, + unsigned int val) +{ + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, + GENERAL_WRITE_REGISTER, 2, 4, addr, 4, + val); + state.bus_type = CDN_BUS_TYPE_APB; + return CDN_STARTED; + } + INTERNAL_PROCESS_MESSAGES; + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_write_register_blocking(unsigned int addr, + unsigned int val) +{ + internal_block_function(cdn_api_general_write_register(addr, val)); +} + +CDN_API_STATUS cdn_api_general_write_field(unsigned int addr, + unsigned char startbit, + unsigned char bitsno, + unsigned int val) +{ + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_WRITE_FIELD, + 4, 4, addr, 1, startbit, 1, bitsno, 4, + val); + state.bus_type = CDN_BUS_TYPE_APB; + return CDN_STARTED; + } + INTERNAL_PROCESS_MESSAGES; + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_write_field_blocking(unsigned int addr, + unsigned char startbit, + unsigned char bitsno, + unsigned int val) +{ + internal_block_function(cdn_api_general_write_field + (addr, startbit, bitsno, val)); +} + +CDN_API_STATUS cdn_api_general_phy_test_access(uint8_t *resp) +{ + CDN_API_STATUS ret; + + *resp = 0; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ACCESS, + 0); + state.bus_type = CDN_BUS_TYPE_APB; + state.rxenable = 1; + + return CDN_STARTED; + } + + INTERNAL_PROCESS_MESSAGES; + + ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ACCESS); + + if (ret != CDN_OK) + return ret; + + internal_readmsg(1, 1, resp); + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_phy_test_access_blocking(uint8_t *resp) +{ + internal_block_function(cdn_api_general_phy_test_access(resp)); +} diff --git a/drivers/video/imx/hdp/API_General.h b/drivers/video/imx/hdp/API_General.h new file mode 100644 index 00000000000..42e4c5c0a79 --- /dev/null +++ b/drivers/video/imx/hdp/API_General.h @@ -0,0 +1,305 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copyright 2017-2018 NXP + * + ****************************************************************************** + * + * API_General.h + * + ****************************************************************************** + */ + +#ifndef API_GENERAL_H_ +#define API_GENERAL_H_ + +#ifndef __UBOOT__ +#include +#else +#include +#endif + +#define GENERAL_TEST_ECHO_MAX_PAYLOAD 100 +#define GENERAL_TEST_ECHO_MIN_PAYLOAD 1 + +/** + * \addtogroup GENERAL_API + * \{ + */ +/** status code returned by API calls */ +typedef enum { + /** operation succedded */ + CDN_OK = 0, + /** CEC operation succedded */ + CDN_CEC_ERR_NONE = 0, + /** mailbox is currently sending or receiving data */ + CDN_BSY, + /** message set up and ready to be sent, no data sent yet */ + CDN_STARTED, + /** error encountered while reading/writing APB */ + CDN_ERR, + /** reply returned with bad opcode */ + CDN_BAD_OPCODE, + /** reply returned with bad module */ + CDN_BAD_MODULE, + /** reply not supported mode */ + CDN_ERROR_NOT_SUPPORTED, + /** Invalid argument passed to CEC API function */ + CDN_CEC_ERR_INVALID_ARG, + /** + * TX Buffer for CEC Messages is full. This is applicable only + * when TX Buffers for CEC Messages are implemented in the HW. + */ + CDN_CEC_ERR_TX_BUFF_FULL, + /** No Messages in the RX Buffers are present. */ + CDN_CEC_ERR_RX_BUFF_EMPTY, + /** Timeout during TX operation */ + CDN_CEC_ERR_TX_TIMEOUT, + /** Timeout during RX operation */ + CDN_CEC_ERR_RX_TIMEOUT, + /** Data transmision fail. */ + CDN_CEC_ERR_TX_FAILED, + /** Data reception fail. */ + CDN_CEC_ERR_RX_FAILED, + /** Operation aborted. */ + CDN_CEC_ERR_ABORT, + /** All Logical Addresses are in use. */ + CDN_CEC_ERR_ALL_LA_IN_USE, +} CDN_API_STATUS; + +typedef enum { + CDN_BUS_TYPE_APB = 0, + CDN_BUS_TYPE_SAPB = 1 +} CDN_BUS_TYPE; + +/** + * GENERAL_Read_Register response struct + */ +typedef struct { + unsigned int addr; + unsigned int val; +} GENERAL_READ_REGISTER_RESPONSE; + +/** + * \brief set up API, must be called before any other API call + */ +void cdn_api_init(void); + +/** + * \brief Loads firmware + * + * \param iMem - pointer to instruction memory + * \param imemSize - size of instruction memory buffer + * \param dMem - pointer to data memory + * \param dmemSize - size of data memory buffer + * \return 0 if success, 1 if apb error encountered, 2 if CPU + * isn't alive after loading firmware + * + * This function does not require initialisation by #CDN_API_Init + */ + +CDN_API_STATUS cdn_api_loadfirmware(unsigned char *imem, + int imemsize, + unsigned char *dmem, int dmemsize); +/** + * \brief debug echo command for APB + * \param val - value to echo + * \return status + * + * will return #CDN_ERROR if reply message doesn't match request + */ +CDN_API_STATUS cdn_api_general_test_echo(unsigned int val, + CDN_BUS_TYPE bus_type); + +/** + * \brief blocking version of #CDN_API_General_Test_Echo + */ +CDN_API_STATUS cdn_api_general_test_echo_blocking(unsigned int val, + CDN_BUS_TYPE bus_type); + +/** + * \brief Extended Echo test for mailbox. + * + * This test will send msg buffer to firmware's mailbox and + * receive it back to the resp buffer. Received data will be + * check against data sent and status will be returned as well + * as received data. + * + * \param msg - Pointer to a buffer to send. + * \param resp - Pointer to buffer for receiving msg payload back. + * \param num_bytes - Number of bytes to send and receive. + * \param bus_type Bus type. + * \return status + * + * will return #CDN_ERROR if reply message doesn't match request or if + * arguments are invalid. + */ +CDN_API_STATUS cdn_api_general_test_echo_ext(uint8_t const *msg, uint8_t *resp, + uint16_t num_bytes, + CDN_BUS_TYPE bus_type); + +/** + * \brief blocking version of #CDN_API_General_Test_Echo_Ext + */ +CDN_API_STATUS cdn_api_general_test_echo_ext_blocking(uint8_t const *msg, + uint8_t *resp, + uint16_t num_bytes, + CDN_BUS_TYPE bus_type); + +/** + * \brief get current version + * \param [out] ver - fw version + * \param [out] libver - lib version + * \return status + * + * this fucntion does not require #CDN_API_Init + */ +CDN_API_STATUS cdn_api_general_getcurversion(unsigned short *ver, + unsigned short *verlib); + +/** + * \brief read event value + * \param [out] event - pointer to store 32-bit events value + * \return status + * + * this function does not require #CDN_API_Init + */ +CDN_API_STATUS cdn_api_get_event(uint32_t *events); + +/** + * \brief read debug register value + * \param [out] val - pointer to store 16-bit debug reg value + * \return status + * + * this function does not require #CDN_API_Init + */ +CDN_API_STATUS cdn_api_get_debug_reg_val(uint16_t *val); + +/** + * \brief check if KEEP_ALIVE register changed + * \return #CDN_BSY if KEEP_ALIVE not changed, #CDN_OK if changed and #CDN_ERR + * if error occured while reading + */ +CDN_API_STATUS cdn_api_checkalive(void); + +/** + * \breif blocking version of #CDN_API_CheckAlive + * blocks untill KEEP_ALIVE register changes or error occurs while reading + */ +CDN_API_STATUS cdn_api_checkalive_blocking(void); + +/** + * \brief set cpu to standby or active + * \param [in] state - 1 for active, 0 for standby + * \return status + */ +CDN_API_STATUS cdn_api_maincontrol(unsigned char mode, unsigned char *resp); + +/** + * \breif blocking version of #CDN_API_MainControl + */ +CDN_API_STATUS cdn_api_maincontrol_blocking(unsigned char mode, + unsigned char *resp); + +/** + * \brief settings for APB + * + * Sends GENERAL_APB_CONF Command via regular Mailbox. + * @param dpcd_bus_sel Set DPCD to use selected bus (0 for APB or 1 for SAPB) + * @param dpcd_bus_lock Lock bus type. Aftern that bus type cannot be changed + * by using this function. + * @param hdcp_bus_sel Same meaning as for DPCD but for HDCP. + * @param hdcp_bus_lock Same meaning as for DPCD but for HDCP. + * @param capb_bus_sel Same meaning as for DPCD but for Cipher APB. + * @param capb_bus_lock Same meaning as for DPCD but for Cipher APB. + * @param dpcd_resp [out] Status of the operation. + * If set to zero then DPCD bus type was successfuly changed. + * If not then error occurred, most likely due to locked DPCD bus. + * @param hdcp_resp [out] Same as for DPCD but for HDCP. + * @param capb_resp [out] Same as for DPCD but for Cipher APB. + * + * \return status + */ +CDN_API_STATUS cdn_api_apbconf(uint8_t dpcd_bus_sel, uint8_t dpcd_bus_lock, + uint8_t hdcp_bus_sel, uint8_t hdcp_bus_lock, + uint8_t capb_bus_sel, uint8_t capb_bus_lock, + uint8_t *dpcd_resp, uint8_t *hdcp_resp, + uint8_t *capb_resp); + +/** + * blocking version of #CDN_API_MainControl + */ +CDN_API_STATUS cdn_api_apbconf_blocking(uint8_t dpcd_bus_sel, + uint8_t dpcd_bus_lock, + uint8_t hdcp_bus_sel, + uint8_t hdcp_bus_lock, + uint8_t capb_bus_sel, + uint8_t capb_bus_lock, + uint8_t *dpcd_resp, + uint8_t *hdcp_resp, + uint8_t *capb_resp); + +/** + * \brief set the xtensa clk, write this api before turn on the cpu + */ +CDN_API_STATUS cdn_api_setclock(unsigned char mhz); + +CDN_API_STATUS cdn_api_general_read_register(unsigned int addr, + GENERAL_READ_REGISTER_RESPONSE + *resp); +CDN_API_STATUS +cdn_api_general_read_register_blocking(unsigned int addr, + GENERAL_READ_REGISTER_RESPONSE *resp); +CDN_API_STATUS cdn_api_general_write_register(unsigned int addr, + unsigned int val); +CDN_API_STATUS cdn_api_general_write_register_blocking(unsigned int addr, + unsigned int val); +CDN_API_STATUS cdn_api_general_write_field(unsigned int addr, + unsigned char startbit, + unsigned char bitsno, + unsigned int val); +CDN_API_STATUS cdn_api_general_write_field_blocking(unsigned int addr, + unsigned char startbit, + unsigned char bitsno, + unsigned int val); +CDN_API_STATUS cdn_api_general_phy_test_access(uint8_t *resp); +CDN_API_STATUS cdn_api_general_phy_test_access_blocking(uint8_t *resp); +CDN_API_STATUS hdp_rx_loadfirmware(unsigned char *imem, + int imemsize, + unsigned char *dmem, int dmemsize); + +#endif diff --git a/drivers/video/imx/hdp/API_HDMITX.c b/drivers/video/imx/hdp/API_HDMITX.c new file mode 100644 index 00000000000..b1b3061028d --- /dev/null +++ b/drivers/video/imx/hdp/API_HDMITX.c @@ -0,0 +1,486 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_HDMITX.c + * + ****************************************************************************** + */ + +#include "API_HDMITX.h" +#include "util.h" +#include "opcodes.h" +#ifndef __UBOOT__ +#include "string.h" +#include "stdio.h" +#endif +#include "mhl_hdtx_top.h" +#include "source_phy.h" +#include "address.h" +#include "source_car.h" +#include "source_vif.h" +#include "general_handler.h" + +CDN_API_STATUS CDN_API_HDMITX_DDC_READ(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out) +{ + internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_READ, + CDN_BUS_TYPE_APB, 3, + 1, data_in->slave, + 1, data_in->offset, + 2, data_in->len + ); + internal_readmsg(5, + 1, &data_out->status, + 1, &data_out->slave, + 1, &data_out->offset, + 2, &data_out->len, + 0, &data_out->buff + ); + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_DDC_READ_blocking(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out) +{ + internal_block_function(CDN_API_HDMITX_DDC_READ(data_in, data_out)); +} + +CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out) +{ + printf("foo: %x\n", data_in->buff[0]); + internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE, + CDN_BUS_TYPE_APB, 4, + 1, data_in->slave, + 1, data_in->offset, + 2, data_in->len, + -data_in->len, data_in->buff + ); + internal_readmsg(4, + 1, &data_out->status, + 1, &data_out->slave, + 1, &data_out->offset, + 2, &data_out->len + ); + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE_blocking(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out) +{ + internal_block_function(CDN_API_HDMITX_DDC_WRITE(data_in, data_out)); +} + +CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ(HDMITX_TRANS_DATA *data_out) +{ + internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_UPDATE_READ, + CDN_BUS_TYPE_APB, 0); + internal_readmsg(2, + 1, &data_out->status, + 0, &data_out->buff + ); + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ_blocking(HDMITX_TRANS_DATA + *data_out) +{ + internal_block_function(CDN_API_HDMITX_DDC_UPDATE_READ(data_out)); +} + +CDN_API_STATUS CDN_API_HDMITX_READ_EDID(unsigned char block, + unsigned char segment, + HDMITX_TRANS_DATA *data_out) +{ + internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID, + CDN_BUS_TYPE_APB, 2, + 1, block, + 1, segment + ); + internal_readmsg(5, + 1, &data_out->status, + 1, &data_out->slave, + 1, &data_out->offset, + 2, &data_out->len, + 0, &data_out->buff + ); + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_READ_EDID_blocking(unsigned char block, + unsigned char segment, + HDMITX_TRANS_DATA *data_out) +{ + internal_block_function(CDN_API_HDMITX_READ_EDID(block, segment, + data_out)); +} + +CDN_API_STATUS +CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol, + unsigned int character_rate) +{ + CDN_API_STATUS ret; + GENERAL_READ_REGISTER_RESPONSE resp; + HDMITX_TRANS_DATA data_in; + HDMITX_TRANS_DATA data_out; + unsigned char buff = 1; + + /*enable/disable scrambler; */ + if (protocol == HDMI_TX_MODE_HDMI_2_0) { + if (character_rate > 340000) + buff = 3; /*enable scrambling + TMDS_Bit_Clock_Ratio */ + else + buff = 1; /*enable scrambling */ + } else { + buff = 0; /*disable scrambling */ + } + + data_in.buff = &buff; + data_in.len = 1; + data_in.slave = 0x54; + data_in.offset = 0x20; /*TMDS config */ +#if 1 + if (protocol == HDMI_TX_MODE_HDMI_2_0) + ret = CDN_API_HDMITX_DDC_WRITE_blocking(&data_in, &data_out); + +#endif + ret = cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + &resp); + + /*remove data enable */ + resp.val = resp.val & (~(F_DATA_EN(1))); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + if (protocol == HDMI_TX_MODE_HDMI_2_0) { + if (character_rate > 3400000) { + /* Set TMDS clock ratio */ + ret = cdn_api_general_write_register_blocking + (ADDR_SOURCE_MHL_HD + + (HDTX_CLOCK_REG_0 << 2), + F_DATA_REGISTER_VAL_0(0x00000)); + ret = cdn_api_general_write_register_blocking + (ADDR_SOURCE_MHL_HD + + (HDTX_CLOCK_REG_1 << 2), + F_DATA_REGISTER_VAL_1(0xFFFFF)); + } + } + + /*set hdmi mode and preemble mode */ + resp.val = resp.val & (~(F_HDMI_MODE(3))); + resp.val = resp.val & (~(F_HDMI2_PREAMBLE_EN(1))); + + resp.val = (resp.val) | (F_HDMI_MODE(protocol)) | + (F_HDMI2_PREAMBLE_EN(1)); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + /*data enable */ + resp.val |= F_DATA_EN(1); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + return ret; +} + +CDN_API_STATUS CDN_API_HDMITX_Init_blocking(void) +{ + CDN_API_STATUS ret; + + /*init phy and CAR and HDMI TX */ +/* ret = cdn_api_general_write_register_blocking + (ADDR_SOURCD_PHY + (LANES_CONFIG<<2), + F_SOURCE_PHY_LANE0_SWAP(0) | + F_SOURCE_PHY_LANE1_SWAP(1) | + F_SOURCE_PHY_LANE2_SWAP(2) | + F_SOURCE_PHY_LANE3_SWAP(3) | + F_SOURCE_PHY_COMB_BYPASS(0) | + F_SOURCE_PHY_20_10(1)); */ + + ret = cdn_api_general_write_register_blocking(ADDR_SOURCD_PHY + + (PHY_DATA_SEL << 2), + F_SOURCE_PHY_MHDP_SEL(1)); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_HPD << 2), + F_HPD_VALID_WIDTH(4) | + F_HPD_GLITCH_WIDTH(0)); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + F_HDMI_MODE(1) | + F_AUTO_MODE(0) | + F_GCP_EN(1) | + F_DATA_EN(1) | + F_CLEAR_AVMUTE(1) | + F_HDMI2_PREAMBLE_EN(1) | + F_HDMI2_CTRL_IL_MODE(1) | + F_PIC_3D(0XF) | + F_BCH_EN(1)); + /* open CARS */ + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_PHY_CAR << 2), + 0xF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_HDTX_CAR << 2), + 0xFF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_PKT_CAR << 2), + 0xF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_AIF_CAR << 2), + 0xF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_CIPHER_CAR << 2), + 0xF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_CRYPTO_CAR << 2), + 0xF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_CEC_CAR << 2), 3); + + /*init vif */ + /*ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_VIF + +(HSYNC2VSYNC_POL_CTRL<<2), F_HPOL(0) | F_VPOL(0)); */ + + return ret; +} + + +CDN_API_STATUS CDN_API_HDMITX_SetVic_blocking(VIC_MODES vicMode, int bpp, + VIC_PXL_ENCODING_FORMAT format) +{ + CDN_API_STATUS ret; + GENERAL_READ_REGISTER_RESPONSE resp; + unsigned int vsync_lines = vic_table[vicMode][VSYNC]; + unsigned int eof_lines = vic_table[vicMode][TYPE_EOF]; + unsigned int sof_lines = vic_table[vicMode][SOF]; + unsigned int hblank = vic_table[vicMode][H_BLANK]; + unsigned int hactive = vic_table[vicMode][H_TOTAL] - hblank; + unsigned int vblank = vsync_lines + eof_lines + sof_lines; + unsigned int vactive = vic_table[vicMode][V_TOTAL] - vblank; + unsigned int hfront = vic_table[vicMode][FRONT_PORCH]; + unsigned int hback = vic_table[vicMode][BACK_PORCH]; + unsigned int vfront = eof_lines; + unsigned int hsync = hblank - hfront - hback; + unsigned int vsync = vsync_lines; + unsigned int vback = sof_lines; + unsigned int v_h_polarity = ((vic_table[vicMode][HSYNC_POL] == + ACTIVE_LOW) ? 0 : 1) + + ((vic_table[vicMode][VSYNC_POL] == ACTIVE_LOW) ? 0 : 2); + + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (SCHEDULER_H_SIZE << 2), + (hactive << 16) + hblank); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (SCHEDULER_V_SIZE << 2), + (vactive << 16) + vblank); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_SIGNAL_FRONT_WIDTH + << 2), + (vfront << 16) + hfront); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_SIGNAL_SYNC_WIDTH + << 2), + (vsync << 16) + hsync); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_SIGNAL_BACK_WIDTH + << 2), + (vback << 16) + hback); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_VIF + + (HSYNC2VSYNC_POL_CTRL + << 2), + v_h_polarity); + + /* Data Enable is 1 */ + + /*Reset Data Enable */ + cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), &resp); + + /*reset data enable */ + resp.val = resp.val & (~(F_DATA_EN(1))); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + /*set bpp */ + resp.val = resp.val & (~(F_VIF_DATA_WIDTH(3))); + switch (bpp) { + case 8: + resp.val = resp.val | (F_VIF_DATA_WIDTH(0)); + break; + + case 10: + resp.val = resp.val | (F_VIF_DATA_WIDTH(1)); + break; + + case 12: + resp.val = resp.val | (F_VIF_DATA_WIDTH(2)); + break; + + case 16: + resp.val = resp.val | (F_VIF_DATA_WIDTH(3)); + break; + } + + /*select color encoding */ + resp.val = resp.val & (~(F_HDMI_ENCODING(3))); + switch (format) { + case PXL_RGB: + + resp.val = resp.val | (F_HDMI_ENCODING(0)); + break; + + case YCBCR_4_4_4: + resp.val = resp.val | (F_HDMI_ENCODING(2)); + break; + + case YCBCR_4_2_2: + resp.val = resp.val | (F_HDMI_ENCODING(1)); + break; + + case YCBCR_4_2_0: + resp.val = resp.val | (F_HDMI_ENCODING(3)); + break; + case Y_ONLY: + /*not exist in hdmi */ + break; + } + + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + /*set data enable */ + resp.val = resp.val | (F_DATA_EN(1)); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + return ret; +} + +CDN_API_STATUS CDN_API_HDMITX_ForceColorDepth_blocking(unsigned char force, + unsigned char val) +{ + unsigned int valToWrite = F_COLOR_DEPTH_VAL(val) | + F_COLOR_DEPTH_FORCE(force); + + return cdn_api_general_write_register_blocking + (ADDR_SOURCE_MHL_HD + + (GCP_FORCE_COLOR_DEPTH_CODING << 2), + valToWrite); +} + +CDN_API_STATUS CDN_API_HDMITX_ReadEvents(uint32_t *events) +{ + CDN_API_STATUS ret; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + + internal_tx_mkfullmsg(MB_MODULE_ID_HDMI_TX, HDMI_TX_EVENTS, 0); + state.rxenable = 1; + state.bus_type = CDN_BUS_TYPE_APB; + + return CDN_STARTED; + } + + INTERNAL_PROCESS_MESSAGES; + + ret = internal_test_rx_head(MB_MODULE_ID_HDMI_TX, HDMI_TX_EVENTS); + + if (ret != CDN_OK) + return ret; + + internal_readmsg(1, 4, events); + + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_ReadEvents_blocking(uint32_t *events) +{ + internal_block_function(CDN_API_HDMITX_ReadEvents(events)); +} + +CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus(uint8_t *hpd_sts) +{ + CDN_API_STATUS ret; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + + /* + * General Module is used here for obtaining HPD State because + * HDMI TX Module is inactive in stand-by mode, thus cannot + * return it. + */ + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, + GENERAL_GET_HPD_STATE, 0); + state.rxenable = 1; + state.bus_type = CDN_BUS_TYPE_APB; + + return CDN_STARTED; + } + + INTERNAL_PROCESS_MESSAGES; + + ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, + GENERAL_GET_HPD_STATE); + + if (ret != CDN_OK) + return ret; + + internal_readmsg(1, 1, hpd_sts); + + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus_blocking(uint8_t *hpd_sts) +{ + internal_block_function(CDN_API_HDMITX_GetHpdStatus(hpd_sts)); +} + diff --git a/drivers/video/imx/hdp/API_HDMITX.h b/drivers/video/imx/hdp/API_HDMITX.h new file mode 100644 index 00000000000..099fd118714 --- /dev/null +++ b/drivers/video/imx/hdp/API_HDMITX.h @@ -0,0 +1,182 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_HDMITX.h + * + ****************************************************************************** + */ + +#ifndef _API_HDMITX_H_ +# define _API_HDMITX_H_ + +# include "API_General.h" +# include "hdmi.h" +# include "vic_table.h" + +/** + * \addtogroup HDMI_TX_API + * \{ + */ + +# define HDMI_TX_EVENT_CODE_HPD_HIGH 0x01 +# define HDMI_TX_EVENT_CODE_HPD_LOW 0x02 +# define HDMI_TX_EVENT_CODE_HPD_STATE_LOW 0x00 +# define HDMI_TX_EVENT_CODE_HPD_STATE_HIGH 0x08 + +typedef struct { + /** if used to return data, this pointer is set (instead of being a + * destination to copy data to + */ + unsigned char *buff; + HDMI_I2C_STATUS status; + unsigned short len; + unsigned char slave; + unsigned char offset; +} HDMITX_TRANS_DATA; + + +typedef enum { + HDMI_TX_MODE_DVI, + HDMI_TX_MODE_HDMI_1_4, + HDMI_TX_MODE_HDMI_2_0, +} HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE; + +/** + * \brief I2C read transaction + * \param [in] data_in - fields used: len, slave, offset + * \param [out] data_out - fields used: all + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_DDC_READ(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out); +CDN_API_STATUS CDN_API_HDMITX_DDC_READ_blocking(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out); + +/** + * \brief I2C write transaction + * \param [in] data_in - fields used: len, slave, offset, buff + * \param [out] data_out - fields used: status, len, slave, offset + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out); +CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE_blocking(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out); + +/** + * \brief I2C update read + * \param [out] data_out - fields used: status, buff + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ(HDMITX_TRANS_DATA *data_out); +CDN_API_STATUS +CDN_API_HDMITX_DDC_UPDATE_READ_blocking(HDMITX_TRANS_DATA *data_out); + +/** + * \brief I2C read edid + * \param [in] block - EDID block + * \pram [in] segment - EDID segment + * \param [out] data_out - fields used: status, buff, slave (as block), + * offset (as segment), len + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_READ_EDID(unsigned char block, + unsigned char segment, + HDMITX_TRANS_DATA *data_out); +CDN_API_STATUS CDN_API_HDMITX_READ_EDID_blocking(unsigned char block, + unsigned char segment, + HDMITX_TRANS_DATA *data_out); + +/** + * \brief set hdmi protocol type (DVI,1.x,2.x) (send scrambler command over + * scdc and set bits in controller) + * \param [in] protocol - type + * \returns status + */ +/*CDN_API_STATUS +CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol, + float character_rate);*/ +CDN_API_STATUS +CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol, + unsigned int character_rate); +/** + * \brief init hdmi registers + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_Init_blocking(void); + +/** + * \brief change to vid id vicMode + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_SetVic_blocking(VIC_MODES vicMode, + int bpp, + VIC_PXL_ENCODING_FORMAT format); + +/** + * \brief option to force color depth in the gcp or not force (HW mode) + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_ForceColorDepth_blocking(unsigned char force, + unsigned char val); + +/** + * \brief send HDMI_TX_TX_READ_EVENTS command + */ +CDN_API_STATUS CDN_API_HDMITX_ReadEvents(uint32_t *events); + +/** + * blocking version of #CDN_API_HDMITX_ReadEvents + */ +CDN_API_STATUS CDN_API_HDMITX_ReadEvents_blocking(uint32_t *events); + +/** + * \brief get current HPD status + */ +CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus(uint8_t *hpd_sts); + +/** + * \brief blocking version of #CDN_API_HDMITX_GetHpdStatus + */ +CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus_blocking(uint8_t *hpd_sts); + +#endif + diff --git a/drivers/video/imx/hdp/API_Infoframe.c b/drivers/video/imx/hdp/API_Infoframe.c new file mode 100644 index 00000000000..acd9612d4a5 --- /dev/null +++ b/drivers/video/imx/hdp/API_Infoframe.c @@ -0,0 +1,157 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_Infoframe.c + * + ****************************************************************************** + */ + +#include "API_Infoframe.h" +#include "address.h" +#include "source_pif.h" +#include "externs.h" +#ifndef __UBOOT__ +#include +#include +#include +#else +#include +#include +#endif +#include "util.h" + +#define BANK_OFFSET 0x0 + +/* Redefined because of compiler warnings about 32 bit shift left */ +#ifdef F_DATA_WR +#undef F_DATA_WR +#define F_DATA_WR(a_) ((uint32_t)(a_)) +#endif + +static CDN_API_STATUS infoframeSet(unsigned char entry_id, + unsigned char packet_len, + unsigned int *packet, + unsigned char packet_type, + unsigned char active_idle) +{ + unsigned int idx; + unsigned int activeIdleBit = (0 == active_idle) ? 0 : 0x20000; + /*invalidate entry */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_REG << 2), + activeIdleBit | F_PKT_ALLOC_ADDRESS(entry_id))) + return CDN_ERR; + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_WR_EN << 2), + F_PKT_ALLOC_WR_EN(1))) + return CDN_ERR; + + /*flush fifo 1 */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_FIFO1_FLUSH << 2), + F_FIFO1_FLUSH(1))) + return CDN_ERR; + + /*write packet into memory */ + for (idx = 0; idx < packet_len; idx++) + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_DATA_WR << 2), + F_DATA_WR(packet[idx]))) + return CDN_ERR; + + /*write entry id */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_WR_ADDR << 2), + F_WR_ADDR(entry_id))) + return CDN_ERR; + + /*write request */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_WR_REQ << 2), + F_HOST_WR(1))) + return CDN_ERR; + + /*update entry */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_REG << 2), + activeIdleBit | F_TYPE_VALID(1) | + F_PACKET_TYPE(packet_type) | + F_PKT_ALLOC_ADDRESS(entry_id))) + return CDN_ERR; + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_WR_EN << 2), + F_PKT_ALLOC_WR_EN(1))) + return CDN_ERR; + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_infoframeset(unsigned char entry_id, + unsigned char packet_len, + unsigned int *packet, + unsigned char packet_type) +{ + return infoframeSet(entry_id, packet_len, packet, packet_type, 1); +} + +CDN_API_STATUS cdn_api_infoframesetnoactiveidle(unsigned char entry_id, + unsigned char packet_len, + unsigned int *packet, + unsigned char packet_type) +{ + return infoframeSet(entry_id, packet_len, packet, packet_type, 0); +} + +CDN_API_STATUS cdn_api_infoframeremove(unsigned char entry_id) +{ + /*invalidate entry */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_REG << 2), + 0x20000 | F_PKT_ALLOC_ADDRESS(entry_id))) + return CDN_ERR; + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_WR_EN << 2), + F_PKT_ALLOC_WR_EN(1))) + return CDN_ERR; + + return CDN_OK; +} + diff --git a/drivers/video/imx/hdp/API_Infoframe.h b/drivers/video/imx/hdp/API_Infoframe.h new file mode 100644 index 00000000000..a384bb2a600 --- /dev/null +++ b/drivers/video/imx/hdp/API_Infoframe.h @@ -0,0 +1,68 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_Infoframe.h + * + ****************************************************************************** + */ + +#ifndef API_INFOFRAME_H +# define API_INFOFRAME_H + +/** + * \addtogroup INFO_FRAME_API + * \{ + */ + +# include "API_General.h" + +CDN_API_STATUS cdn_api_infoframeset(unsigned char entry_id, + unsigned char packet_len, + unsigned int *packet, + unsigned char packet_type); +CDN_API_STATUS cdn_api_infoframesetnoactiveidle(unsigned char entry_id, + unsigned char packet_len, + unsigned int *packet, + unsigned char packet_type); +CDN_API_STATUS cdn_api_infoframeremove(unsigned char entry_id); + +#endif + diff --git a/drivers/video/imx/hdp/Makefile b/drivers/video/imx/hdp/Makefile new file mode 100644 index 00000000000..d704b73201c --- /dev/null +++ b/drivers/video/imx/hdp/Makefile @@ -0,0 +1,49 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-$(CONFIG_VIDEO_IMX_HDP_LOAD) += API_General.o util.o test_base_sw.o + +obj-$(CONFIG_VIDEO_IMX8_HDMI) += \ + API_General.o \ + test_base_sw.o \ + API_AVI.o \ + API_Infoframe.o \ + util.o \ + vic_table.o \ + edid_parser.o \ + API_AFE.o \ + API_HDMITX.o \ + API_AFE_t28hpc_hdmitx.o + +# common objects +#obj-y += \ +# API_General.o API_AVI.o API_Infoframe.o \ +# util.o vic_table.o test_base_sw.o \ +# avgen_drv.o edid_parser.o \ +# API_AFE.o + +#DP objects +# API_DPTX.o \ +# API_AFE_mcu2_dp.o\ +# mhdp_firmware.o + +#hdmi objects +#obj-y += \ +# API_HDMITX.o \ +# API_HDCP.o \ +# API_AFE_t28hpc_hdmitx.o +# + +# USE for QM +# blob/API_AFE_mcu1_dp.o +# blob/API_AFE_ss28fdsoi_kiran_hdmitx.o +# blob/ss28fdsoi_hdmitx_table.o +# blob/hdmitx_firmware.o +# blob/mhdp_firmware.o + +# Use for mscale +# API_AFE_mcu2_dp.o () +# API_AFE_t28hpc_hdmitx.c +# diff --git a/drivers/video/imx/hdp/address.h b/drivers/video/imx/hdp/address.h new file mode 100644 index 00000000000..327e7a90e4c --- /dev/null +++ b/drivers/video/imx/hdp/address.h @@ -0,0 +1,109 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copyright 2017 NXP + * + ****************************************************************************** + * + * address.h + * + ****************************************************************************** + */ + +#ifndef ADDRESS_H_ +# define ADDRESS_H_ + +# define ADDR_IMEM 0x10000 +# define ADDR_DMEM 0x20000 +# define ADDR_CIPHER 0x60000 +# define BASE_CIPHER 0x600 +# define ADDR_APB_CFG 0x00000 +# define BASE_APB_CFG 0x000 +# define ADDR_SOURCE_AIF_DECODER 0x30000 +# define BASE_SOURCE_AIF_DECODER 0x300 +# define ADDR_SOURCE_AIF_SMPL2PCKT 0x30080 +# define BASE_SOURCE_AIF_SMPL2PCKT 0x300 +# define ADDR_AIF_ENCODER 0x30000 +# define BASE_AIF_ENCODER 0x300 +# define ADDR_SOURCE_PIF 0x30800 +# define BASE_SOURCE_PIF 0x308 +# define ADDR_SINK_PIF 0x30800 +# define BASE_SINK_PIF 0x308 +# define ADDR_APB_CFG 0x00000 +# define BASE_APB_CFG 0x000 +# define ADDR_SOURCE_CSC 0x40000 +# define BASE_SOURCE_CSC 0x400 +# define ADDR_UCPU_CFG 0x00000 +# define BASE_UCPU_CFG 0x000 +# define ADDR_SOURCE_CAR 0x00900 +# define BASE_SOURCE_CAR 0x009 +# define ADDR_SINK_CAR 0x00900 +# define BASE_SINK_CAR 0x009 +# define ADDR_CLOCK_METERS 0x00A00 +# define BASE_CLOCK_METERS 0x00A +# define ADDR_SOURCE_VIF 0x00b00 +# define BASE_SOURCE_VIF 0x00b +# define ADDR_SINK_MHL_HD 0x01000 +# define ADDR_SINK_VIDEO_HD 0x01800 +# define BASE_SINK_MHL_HD 0x010 +# define ADDR_SINK_CORE 0x07800 +# define BASE_SINK_CORE 0x078 +# define ADDR_DPTX_PHY 0x02000 +# define BASE_DPTX_PHY 0x020 +# define ADDR_DPTX_HPD 0x02100 +# define BASE_DPTX_HPD 0x021 +# define ADDR_DPTX_FRAMER 0x02200 +# define BASE_DPTX_FRAMER 0x022 +# define ADDR_DPTX_STREAM 0x02200 +# define BASE_DPTX_STREAM 0x022 +# define ADDR_DPTX_GLBL 0x02300 +# define BASE_DPTX_GLBL 0x023 +# define ADDR_DPTX_HDCP 0x02400 +# define BASE_DPTX_HDCP 0x024 +# define ADDR_DP_AUX 0x02800 +# define BASE_DP_AUX 0x028 +# define ADDR_CRYPTO 0x05800 +# define BASE_CRYPTO 0x058 +# define ADDR_CIPHER 0x60000 +# define BASE_CIPHER 0x600 +# define ADDR_SOURCE_MHL_HD 0x01000 + +# define ADDR_AFE (0x20000 * 4) +# define ADDR_SOURCD_PHY (0x800) + +#endif + diff --git a/drivers/video/imx/hdp/apb_cfg.h b/drivers/video/imx/hdp/apb_cfg.h new file mode 100644 index 00000000000..572ab07b94d --- /dev/null +++ b/drivers/video/imx/hdp/apb_cfg.h @@ -0,0 +1,185 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copyright 2017-2018 NXP + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * apb_cfg.h + * + ****************************************************************************** + */ + +#ifndef APB_CFG_H_ +#define APB_CFG_H_ + +/* register APB_CTRL */ +#define APB_CTRL 0 +#define F_APB_XT_RESET(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_APB_XT_RESET_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_APB_DRAM_PATH(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_APB_DRAM_PATH_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_APB_IRAM_PATH(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_APB_IRAM_PATH_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) + +/* register XT_INT_CTRL */ +#define XT_INT_CTRL 1 +#define F_XT_INT_POLARITY(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_XT_INT_POLARITY_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) + +/* register MAILBOX_FULL_ADDR */ +#define MAILBOX_FULL_ADDR 2 +#define F_MAILBOX_FULL(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_MAILBOX_FULL_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register MAILBOX_EMPTY_ADDR */ +#define MAILBOX_EMPTY_ADDR 3 +#define F_MAILBOX_EMPTY(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_MAILBOX_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register MAILBOX0_WR_DATA */ +#define MAILBOX0_WR_DATA 4 +#define F_MAILBOX0_WR_DATA(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_MAILBOX0_WR_DATA_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register MAILBOX0_RD_DATA */ +#define MAILBOX0_RD_DATA 5 +#define F_MAILBOX0_RD_DATA(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_MAILBOX0_RD_DATA_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register KEEP_ALIVE */ +#define KEEP_ALIVE 6 +#define F_KEEP_ALIVE_CNT(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_KEEP_ALIVE_CNT_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register VER_L */ +#define VER_L 7 +#define F_VER_LSB(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_VER_LSB_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register VER_H */ +#define VER_H 8 +#define F_VER_MSB(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_VER_MSB_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register VER_LIB_L_ADDR */ +#define VER_LIB_L_ADDR 9 +#define F_SW_LIB_VER_L(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_LIB_VER_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register VER_LIB_H_ADDR */ +#define VER_LIB_H_ADDR 10 +#define F_SW_LIB_VER_H(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_LIB_VER_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_DEBUG_L */ +#define SW_DEBUG_L 11 +#define F_SW_DEBUG_7_0(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_DEBUG_7_0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_DEBUG_H */ +#define SW_DEBUG_H 12 +#define F_SW_DEBUG_15_8(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_DEBUG_15_8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register MAILBOX_INT_MASK */ +#define MAILBOX_INT_MASK 13 +#define F_MAILBOX_INT_MASK(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_MAILBOX_INT_MASK_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) + +/* register MAILBOX_INT_STATUS */ +#define MAILBOX_INT_STATUS 14 +#define F_MAILBOX_INT_STATUS(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_MAILBOX_INT_STATUS_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) + +/* register SW_CLK_L */ +#define SW_CLK_L 15 +#define F_SW_CLOCK_VAL_L(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_CLOCK_VAL_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_CLK_H */ +#define SW_CLK_H 16 +#define F_SW_CLOCK_VAL_H(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_CLOCK_VAL_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_EVENTS0 */ +#define SW_EVENTS0 17 +#define F_SW_EVENTS7_0(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_EVENTS7_0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_EVENTS1 */ +#define SW_EVENTS1 18 +#define F_SW_EVENTS15_8(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_EVENTS15_8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_EVENTS2 */ +#define SW_EVENTS2 19 +#define F_SW_EVENTS23_16(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_EVENTS23_16_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_EVENTS3 */ +#define SW_EVENTS3 20 +#define F_SW_EVENTS31_24(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_EVENTS31_24_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register XT_OCD_CTRL */ +#define XT_OCD_CTRL 24 +#define F_XT_DRESET(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_XT_DRESET_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_XT_OCDHALTONRESET(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_XT_OCDHALTONRESET_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) + +/* register XT_OCD_CTRL_RO */ +#define XT_OCD_CTRL_RO 25 +#define F_XT_XOCDMODE(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_XT_XOCDMODE_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register APB_INT_MASK */ +#define APB_INT_MASK 27 +#define F_APB_INTR_MASK(x) (((x) & ((1 << 3) - 1)) << 0) +#define F_APB_INTR_MASK_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) + +/* register APB_STATUS_MASK */ +#define APB_STATUS_MASK 28 +#define F_APB_INTR_STATUS(x) (((x) & ((1 << 3) - 1)) << 0) +#define F_APB_INTR_STATUS_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) + +#endif /*APB_CFG*/ diff --git a/drivers/video/imx/hdp/avgen.h b/drivers/video/imx/hdp/avgen.h new file mode 100644 index 00000000000..669a10187f1 --- /dev/null +++ b/drivers/video/imx/hdp/avgen.h @@ -0,0 +1,253 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * avgen.h + * + ****************************************************************************** + */ + +#ifndef AVGEN_H_ +# define AVGEN_H_ + + +/* register HDMIPOL */ +# define HDMIPOL 0 +# define F_HDMI_V_H_POLARITY(x) (((x) & ((1 << 2) - 1)) << 0) +# define F_HDMI_V_H_POLARITY_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) +# define F_HDMI_BITWIDTH(x) (((x) & ((1 << 2) - 1)) << 2) +# define F_HDMI_BITWIDTH_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2) + +/* register HDMI_FRONT_PORCHE_L */ +# define HDMI_FRONT_PORCHE_L 1 +# define F_HDMI_FRONT_PORCHE_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_FRONT_PORCHE_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDFP */ +# define HDFP 2 +# define F_HDMI_FRONT_PORCHE_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_FRONT_PORCHE_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDBP */ +# define HDBP 3 +# define F_HDMI_BACK_PORCHE_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_BACK_PORCHE_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDMI_BACK_PORCHE_H */ +# define HDMI_BACK_PORCHE_H 4 +# define F_HDMI_BACK_PORCHE_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_BACK_PORCHE_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDAS */ +# define HDAS 5 +# define F_HDMI_ACTIVE_SLOT_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_ACTIVE_SLOT_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDMI_ACTIVE_SLOT_H */ +# define HDMI_ACTIVE_SLOT_H 6 +# define F_HDMI_ACTIVE_SLOT_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_ACTIVE_SLOT_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDFL */ +# define HDFL 7 +# define F_HDMI_FRAME_LINES_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_FRAME_LINES_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDMI_FRAME_LINES_H */ +# define HDMI_FRAME_LINES_H 8 +# define F_HDMI_FRAME_LINES_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_FRAME_LINES_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDLW */ +# define HDLW 9 +# define F_HDMI_LINE_WIDTH_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_LINE_WIDTH_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDMI_LINE_WIDTH_H */ +# define HDMI_LINE_WIDTH_H 10 +# define F_HDMI_LINE_WIDTH_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_LINE_WIDTH_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDVL */ +# define HDVL 11 +# define F_HDMI_VSYNC_LINES(x) (((x) & ((1 << 7) - 1)) << 0) +# define F_HDMI_VSYNC_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0) + +/* register HDEL */ +# define HDEL 12 +# define F_HDMI_EOF_LINES(x) (((x) & ((1 << 7) - 1)) << 0) +# define F_HDMI_EOF_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0) + +/* register HDSL */ +# define HDSL 13 +# define F_HDMI_SOF_LINES(x) (((x) & ((1 << 7) - 1)) << 0) +# define F_HDMI_SOF_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0) + +/* register HDCFUPDT */ +# define HDCFUPDT 14 +# define F_HDMI_CODE_FORMAT_UPDT(x) (((x) & ((1 << 6) - 1)) << 0) +# define F_HDMI_CODE_FORMAT_UPDT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0) + +/* register HDCF */ +# define HDCF 15 +# define F_HDMI_CODE_FORMAT(x) (((x) & ((1 << 6) - 1)) << 0) +# define F_HDMI_CODE_FORMAT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0) + +/* register HDASPACE */ +# define HDASPACE 16 +# define F_HDASPACE(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDASPACE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDMI_3D_MODE */ +# define HDMI_3D_MODE 17 +# define F_HDMI_3D_MODE(x) (((x) & ((1 << 3) - 1)) << 0) +# define F_HDMI_3D_MODE_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) + +/* register PTRNGENR */ +# define PTRNGENR 18 +# define F_PTRNGENR_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENR_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRNGENR_H */ +# define PTRNGENR_H 19 +# define F_PTRNGENR_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENR_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRNGENG */ +# define PTRNGENG 20 +# define F_PTRNGENG_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENG_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRNEGENG_H */ +# define PTRNEGENG_H 21 +# define F_PTRNGENG_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENG_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRNGENB */ +# define PTRNGENB 22 +# define F_PTRNGENB_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENB_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRGENB */ +# define PTRGENB 23 +# define F_PTRNGENB_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENB_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRNGENFF */ +# define PTRNGENFF 30 +# define F_PTRNGENIP(x) (((x) & ((1 << 1) - 1)) << 1) +# define F_PTRNGENIP_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) + +/* register PGENCTRL */ +# define PGENCTRL 32 +# define F_PGENCF(x) (((x) & ((1 << 6) - 1)) << 1) +# define F_PGENCF_RD(x) (((x) & (((1 << 6) - 1) << 1)) >> 1) +# define F_PTRNGENSTRT(x) (((x) & ((1 << 1) - 1)) << 7) +# define F_PTRNGENSTRT_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) + +/* register PGENCTRL_H */ +# define PGENCTRL_H 33 +# define F_PTRNGENRST(x) (((x) & ((1 << 1) - 1)) << 0) +# define F_PTRNGENRST_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +# define F_PIC_SEL(x) (((x) & ((1 << 3) - 1)) << 1) +# define F_PIC_SEL_RD(x) (((x) & (((1 << 3) - 1) << 1)) >> 1) +# define F_PIC_YCBCR_SEL(x) (((x) & ((1 << 2) - 1)) << 4) +# define F_PIC_YCBCR_SEL_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4) + +/* register PGEN_COLOR_BAR_CTRL */ +# define PGEN_COLOR_BAR_CTRL 34 +# define F_PGEN_NUM_BAR(x) (((x) & ((1 << 3) - 1)) << 0) +# define F_PGEN_NUM_BAR_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) + +/* register PGEN_COLOR_BAR_CONTROL_H */ +# define PGEN_COLOR_BAR_CONTROL_H 35 +# define F_PGEN_COLOR_UPDT(x) (((x) & ((1 << 6) - 1)) << 0) +# define F_PGEN_COLOR_UPDT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0) + +/* register GEN_AUDIO_CONTROL */ +# define GEN_AUDIO_CONTROL 36 +# define F_AUDIO_START(x) (((x) & ((1 << 1) - 1)) << 1) +# define F_AUDIO_START_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +# define F_AUDIO_RESET(x) (((x) & ((1 << 1) - 1)) << 2) +# define F_AUDIO_RESET_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) + +/* register SPDIF_CTRL_A */ +# define SPDIF_CTRL_A 37 +# define F_SPDIF_SOURCE_NUM(x) (((x) & ((1 << 4) - 1)) << 0) +# define F_SPDIF_SOURCE_NUM_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +# define F_SPDIF_CH_NUM(x) (((x) & ((1 << 4) - 1)) << 4) +# define F_SPDIF_CH_NUM_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4) + +/* register SPDIF_CTRL_A_H */ +# define SPDIF_CTRL_A_H 38 +# define F_SPDIF_SMP_FREQ(x) (((x) & ((1 << 4) - 1)) << 0) +# define F_SPDIF_SMP_FREQ_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +# define F_SPDIF_CLK_ACCUR(x) (((x) & ((1 << 2) - 1)) << 4) +# define F_SPDIF_CLK_ACCUR_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4) +# define F_SPDIF_VALID(x) (((x) & ((1 << 1) - 1)) << 6) +# define F_SPDIF_VALID_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) + +/* register SPDIF_CTRL_B */ +# define SPDIF_CTRL_B 39 +# define F_SPDIF_WORD_LENGTH(x) (((x) & ((1 << 4) - 1)) << 0) +# define F_SPDIF_WORD_LENGTH_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +# define F_SPDIF_ORG_SMP_FREQ(x) (((x) & ((1 << 4) - 1)) << 4) +# define F_SPDIF_ORG_SMP_FREQ_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4) + +/* register SPDIF_CTRL_B_H */ +# define SPDIF_CTRL_B_H 40 +# define F_CATEGORY_MODE(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_CATEGORY_MODE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register AUDIO_DIV_EN */ +# define AUDIO_DIV_EN 45 +# define F_AGEN_60958_I2S(x) (((x) & ((1 << 1) - 1)) << 1) +# define F_AGEN_60958_I2S_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +# define F_AGEN_PRL_SUBFRAME(x) (((x) & ((1 << 1) - 1)) << 2) +# define F_AGEN_PRL_SUBFRAME_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +# define F_AGEN_SAMPLES_DATA(x) (((x) & ((1 << 1) - 1)) << 3) +# define F_AGEN_SAMPLES_DATA_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) + +#endif /*AVGEN */ + diff --git a/drivers/video/imx/hdp/avgen_drv.c b/drivers/video/imx/hdp/avgen_drv.c new file mode 100644 index 00000000000..89acafe340c --- /dev/null +++ b/drivers/video/imx/hdp/avgen_drv.c @@ -0,0 +1,306 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * avgen_drv.c + * + ****************************************************************************** + */ + +#include "mhl_hdtx_top.h" +#include "address.h" +#include "avgen.h" +#include "avgen_drv.h" +#include "util.h" +#include "externs.h" + +#define ADDR_AVGEN 0x80000 + +CDN_API_STATUS CDN_API_AVGEN_Set(VIC_MODES vicMode, CDN_PROTOCOL_TYPE protocol, + VIC_PXL_ENCODING_FORMAT format) +{ + /*CDN_API_STATUS ret; */ + /*GENERAL_Read_Register_response resp; */ + unsigned int pixelClockFreq = CDN_API_Get_PIXEL_FREQ_KHZ_ClosetVal + (vic_table[vicMode][PIXEL_FREQ_KHZ], protocol); + unsigned int v_h_polarity = + ((vic_table[vicMode][HSYNC_POL] == ACTIVE_LOW) ? 0 : 1) + + ((vic_table[vicMode][VSYNC_POL] == ACTIVE_LOW) ? 0 : 2); + unsigned int front_porche_l = vic_table[vicMode][FRONT_PORCH] - 256 * + ((unsigned int)vic_table[vicMode][FRONT_PORCH] / 256); + unsigned int front_porche_h = vic_table[vicMode][FRONT_PORCH] / 256; + unsigned int back_porche_l = vic_table[vicMode][BACK_PORCH] - 256 * + ((unsigned int)vic_table[vicMode][BACK_PORCH] / 256); + unsigned int back_porche_h = vic_table[vicMode][BACK_PORCH] / 256; + unsigned int active_slot_l = vic_table[vicMode][H_BLANK] - 256 * + ((unsigned int)vic_table[vicMode][H_BLANK] / 256); + unsigned int active_slot_h = vic_table[vicMode][H_BLANK] / 256; + unsigned int frame_lines_l = vic_table[vicMode][V_TOTAL] - 256 * + ((unsigned int)vic_table[vicMode][V_TOTAL] / 256); + unsigned int frame_lines_h = vic_table[vicMode][V_TOTAL] / 256; + unsigned int line_width_l = vic_table[vicMode][H_TOTAL] - 256 * + ((unsigned int)vic_table[vicMode][H_TOTAL] / 256); + unsigned int line_width_h = vic_table[vicMode][H_TOTAL] / 256; + unsigned int vsync_lines = vic_table[vicMode][VSYNC]; + unsigned int eof_lines = vic_table[vicMode][TYPE_EOF]; + unsigned int sof_lines = vic_table[vicMode][SOF]; + unsigned int interlace_progressive = + (vic_table[vicMode][I_P] == INTERLACED) ? 2 : 0; + unsigned int set_vif_clock = 0; + + /*needed for HDMI /////////////////////////////// */ + /*unsigned int hblank = vic_table[vicMode][H_BLANK]; */ + /*unsigned int hactive = vic_table[vicMode][H_TOTAL]-hblank; */ + /*unsigned int vblank = vsync_lines+eof_lines+sof_lines; */ + /*unsigned int vactive = vic_table[vicMode][V_TOTAL]-vblank; */ + /*unsigned int hfront = vic_table[vicMode][FRONT_PORCH]; */ + /*unsigned int hback = vic_table[vicMode][BACK_PORCH]; */ + /*unsigned int vfront = eof_lines; */ + /*unsigned int hsync = hblank-hfront-hback; */ + /*unsigned int vsync = vsync_lines; */ + /*unsigned int vback = sof_lines; */ + unsigned int set_CLK_SEL = 0; + unsigned int set_REF_CLK_SEL = 0; + unsigned int set_pll_CLK_IN = 0; + unsigned int set_pll_clkfbout_l = 0; + unsigned int set_pll_clkfbout_h = 0; + unsigned int set_pll_CLKOUT5_L = 0; + unsigned int set_pll_CLKOUT5_H = 0; + unsigned int set_pll2_CLKIN = 0; + unsigned int set_pll2_CLKFBOUT_L = 0; + unsigned int set_pll2_CLKFBOUT_H = 0; + unsigned int set_pll2_CLKOUT5_L = 0; + unsigned int set_pll2_CLKOUT5_H = 0; + /*///////////////////////////////////////////////// */ + + cdn_apb_write(0x1c00C6 << 2, + (int)(vic_table[vicMode][PIXEL_FREQ_KHZ] * 1000)); + cdn_apb_write(0x1c00C6 << 2, (int)(pixelClockFreq)); + + if ((int)(pixelClockFreq) == 25) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 4; + set_REF_CLK_SEL = 0; + set_pll_CLK_IN = 65; + set_pll_clkfbout_l = 4292; + set_pll_clkfbout_h = 128; + set_pll_CLKOUT5_L = 4422; + set_pll_CLKOUT5_H = 128; + set_pll2_CLKIN = 12289; + set_pll2_CLKFBOUT_L = 4356; + set_pll2_CLKFBOUT_H = 0; + set_pll2_CLKOUT5_L = 4552; + set_pll2_CLKOUT5_H = 128; + } else { + set_vif_clock = 0x300; + } + } else if ((int)pixelClockFreq == 27000) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 5; + set_REF_CLK_SEL = 0; + set_pll_CLK_IN = 49217; + set_pll_clkfbout_l = 4226; + set_pll_clkfbout_h = 0; + set_pll_CLKOUT5_L = 4422; + set_pll_CLKOUT5_H = 128; + } else { + set_vif_clock = 0x301; + } + } else if ((int)pixelClockFreq == 54000) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 5; + set_REF_CLK_SEL = 0; + set_pll_CLK_IN = 4096; + set_pll_clkfbout_l = 4226; + set_pll_clkfbout_h = 0; + set_pll_CLKOUT5_L = 4422; + set_pll_CLKOUT5_H = 128; + } else { + set_vif_clock = 0x302; + } + } else if (pixelClockFreq == 74250) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 1; + set_pll_CLK_IN = 74; + } else { + set_vif_clock = 0x303; + } + } else if (pixelClockFreq == 148500) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 0; + set_pll_CLK_IN = 148; + } else { + set_vif_clock = 0x304; + } + } else if ((int)pixelClockFreq == 108000) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 5; + set_REF_CLK_SEL = 2; + set_pll_CLK_IN = 8258; + set_pll_clkfbout_l = 4616; + set_pll_clkfbout_h = 0; + set_pll_CLKOUT5_L = 4422; + set_pll_CLKOUT5_H = 128; + } else { + set_vif_clock = 0x305; + } + } else { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 1; + set_pll_CLK_IN = pixelClockFreq; + } else { + set_vif_clock = 0; + } + } + unsigned int start_pgen = 128; + /*unsigned int temp; */ + if (protocol == CDN_HDMITX_TYPHOON) { + if (cdn_apb_write(0x0c0001 << 2, + ((0) + (2 * set_CLK_SEL) + (16 * 0) + + (32 * 0) + (64 * 3) + (65536 * 3) + + (1048576 * set_REF_CLK_SEL)))) + return CDN_ERR; + if (cdn_apb_write(0x1c00C6 << 2, set_pll_CLK_IN)) + return CDN_ERR; + if (cdn_apb_write(0x1c00CC << 2, set_pll_clkfbout_l)) + return CDN_ERR; + if (cdn_apb_write(0x1c00CD << 2, set_pll_clkfbout_h)) + return CDN_ERR; + if (cdn_apb_write(0x1c00CE << 2, set_pll_CLKOUT5_L)) + return CDN_ERR; + if (cdn_apb_write(0x1c00CF << 2, set_pll_CLKOUT5_H)) + return CDN_ERR; + if (cdn_apb_write(0x1c0086 << 2, set_pll2_CLKIN)) + return CDN_ERR; + if (cdn_apb_write(0x1c008C << 2, set_pll2_CLKFBOUT_L)) + return CDN_ERR; + if (cdn_apb_write(0x1c008D << 2, set_pll2_CLKFBOUT_H)) + return CDN_ERR; + if (cdn_apb_write(0x1c008E << 2, set_pll2_CLKOUT5_L)) + return CDN_ERR; + if (cdn_apb_write(0x1c008F << 2, set_pll2_CLKOUT5_H)) + return CDN_ERR; + if (cdn_apb_write(0x0c0001 << 2, + ((1) + (2 * set_CLK_SEL) + (16 * 0) + + (32 * 0) + (64 * 3) + (65536 * 3) + + (1048576 * set_REF_CLK_SEL)))) + return CDN_ERR; + } + + if (cdn_apb_write((ADDR_AVGEN + HDMIPOL) << 2, v_h_polarity)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDMI_FRONT_PORCHE_L) << 2, + front_porche_l)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDFP) << 2, front_porche_h)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDBP) << 2, back_porche_l)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDMI_BACK_PORCHE_H) << 2, + back_porche_h)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDAS) << 2, active_slot_l)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDMI_ACTIVE_SLOT_H) << 2, + active_slot_h)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDFL) << 2, frame_lines_l)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDMI_FRAME_LINES_H) << 2, + frame_lines_h)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDLW) << 2, line_width_l)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDMI_LINE_WIDTH_H) << 2, line_width_h)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDVL) << 2, vsync_lines)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDEL) << 2, eof_lines)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDSL) << 2, sof_lines)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + PTRNGENFF) << 2, interlace_progressive)) + return CDN_ERR; + + if (protocol == CDN_HDMITX_TYPHOON) { + switch (format) { + case PXL_RGB: + + if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2, + F_PIC_SEL(1) | F_PIC_YCBCR_SEL(0))) + return CDN_ERR; + break; + + case YCBCR_4_4_4: + if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2, + F_PIC_SEL(2) | F_PIC_YCBCR_SEL(0))) + return CDN_ERR; + + break; + + case YCBCR_4_2_2: + if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2, + F_PIC_SEL(2) | F_PIC_YCBCR_SEL(1))) + return CDN_ERR; + + break; + + case YCBCR_4_2_0: + if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2, + F_PIC_SEL(2) | F_PIC_YCBCR_SEL(2))) + return CDN_ERR; + + break; + case Y_ONLY: + /*not exist in hdmi */ + break; + } + } else { + if (set_vif_clock != 0) + if (cdn_apb_write(0xC0006 << 2, set_vif_clock)) + return CDN_ERR; + } + + if (cdn_apb_write((ADDR_AVGEN + PGENCTRL) << 2, start_pgen)) + return CDN_ERR; + + return CDN_OK; +} + diff --git a/drivers/video/imx/hdp/avgen_drv.h b/drivers/video/imx/hdp/avgen_drv.h new file mode 100644 index 00000000000..1f8c76b4682 --- /dev/null +++ b/drivers/video/imx/hdp/avgen_drv.h @@ -0,0 +1,69 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * avgen_drv.h + * + ****************************************************************************** + */ + +#ifndef AVGEN_DRV_H_ +# define AVGEN_DRV_H_ + +#ifndef __UBOOT__ +# include +#else +#include +#endif + +# include "vic_table.h" +# include "API_General.h" +# include "defs.h" + +/** + * \brief set avgen according to mode and vic table, user that doesnt have + * cadence AVGEN, need to implement this function on user + * platform + */ +CDN_API_STATUS CDN_API_AVGEN_Set(VIC_MODES vicMode, CDN_PROTOCOL_TYPE protocol, + VIC_PXL_ENCODING_FORMAT format); + +#endif + diff --git a/drivers/video/imx/hdp/defs.h b/drivers/video/imx/hdp/defs.h new file mode 100644 index 00000000000..4a6361e4fa2 --- /dev/null +++ b/drivers/video/imx/hdp/defs.h @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * Copyright (C) 2015-2016 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * defs.h + * + ****************************************************************************** + */ + +#ifndef _DEFS_H_ +#define _DEFS_H_ + +typedef enum { + CDN_DPTX , + CDN_HDMITX_TYPHOON, + CDN_HDMITX_KIRAN, +} CDN_PROTOCOL_TYPE; + +#endif /*_DEFS_H_ */ + diff --git a/drivers/video/imx/hdp/edid_parser.c b/drivers/video/imx/hdp/edid_parser.c new file mode 100644 index 00000000000..24aa7397910 --- /dev/null +++ b/drivers/video/imx/hdp/edid_parser.c @@ -0,0 +1,617 @@ +/****************************************************************************** + * + * Copyright (C) 2015-2016 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * edid_parser.c + * + ****************************************************************************** + */ + +#include "edid_parser.h" + +static EDID_PARSER_RESULT edid_parse_dtd(S_DTD_DATA *descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_DTD; + descriptor->header.tag = 0; + + descriptor->pixel_clock = raw_data[raw_data_index]; + descriptor->pixel_clock += + (unsigned short)raw_data[raw_data_index + 1] << 8; + + descriptor->horizontal_addressable_video = raw_data[raw_data_index + 2]; + descriptor->horizontal_addressable_video += + ((unsigned short)raw_data[raw_data_index + 4] & 0xF0) << 4; + descriptor->horizontal_blanking = raw_data[raw_data_index + 3]; + descriptor->horizontal_blanking += + ((unsigned short)raw_data[raw_data_index + 4] & 0x0F) << 8; + + descriptor->vertical_addressable_video = raw_data[raw_data_index + 5]; + descriptor->vertical_addressable_video += + ((unsigned short)raw_data[raw_data_index + 7] & 0xF0) << 4; + descriptor->vertical_blanking = raw_data[raw_data_index + 6]; + descriptor->vertical_blanking += + ((unsigned short)raw_data[raw_data_index + 7] & 0x0F) << 8; + + descriptor->horizontal_front_porch = raw_data[raw_data_index + 8]; + descriptor->horizontal_front_porch += + ((unsigned short)raw_data[raw_data_index + 11] & 0xC0) << 2; + descriptor->horizontal_sync_pulse_width = raw_data[raw_data_index + 9]; + descriptor->horizontal_sync_pulse_width += + ((unsigned short)raw_data[raw_data_index + 11] & 0x30) << 4; + + descriptor->vertical_front_porch = + (raw_data[raw_data_index + 10] & 0xF0) >> 4; + descriptor->vertical_front_porch += + (raw_data[raw_data_index + 11] & 0x0C) << 2; + descriptor->vertical_sync_pulse_width = + raw_data[raw_data_index + 10] & 0x0F; + descriptor->vertical_sync_pulse_width += + (raw_data[raw_data_index + 11] & 0x03) << 4; + + descriptor->horizontal_addressable_video_image_size = + raw_data[raw_data_index + 12]; + descriptor->horizontal_addressable_video_image_size += + ((unsigned short)raw_data[raw_data_index + 14] & 0xF0) << 4; + descriptor->vertical_addressable_video_image_size = + raw_data[raw_data_index + 13]; + descriptor->vertical_addressable_video_image_size += + ((unsigned short)raw_data[raw_data_index + 14] & 0x0F) << 8; + + descriptor->horizontal_border = raw_data[raw_data_index + 15]; + descriptor->vertical_border = raw_data[raw_data_index + 16]; + + descriptor->signal_features = raw_data[raw_data_index + 17]; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_serial_number(S_SERIAL_NUMBER_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + descriptor->header.type = DESCRIPTOR_TYPE_SERIAL_NUMBER; + descriptor->header.tag = 0xFF; + + int idx; + for (idx = 0; idx < 13; idx++) + descriptor->serial_number[idx] = + raw_data[raw_data_index + 5 + idx]; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_data_string(S_DATA_STRING_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + descriptor->header.type = DESCRIPTOR_TYPE_DATA_STRING; + descriptor->header.tag = 0xFE; + int idx; + for (idx = 0; idx < 13; idx++) + descriptor->data_string[idx] = + raw_data[raw_data_index + 5 + idx]; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_range_limits(S_RANGE_LIMITS_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_RANGE_LIMITS; + descriptor->header.tag = 0xFD; + + descriptor->offset_flags = raw_data[raw_data_index + 4]; + descriptor->min_vertical_rate = raw_data[raw_data_index + 5]; + descriptor->max_vertical_rate = raw_data[raw_data_index + 6]; + descriptor->min_horizontal_rate = raw_data[raw_data_index + 7]; + descriptor->max_horizontal_rate = raw_data[raw_data_index + 8]; + descriptor->max_pixel_clock = raw_data[raw_data_index + 9]; + + switch (raw_data[raw_data_index + 10]) { + case 0x00: + descriptor->type = VIDEO_TIMING_DEFAULT_GTF; + break; + case 0x01: + descriptor->type = VIDEO_TIMING_RANGE_LIMITS_ONLY; + break; + case 0x02: + descriptor->type = VIDEO_TIMING_SECONDARY_GTF; + S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF *timing_type_gtf = + (S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF *) + descriptor->suport_flags; + timing_type_gtf->start_break_frequency = + raw_data[raw_data_index + 12]; + timing_type_gtf->c = raw_data[raw_data_index + 13]; + timing_type_gtf->m = raw_data[raw_data_index + 14]; + timing_type_gtf->m += + (unsigned short)raw_data[raw_data_index + 15] << 8; + timing_type_gtf->k = raw_data[raw_data_index + 16]; + timing_type_gtf->j = raw_data[raw_data_index + 17]; + break; + case 0x04: + descriptor->type = VIDEO_TIMING_CVT; + S_RANGE_LIMITS_VIDEO_TIMING_CVT *timing_type_cvt = + (S_RANGE_LIMITS_VIDEO_TIMING_CVT *)descriptor-> + suport_flags; + timing_type_cvt->cvt_version = raw_data[raw_data_index + 11]; + timing_type_cvt->additional_pixel_clock_precision = + raw_data[raw_data_index + 12] >> 2; + timing_type_cvt->max_active_pixels = + raw_data[raw_data_index + 13]; + timing_type_cvt->max_active_pixels += + (unsigned short)(raw_data[raw_data_index + 12] & 0x03) + << 8; + timing_type_cvt->supported_ar = + raw_data[raw_data_index + 14] >> 3; + timing_type_cvt->preferred_ar = + raw_data[raw_data_index + 15] >> 5; + timing_type_cvt->blanking_support = + (raw_data[raw_data_index + 15] & 0x18) >> 3; + timing_type_cvt->supported_scalling = + raw_data[raw_data_index + 16] >> 4; + timing_type_cvt->preferred_vertical_refresh_rate = + raw_data[raw_data_index + 17]; + break; + } + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_product_name(S_PRODUCT_NAME_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_PRODUCT_NAME; + descriptor->header.tag = 0xFC; + int idx; + for (idx = 0; idx < 13; idx++) + descriptor->product_name[idx] = + raw_data[raw_data_index + 5 + idx]; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_color_point(S_COLOR_POINT_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_COLOR_POINT; + descriptor->header.tag = 0xFB; + descriptor->white_point_index_1 = raw_data[raw_data_index + 5]; + descriptor->white_x_1 = (raw_data[raw_data_index + 6] & 0x0C) >> 2; + descriptor->white_x_1 += + (unsigned short)raw_data[raw_data_index + 7] << 2; + descriptor->white_y_1 = raw_data[raw_data_index + 6] & 0x03; + descriptor->white_y_1 += + (unsigned short)raw_data[raw_data_index + 8] << 2; + descriptor->gamma_1 = raw_data[raw_data_index + 9]; + + descriptor->white_point_index_2 = raw_data[raw_data_index + 10]; + descriptor->white_x_2 = (raw_data[raw_data_index + 11] & 0x0C) >> 2; + descriptor->white_x_2 += + (unsigned short)raw_data[raw_data_index + 12] << 2; + descriptor->white_y_2 = raw_data[raw_data_index + 11] & 0x03; + descriptor->white_y_2 += + (unsigned short)raw_data[raw_data_index + 13] << 2; + descriptor->gamma_2 = raw_data[raw_data_index + 14]; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_standard_timing(S_STANDARD_TIMING_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_STANDARD_TIMING; + descriptor->header.tag = 0xFA; + int idx; + for (idx = 0; idx < 6; idx++) { + descriptor->standard_timings[idx] = + raw_data[raw_data_index + 5 + 2 * idx]; + descriptor->standard_timings[idx] += + (unsigned short)raw_data[raw_data_index + 5 + 2 * idx + + 1]; + } + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_color_management(S_COLOR_MANAGEMENT_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_COLOR_MANAGEMENT; + descriptor->header.tag = 0xF9; + + descriptor->version = raw_data[raw_data_index + 5]; + + descriptor->red_a3 = raw_data[raw_data_index + 6]; + descriptor->red_a3 += (unsigned short)raw_data[raw_data_index + 7] << 8; + descriptor->red_a2 = raw_data[raw_data_index + 8]; + descriptor->red_a2 += (unsigned short)raw_data[raw_data_index + 9] << 8; + + descriptor->green_a3 = raw_data[raw_data_index + 10]; + descriptor->green_a3 += + (unsigned short)raw_data[raw_data_index + 11] << 8; + descriptor->green_a2 = raw_data[raw_data_index + 12]; + descriptor->green_a2 += + (unsigned short)raw_data[raw_data_index + 13] << 8; + + descriptor->blue_a3 = raw_data[raw_data_index + 14]; + descriptor->blue_a3 += + (unsigned short)raw_data[raw_data_index + 15] << 8; + descriptor->blue_a2 = raw_data[raw_data_index + 16]; + descriptor->blue_a2 += + (unsigned short)raw_data[raw_data_index + 17] << 8; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_cvt_timing_codes(S_CVT_TIMING_CODES_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_CVT_TIMING_CODES; + descriptor->header.tag = 0xF8; + descriptor->version = raw_data[raw_data_index + 5]; + + int idx; + for (idx = 0; idx < 4; idx++) { + descriptor->addressable_lines[idx] = + raw_data[raw_data_index + 6 + idx * 3]; + descriptor->addressable_lines[idx] += + (unsigned short)(raw_data[raw_data_index + 7 + idx * 3] + & 0xF0) << 4; + descriptor->aspect_ratio[idx] = + (raw_data[raw_data_index + 7 + idx * 3] & 0x0C) >> 2; + descriptor->preferred_vertical_rate[idx] = + (raw_data[raw_data_index + 8 + idx * 3] & 0x60) >> 5; + descriptor->supported_vertical_rate_and_blanking[idx] = + raw_data[raw_data_index + 8 + idx * 3] & 0x1F; + } + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT +edid_parse_established_timings_3(S_ESTABLISHED_TIMINGS_3_DATA *descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_ESTABLISHED_TIMINGS_3; + descriptor->header.tag = 0xF7; + descriptor->version = raw_data[raw_data_index + 5]; + int idx; + for (idx = 0; idx < 6; idx++) { + descriptor->established_timings[idx] = + raw_data[raw_data_index + 6 + idx]; + } + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_dummy(S_DUMMY_DATA *descriptor, + unsigned char *raw_data) +{ + descriptor->header.type = DESCRIPTOR_TYPE_DUMMY; + descriptor->header.tag = 0x10; + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT +edid_parse_manufacturer_specific(S_MANUFACTURER_SPECIFIC_DATA *descriptor, + unsigned char *raw_data, unsigned char tag) +{ + descriptor->header.type = DESCRIPTOR_TYPE_MANUFACTURER_SPECIFIC; + descriptor->header.tag = tag; + + return EDID_PARSER_SUCCESS; +} + +EDID_PARSER_RESULT edid_parse(S_EDID_DATA *edid, unsigned char *raw_data, + unsigned int len) +{ + unsigned int raw_data_index = 0; + unsigned char sum = 0; + /*CHECK SUM OF BYTES IN BLOCK0 */ + for (raw_data_index = 0; raw_data_index < EDID_LENGTH; raw_data_index++) + sum += raw_data[raw_data_index]; + + if (sum != 0) + return EDID_PARSER_ERROR; + + /*READ HEADER */ + for (raw_data_index = 0; raw_data_index < EDID_HEADER_LENGTH; + raw_data_index++) + edid->header[raw_data_index] = raw_data[raw_data_index]; + + /*READ VENDOR & PRODUCT IDENTIFICATION */ + /*manufacturer name */ + edid->manufacturer_name[0] = ((raw_data[8] & 0x7C) >> 2) + 0x40; + edid->manufacturer_name[1] = + ((raw_data[8] & 0x03) << 3) + ((raw_data[9] & 0xE0) >> 5) + + 0x40; + edid->manufacturer_name[2] = ((raw_data[9] & 0x1F)) + 0x40; + edid->manufacturer_name[3] = 0; + + /*product code */ + edid->product_code = (raw_data[10]); + edid->product_code += ((unsigned short)raw_data[11]) << 8; + + /*serial number */ + edid->serial_number = raw_data[12]; + edid->serial_number += (unsigned int)raw_data[13] << 8; + edid->serial_number += (unsigned int)raw_data[14] << 16; + edid->serial_number += (unsigned int)raw_data[15] << 24; + + /*week of manufacture */ + edid->week = raw_data[16]; + + /*year of manufacture */ + edid->year = raw_data[17]; + + /*EDID STRUCTURE VERSION & REVISION */ + edid->edid_version = ((unsigned short)raw_data[18] << 8) + raw_data[19]; + + /*BASIC DISPLAY PARAMETERS AND FEATURES */ + /*video input definition */ + edid->video_input_definition = raw_data[20]; + + /*horizontal screen size */ + edid->horizontal_size = raw_data[21]; + + /*vertical screen size */ + edid->vertical_size = raw_data[22]; + + /*display transfer characteristic */ + edid->gamma = raw_data[23]; + + /*feature support */ + edid->feature_support = raw_data[24]; + + /*COLOR CHARACTERISTIC */ + /*red */ + edid->chromacity_coorditates_red_x = (raw_data[25] & 0xC0) >> 6; + edid->chromacity_coorditates_red_x += (unsigned short)raw_data[27] << 2; + edid->chromacity_coorditates_red_y = (raw_data[25] & 0x30) >> 4; + edid->chromacity_coorditates_red_y += (unsigned short)raw_data[28] << 2; + + /*green */ + edid->chromacity_coorditates_green_x = (raw_data[25] & 0x0C) >> 2; + edid->chromacity_coorditates_green_x += + (unsigned short)raw_data[29] << 2; + edid->chromacity_coorditates_green_y = (raw_data[25] & 0x03); + edid->chromacity_coorditates_green_y += + (unsigned short)raw_data[30] << 2; + + /*blue */ + edid->chromacity_coorditates_blue_x = (raw_data[26] & 0xC0) >> 6; + edid->chromacity_coorditates_blue_x += + (unsigned short)raw_data[31] << 2; + edid->chromacity_coorditates_blue_y = (raw_data[26] & 0x30) >> 4; + edid->chromacity_coorditates_blue_y += + (unsigned short)raw_data[32] << 2; + + /*blue */ + edid->chromacity_coorditates_white_x = (raw_data[26] & 0x0C) >> 2; + edid->chromacity_coorditates_white_x += + (unsigned short)raw_data[33] << 2; + edid->chromacity_coorditates_white_y = (raw_data[26] & 0x03); + edid->chromacity_coorditates_white_y += + (unsigned short)raw_data[34] << 2; + + /*ESTABLISHED TIMINGS */ + edid->established_timing_1 = raw_data[35]; + edid->established_timing_2 = raw_data[36]; + edid->manufacturer_timing = raw_data[37]; + + /*STANDARD TIMINGS */ + for (raw_data_index = 0; raw_data_index < 8; raw_data_index++) { + edid->standard_timings[raw_data_index] = + raw_data[38 + (2 * raw_data_index)]; + edid->standard_timings[raw_data_index] += + (unsigned short)raw_data[38 + (2 * raw_data_index + 1)]; + } + /*extensions */ + edid->extensions = raw_data[126]; + + /*DESCRIPTORS */ + unsigned int descriptor_index; + raw_data_index = 54; + for (descriptor_index = 0; descriptor_index < 4; descriptor_index++) { + if (raw_data[raw_data_index] == 0 && + raw_data[raw_data_index] == 0) { + /*display descriptor found */ + unsigned char tag = raw_data[raw_data_index + 3]; + if (tag == 0xFF) { + /*display product serial number */ + S_SERIAL_NUMBER_DATA *descriptor = + (S_SERIAL_NUMBER_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_serial_number + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xFE) { + /*alphanumeric data string */ + S_DATA_STRING_DATA *descriptor = + (S_DATA_STRING_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_data_string + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xFD) { + /*display range limits */ + S_RANGE_LIMITS_DATA *descriptor = + (S_RANGE_LIMITS_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_range_limits + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xFC) { + /*display product name */ + S_PRODUCT_NAME_DATA *descriptor = + (S_PRODUCT_NAME_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_product_name + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xFB) { + /*color point data */ + S_COLOR_POINT_DATA *descriptor = + (S_COLOR_POINT_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_color_point + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xFA) { + /*standard timing identifications */ + S_STANDARD_TIMING_DATA *descriptor = + (S_STANDARD_TIMING_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_standard_timing + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xF9) { + /*display color management (DCM) */ + S_COLOR_MANAGEMENT_DATA *descriptor = + (S_COLOR_MANAGEMENT_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_color_management + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xF8) { + /*CVT 3 byte timing codes */ + S_CVT_TIMING_CODES_DATA *descriptor = + (S_CVT_TIMING_CODES_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_cvt_timing_codes + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xF7) { + /*established timings III */ + S_ESTABLISHED_TIMINGS_3_DATA *descriptor = + (S_ESTABLISHED_TIMINGS_3_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_established_timings_3 + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0x10) { + /*dummy */ + S_DUMMY_DATA *descriptor = + (S_DUMMY_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_dummy + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag <= 0x0F) { + /*manufacturer specific data */ + S_MANUFACTURER_SPECIFIC_DATA *descriptor = + (S_MANUFACTURER_SPECIFIC_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_manufacturer_specific + (descriptor, raw_data + raw_data_index, + tag) != EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + } + } else { + /*detailed timing definition */ + S_DTD_DATA *descriptor = + (S_DTD_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_dtd + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + } + raw_data_index += 18; + } + + return EDID_PARSER_SUCCESS; +} diff --git a/drivers/video/imx/hdp/edid_parser.h b/drivers/video/imx/hdp/edid_parser.h new file mode 100644 index 00000000000..13eb0b1882b --- /dev/null +++ b/drivers/video/imx/hdp/edid_parser.h @@ -0,0 +1,297 @@ +/****************************************************************************** + * + * Copyright (C) 2015-2016 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * edid_parser.h + * + ****************************************************************************** + */ + +#ifndef EDID_PARSER_H +#define EDID_PARSER_H + +#define MAX_DESCRIPTOR_LENGTH 36 +#define MAX_RANGE_LIMITS_VIDEO_TIMING_LENGTH 12 +#define EDID_HEADER_LENGTH 8 +#define EDID_LENGTH 128 + +typedef enum { + EDID_PARSER_SUCCESS, + EDID_PARSER_ERROR, +} EDID_PARSER_RESULT; + +typedef enum { + DESCRIPTOR_TYPE_DTD, + DESCRIPTOR_TYPE_SERIAL_NUMBER, + DESCRIPTOR_TYPE_DATA_STRING, + DESCRIPTOR_TYPE_RANGE_LIMITS, + DESCRIPTOR_TYPE_PRODUCT_NAME, + DESCRIPTOR_TYPE_COLOR_POINT, + DESCRIPTOR_TYPE_STANDARD_TIMING, + DESCRIPTOR_TYPE_COLOR_MANAGEMENT, + DESCRIPTOR_TYPE_CVT_TIMING_CODES, + DESCRIPTOR_TYPE_ESTABLISHED_TIMINGS_3, + DESCRIPTOR_TYPE_DUMMY, + DESCRIPTOR_TYPE_MANUFACTURER_SPECIFIC +} EDID_DESCRIPTOR_TYPE; + +typedef enum { + VIDEO_TIMING_DEFAULT_GTF, + VIDEO_TIMING_RANGE_LIMITS_ONLY, + VIDEO_TIMING_SECONDARY_GTF, + VIDEO_TIMING_CVT, +} RANGE_LIMITS_VIDEO_TIMING_TYPE; + +/** + * \brief Common descriptor header structure + */ +typedef struct { + EDID_DESCRIPTOR_TYPE type; + unsigned char tag; + +} S_DESCRIPTOR_HEADER_DATA; +/** + * \brief Detailed Timing Descriptor (DTD) structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned short pixel_clock; + unsigned short horizontal_addressable_video; + unsigned short horizontal_blanking; + unsigned short vertical_addressable_video; + unsigned short vertical_blanking; + unsigned short horizontal_front_porch; + unsigned short horizontal_sync_pulse_width; + unsigned short vertical_front_porch; + unsigned short vertical_sync_pulse_width; + unsigned short horizontal_addressable_video_image_size; + unsigned short vertical_addressable_video_image_size; + unsigned char horizontal_border; + unsigned char vertical_border; + unsigned char signal_features; +} S_DTD_DATA; + +/** + * \brief Serial Number Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char serial_number[13]; + +} S_SERIAL_NUMBER_DATA; + +/** + * \brief Data String Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + char data_string[13]; + +} S_DATA_STRING_DATA; + +/** + * \brief Range Limits Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char offset_flags; + unsigned char min_vertical_rate; + unsigned char max_vertical_rate; + unsigned char min_horizontal_rate; + unsigned char max_horizontal_rate; + unsigned char max_pixel_clock; + RANGE_LIMITS_VIDEO_TIMING_TYPE type; + unsigned char suport_flags[MAX_RANGE_LIMITS_VIDEO_TIMING_LENGTH]; +} S_RANGE_LIMITS_DATA; + +/** + * \brief Range Limits Secondary GTF Flags structure + */ +typedef struct { + unsigned char start_break_frequency; + unsigned char c; + unsigned short m; + unsigned char k; + unsigned char j; + +} S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF; + +/** + * \brief Range Limits CVT Flags structure + */ +typedef struct { + unsigned char cvt_version; + unsigned char additional_pixel_clock_precision; + unsigned short max_active_pixels; + unsigned char supported_ar; + unsigned char preferred_ar; + unsigned char blanking_support; + unsigned char supported_scalling; + unsigned char preferred_vertical_refresh_rate; +} S_RANGE_LIMITS_VIDEO_TIMING_CVT; + +/** + * \brief Product Name Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + char product_name[13]; + +} S_PRODUCT_NAME_DATA; + +/** + * \brief Color point Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char white_point_index_1; + unsigned short white_x_1; + unsigned short white_y_1; + unsigned char gamma_1; + unsigned char white_point_index_2; + unsigned short white_x_2; + unsigned short white_y_2; + unsigned char gamma_2; +} S_COLOR_POINT_DATA; + +/** + * \brief Standard Timing Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned short standard_timings[6]; +} S_STANDARD_TIMING_DATA; + +/** + * \brief Color Management Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char version; + unsigned short red_a3; + unsigned short red_a2; + unsigned short green_a3; + unsigned short green_a2; + unsigned short blue_a3; + unsigned short blue_a2; +} S_COLOR_MANAGEMENT_DATA; + +/** + * \brief CVT 3 Byte Code Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char version; + unsigned short addressable_lines[4]; + unsigned char aspect_ratio[4]; + unsigned char preferred_vertical_rate[4]; + unsigned char supported_vertical_rate_and_blanking[4]; + +} S_CVT_TIMING_CODES_DATA; + +/** + * \brief Established Timings 3 Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char version; + unsigned char established_timings[6]; +} S_ESTABLISHED_TIMINGS_3_DATA; + +/** + * \brief Dummy Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; +} S_DUMMY_DATA; + +/** + * \brief Manufacturer Specific Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char desc_data[18]; +} S_MANUFACTURER_SPECIFIC_DATA; + +/** + * \brief CEA-861 extension structure + */ +typedef struct { + unsigned char revision; + unsigned char underscan; + unsigned char audio; +} S_CEA861_DATA; + +/** + * \brief Extended Display Identification Data (EDID) structure + */ +typedef struct { + unsigned char header[8]; + char manufacturer_name[4]; + unsigned short product_code; + unsigned int serial_number; + unsigned char week; + unsigned short year; + unsigned short edid_version; + unsigned char video_input_definition; + unsigned char horizontal_size; + unsigned char vertical_size; + unsigned char gamma; + unsigned char feature_support; + unsigned short chromacity_coorditates_red_x; + unsigned short chromacity_coorditates_red_y; + unsigned short chromacity_coorditates_green_x; + unsigned short chromacity_coorditates_green_y; + unsigned short chromacity_coorditates_blue_x; + unsigned short chromacity_coorditates_blue_y; + unsigned short chromacity_coorditates_white_x; + unsigned short chromacity_coorditates_white_y; + unsigned char established_timing_1; + unsigned char established_timing_2; + unsigned char manufacturer_timing; + unsigned short standard_timings[8]; + unsigned char descriptors[4][MAX_DESCRIPTOR_LENGTH]; + unsigned char extensions; +} S_EDID_DATA; + +EDID_PARSER_RESULT edid_parse(S_EDID_DATA *edid, unsigned char *raw_data, + unsigned int len); + +#endif /* EDID_PARSER_H */ diff --git a/drivers/video/imx/hdp/externs.h b/drivers/video/imx/hdp/externs.h new file mode 100644 index 00000000000..31ed64693ef --- /dev/null +++ b/drivers/video/imx/hdp/externs.h @@ -0,0 +1,85 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copyright 2017-2018 NXP + * + ****************************************************************************** + * + * externs.h + * + ****************************************************************************** + */ + +#ifndef EXTERNS_H_ +#define EXTERNS_H_ + +#ifndef __UBOOT__ +#include + +#else +#include +#endif +/** + * \addtogroup UTILS + * \{ + */ +/** + * \brief read from apb + * \param addr - address to read + * \param value - pointer to store value + * \return non-zero value if error + */ +/*extern int cdn_bus_read(unsigned int addr, unsigned int* value);*/ + +/** + * \brief write to apb + * \param addr - address to write + * \param value - value to write + * \return non-zero if error + */ +/*extern int cdn_bus_write(unsigned int addr, unsigned int value);*/ + +uint32_t cdn_apb_read(uint32_t addr, uint32_t *value); +uint32_t cdn_sapb_read(uint32_t addr, uint32_t *value); +uint32_t cdn_apb_write(uint32_t addr, uint32_t value); +uint32_t cdn_sapb_write(uint32_t addr, uint32_t value); +uint32_t hdp_rx_apb_read(uint32_t addr, uint32_t *value); +uint32_t hdp_rx_sapb_read(uint32_t addr, uint32_t *value); +uint32_t hdp_rx_apb_write(uint32_t addr, uint32_t value); +uint32_t hdp_rx_sapb_write(uint32_t addr, uint32_t value); +#endif + diff --git a/drivers/video/imx/hdp/general_handler.h b/drivers/video/imx/hdp/general_handler.h new file mode 100644 index 00000000000..4a3132cf06e --- /dev/null +++ b/drivers/video/imx/hdp/general_handler.h @@ -0,0 +1,163 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copyright 2017-2018 NXP + * + ****************************************************************************** + * + * general_handler.h + * + ****************************************************************************** + */ + +#ifndef GENERAL_HANDLER_H +#define GENERAL_HANDLER_H + +/** + * \file + * \brief general handler, checks available messages, receives + * it from mailbox, handles requests and sends response + * to the host + */ +#define DP_TX_MAIL_HANDLER_REQUEST_BUFFER_LEN 256 + +/** + * \brief opcode defines host->controller + */ +#define GENERAL_MAIN_CONTROL 0x01 +#define GENERAL_TEST_ECHO 0x02 +#define GENERAL_BUS_SETTINGS 0x03 +#define GENERAL_TEST_ACCESS 0x04 + +#define GENERAL_WRITE_REGISTER 0x05 +#define GENERAL_WRITE_FIELD 0x06 +#define GENERAL_READ_REGISTER 0x07 +#define GENERAL_GET_HPD_STATE 0x11 + +#define GENERAL_TEST_TRNG_SIMPLE 0xF0 + +#define GENERAL_MAIN_CONTROL_SET_ACTIVE_BIT 0 +#define GENERAL_MAIN_CONTROL_SET_ALT_CIPHER_ADDR 1 +#define GENERAL_MAIN_CONTROL_SET_FAST_HDCP_DELAYS 2 + +#define GENERAL_BUS_SETTINGS_DPCD_BUS_BIT 0 +#define GENERAL_BUS_SETTINGS_DPCD_BUS_LOCK_BIT 1 +#define GENERAL_BUS_SETTINGS_HDCP_BUS_BIT 2 +#define GENERAL_BUS_SETTINGS_HDCP_BUS_LOCK_BIT 3 +#define GENERAL_BUS_SETTINGS_CAPB_OWNER_BIT 4 +#define GENERAL_BUS_SETTINGS_CAPB_OWNER_LOCK_BIT 5 + +/** + * \brief opcode defines controller->host + */ + +#define GENERAL_MAIN_CONTROL_RESP 0x01 +#define GENERAL_TEST_ECHO_RESP 0x02 +#define GENERAL_BUS_SETTINGS_RESP 0x03 + +#define GENERAL_READ_REGISTER_RESP 0x07 + +#define GENERAL_BUS_SETTINGS_RESP_DPCD_BUS_BIT 0 +#define GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT 1 +#define GENERAL_BUS_SETTINGS_RESP_CAPB_OWNER_BIT 2 + +#define GENERAL_BUS_SETTINGS_RESP_SUCCESS 0 +#define GENERAL_BUS_SETTINGS_RESP_LOCK_ERROR 1 + +typedef struct { + unsigned char dpcd_locked; + unsigned char hdcp_locked; + unsigned char capb_locked; + unsigned char active_mode; +} S_GENERAL_HANDLER_DATA; + +/** + * \brief event id sent to the host + */ +typedef enum { + EVENT_ID_DPTX_HPD = 0, + EVENT_ID_HDMI_TX_HPD = 0, + EVENT_ID_HDMI_RX_5V = 0, + + EVENT_ID_DPTX_TRAINING = 1, + EVENT_ID_HDMI_RX_SCDC_CHANGE = 1, + + EVENT_ID_RESERVE0 = 2, + EVENT_ID_RESERVE1 = 3, + + EVENT_ID_HDCPTX_STATUS = 4, + EVENT_ID_HDCPRX_STATUS = 4, + + EVENT_ID_HDCPTX_IS_KM_STORED = 5, + EVENT_ID_HDCPTX_STORE_KM = 6, + EVENT_ID_HDCPTX_IS_RECEIVER_ID_VALID = 7, + EVENT_ID_HDMITX_READ_REQUEST = 8, +} EVENT_ID; + +/** + * \brief convert bank id and register number to address and write to ptr + */ + +#define select_reg_old(bank, reg_no, ptr) \ +do { \ + ptr = 0; \ + if ((bank == 0x22) || (bank == 0x20) || (bank == 0x0b) || \ + (bank == 0x09) || (bank == 0x0A)) \ + ptr = (unsigned int *)(bank << 8 | reg_no); \ +} while (0) + +#define select_reg(bank, reg_no, ptr) \ + ptr = (unsigned int *)(bank << 8 | reg_no) + +#define select_reg4(pmsb, p2, p3, plsb, ptr) \ + ptr = (unsigned int *)((pmsb << 24) | (p2 << 16) | \ + (p3 << 8) | (plsb << 0)) + + +#define EVENTS_DPTX_CNT 2 +#define EVENTS_HDCPTX_CNT 4 + +void general_handler_set_active_mode(void); +void general_handler_set_standby_mode(void); + +/** + * \brief request sending en event to the host + * \param [in] eventId + * \param [in] eventCode + */ + +#endif /* GENERAL_HANDLER_H */ diff --git a/drivers/video/imx/hdp/hdmi.h b/drivers/video/imx/hdp/hdmi.h new file mode 100644 index 00000000000..a8989829f26 --- /dev/null +++ b/drivers/video/imx/hdp/hdmi.h @@ -0,0 +1,124 @@ +/****************************************************************************** + * + * Copyright (C) 2015-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * hdmi.h + * + ****************************************************************************** + */ + +#ifndef _HDMI__ +#define _HDMI__ +/* ONLY ENUMS AND #DEFINES IN THIS FILE * + * THIS FILE WILL BE USED IN HOST'S API */ + +#define EDID_SLAVE_ADDRESS 0x50 +#define EDID_SEGMENT_SLAVE_ADDRESS 0x30 +#define SCDC_SLAVE_ADDRESS 0x54 + +typedef enum { + HDMI_TX_READ, + HDMI_TX_WRITE, + HDMI_TX_UPDATE_READ, + HDMI_TX_EDID, + HDMI_TX_EVENTS, + HDMI_TX_HPD_STATUS, + HDMI_TX_DEBUG_ECHO = 0xAA, + HDMI_TX_TEST = 0xBB, + HDMI_TX_EDID_INTERNAL = 0xF0, +} HDMI_TX_OPCODE; + +typedef enum { + HDMI_I2C_ACK, + HDMI_I2C_NACK, + HDMI_I2C_TO, + HDMI_I2C_ARB_LOST, + HDMI_I2C_RRTO, + HDMI_I2C_RRT, + /** when i2c hardware didn't respond after some time */ + HDMI_I2C_HW_TO, + HDMI_I2C_ERR /*unspecified error */ +} HDMI_I2C_STATUS; + +typedef enum { + HDMI_RX_SET_EDID, + HDMI_RX_SCDC_SET, + HDMI_RX_SCDC_GET, + HDMI_RX_READ_EVENTS, + HDMI_RX_SET_HPD, + + HDMI_RX_DEBUG_ECHO = 0xAA, + HDMI_RX_TEST = 0xBB, +} HDMI_RX_OPCODE; + +typedef enum { + HDMI_SCDC_SINK_VER, + HDMI_SCDC_SOURCE_VER, +} HDMI_SCDC_FIELD; + +/*/////////////////////////////////////// */ +/*/////////////////////////////////////// */ +typedef struct { + unsigned char sink_ver; + unsigned char manufacturer_oui_1; + unsigned char manufacturer_oui_2; + unsigned char manufacturer_oui_3; + unsigned char devId[8]; + unsigned char hardware_major_rev; + unsigned char hardware_minor_rev; + unsigned char software_major_rev; + unsigned char software_minor_rev; + unsigned char manufacturerSpecific[34]; +} S_HDMI_SCDC_SET_MSG; + +typedef struct { + unsigned char source_ver; + unsigned char TMDS_Config; + unsigned char config_0; + unsigned char manufacturerSpecific[34]; +} S_HDMI_SCDC_GET_MSG; + +/*hpd events location */ +#define HDMI_RX_EVENT_5V_HIGH 0 +#define HDMI_RX_EVENT_5V_LOW 1 +#define HDMI_TX_EVENT_reserved 2 +#define HDMI_RX_EVENT_5V_VAL 3 + +#endif /*_HDMI__ */ diff --git a/drivers/video/imx/hdp/mhl_hdtx_top.h b/drivers/video/imx/hdp/mhl_hdtx_top.h new file mode 100644 index 00000000000..ee105f82489 --- /dev/null +++ b/drivers/video/imx/hdp/mhl_hdtx_top.h @@ -0,0 +1,220 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * mhl_hdtx_top.h + * + ****************************************************************************** + */ + +#ifndef MHL_HDTX_TOP_H_ +#define MHL_HDTX_TOP_H_ + +/* register SCHEDULER_H_SIZE */ +#define SCHEDULER_H_SIZE 0 +#define F_H_BLANK_SIZE(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_H_BLANK_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_H_ACTIVE_SIZE(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_H_ACTIVE_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register SCHEDULER_V_SIZE */ +#define SCHEDULER_V_SIZE 1 +#define F_V_BLANK_SIZE(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_V_BLANK_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_V_ACTIVE_SIZE(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_V_ACTIVE_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register SCHEDULER_KEEP_OUT */ +#define SCHEDULER_KEEP_OUT 2 +#define F_HKEEP_OUT(x) (((x) & ((1 << 9) - 1)) << 0) +#define F_HKEEP_OUT_RD(x) (((x) & (((1 << 9) - 1) << 0)) >> 0) +#define F_VKEEP_OUT_START(x) (((x) & ((1 << 11) - 1)) << 9) +#define F_VKEEP_OUT_START_RD(x) (((x) & (((1 << 11) - 1) << 9)) >> 9) +#define F_VKEEP_OUT_ZONE(x) (((x) & ((1 << 8) - 1)) << 20) +#define F_VKEEP_OUT_ZONE_RD(x) (((x) & (((1 << 8) - 1) << 20)) >> 20) + +/* register HDTX_SIGNAL_FRONT_WIDTH */ +#define HDTX_SIGNAL_FRONT_WIDTH 3 +#define F_HFRONT(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_HFRONT_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_VFRONT(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_VFRONT_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register HDTX_SIGNAL_SYNC_WIDTH */ +#define HDTX_SIGNAL_SYNC_WIDTH 4 +#define F_HSYNC(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_HSYNC_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_VSYNC(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_VSYNC_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register HDTX_SIGNAL_BACK_WIDTH */ +#define HDTX_SIGNAL_BACK_WIDTH 5 +#define F_HBACK(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_HBACK_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_VBACK(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_VBACK_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register HDTX_CONTROLLER */ +#define HDTX_CONTROLLER 6 +#define F_HDMI_MODE(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_HDMI_MODE_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) +#define F_VIF_DATA_WIDTH(x) (((x) & ((1 << 2) - 1)) << 2) +#define F_VIF_DATA_WIDTH_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2) +#define F_AUTO_MODE(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_AUTO_MODE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_IL_PROG(x) (((x) & ((1 << 2) - 1)) << 5) +#define F_IL_PROG_RD(x) (((x) & (((1 << 2) - 1) << 5)) >> 5) +#define F_PIC_3D(x) (((x) & ((1 << 4) - 1)) << 7) +#define F_PIC_3D_RD(x) (((x) & (((1 << 4) - 1) << 7)) >> 7) +#define F_BCH_EN(x) (((x) & ((1 << 1) - 1)) << 11) +#define F_BCH_EN_RD(x) (((x) & (((1 << 1) - 1) << 11)) >> 11) +#define F_GCP_EN(x) (((x) & ((1 << 1) - 1)) << 12) +#define F_GCP_EN_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12) +#define F_SET_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 13) +#define F_SET_AVMUTE_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13) +#define F_CLEAR_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 14) +#define F_CLEAR_AVMUTE_RD(x) (((x) & (((1 << 1) - 1) << 14)) >> 14) +#define F_DATA_EN(x) (((x) & ((1 << 1) - 1)) << 15) +#define F_DATA_EN_RD(x) (((x) & (((1 << 1) - 1) << 15)) >> 15) +#define F_HDMI_ENCODING(x) (((x) & ((1 << 2) - 1)) << 16) +#define F_HDMI_ENCODING_RD(x) (((x) & (((1 << 2) - 1) << 16)) >> 16) +#define F_HDMI2_PREAMBLE_EN(x) (((x) & ((1 << 1) - 1)) << 18) +#define F_HDMI2_PREAMBLE_EN_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18) +#define F_HDMI2_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 19) +#define F_HDMI2_CTRL_IL_MODE_RD(x) (((x) & (((1 << 1) - 1) << 19)) >> 19) + +/* register HDTX_HDCP */ +#define HDTX_HDCP 7 +#define F_HDTX_HDCP_SELECT(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_HDTX_HDCP_SELECT_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) +#define F_ENC_BIT(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_ENC_BIT_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_HDCP_ENABLE_1P1_FEATURES(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_HDCP_ENABLE_1P1_FEATURES_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_HDCP_DELAY_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_HDCP_DELAY_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_HDCP_DELAY_FIFO_SW_START(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_HDCP_DELAY_FIFO_SW_START_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_HDCP_DOUBLE_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_HDCP_DOUBLE_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_HDCP_SINGLE_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_HDCP_SINGLE_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) +#define F_HDCP_DELAY_FIFO_AFULL_THR(x) (((x) & ((1 << 4) - 1)) << 8) +#define F_HDCP_DELAY_FIFO_AFULL_THR_RD(x) (((x) & (((1 << 4) - 1) << 8)) >> 8) +#define F_HDCP_CTRL_SW_RST(x) (((x) & ((1 << 1) - 1)) << 12) +#define F_HDCP_CTRL_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12) +#define F_HDCP_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 13) +#define F_HDCP_CTRL_IL_MODE_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13) + +/* register HDTX_HPD */ +#define HDTX_HPD 8 +#define F_HPD_VALID_WIDTH(x) (((x) & ((1 << 12) - 1)) << 0) +#define F_HPD_VALID_WIDTH_RD(x) (((x) & (((1 << 12) - 1) << 0)) >> 0) +#define F_HPD_GLITCH_WIDTH(x) (((x) & ((1 << 8) - 1)) << 12) +#define F_HPD_GLITCH_WIDTH_RD(x) (((x) & (((1 << 8) - 1) << 12)) >> 12) + +/* register HDTX_CLOCK_REG_0 */ +#define HDTX_CLOCK_REG_0 9 +#define F_DATA_REGISTER_VAL_0(x) (((x) & ((1 << 20) - 1)) << 0) +#define F_DATA_REGISTER_VAL_0_RD(x) (((x) & (((1 << 20) - 1) << 0)) >> 0) + +/* register HDTX_CLOCK_REG_1 */ +#define HDTX_CLOCK_REG_1 10 +#define F_DATA_REGISTER_VAL_1(x) (((x) & ((1 << 20) - 1)) << 0) +#define F_DATA_REGISTER_VAL_1_RD(x) (((x) & (((1 << 20) - 1) << 0)) >> 0) + +/* register HPD_PLUG_IN */ +#define HPD_PLUG_IN 11 +#define F_FILTER_HPD(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_FILTER_HPD_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register HDCP_IN */ +#define HDCP_IN 12 +#define F_HDCP_ESS_STATE(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_HDCP_ESS_STATE_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +#define F_HDCP_DOUBLE_FIFO_WFULL(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_HDCP_DOUBLE_FIFO_WFULL_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_HDCP_DOUBLE_FIFO_REMPTY(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_HDCP_DOUBLE_FIFO_REMPTY_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_HDCP_DOUBLE_FIFO_OVERRUN(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_HDCP_DOUBLE_FIFO_OVERRUN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_HDCP_DOUBLE_FIFO_UNDERRUN(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_HDCP_DOUBLE_FIFO_UNDERRUN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) +#define F_HDCP_DELAY_FIFO_EMPTY(x) (((x) & ((1 << 1) - 1)) << 8) +#define F_HDCP_DELAY_FIFO_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8) +#define F_HDCP_DELAY_FIFO_FULL(x) (((x) & ((1 << 1) - 1)) << 9) +#define F_HDCP_DELAY_FIFO_FULL_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9) +#define F_HDCP_SINGLE_FIFO_WFULL(x) (((x) & ((1 << 2) - 1)) << 10) +#define F_HDCP_SINGLE_FIFO_WFULL_RD(x) (((x) & (((1 << 2) - 1) << 10)) >> 10) +#define F_HDCP_SINGLE_FIFO_REMPTY(x) (((x) & ((1 << 2) - 1)) << 12) +#define F_HDCP_SINGLE_FIFO_REMPTY_RD(x) (((x) & (((1 << 2) - 1) << 12)) >> 12) +#define F_HDCP_SINGLE_FIFO_OVERRUN(x) (((x) & ((1 << 2) - 1)) << 14) +#define F_HDCP_SINGLE_FIFO_OVERRUN_RD(x) (((x) & (((1 << 2) - 1) << 14)) >> 14) +#define F_HDCP_SINGLE_FIFO_UNDERRUN(x) (((x) & ((1 << 2) - 1)) << 16) +#define F_HDCP_SINGLE_FIFO_UNDERRUN_RD(x) (((x) & (((1 << 2) - 1) << 16)) >> 16) + +/* register GCP_FORCE_COLOR_DEPTH_CODING */ +#define GCP_FORCE_COLOR_DEPTH_CODING 13 +#define F_COLOR_DEPTH_VAL(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_COLOR_DEPTH_VAL_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +#define F_COLOR_DEPTH_FORCE(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_COLOR_DEPTH_FORCE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_DEFAULT_PHASE_VAL(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_DEFAULT_PHASE_VAL_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) + +/* register SSCP_POSITIONING */ +#define SSCP_POSITIONING 14 +#define F_SSCP_ROW_VAL(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_SSCP_ROW_VAL_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_SSCP_COL_VAL(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_SSCP_COL_VAL_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register HDCP_WIN_OF_OPP_POSITION */ +#define HDCP_WIN_OF_OPP_POSITION 15 +#define F_HDCP_WIN_OF_OPP_START(x) (((x) & ((1 << 10) - 1)) << 0) +#define F_HDCP_WIN_OF_OPP_START_RD(x) (((x) & (((1 << 10) - 1) << 0)) >> 0) +#define F_HDCP_WIN_OF_OPP_SIZE(x) (((x) & ((1 << 6) - 1)) << 10) +#define F_HDCP_WIN_OF_OPP_SIZE_RD(x) (((x) & (((1 << 6) - 1) << 10)) >> 10) + +#endif /*MHL_HDTX_TOP */ diff --git a/drivers/video/imx/hdp/opcodes.h b/drivers/video/imx/hdp/opcodes.h new file mode 100644 index 00000000000..fdc661c119b --- /dev/null +++ b/drivers/video/imx/hdp/opcodes.h @@ -0,0 +1,115 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copyright 2017-2018 NXP + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * opcodes.h + * + ****************************************************************************** + */ + +#ifndef OPCODES_H_ +# define OPCODES_H_ + +# define DP_TX_MAIL_HANDLER_H +# define DP_TX_MAIL_HANDLER_REQUEST_BUFFER_LEN 256 +# define DPTX_SET_POWER_MNG 0x00 +# define DPTX_SET_HOST_CAPABILITIES 0x01 +# define DPTX_GET_EDID 0x02 +# define DPTX_READ_DPCD 0x03 +# define DPTX_WRITE_DPCD 0x04 +# define DPTX_ENABLE_EVENT 0x05 +# define DPTX_WRITE_REGISTER 0x06 +# define DPTX_READ_REGISTER 0x07 +# define DPTX_WRITE_FIELD 0x08 +# define DPTX_TRAINING_CONTROL 0x09 +# define DPTX_READ_EVENT 0x0A +# define DPTX_READ_LINK_STAT 0x0B +# define DPTX_SET_VIDEO 0x0C +# define DPTX_SET_AUDIO 0x0D +# define DPTX_GET_LAST_AUX_STAUS 0x0E +# define DPTX_SET_LINK_BREAK_POINT 0x0F +# define DPTX_FORCE_LANES 0x10 +# define DPTX_HPD_STATE 0x11 +# define DPTX_DBG_SET 0xF0 +# define DP_TX_OPCODE_READ_I2C_REQUEST 0xA5 +# define DP_TX_OPCODE_WRITE_I2C_REQUEST 0xA6 +# define DP_TX_OPCODE_MESSAGE_FILTER 0xA7 +# define DPTX_EDID_RESP 0x02 +# define DPTX_DPCD_READ_RESP 0x03 +# define DPTX_DPCD_WRITE_RESP 0x04 +# define DPTX_READ_EVENT_RESP 0x0A +# define DPTX_READ_REGISTER_RESP 0x07 +# define DP_TX_OPCODE_MESSAGE 0x10 +# define DP_TX_OPCODE_READ_I2C_RESPONSE 0x50 +# define DP_TX_OPCODE_WRITE_I2C_RESPONSE 0x60 +# define DP_TX_OPCODE_LOOPBACK_TEST 0xFE +# define DP_TX_OPCODE_BIT_TEST 0xFF +# define DP_TX_EVENT_ENABLE_HPD_BIT 0x00 +# define DP_TX_EVENT_ENABLE_TRAINING_BIT 0x01 +# define DP_TX_EVENT_CODE_HPD_HIGH 0x01 +# define DP_TX_EVENT_CODE_HPD_LOW 0x02 +# define DP_TX_EVENT_CODE_HPD_PULSE 0x04 +# define DP_TX_EVENT_CODE_HPD_STATE_HIGH 0x08 +# define DP_TX_EVENT_CODE_HPD_STATE_LOW 0x00 +# define DP_TX_EVENT_CODE_TRAINING_FULL_STARTED 0x01 +# define DP_TX_EVENT_CODE_TRAINING_FAST_STARTED 0x02 +# define DP_TX_EVENT_CODE_TRAINING_FINISHED_CR 0x04 +# define DP_TX_EVENT_CODE_TRAINING_FINISHED_EQ 0x08 +# define DP_TX_EVENT_CODE_TRAINING_FINISHED_FAST 0x10 +# define DP_TX_EVENT_CODE_TRAINING_FAILED_CR 0x20 +# define DP_TX_EVENT_CODE_TRAINING_FAILED_EQ 0x40 +# define DP_TX_EVENT_CODE_TRAINING_FAILED_FAST 0x80 +# define MB_MODULE_ID_DP_TX 0x01 +# define MB_MODULE_ID_DP_RX 0x02 +# define MB_MODULE_ID_HDMI_TX 0x03 +# define MB_MODULE_ID_HDMI_RX 0x04 +# define MB_MODULE_ID_MHL_TX 0x05 +# define MB_MODULE_ID_MHL_RX 0x06 +# define MB_MODULE_ID_HDCP_TX 0x07 +# define MB_MODULE_ID_HDCP_RX 0x08 +# define MB_MODULE_ID_HDCP_GENERAL 0x09 +# define MB_MODULE_ID_GENERAL 0x0A +# define MB_MODULE_ID 1 + +#endif diff --git a/drivers/video/imx/hdp/source_car.h b/drivers/video/imx/hdp/source_car.h new file mode 100644 index 00000000000..1a5f85f8aaa --- /dev/null +++ b/drivers/video/imx/hdp/source_car.h @@ -0,0 +1,179 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * source_car.h + * + ****************************************************************************** + */ + +#ifndef SOURCE_CAR_H_ +#define SOURCE_CAR_H_ + +/* register SOURCE_HDTX_CAR */ +#define SOURCE_HDTX_CAR 0 +#define F_HDTX_PIXEL_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_HDTX_PIXEL_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_HDTX_PIXEL_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_HDTX_PIXEL_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_HDTX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_HDTX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_HDTX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_HDTX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_HDTX_PHY_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_HDTX_PHY_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_HDTX_PHY_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_HDTX_PHY_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_HDTX_PHY_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_HDTX_PHY_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_HDTX_PHY_CHAR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_HDTX_PHY_CHAR_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) + +/* register SOURCE_DPTX_CAR */ +#define SOURCE_DPTX_CAR 1 +#define F_CFG_DPTX_VIF_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_CFG_DPTX_VIF_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_CFG_DPTX_VIF_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_CFG_DPTX_VIF_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_DPTX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_DPTX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_DPTX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_DPTX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_SOURCE_AUX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_SOURCE_AUX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_SOURCE_AUX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_SOURCE_AUX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_DPTX_PHY_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_DPTX_PHY_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_DPTX_PHY_CHAR_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_DPTX_PHY_CHAR_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) +#define F_DPTX_PHY_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 8) +#define F_DPTX_PHY_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8) +#define F_DPTX_PHY_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 9) +#define F_DPTX_PHY_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9) +#define F_DPTX_FRMR_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 10) +#define F_DPTX_FRMR_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 10)) >> 10) +#define F_DPTX_FRMR_DATA_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 11) +#define F_DPTX_FRMR_DATA_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 11)) >> 11) + +/* register SOURCE_PHY_CAR */ +#define SOURCE_PHY_CAR 2 +#define F_SOURCE_PHY_DATA_OUT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_PHY_DATA_OUT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_DATA_OUT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_PHY_DATA_OUT_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_SOURCE_PHY_CHAR_OUT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_SOURCE_PHY_CHAR_OUT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 3)) >> 3) + +/* register SOURCE_CEC_CAR */ +#define SOURCE_CEC_CAR 3 +#define F_SOURCE_CEC_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_CEC_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_CEC_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_CEC_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) + +/* register SOURCE_CBUS_CAR */ +#define SOURCE_CBUS_CAR 4 +#define F_SOURCE_CBUS_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_CBUS_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_CBUS_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_CBUS_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) + +/* register SOURCE_PKT_CAR */ +#define SOURCE_PKT_CAR 6 +#define F_SOURCE_PKT_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_PKT_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_PKT_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_PKT_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_SOURCE_PKT_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_SOURCE_PKT_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_SOURCE_PKT_SYS_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_SOURCE_PKT_SYS_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) + +/* register SOURCE_AIF_CAR */ +#define SOURCE_AIF_CAR 7 +#define F_SOURCE_AIF_PKT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_AIF_PKT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_AIF_PKT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_AIF_PKT_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_SOURCE_AIF_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_SOURCE_AIF_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_SOURCE_AIF_SYS_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_SOURCE_AIF_SYS_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_SPDIF_CDR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_SPDIF_CDR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_SPDIF_CDR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_SPDIF_CDR_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_SPDIF_MCLK_EN(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_SPDIF_MCLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_SPDIF_MCLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_SPDIF_MCLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) + +/* register SOURCE_CIPHER_CAR */ +#define SOURCE_CIPHER_CAR 8 +#define F_SOURCE_CIPHER_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_CIPHER_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_CIPHER_CHAR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_CIPHER_CHAR_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_SOURCE_CIPHER_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_SOURCE_CIPHER_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 3)) >> 3) + +/* register SOURCE_CRYPTO_CAR */ +#define SOURCE_CRYPTO_CAR 9 +#define F_SOURCE_CRYPTO_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_CRYPTO_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_CRYPTO_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_CRYPTO_SYS_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 1)) >> 1) + +#endif /*SOURCE_CAR */ diff --git a/drivers/video/imx/hdp/source_phy.h b/drivers/video/imx/hdp/source_phy.h new file mode 100644 index 00000000000..540809db971 --- /dev/null +++ b/drivers/video/imx/hdp/source_phy.h @@ -0,0 +1,181 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * source_phy.h + * + ****************************************************************************** + */ + +#ifndef SOURCE_PHY_H_ +#define SOURCE_PHY_H_ + +/* register SHIFT_PATTERN_IN_3_0 */ +#define SHIFT_PATTERN_IN_3_0 0 +#define F_SOURCE_PHY_SHIFT_PATTERN0(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SOURCE_PHY_SHIFT_PATTERN0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_SHIFT_PATTERN1(x) (((x) & ((1 << 8) - 1)) << 8) +#define F_SOURCE_PHY_SHIFT_PATTERN1_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_SHIFT_PATTERN2(x) (((x) & ((1 << 8) - 1)) << 16) +#define F_SOURCE_PHY_SHIFT_PATTERN2_RD(x) (((x) & (((1 << 8) - 1) << 16)) >> 16) +#define F_SOURCE_PHY_SHIFT_PATTERN3(x) (((x) & ((1 << 8) - 1)) << 24) +#define F_SOURCE_PHY_SHIFT_PATTERN3_RD(x) (((x) & (((1 << 8) - 1) << 24)) >> 24) + +/* register SHIFT_PATTERN_IN_4_7 */ +#define SHIFT_PATTERN_IN_4_7 1 +#define F_SOURCE_PHY_SHIFT_PATTERN4(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SOURCE_PHY_SHIFT_PATTERN4_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_SHIFT_PATTERN5(x) (((x) & ((1 << 8) - 1)) << 8) +#define F_SOURCE_PHY_SHIFT_PATTERN5_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_SHIFT_PATTERN6(x) (((x) & ((1 << 8) - 1)) << 16) +#define F_SOURCE_PHY_SHIFT_PATTERN6_RD(x) (((x) & (((1 << 8) - 1) << 16)) >> 16) +#define F_SOURCE_PHY_SHIFT_PATTERN7(x) (((x) & ((1 << 8) - 1)) << 24) +#define F_SOURCE_PHY_SHIFT_PATTERN7_RD(x) (((x) & (((1 << 8) - 1) << 24)) >> 24) + +/* register SHIFT_PATTERN_IN9_8 */ +#define SHIFT_PATTERN_IN9_8 2 +#define F_SOURCE_PHY_SHIFT_PATTERN8(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SOURCE_PHY_SHIFT_PATTERN8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_SHIFT_PATTERN9(x) (((x) & ((1 << 8) - 1)) << 8) +#define F_SOURCE_PHY_SHIFT_PATTERN9_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_SHIFT_LOAD(x) (((x) & ((1 << 1) - 1)) << 16) +#define F_SOURCE_PHY_SHIFT_LOAD_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16) +#define F_SOURCE_PHY_SHIFT_EN(x) (((x) & ((1 << 1) - 1)) << 17) +#define F_SOURCE_PHY_SHIFT_EN_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17) +#define F_SOURCE_PHY_SHIFT_REPETITION(x) (((x) & ((1 << 3) - 1)) << 18) +#define F_SOURCE_PHY_SHIFT_REPETITION_RD(x) \ + (((x) & (((1 << 3) - 1) << 18)) >> 18) + +/* register PRBS_CNTRL */ +#define PRBS_CNTRL 3 +#define F_SOURCE_PHY_PRBS0_MODE(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_SOURCE_PHY_PRBS0_MODE_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_PRBS0_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 2) +#define F_SOURCE_PHY_PRBS0_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2) +#define F_SOURCE_PHY_PRBS1_MODE(x) (((x) & ((1 << 2) - 1)) << 4) +#define F_SOURCE_PHY_PRBS1_MODE_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4) +#define F_SOURCE_PHY_PRBS1_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 6) +#define F_SOURCE_PHY_PRBS1_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 6)) >> 6) +#define F_SOURCE_PHY_PRBS2_MODE(x) (((x) & ((1 << 2) - 1)) << 8) +#define F_SOURCE_PHY_PRBS2_MODE_RD(x) (((x) & (((1 << 2) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_PRBS2_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 10) +#define F_SOURCE_PHY_PRBS2_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 10)) >> 10) +#define F_SOURCE_PHY_PRBS3_MODE(x) (((x) & ((1 << 2) - 1)) << 12) +#define F_SOURCE_PHY_PRBS3_MODE_RD(x) (((x) & (((1 << 2) - 1) << 12)) >> 12) +#define F_SOURCE_PHY_PRBS3_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 14) +#define F_SOURCE_PHY_PRBS3_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 14)) >> 14) + +/* register PRBS_ERR_INSERTION */ +#define PRBS_ERR_INSERTION 4 +#define F_ADD_ERROR0(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_ADD_ERROR0_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_NUMBER_OF_ERRORS0(x) (((x) & ((1 << 5) - 1)) << 1) +#define F_NUMBER_OF_ERRORS0_RD(x) (((x) & (((1 << 5) - 1) << 1)) >> 1) +#define F_ADD_ERROR1(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_ADD_ERROR1_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_NUMBER_OF_ERRORS1(x) (((x) & ((1 << 5) - 1)) << 7) +#define F_NUMBER_OF_ERRORS1_RD(x) (((x) & (((1 << 5) - 1) << 7)) >> 7) +#define F_ADD_ERROR2(x) (((x) & ((1 << 1) - 1)) << 12) +#define F_ADD_ERROR2_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12) +#define F_NUMBER_OF_ERRORS2(x) (((x) & ((1 << 5) - 1)) << 13) +#define F_NUMBER_OF_ERRORS2_RD(x) (((x) & (((1 << 5) - 1) << 13)) >> 13) +#define F_ADD_ERROR3(x) (((x) & ((1 << 1) - 1)) << 18) +#define F_ADD_ERROR3_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18) +#define F_NUMBER_OF_ERRORS3(x) (((x) & ((1 << 5) - 1)) << 19) +#define F_NUMBER_OF_ERRORS3_RD(x) (((x) & (((1 << 5) - 1) << 19)) >> 19) + +/* register LANES_CONFIG */ +#define LANES_CONFIG 5 +#define F_SOURCE_PHY_LANE0_SWAP(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_SOURCE_PHY_LANE0_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_LANE1_SWAP(x) (((x) & ((1 << 2) - 1)) << 2) +#define F_SOURCE_PHY_LANE1_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2) +#define F_SOURCE_PHY_LANE2_SWAP(x) (((x) & ((1 << 2) - 1)) << 4) +#define F_SOURCE_PHY_LANE2_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4) +#define F_SOURCE_PHY_LANE3_SWAP(x) (((x) & ((1 << 2) - 1)) << 6) +#define F_SOURCE_PHY_LANE3_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 6)) >> 6) +#define F_SOURCE_PHY_LANE0_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 8) +#define F_SOURCE_PHY_LANE0_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_LANE1_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 9) +#define F_SOURCE_PHY_LANE1_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9) +#define F_SOURCE_PHY_LANE2_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 10) +#define F_SOURCE_PHY_LANE2_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 10)) >> 10) +#define F_SOURCE_PHY_LANE3_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 11) +#define F_SOURCE_PHY_LANE3_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 11)) >> 11) +#define F_SOURCE_PHY_AUX_SPARE(x) (((x) & ((1 << 4) - 1)) << 12) +#define F_SOURCE_PHY_AUX_SPARE_RD(x) (((x) & (((1 << 4) - 1) << 12)) >> 12) +#define F_SOURCE_PHY_LANE0_POLARITY(x) (((x) & ((1 << 1) - 1)) << 16) +#define F_SOURCE_PHY_LANE0_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16) +#define F_SOURCE_PHY_LANE1_POLARITY(x) (((x) & ((1 << 1) - 1)) << 17) +#define F_SOURCE_PHY_LANE1_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17) +#define F_SOURCE_PHY_LANE2_POLARITY(x) (((x) & ((1 << 1) - 1)) << 18) +#define F_SOURCE_PHY_LANE2_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18) +#define F_SOURCE_PHY_LANE3_POLARITY(x) (((x) & ((1 << 1) - 1)) << 19) +#define F_SOURCE_PHY_LANE3_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 19)) >> 19) +#define F_SOURCE_PHY_DATA_DEL_EN(x) (((x) & ((1 << 1) - 1)) << 20) +#define F_SOURCE_PHY_DATA_DEL_EN_RD(x) (((x) & (((1 << 1) - 1) << 20)) >> 20) +#define F_SOURCE_PHY_COMB_BYPASS(x) (((x) & ((1 << 1) - 1)) << 21) +#define F_SOURCE_PHY_COMB_BYPASS_RD(x) (((x) & (((1 << 1) - 1) << 21)) >> 21) +#define F_SOURCE_PHY_20_10(x) (((x) & ((1 << 1) - 1)) << 22) +#define F_SOURCE_PHY_20_10_RD(x) (((x) & (((1 << 1) - 1) << 22)) >> 22) + +/* register PHY_DATA_SEL */ +#define PHY_DATA_SEL 6 +#define F_SOURCE_PHY_DATA_SEL(x) (((x) & ((1 << 3) - 1)) << 0) +#define F_SOURCE_PHY_DATA_SEL_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_MHDP_SEL(x) (((x) & ((1 << 2) - 1)) << 3) +#define F_SOURCE_PHY_MHDP_SEL_RD(x) (((x) & (((1 << 2) - 1) << 3)) >> 3) + +/* register LANES_DEL_VAL */ +#define LANES_DEL_VAL 7 +#define F_SOURCE_PHY_LANE0_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_SOURCE_PHY_LANE0_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_LANE1_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 4) +#define F_SOURCE_PHY_LANE1_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4) +#define F_SOURCE_PHY_LANE2_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 8) +#define F_SOURCE_PHY_LANE2_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_LANE3_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 12) +#define F_SOURCE_PHY_LANE3_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 12)) >> 12) + +#endif /*SOURCE_PHY */ diff --git a/drivers/video/imx/hdp/source_pif.h b/drivers/video/imx/hdp/source_pif.h new file mode 100644 index 00000000000..b9cbe16659d --- /dev/null +++ b/drivers/video/imx/hdp/source_pif.h @@ -0,0 +1,174 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * source_pif.h + * + ****************************************************************************** + */ + +#ifndef SOURCE_PIF_H_ +#define SOURCE_PIF_H_ + +/* register SOURCE_PIF_WR_ADDR */ +#define SOURCE_PIF_WR_ADDR 0 +#define F_WR_ADDR(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_WR_ADDR_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_WR_REQ */ +#define SOURCE_PIF_WR_REQ 1 +#define F_HOST_WR(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_HOST_WR_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_RD_ADDR */ +#define SOURCE_PIF_RD_ADDR 2 +#define F_RD_ADDR(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_RD_ADDR_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_RD_REQ */ +#define SOURCE_PIF_RD_REQ 3 +#define F_HOST_RD(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_HOST_RD_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_DATA_WR */ +#define SOURCE_PIF_DATA_WR 4 +/*# define F_DATA_WR(x) (((x) & ((1 << 32) - 1)) << 0) */ +/*# define F_DATA_WR_RD(x) (((x) & (((1 << 32) - 1) << 0)) >> 0) */ +#define F_DATA_WR(x) (((x) & 0xffffffff) << 0) +#define F_DATA_WR_RD(x) (((x) & 0xffffffff) >> 0) + +/* register SOURCE_PIF_DATA_RD */ +#define SOURCE_PIF_DATA_RD 5 +#define F_FIFO2_DATA_OUT(x) (((x) & ((1 << 32) - 1)) << 0) +#define F_FIFO2_DATA_OUT_RD(x) (((x) & (((1 << 32) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_FIFO1_FLUSH */ +#define SOURCE_PIF_FIFO1_FLUSH 6 +#define F_FIFO1_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_FIFO1_FLUSH_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_FIFO2_FLUSH */ +#define SOURCE_PIF_FIFO2_FLUSH 7 +#define F_FIFO2_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_FIFO2_FLUSH_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_STATUS */ +#define SOURCE_PIF_STATUS 8 +#define F_SOURCE_PKT_MEM_CTRL_FSM_STATE(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_SOURCE_PKT_MEM_CTRL_FSM_STATE_RD(x) \ + (((x) & (((1 << 2) - 1) << 0)) >> 0) +#define F_FIFO1_FULL(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_FIFO1_FULL_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_FIFO2_EMPTY(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_FIFO2_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) + +/* register SOURCE_PIF_INTERRUPT_SOURCE */ +#define SOURCE_PIF_INTERRUPT_SOURCE 9 +#define F_HOST_WR_DONE_INT(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_HOST_WR_DONE_INT_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_HOST_RD_DONE_INT(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_HOST_RD_DONE_INT_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_NONVALID_TYPE_REQUESTED_INT(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_NONVALID_TYPE_REQUESTED_INT_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_PSLVERR(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_PSLVERR_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_ALLOC_WR_DONE(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_ALLOC_WR_DONE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_ALLOC_WR_ERROR(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_ALLOC_WR_ERROR_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_FIFO1_OVERFLOW(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_FIFO1_OVERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_FIFO1_UNDERFLOW(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_FIFO1_UNDERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) +#define F_FIFO2_OVERFLOW(x) (((x) & ((1 << 1) - 1)) << 8) +#define F_FIFO2_OVERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8) +#define F_FIFO2_UNDERFLOW(x) (((x) & ((1 << 1) - 1)) << 9) +#define F_FIFO2_UNDERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9) + +/* register SOURCE_PIF_INTERRUPT_MASK */ +#define SOURCE_PIF_INTERRUPT_MASK 10 +#define F_HOST_WR_DONE_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_HOST_WR_DONE_INT_MASK_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_HOST_RD_DONE_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_HOST_RD_DONE_INT_MASK_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_NONVALID_TYPE_REQUESTED_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_NONVALID_TYPE_REQUESTED_INT_MASK_RD(x) \ + (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_PSLVERR_MASK(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_PSLVERR_MASK_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_ALLOC_WR_DONE_MASK(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_ALLOC_WR_DONE_MASK_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_ALLOC_WR_ERROR_MASK(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_ALLOC_WR_ERROR_MASK_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_FIFO1_OVERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_FIFO1_OVERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_FIFO1_UNDERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_FIFO1_UNDERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) +#define F_FIFO2_OVERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 8) +#define F_FIFO2_OVERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8) +#define F_FIFO2_UNDERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 9) +#define F_FIFO2_UNDERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9) + +/* register SOURCE_PIF_PKT_ALLOC_REG */ +#define SOURCE_PIF_PKT_ALLOC_REG 11 +#define F_PKT_ALLOC_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_PKT_ALLOC_ADDRESS_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +#define F_PACKET_TYPE(x) (((x) & ((1 << 8) - 1)) << 8) +#define F_PACKET_TYPE_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8) +#define F_TYPE_VALID(x) (((x) & ((1 << 1) - 1)) << 16) +#define F_TYPE_VALID_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16) +#define F_ACTIVE_IDLE_TYPE(x) (((x) & ((1 << 1) - 1)) << 17) +#define F_ACTIVE_IDLE_TYPE_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17) + +/* register SOURCE_PIF_PKT_ALLOC_WR_EN */ +#define SOURCE_PIF_PKT_ALLOC_WR_EN 12 +#define F_PKT_ALLOC_WR_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_PKT_ALLOC_WR_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_SW_RESET */ +#define SOURCE_PIF_SW_RESET 13 +#define F_SW_RST(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +#endif /*SOURCE_PIF */ diff --git a/drivers/video/imx/hdp/source_vif.h b/drivers/video/imx/hdp/source_vif.h new file mode 100644 index 00000000000..a9b6c00154f --- /dev/null +++ b/drivers/video/imx/hdp/source_vif.h @@ -0,0 +1,93 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * source_vif.h + * + ****************************************************************************** + */ + +#ifndef SOURCE_VIF_H_ +#define SOURCE_VIF_H_ + +/* register BND_HSYNC2VSYNC */ +#define BND_HSYNC2VSYNC 0 +#define F_IP_DTCT_WIN(x) (((x) & ((1 << 12) - 1)) << 0) +#define F_IP_DTCT_WIN_RD(x) (((x) & (((1 << 12) - 1) << 0)) >> 0) +#define F_IP_DET_EN(x) (((x) & ((1 << 1) - 1)) << 12) +#define F_IP_DET_EN_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12) +#define F_IP_VIF_BYPASS(x) (((x) & ((1 << 1) - 1)) << 13) +#define F_IP_VIF_BYPASS_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13) + +/* register HSYNC2VSYNC_F1_L1 */ +#define HSYNC2VSYNC_F1_L1 1 +#define F_IP_DTCT_HSYNC2VSYNC_F1(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_IP_DTCT_HSYNC2VSYNC_F1_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) + +/* register HSYNC2VSYNC_F2_L1 */ +#define HSYNC2VSYNC_F2_L1 2 +#define F_IP_DTCT_HSYNC2VSYNC_F2(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_IP_DTCT_HSYNC2VSYNC_F2_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) + +/* register HSYNC2VSYNC_STATUS */ +#define HSYNC2VSYNC_STATUS 3 +#define F_IP_DTCT_ERR(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_IP_DTCT_ERR_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_IP_DCT_IP(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_IP_DCT_IP_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_IP_DTCT_VJITTER(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_IP_DTCT_VJITTER_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_IP_DTCT_HJITTER(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_IP_DTCT_HJITTER_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) + +/* register HSYNC2VSYNC_POL_CTRL */ +#define HSYNC2VSYNC_POL_CTRL 4 +#define F_VPOL(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_VPOL_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_HPOL(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_HPOL_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_VIF_AUTO_MODE(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_VIF_AUTO_MODE_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +#endif /*SOURCE_VIF */ diff --git a/drivers/video/imx/hdp/test_base_sw.c b/drivers/video/imx/hdp/test_base_sw.c new file mode 100644 index 00000000000..a276c829e87 --- /dev/null +++ b/drivers/video/imx/hdp/test_base_sw.c @@ -0,0 +1,232 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copyright 2017-2018 NXP + * + ****************************************************************************** + * + * test_base_sw.c + * + ****************************************************************************** + */ + +#ifndef __UBOOT__ +#include +#include +#include +#else +#include +#include + +#ifdef CONFIG_ARCH_IMX8M +/* mscale */ +#define HDMI_BASE 0x32c00000 +#define HDMI_PHY_BASE 0x32c80000 +#define HDMI_SEC_BASE 0x32e40000 +#endif +#ifdef CONFIG_ARCH_IMX8 +/* QM */ +#define HDMI_BASE 0x56268000 +#define HDMI_SEC_BASE 0x56269000 +#define HDMI_OFFSET_ADDR 0x56261008 +#define HDMI_SEC_OFFSET_ADDR 0x5626100c + +#define HDMI_RX_BASE 0x58268000 +#define HDMI_RX_SEC_BASE 0x58269000 +#define HDMI_RX_OFFSET_ADDR 0x58261004 +#define HDMI_RX_SEC_OFFSET_ADDR 0x58261008 +#endif + +#endif + +#ifdef CONFIG_ARCH_IMX8M +int cdn_apb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + uint64_t tmp_addr = addr + HDMI_BASE; + temp = __raw_readl(tmp_addr); + *value = temp; + return 0; +} + +int cdn_apb_write(unsigned int addr, unsigned int value) +{ + uint64_t tmp_addr = addr + HDMI_BASE; + + __raw_writel(value, tmp_addr); + return 0; +} + +int cdn_sapb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + uint64_t tmp_addr = addr + HDMI_SEC_BASE; + temp = __raw_readl(tmp_addr); + *value = temp; + return 0; +} + +int cdn_sapb_write(unsigned int addr, unsigned int value) +{ + uint64_t tmp_addr = addr + HDMI_SEC_BASE; + __raw_writel(value, tmp_addr); + return 0; +} + +void cdn_sleep(uint32_t ms) +{ + mdelay(ms); +} + +void cdn_usleep(uint32_t us) +{ + udelay(us); +} +#endif +#ifdef CONFIG_ARCH_IMX8 +int cdn_apb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + uint64_t tmp_addr = (addr & 0xfff) + HDMI_BASE; + + /* printf("%s():%d addr = 0x%08x, tmp_addr = 0x%08x, offset = 0x%08x\n", + __func__, __LINE__, addr, (unsigned int)tmp_addr, addr>>12); */ + + __raw_writel(addr >> 12, HDMI_OFFSET_ADDR); + + temp = __raw_readl(tmp_addr); + /* printf("%s():%d temp = 0x%08x\n", __func__, __LINE__, temp ); */ + + *value = temp; + return 0; +} + +int cdn_apb_write(unsigned int addr, unsigned int value) +{ + uint64_t tmp_addr = (addr & 0xfff) + HDMI_BASE; + + /*printf("%s():%d addr=0x%08x, taddr=0x%08x, off=0x%08x, val=0x%08x\n", + __func__, __LINE__, addr, (unsigned int)tmp_addr, + addr>>12, value);*/ + + __raw_writel(addr >> 12, HDMI_OFFSET_ADDR); + + /* printf("%s():%d\n", __func__, __LINE__); */ + __raw_writel(value, tmp_addr); + + return 0; +} + +int cdn_sapb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + uint64_t tmp_addr = (addr & 0xfff) + HDMI_SEC_BASE; + + __raw_writel(addr >> 12, HDMI_SEC_OFFSET_ADDR); + + temp = __raw_readl(tmp_addr); + *value = temp; + return 0; +} + +int cdn_sapb_write(unsigned int addr, unsigned int value) +{ + uint64_t tmp_addr = (addr & 0xfff) + HDMI_SEC_BASE; + + __raw_writel(addr >> 12, HDMI_SEC_OFFSET_ADDR); + __raw_writel(value, tmp_addr); + + return 0; +} + +int hdp_rx_apb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + uint64_t tmp_addr = (addr & 0xfff) + HDMI_RX_BASE; + + __raw_writel(addr >> 12, HDMI_RX_OFFSET_ADDR); + + temp = __raw_readl(tmp_addr); + + *value = temp; + return 0; +} + +int hdp_rx_apb_write(unsigned int addr, unsigned int value) +{ + uint64_t tmp_addr = (addr & 0xfff) + HDMI_RX_BASE; + + __raw_writel(addr >> 12, HDMI_RX_OFFSET_ADDR); + + __raw_writel(value, tmp_addr); + + return 0; +} + +int hdp_rx_sapb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + uint64_t tmp_addr = (addr & 0xfff) + HDMI_RX_SEC_BASE; + + __raw_writel(addr >> 12, HDMI_RX_SEC_OFFSET_ADDR); + + temp = __raw_readl(tmp_addr); + *value = temp; + return 0; +} + +int hdp_rx_sapb_write(unsigned int addr, unsigned int value) +{ + uint64_t tmp_addr = (addr & 0xfff) + HDMI_RX_SEC_BASE; + + __raw_writel(addr >> 12, HDMI_RX_SEC_OFFSET_ADDR); + __raw_writel(value, tmp_addr); + + return 0; +} + +void cdn_sleep(uint32_t ms) +{ + mdelay(ms); +} + +void cdn_usleep(uint32_t us) +{ + udelay(us); +} +#endif + diff --git a/drivers/video/imx/hdp/util.c b/drivers/video/imx/hdp/util.c new file mode 100644 index 00000000000..e74aaa509cc --- /dev/null +++ b/drivers/video/imx/hdp/util.c @@ -0,0 +1,329 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copyright 2017-2018 NXP + * + ****************************************************************************** + * + * util.c + * + ****************************************************************************** + */ + +#include "util.h" +#include "API_General.h" +#include "externs.h" +#ifndef __UBOOT__ +#include +#endif +#include "apb_cfg.h" +#include "opcodes.h" +#ifndef __UBOOT__ +#include + +#endif +state_struct state; + +int cdn_bus_read(unsigned int addr, unsigned int *value) +{ + return state.bus_type ? + cdn_sapb_read(addr, value) : cdn_apb_read(addr, value); +} + +int cdn_bus_write(unsigned int addr, unsigned int value) +{ + return state.bus_type ? + cdn_sapb_write(addr, value) : cdn_apb_write(addr, value); +} + +void internal_itobe(int val, volatile unsigned char *dest, int bytes) +{ + int i; + for (i = bytes - 1; i >= 0; --i) { + dest[i] = (unsigned char)val; + val >>= 8; + } +} + +uint32_t internal_betoi(volatile uint8_t const *src, uint8_t bytes) +{ + uint32_t ret = 0; + int i; + + if (bytes > sizeof(ret)) { + printf("Warning. Read request for payload larger then supported.\n"); + bytes = sizeof(ret); + } + + for (i = 0; i < bytes; ++i) { + ret <<= 8; + ret |= (unsigned int)src[i]; + } + + return ret; +} + +unsigned int internal_mkmsg(volatile unsigned char *dest, int valno, ...) +{ + va_list vl; + unsigned int len = 0; + va_start(vl, valno); + len = internal_vmkmsg(dest, valno, vl); + va_end(vl); + return len; +} + +unsigned int internal_vmkmsg(volatile unsigned char *dest, int valno, + va_list vl) +{ + unsigned int len = 0; + int i; + for (i = 0; i < valno; ++i) { + int size = va_arg(vl, int); + if (size > 0) { + internal_itobe(va_arg(vl, int), dest, size); + dest += size; + len += size; + } else { + memcpy((void *)dest, va_arg(vl, void *), -size); + dest -= size; + len -= size; + } + } + return len; +} + +void internal_tx_mkfullmsg(unsigned char module, unsigned char opcode, + int valno, ...) +{ + va_list vl; + va_start(vl, valno); + internal_vtx_mkfullmsg(module, opcode, valno, vl); + va_end(vl); +} + +void internal_vtx_mkfullmsg(unsigned char module, unsigned char opcode, + int valno, va_list vl) +{ + unsigned int len = + internal_vmkmsg(state.txbuffer + INTERNAL_CMD_HEAD_SIZE, valno, vl); + internal_mbox_tx_enable(module, opcode, len); + state.txenable = 1; + state.running = 1; +} + +void internal_readmsg(int valno, ...) +{ + va_list vl; + va_start(vl, valno); + internal_vreadmsg(valno, vl); + va_end(vl); +} + +void internal_vreadmsg(int valno, va_list vl) +{ + uint8_t *src = state.rxbuffer + INTERNAL_CMD_HEAD_SIZE; + size_t i; + + for (i = 0; i < (size_t) valno; ++i) { + int size = va_arg(vl, int); + void *ptr = va_arg(vl, void *); + + if (!ptr) { + src += size; + } else if (!size) { + *((unsigned char **)ptr) = src; + } else if (size > 0) { + switch ((size_t) size) { + case sizeof(uint8_t): + *((uint8_t *)ptr) = internal_betoi(src, size); + break; + case sizeof(uint16_t): + *((uint16_t *)ptr) = internal_betoi(src, size); + break; + case 3: /* 3-byte value (e.g. DPCD address) + can be safely converted from BE.*/ + case sizeof(uint32_t): + *((uint32_t *)ptr) = internal_betoi(src, size); + break; + default: + printf("Warning. Unsupported variable size.\n"); + memcpy(ptr, src, size); + }; + + src += size; + } else { + memcpy(ptr, src, -size); + src -= size; + } + } +} + +INTERNAL_MBOX_STATUS mailbox_write(unsigned char val) +{ + INTERNAL_MBOX_STATUS ret; + unsigned int full; + if (cdn_bus_read(MAILBOX_FULL_ADDR << 2, &full)) { + ret.tx_status = CDN_TX_APB_ERROR; + return ret; + } + if (full) { + ret.tx_status = CDN_TX_FULL; + return ret; + } + if (cdn_bus_write(MAILBOX0_WR_DATA << 2, val)) { + ret.tx_status = CDN_TX_APB_ERROR; + return ret; + } + ret.tx_status = CDN_TX_WRITE; + return ret; +} + +INTERNAL_MBOX_STATUS mailbox_read(volatile unsigned char *val) +{ + INTERNAL_MBOX_STATUS ret; + unsigned int empty; + unsigned int rd; + if (cdn_bus_read(MAILBOX_EMPTY_ADDR << 2, &empty)) { + ret.rx_status = CDN_RX_APB_ERROR; + return ret; + } + if (empty) { + ret.rx_status = CDN_RX_EMPTY; + return ret; + } + if (cdn_bus_read(MAILBOX0_RD_DATA << 2, &rd)) { + ret.rx_status = CDN_RX_APB_ERROR; + return ret; + } + *val = (unsigned char)rd; + ret.rx_status = CDN_RX_READ; + return ret; +} + +INTERNAL_MBOX_STATUS internal_mbox_tx_process(void) +{ + unsigned int txcount = 0; + unsigned int length = + (unsigned int)state.txbuffer[2] << 8 | (unsigned int)state. + txbuffer[3]; + INTERNAL_MBOX_STATUS ret = {.txend = 0 }; + ret.tx_status = CDN_TX_NOTHING; + INTERNAL_MBOX_STATUS tx_ret; + if (!state.txenable) + return ret; + while ((tx_ret.tx_status = + mailbox_write(state.txbuffer[state.txi]).tx_status) == + CDN_TX_WRITE) { + txcount++; + if (++state.txi >= length + 4) { + state.txenable = 0; + state.txi = 0; + ret.txend = 1; + break; + } + } + if (txcount && tx_ret.tx_status == CDN_TX_FULL) + ret.tx_status = CDN_TX_WRITE; + else + ret.tx_status = tx_ret.tx_status; + return ret; +} + +INTERNAL_MBOX_STATUS internal_mbox_rx_process(void) +{ + unsigned int rxcount = 0; + INTERNAL_MBOX_STATUS ret = { 0, 0, 0, 0 }; + INTERNAL_MBOX_STATUS rx_ret; + while ((rx_ret.rx_status = + mailbox_read(state.rxbuffer + state.rxi).rx_status) == + CDN_RX_READ) { + rxcount++; + if (++state.rxi >= 4 + + ((unsigned int)state.rxbuffer[2] << 8 | + (unsigned int)state.rxbuffer[3])) { /* end of message */ + state.rxi = 0; + ret.rxend = 1; + state.rxenable = 0; + break; + } + } + ret.rx_status = rxcount ? CDN_RX_READ : CDN_RX_EMPTY; + return ret; +} + +unsigned int internal_apb_available(void) +{ + return !(state.rxenable || state.txenable); +} + +void internal_mbox_tx_enable(unsigned char module, unsigned char opcode, + unsigned short length) +{ + state.txbuffer[0] = opcode; + state.txbuffer[1] = module; + state.txbuffer[2] = (unsigned char)(length >> 8); + state.txbuffer[3] = (unsigned char)length; + state.txenable = 1; +} + +CDN_API_STATUS internal_test_rx_head(unsigned char module, unsigned char opcode) +{ + if (opcode != state.rxbuffer[0]) + return CDN_BAD_OPCODE; + if (module != state.rxbuffer[1]) + return CDN_BAD_MODULE; + return CDN_OK; +} + +CDN_API_STATUS internal_test_rx_head_match(void) +{ + return internal_test_rx_head(state.txbuffer[1], state.txbuffer[0]); +} + +void print_fw_ver(void) +{ + unsigned short ver, verlib; + cdn_api_general_getcurversion(&ver, &verlib); + printf("FIRMWARE VERSION: %d, LIB VERSION: %d\n", ver, verlib); +} + +unsigned short internal_get_msg_len(void) +{ + return ((unsigned short)state.rxbuffer[2] << 8) | (unsigned short)state. + rxbuffer[3]; +} diff --git a/drivers/video/imx/hdp/util.h b/drivers/video/imx/hdp/util.h new file mode 100644 index 00000000000..6e8b6b7f6f7 --- /dev/null +++ b/drivers/video/imx/hdp/util.h @@ -0,0 +1,281 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copyright 2017 NXP + * + ****************************************************************************** + * + * util.h + * + ****************************************************************************** + */ + +#ifndef UTIL_H_ +#define UTIL_H_ + +#include "API_General.h" +#ifndef __UBOOT__ +#include +#include +#else +#include +#endif +/** + * \addtogroup UTILS + * \{ + */ +#define INTERNAL_CMD_HEAD_SIZE 4 + +/** + * \brief expands to blocking function body + * \param x - function call + */ +#define internal_block_function(x) \ +do { \ + CDN_API_STATUS ret; \ + do { \ + ret = x; \ + } while (ret == CDN_BSY || ret == CDN_STARTED); \ + return ret; \ +} while (0) + +/** + * \brief write message and write response (if any), non-blocking way. Also sets state.running = 0 + */ +#define INTERNAL_PROCESS_MESSAGES \ +do { \ + if (state.txenable && !internal_mbox_tx_process().txend) \ + return CDN_BSY; \ + if (state.rxenable && !internal_mbox_rx_process().rxend) \ + return CDN_BSY; \ + state.running = 0; \ +} while (0) + +#define internal_opcode_ok_or_return(module, opcode) \ +do { \ + CDN_API_STATUS ret = internal_test_rx_head(module, opcode); \ + if (ret != CDN_OK) \ + return ret; \ +} while (0) + +#define internal_opcode_match_or_return() \ +do { \ + CDN_API_STATUS ret = internal_test_rx_head_match(); \ + if (ret != CDN_OK) \ + return ret; \ +} while (0) + +/* macro for simple tx only command, command format as in mkfullmsg + (with count) */ +#define internal_macro_command_tx(module, opcode, bustype, command...) \ +do { \ + if (!state.running) { \ + internal_tx_mkfullmsg(module, opcode, command); \ + state.bus_type = bustype; \ + return CDN_STARTED; \ + } \ + INTERNAL_PROCESS_MESSAGES; \ +} while (0) + +/* macro for command with response with matching opcode, command format as in + mkfullmsg (with count) */ +#define internal_macro_command_txrx(module, opcode, bustype, command...) \ +do { \ + if (!state.running) { \ + internal_tx_mkfullmsg(module, opcode, command); \ + state.bus_type = bustype; \ + state.rxenable = 1; \ + return CDN_STARTED; \ + } \ + INTERNAL_PROCESS_MESSAGES; \ + internal_opcode_match_or_return(); \ +} while (0) + +typedef struct { + /** apb write status */ + enum tx_status_enum { + /** one or more bytes written */ + CDN_TX_WRITE = 0, + /** nothing to write */ + CDN_TX_NOTHING = 1, + /** mailbox full, 0 bytes written */ + CDN_TX_FULL = 2, + /** APB error while writing */ + CDN_TX_APB_ERROR = 3 + } tx_status:3; + /** apb read status */ + enum rx_status_enum { + /** 1 or more bytes read */ + CDN_RX_READ = 0, + /** mailbox empty, 0 bytes read */ + CDN_RX_EMPTY = 1, + /** apb error while reading */ + CDN_RX_APB_ERROR = 2 + } rx_status:2; + /** indicates end of currenly recived message */ + unsigned char rxend:1; + /** end of tx message reached */ + unsigned char txend:1; +} INTERNAL_MBOX_STATUS; + +/** + * \brief put val into dest in big endian format + * \param val - value to put + * \param dest - place to put value + * \param bytes - true size of val in bytes. for example if + * bytes = 2 val is treated as short int + */ +void internal_itobe(int val, volatile unsigned char *dest, int bytes); + +/** + * \brief read big endian value from src and return it + * \param src - source to read from + * \param bytes - size of read value + * \return result + */ +uint32_t internal_betoi(volatile uint8_t const *src, uint8_t bytes); + +/** + * \brief create message from size and value pairs; also sets + * state.running and state.txEnable + * \param dest - pointer to write message to + * \param valNo - number of values to write + * \param ... - pairs of size and value, each value is written + * after another. if size is positive value, value is + * written with #internal_itobe, if size is negative, + * value is treated as src pointer for memcpy + * + * example: + * + * unsigned short x = 0xAABB; + * + * internal_mkmsg(dest, 3, 1, 1, 2, 3, -2, &x); + * + * will write 01 00 03 AA BB to dest + */ +unsigned int internal_mkmsg(volatile unsigned char *dest, int valno, ...); +unsigned int internal_vmkmsg(volatile unsigned char *dest, int valno, + va_list vl); + +/** + * \brief setup message header in txBuffer, set txEnable = 1 + */ +void internal_mbox_tx_enable(unsigned char module, unsigned char opcode, + unsigned short length); + +/** + * \brief write from txBuffer to mailbox untill full or end of message. + * + * when txEnable == 0 writes nothing + * when write reaches end of message set txEnable = 0 + */ + +/** + * \brief combination of #internal_mkmsg and #internal_mbox_tx_enable + * + * #internal_mkmsg dest and #internal_mbox_tx_enable length are determined + * automaticly this function also sets state.txEnable = 1 and + * state.running + */ +void internal_tx_mkfullmsg(unsigned char module, unsigned char opcode, + int valno, ...); +void internal_vtx_mkfullmsg(unsigned char module, unsigned char opcode, + int valno, va_list vl); + +/** + * \brief read from state.txBuffer and store results in specified pointers + * \param valNo - numbero of values to read + * \param ... - pairs of size and ptr + * + * this function is similar to #internal_mkmsg - + * + * when size is positive read value using #internal_betoi + * when size is negative mempcy from txBuffer to ptr -size bytes + * when size is 0 write to ptr addres of current position in rxbuffer + * when ptr is NULL ignore size bytes (if size is negative this + * will rewind buffer) + */ +void internal_readmsg(int valno, ...); +void internal_vreadmsg(int valno, va_list vl); + +INTERNAL_MBOX_STATUS internal_mbox_tx_process(void); +/** + * \brief read to rxBuffer from mailbox untill empty or end of message + * + * when rxEnable == 0 reads nothing + * when end of message reached sets rxEnable = 0 + */ +INTERNAL_MBOX_STATUS internal_mbox_rx_process(void); + +/** + * \brief check if apb is available + * \return !(rxEnable && txEable) + */ +unsigned int internal_apb_available(void); + +/** + * \brief test if parameters match module and opcode in rxBuffer + * \return CDN_OK or CDN_BAD_OPCODE or CDN_BAD_MODULE + */ +CDN_API_STATUS internal_test_rx_head(unsigned char module, + unsigned char opcode); + +CDN_API_STATUS internal_test_rx_head_match(void); + +/** + * \brief print current fw and lib version + */ +void print_fw_ver(void); + +typedef struct { + unsigned char txbuffer[1024]; + unsigned char rxbuffer[1024]; + unsigned int txi; /* iterators */ + unsigned int rxi; + unsigned char txenable; /*data readt to send*/ + unsigned char rxenable; + unsigned char running; + CDN_BUS_TYPE bus_type; + unsigned int tmp; +} state_struct; + +extern state_struct state; +extern int cdn_bus_read(unsigned int addr, unsigned int* value); +extern int cdn_bus_write(unsigned int addr, unsigned int value); +unsigned short internal_get_msg_len(void); + +#endif diff --git a/drivers/video/imx/hdp/vic_table.c b/drivers/video/imx/hdp/vic_table.c new file mode 100644 index 00000000000..c4984008189 --- /dev/null +++ b/drivers/video/imx/hdp/vic_table.c @@ -0,0 +1,68 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * vic_table.c + * + ****************************************************************************** + */ +#include "vic_table.h" + +const unsigned int vic_table[VIC_MODE_COUNT][27] = { + {858, 720, 138, 62, 16, 60, 525, 480, 45, 6, 9, 30, 59, 27000, + PROGRESSIVE, ACTIVE_LOW, ACTIVE_LOW, 1, 65535, 1, 46, 65535, 65535, 3, + 8, 0}, + {1650, 1280, 370, 40, 110, 220, 750, 720, 30, 5, 5, 20, 60, 74250, + PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 1, 65535, 1, 31, 65535, 65535, + 4, 8, 0}, + {2200, 1920, 280, 44, 88, 148, 1125, 1080, 45, 5, 4, + 36, 60, 148500, PROGRESSIVE, ACTIVE_HIGH, + ACTIVE_HIGH, 1, 65535, 1, 46, 65535, 65535, 16, 8, 0}, + {4400, 3840, 560, 88, 176, 296, 2250, 2160, 90, 10, 8, 72, 60, + 594000, PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 4, 266, 262, 22, 525, + 285, 97, 8, 0}, + {4400, 3840, 560, 88, 176, 296, 2250, 2160, 90, 10, 8, 72, 30, + 297000, PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 4, 266, 262, 22, 525, + 285, 95, 8, 0}, +}; diff --git a/drivers/video/imx/hdp/vic_table.h b/drivers/video/imx/hdp/vic_table.h new file mode 100644 index 00000000000..dce88347b7e --- /dev/null +++ b/drivers/video/imx/hdp/vic_table.h @@ -0,0 +1,140 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * vic_table.h + * + ****************************************************************************** + */ + +#ifndef VIC_TABLE_H_ +#define VIC_TABLE_H_ + +#define PROGRESSIVE 0 +#define INTERLACED 1 + +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +typedef enum { + H_TOTAL, + H_ACTIVE, + H_BLANK, + HSYNC, + FRONT_PORCH, + BACK_PORCH, + /* H_FREQ_KHZ, */ + V_TOTAL, + V_ACTIVE, + V_BLANK, + VSYNC, + TYPE_EOF, + SOF, + V_FREQ_HZ, + PIXEL_FREQ_KHZ, + I_P, + HSYNC_POL, + VSYNC_POL, + START_OF_F0, + START_OF_F1, + VSYNC_START_INTERLACED_F0, + VSYNC_END_INTERLACED_F0, + VSYNC_START_INTERLACED_F1, + VSYNC_END_INTERLACED_F1, + VIC, + VIC_R3_0, + VIC_PR, +} MSA_PARAM; + +typedef enum { + NUM_OF_LANES_1 = 1, + NUM_OF_LANES_2 = 2, + NUM_OF_LANES_4 = 4, +} VIC_NUM_OF_LANES; + +typedef enum { + RATE_1_6 = 162, + RATE_2_7 = 270, + RATE_5_4 = 540, + RATE_8_1 = 810, +} VIC_SYMBOL_RATE; + +typedef enum { + PXL_RGB = 0x1, + YCBCR_4_4_4 = 0x2, + YCBCR_4_2_2 = 0x4, + YCBCR_4_2_0 = 0x8, + Y_ONLY = 0x10, +} VIC_PXL_ENCODING_FORMAT; + +typedef enum { + BCS_6 = 0x1, + BCS_8 = 0x2, + BCS_10 = 0x4, + BCS_12 = 0x8, + BCS_16 = 0x10, +} VIC_COLOR_DEPTH; + +typedef enum { + STEREO_VIDEO_LEFT = 0x0, + STEREO_VIDEO_RIGHT = 0x1, +} STEREO_VIDEO_ATTR; + +typedef enum { + BT_601 = 0x0, + BT_709 = 0x1, +} BT_TYPE; + +typedef enum { + VIC_MODE_3_59_94Hz, + VIC_MODE_4_60Hz, + VIC_MODE_16_60Hz, + VIC_MODE_97_60Hz, + VIC_MODE_95_30Hz, + VIC_MODE_COUNT +} VIC_MODES; + +extern const unsigned int vic_table[VIC_MODE_COUNT][27]; + +#endif diff --git a/drivers/video/imx/hdp_load.c b/drivers/video/imx/hdp_load.c new file mode 100644 index 00000000000..62d0351ae72 --- /dev/null +++ b/drivers/video/imx/hdp_load.c @@ -0,0 +1,123 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "API_General.h" +#include "scfw_utils.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define ON 1 +#define OFF 0 + +static void display_set_power(int onoff) +{ + sc_ipc_t ipch = gd->arch.ipc_channel_handle; + + SC_PM_SET_RESOURCE_POWER_MODE(ipch, SC_R_DC_0, onoff); + SC_PM_SET_RESOURCE_POWER_MODE(ipch, SC_R_HDMI, onoff); +} + +static void display_set_clocks(void) +{ + sc_ipc_t ipch = gd->arch.ipc_channel_handle; + const sc_pm_clock_rate_t pll = 800000000; + const sc_pm_clock_rate_t hdmi_core_clock = pll / 4; /* 200 Mhz */ + const sc_pm_clock_rate_t hdmi_bus_clock = pll / 8; /* 100 Mhz */ + + SC_PM_SET_RESOURCE_POWER_MODE(ipch, + SC_R_HDMI_PLL_0, SC_PM_PW_MODE_OFF); + SC_PM_SET_CLOCK_RATE(ipch, + SC_R_HDMI_PLL_0, SC_PM_CLK_PLL, pll); + SC_PM_SET_RESOURCE_POWER_MODE(ipch, + SC_R_HDMI_PLL_0, SC_PM_PW_MODE_ON); + + /* HDMI DI Bus Clock */ + SC_PM_SET_CLOCK_RATE(ipch, + SC_R_HDMI, SC_PM_CLK_MISC4, hdmi_bus_clock); + /* HDMI DI Core Clock */ + SC_PM_SET_CLOCK_RATE(ipch, + SC_R_HDMI, SC_PM_CLK_MISC2, hdmi_core_clock); +} + +static void display_enable_clocks(int enable) +{ + sc_ipc_t ipch = gd->arch.ipc_channel_handle; + + SC_PM_CLOCK_ENABLE(ipch, SC_R_HDMI_PLL_0, SC_PM_CLK_PLL, enable); + SC_PM_CLOCK_ENABLE(ipch, SC_R_HDMI, SC_PM_CLK_MISC2, enable); + SC_PM_CLOCK_ENABLE(ipch, SC_R_HDMI, SC_PM_CLK_MISC4, enable); + if (enable == OFF) + SC_PM_SET_RESOURCE_POWER_MODE(ipch, SC_R_HDMI_PLL_0, + SC_PM_PW_MODE_OFF); +} + +int do_hdp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + if (argc < 2) + return 0; + + if (strncmp(argv[1], "tracescfw", 9) == 0) { + g_debug_scfw = 1; + printf("Enabled SCFW API tracing\n"); + } else if (strncmp(argv[1], "load", 4) == 0) { + unsigned long address = 0; + unsigned long offset = 0x2000; + const int iram_size = 0x10000; + const int dram_size = 0x8000; + const char *s; + sc_ipc_t ipch = gd->arch.ipc_channel_handle; + + if (argc > 2) { + address = simple_strtoul(argv[2], NULL, 0); + if (argc > 3) + offset = simple_strtoul(argv[3], NULL, 0); + } else { + printf("Missing address\n"); + } + + printf("Loading hdp firmware from 0x%016lx offset 0x%016lx\n", + address, offset); + display_set_power(SC_PM_PW_MODE_ON); + display_set_clocks(); + display_enable_clocks(ON); + cdn_api_loadfirmware((unsigned char *)(address + offset), + iram_size, + (unsigned char *)(address + offset + + iram_size), + dram_size); + + s = env_get("hdp_authenticate_fw"); + if (s && !strcmp(s, "yes")) + SC_MISC_AUTH(ipch, SC_MISC_SECO_AUTH_HDMI_TX_FW, 0); + + display_enable_clocks(OFF); + printf("Loading hdp firmware Complete\n"); + + /* do not turn off hdmi power or firmware load will be lost */ + } else { + printf("test error argc %d\n", argc); + } + + return 0; +} + +/***************************************************/ +U_BOOT_CMD( + hdp, CONFIG_SYS_MAXARGS, 1, do_hdp, + "load hdmi firmware ", + "[] ...\n" + "hdpload [address] []\n" + " address - address where the binary image starts\n" + " - IRAM offset in the binary image (8192 default)\n" + "\n" + " if \"hdp_authenticate_fw\" is set to \"yes\", the seco\n" + " will authenticate the firmware and load HDCP keys.\n" + "\n" + "tracescfw - Trace SCFW API calls for video commands\n" + ); diff --git a/drivers/video/imx/hdprx_load.c b/drivers/video/imx/hdprx_load.c new file mode 100644 index 00000000000..028693441ba --- /dev/null +++ b/drivers/video/imx/hdprx_load.c @@ -0,0 +1,85 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "API_General.h" +#include "scfw_utils.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define ON 1 +#define OFF 0 + +static void hdmi_rx_set_power(int onoff) +{ + sc_ipc_t ipch = gd->arch.ipc_channel_handle; + + SC_PM_SET_RESOURCE_POWER_MODE(ipch, SC_R_ISI_CH0, onoff); + SC_PM_SET_RESOURCE_POWER_MODE(ipch, SC_R_HDMI_RX, onoff); + SC_PM_SET_RESOURCE_POWER_MODE(ipch, SC_R_HDMI_RX_BYPASS, onoff); +} + +int do_hdprx(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + if (argc < 2) + return 0; + + if (strncmp(argv[1], "tracescfw", 9) == 0) { + g_debug_scfw = 1; + printf("Enabled SCFW API tracing\n"); + } else if (strncmp(argv[1], "load", 4) == 0) { + unsigned long address = 0; + unsigned long offset = 0x2000; + const int iram_size = 0x10000; + const int dram_size = 0x8000; + const char *s; + sc_ipc_t ipch = gd->arch.ipc_channel_handle; + + if (argc > 2) { + address = simple_strtoul(argv[2], NULL, 0); + if (argc > 3) + offset = simple_strtoul(argv[3], NULL, 0); + } else { + printf("Missing address\n"); + } + + printf("Loading hdprx firmware from 0x%016lx offset 0x%016lx\n", + address, offset); + hdmi_rx_set_power(SC_PM_PW_MODE_ON); + hdp_rx_loadfirmware((unsigned char *)(address + offset), + iram_size, + (unsigned char *)(address + offset + + iram_size), + dram_size); + + s = env_get("hdprx_authenticate_fw"); + if (s && !strcmp(s, "yes")) + SC_MISC_AUTH(ipch, SC_MISC_SECO_AUTH_HDMI_RX_FW, 0); + printf("Loading hdp rx firmware Complete\n"); + /* do not turn off hdmi power or firmware load will be lost */ + } else { + printf("test error argc %d\n", argc); + } + + return 0; +} + +/***************************************************/ +U_BOOT_CMD( + hdprx, CONFIG_SYS_MAXARGS, 1, do_hdprx, + "load hdmi rx firmware ", + "[] ...\n" + "hdpload [address] []\n" + " address - address where the binary image starts\n" + " - IRAM offset in the binary image (8192 default)\n" + "\n" + " if \"hdprx_authenticate_fw\" is set to \"yes\", the seco\n" + " will authenticate the firmware and load HDCP keys.\n" + "\n" + "tracescfw - Trace SCFW API calls for video commands\n" + ); diff --git a/drivers/video/imx/imx8_hdmi.c b/drivers/video/imx/imx8_hdmi.c new file mode 100644 index 00000000000..3d73c139c24 --- /dev/null +++ b/drivers/video/imx/imx8_hdmi.c @@ -0,0 +1,296 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include "API_General.h" +#include "vic_table.h" +#include "API_HDMITX.h" +#include "apb_cfg.h" +#include "externs.h" +#include "API_AVI.h" +#include "address.h" +#include "source_car.h" +#include "source_phy.h" +#include "API_AFE.h" +#include "source_vif.h" +#include "general_handler.h" +#include "mhl_hdtx_top.h" + + +#ifdef CONFIG_IMX8QM +#include "API_AFE_mcu1_dp.h" +#include "API_AFE_ss28fdsoi_kiran_hdmitx.h" +#endif + +#ifdef CONFIG_IMX8M +#include "API_AFE_t28hpc_hdmitx.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define ON 1 +#define OFF 0 + +unsigned long g_encoding = 1; /* 1 RGB, 2 YUV 444, 4 YUV 422, 8 YUV 420 */ +unsigned long g_color_depth = 8; /* 8 pits per color */ + +static int imx8_hdmi_set_vic_mode(int vic, + struct video_mode_settings *vms) +{ + /*struct video_mode_settings *vms = &vm_settings[VM_USER]; */ + uint32_t pixel_clock_kHz; + uint32_t frame_rate_Hz; + uint32_t frame_rate_frac_Hz; + uint32_t cea_vic; + char iflag; + + if (vic >= VIC_MODE_COUNT) { + debug("%s(): unsupported VIC\n", __func__); + return -1; + } + + + vms->hfp = vic_table[vic][FRONT_PORCH]; + vms->hbp = vic_table[vic][BACK_PORCH]; + vms->hsync = vic_table[vic][HSYNC]; + vms->vfp = vic_table[vic][TYPE_EOF]; + vms->vbp = vic_table[vic][SOF]; + vms->vsync = vic_table[vic][VSYNC]; + vms->xres = vic_table[vic][H_ACTIVE]; + vms->yres = vic_table[vic][V_ACTIVE]; + + vms->hpol = vic_table[vic][HSYNC_POL] != 0; + vms->vpol = vic_table[vic][VSYNC_POL] != 0; + + cea_vic = vic_table[vic][VIC]; + if (vic_table[vic][I_P] != 0) + iflag = 'i'; + else + iflag = 'p'; + pixel_clock_kHz = vic_table[vic][PIXEL_FREQ_KHZ]; + frame_rate_Hz = vic_table[vic][V_FREQ_HZ] * 1000; + frame_rate_frac_Hz = frame_rate_Hz % 1000; + frame_rate_Hz /= 1000; + + vms->pixelclock = pixel_clock_kHz; + + debug("Cadence VIC %3d, CEA VIC %3d: %4d x %4d %c @ %3d.%03d [%6d kHz] Vpol=%d Hpol=%d\n", + vic, cea_vic, vms->xres, vms->yres, iflag, frame_rate_Hz, + frame_rate_frac_Hz, pixel_clock_kHz, vms->vpol, vms->hpol); + + debug(" mode timing fp sync bp h:%3d %3d %3d v:%3d %3d %3d\n", + vms->hfp, vms->hsync, vms->hbp, vms->vfp, vms->vsync, vms->vbp); + + return 0; + /*debug("leaving %s() ...\n", __func__); */ +} + +static int imx8_hdmi_init(int vic, + int encoding, + int color_depth, + bool pixel_clk_from_phy) +{ + int ret; +#ifdef CONFIG_IMX8QM + sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle; + void __iomem *hdmi_csr_base = (void __iomem *)0x56261000; +#endif + /*GENERAL_Read_Register_response regresp; */ + /*uint8_t sts; */ + uint32_t character_freq_khz; + + uint8_t echo_msg[] = "echo test"; + uint8_t echo_resp[sizeof(echo_msg) + 1]; + /*uint8_t response; */ + /*uint8_t dpcd_resp; */ + /*uint8_t hdcp_resp; */ + /*uint8_t capb_resp; */ + /*uint32_t temp; */ + + /*================================================================== */ + /* Parameterization: */ + /*================================================================== */ + + /* VIC Mode - index from vic_table (see API_SRC/vic_table.c) */ + VIC_MODES vic_mode = vic; + + /* Pixel Encodeing Format */ + /* PXL_RGB = 0x1, */ + /* YCBCR_4_4_4 = 0x2, */ + /* YCBCR_4_2_2 = 0x4, */ + /* YCBCR_4_2_0 = 0x8, */ + /* Y_ONLY = 0x10, */ + VIC_PXL_ENCODING_FORMAT format = encoding; + /*VIC_PXL_ENCODING_FORMAT format = 1; */ + + /* B/W Balance Type: 0 no data, 1 IT601, 2 ITU709 */ + BT_TYPE bw_type = 0; + + /* bpp (bits per subpixel) - 8 24bpp, 10 30bpp, 12 36bpp, 16 48bpp */ + uint8_t bps = color_depth; + + /* Set HDMI TX Mode */ + /* Mode = 0 - DVI, 1 - HDMI1.4, 2 HDMI 2.0 */ + HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE ptype = 1; + + if (vic_mode == VIC_MODE_97_60Hz) + ptype = 2; + + /*================================================================== */ + /* Parameterization done */ + /*================================================================== */ +#ifdef CONFIG_IMX8QM + /* set the pixel link mode and pixel type */ + SC_MISC_SET_CONTROL(ipcHndl, SC_R_HDMI, SC_C_PHY_RESET, 0); +#if 1 + SC_MISC_SET_CONTROL(ipcHndl, SC_R_DC_0, SC_C_PXL_LINK_MST1_ADDR, 1); + /*SC_MISC_SET_CONTROL(ipcHndl, SC_R_DC_0, SC_C_PXL_LINK_MST1_ADDR, 0);*/ + if (g_clock_mode == CLOCK_MODES_HDMI_DUAL) { + SC_MISC_SET_CONTROL(ipcHndl, SC_R_DC_0, + SC_C_PXL_LINK_MST2_ADDR, 2); + /*SC_MISC_SET_CONTROL(ipcHndl, SC_R_DC_0, + SC_C_PXL_LINK_MST2_ADDR, 0); */ + __raw_writel(0x6, hdmi_csr_base); + } else +#endif + __raw_writel(0x34, hdmi_csr_base); +#endif + cdn_api_init(); + debug("CDN_API_Init completed\n"); + + ret = cdn_api_checkalive(); + debug("CDN_API_CheckAlive returned ret = %d\n", ret); + + if (ret) + return -EPERM; + + ret = cdn_api_general_test_echo_ext_blocking(echo_msg, + echo_resp, + sizeof(echo_msg), + CDN_BUS_TYPE_APB); + debug("_General_Test_Echo_Ext_blocking - (ret = %d echo_resp = %s)\n", + ret, echo_resp); + + /* Configure PHY */ + character_freq_khz = phy_cfg_t28hpc(4, vic_mode, bps, + format, pixel_clk_from_phy); + debug("phy_cfg_t28hpc (character_freq_mhz = %d)\n", + character_freq_khz); + + /*phy_reset(1); */ + +#ifdef CONFIG_IMX8QM + SC_MISC_SET_CONTROL(ipcHndl, SC_R_HDMI, SC_C_PHY_RESET, 1); +#endif + hdmi_tx_t28hpc_power_config_seq(4); +#ifdef CONFIG_IMX8QM + /* Set the lane swapping */ + ret = cdn_api_general_write_register_blocking + (ADDR_SOURCD_PHY + (LANES_CONFIG << 2), + F_SOURCE_PHY_LANE0_SWAP(3) | F_SOURCE_PHY_LANE1_SWAP(0) | + F_SOURCE_PHY_LANE2_SWAP(1) | F_SOURCE_PHY_LANE3_SWAP(2) | + F_SOURCE_PHY_COMB_BYPASS(0) | F_SOURCE_PHY_20_10(1)); +#else + /* Set the lane swapping */ + ret = cdn_api_general_write_register_blocking + (ADDR_SOURCD_PHY + (LANES_CONFIG << 2), + F_SOURCE_PHY_LANE0_SWAP(0) | F_SOURCE_PHY_LANE1_SWAP(1) | + F_SOURCE_PHY_LANE2_SWAP(2) | F_SOURCE_PHY_LANE3_SWAP(3) | + F_SOURCE_PHY_COMB_BYPASS(0) | F_SOURCE_PHY_20_10(1)); +#endif + debug("_General_Write_Register_blocking LANES_CONFIG ret = %d\n", ret); + + ret = CDN_API_HDMITX_Init_blocking(); + debug("CDN_API_STATUS CDN_API_HDMITX_Init_blocking ret = %d\n", ret); + + ret = CDN_API_HDMITX_Init_blocking(); + debug("CDN_API_STATUS CDN_API_HDMITX_Init_blocking ret = %d\n", ret); + + ret = CDN_API_HDMITX_Set_Mode_blocking(ptype, character_freq_khz); + debug("CDN_API_HDMITX_Set_Mode_blocking ret = %d\n", ret); + + ret = cdn_api_set_avi(vic_mode, format, bw_type); + debug("cdn_api_set_avi ret = %d\n", ret); + + ret = CDN_API_HDMITX_SetVic_blocking(vic_mode, bps, format); + debug("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret); + +#ifdef CONFIG_IMX8QM + { + GENERAL_Read_Register_response regresp; + /* adjust the vsync/hsync polarity */ + cdn_api_general_read_register_blocking(ADDR_SOURCE_VIF + + (HSYNC2VSYNC_POL_CTRL + << 2), + ®resp); + debug("Initial HSYNC2VSYNC_POL_CTRL: 0x%x\n", regresp.val); + if ((regresp.val & 0x3) != 0) + __raw_writel(0x4, hdmi_csr_base); + } +#endif + /*regresp.val &= ~0x03; // clear HSP and VSP bits */ + /*debug("Final HSYNC2VSYNC_POL_CTRL: 0x%x\n",regresp.val); */ + /*CDN_API_General_Write_Register_blocking(ADDR_DPTX_FRAMER + + (DP_FRAMER_SP << 2), + regresp.val); */ + + udelay(20000); + + return 0; +} + +int imx8_hdmi_enable(int encoding, + struct video_mode_settings *vms) +{ + int vic = 0; + const int use_phy_pixel_clk = 1; + + /* map the resolution to a VIC index in the vic table*/ + if ((vms->xres == 1280) && (vms->yres == 720)) + vic = 1; /* 720p60 */ + else if ((vms->xres == 1920) && (vms->yres == 1080)) + vic = 2; /* 1080p60 */ + else if ((vms->xres == 3840) && (vms->yres == 2160)) + vic = 3; /* 2160p60 */ + else /* if ((vms->xres == 720) && (vms->yres == 480)) */ + vic = 0; /* 480p60 */ + + imx8_hdmi_set_vic_mode(vic, vms); + return imx8_hdmi_init(vic, encoding, g_color_depth, use_phy_pixel_clk); +} + +void imx8_hdmi_disable(void) +{ + int ret; + GENERAL_READ_REGISTER_RESPONSE resp; + + resp.val = 0; + ret = cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + &resp); + if (ret != CDN_OK) { + printf("%s(): dn_api_general_read_register_blocking failed\n", + __func__); + /*return;*/ + } + + resp.val &= ~F_DATA_EN(1); /* disable HDMI */ + /*resp.val |= F_SET_AVMUTE( 1);*/ + + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + if (ret != CDN_OK) { + printf("%s(): dn_api_general_write_register_blocking failed\n", + __func__); + return; + } +} diff --git a/drivers/video/imx/scfw_utils.h b/drivers/video/imx/scfw_utils.h new file mode 100644 index 00000000000..d8764e81052 --- /dev/null +++ b/drivers/video/imx/scfw_utils.h @@ -0,0 +1,102 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _SCFW_UTILS_H_ +#define _SCFW_UTILS_H_ + +#include +#include + +static int g_debug_scfw; /* set to one to turn on SCFW API tracing */ + +#define SC_PM_SET_CLOCK_PARENT(__ipcHndl__, __res__, __clk__, __parent__) \ +do { \ + char _res_str[] = #__res__;\ + char _clk_str[] = #__clk__;\ + sc_err_t _ret;\ + if (g_debug_scfw) \ + printf("(%4d) sc_pm_set_clock_parent %s:%s -> %d\n",\ + __LINE__, _res_str, _clk_str, __parent__);\ + _ret = sc_pm_set_clock_parent(__ipcHndl__,\ + __res__, __clk__, __parent__);\ + if (_ret != SC_ERR_NONE) \ + printf("(%d)>> sc_pm_set_clock_parent failed! %s:%s -> %d (error = %d)\n",\ + __LINE__, _res_str, _clk_str, __parent__, _ret);\ +} while (0) + +#define SC_PM_SET_CLOCK_RATE(__ipcHndl__, __res__, __clk__, __rate__) \ +do { \ + char _res_str[] = #__res__;\ + char _clk_str[] = #__clk__;\ + sc_err_t _ret;\ + sc_pm_clock_rate_t _actual = __rate__;\ + if (g_debug_scfw) \ + printf("(%4d) sc_pm_set_clock_rate %s:%s -> %d\n",\ + __LINE__, _res_str, _clk_str, __rate__);\ + _ret = sc_pm_set_clock_rate(__ipcHndl__, __res__, __clk__, &_actual);\ + if (_ret != SC_ERR_NONE)\ + printf("(%4d)>> sc_pm_set_clock_rate failed! %s:%s -> %d (error = %d)\n",\ + __LINE__, _res_str, _clk_str, __rate__, _ret);\ + if (_actual != __rate__)\ + printf("(%4d)>> Actual rate for %s:%s is %d instead of %d\n", \ + __LINE__, _res_str, _clk_str, _actual, __rate__); \ +} while (0) + +#define SC_PM_CLOCK_ENABLE(__ipcHndl__, __res__, __clk__, __enable__) \ +do { \ + char _res_str[] = #__res__;\ + char _clk_str[] = #__clk__;\ + sc_err_t _ret;\ + if (g_debug_scfw) \ + printf("(%4d) sc_pm_clock_enable %s:%s -> %d\n",\ + __LINE__, _res_str, _clk_str, __enable__);\ + _ret = sc_pm_clock_enable(__ipcHndl__,\ + __res__, __clk__, __enable__, false);\ + if (_ret != SC_ERR_NONE)\ + printf("(%4d)>> sc_pm_clock_enable failed! %s:%s -> %d (error = %d)\n",\ + __LINE__, _res_str, _clk_str, __enable__, _ret);\ +} while (0) \ + +#define SC_MISC_SET_CONTROL(__ipcHndl__, __res__, __clk__, __value__) \ +do { \ + char _res_str[] = #__res__; \ + char _clk_str[] = #__clk__; \ + sc_err_t _ret; \ + if (g_debug_scfw) \ + printf("(%4d) sc_misc_set_control %s:%s -> %d\n",\ + __LINE__, _res_str, _clk_str, __value__);\ + _ret = sc_misc_set_control(__ipcHndl__, \ + __res__, __clk__, __value__); \ + if (_ret != SC_ERR_NONE) \ + printf("(%4d)>> sc_misc_set_control failed! %s:%s -> %d (error = %d)\n", \ + __LINE__, _res_str, _clk_str, __value__, _ret); \ +} while (0) + +#define SC_PM_SET_RESOURCE_POWER_MODE(__ipcHndl__, __res__, __enable__) \ +do { \ + char _res_str[] = #__res__; \ + sc_err_t _ret; \ + if (g_debug_scfw) \ + printf("(%4d) sc_pm_set_resource_power_mode %s -> %d\n",\ + __LINE__, _res_str, __enable__);\ + _ret = sc_pm_set_resource_power_mode(__ipcHndl__, __res__, __enable__);\ + if (_ret != SC_ERR_NONE) \ + printf("(%4d)>> sc_pm_set_resource_power_mode failed! %s -> %d (error = %d)\n", \ + __LINE__, _res_str, __enable__, _ret);\ +} while (0) + +#define SC_MISC_AUTH(__ipcHndl__, __cmd__, __addr__) \ +do { \ + sc_err_t _ret; \ + if (g_debug_scfw) \ + printf("(%4d) sc_misc_seco_authenticate -> cmd %d addr %d\n",\ + __LINE__, __cmd__, __addr__);\ + _ret = sc_misc_seco_authenticate(__ipcHndl__, __cmd__, __addr__); \ + if (_ret != SC_ERR_NONE) \ + printf("(%4d)>> sc_misc_seco_authenticate cmd %d addr %d (error = %d)\n", \ + __LINE__, __cmd__, __addr__, _ret); \ +} while (0) + +#endif /*_SCFW_UTILS_H_ */ diff --git a/drivers/video/imx_mipi_dsi_bridge.c b/drivers/video/imx_mipi_dsi_bridge.c new file mode 100644 index 00000000000..a3e9e26317d --- /dev/null +++ b/drivers/video/imx_mipi_dsi_bridge.c @@ -0,0 +1,104 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static struct mipi_dsi_bridge_driver *registered_driver = NULL; + +int imx_mipi_dsi_bridge_attach(struct mipi_dsi_client_dev *dsi_dev) +{ + int ret = 0; + + if (!registered_driver) + return -EPERM; + + if (registered_driver->attach) + ret = registered_driver->attach(registered_driver, dsi_dev); + + return ret; +} + +int imx_mipi_dsi_bridge_mode_set(struct fb_videomode *pvmode) +{ + int ret = 0; + + if (!registered_driver) + return -EPERM; + + if (registered_driver->mode_set) + ret = registered_driver->mode_set(registered_driver, pvmode); + + return ret; +} + +int imx_mipi_dsi_bridge_enable(void) +{ + int ret = 0; + + if (!registered_driver) + return -EPERM; + + if (registered_driver->enable) + ret = registered_driver->enable(registered_driver); + + return ret; +} + +int imx_mipi_dsi_bridge_disable(void) +{ + int ret = 0; + + if (!registered_driver) + return -EPERM; + + if (registered_driver->disable) + ret = registered_driver->disable(registered_driver); + + return ret; +} + +int imx_mipi_dsi_bridge_pkt_write(u8 data_type, const u8 *buf, int len) +{ + int ret = 0; + + if (!registered_driver) + return -EPERM; + + if (registered_driver->pkt_write) + ret = registered_driver->pkt_write(registered_driver, data_type, buf, len); + + return ret; +} + +int imx_mipi_dsi_bridge_add_client_driver(struct mipi_dsi_client_driver *client_driver) +{ + int ret = 0; + + if (!registered_driver) + return -EPERM; + + if (registered_driver->add_client_driver) + ret = registered_driver->add_client_driver(registered_driver, client_driver); + + return ret; +} + +int imx_mipi_dsi_bridge_register_driver(struct mipi_dsi_bridge_driver *driver) +{ + if (!driver) + return -EINVAL; + + if (registered_driver) + return -EBUSY; + + registered_driver = driver; + + return 0; +} diff --git a/drivers/video/imxdpuv1.c b/drivers/video/imxdpuv1.c new file mode 100644 index 00000000000..6b1864d3591 --- /dev/null +++ b/drivers/video/imxdpuv1.c @@ -0,0 +1,6219 @@ +/* + * Copyright 2015-2017 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "imxdpuv1_private.h" +#include "imxdpuv1_registers.h" +#include "imxdpuv1_events.h" + +#include "imxdpuv1_be.h" + +#define ptr_to_uint32(__ptr__) ((uint32_t)((uint64_t)(__ptr__))) + +/* Private data*/ +static struct imxdpuv1_soc imxdpuv1_array[IMXDPUV1_MAX_NUM]; + +typedef struct { + uint8_t len; + uint8_t buffers; +} imxdpuv1_burst_entry_t; + +static const imxdpuv1_burst_entry_t burst_param[] = { + { 0, 0 }, /* IMXDPUV1_SCAN_DIR_UNKNOWN */ + { 8, 32 }, /* IMXDPUV1_SCAN_DIR_LEFT_RIGHT_DOWN */ + { 16, 16 }, /* IMXDPUV1_SCAN_DIR_HORIZONTAL */ + { 8, 32 }, /* IMXDPUV1_SCAN_DIR_VERTICAL possibly 8/32 here */ + { 8, 32 }, /* IMXDPUV1_SCAN_DIR_FREE */ +}; + +typedef struct { + uint32_t extdst; + uint32_t sub; +} trigger_entry_t; + +static const trigger_entry_t trigger_list[IMXDPUV1_SHDLD_IDX_MAX] = { + /* IMXDPUV1_SHDLD_* extdst, sub */ + /* _DISP0 */{ 1, 0 }, + /* _DISP1 */{ 1, 0 }, + /* _CONST0 */{ IMXDPUV1_SHDLD_CONSTFRAME0, 0 }, + /* _CONST1 */{ IMXDPUV1_SHDLD_CONSTFRAME1, 0 }, + /* _CHAN_00 */{ IMXDPUV1_SHDLD_FETCHDECODE2, 0 }, + /* _CHAN_01 */{ IMXDPUV1_SHDLD_FETCHDECODE0, 0 }, + /* _CHAN_02 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_1 }, + /* _CHAN_03 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_2 }, + /* _CHAN_04 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_3 }, + /* _CHAN_05 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_4 }, + /* _CHAN_06 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_5 }, + /* _CHAN_07 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_6 }, + /* _CHAN_08 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_7 }, + /* _CHAN_09 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_8 }, + /* _CHAN_10 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_1 << 16 }, + /* _CHAN_11 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_2 << 16 }, + /* _CHAN_12 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_3 << 16 }, + /* _CHAN_13 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_4 << 16 }, + /* _CHAN_14 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_5 << 16 }, + /* _CHAN_15 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_6 << 16 }, + /* _CHAN_16 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_7 << 16 }, + /* _CHAN_17 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_8 << 16 }, + /* _CHAN_18 */{ IMXDPUV1_SHDLD_FETCHDECODE3, 0 }, + /* _CHAN_19 */{ IMXDPUV1_SHDLD_FETCHDECODE1, 0 }, + /* _CHAN_20 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_1 << 8 }, + /* _CHAN_21 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_2 << 8 }, + /* _CHAN_22 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_3 << 8 }, + /* _CHAN_23 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_4 << 8 }, + /* _CHAN_24 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_5 << 8 }, + /* _CHAN_25 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_6 << 8 }, + /* _CHAN_26 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_7 << 8 }, + /* _CHAN_27 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_8 << 8 }, + /* _CHAN_28 */{ IMXDPUV1_SHDLD_FETCHECO0, 0 }, + /* _CHAN_29 */{ IMXDPUV1_SHDLD_FETCHECO1, 0 }, + /* _CHAN_30 */{ IMXDPUV1_SHDLD_FETCHECO2, 0 } +}; + +#ifdef ENABLE_IMXDPUV1_TRACE_REG +uint32_t _imxdpuv1_read(struct imxdpuv1_soc *imxdpu, uint32_t offset, char *file, + int line) +{ + uint32_t val = 0; + val = __raw_readl(imxdpu->base + offset); + IMXDPUV1_TRACE_REG("%s:%d R reg 0x%08x --> val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)val); + return val; +} + +void _imxdpuv1_write(struct imxdpuv1_soc *imxdpu, uint32_t offset, uint32_t value, + char *file, int line) +{ + __raw_writel(value, imxdpu->base + offset); + IMXDPUV1_TRACE_REG("%s:%d W reg 0x%08x <-- val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)value); +} + +#endif + +void _imxdpuv1_write_block(struct imxdpuv1_soc *imxdpu, uint32_t offset, + void *values, uint32_t cnt, char *file, int line) +{ + int i; + uint32_t *dest = (uint32_t *)(imxdpu->base + offset); + uint32_t *src = (uint32_t *)values; + IMXDPUV1_TRACE_REG("%s:%d W reg 0x%08x <-- cnt 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)cnt); + for (i = 0; i < cnt; i++) { + dest[i] = src[i]; + IMXDPUV1_TRACE_REG("%s:%d WB reg 0x%08x <-- val 0x%08x\n", file, line, + (uint32_t) ((uint64_t)(&dest[i])), (uint32_t)(src[i])); + + } +} + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_READ +uint32_t _imxdpuv1_read_irq(struct imxdpuv1_soc *imxdpu, uint32_t offset, + char *file, int line) +{ + uint32_t val = 0; + val = __raw_readl(imxdpu->base + offset); + IMXDPUV1_TRACE_IRQ("%s:%d IRQ R reg 0x%08x --> val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)val); + return val; +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_WRITE +void _imxdpuv1_write_irq(struct imxdpuv1_soc *imxdpu, uint32_t offset, + uint32_t value, char *file, int line) +{ + __raw_writel(value, imxdpu->base + offset); + IMXDPUV1_TRACE_IRQ("%s:%d IRQ W reg 0x%08x <-- val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)value); +} +#endif + +/* static prototypes */ +int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan); +static int imxdpuv1_disp_start_shadow_loads(int8_t imxdpuv1_id, int8_t disp); +void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id); +static bool imxdpuv1_is_yuv(uint32_t fmt); +bool imxdpuv1_is_rgb(uint32_t fmt); + +/*! + * Returns IMXDPUV1_TRUE for a valid channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + + if ((chan_idx >= IMXDPUV1_CHAN_IDX_IN_FIRST) && + (chan_idx < IMXDPUV1_CHAN_IDX_IN_MAX)) + return IMXDPUV1_TRUE; + if ((chan_idx >= IMXDPUV1_CHAN_IDX_OUT_FIRST) && + (chan_idx < IMXDPUV1_CHAN_IDX_OUT_MAX)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid store channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_store_chan(imxdpuv1_chan_t chan) +{ +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_STORE4) || (blk_id == IMXDPUV1_ID_STORE4)) + return IMXDPUV1_TRUE; +#endif + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_eco_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHECO0) || + (blk_id == IMXDPUV1_ID_FETCHECO1) || + (blk_id == IMXDPUV1_ID_FETCHECO2)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch decode channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_decode_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHDECODE0) || + (blk_id == IMXDPUV1_ID_FETCHDECODE1) +#ifdef IMXDPUV1_VERSION_0 + || (blk_id == IMXDPUV1_ID_FETCHDECODE2) + || (blk_id == IMXDPUV1_ID_FETCHDECODE3) +#endif + ) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE if a fetch channel has an eco fetch + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int has_fetch_eco_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHDECODE0) || + (blk_id == IMXDPUV1_ID_FETCHDECODE1) || + (blk_id == IMXDPUV1_ID_FETCHWARP2)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch warp channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_warp_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHWARP2)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch layer channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_layer_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHLAYER0) +#ifdef IMXDPUV1_VERSION_0 + || (blk_id == IMXDPUV1_ID_FETCHLAYER1) +#endif + ) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid layer sub1 channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_layer_sub_chan1(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHLAYER0) || +#ifdef IMXDPUV1_VERSION_0 + (blk_id == IMXDPUV1_ID_FETCHLAYER1) || +#endif + (blk_id == IMXDPUV1_ID_FETCHWARP2)) + if (get_channel_sub(chan) == IMXDPUV1_SUB_1) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns subindex of a channel + * + * @param channel + * + * @return returns the subindex of a channel + */ +static int imxdpuv1_get_channel_subindex(imxdpuv1_chan_t chan) +{ + switch (get_channel_sub(chan)) { + case IMXDPUV1_SUB_2: + return 1; + case IMXDPUV1_SUB_3: + return 2; + case IMXDPUV1_SUB_4: + return 3; + case IMXDPUV1_SUB_5: + return 4; + case IMXDPUV1_SUB_6: + return 5; + case IMXDPUV1_SUB_7: + return 6; + case IMXDPUV1_SUB_8: + return 7; + case IMXDPUV1_SUB_1: + case IMXDPUV1_SUBWINDOW_NONE: + default: + return 0; + } +} + +/*! + * Returns returns the eco channel for a channel index + * + * @param chan + * + * @return returns number of bits per pixel or zero + * if the format is not matched. + */ +imxdpuv1_chan_t imxdpuv1_get_eco(imxdpuv1_chan_t chan) +{ + switch (get_eco_idx(chan)) { + case get_channel_idx(IMXDPUV1_CHAN_28): + return IMXDPUV1_CHAN_28; + case get_channel_idx(IMXDPUV1_CHAN_29): + return IMXDPUV1_CHAN_29; + case get_channel_idx(IMXDPUV1_CHAN_30): + return IMXDPUV1_CHAN_30; + default: + return 0; + } +} +/*! + * Returns the start address offset for a given block ID + * + * @param block id + * + * @return This function returns the address offset if the block id + * matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID + * is returned. + */ +uint32_t id2blockoffset(imxdpuv1_id_t block_id) +{ + switch (block_id) { + /*case IMXDPUV1_ID_NONE: return IMXDPUV1_NONE_LOCKUNLOCK; */ + case IMXDPUV1_ID_FETCHDECODE9: + return IMXDPUV1_FETCHDECODE9_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FETCHPERSP9: + return IMXDPUV1_FETCHPERSP9_LOCKUNLOCK; +#else + case IMXDPUV1_ID_FETCHWARP9: + return IMXDPUV1_FETCHWARP9_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_FETCHECO9: + return IMXDPUV1_FETCHECO9_LOCKUNLOCK; + case IMXDPUV1_ID_ROP9: + return IMXDPUV1_ROP9_LOCKUNLOCK; + case IMXDPUV1_ID_CLUT9: + return IMXDPUV1_CLUT9_LOCKUNLOCK; + case IMXDPUV1_ID_MATRIX9: + return IMXDPUV1_MATRIX9_LOCKUNLOCK; + case IMXDPUV1_ID_HSCALER9: + return IMXDPUV1_HSCALER9_LOCKUNLOCK; + case IMXDPUV1_ID_VSCALER9: + return IMXDPUV1_VSCALER9_LOCKUNLOCK; + case IMXDPUV1_ID_FILTER9: + return IMXDPUV1_FILTER9_LOCKUNLOCK; + case IMXDPUV1_ID_BLITBLEND9: + return IMXDPUV1_BLITBLEND9_LOCKUNLOCK; + case IMXDPUV1_ID_STORE9: + return IMXDPUV1_STORE9_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME0: + return IMXDPUV1_CONSTFRAME0_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST0: + return IMXDPUV1_EXTDST0_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME4: + return IMXDPUV1_CONSTFRAME4_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST4: + return IMXDPUV1_EXTDST4_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME1: + return IMXDPUV1_CONSTFRAME1_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST1: + return IMXDPUV1_EXTDST1_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME5: + return IMXDPUV1_CONSTFRAME5_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST5: + return IMXDPUV1_EXTDST5_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_EXTSRC4: + return IMXDPUV1_EXTSRC4_LOCKUNLOCK; + case IMXDPUV1_ID_STORE4: + return IMXDPUV1_STORE4_LOCKUNLOCK; + case IMXDPUV1_ID_EXTSRC5: + return IMXDPUV1_EXTSRC5_LOCKUNLOCK; + case IMXDPUV1_ID_STORE5: + return IMXDPUV1_STORE5_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE2: + return IMXDPUV1_FETCHDECODE2_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE3: + return IMXDPUV1_FETCHDECODE3_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_FETCHWARP2: + return IMXDPUV1_FETCHWARP2_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHECO2: + return IMXDPUV1_FETCHECO2_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE0: + return IMXDPUV1_FETCHDECODE0_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHECO0: + return IMXDPUV1_FETCHECO0_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE1: + return IMXDPUV1_FETCHDECODE1_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHECO1: + return IMXDPUV1_FETCHECO1_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHLAYER0: + return IMXDPUV1_FETCHLAYER0_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FETCHLAYER1: + return IMXDPUV1_FETCHLAYER1_LOCKUNLOCK; + case IMXDPUV1_ID_GAMMACOR4: + return IMXDPUV1_GAMMACOR4_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_MATRIX4: + return IMXDPUV1_MATRIX4_LOCKUNLOCK; + case IMXDPUV1_ID_HSCALER4: + return IMXDPUV1_HSCALER4_LOCKUNLOCK; + case IMXDPUV1_ID_VSCALER4: + return IMXDPUV1_VSCALER4_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM4: + return IMXDPUV1_HISTOGRAM4_CONTROL; + case IMXDPUV1_ID_GAMMACOR5: + return IMXDPUV1_GAMMACOR5_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_MATRIX5: + return IMXDPUV1_MATRIX5_LOCKUNLOCK; + case IMXDPUV1_ID_HSCALER5: + return IMXDPUV1_HSCALER5_LOCKUNLOCK; + case IMXDPUV1_ID_VSCALER5: + return IMXDPUV1_VSCALER5_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM5: + return IMXDPUV1_HISTOGRAM5_CONTROL; +#endif + case IMXDPUV1_ID_LAYERBLEND0: + return IMXDPUV1_LAYERBLEND0_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND1: + return IMXDPUV1_LAYERBLEND1_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND2: + return IMXDPUV1_LAYERBLEND2_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND3: + return IMXDPUV1_LAYERBLEND3_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_LAYERBLEND4: + return IMXDPUV1_LAYERBLEND4_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND5: + return IMXDPUV1_LAYERBLEND5_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND6: + return IMXDPUV1_LAYERBLEND6_LOCKUNLOCK; + case IMXDPUV1_ID_EXTSRC0: + return IMXDPUV1_EXTSRC0_LOCKUNLOCK; + case IMXDPUV1_ID_EXTSRC1: + return IMXDPUV1_EXTSRC1_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_DISENGCFG: + return IMXDPUV1_DISENGCFG_LOCKUNLOCK0; + case IMXDPUV1_ID_FRAMEGEN0: + return IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + case IMXDPUV1_ID_MATRIX0: + return IMXDPUV1_MATRIX0_LOCKUNLOCK; + case IMXDPUV1_ID_GAMMACOR0: + return IMXDPUV1_GAMMACOR0_LOCKUNLOCK; + case IMXDPUV1_ID_DITHER0: + return IMXDPUV1_DITHER0_LOCKUNLOCK; + case IMXDPUV1_ID_TCON0: + return IMXDPUV1_TCON0_LOCKUNLOCK; + case IMXDPUV1_ID_SIG0: + return IMXDPUV1_SIG0_LOCKUNLOCK; + case IMXDPUV1_ID_FRAMEGEN1: + return IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + case IMXDPUV1_ID_MATRIX1: + return IMXDPUV1_MATRIX1_LOCKUNLOCK; + case IMXDPUV1_ID_GAMMACOR1: + return IMXDPUV1_GAMMACOR1_LOCKUNLOCK; + case IMXDPUV1_ID_DITHER1: + return IMXDPUV1_DITHER1_LOCKUNLOCK; + case IMXDPUV1_ID_TCON1: + return IMXDPUV1_TCON1_LOCKUNLOCK; + case IMXDPUV1_ID_SIG1: + return IMXDPUV1_SIG1_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FRAMECAP4: + return IMXDPUV1_FRAMECAP4_LOCKUNLOCK; + case IMXDPUV1_ID_FRAMECAP5: + return IMXDPUV1_FRAMECAP5_LOCKUNLOCK; +#endif + default: + return IMXDPUV1_OFFSET_INVALID; + } +} + +/*! + * Returns the start address offset for the dynamic configuraiton for + * a given block ID + * + * @param block id + * + * @return This function returns the address offset if the block id + * matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID + * is returned. + */ +uint32_t id2dynamicoffset(imxdpuv1_id_t block_id) +{ + switch (block_id) { + case IMXDPUV1_ID_FETCHDECODE9: + return IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC; + +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FETCHPERSP9: + return IMXDPUV1_PIXENGCFG_FETCHPERSP9_DYNAMIC; +#else + case IMXDPUV1_ID_FETCHWARP9: + return IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC; +#endif + case IMXDPUV1_ID_ROP9: + return IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC; + case IMXDPUV1_ID_CLUT9: + return IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC; + case IMXDPUV1_ID_MATRIX9: + return IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC; + case IMXDPUV1_ID_HSCALER9: + return IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC; + case IMXDPUV1_ID_VSCALER9: + return IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC; + case IMXDPUV1_ID_FILTER9: + return IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC; + case IMXDPUV1_ID_BLITBLEND9: + return IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC; + case IMXDPUV1_ID_STORE9: + return IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC; + case IMXDPUV1_ID_EXTDST0: + return IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC; + case IMXDPUV1_ID_EXTDST4: + return IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC; + case IMXDPUV1_ID_EXTDST1: + return IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_EXTDST5: + return IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC; + case IMXDPUV1_ID_STORE4: + return IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC; + case IMXDPUV1_ID_STORE5: + return IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE2: + return IMXDPUV1_PIXENGCFG_FETCHDECODE2_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE3: + return IMXDPUV1_PIXENGCFG_FETCHDECODE3_DYNAMIC; +#endif + case IMXDPUV1_ID_FETCHWARP2: + return IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE0: + return IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE1: + return IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_GAMMACOR4: + return IMXDPUV1_PIXENGCFG_GAMMACOR4_DYNAMIC; +#endif + case IMXDPUV1_ID_MATRIX4: + return IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC; + case IMXDPUV1_ID_HSCALER4: + return IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC; + case IMXDPUV1_ID_VSCALER4: + return IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM4: + return IMXDPUV1_PIXENGCFG_HISTOGRAM4_DYNAMIC; + case IMXDPUV1_ID_GAMMACOR5: + return IMXDPUV1_PIXENGCFG_GAMMACOR5_DYNAMIC; +#endif + case IMXDPUV1_ID_MATRIX5: + return IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC; + case IMXDPUV1_ID_HSCALER5: + return IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC; + case IMXDPUV1_ID_VSCALER5: + return IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM5: + return IMXDPUV1_PIXENGCFG_HISTOGRAM5_DYNAMIC; +#endif + case IMXDPUV1_ID_LAYERBLEND0: + return IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND1: + return IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND2: + return IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND3: + return IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_LAYERBLEND4: + return IMXDPUV1_PIXENGCFG_LAYERBLEND4_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND5: + return IMXDPUV1_PIXENGCFG_LAYERBLEND5_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND6: + return IMXDPUV1_PIXENGCFG_LAYERBLEND6_DYNAMIC; +#endif + default: + return IMXDPUV1_OFFSET_INVALID; + } +} + +/*! + * Returns the start address offset for a given shadow index + * + * @param block id + * + * @return This function returns the address offset if the shadow + * index matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID + * is returned. + */ +imxdpuv1_chan_t shadowindex2channel(imxdpuv1_shadow_load_index_t shadow_index) +{ + switch (shadow_index) { + case IMXDPUV1_SHDLD_IDX_CHAN_00: + return IMXDPUV1_CHAN_00; + case IMXDPUV1_SHDLD_IDX_CHAN_01: + return IMXDPUV1_CHAN_01; + case IMXDPUV1_SHDLD_IDX_CHAN_02: + return IMXDPUV1_CHAN_02; + case IMXDPUV1_SHDLD_IDX_CHAN_03: + return IMXDPUV1_CHAN_03; + case IMXDPUV1_SHDLD_IDX_CHAN_04: + return IMXDPUV1_CHAN_04; + case IMXDPUV1_SHDLD_IDX_CHAN_05: + return IMXDPUV1_CHAN_05; + case IMXDPUV1_SHDLD_IDX_CHAN_06: + return IMXDPUV1_CHAN_06; + case IMXDPUV1_SHDLD_IDX_CHAN_07: + return IMXDPUV1_CHAN_07; + case IMXDPUV1_SHDLD_IDX_CHAN_08: + return IMXDPUV1_CHAN_08; + case IMXDPUV1_SHDLD_IDX_CHAN_09: + return IMXDPUV1_CHAN_09; + case IMXDPUV1_SHDLD_IDX_CHAN_10: + return IMXDPUV1_CHAN_10; + case IMXDPUV1_SHDLD_IDX_CHAN_11: + return IMXDPUV1_CHAN_11; + case IMXDPUV1_SHDLD_IDX_CHAN_12: + return IMXDPUV1_CHAN_12; + case IMXDPUV1_SHDLD_IDX_CHAN_13: + return IMXDPUV1_CHAN_13; + case IMXDPUV1_SHDLD_IDX_CHAN_14: + return IMXDPUV1_CHAN_14; + case IMXDPUV1_SHDLD_IDX_CHAN_15: + return IMXDPUV1_CHAN_15; + case IMXDPUV1_SHDLD_IDX_CHAN_16: + return IMXDPUV1_CHAN_16; + case IMXDPUV1_SHDLD_IDX_CHAN_17: + return IMXDPUV1_CHAN_17; + case IMXDPUV1_SHDLD_IDX_CHAN_18: + return IMXDPUV1_CHAN_18; + case IMXDPUV1_SHDLD_IDX_CHAN_19: + return IMXDPUV1_CHAN_19; + case IMXDPUV1_SHDLD_IDX_CHAN_20: + return IMXDPUV1_CHAN_20; + case IMXDPUV1_SHDLD_IDX_CHAN_21: + return IMXDPUV1_CHAN_21; + case IMXDPUV1_SHDLD_IDX_CHAN_22: + return IMXDPUV1_CHAN_22; + case IMXDPUV1_SHDLD_IDX_CHAN_23: + return IMXDPUV1_CHAN_23; + case IMXDPUV1_SHDLD_IDX_CHAN_24: + return IMXDPUV1_CHAN_24; + case IMXDPUV1_SHDLD_IDX_CHAN_25: + return IMXDPUV1_CHAN_25; + case IMXDPUV1_SHDLD_IDX_CHAN_26: + return IMXDPUV1_CHAN_26; + case IMXDPUV1_SHDLD_IDX_CHAN_27: + return IMXDPUV1_CHAN_27; + case IMXDPUV1_SHDLD_IDX_CHAN_28: + return IMXDPUV1_CHAN_28; + case IMXDPUV1_SHDLD_IDX_CHAN_29: + return IMXDPUV1_CHAN_29; + case IMXDPUV1_SHDLD_IDX_CHAN_30: + return IMXDPUV1_CHAN_30; + default: + return IMXDPUV1_CHANNEL_INVALID; + } +} + + +/*! + * This function returns the pointer to the imxdpu structutre + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns the pointer to the imxdpu structutre + * return a NULL pointer for a failure. + */ +struct imxdpuv1_soc *imxdpuv1_get_soc(int8_t imxdpuv1_id) +{ + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return NULL; + } + return &(imxdpuv1_array[imxdpuv1_id]); +} + +/*! + * This function enables the interrupt for the specified interrupt line. + * The interrupt lines are defined in imxdpuv1_events.h. + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to enable interrupt for. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_enable_irq(int8_t imxdpuv1_id, uint32_t irq) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + if (irq == 0) + panic("Trying to enable irq 0!"); +#endif + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_clear_irq(imxdpuv1_id, irq); + if (irq < IMXDPUV1_INTERRUPT_MAX) { + if (irq < 32) { + imxdpu->enabled_int[0] |= INTSTAT0_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, + imxdpu->enabled_int[0]); + } else if (irq < 64) { + imxdpu->enabled_int[1] |= INTSTAT1_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, + imxdpu->enabled_int[1]); +#ifdef IMXDPUV1_VERSION_0 + } else { + imxdpu->enabled_int[2] |= INTSTAT2_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, + imxdpu->enabled_int[2]); +#endif + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function disables the interrupt for the specified interrupt line.g + * The interrupt lines are defined in imxdpuv1_events.h. + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to disable interrupt for. + * + */ +int imxdpuv1_disable_irq(int8_t imxdpuv1_id, uint32_t irq) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (irq < IMXDPUV1_INTERRUPT_MAX) { + if (irq < 32) { + imxdpu->enabled_int[0] &= ~INTSTAT0_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, + imxdpu->enabled_int[0]); + } else if (irq < 64) { + imxdpu->enabled_int[1] &= ~INTSTAT1_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, + imxdpu->enabled_int[1]); +#ifdef IMXDPUV1_VERSION_0 + } else { + imxdpu->enabled_int[2] &= ~INTSTAT2_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, + imxdpu->enabled_int[2]); +#endif + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function clears all interrupts. + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_clear_all_irqs(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_MASK); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2_USERINTERRUPTCLEAR2_MASK); +#endif +#if 1 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR0, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_MASK); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR1, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR2, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR2_INTERRUPTCLEAR2_MASK); +#endif +#endif + return ret; +} + +/*! + * This function disables all interrupts. + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_disable_all_irqs(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, 0); + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, 0); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, 0); +#endif + +#if 1 + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE0, 0); + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE1, 0); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE2, 0); +#endif +#endif + + imxdpu->enabled_int[0] = 0; + imxdpu->enabled_int[1] = 0; +#ifdef IMXDPUV1_VERSION_0 + imxdpu->enabled_int[2] = 0; +#endif + return ret; +} + +/*! + * This function clears the interrupt for the specified interrupt line. + * The interrupt lines are defined in ipu_irq_line enum. + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to clear interrupt for. + * + */ +int imxdpuv1_clear_irq(int8_t imxdpuv1_id, uint32_t irq) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (irq < IMXDPUV1_INTERRUPT_MAX) { + if (irq < 32) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0, + 1U << irq); + } + if (irq < 64) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1, + 1U << (irq - 32)); +#ifdef IMXDPUV1_VERSION_0 + } else { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2, + 1U << (irq - 64)); +#endif + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function initializes the imxdpu interrupts + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_init_irqs(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_disable_all_irqs(imxdpuv1_id); + imxdpuv1_clear_all_irqs(imxdpuv1_id); + + /* Set all irq to user mode */ + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2_USERINTERRUPTMASK2_MASK); +#endif + /* enable needed interupts */ + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST0_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST1_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ); + +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_SEQCOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_SEQCOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_FRAMECOMPLETE_IRQ); +#endif + /* enable the frame interrupts as IMXDPUV1_IRQF_ONESHOT */ + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_FRAMEGEN0_INT0_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_FRAMEGEN1_INT0_IRQ); + + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_COMCTRL_SW0_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_COMCTRL_SW1_IRQ); + + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ); + + IMXDPUV1_TRACE("%s() enabled_int[0] 0x%08x\n", __func__, + imxdpu->enabled_int[0]); + IMXDPUV1_TRACE("%s() enabled_int[1] 0x%08x\n", __func__, + imxdpu->enabled_int[1]); +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_TRACE("%s() enabled_int[2] 0x%08x\n", __func__, + imxdpu->enabled_int[2]); +#endif + return ret; +} + +/*! + * This function checks pending shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_check_shadow_loads(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + uint32_t addr_extdst = IMXDPUV1_OFFSET_INVALID; /* address for extdst */ + uint32_t extdst = 0; + uint32_t extdst_stat = 0; + uint32_t fgen = 1; + uint32_t fgen_stat = 0; + uint32_t sub = 0; + uint32_t sub_stat = 0; + uint32_t stat; + + int32_t i; + + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + stat = imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0); + if (disp == 0) { + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST; + if (stat & IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ) { + fgen = 0; + } + } else if (disp == 1) { + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST; + if (stat & IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ) { + fgen = 0; + } + } else { + return -EINVAL; + } + + sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE)) & 0xff; +#ifdef IMXDPUV1_VERSION_0 + sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE) << 8) & 0xff00; +#endif + sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE) << 16) & 0xff0000; + extdst = imxdpuv1_read(imxdpu, addr_extdst); + + /* this loop may need to be optimized */ + for (i = 0; i < IMXDPUV1_SHDLD_IDX_CHAN_00; i++) { + if (imxdpu->shadow_load_state[disp][i].state.complete) { + if (imxdpu->shadow_load_state[disp][i].state.trys > 0) { + IMXDPUV1_TRACE_IRQ + ("shadow index complete after retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } else { + IMXDPUV1_TRACE_IRQ("shadow index complete: index %d\n", i); + } + imxdpu->shadow_load_state[disp][i].word = 0; + } else if (imxdpu->shadow_load_state[disp][i].state.processing) { + if (i > IMXDPUV1_SHDLD_IDX_CONST1) { + if (!(extdst & trigger_list[i].extdst) && !fgen) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + extdst_stat |= trigger_list[i].extdst; + fgen_stat |= 1 << i; + } + } else if (!(extdst & trigger_list[i].extdst)) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + imxdpu->shadow_load_state[disp][i].state.trys++; + extdst |= trigger_list[i].extdst; + IMXDPUV1_TRACE_IRQ + ("shadow index retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } + } + } + + + for (i = IMXDPUV1_SHDLD_IDX_CHAN_00; i < IMXDPUV1_SHDLD_IDX_MAX; i++) { + if (imxdpu->shadow_load_state[disp][i].state.complete) { + + if (imxdpu->shadow_load_state[disp][i].state.trys > 0) { + IMXDPUV1_TRACE_IRQ + ("shadow index complete after retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } else { + IMXDPUV1_TRACE_IRQ("shadow index complete: index %d\n", i); + } + imxdpu->shadow_load_state[disp][i].word = 0; + } else if (imxdpu->shadow_load_state[disp][i].state.processing) { + /* fetch layer and fetchwarp */ + if ((trigger_list[i].extdst != 0) && + (trigger_list[i].sub != 0)) { + if (!(extdst & trigger_list[i].extdst) && + !(sub & trigger_list[i].sub)) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + extdst_stat |= trigger_list[i].extdst; + sub_stat |= trigger_list[i].sub; + } + } else if (!(extdst & trigger_list[i].extdst)) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + imxdpu->shadow_load_state[disp][i].state.trys++; + extdst_stat |= trigger_list[i].extdst; + IMXDPUV1_TRACE_IRQ + ("shadow index retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } + } + } + + if ((extdst_stat == 0) && (sub_stat == 0) && (fgen_stat == 0)) { + /* clear interrupt */ + IMXDPUV1_TRACE_IRQ("shadow requests are complete.\n"); + } else { + IMXDPUV1_TRACE_IRQ + ("shadow requests are not complete: extdst 0x%08x, sub 0x%08x, fgen 0x%08x\n", + extdst, sub, fgen); + IMXDPUV1_TRACE_IRQ + ("shadow requests are not complete: extdst_stat 0x%08x, sub_stat 0x%08x, fgen_stat 0x%08x\n", + extdst_stat, sub_stat, fgen_stat); + } + + return ret; +} + +/*! + * This function starts pending shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +static int imxdpuv1_disp_start_shadow_loads(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + uint32_t addr_extdst; /* address for extdst */ + uint32_t addr_fgen; /* address for frame generator */ + uint32_t extdst = 0; + uint32_t fgen = 0; + uint32_t sub = 0; + int32_t i; + + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + addr_fgen = IMXDPUV1_FRAMEGEN0_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST; + + } else if (disp == 1) { + addr_fgen = IMXDPUV1_FRAMEGEN1_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST; + } else { + return -EINVAL; + } + + /* this loop may need to be optimized */ + for (i = 0; i < IMXDPUV1_SHDLD_IDX_CHAN_00; i++) { + if (imxdpu->shadow_load_state[disp][i].state.request && + (imxdpu->shadow_load_state[disp][i].state.processing == 0)) { + imxdpu->shadow_load_state[disp][i].state.processing = 1; + extdst |= trigger_list[i].extdst; + /* only trigger frame generator for const frames*/ + if (i >= IMXDPUV1_SHDLD_IDX_CONST0) { + fgen |= 1; + } + } + } + for (i = IMXDPUV1_SHDLD_IDX_CHAN_00; i < IMXDPUV1_SHDLD_IDX_MAX; i++) { + if (imxdpu->shadow_load_state[disp][i].state.request && + (imxdpu->shadow_load_state[disp][i].state.processing == 0)) { + imxdpu->shadow_load_state[disp][i].state.processing = 1; + /*todo: need a completion handler */ + extdst |= trigger_list[i].extdst; + sub |= trigger_list[i].sub; + } + } + + if (sub) { + IMXDPUV1_TRACE_IRQ("Fetch layer shadow request 0x%08x\n", sub); + if (sub & 0xff) { /* FETCHLAYER0 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE, + sub & 0xff); + } +#ifdef IMXDPUV1_VERSION_0 + if (sub & 0xff00) { /* FETCHLAYER1 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE, + (sub >> 8) & 0xff); + } +#endif + if (sub & 0xff0000) { /* FETCHWARP2 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE, + (sub >> 16) & 0xff); + } + } + + if (extdst) { + IMXDPUV1_TRACE_IRQ("Extdst shadow request 0x%08x\n", extdst); + imxdpuv1_write(imxdpu, addr_extdst, extdst); + } + + if (fgen) { + IMXDPUV1_TRACE_IRQ("Fgen shadow request 0x%08x\n", fgen); + imxdpuv1_write(imxdpu, addr_fgen, fgen); + } + + return ret; +} + +/*! + * This function handles the VYNC interrupt for a display + * + * @param imxdpu imxdpu instance + * @param disp display index + * + */ +static void imxdpuv1_disp_vsync_handler(int8_t imxdpuv1_id, int8_t disp) +{ + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + if (!((disp == 0) || (disp == 1))) + return; + + /* send notifications + shadow load finished + */ + + imxdpuv1_disp_start_shadow_loads(imxdpuv1_id, disp); + imxdpuv1_disp_update_fgen_status(imxdpuv1_id, disp); + + return; + +} + +/*! + * This function calls a register handler for an interrupt + * + * @param imxdpu imxdpu instance + * @param irq interrupt line + * + */ +static void imxdpuv1_handle_registered_irq(int8_t imxdpuv1_id, int8_t irq) +{ + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if ((irq < 0) || (irq >= IMXDPUV1_INTERRUPT_MAX)) + return; + + if (imxdpu->irq_list[irq].handler == NULL) + return; + + imxdpu->irq_list[irq].handler(irq, imxdpu->irq_list[irq].data); + + if ((imxdpu->irq_list[irq].flags & IMXDPUV1_IRQF_ONESHOT) != 0) { + imxdpuv1_disable_irq(imxdpuv1_id, irq); + imxdpuv1_clear_irq(imxdpuv1_id, irq); + } + return; + +} + +/* todo: this irq handler assumes all irq are ORed together. + The irqs may be grouped so this function can be + optimized if that is the case*/ +/*! + * This function processes all IRQs for the IMXDPU + * + * @param data pointer to the imxdpu structure + * + */ +int imxdpuv1_handle_irq(int32_t imxdpuv1_id) +{ + uint32_t int_stat[3]; + uint32_t int_temp[3]; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + IMXDPUV1_TRACE_IRQ("%s(): invalid imxdpuv1_id\n", __func__); +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + panic("wrong imxdpuv1_id"); +#endif + return IMXDPUV1_FALSE; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpu->irq_count++; + +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + { + uint32_t int_enable0; + int_enable0 = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0); + if (int_enable0 & 1) { + panic("IRQ0 enabled\n"); + } + if (imxdpu->enabled_int[0] & 1) { + panic("IRQ0 in enabled_int is set\n"); + } + } +#endif + /* Get and clear interrupt status */ + int_temp[0] = + imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0); + int_stat[0] = imxdpu->enabled_int[0] & int_temp[0]; + int_temp[1] = + imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1); + int_stat[1] = imxdpu->enabled_int[1] & int_temp[1]; +#ifdef IMXDPUV1_VERSION_0 +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + /* Enable this (IMXDPUV1_ENABLE_INTSTAT2) if intstat2 interrupts + are needed */ + int_temp[2] = + imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS2); + int_stat[2] = imxdpu->enabled_int[2] & int_temp[2]; +#endif +#endif + /* No interrupts are pending */ + if ((int_temp[0] == 0) && (int_temp[1] == 0) +#ifdef IMXDPUV1_VERSION_0 +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + && (int_temp[2] == 0) +#endif +#endif + ) { + } + + /* No enabled interrupts are pending */ + if ((int_stat[0] == 0) && (int_stat[1] == 0) +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + && (int_stat[2] == 0) +#endif + ) { + IMXDPUV1_TRACE_IRQ + ("Error: No enabled interrupts, 0x%08x 0x%08x\n", + int_temp[0] & ~imxdpu->enabled_int[0], + int_temp[1] & ~imxdpu->enabled_int[1]); +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + panic("no enabled IMXDPU interrupts"); +#endif + + return IMXDPUV1_FALSE; + } + + /* Clear the enabled interrupts */ + if (int_stat[0]) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0, + int_stat[0]); + } + if (int_stat[1]) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1, + int_stat[1]); + } +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + if (int_stat[2]) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2, + int_stat[2]); + } +#endif + +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + if (int_stat[1] != 0) { + /* add int_stat[2] if needed */ + } +#endif +#ifdef IMXDPUV1_VERSION_0 + /* now handle the interrupts that are pending */ + if (int_stat[0] != 0) { + if (int_stat[0] & 0xff) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SHDLOAD_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SEQCOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SEQCOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0); + + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ); + } + } + if (int_stat[0] & 0xff00) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST1_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT( + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE4_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ_CAPTURE("IMXDPUV1_STORE4_SHDLOAD_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE4_SHDLOAD_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ_CAPTURE( + "IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE4_SEQCOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ_CAPTURE( + "IMXDPUV1_STORE4_SEQCOMPLETE_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE4_SEQCOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_HISTOGRAM4_VALID_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_HISTOGRAM4_VALID_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_HISTOGRAM4_VALID_IRQ); + } + } + if (int_stat[0] & 0xff000000) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_HISTOGRAM5_VALID_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_HISTOGRAM5_VALID_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_HISTOGRAM5_VALID_IRQ); + } + if (int_stat[1] & + INTSTAT0_BIT(IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ)) { + IMXDPUV1_PRINT + ("IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ irq\n"); + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN0_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 0); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN0_INT0_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT1_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN0_INT1_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN0_INT1_IRQ); + } + } + } + + if (int_stat[1] != 0) { + if (int_stat[1] & 0xff) { + + } + if (int_stat[1] & 0xff00) { + if (int_stat[1] & + INTSTAT1_BIT(IMXDPUV1_FRAMEGEN1_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN1_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN1_INT0_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + if (int_stat[0] & + INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW0_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW0_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW0_IRQ); + } + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW2_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW2_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW2_IRQ); + } + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW3_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW3_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW3_IRQ); + } + + } + } +#else + /* now handle the interrupts that are pending */ + if (int_stat[0] != 0) { + if (int_stat[0] & 0xff) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SHDLOAD_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SEQCOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SEQCOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0); + + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ); + } + } + if (int_stat[0] & 0xff00) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST1_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT( + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN0_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 0); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN0_INT0_IRQ); + } + + } + if (int_stat[0] & 0xff000000) { + if (int_stat[1] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN1_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN1_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN1_INT0_IRQ); + } + } + } + + if (int_stat[1] != 0) { + if (int_stat[1] & 0xff) { + if (int_stat[0] & + INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW0_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW0_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW0_IRQ); + } + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW2_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW2_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW2_IRQ); + } + } + if (int_stat[1] & 0xff00) { + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW3_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW3_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW3_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + /* Reserved for command sequencer debug */ + } + } +#endif + return IMXDPUV1_TRUE; +} + +/*! + * This function registers an interrupt handler function for the specified + * irq line. The interrupt lines are defined in imxdpuv1_events.h + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to get status for. + * + * @param handler Input parameter for address of the handler + * function. + * + * @param irq_flags Flags for interrupt mode. Currently not used. + * + * @param devname Input parameter for string name of driver + * registering the handler. + * + * @param data Input parameter for pointer of data to be + * passed to the handler. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_request_irq(int8_t imxdpuv1_id, + uint32_t irq, + int (*handler)(int, void *), + uint32_t irq_flags, const char *devname, void *data) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (imxdpu->irq_list[irq].handler != NULL) { + IMXDPUV1_TRACE("handler already installed on irq %d\n", irq); + ret = -EINVAL; + goto out; + } + + imxdpu->irq_list[irq].handler = handler; + imxdpu->irq_list[irq].flags = irq_flags; + imxdpu->irq_list[irq].data = data; + imxdpu->irq_list[irq].name = devname; + + /* Clear and enable the IRQ */ + imxdpuv1_clear_irq(imxdpuv1_id, irq); + /* Don't enable if a one shot */ + if ((imxdpu->irq_list[irq].flags & IMXDPUV1_IRQF_ONESHOT) == 0) + imxdpuv1_enable_irq(imxdpuv1_id, irq); +out: + return ret; +} + +/*! + * This function unregisters an interrupt handler for the specified interrupt + * line. The interrupt lines are defined in imxdpuv1_events.h + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to get status for. + * + * @param data Input parameter for pointer of data to be passed + * to the handler. This must match value passed to + * ipu_request_irq(). + * + */ +int imxdpuv1_free_irq(int8_t imxdpuv1_id, uint32_t irq, void *data) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_disable_irq(imxdpuv1_id, irq); + imxdpuv1_clear_irq(imxdpuv1_id, irq); + if (imxdpu->irq_list[irq].data == data) + memset(&imxdpu->irq_list[irq], 0, sizeof(imxdpu->irq_list[irq])); + + return ret; +} + +/*! + * This function un-initializes the imxdpu interrupts + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_uninit_interrupts(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpu->enabled_int[0] = 0; + imxdpu->enabled_int[1] = 0; +#ifdef IMXDPUV1_VERSION_0 + imxdpu->enabled_int[2] = 0; +#endif + imxdpuv1_clear_all_irqs(imxdpuv1_id); + + /* Set all interrupt to user mode */ + imxdpuv1_write(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK); + imxdpuv1_write(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2_USERINTERRUPTMASK2_MASK); +#endif + /* Set all interrupts to user mode. this will to change to + enable panic mode */ + imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, 0); + imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, 0); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, 0); +#endif + /* enable needed interupts */ + return ret; +} + +/*! + * This function initializes the imxdpu and the required data structures + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +/* todo: replace with probe function or call from probe + use device tree as needed */ +int imxdpuv1_init(int8_t imxdpuv1_id) +{ + int ret = 0; + int i; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* todo: add resource mapping for xrdc, layers, blit, display, ... */ + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + + /* Map the channels to display streams + todo: + make this mapping dynamic + add channel features + map capture channels + */ + for (i = IMXDPUV1_CHAN_IDX_IN_FIRST; i < IMXDPUV1_CHAN_IDX_MAX; i++) { + if (i <= IMXDPUV1_CHAN_IDX_17) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0; + else if (i < IMXDPUV1_CHAN_IDX_IN_MAX) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 1; + else if (i < IMXDPUV1_CHAN_IDX_OUT_FIRST) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0; + else if (i < IMXDPUV1_CHAN_IDX_OUT_MAX) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 1; + else + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0; + } + + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + imxdpu->irq_count = 0; + + if (imxdpuv1_id == 0) { + imxdpu->base = (void __iomem *)IMXDPUV1_REGS_BASE_PHY0; + IMXDPUV1_TRACE("%s(): virtual base address is 0x%p (0x%08x physical)\n", + __func__, imxdpu->base, IMXDPUV1_REGS_BASE_PHY0); + + } else if (imxdpuv1_id == 1) { + imxdpu->base = (void __iomem *)IMXDPUV1_REGS_BASE_PHY1; + IMXDPUV1_TRACE("%s(): virtual base address is 0x%p (0x%08x physical)\n", + __func__, imxdpu->base, IMXDPUV1_REGS_BASE_PHY1); + + } else { + return -ENOMEM; + } + + /* todo: may need to check resource allocaiton/ownership for these */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE, + IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY0, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY0_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY1, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY1_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY2, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY2_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY3, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY3_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY4, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY4_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY5, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY5_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY6, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY6_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY7, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY7_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE, + IMXDPUV1_FETCHLAYER1_TRIGGERENABLE_RESET_VALUE); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY0, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY1, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY2, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY3, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY4, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY5, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY6, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY7, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE, + IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_VALUE); + + /* Initial StaticControl configuration - reset values */ + /* IMXDPUV1_FETCHDECODE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE9_STATICCONTROL, + IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_FETCHPERSP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHPERSP9_STATICCONTROL, + IMXDPUV1_FETCHPERSP9_STATICCONTROL_RESET_VALUE); +#else + /* IMXDPUV1_FETCHPERSP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP9_STATICCONTROL, + IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_VALUE); +#endif + + /* IMXDPUV1_FETCHECO9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_ROP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_ROP9_STATICCONTROL, + IMXDPUV1_ROP9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_CLUT9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_STATICCONTROL, + IMXDPUV1_CLUT9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_MATRIX9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_MATRIX9_STATICCONTROL, + IMXDPUV1_MATRIX9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_HSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_HSCALER9_STATICCONTROL, + IMXDPUV1_HSCALER9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_VSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_VSCALER9_STATICCONTROL, + IMXDPUV1_VSCALER9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FILTER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FILTER9_STATICCONTROL, + IMXDPUV1_FILTER9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_BLITBLEND9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_BLITBLEND9_STATICCONTROL, + IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_STORE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE9_STATICCONTROL, + IMXDPUV1_STORE9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_CONSTFRAME0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME0_STATICCONTROL, + IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST0_STATICCONTROL, + IMXDPUV1_EXTDST0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST4_STATICCONTROL, + IMXDPUV1_EXTDST4_STATICCONTROL_RESET_VALUE); + + /* todo: IMXDPUV1_CONSTFRAME4_STATICCONTROL */ + + /* IMXDPUV1_CONSTFRAME1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME1_STATICCONTROL, + IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST1_STATICCONTROL, + IMXDPUV1_EXTDST1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST5_STATICCONTROL, + IMXDPUV1_EXTDST5_STATICCONTROL_RESET_VALUE); + + /* todo: IMXDPUV1_CONSTFRAME5_STATICCONTROL */ +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_EXTSRC4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC4_STATICCONTROL, + IMXDPUV1_EXTSRC4_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_STORE4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE4_STATICCONTROL, + IMXDPUV1_STORE4_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTSRC5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC5_STATICCONTROL, + IMXDPUV1_EXTSRC5_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_STORE5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE5_STATICCONTROL, + IMXDPUV1_STORE5_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE2_STATICCONTROL, + IMXDPUV1_FETCHDECODE2_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE3_STATICCONTROL, + IMXDPUV1_FETCHDECODE3_STATICCONTROL_RESET_VALUE); +#endif + /* IMXDPUV1_FETCHWARP2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_STATICCONTROL, + IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHECO2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE0_STATICCONTROL, + IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHECO0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO0_STATICCONTROL, + IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE1_STATICCONTROL, + IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHECO1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO1_STATICCONTROL, + IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_VALUE); + + /* todo: IMXDPUV1_MATRIX5_STATICCONTROL */ + /* todo: IMXDPUV1_HSCALER5_STATICCONTROL */ + /* todo: IMXDPUV1_VSCALER5_STATICCONTROL */ + /* IMXDPUV1_LAYERBLEND0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND0_STATICCONTROL, + IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND1_STATICCONTROL, + IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND2_STATICCONTROL, + IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND3_STATICCONTROL, + IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_LAYERBLEND4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND5_STATICCONTROL, + IMXDPUV1_LAYERBLEND5_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND6_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND6_STATICCONTROL, + IMXDPUV1_LAYERBLEND6_STATICCONTROL_RESET_VALUE); +#endif + /* Dynamic config */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHPERSP9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#else + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC, + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC, + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE2_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE3_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_GAMMACOR4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HISTOGRAM4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_GAMMACOR5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HISTOGRAM5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#endif + /* Static configuration - reset values */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_STATIC, + IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_STATIC, + IMXDPUV1_PIXENGCFG_STORE4_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_STATIC, + IMXDPUV1_PIXENGCFG_STORE5_STATIC_RESET_VALUE); +#endif + /* Static configuration - initial settings */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE, + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__SINGLE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET, + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE, + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__AUTO) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET, + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); + + /* todo: IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_OFFSET */ + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE, + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__AUTO) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET, + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); + + /* todo: IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_OFFSET */ +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SYNC_MODE, + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SYNC_MODE__SINGLE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SW_RESET, + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); +#endif + /* todo: IMXDPUV1_PIXENGCFG_STORE4_STATIC */ + /* Static Control configuration */ + /* IMXDPUV1_FETCHDECODE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_FETCHPERSP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHPERSP9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHPERSP9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHPERSP9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#else + /* IMXDPUV1_FETCHWARP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#endif + /* IMXDPUV1_FETCHECO9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_ROP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_ROP9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_ROP9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_CLUT9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_STATICCONTROL_SHDEN, 1)); + + imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_UNSHADOWEDCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN, + IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__ENABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN, + IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__ENABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN, + IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__ENABLE)); + + /* IMXDPUV1_MATRIX9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_MATRIX9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_HSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_HSCALER9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_VSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_VSCALER9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_FILTER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FILTER9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FILTER9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_BLITBLEND9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_BLITBLEND9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_STORE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1)); + + /* IMXDPUV1_CONSTFRAME0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_EXTDST0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE, + IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__EXTERNAL)); + + /* todo: IMXDPUV1_CONSTFRAME4_STATICCONTROL */ + /* todo: IMXDPUV1_EXTDST4_STATICCONTROL */ + + /* IMXDPUV1_CONSTFRAME1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_EXTDST1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE, + IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__EXTERNAL)); + + /* todo: IMXDPUV1_CONSTFRAME5_STATICCONTROL */ + /* todo: IMXDPUV1_EXTDST5_STATICCONTROL */ +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_EXTSRC4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL, + IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL__LOCAL)); + + /* IMXDPUV1_STORE4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE4_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE4_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1)); + + /* IMXDPUV1_EXTSRC5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC5_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC5_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC5_STATICCONTROL_STARTSEL, + IMXDPUV1_EXTSRC5_STATICCONTROL_STARTSEL__LOCAL)); + + /* IMXDPUV1_STORE5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE5_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE5_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE5_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1)); + + /* IMXDPUV1_FETCHDECODE2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE2_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE2_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE2_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHDECODE3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE3_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE3_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE3_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#endif + /* IMXDPUV1_FETCHWARP2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY, 0)); + + /* IMXDPUV1_FETCHECO2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHDECODE0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE, + 0)); + + /* IMXDPUV1_FETCHECO0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHDECODE1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHECO1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHLAYER0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY, 0)); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_FETCHLAYER1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHLAYER1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER1_STATICCONTROL_SHDLDREQSTICKY, 0)); + + /* IMXDPUV1_GAMMACOR4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR4_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR4_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR4_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR4_STATICCONTROL_REDWRITEENABLE, 1)); +#endif + /* todo: IMXDPUV1_MATRIX4_STATICCONTROL */ + /* todo: IMXDPUV1_HSCALER4_STATICCONTROL */ + /* todo: IMXDPUV1_VSCALER4_STATICCONTROL */ +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_GAMMACOR5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR5_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR5_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR5_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR5_STATICCONTROL_REDWRITEENABLE, 1)); +#endif + /* todo: IMXDPUV1_MATRIX5_STATICCONTROL */ + /* todo: IMXDPUV1_HSCALER5_STATICCONTROL */ + /* todo: IMXDPUV1_VSCALER5_STATICCONTROL */ + + /* IMXDPUV1_LAYERBLEND0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND2_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND3_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__BOTH)); + +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_LAYERBLEND4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND5_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND6_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND6_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDTOKSEL__BOTH)); +#endif + /* todo: IMXDPUV1_EXTSRC0_STATICCONTROL */ + /* todo: IMXDPUV1_EXTSRC1_STATICCONTROL */ + /* todo: IMXDPUV1_MATRIX0_STATICCONTROL */ + /* IMXDPUV1_GAMMACOR0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR0_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE, 1)); + /* todo: IMXDPUV1_SIG0_STATICCONTROL */ + /* todo: IMXDPUV1_MATRIX1_STATICCONTROL */ + /* IMXDPUV1_GAMMACOR1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR1_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE, 1)); + /* IMXDPUV1_SIG1_STATICCONTROL */ + + imxdpuv1_init_irqs(imxdpuv1_id); + + return ret; +} + +int imxdpuv1_init_sync_panel(int8_t imxdpuv1_id, + int8_t disp, + uint32_t pixel_fmt, struct imxdpuv1_videomode mode) +{ + int ret = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + return ret; +} + +int imxdpuv1_uninit_sync_panel(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + return ret; +} + +int imxdpuv1_reset_disp_panel(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + return ret; +} + +/*! + * This function initializes the display + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_init(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + struct imxdpuv1_videomode *mode; + int reg = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + mode = &imxdpu->video_mode[disp]; + /*imxdpuv1_disp_dump_mode(&imxdpu->video_mode[disp]);*/ + + if (disp == 0) { +#ifdef IMXDPUV1_TCON0_MAP_24BIT_0_23 + /* Static 24-bit TCON bit mapping for FPGA */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT7_4, 0x1d1c1b1a); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT3_0, 0x19181716); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT15_12, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT11_8, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT23_20, 0x09080706); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT19_16, 0x05040302); +#else + /* tcon mapping + * RR RRRR RRRR GGGG GGGG GGBB BBBB BBBB + * 98 7654 3210 9876 5432 1098 7654 3210 + * bits + * 00 0000 0000 1111 1111 1122 2222 2222 + * 98 7654 3210 8765 5432 1098 7654 3210 + */ + /* 30-bit timing controller setup */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT31_28, 0x00000908); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT27_24, 0x07060504); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT23_20, 0x03020100); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT19_16, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT15_12, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT11_8, 0x0b0a1d1c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT7_4, 0x1b1a1918); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT3_0, 0x17161514); + +#endif + + /* set data enable polarity */ + if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__HIGH); + else + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__LOW); + + imxdpuv1_write(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL0, reg); + /* printf("polreg=0x%x\n", imxdpuv1_read(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL0)); */ + + } else if (disp == 1) { +#ifdef IMXDPUV1_TCON1_MAP_24BIT_0_23 + /* Static TCON bit mapping */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT7_4, 0x1d1c1b1a); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT3_0, 0x19181716); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT15_12, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT11_8, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT23_20, 0x09080706); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT19_16, 0x05040302); +#else + /* tcon mapping + * RR RRRR RRRR GGGG GGGG GGBB BBBB BBBB + * 98 7654 3210 9876 5432 1098 7654 3210 + * bits + * 00 0000 0000 1111 1111 1122 2222 2222 + * 98 7654 3210 8765 5432 1098 7654 3210 + */ + /* 30-bit timing controller setup */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT31_28, 0x00000908); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT27_24, 0x07060504); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT23_20, 0x03020100); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT19_16, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT15_12, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT11_8, 0x0b0a1d1c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT7_4, 0x1b1a1918); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT3_0, 0x17161514); +#endif + /* set data enable polarity */ + if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__HIGH); + else + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__LOW); + + imxdpuv1_write(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL1, reg); + /* printf("polreg=0x%x\n", imxdpuv1_read(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL1)); */ + + } else { + return -EINVAL; + } + /* todo: initialize prefetch */ + + return ret; +} + +int imxdpuv1_disp_setup_tcon_bypass_mode( + int8_t imxdpuv1_id, + int8_t disp, + const struct imxdpuv1_videomode *mode) +{ + struct imxdpuv1_soc *imxdpu; + uint32_t b_off; /* block offset for tcon generator */ + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_TCON0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_TCON1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_TCON_CTRL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE, + IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__BALANCED) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE, + IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION, + 0x140)); + /* setup hsync */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0POSON_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0, mode->hlen + mode->hfp)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0MASKON_OFFSET, 0xffff); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0, mode->hlen + mode->hfp + mode->hsync)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0MASKOFF_OFFSET, 0xffff); + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX0SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0, 2)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX0FCTTABLE_OFFSET, 1); + + /* Setup Vsync */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1POSON_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1, mode->hlen + mode->hfp + mode->hsync) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1, mode->vlen + mode->vfp - 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1MASKON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1, mode->hlen + mode->hfp + mode->hsync)| + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1, mode->vlen + mode->vfp + mode->vsync - 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1MASKOFF_OFFSET, 0); + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX1SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0, 3)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX1FCTTABLE_OFFSET, 1); + + /* data enable horizontal */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2POSON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2MASKON_OFFSET, 0xffff); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2, mode->hlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2MASKOFF_OFFSET, 0xffff); + /* data enable vertical */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3POSON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3MASKON_OFFSET, 0x7fff0000); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3, mode->vlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3MASKOFF_OFFSET, 0x7fff0000); + + /* use both SPG2 and SPG3 to generate data enable */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX2SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0, 4)| + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1, 5)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX2FCTTABLE_OFFSET, 8); + + /* shadow load trigger (aka kachunk) */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4POSON_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4, 10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4, mode->vlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4MASKON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4, 26) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4, mode->vlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4MASKOFF_OFFSET, 0); + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX3SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0, 6)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX3FCTTABLE_OFFSET, 2); + + return 0; +} + +/*! + * This function sets up the frame generator + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param enable state to set frame generator to + * @param mode to set the display to + * @param cc_red constant color red + * @param cc_green constant color green + * @param cc_blue constant color blue + * @param cc_alpha constant color alpha +* + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_frame_gen( + int8_t imxdpuv1_id, + int8_t disp, + const struct imxdpuv1_videomode *mode, + uint16_t cc_red, /* 10 bits */ + uint16_t cc_green, /* 10 bits */ + uint16_t cc_blue, /* 10 bits */ + uint8_t cc_alpha, + bool test_mode_enable) +{ /* 1 bits, yes 1 bit */ + int ret = 0; + uint32_t b_off; /* block offset for frame generator */ + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + /* todo: + add video mode sanity check here + check if LRSYNC is required + */ + + if (mode->flags & IMXDPUV1_MODE_FLAGS_LRSYNC) { + /* todo: here we need to use two outputs to make one */ + if (disp == 0) { + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE, + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__MASTER); + } else { + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE, + IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_CYC); + } + } else { + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE, + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__OFF); + } + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGSTCTRL_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG1_HACT, mode->hlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL, + (mode->hlen + mode->hfp + mode->hbp + mode->hsync - 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_HTCFG1_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC, + mode->hsync - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP, + mode->hbp + mode->hsync - 1) | + /* shadow enable */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_HTCFG2_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG1_VACT, mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL, + (mode->vlen + mode->vfp + mode->vbp + mode->vsync - + 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_VTCFG1_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC, + mode->vsync - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP, + mode->vbp + mode->vsync - 1) | + /* shadow enable */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_VTCFG2_OFFSET, reg); + + /* Interupt at position (0, vlen - 3) for end of frame interrupt */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW, + mode->vlen - 3) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT0CONFIG_OFFSET, reg); + + /* Interupt at position 1, mode->vlen */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW, + mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT1CONFIG_OFFSET, reg); + + /* Interupt at position 2, mode->vlen */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL, 2) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW, + mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT2CONFIG_OFFSET, reg); + + /* Interupt at position 3, mode->vlen */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL, 3) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW, + mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT3CONFIG_OFFSET, reg); + + /* todo: these need to be checked + _SKICKCOL for verification: =(FW - 40) , for ref driver = 1 ? + _SKICKROW for verif. =(FH - 1), ref driver = vlen-2 + */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL, + mode->hlen - 40) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW, + mode->vlen + 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_SKICKCONFIG_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_PACFG_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_SACFG_OFFSET, reg); + + if (IMXDPUV1_ENABLE == test_mode_enable) { + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM, + IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__TEST); + } else { + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM, + IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA, 0); + } + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGINCTRL_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC, + IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__CONSTCOL) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC, 0); + imxdpuv1_write(imxdpu, b_off + + IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_OFFSET, reg); + + /* Set the constant color - ARGB 1-10-10-10 */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCRED, cc_red) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE, cc_blue) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN, cc_green) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA, cc_alpha); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGCCR_OFFSET, reg); + + + imxdpuv1_disp_setup_tcon_bypass_mode(imxdpuv1_id, disp, mode); + + /* save the mode */ + imxdpu->video_mode[disp] = *mode; + + /* imxdpuv1_disp_dump_mode(&imxdpu->video_mode[disp]); */ + + return ret; +} + +/*! + * This function updates the frame generator status + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_update_fgen_status(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + uint32_t b_off; /* block offset for frame generator */ + uint32_t reg; + uint32_t temp; + struct imxdpuv1_soc *imxdpu; + static uint32_t fcount[IMXDPUV1_NUM_DI_MAX] = { 0, 0 }; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + /* todo: + add video mode sanity check here + check if LRSYNC is required + */ + + reg = imxdpuv1_read_irq(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_OFFSET); + IMXDPUV1_TRACE_IRQ("DISP %d: findex %d, lindex %d\n", disp, + IMXDPUV1_GET_FIELD + (IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX, reg), + IMXDPUV1_GET_FIELD + (IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX, reg)); + + temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX, reg); + if (temp != fcount[disp]) { + fcount[disp] = temp; + /* Just increment we assume this is called one per frame */ + imxdpu->fgen_stats[disp].frame_count++; + } + + reg = imxdpuv1_read_irq(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGCHSTAT_OFFSET); + temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT, reg); + + /* Sync status bits should be set */ + if ((temp != imxdpu->fgen_stats[disp].sec_sync_state) && (temp == 1)) { + imxdpu->fgen_stats[disp].sec_sync_count++; + IMXDPUV1_TRACE_IRQ("DISP %d: sec in sync\n", disp); + } + if ((temp != imxdpu->fgen_stats[disp].sec_sync_state) && (temp == 0)) { + IMXDPUV1_TRACE_IRQ("DISP %d: sec out of sync\n", disp); + } + imxdpu->fgen_stats[disp].sec_sync_state = temp; + temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT, reg); + + /* Sync status bits should be set */ + if ((temp != imxdpu->fgen_stats[disp].prim_sync_state) && + (temp == 1)) { + imxdpu->fgen_stats[disp].prim_sync_count++; + IMXDPUV1_TRACE_IRQ("DISP %d: prim in sync\n", disp); + } + if ((temp != imxdpu->fgen_stats[disp].prim_sync_state) && + (temp == 0)) { + IMXDPUV1_TRACE_IRQ("DISP %d: prim out of sync\n", disp); + } + imxdpu->fgen_stats[disp].prim_sync_state = temp; + + /* primary fifo bit should be clear if in use (panic stream) */ + if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY, reg)) { + IMXDPUV1_TRACE_IRQ("DISP %d: primary fifo empty\n", disp); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET, + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_MASK); + imxdpu->fgen_stats[disp].prim_fifo_empty_count++; + } + /* secondary fifo and skew error bits should be clear + if in use (content stream) */ + if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY, reg) || + IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR, reg)) { + if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY, reg)) { + IMXDPUV1_TRACE_IRQ("DISP %d: secondary fifo empty\n", + disp); + imxdpu->fgen_stats[disp].sec_fifo_empty_count++; + } + if (IMXDPUV1_GET_FIELD + (IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR, reg)) { + IMXDPUV1_TRACE_IRQ("DISP %d: secondary skew error\n", + disp); + imxdpu->fgen_stats[disp].skew_error_count++; + } + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET, + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_MASK); + } + return ret; +} +/*! + * This function sets up the frame capture + * + * @param imxdpuv1_id id of the diplay unit + * @param src_id id of the capture source block + * @param dest_id id of the capture dest block + * @param sync_count number of valid required to aquire sync + * @param cap_mode mode of the video input + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_setup_frame( + int8_t imxdpuv1_id, + int8_t src_id, + int8_t dest_id, + int8_t sync_count, + const struct imxdpuv1_videomode *cap_mode) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + uint32_t b_off_frame; /* block offset for capture source */ + uint32_t b_off_extsrc; /* block offset for extsrc */ + + int8_t cap_id; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (src_id == IMXDPUV1_ID_FRAMECAP4) { + cap_id = 0; + b_off_frame = IMXDPUV1_FRAMECAP4_LOCKUNLOCK; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMECAP5) { + cap_id = 1; + b_off_frame = IMXDPUV1_FRAMECAP5_LOCKUNLOCK; + b_off_extsrc = IMXDPUV1_EXTSRC5_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP0) { + cap_id = 0; + b_off_frame = IMXDPUV1_FRAMEDUMP0_CONTROL; + b_off_extsrc = IMXDPUV1_EXTSRC0_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP1) { + cap_id = 1; + b_off_frame = IMXDPUV1_FRAMEDUMP1_CONTROL; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else { + return -EINVAL; + } + + if (dest_id == IMXDPUV1_ID_STORE4) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC_STORE4_SRC_SEL__EXTSRC4); + } else if (dest_id == IMXDPUV1_ID_STORE5) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC_STORE5_SRC_SEL__EXTSRC5); + } else if (dest_id == IMXDPUV1_ID_EXTDST0) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC, + IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC4); + } else if (dest_id == IMXDPUV1_ID_EXTDST1) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC, + IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC5); + } else { + return -EINVAL; + } + + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_STATICCONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL, + IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL__LOCAL) | + IMXDPUV1_EXTSRC4_STATICCONTROL_SHDEN_MASK); + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_CONSTANTCOLOR_OFFSET, 0); + + if (cap_mode->format == IMXDPUV1_PIX_FMT_BGR24) { + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSRED, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSGREEN, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSBLUE, 0x8)); + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE, 0x00)); + + /* fixme: handle all cases for control */ + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_YUVCONVERSIONMODE, + IMXDPUV1_EXTSRC4_CONTROL_YUVCONVERSIONMODE__ITU601) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE, + IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE__YUV422) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_YUV422UPSAMPLINGMODE, + IMXDPUV1_EXTSRC4_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE) | + IMXDPUV1_EXTSRC4_CONTROL_CLIPWINDOWENABLE_MASK); + + } else if (cap_mode->format == IMXDPUV1_PIX_FMT_YUYV) { + + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_OFFSET, + + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSRED, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSGREEN, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSBLUE, 0x8)); + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE, 0x0)); + + /* fixme: handle all cases for control */ + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE, + IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE__YUV422) | + IMXDPUV1_EXTSRC4_CONTROL_CLIPWINDOWENABLE_MASK); + + } else { + IMXDPUV1_PRINT("%s(): invalid capture interface format\n", __func__); + return -EINVAL; + } + + + if ((src_id == IMXDPUV1_ID_FRAMECAP4) || (src_id == IMXDPUV1_ID_FRAMECAP5)) { + /* setup cature */ + uint8_t capture_interface_mode; + /* Fixme: change these mode bits to an enumeration */ + if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_32BIT) != 0) { + capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ENHSVS_32BIT; + } else if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_BT656_10BIT) != 0) { + capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ITU656_10BIT; + } else if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_BT656_8BIT) != 0) { + capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ITU656_8BIT; + } else { + return -EINVAL; + } + + if (cap_id == 0) { + imxdpuv1_write(imxdpu, IMXDPUV1_CAPENGCFG_CAPTUREINPUT0, + IMXDPUV1_SET_FIELD(IMXDPUV1_CAPENGCFG_CAPTUREINPUT0_CAPTUREMODE0, + capture_interface_mode)); + } else { + imxdpuv1_write(imxdpu, IMXDPUV1_CAPENGCFG_CAPTUREINPUT1, + IMXDPUV1_SET_FIELD(IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1, + capture_interface_mode)); + } + + imxdpuv1_write(imxdpu, b_off_frame + IMXDPUV1_FRAMECAP4_FDR_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_HEIGHT, cap_mode->vlen - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_WIDTH, cap_mode->hlen - 1)); + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_FDR1_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_HEIGHT, cap_mode->vlen1 - 1)); + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_SCR_OFFSET, sync_count); + + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_KCR_OFFSET, 0); + if ((cap_mode->clip_height != 0) && (cap_mode->clip_width != 0)) { + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWHEIGHT, cap_mode->clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWWIDTH, cap_mode->clip_width - 1)); + + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWXOFFSET, cap_mode->clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWYOFFSET, cap_mode->clip_top)); + } + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_SPR_OFFSET, + + /* low is active low, high is active high */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLHS, + ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) != 0)) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLVS, + ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) != 0)) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLEN, + ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) == 0)) + ); + + + /* fixme: may need to move this mapping */ + if (src_id == IMXDPUV1_ID_FRAMECAP4) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC_STORE4_SRC_SEL__EXTSRC4); + } else if (src_id == IMXDPUV1_ID_FRAMECAP5) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC_STORE5_SRC_SEL__EXTSRC5); + } + } + + if ((src_id == IMXDPUV1_ID_FRAMEDUMP0) || (src_id == IMXDPUV1_ID_FRAMEDUMP1)) { + /* todo */ + } + + /* save the mode */ + imxdpu->capture_mode[cap_id] = *cap_mode; + /* imxdpuv1_disp_dump_mode(cap_mode); */ + return ret; +#endif +} + +/*! + * This function sets up the frame capture + * + * @param imxdpuv1_id id of the diplay unit + * @param cap id of the capture inpute + * @param sync_count number of valid required to aquire sync + * @param cap_mode mode of the video input + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_setup_crop( + int8_t imxdpuv1_id, + int8_t src_id, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + uint32_t b_off_extsrc; /* block offset for extsrc */ +#if 0 + uint32_t b_off_dest; /* block offset for destination */ +#endif + int8_t cap_id; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (src_id == IMXDPUV1_ID_FRAMECAP4) { + cap_id = 0; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMECAP5) { + cap_id = 1; + b_off_extsrc = IMXDPUV1_EXTSRC5_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP0) { + cap_id = 0; + b_off_extsrc = IMXDPUV1_EXTSRC0_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP1) { + cap_id = 1; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else { + return -EINVAL; + } + + if ((src_id == IMXDPUV1_ID_FRAMECAP4) || (src_id == IMXDPUV1_ID_FRAMECAP5)) { + if ((clip_height != 0) && (clip_width != 0)) { + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWHEIGHT, clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWWIDTH, clip_width - 1)); + + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWXOFFSET, clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWYOFFSET, clip_top)); + /* save the clip data */ + imxdpu->capture_mode[cap_id].clip_height = clip_height; + imxdpu->capture_mode[cap_id].clip_width = clip_width; + imxdpu->capture_mode[cap_id].clip_top = clip_top; + imxdpu->capture_mode[cap_id].clip_left = clip_left; + } + } + + if ((src_id == IMXDPUV1_ID_FRAMEDUMP0) || (src_id == IMXDPUV1_ID_FRAMEDUMP1)) { + /* todo */ + } + /* imxdpuv1_disp_dump_mode(&imxdpu->video_mode[cap_id]); */ + return ret; +#endif +} +/*! + * This function enables the frame capture + * + * @param imxdpuv1_id id of the display unit + * @param cap id of the capture output pipe + * @param enable state to set frame generator to + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_enable(int8_t imxdpuv1_id, int8_t cap, bool enable) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + uint32_t b_off; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (cap == 0) { + b_off = IMXDPUV1_FRAMECAP4_LOCKUNLOCK; + } else { + return -EINVAL; + } + + if (enable) { + /* imxdpuv1_dump_pixencfg_status(imxdpuv1_id); */ + printf("%s(): %s:%d stubbed feature\n", __func__, __FILE__, __LINE__); + /* imxdpuv1_dump_pixencfg_status(imxdpuv1_id); */ + } + reg = enable ? IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_CTR_CEN, 1) : + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_CTR_CEN, 0); + + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMECAP4_CTR_OFFSET, reg); + + return ret; +#endif +} + +/*! + * This function triggers a shadow load + * + * @param imxdpuv1_id id of the diplay unit + * @param dest_id id of the capture dest block + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_request_shadow_load(int8_t imxdpuv1_id, int8_t dest_id, uint32_t mask) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + switch (dest_id) { + case IMXDPUV1_ID_STORE4: + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE4_REQUEST, + mask); + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE4_TRIGGER, + IMXDPUV1_PIXENGCFG_STORE4_TRIGGER_STORE4_SYNC_TRIGGER_MASK); + break; + case IMXDPUV1_ID_STORE5: + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE5_REQUEST, + mask); + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE5_TRIGGER, + IMXDPUV1_PIXENGCFG_STORE5_TRIGGER_STORE5_SYNC_TRIGGER_MASK); + break; + + default: + return -EINVAL; + + } + return ret; +#endif +} + +/*! + * This function requests a shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param shadow_load_idx index of the shadow load requested + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_request_shadow_load(int8_t imxdpuv1_id, + int8_t disp, + imxdpuv1_shadow_load_index_t shadow_load_idx) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s(): imxdpuv1_id %d, disp %d, shadow_load_idx %d\n", + __func__, imxdpuv1_id, disp, shadow_load_idx); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + /* trigger configuration of the pipeline */ + + if ((disp == 0) || (disp == 1)) { + /* last request was complete or no request in progress, + then start a new request */ + if (imxdpu->shadow_load_state[disp][shadow_load_idx].word == 0) { + imxdpu->shadow_load_state[disp][shadow_load_idx].state. + request = IMXDPUV1_TRUE; + } else { /* check ifg the request is busy */ + IMXDPUV1_TRACE("%s(): shadow load not complete.", __func__); + return -EBUSY; + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function force a shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param shadow_load_idx index of the shadow load requested + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_force_shadow_load(int8_t imxdpuv1_id, + int8_t disp, + uint64_t mask) +{ + int ret = 0; + uint32_t addr_extdst; /* address for extdst */ + uint32_t addr_fgen; /* address for frame generator */ + uint32_t extdst = 0; + uint32_t fgen = 0; + uint32_t sub = 0; + struct imxdpuv1_soc *imxdpu; + int i; + uint64_t temp_mask; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!((disp == 0) || (disp == 1))) { + return -EINVAL; + } + + if (mask == 0) { + return -EINVAL; + } + + if (disp == 0) { + addr_fgen = IMXDPUV1_FRAMEGEN0_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST; + } else if (disp == 1) { + addr_fgen = IMXDPUV1_FRAMEGEN1_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST; + } else { + return -EINVAL; + } + + for (i = 0; i < IMXDPUV1_SHDLD_IDX_MAX; i++) { + temp_mask = 1 << i; + if ((mask & temp_mask) == 0) + continue; + + extdst |= trigger_list[i].extdst; + sub |= trigger_list[i].sub; + + if ((i == IMXDPUV1_SHDLD_IDX_CONST0) || + (i == IMXDPUV1_SHDLD_IDX_CONST1)) { + fgen |= 1; + } + mask &= ~temp_mask; + } + + if (sub) { + IMXDPUV1_TRACE_IRQ("Fetch layer shadow request 0x%08x\n", sub); + if (sub & 0xff) { /* FETCHLAYER0 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE, + sub & 0xff); + } +#ifdef IMXDPUV1_VERSION_0 + if (sub & 0xff00) { /* FETCHLAYER1 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE, + (sub >> 8) & 0xff); + } +#endif + if (sub & 0xff0000) { /* FETCHWARP2 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE, + (sub >> 16) & 0xff); + } + } + + if (extdst) { + IMXDPUV1_TRACE_IRQ("Extdst shadow request 0x%08x\n", extdst); + imxdpuv1_write(imxdpu, addr_extdst, extdst); + } + + if (fgen) { + IMXDPUV1_TRACE_IRQ("Fgen shadow request 0x%08x\n", fgen); + imxdpuv1_write(imxdpu, addr_fgen, fgen); + } + + return ret; +} + +/*! + * This function shows the frame generators status + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_show_fgen_status(int8_t imxdpuv1_id) +{ +#ifndef ENABLE_IMXDPUV1_TRACE + return 0; +#else + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + IMXDPUV1_PRINT("IMXDPU %d stat fg0 fg1\n" + "prim_sync_state: %10d %10d\n" + "sec_sync_state: %10d %10d\n" + "prim_sync_count: %10d %10d\n" + "sec_sync_count: %10d %10d\n" + "skew_error_count: %10d %10d\n" + "prim_fifo_empty_count: %10d %10d\n" + "sec_fifo_empty_count: %10d %10d\n" + "frame_count: %10d %10d\n" + "irq_count: %10u\n\n", + imxdpuv1_id, + imxdpu->fgen_stats[0].prim_sync_state, + imxdpu->fgen_stats[1].prim_sync_state, + imxdpu->fgen_stats[0].sec_sync_state, + imxdpu->fgen_stats[1].sec_sync_state, + imxdpu->fgen_stats[0].prim_sync_count, + imxdpu->fgen_stats[1].prim_sync_count, + imxdpu->fgen_stats[0].sec_sync_count, + imxdpu->fgen_stats[1].sec_sync_count, + imxdpu->fgen_stats[0].skew_error_count, + imxdpu->fgen_stats[1].skew_error_count, + imxdpu->fgen_stats[0].prim_fifo_empty_count, + imxdpu->fgen_stats[1].prim_fifo_empty_count, + imxdpu->fgen_stats[0].sec_fifo_empty_count, + imxdpu->fgen_stats[1].sec_fifo_empty_count, + imxdpu->fgen_stats[0].frame_count, + imxdpu->fgen_stats[1].frame_count, + imxdpu->irq_count); + + return ret; +#endif +} + +/*! + * This function enables the frame generator + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param enable state to set frame generator to + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_enable_frame_gen(int8_t imxdpuv1_id, int8_t disp, bool enable) +{ + int ret = 0; + uint32_t b_off; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + imxdpuv1_disp_start_shadow_loads(imxdpuv1_id, disp); + + reg = enable ? IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN, 1) : + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGENABLE_OFFSET, reg); + + return ret; +} + +/*! + * This function sets up the constframe generator + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param bg_red background red + * @param bg_green background green + * @param bg_blue background blue + * @param bg_alpha background alpha + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_constframe( + int8_t imxdpuv1_id, + int8_t disp, + uint8_t bg_red, + uint8_t bg_green, + uint8_t bg_blue, + uint8_t bg_alpha) +{ + int ret = 0; + uint32_t b_off; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_shadow_load_index_t shadow_idx; + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* todo: add constfram4 and constframe5 */ + if (disp == 0) { + b_off = IMXDPUV1_CONSTFRAME0_LOCKUNLOCK; + shadow_idx = IMXDPUV1_SHDLD_IDX_CONST0; + } else if (disp == 1) { + b_off = IMXDPUV1_CONSTFRAME1_LOCKUNLOCK; + shadow_idx = IMXDPUV1_SHDLD_IDX_CONST1; + } else { + return -EINVAL; + } + + if (imxdpu->video_mode[disp].flags & IMXDPUV1_MODE_FLAGS_LRSYNC) { + /* todo: need to handle sync display case */ + } + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT, + imxdpu->video_mode[disp].vlen - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH, + imxdpu->video_mode[disp].hlen - 1); + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_OFFSET, reg); + + /* todo: add linear light correction if needed */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTRED, bg_red) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTGREEN, bg_green) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTBLUE, bg_blue) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTALPHA, bg_alpha)); + + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, disp, shadow_idx); + + /* todo: add linear light correction if needed */ + return ret; +} + +/*! + * This function sets up a layer + * + * @param imxdpuv1_id id of the diplay unit + * @param layer layer data to use + * @param layer_idx layer index to use + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_layer(int8_t imxdpuv1_id, + const imxdpuv1_layer_t *layer, + imxdpuv1_layer_idx_t layer_idx, + bool is_top_layer) +{ + int ret = 0; + uint32_t dynamic_offset; + uint32_t static_offset; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + IMXDPUV1_TRACE("%s(): enable %d, primary %d, secondary %d, stream 0x%08x\n", __func__, + layer->enable, + layer->primary, + layer->secondary, + layer->stream); + imxdpu->blend_layer[layer_idx] = *layer; + + dynamic_offset = id2dynamicoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (dynamic_offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + static_offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (static_offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + reg = + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL, + imxdpu->blend_layer[layer_idx].primary) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL, + imxdpu->blend_layer[layer_idx].secondary) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN, + IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__AUTOMATIC); + imxdpuv1_write(imxdpu, dynamic_offset, reg); + + if (imxdpu->blend_layer[layer_idx].stream & IMXDPUV1_DISPLAY_STREAM_0) { + + IMXDPUV1_TRACE("%s(): IMXDPUV1_DISPLAY_STREAM_0\n", __func__); + if (is_top_layer) { + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL, + layer_idx + IMXDPUV1_ID_LAYERBLEND0); + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC, reg); + } + + /* trigger configuration of the pipeline */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER, + IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_MASK); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, 0, + IMXDPUV1_SHDLD_IDX_DISP0); + } + if (imxdpu->blend_layer[layer_idx].stream & IMXDPUV1_DISPLAY_STREAM_1) { + IMXDPUV1_TRACE_IRQ("%s(): IMXDPUV1_DISPLAY_STREAM_1\n", __func__); + if (is_top_layer) { + reg = + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL, + layer_idx + IMXDPUV1_ID_LAYERBLEND0); + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC, reg); + + } + /* trigger configuration of the pipeline */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER, + IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_MASK); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, 1, + IMXDPUV1_SHDLD_IDX_DISP1); + } + + /* todo: add code to disable a layer */ + return ret; +} + +/*! + * This function sets global alpha for a blend layer + * + * @param imxdpuv1_id id of the diplay unit + * @param layer_idx layer index to use + * @param alpha global alpha + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_layer_global_alpha(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + uint8_t alpha) +{ + int ret = 0; + uint32_t offset; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* update imxdpu */ + + offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA, + alpha) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE); + imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_OFFSET, + reg); + + reg = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_CONTROL_MODE, + IMXDPUV1_LAYERBLEND0_CONTROL_MODE__BLEND) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE, + IMXDPUV1_DISABLE); + + imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_CONTROL_OFFSET, reg); + + return ret; +} + +/*! + * This function sets the position of the a blend layer secondary input + * + * @param imxdpuv1_id id of the diplay unit + * @param layer_idx layer index to use + * @param x x position + * @param y y position + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_layer_position(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + int16_t x, int16_t y) +{ + int ret = 0; + uint32_t offset; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* update imxdpu */ + + offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_POSITION_XPOS, x) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_POSITION_YPOS, y); + imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_POSITION_OFFSET, reg); + + return ret; +} + +/*! + * This function sets the position of the a channel (window) layer + * + * @param imxdpuv1_id id of the diplay unit + * @param layer_idx layer index to use + * @param x x position + * @param y y position + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_chan_position(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, int16_t x, int16_t y) +{ + int ret = 0; + uint32_t offset; + int idx; + int sub_idx; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* update imxdpu */ + + offset = id2blockoffset(get_channel_blk(chan)); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + idx = get_channel_idx(chan); + if ((idx >= IMXDPUV1_CHAN_IDX_IN_MAX) || (idx < 0)) { + return -EINVAL; + } + + sub_idx = imxdpuv1_get_channel_subindex(chan); + + imxdpu->chan_data[idx].dest_top = y; + imxdpu->chan_data[idx].dest_left = x; + + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0, + imxdpu->chan_data[idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0, + imxdpu->chan_data[idx].dest_top); + + if (is_fetch_layer_chan(chan) || is_fetch_warp_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer or warp\n", __func__); + imxdpuv1_write(imxdpu, + offset + IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET + + ((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)), + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0); + + } else if (is_fetch_decode_chan(chan)) { + if (imxdpu->chan_data[idx].use_eco_fetch) { + imxdpuv1_disp_set_chan_position(imxdpuv1_id, + imxdpuv1_get_eco(chan), + x, y); + } + imxdpuv1_write(imxdpu, + offset + IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET, + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0); + } else if (is_fetch_eco_chan(chan)) { + imxdpuv1_write(imxdpu, + offset + IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET, + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0); + } else { + return -EINVAL; + } + + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[idx].disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + idx); + + return ret; +} + +/*! + * This function sets the source and destination crop + * position of the a channel (window) layer + * + * @param imxdpuv1_id id of the diplay unit + * @param chan chan to use + * @param clip_top source y position + * @param clip_left source x position + * @param clip_width source width + * @param clip_height source height + * @param dest_top destination y + * @param dest_left destination x + * @param dest_width destination width + * @param dest_height destination height + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_chan_crop( + int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height) +{ + int ret = 0; + uint32_t offset; + int idx; + int sub_idx; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + offset = id2blockoffset(get_channel_blk(chan)); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + idx = get_channel_idx(chan); + if ((idx >= IMXDPUV1_CHAN_IDX_IN_MAX) || (idx < 0)) { + return -EINVAL; + } + + if ((imxdpu->chan_data[idx].clip_height < 0) || + (imxdpu->chan_data[idx].clip_width < 0)) { + return -EINVAL; + } + + sub_idx = imxdpuv1_get_channel_subindex(chan); + + imxdpu->chan_data[idx].dest_top = dest_top; + imxdpu->chan_data[idx].dest_left = dest_left; + imxdpu->chan_data[idx].dest_width = IMXDPUV1_MIN(dest_width, clip_width); + imxdpu->chan_data[idx].dest_height = IMXDPUV1_MIN(dest_height, clip_height); + imxdpu->chan_data[idx].clip_top = clip_top; + imxdpu->chan_data[idx].clip_left = clip_left; + imxdpu->chan_data[idx].clip_width = IMXDPUV1_MIN(dest_width, clip_width); + imxdpu->chan_data[idx].clip_height = IMXDPUV1_MIN(dest_height, clip_height); + + /* Need to check more cases here */ + if ((imxdpu->chan_data[idx].clip_height != 0) && + (imxdpu->chan_data[idx].clip_width != 0)) { + imxdpu->chan_data[idx].fetch_layer_prop.layerproperty0 |= + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + IMXDPUV1_ENABLE); + imxdpu->chan_data[idx].fetch_layer_prop.clipwindowdimensions0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT, + imxdpu->chan_data[idx].clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH, + imxdpu->chan_data[idx].clip_width - 1); + } else { + imxdpu->chan_data[idx].fetch_layer_prop.layerproperty0 &= + ~IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_MASK; + imxdpu->chan_data[idx].fetch_layer_prop.clipwindowdimensions0 = 0; + } + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_XOFFSET, + imxdpu->chan_data[idx].dest_left - imxdpu->chan_data[idx].clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_YOFFSET, + imxdpu->chan_data[idx].dest_top - imxdpu->chan_data[idx].clip_top); + imxdpu->chan_data[idx].fetch_layer_prop.clipwindowoffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_XOFFSET, + imxdpu->chan_data[idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_YOFFSET, + imxdpu->chan_data[idx].dest_top); + + if (is_fetch_layer_chan(chan) || is_fetch_warp_chan(chan)) { + imxdpuv1_write_block(imxdpu, + offset + + IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET + + ((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)), + (void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0, + 5); + + } else if (is_fetch_decode_chan(chan)) { + if (imxdpu->chan_data[idx].use_eco_fetch) { + imxdpuv1_disp_set_chan_crop(imxdpuv1_id, + imxdpuv1_get_eco(chan), + clip_top, + clip_left, + clip_width, + clip_height, + dest_top, + dest_left, + dest_width, + dest_height); + } + imxdpuv1_write_block(imxdpu, + offset + + IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET, + (void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0, + 5); + } else if (is_fetch_eco_chan(chan)) { + imxdpuv1_write_block(imxdpu, + offset + IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET, + (void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0, + 5); + + } else { + return -EINVAL; + } + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[idx].disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + idx); + + return ret; +} + +/*! + * This function sets initializes a channel and buffer + * + * @param imxdpuv1_id id of the diplay unit + * @param chan chan to use + * @param src_pixel_fmt source pixel format + * @param clip_top source y position + * @param clip_left source x position + * @param clip_width source width + * @param clip_height source height + * @param stride stride of the buffer + * @param disp_id display id + * @param dest_top destination y + * @param dest_left destination x + * @param dest_width destination width + * @param dest_height destination height + * @param const_color constant color for clip region + * @param disp_addr display buffer physical address + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_channel(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t src_pixel_fmt, + uint16_t src_width, + uint16_t src_height, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + uint16_t stride, + uint8_t disp_id, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height, + uint32_t const_color, + bool use_global_alpha, + bool use_local_alpha, + unsigned int disp_addr) +{ + int ret = 0; + imxdpuv1_channel_params_t channel; + uint32_t uv_offset = 0; + + IMXDPUV1_TRACE("%s(): " + "imxdpuv1_id %d\n" + "chan_t chan %x\n" + "src_pixel_fmt 0x%x\n" + "src_width %d\n" + "src_height %d\n" + "clip_top %d\n" + "clip_left %d\n" + "clip_width %d\n" + "clip_height %d\n" + "stride %d\n" + "disp_id %d\n" + "dest_top %d\n" + "dest_left %d\n" + "dest_width %d\n" + "dest_height %d\n" + "const_color 0x%x\n" + "disp_addr 0x%x\n", + __func__, + imxdpuv1_id, + chan, + src_pixel_fmt, + src_width, + src_height, + clip_top, + clip_left, + clip_width, + clip_height, + stride, + disp_id, + dest_top, + dest_left, + dest_width, + dest_height, + const_color, + disp_addr); + + channel.common.chan = chan; + channel.common.src_pixel_fmt = src_pixel_fmt; + channel.common.src_width = src_width; + channel.common.src_height = src_height; + channel.common.clip_top = clip_top; + channel.common.clip_left = clip_left; + channel.common.clip_width = clip_width; + channel.common.clip_height = clip_height; + channel.common.stride = stride; + channel.common.disp_id = disp_id; + channel.common.dest_top = dest_top; + channel.common.dest_left = dest_left; + channel.common.dest_width = dest_width; + channel.common.dest_height = dest_height; + channel.common.const_color = const_color; + channel.common.use_global_alpha = use_global_alpha; + channel.common.use_local_alpha = use_local_alpha; + + if (imxdpuv1_get_planes(src_pixel_fmt) == 2) { + uv_offset = src_width * src_height; /* works for NV12 and NV16*/ + } + ret = imxdpuv1_init_channel(imxdpuv1_id, &channel); + + ret = imxdpuv1_init_channel_buffer(imxdpuv1_id, channel.common.chan, channel.common.stride, IMXDPUV1_ROTATE_NONE, + disp_addr, + uv_offset, + 0); + + ret = imxdpuv1_disp_set_chan_crop(imxdpuv1_id, + channel.common.chan, + channel.common.clip_top, + channel.common.clip_left, + channel.common.clip_width, + channel.common.clip_height, + channel.common.dest_top, + channel.common.dest_left, + channel.common.dest_width, + channel.common.dest_height); + +#ifdef DEBUG + { + imxdpuv1_chan_t eco_chan; + imxdpuv1_dump_channel(imxdpuv1_id, channel.common.chan); + eco_chan = imxdpuv1_get_eco(channel.common.chan); + if (eco_chan != 0) { + imxdpuv1_dump_channel(imxdpuv1_id, eco_chan); + } + } +#endif + return ret; +} + +/*! + * This function prints the video mode passed as a parameter + * + * @param *mode pointer to video mode struct to show + */ +void imxdpuv1_disp_dump_mode(const struct imxdpuv1_videomode *mode) +{ + IMXDPUV1_PRINT("%s():\n", __func__); + IMXDPUV1_PRINT("\thlen %4d\n", mode->hlen); + IMXDPUV1_PRINT("\thfp %4d\n", mode->hfp); + IMXDPUV1_PRINT("\thbp %4d\n", mode->hbp); + IMXDPUV1_PRINT("\thsync %4d\n", mode->hsync); + IMXDPUV1_PRINT("\tvlen %4d\n", mode->vlen); + IMXDPUV1_PRINT("\tvfp %4d\n", mode->vfp); + IMXDPUV1_PRINT("\tvbp %4d\n", mode->vbp); + IMXDPUV1_PRINT("\tvsync %4d\n", mode->vsync); + IMXDPUV1_PRINT("\tvlen1 %4d\n", mode->vlen1); + IMXDPUV1_PRINT("\tvfp1 %4d\n", mode->vfp1); + IMXDPUV1_PRINT("\tvbp1 %4d\n", mode->vbp1); + IMXDPUV1_PRINT("\tvsync1 %4d\n", mode->vsync1); + + IMXDPUV1_PRINT("\tflags 0x%08x:\n", mode->flags); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_HSYNC_POL is high\n"); + else + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_HSYNC_POL is low\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_VSYNC_POL is high\n"); + else + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_VSYNC_POL is low\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_DE_POL is high\n"); + else + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_DE_POL is low\n"); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_INTERLACED) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_INTERLACED is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_LRSYNC) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_LRSYNC is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_SPLIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_SPLIT is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_32BIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_32BIT is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_BT656_10BIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_BT656_10BIT is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_BT656_8BIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_BT656_8BIT is set\n"); +} + +/*! + * Returns the bytes per pixel + * + * @param pixel format + * + * @return returns number of bytes per pixel or zero + * if the format is not matched. + */ +int imxdpuv1_bytes_per_pixel(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + /* todo add NV12, and NV16 */ + case IMXDPUV1_PIX_FMT_NV12: + return 1; /* luma */ + + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + return 2; + break; + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + return 3; + break; + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_AYUV: + return 4; + break; + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + return 0; + } +} + +/*! + * Returns the number of bits per color component for the color + * component bits register + * + * @param pixel format + * + * @return Returns the number of bits per color component for + * the color component bits register. + */ +uint32_t imxdpuv1_get_colorcomponentbits(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + /* todo add NV12, NV16, YUYV, and UYVY */ + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + return + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x00); + case IMXDPUV1_PIX_FMT_NV12: + return + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x00); + + case IMXDPUV1_PIX_FMT_RGB565: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 5) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 11) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0); + + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_RGB32: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x0); + + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_AYUV: + return + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x08); + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format 0x%08x", __func__, fmt); + return 0; + } + return 0; +} + +/*! + * Returns the number of planes for the pixel format + * + * @param pixel format + * + * @return returns number of bytes per pixel or zero + * if the format is not matched. + */ +uint32_t imxdpuv1_get_planes(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_NV12: + return 2; + + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_ARGB32: + return 1; + default: + return 0; + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + } +} + +/*! + * Returns the color component bit position shifts + * + * @param pixel format + * + * @return returns the register setting for the + * colorcomponentshift register + * + */ +uint32_t imxdpuv1_get_colorcomponentshift(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + + case IMXDPUV1_PIX_FMT_NV12: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + + case IMXDPUV1_PIX_FMT_RGB565: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 5) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 6) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 5) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0); + case IMXDPUV1_PIX_FMT_YUYV: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + case IMXDPUV1_PIX_FMT_UYVY: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + /* 0xaaRRGGBB */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x18); + case IMXDPUV1_PIX_FMT_AYUV: + /* 0xVVUUYYAA */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x18) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00); + + case IMXDPUV1_PIX_FMT_ABGR32: + /* 0xRRGGBBAA */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x18) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00); + + case IMXDPUV1_PIX_FMT_ARGB32: + /* 0xBBGGRRAA */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x18) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00); + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + /* 0xaaBBGGRR or 0xaaUUVVYY */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x18); + default: + return 0; + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + } +} + +/*! + * Returns true is the format has local alpha + * + * @param pixel format + * + * @return Returns true is the format has local alpha + */ +uint32_t imxdpuv1_has_localalpha(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_RGBA32: + return IMXDPUV1_TRUE; + default: + return IMXDPUV1_FALSE; + } +} + +/*! + * Returns the bits per pixel + * + * @param pixel format + * + * @return returns number of bits per pixel or zero + * if the format is not matched. + */ +int imxdpuv1_bits_per_pixel(uint32_t fmt) +{ + int ret = 0; + switch (fmt) { + case IMXDPUV1_PIX_FMT_NV12: + ret = 8; + break; + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_YVYU: + ret = 16; + break; + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + ret = 24; + break; + + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_AYUV: + ret = 32; + break; + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format\n", __func__); + ret = 1; + break; + } + IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret); + + return ret; +} + +/*! + * Tests for YUV + * + * @param pixel format + * + * @return returns true if the format is YUV. + */ +static bool imxdpuv1_is_yuv(uint32_t fmt) +{ + int ret = IMXDPUV1_FALSE; + switch (fmt) { + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_NV12: + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_YUV444: + ret = IMXDPUV1_TRUE; + break; + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + ret = IMXDPUV1_FALSE; + break; + + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + ret = IMXDPUV1_FALSE; + break; + } + IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret); + + return ret; +} + +/*! + * Tests for RGB formats + * + * @param pixel format + * + * @return returns true if the format is any supported RGB + */ +bool imxdpuv1_is_rgb(uint32_t fmt) +{ + int ret = IMXDPUV1_FALSE; + switch (fmt) { + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_NV12: + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_GENERIC_32: + ret = IMXDPUV1_FALSE; + break; + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + ret = IMXDPUV1_TRUE; + break; + + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + ret = IMXDPUV1_FALSE; + break; + } + IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret); + + return ret; +} + +/*! + * Intializes buffers to be used for a channel + * + * @param imxdpuv1_id id of the diplay unit + * @param chan channel to use for this buffer + * @param stride total width in the buffer in pixels + * @param rot_mode rotatation mode + * @param phyaddr_0 buffer 0 address + * @param u_offset U offset + * @param v_offset V offset + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_init_channel_buffer( + int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t stride, + imxdpuv1_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, + uint32_t u_offset, + uint32_t v_offset) +{ + int ret = 0; + uint32_t b_off; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + int sub_idx = imxdpuv1_get_channel_subindex(chan); + bool enable_clip = IMXDPUV1_FALSE; + bool enable_buffer = IMXDPUV1_TRUE; + uint8_t enable_yuv = IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__OFF; + uint8_t input_select = IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__INACTIVE; + uint32_t fwidth; + uint32_t fheight; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + + b_off = id2blockoffset(get_channel_blk(chan)); + if (b_off == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0; + imxdpu->chan_data[chan_idx].u_offset = u_offset; + imxdpu->chan_data[chan_idx].v_offset = v_offset; + + /* update stride if provided */ + if (stride != 0) { + /* todo: check stride range */ + imxdpu->chan_data[chan_idx].stride = stride; + } + + /* common fetch setup */ + if (!is_store_chan(chan)) { + /* default horizontal scan + * todo: add support for vertical and warp scans + */ + if (sub_idx == 0) { + imxdpuv1_write(imxdpu, + b_off + + IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_OFFSET, + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH, + burst_param[IMXDPUV1_BURST_HORIZONTAL]. + len) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS, + burst_param[IMXDPUV1_BURST_HORIZONTAL].buffers)); + } + /* todo: Add range checking here */ + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = phyaddr_0; + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferattributes0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_BITSPERPIXEL, + imxdpuv1_bits_per_pixel( + imxdpu->chan_data[chan_idx].src_pixel_fmt)) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_STRIDE, + imxdpu->chan_data[chan_idx].stride - 1); + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferdimension0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINECOUNT, + imxdpu->chan_data[chan_idx].src_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINEWIDTH, + imxdpu->chan_data[chan_idx].src_width - 1); + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 = + imxdpuv1_get_colorcomponentbits( + imxdpu->chan_data[chan_idx].src_pixel_fmt); + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 = + imxdpuv1_get_colorcomponentshift( + imxdpu->chan_data[chan_idx].src_pixel_fmt); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.layeroffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_XOFFSET, + imxdpu->chan_data[chan_idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_YOFFSET, + imxdpu->chan_data[chan_idx].dest_top); + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowoffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_XOFFSET, + imxdpu->chan_data[chan_idx].clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_YOFFSET, + imxdpu->chan_data[chan_idx].clip_top); + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT, + imxdpu->chan_data[chan_idx].clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH, + imxdpu->chan_data[chan_idx].clip_width - 1); + if ((imxdpu->chan_data[chan_idx].clip_height != 0) && + (imxdpu->chan_data[chan_idx].clip_width != 0)) { + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT, + imxdpu->chan_data[chan_idx].clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH, + imxdpu->chan_data[chan_idx].clip_width - 1); + + enable_clip = IMXDPUV1_ENABLE; + } else { + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 = 0; + } + + imxdpu->chan_data[chan_idx].fetch_layer_prop.constantcolor0 = + imxdpu->chan_data[chan_idx].const_color; + + if (imxdpu->chan_data[chan_idx].phyaddr_0 == 0) { + enable_buffer = IMXDPUV1_FALSE; + } + if (imxdpuv1_is_yuv(imxdpu->chan_data[chan_idx].src_pixel_fmt)) { + /* TODO: need to get correct encoding range */ + enable_yuv = IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601; + } + } + + + if (is_fetch_decode_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch decode channel\n", __func__); + if (imxdpu->chan_data[chan_idx].use_eco_fetch) { + input_select = IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COMPPACK; + if (chan == IMXDPUV1_CHAN_01) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHECO0)); + } else if (chan == IMXDPUV1_CHAN_19) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHECO1)); + } + imxdpuv1_init_channel_buffer(imxdpuv1_id, + imxdpuv1_get_eco(chan), + stride, + rot_mode, + phyaddr_0, + u_offset, v_offset); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 = + (0x08 << IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT); + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 = + (0x00 << IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT); + + } /* else need to handle Alpha, Warp, CLUT ... */ + + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE, + enable_yuv) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE, + imxdpu->chan_data[chan_idx].use_global_alpha) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE, + imxdpu->chan_data[chan_idx].use_local_alpha); + + /* todo: handle all cases for control register */ + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE, + IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE) | + IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK | /* needed ?*/ + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR, 1) | /*needed for clip */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT, input_select)); /*needed for eco */ + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT, + imxdpu->chan_data[chan_idx].dest_height - + 1 /*fheight-1 */) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH, + imxdpu->chan_data[chan_idx].dest_width - + 1 /*fwidth-1 */)); + + imxdpuv1_write_block(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET, + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + } else if (is_fetch_layer_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer channel\n", __func__); + /* here the frame is shared for all sub layers so we use + the video mode dimensions. + fetch layer sub 1 must be setup first + todo: add a check so that any sub layer can set this */ + if (is_fetch_layer_sub_chan1(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer sub channel 1\n", + __func__); + fwidth = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].hlen; + fheight = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].vlen; + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_CONTROL_OFFSET, + IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK | /* needed ?*/ + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR, 1) + ); /*needed for eco */ + + imxdpuv1_write(imxdpu, + b_off + + IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT, + /*imxdpu->chan_data[chan_idx].dest_height-1 */ + fheight - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH, + /*imxdpu->chan_data[chan_idx].dest_width-1 */ + fwidth - 1)); + } + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE, + enable_yuv) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE, + imxdpu->chan_data[chan_idx].use_global_alpha) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE, + imxdpu->chan_data[chan_idx].use_local_alpha); + + imxdpuv1_write_block(imxdpu, + b_off + + IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET + + ((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)), + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + } else if (is_fetch_warp_chan(chan)) { + /* here the frame is shared for all sub layers so we use + the video mode dimensions. + fetch layer sub 1 must be setup first + todo: add a check so that any sub layer can set this */ + if (is_fetch_layer_sub_chan1(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer sub channel 1\n", + __func__); + fwidth = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].hlen; + fheight = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].vlen; + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_CONTROL_OFFSET, 0x700); + + imxdpuv1_write(imxdpu, + b_off + + IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT, + /*imxdpu->chan_data[chan_idx].dest_height-1 */ + fheight - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH, + /*imxdpu->chan_data[chan_idx].dest_width-1 */ + fwidth - 1)); + } + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE, + enable_yuv) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE, + imxdpu->chan_data[chan_idx].use_global_alpha) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE, + imxdpu->chan_data[chan_idx].use_local_alpha); + + imxdpuv1_write_block(imxdpu, + b_off + + IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET + + (IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx), + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + } else if (is_fetch_eco_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch eco setup\n", __func__); + if (imxdpu->chan_data[chan_idx].src_pixel_fmt == IMXDPUV1_PIX_FMT_NV12) { + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = phyaddr_0 + u_offset; + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferattributes0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_BITSPERPIXEL, 16) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_STRIDE, + imxdpu->chan_data[chan_idx].stride - 1); + + /* chroma resolution*/ + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferdimension0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINECOUNT, + imxdpu->chan_data[chan_idx].src_height / 2 - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINEWIDTH, + imxdpu->chan_data[chan_idx].src_width / 2 - 1); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x0); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip); + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHECO0_FRAMERESAMPLING_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX, 0x2) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY, 0x2) + ); + + /* todo: handle all cases for control register */ + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHECO0_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR, 1)); + + /* luma resolution */ + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT, + imxdpu->chan_data[chan_idx].dest_height - + 1 /*fheight-1 */) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH, + imxdpu->chan_data[chan_idx].dest_width - + 1 /*fwidth-1 */)); + + } /* else need to handle Alpha, Warp, CLUT ... */ + + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip); + + imxdpuv1_write_block(imxdpu, + b_off + IMXDPUV1_FETCHECO0_BASEADDRESS0_OFFSET, + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + + } else if (is_store_chan(chan)) { + imxdpu->chan_data[chan_idx].store_layer_prop.baseaddress0 = phyaddr_0; + imxdpu->chan_data[chan_idx].store_layer_prop.destbufferattributes0 = + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL, + imxdpuv1_bits_per_pixel( + imxdpu->chan_data[chan_idx].dest_pixel_fmt)) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE, + imxdpu->chan_data[chan_idx].stride-1); + imxdpu->chan_data[chan_idx].store_layer_prop.destbufferdimension0 = + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT, + imxdpu->chan_data[chan_idx].dest_height - 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH, + imxdpu->chan_data[chan_idx].dest_width - 1); + imxdpu->chan_data[chan_idx].store_layer_prop.colorcomponentbits0 = + imxdpuv1_get_colorcomponentbits( + imxdpu->chan_data[chan_idx].dest_pixel_fmt); + imxdpu->chan_data[chan_idx].store_layer_prop.colorcomponentshift0 = + imxdpuv1_get_colorcomponentshift( + imxdpu->chan_data[chan_idx].dest_pixel_fmt); + imxdpu->chan_data[chan_idx].store_layer_prop.frameoffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET, + -imxdpu->chan_data[chan_idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET, + -imxdpu->chan_data[chan_idx].dest_top); + + + imxdpuv1_write_block(imxdpu, + b_off + IMXDPUV1_STORE9_BASEADDRESS_OFFSET, + (void *)&imxdpu->chan_data[chan_idx]. + store_layer_prop, + sizeof(store_layer_setup_t) / 4); + + if ((imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_YUYV) || + (imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_YVYU) || + (imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_UYVY)) { + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_STORE9_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_CONTROL_RASTERMODE, + IMXDPUV1_STORE9_CONTROL_RASTERMODE__YUV422)); + } + + } + + /* imxdpuv1_dump_channel(imxdpuv1_id, chan); */ + + return ret; +} + +/*! + * Intializes a channel + * + * @param imxdpuv1_id id of the diplay unit + * @param chan channel to update + * @param phyaddr_0 physical address + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t imxdpuv1_update_channel_buffer( + int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + dma_addr_t phyaddr_0) +{ + int ret = 0; + uint32_t b_off; /* block offset for frame generator */ + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + + b_off = id2blockoffset(get_channel_blk(chan)); + if (b_off == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + if (imxdpu->chan_data[chan_idx].use_eco_fetch == IMXDPUV1_FALSE) { + imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0; + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = phyaddr_0; + } +#ifdef IMXDPUV1_VERSION_0 + if (is_store_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): store channel\n", __func__); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_STORE4_BASEADDRESS_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + + /* fixme: need to handle all pipline elements */ + imxdpuv1_write_irq(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_REQUEST, 1); + + return ret; + } +#endif + if (is_fetch_decode_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch decode channel\n", __func__); + if (imxdpu->chan_data[chan_idx].use_eco_fetch) { + imxdpuv1_update_channel_buffer(imxdpuv1_id, + imxdpuv1_get_eco(chan), + phyaddr_0); + } + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_MASK); + } else if (is_fetch_layer_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch layer channel\n", __func__); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_MASK); + } else if (is_fetch_warp_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch warp channel\n", __func__); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_MASK); + } else if (is_fetch_eco_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch eco channel\n", __func__); + + imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0 + imxdpu->chan_data[chan_idx].u_offset; + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = imxdpu->chan_data[chan_idx].phyaddr_0; + + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHECO0_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_MASK); + } + + return ret; +} + +/*! + * Intializes a channel + * + * @param imxdpuv1_id id of the diplay unit + * @param params pointer to channel parameters + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_init_channel(int8_t imxdpuv1_id, imxdpuv1_channel_params_t *params) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_t chan = params->common.chan; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + /* here we use the video mode for channel frame width, todo: we may need to + add a paramter for this */ + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + imxdpu->chan_data[chan_idx].chan = chan; + + memset(&imxdpu->chan_data[chan_idx].fetch_layer_prop, 0, + sizeof(fetch_layer_setup_t)); + imxdpu->chan_data[chan_idx].use_eco_fetch = IMXDPUV1_FALSE; + + if (is_fetch_decode_chan(chan)) { + IMXDPUV1_TRACE("%s(): decode channel setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_decode.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_decode.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_decode.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_decode.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_decode.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_decode.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_decode.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_decode.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_decode.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_decode.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_decode.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_decode.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_decode.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_decode.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_decode.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_decode.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_decode.disp_id; + + if (imxdpu->chan_data[chan_idx].use_video_proc == + IMXDPUV1_TRUE) { + imxdpu->chan_data[chan_idx].h_scale_factor = + params->fetch_decode.h_scale_factor; + imxdpu->chan_data[chan_idx].h_phase = + params->fetch_decode.h_phase; + imxdpu->chan_data[chan_idx].v_scale_factor = + params->fetch_decode.v_scale_factor; + imxdpu->chan_data[chan_idx].v_phase[0][0] = + params->fetch_decode.v_phase[0][0]; + imxdpu->chan_data[chan_idx].v_phase[0][1] = + params->fetch_decode.v_phase[0][1]; + imxdpu->chan_data[chan_idx].v_phase[1][0] = + params->fetch_decode.v_phase[1][0]; + imxdpu->chan_data[chan_idx].v_phase[1][1] = + params->fetch_decode.v_phase[1][1]; + } + + if (imxdpuv1_get_planes(imxdpu->chan_data[chan_idx].src_pixel_fmt) == 2) { + if (has_fetch_eco_chan(chan)) { + imxdpuv1_channel_params_t temp_params = *params; + + imxdpu->chan_data[chan_idx].use_eco_fetch = IMXDPUV1_TRUE; + temp_params.fetch_decode.chan = imxdpuv1_get_eco(params->fetch_decode.chan); + imxdpuv1_init_channel(imxdpuv1_id, &temp_params); + } else { + return -EINVAL; + } + } + } else if (is_fetch_layer_chan(chan)) { + IMXDPUV1_TRACE("%s(): layer channel setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_layer.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_layer.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_layer.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_layer.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_layer.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_layer.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_layer.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_layer.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_layer.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_layer.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_layer.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_layer.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_layer.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_layer.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_layer.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_layer.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_layer.disp_id; + + } else if (is_fetch_warp_chan(chan)) { + IMXDPUV1_TRACE("%s(): warp channel setup\n", __func__); + + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_warp.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_warp.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_warp.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_warp.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_warp.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_warp.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_warp.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_warp.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_warp.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_warp.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_warp.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_warp.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_warp.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_warp.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_warp.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_warp.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_warp.disp_id; + + } else if (is_fetch_eco_chan(chan)) { + + IMXDPUV1_TRACE("%s(): fetch eco channel setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_decode.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_decode.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_decode.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_decode.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_decode.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_decode.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_decode.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_decode.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_decode.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_decode.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_decode.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_decode.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_decode.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_decode.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_decode.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_decode.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_decode.disp_id; + + if (imxdpu->chan_data[chan_idx].use_video_proc == + IMXDPUV1_TRUE) { + imxdpu->chan_data[chan_idx].h_scale_factor = + params->fetch_decode.h_scale_factor; + imxdpu->chan_data[chan_idx].h_phase = + params->fetch_decode.h_phase; + imxdpu->chan_data[chan_idx].v_scale_factor = + params->fetch_decode.v_scale_factor; + imxdpu->chan_data[chan_idx].v_phase[0][0] = + params->fetch_decode.v_phase[0][0]; + imxdpu->chan_data[chan_idx].v_phase[0][1] = + params->fetch_decode.v_phase[0][1]; + imxdpu->chan_data[chan_idx].v_phase[1][0] = + params->fetch_decode.v_phase[1][0]; + imxdpu->chan_data[chan_idx].v_phase[1][1] = + params->fetch_decode.v_phase[1][1]; + } + + } else if (is_store_chan(chan)) { + IMXDPUV1_TRACE("%s(): store setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->store.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->store.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->store.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->store.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->store.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->store.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->store.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->store.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->store.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->store.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->store.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->store.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->store.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->store.const_color; + imxdpu->chan_data[chan_idx].source_id = + params->store.capture_id; + + if (imxdpu->chan_data[chan_idx].use_video_proc == + IMXDPUV1_TRUE) { + imxdpu->chan_data[chan_idx].h_scale_factor = + params->store.h_scale_factor; + imxdpu->chan_data[chan_idx].h_phase = + params->store.h_phase; + imxdpu->chan_data[chan_idx].v_scale_factor = + params->store.v_scale_factor; + imxdpu->chan_data[chan_idx].v_phase[0][0] = + params->store.v_phase[0][0]; + imxdpu->chan_data[chan_idx].v_phase[0][1] = + params->store.v_phase[0][1]; + imxdpu->chan_data[chan_idx].v_phase[1][0] = + params->store.v_phase[1][0]; + imxdpu->chan_data[chan_idx].v_phase[1][1] = + params->store.v_phase[1][1]; + } + + } else { + IMXDPUV1_TRACE("%s(): ERROR, invalid channel type!\n", __func__); + return -EINVAL; + } + + /* imxdpuv1_dump_channel(imxdpuv1_id, chan); */ + + return ret; +} + +/*! + * Dumps the fetch layer properties structure for a channel. + * + * @param layer id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_fetch_layer(fetch_layer_setup_t *layer) +{ + IMXDPUV1_PRINT("baseaddress 0x%08x\n" + "sourcebufferattributes 0x%08x\n" + "sourcebufferdimension h %d w %d\n" + "colorcomponentbits 0x%08x\n" + "colorcomponentshift 0x%08x\n" + "layeroffset y(top) %d x(left) %d\n" + "clipwindowoffset y(top) %d x(left) %d\n" + "clipwindowdimensions h %d w %d\n" + "constantcolor 0x%08x\n" + "layerproperty 0x%08x\n", + layer->baseaddress0, + layer->sourcebufferattributes0, + layer->sourcebufferdimension0 >> 16, + layer->sourcebufferdimension0 & 0x3fff, + layer->colorcomponentbits0, layer->colorcomponentshift0, + layer->layeroffset0 >> 16, layer->layeroffset0 & 0x3fff, + layer->clipwindowoffset0 >> 16, + layer->clipwindowoffset0 & 0x3fff, + layer->clipwindowdimensions0 >> 16, + layer->clipwindowdimensions0 & 0x3fff, + layer->constantcolor0, layer->layerproperty0); + return; +} +/*! + * Dumps the store layer properties structure for a channel. + * + * @param layer id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_store_layer(store_layer_setup_t *layer) +{ + IMXDPUV1_TRACE( + "baseaddress0 0x%08x\n" + "destbufferattributes0 0x%08x\n" + "destbufferdimension0 h %d w %d\n" + "frameoffset0 %d\n" + "colorcomponentbits0 0x%08x\n" + "colorcomponentshift0 0x%08x\n", + layer->baseaddress0, + layer->destbufferattributes0, + layer->destbufferdimension0 >> 16, layer->destbufferdimension0 & 0x3fff, + layer->frameoffset0, + layer->colorcomponentbits0, + layer->colorcomponentshift0); + return; +} + +/*! + * Dumps the pixel engine configuration status + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_layerblend(int8_t imxdpuv1_id) +{ + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS); + IMXDPUV1_TRACE("LAYERBLEND0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND0_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS); + IMXDPUV1_PRINT("LAYERBLEND1_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND1_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS); + IMXDPUV1_PRINT("LAYERBLEND2_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND2_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS); + IMXDPUV1_PRINT("LAYERBLEND3_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND3_LOCKSTATUS: 0x%08x\n", reg); +#ifdef IMXDPUV1_VERSION_0 + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_STATUS); + IMXDPUV1_PRINT("LAYERBLEND4_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND4_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_STATUS); + IMXDPUV1_PRINT("LAYERBLEND5_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND5_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_STATUS); + IMXDPUV1_PRINT("LAYERBLEND6_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND6_LOCKSTATUS: 0x%08x\n", reg); +#endif + return; +} + +/*! + * Dumps the pixel engine configuration status + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id) +{ + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST); + IMXDPUV1_PRINT("EXTDST0_REQUEST: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST); + IMXDPUV1_PRINT("EXTDST1_REQUEST: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST); + IMXDPUV1_PRINT("EXTDST4_REQUEST: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST); + IMXDPUV1_PRINT("EXTDST5_REQUEST: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATUS); + IMXDPUV1_PRINT("EXTDST0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATUS); + IMXDPUV1_PRINT("EXTDST1_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_STATUS); + IMXDPUV1_PRINT("EXTDST4_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_STATUS); + IMXDPUV1_PRINT("EXTDST5_STATUS: 0x%08x\n", reg); +#ifdef IMXDPUV1_VERSION_0 + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE2_STATUS); + IMXDPUV1_PRINT("FETCHDECODE2_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE3_STATUS); + IMXDPUV1_PRINT("FETCHDECODE3_STATUS: 0x%08x\n", reg); +#endif + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS); + IMXDPUV1_PRINT("FETCHWARP2_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS); + IMXDPUV1_PRINT("FETCHECO2_STATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS); + IMXDPUV1_PRINT("FETCHDECODE0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS); + IMXDPUV1_PRINT("FETCHECO0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS); + IMXDPUV1_PRINT("FETCHDECODE1_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS); + IMXDPUV1_PRINT("FETCHECO1_STATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS); + IMXDPUV1_PRINT("FETCHLAYER0_STATUS: 0x%08x\n", reg); +#ifdef IMXDPUV1_VERSION_0 + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHLAYER1_STATUS); + IMXDPUV1_PRINT("FETCHLAYER1_STATUS: 0x%08x\n", reg); +#endif + return; +} + +/*! + * Dumps the channel data + * + * @param imxdpuv1_id id of the diplay unit + * @param chan channel to dump + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + if (is_store_chan(chan)) { + IMXDPUV1_PRINT("chan_id 0x%x\n" + "src_pixel_fmt 0x%08x\n" + "src_width %d\n" + "src_height %d\n" + "clip_top %d(0x%04x)\n" + "clip_left %d(0x%04x)\n" + "clip_width %d\n" + "clip_height %d\n" + "stride %d\n" + "dest_pixel_fmt 0x%08x\n" + "dest_top %d(0x%04x)\n" + "dest_left %d(0x%04x)\n" + "dest_width %d\n" + "dest_height %d\n", + (uint32_t)imxdpu->chan_data[chan_idx].chan, + imxdpu->chan_data[chan_idx].src_pixel_fmt, + imxdpu->chan_data[chan_idx].src_width, + imxdpu->chan_data[chan_idx].src_height, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_width, + imxdpu->chan_data[chan_idx].clip_height, + imxdpu->chan_data[chan_idx].stride, + imxdpu->chan_data[chan_idx].dest_pixel_fmt, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_width, + imxdpu->chan_data[chan_idx].dest_height); + + IMXDPUV1_PRINT( + "use_video_proc %d\n" + "use_eco_fetch %d\n" + "interlaced %d\n" + "phyaddr_0 0x%08x\n" + "rot_mode %d\n" + "in_use %d\n" + "use_global_alpha %d\n" + "use_local_alpha %d\n", + imxdpu->chan_data[chan_idx].use_video_proc, + imxdpu->chan_data[chan_idx].use_eco_fetch, + imxdpu->chan_data[chan_idx].interlaced, + ptr_to_uint32(imxdpu->chan_data[chan_idx].phyaddr_0), + imxdpu->chan_data[chan_idx].rot_mode, + imxdpu->chan_data[chan_idx].in_use, + imxdpu->chan_data[chan_idx].use_global_alpha, + imxdpu->chan_data[chan_idx].use_local_alpha + ); + + imxdpuv1_dump_store_layer(&imxdpu->chan_data[chan_idx].store_layer_prop); + + } else { + IMXDPUV1_PRINT("chan_id 0x%x\n" + "src_pixel_fmt 0x%08x\n" + "src_width %d\n" + "src_height %d\n" + "clip_top %d(0x%04x)\n" + "clip_left %d(0x%04x)\n" + "clip_width %d\n" + "clip_height %d\n" + "stride %d\n" + "dest_pixel_fmt 0x%08x\n" + "dest_top %d(0x%04x)\n" + "dest_left %d(0x%04x)\n" + "dest_width %d\n" + "dest_height %d\n", + (uint32_t)imxdpu->chan_data[chan_idx].chan, + imxdpu->chan_data[chan_idx].src_pixel_fmt, + imxdpu->chan_data[chan_idx].src_width, + imxdpu->chan_data[chan_idx].src_height, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_width, + imxdpu->chan_data[chan_idx].clip_height, + imxdpu->chan_data[chan_idx].stride, + imxdpu->chan_data[chan_idx].dest_pixel_fmt, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_width, + imxdpu->chan_data[chan_idx].dest_height); + + + IMXDPUV1_PRINT( + "use_video_proc %d\n" + "use_eco_fetch %d\n" + "interlaced %d\n" + "phyaddr_0 0x%08x\n" + "u_offset 0x%08x\n" + "v_offset 0x%08x\n" + "rot_mode %d\n" + "in_use %d\n" + "use_global_alpha %d\n" + "use_local_alpha %d\n", + imxdpu->chan_data[chan_idx].use_video_proc, + imxdpu->chan_data[chan_idx].use_eco_fetch, + imxdpu->chan_data[chan_idx].interlaced, + ptr_to_uint32(imxdpu->chan_data[chan_idx].phyaddr_0), + imxdpu->chan_data[chan_idx].u_offset, + imxdpu->chan_data[chan_idx].v_offset, + imxdpu->chan_data[chan_idx].rot_mode, + imxdpu->chan_data[chan_idx].in_use, + imxdpu->chan_data[chan_idx].use_global_alpha, + imxdpu->chan_data[chan_idx].use_local_alpha + ); + + imxdpuv1_dump_fetch_layer(&imxdpu->chan_data[chan_idx].fetch_layer_prop); + } + return ret; +} + +/*! + * Shows the interrupt status registers + * + * @param id of the diplay unit + * + */ +void imxdpuv1_dump_int_stat(int8_t imxdpuv1_id) +{ + int i; + struct imxdpuv1_soc *imxdpu; + uint32_t reg; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0 + + (i * 4)); + IMXDPUV1_PRINT("USERINTERRUPTMASK%d: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0 + + (i * 4)); + IMXDPUV1_PRINT("USERINTERRUPTENABLE%d: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0 + + (i * 4)); + IMXDPUV1_PRINT("USERINTERRUPTSTATUS%d: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTENABLE0 + (i * 4)); + IMXDPUV1_PRINT("INTERRUPTENABLE%i: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTSTATUS0 + (i * 4)); + IMXDPUV1_PRINT("INTERRUPTSTATUS%i: 0x%08x\n", i, reg); + } +} diff --git a/drivers/video/imxdpuv1_be.h b/drivers/video/imxdpuv1_be.h new file mode 100644 index 00000000000..a004bf82447 --- /dev/null +++ b/drivers/video/imxdpuv1_be.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMXDPUV1_BE_H +#define IMXDPUV1_BE_H + +struct fetch_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t burst_buf; + uint32_t buf_address; + uint32_t buf_attributes; + uint32_t buf_dimension; + uint32_t color_bits; + uint32_t color_shift; + uint32_t layer_offset; + uint32_t clip_offset; + uint32_t clip_dimension; + uint32_t const_color; + uint32_t layer_property; + uint32_t frame_dimension; + uint32_t frame_resample; +}; + +struct store_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t burst_buf; + uint32_t buf_address; + uint32_t buf_attributes; + uint32_t buf_dimension; + uint32_t frame_offset; + uint32_t color_bits; + uint32_t color_shift; +}; +struct rop_unit { + uint32_t in_pipeline; + uint32_t control; +}; +struct matrix_unit { + uint32_t in_pipeline; + uint32_t control; +}; +struct hscaler_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t setup1; + uint32_t setup2; +}; +struct vscaler_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t setup1; + uint32_t setup2; + uint32_t setup3; + uint32_t setup4; + uint32_t setup5; +}; +struct blitblend_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t const_color; + uint32_t red_func; + uint32_t green_func; + uint32_t blue_func; + uint32_t alpha_func; + uint32_t blend_mode1; + uint32_t blend_mode2; +}; +struct engcfg_unit { + uint32_t fetchpersp9_dynamic; + uint32_t fetchdecode9_dynamic; + uint32_t rop9_dynamic; + uint32_t matrix9_dynamic; + uint32_t hscaler9_dynamic; + uint32_t vscaler9_dynamic; + uint32_t blitblend9_dynamic; + uint32_t store9_dynamic; +}; + +struct be_blit_cfg { + struct fetch_unit fetch_decode; + struct fetch_unit fetch_persp; + struct fetch_unit fetch_eco; + struct store_unit store; + struct rop_unit rop; + struct matrix_unit matrix; + struct hscaler_unit hscaler; + struct vscaler_unit vscaler; + struct blitblend_unit blitblend; + struct engcfg_unit engcfg; +}; + +/* PRIVATE DATA */ +struct imxdpuv1_info { + /*reg */ + void __iomem *base; +}; + +#define IMXDPUV1_IOC_MAGIC 'i' +#define IMXDPUV1_IOC_BLIT _IOW(IMXDPUV1_IOC_MAGIC, 1, struct be_blit_cfg) +#define IMXDPUV1_IOC_WAIT _IO(IMXDPUV1_IOC_MAGIC, 2) + +void imxdpuv1_be_irq_handler(int8_t imxdpuv1_id, int8_t irq); +int imxdpuv1_be_init(int8_t imxdpuv1_id, void __iomem *imxdpuv1_base); +int imxdpuv1_be_blit(struct imxdpuv1_info *imxdpu, struct be_blit_cfg *cfg); +int imxdpuv1_be_wait_shadow_load(struct imxdpuv1_info *imxdpu); +int imxdpuv1_be_wait_complete(struct imxdpuv1_info *imxdpu); +int imxdpuv1_be_load(struct imxdpuv1_info *imxdpu, void __user *p); +int imxdpuv1_be_wait(struct imxdpuv1_info *imxdpu); + +#endif diff --git a/drivers/video/imxdpuv1_private.h b/drivers/video/imxdpuv1_private.h new file mode 100644 index 00000000000..b874c38b47e --- /dev/null +++ b/drivers/video/imxdpuv1_private.h @@ -0,0 +1,470 @@ +/* + * Copyright (c) 2005-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Instance: imxdpuv1_private.h */ +#ifndef IMXDPUV1_PRIVATE_H +#define IMXDPUV1_PRIVATE_H + +#include +#include + +#include +#include "imxdpuv1.h" + +typedef enum { + IMXDPUV1_BURST_UNKNOWN = 0, + IMXDPUV1_BURST_LEFT_RIGHT_DOWN, + IMXDPUV1_BURST_HORIZONTAL, + IMXDPUV1_BURST_VERTICAL, + IMXDPUV1_BURST_FREE, +} imxdpuv1_burst_t; + +#define INTSTAT0_BIT(__bit__) (1U<<(__bit__)) +#define INTSTAT1_BIT(__bit__) (1U<<((__bit__)-32)) +#define INTSTAT2_BIT(__bit__) (1U<<((__bit__)-64)) + +struct imxdpuv1_irq_node { + int(*handler) (int, void *); + const char *name; + void *data; + uint32_t flags; +}; + +/* Generic definitions that are common to many registers */ +#define IMXDPUV1_COLOR_BITSALPHA0_MASK 0xFU +#define IMXDPUV1_COLOR_BITSALPHA0_SHIFT 0U +#define IMXDPUV1_COLOR_BITSBLUE0_MASK 0xF00U +#define IMXDPUV1_COLOR_BITSBLUE0_SHIFT 8U +#define IMXDPUV1_COLOR_BITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_COLOR_BITSGREEN0_SHIFT 16U +#define IMXDPUV1_COLOR_BITSRED0_MASK 0xF000000U +#define IMXDPUV1_COLOR_BITSRED0_SHIFT 24U + +#define IMXDPUV1_COLOR_SHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_COLOR_SHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_COLOR_SHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_COLOR_SHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_COLOR_SHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_COLOR_SHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_COLOR_SHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_COLOR_SHIFTRED0_SHIFT 24U + +#define IMXDPUV1_COLOR_CONSTALPHA_MASK 0xFFU +#define IMXDPUV1_COLOR_CONSTALPHA_SHIFT 0U +#define IMXDPUV1_COLOR_CONSTBLUE_MASK 0xFF00U +#define IMXDPUV1_COLOR_CONSTBLUE_SHIFT 8U +#define IMXDPUV1_COLOR_CONSTGREEN_MASK 0xFF0000U +#define IMXDPUV1_COLOR_CONSTGREEN_SHIFT 16U +#define IMXDPUV1_COLOR_CONSTRED_MASK 0xFF000000U +#define IMXDPUV1_COLOR_CONSTRED_SHIFT 24U + +/* these are common for fetch but not store */ +#define IMXDPUV1_BUFF_ATTR_STRIDE_MASK 0xFFFFU +#define IMXDPUV1_BUFF_ATTR_STRIDE_SHIFT 0U +#define IMXDPUV1_BUFF_ATTR_BITSPERPIXEL_MASK 0x3F0000U +#define IMXDPUV1_BUFF_ATTR_BITSPERPIXEL_SHIFT 16U + +#define IMXDPUV1_BUFF_DIMEN_LINECOUNT_SHIFT 16U +#define IMXDPUV1_BUFF_DIMEN_LINEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_BUFF_DIMEN_LINEWIDTH_SHIFT 0U +#define IMXDPUV1_BUFF_DIMEN_LINECOUNT_MASK 0x3FFF0000U + +#define IMXDPUV1_LAYER_XOFFSET_MASK 0x7FFFU +#define IMXDPUV1_LAYER_XOFFSET_SHIFT 0U +#define IMXDPUV1_LAYER_XSBIT_MASK 0x4000U +#define IMXDPUV1_LAYER_XSBIT_SHIFT 0U + +#define IMXDPUV1_LAYER_YOFFSET_MASK 0x7FFF0000U +#define IMXDPUV1_LAYER_YOFFSET_SHIFT 16U +#define IMXDPUV1_LAYER_YSBIT_MASK 0x4000U +#define IMXDPUV1_LAYER_YSBIT_SHIFT 16U + +#define IMXDPUV1_CLIP_XOFFSET_MASK 0x7FFFU +#define IMXDPUV1_CLIP_XOFFSET_SHIFT 0U +#define IMXDPUV1_CLIP_YOFFSET_MASK 0x7FFF0000U +#define IMXDPUV1_CLIP_YOFFSET_SHIFT 16U + +#define IMXDPUV1_CLIP_WIDTH_MASK 0x3FFFU +#define IMXDPUV1_CLIP_WIDTH_SHIFT 0U +#define IMXDPUV1_CLIP_HEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CLIP_HEIGHT_SHIFT 16U + +#define IMXDPUV1_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_EMPTYFRAME_SHIFT 31U + +#define IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE 0U +#define IMXDPUV1_PIXENGCFG_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_SRC_SEL_SHIFT 0U + +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE 0U + +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL_SHIFT 8U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE 0U + +#define IMXDPUV1_PIXENGCFG_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_CLKEN_SHIFT 24U +/* Field Value: _CLKEN__DISABLE, Clock for block is disabled */ +#define IMXDPUV1_PIXENGCFG_CLKEN__DISABLE 0U +/* Field Value: _CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC 0x1U +/* Field Value: _CLKEN__FULL, Clock for block is without gating */ +#define IMXDPUV1_PIXENGCFG_CLKEN__FULL 0x3U + + +/* Register: IMXDPUV1_LayerProperty0 Common Bits */ +#define IMXDPUV1_LAYERPROPERTY_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_LAYERPROPERTY_RESET_VALUE 0x80000100U +#define IMXDPUV1_LAYERPROPERTY_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERPROPERTY_PALETTEENABLE_MASK 0x1U +#define IMXDPUV1_LAYERPROPERTY_PALETTEENABLE_SHIFT 0U +#define IMXDPUV1_LAYERPROPERTY_TILEMODE_MASK 0x30U +#define IMXDPUV1_LAYERPROPERTY_TILEMODE_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE_MASK 0x100U +#define IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE_SHIFT 8U +#define IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE_MASK 0x200U +#define IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE_SHIFT 9U +#define IMXDPUV1_LAYERPROPERTY_ALPHAMASKENABLE_MASK 0x400U +#define IMXDPUV1_LAYERPROPERTY_ALPHAMASKENABLE_SHIFT 10U +#define IMXDPUV1_LAYERPROPERTY_ALPHATRANSENABLE_MASK 0x800U +#define IMXDPUV1_LAYERPROPERTY_ALPHATRANSENABLE_SHIFT 11U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHASRCENABLE_MASK 0x1000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHASRCENABLE_SHIFT 12U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHACONSTENABLE_MASK 0x2000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHACONSTENABLE_SHIFT 13U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHAMASKENABLE_MASK 0x4000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHAMASKENABLE_SHIFT 14U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHATRANSENABLE_MASK 0x8000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHATRANSENABLE_SHIFT 15U +#define IMXDPUV1_LAYERPROPERTY_PREMULCONSTRGB_MASK 0x10000U +#define IMXDPUV1_LAYERPROPERTY_PREMULCONSTRGB_SHIFT 16U +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE_MASK 0x60000U +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU709 0x3U +#define IMXDPUV1_LAYERPROPERTY_GAMMAREMOVEENABLE_MASK 0x100000U +#define IMXDPUV1_LAYERPROPERTY_GAMMAREMOVEENABLE_SHIFT 20U +#define IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_MASK 0x40000000U +#define IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_SHIFT 30U +#define IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE_MASK 0x80000000U +#define IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE_SHIFT 31U + +typedef struct { + /* Source buffer base address of layer 0. */ + uint32_t baseaddress0; + /* Source buffer attributes for layer 0. */ + uint32_t sourcebufferattributes0; + /* Source buffer dimension of layer 0. */ + uint32_t sourcebufferdimension0; + /* Size of color components for RGB, YUV and index formats (layer 0). */ + uint32_t colorcomponentbits0; + /* Bit position of color components for RGB, YUV and index + formats (layer 0). */ + uint32_t colorcomponentshift0; + /* Position of layer 0 within the destination frame. */ + uint32_t layeroffset0; + /* Clip window position for layer 0. */ + uint32_t clipwindowoffset0; + /* Clip window size for layer 0. */ + uint32_t clipwindowdimensions0; + /* Constant color for layer 0. */ + uint32_t constantcolor0; + /* Common properties of layer 0. */ + uint32_t layerproperty0; +} fetch_layer_setup_t; + +typedef struct { + /* Destination buffer base address of layer 0. */ + uint32_t baseaddress0; + /* Destination buffer attributes for layer 0. */ + uint32_t destbufferattributes0; + /* Source buffer dimension of layer 0. */ + uint32_t destbufferdimension0; + /* Frame offset of layer 0. */ + uint32_t frameoffset0; + /* Size of color components for RGB, YUV and index formats (layer 0). */ + uint32_t colorcomponentbits0; + /* Bit position of color components for RGB, YUV and index + formats (layer 0). */ + uint32_t colorcomponentshift0; +} store_layer_setup_t; + +typedef enum { + IMXDPUV1_SHDLD_IDX_DISP0 = (0), + IMXDPUV1_SHDLD_IDX_DISP1 = (1), + IMXDPUV1_SHDLD_IDX_CONST0 = (2), /* IMXDPUV1_ID_CONSTFRAME0 */ + IMXDPUV1_SHDLD_IDX_CONST1 = (3), /* IMXDPUV1_ID_CONSTFRAME1 */ + IMXDPUV1_SHDLD_IDX_CHAN_00 = (4), /* IMXDPUV1_ID_FETCHDECODE2 */ + IMXDPUV1_SHDLD_IDX_CHAN_01 = (5), /* IMXDPUV1_ID_FETCHDECODE0 */ + IMXDPUV1_SHDLD_IDX_CHAN_02 = (6), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_03 = (7), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_04 = (8), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_05 = (9), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_06 = (10), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_07 = (11), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_08 = (12), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_09 = (13), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_10 = (14), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_11 = (15), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_12 = (16), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_13 = (17), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_14 = (18), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_15 = (19), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_16 = (20), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_17 = (21), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_18 = (22), /* IMXDPUV1_ID_FETCHDECODE3 */ + IMXDPUV1_SHDLD_IDX_CHAN_19 = (23), /* IMXDPUV1_ID_FETCHDECODE1 */ + IMXDPUV1_SHDLD_IDX_CHAN_20 = (24), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_21 = (25), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_22 = (26), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_23 = (27), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_24 = (28), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_25 = (29), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_26 = (30), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_27 = (31), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_28 = (32), /* IMXDPUV1_ID_FETCHECO0*/ + IMXDPUV1_SHDLD_IDX_CHAN_29 = (33), /* IMXDPUV1_ID_FETCHECO1*/ + IMXDPUV1_SHDLD_IDX_CHAN_30 = (34), /* IMXDPUV1_ID_FETCHECO2*/ + IMXDPUV1_SHDLD_IDX_MAX = (35), +} imxdpuv1_shadow_load_index_t; + +typedef struct { + bool prim_sync_state; + bool sec_sync_state; + uint32_t prim_sync_count; + uint32_t sec_sync_count; + uint32_t skew_error_count; + uint32_t prim_fifo_empty_count; + uint32_t sec_fifo_empty_count; + uint32_t frame_count; +} frame_gen_stats_t; + +/*! + * Definition of IMXDPU channel structure + */ +typedef struct { + int8_t disp_id; /* Iris instance id of "owner" */ + + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + int16_t src_top; + int16_t src_left; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint16_t const_color; + + uint32_t h_scale_factor; /* downscaling out/in */ + uint32_t h_phase; + uint32_t v_scale_factor; /* downscaling out/in */ + uint32_t v_phase[2][2]; + + bool use_video_proc; + bool interlaced; + bool use_eco_fetch; + bool use_global_alpha; + bool use_local_alpha; + + /* note: dma_addr_t changes for 64-bit arch */ + dma_addr_t phyaddr_0; + + uint32_t u_offset; + uint32_t v_offset; + + uint8_t blend_layer; + uint8_t destination_stream; + uint8_t source_id; + + imxdpuv1_rotate_mode_t rot_mode; + + /* todo add features sub-windows, upscaling, warping */ + fetch_layer_setup_t fetch_layer_prop; + store_layer_setup_t store_layer_prop; + + bool in_use; + + /* todo: add channel features */ +} chan_private_t; + +typedef union { + struct { + uint8_t request; + uint8_t processing; + uint8_t complete; + uint8_t trys; + } state; + uint32_t word; +} imxdpuv1_shadow_state_t; + +/* PRIVATE DATA */ +struct imxdpuv1_soc { + int8_t devtype; + int8_t online; + uint32_t enabled_int[3]; + struct imxdpuv1_irq_node irq_list[IMXDPUV1_INTERRUPT_MAX]; + + struct device *dev; + struct imxdpuv1_videomode video_mode[IMXDPUV1_NUM_DI]; + struct imxdpuv1_videomode capture_mode[IMXDPUV1_NUM_CI]; + frame_gen_stats_t fgen_stats[IMXDPUV1_NUM_DI]; + uint32_t irq_count; + + + /* + * Bypass reset to avoid display channel being + * stopped by probe since it may starts to work + * in bootloader. + */ + int8_t bypass_reset; + + /* todo: need to decide where the locking is implemented */ + + /*clk*/ + + /*irq*/ + + /*reg*/ + void __iomem *base; + + /*use count*/ + imxdpuv1_layer_t blend_layer[IMXDPUV1_LAYER_MAX]; + chan_private_t chan_data[IMXDPUV1_CHAN_IDX_MAX]; + + uint8_t shadow_load_pending[IMXDPUV1_NUM_DI][IMXDPUV1_SHDLD_IDX_MAX]; + imxdpuv1_shadow_state_t shadow_load_state[IMXDPUV1_NUM_DI][IMXDPUV1_SHDLD_IDX_MAX]; +}; + + + +/* PRIVATE FUNCTIONS */ +#ifdef ENABLE_IMXDPUV1_TRACE_REG +uint32_t _imxdpuv1_read(struct imxdpuv1_soc *dpu, u32 offset, char *file, int line); +#define imxdpuv1_read(_inst_, _offset_) _imxdpuv1_read(_inst_, _offset_, __FILE__, __LINE__) +#else +static inline uint32_t imxdpuv1_read(struct imxdpuv1_soc *dpu, uint32_t offset) +{ + return __raw_readl(dpu->base + offset); +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_READ +uint32_t _imxdpuv1_read_irq(struct imxdpuv1_soc *dpu, u32 offset, char *file, int line); +#define imxdpuv1_read_irq(_inst_, _offset_) _imxdpuv1_read_irq(_inst_, _offset_, __FILE__, __LINE__) +#else +static inline uint32_t imxdpuv1_read_irq(struct imxdpuv1_soc *dpu, uint32_t offset) +{ + return __raw_readl(dpu->base + offset); +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_REG +void _imxdpuv1_write(struct imxdpuv1_soc *dpu, uint32_t value, uint32_t offset, char *file, int line); +#define imxdpuv1_write(_inst_, _value_, _offset_) _imxdpuv1_write(_inst_, _value_, _offset_, __FILE__, __LINE__) +#else +static inline void imxdpuv1_write(struct imxdpuv1_soc *dpu, uint32_t offset, uint32_t value) +{ + __raw_writel(value, dpu->base + offset); +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_WRITE +void _imxdpuv1_write_irq(struct imxdpuv1_soc *dpu, uint32_t value, uint32_t offset, char *file, int line); +#define imxdpuv1_write_irq(_inst_, _value_, _offset_) _imxdpuv1_write_irq(_inst_, _value_, _offset_, __FILE__, __LINE__) +#else +static inline void imxdpuv1_write_irq(struct imxdpuv1_soc *dpu, uint32_t offset, uint32_t value) +{ + __raw_writel(value, dpu->base + offset); +} +#endif + +void _imxdpuv1_write_block(struct imxdpuv1_soc *imxdpu, uint32_t offset, void *values, uint32_t cnt, char *file, int line); +#define imxdpuv1_write_block(_inst_, _values_, _offset_, _cnt_) _imxdpuv1_write_block(_inst_, _values_, _offset_, _cnt_, __FILE__, __LINE__) + +/* mapping of RGB, Tcon, or static values to output */ +#define IMXDPUV1_TCON_MAPBIT__RGB(_x_) ((_x_)) +#define IMXDPUV1_TCON_MAPBIT__Tsig(_x_) ((_x_) + 30) +#define IMXDPUV1_TCON_MAPBIT__HIGH 42U +#define IMXDPUV1_TCON_MAPBIT__LOW 43U + +/* these match the bit definitions for the shadlow load + request registers + */ +typedef enum { + IMXDPUV1_SHLDREQID_FETCHDECODE9 = 0, + IMXDPUV1_SHLDREQID_FETCHPERSP9, + IMXDPUV1_SHLDREQID_FETCHECO9, + IMXDPUV1_SHLDREQID_CONSTFRAME0, + IMXDPUV1_SHLDREQID_CONSTFRAME4, + IMXDPUV1_SHLDREQID_CONSTFRAME1, + IMXDPUV1_SHLDREQID_CONSTFRAME5, +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_SHLDREQID_EXTSRC4, + IMXDPUV1_SHLDREQID_EXTSRC5, + IMXDPUV1_SHLDREQID_FETCHDECODE2, + IMXDPUV1_SHLDREQID_FETCHDECODE3, +#endif + IMXDPUV1_SHLDREQID_FETCHWARP2, + IMXDPUV1_SHLDREQID_FETCHECO2, + IMXDPUV1_SHLDREQID_FETCHDECODE0, + IMXDPUV1_SHLDREQID_FETCHECO0, + IMXDPUV1_SHLDREQID_FETCHDECODE1, + IMXDPUV1_SHLDREQID_FETCHECO1, + IMXDPUV1_SHLDREQID_FETCHLAYER0, +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_SHLDREQID_FETCHLAYER1, + IMXDPUV1_SHLDREQID_EXTSRC0, + IMXDPUV1_SHLDREQID_EXTSRC1 +#endif +} imxdpuv1_shadow_load_req_t; + +#define IMXDPUV1_PIXENGCFG_DIVIDER_RESET 0x80 + +#endif /* IMXDPUV1_PRIVATE_H */ + diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 889085aa767..c09c22201db 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -224,15 +224,69 @@ static struct clk ipu_clk = { #define CONFIG_SYS_LDB_CLOCK 65000000 #endif -static struct clk ldb_clk = { +#if defined(CONFIG_MX6) || defined(CONFIG_MX53) +static int clk_ldb_clk_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void clk_ldb_clk_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static struct clk ldb_clk[2] = { + { .name = "ldb_clk", + .id = 0, .rate = CONFIG_SYS_LDB_CLOCK, +#ifdef CONFIG_MX6 + .enable_reg = (u32 *)(CCM_BASE_ADDR + + offsetof(struct mxc_ccm_reg, CCGR3)), + .enable_shift = MXC_CCM_CCGR3_LDB_DI0_OFFSET, +#else + .enable_reg = (u32 *)(CCM_BASE_ADDR + + offsetof(struct mxc_ccm_reg, CCGR6)), + .enable_shift = MXC_CCM_CCGR6_LDB_DI0_OFFSET, +#endif + .enable = clk_ldb_clk_enable, + .disable = clk_ldb_clk_disable, .usecount = 0, + }, { + .name = "ldb_clk", + .id = 1, + .rate = CONFIG_SYS_LDB_CLOCK, +#ifdef CONFIG_MX6 + .enable_reg = (u32 *)(CCM_BASE_ADDR + + offsetof(struct mxc_ccm_reg, CCGR3)), + .enable_shift = MXC_CCM_CCGR3_LDB_DI1_OFFSET, +#else + .enable_reg = (u32 *)(CCM_BASE_ADDR + + offsetof(struct mxc_ccm_reg, CCGR6)), + .enable_shift = MXC_CCM_CCGR6_LDB_DI1_OFFSET, +#endif + .enable = clk_ldb_clk_enable, + .disable = clk_ldb_clk_disable, + .usecount = 0, + } }; +#endif /* Globals */ struct clk *g_ipu_clk; -struct clk *g_ldb_clk; +#if defined(CONFIG_MX6) || defined(CONFIG_MX53) +struct clk *g_ldb_clk[2]; +#endif unsigned char g_ipu_clk_enabled; struct clk *g_di_clk[2]; struct clk *g_pixel_clk[2]; @@ -391,8 +445,10 @@ static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) if (parent == g_ipu_clk) di_gen &= ~DI_GEN_DI_CLK_EXT; - else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk) +#if defined(CONFIG_MX6) || defined(CONFIG_MX53) + else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk[clk->id]) di_gen |= DI_GEN_DI_CLK_EXT; +#endif else return -EINVAL; @@ -493,8 +549,12 @@ int ipu_probe(void) g_ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q; #endif debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk)); - g_ldb_clk = &ldb_clk; - debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk)); +#if defined(CONFIG_MX6) || defined(CONFIG_MX53) + g_ldb_clk[0] = &ldb_clk[0]; + g_ldb_clk[1] = &ldb_clk[1]; + debug("ldb_clk[0] = %u\n", clk_get_rate(g_ldb_clk[0])); + debug("ldb_clk[1] = %u\n", clk_get_rate(g_ldb_clk[1])); +#endif ipu_reset(); clk_set_parent(g_pixel_clk[0], g_ipu_clk); @@ -1255,7 +1315,8 @@ ipu_color_space_t format_to_colorspace(uint32_t fmt) /* should be removed when clk framework is availiable */ int ipu_set_ldb_clock(int rate) { - ldb_clk.rate = rate; + ldb_clk[0].rate = rate; + ldb_clk[1].rate = rate; return 0; } diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c index 47d741796e9..8b3b82d8734 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@ -6,7 +6,7 @@ * * Linux IPU driver for MX51: * - * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. + * (C) Copyright 2005-2016 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -48,7 +48,9 @@ static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23; int g_di1_tvout; extern struct clk *g_ipu_clk; -extern struct clk *g_ldb_clk; +#if defined(CONFIG_MX6) || defined(CONFIG_MX53) +extern struct clk *g_ldb_clk[2]; +#endif extern struct clk *g_di_clk[2]; extern struct clk *g_pixel_clk[2]; @@ -643,6 +645,9 @@ void ipu_dp_dc_enable(ipu_channel_t channel) __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); clk_enable(g_pixel_clk[di]); +#if defined(CONFIG_MX6) || defined(CONFIG_MX53) + clk_enable(g_ldb_clk[di]); +#endif } static unsigned char dc_swap; @@ -733,6 +738,9 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) /* Clock is already off because it must be done quickly, but we need to fix the ref count */ clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]); +#if defined(CONFIG_MX6) || defined(CONFIG_MX53) + clk_disable(g_ldb_clk[g_dc_di_assignment[dc_chan]]); +#endif } } @@ -883,7 +891,9 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, udelay(10000); } } - clk_set_parent(g_pixel_clk[disp], g_ldb_clk); +#if defined(CONFIG_MX6) || defined(CONFIG_MX53) + clk_set_parent(g_pixel_clk[disp], g_ldb_clk[disp]); +#endif } else { if (clk_get_usecount(g_pixel_clk[disp]) != 0) clk_set_parent(g_pixel_clk[disp], g_ipu_clk); diff --git a/drivers/video/mipi_dsi_northwest.c b/drivers/video/mipi_dsi_northwest.c new file mode 100644 index 00000000000..7817aa4e254 --- /dev/null +++ b/drivers/video/mipi_dsi_northwest.c @@ -0,0 +1,938 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "mipi_dsi_northwest_regs.h" +#include +#include +#include +#include + +#define MIPI_LCD_SLEEP_MODE_DELAY (120) +#define MIPI_FIFO_TIMEOUT 250000 /* 250ms */ +#define PS2KHZ(ps) (1000000000UL / (ps)) + +#define DIV_ROUND_CLOSEST_ULL(x, divisor)( \ +{ \ + typeof(divisor) __d = divisor; \ + unsigned long long _tmp = (x) + (__d) / 2; \ + do_div(_tmp, __d); \ + _tmp; \ +} \ +) + +enum mipi_dsi_mode { + DSI_COMMAND_MODE, + DSI_VIDEO_MODE +}; + +#define DSI_LP_MODE 0 +#define DSI_HS_MODE 1 + +enum mipi_dsi_payload { + DSI_PAYLOAD_CMD, + DSI_PAYLOAD_VIDEO, +}; + +/* + * mipi-dsi northwest driver information structure, holds useful data for the driver. + */ +struct mipi_dsi_northwest_info { + u32 mmio_base; + u32 sim_base; + int enabled; + struct mipi_dsi_client_dev *dsi_panel_dev; + struct mipi_dsi_client_driver *dsi_panel_drv; + struct fb_videomode mode; +}; + +struct pll_divider { + unsigned int cm; /* multiplier */ + unsigned int cn; /* predivider */ + unsigned int co; /* outdivider */ +}; + +/** + * 'CM' value to 'CM' reigister config value map + * 'CM' = [16, 255]; + */ +static unsigned int cm_map_table[240] = { + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, /* 16 ~ 23 */ + 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, /* 24 ~ 31 */ + + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, /* 32 ~ 39 */ + 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, /* 40 ~ 47 */ + + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, /* 48 ~ 55 */ + 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, /* 56 ~ 63 */ + + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, /* 64 ~ 71 */ + 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, /* 72 ~ 79 */ + + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, /* 80 ~ 87 */ + 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, /* 88 ~ 95 */ + + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, /* 96 ~ 103 */ + 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, /* 104 ~ 111 */ + + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, /* 112 ~ 119 */ + 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, /* 120 ~ 127 */ + + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* 128 ~ 135 */ + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, /* 136 ~ 143 */ + + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* 144 ~ 151 */ + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 152 ~ 159 */ + + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, /* 160 ~ 167 */ + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, /* 168 ~ 175 */ + + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, /* 176 ~ 183 */ + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, /* 184 ~ 191 */ + + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, /* 192 ~ 199 */ + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, /* 200 ~ 207 */ + + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, /* 208 ~ 215 */ + 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, /* 216 ~ 223 */ + + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, /* 224 ~ 231 */ + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, /* 232 ~ 239 */ + + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, /* 240 ~ 247 */ + 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f /* 248 ~ 255 */ +}; + +/** + * map 'CN' value to 'CN' reigister config value + * 'CN' = [1, 32]; + */ +static unsigned int cn_map_table[32] = { + 0x1f, 0x00, 0x10, 0x18, 0x1c, 0x0e, 0x07, 0x13, /* 1 ~ 8 */ + 0x09, 0x04, 0x02, 0x11, 0x08, 0x14, 0x0a, 0x15, /* 9 ~ 16 */ + 0x1a, 0x1d, 0x1e, 0x0f, 0x17, 0x1b, 0x0d, 0x16, /* 17 ~ 24 */ + 0x0b, 0x05, 0x12, 0x19, 0x0c, 0x06, 0x03, 0x01 /* 25 ~ 32 */ +}; + +/** + * map 'CO' value to 'CO' reigister config value + * 'CO' = { 1, 2, 4, 8 }; + */ +static unsigned int co_map_table[4] = { + 0x0, 0x1, 0x2, 0x3 +}; + +unsigned long gcd(unsigned long a, unsigned long b) +{ + unsigned long r = a | b; + + if (!a || !b) + return r; + + /* Isolate lsbit of r */ + r &= -r; + + while (!(b & r)) + b >>= 1; + if (b == r) + return r; + + for (;;) { + while (!(a & r)) + a >>= 1; + if (a == r) + return r; + if (a == b) + return a; + + if (a < b) + swap(a, b); + a -= b; + a >>= 1; + if (a & r) + a += b; + a >>= 1; + } +} + + +/** + * board_mipi_panel_reset - give a reset cycle for mipi dsi panel + * + * Target board specific, like use gpio to reset the dsi panel + * Machine board file overrides board_mipi_panel_reset + * + * Return: 0 Success + */ +int __weak board_mipi_panel_reset(void) +{ + return 0; +} + +/** + * board_mipi_panel_shutdown - Shut down the mipi dsi panel + * + * Target board specific, like use gpio to shut down the dsi panel + * Machine board file overrides board_mipi_panel_shutdown + * + * Return: 0 Success + */ +int __weak board_mipi_panel_shutdown(void) +{ + return 0; +} + +static void mipi_dsi_set_mode(struct mipi_dsi_northwest_info *mipi_dsi, + uint8_t mode); +static int mipi_dsi_dcs_cmd(struct mipi_dsi_northwest_info *mipi_dsi, + u8 cmd, const u32 *param, int num); + +static void mipi_dsi_set_mode(struct mipi_dsi_northwest_info *mipi_dsi, + uint8_t mode) +{ + switch (mode) { + case DSI_LP_MODE: + writel(0x1, mipi_dsi->mmio_base + HOST_CFG_NONCONTINUOUS_CLK); + break; + case DSI_HS_MODE: + writel(0x0, mipi_dsi->mmio_base + HOST_CFG_NONCONTINUOUS_CLK); + break; + default: + printf("invalid dsi mode\n"); + return; + } + + mdelay(1); +} + +static int mipi_dsi_dphy_init(struct mipi_dsi_northwest_info *mipi_dsi) +{ + uint32_t time_out = 100; + uint32_t lock; + uint32_t req_bit_clk; + uint32_t bpp; + + int i, best_div = -1; + int64_t delta; + uint64_t least_delta = ~0U; + uint64_t limit, div_result; + uint64_t denominator, numerator, divisor; + uint64_t norm_denom, norm_num, split_denom; + struct pll_divider div = { 0 }; + + setbits_le32(mipi_dsi->sim_base + SIM_SOPT1, MIPI_ISO_DISABLE); + + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_panel_dev->format); + + /* req_bit_clk is PLL out, clk_byte is 1/8th of the req_bit_clk + * We need meet clk_byte_freq >= dpi_pclk_freq * DPI_pixel_size / ( 8 * (cfg_num_lanes + 1)) + */ + + req_bit_clk = PS2KHZ(mipi_dsi->mode.pixclock) * 1000U; + req_bit_clk = req_bit_clk * bpp; + + switch (mipi_dsi->dsi_panel_dev->lanes) { + case 1: + break; + case 2: + req_bit_clk = req_bit_clk >> 1; + break; + case 4: + req_bit_clk = req_bit_clk >> 2; + break; + default: + printf("requested data lane num is invalid\n"); + return -EINVAL; + } + + /* The max rate for PLL out is 800Mhz */ + if (req_bit_clk > 800000000) + return -EINVAL; + + /* calc CM, CN and CO according to PHY PLL formula: + * + * 'PLL out bitclk = refclk * CM / (CN * CO);' + * + * Let: + * 'numerator = bitclk / divisor'; + * 'denominator = refclk / divisor'; + * Then: + * 'numerator / denominator = CM / (CN * CO)'; + * + * CM is in [16, 255] + * CN is in [1, 32] + * CO is in { 1, 2, 4, 8 }; + */ + divisor = gcd(24000000, req_bit_clk); + WARN_ON(divisor == 1); + + div_result = req_bit_clk; + do_div(div_result, divisor); + numerator = div_result; + + div_result = 24000000; + do_div(div_result, divisor); + denominator = div_result; + + /* denominator & numerator out of range check */ + if (DIV_ROUND_CLOSEST_ULL(numerator, denominator) > 255 || + DIV_ROUND_CLOSEST_ULL(denominator, numerator) > 32 * 8) + return -EINVAL; + + /* Normalization: reduce or increase + * numerator to [16, 255] + * denominator to [1, 32 * 8] + * Reduce normalization result is 'approximiate' + * Increase nomralization result is 'precise' + */ + if (numerator > 255 || denominator > 32 * 8) { + /* approximate */ + if (likely(numerator > denominator)) { + /* 'numerator > 255'; + * 'limit' should meet below conditions: + * a. '(numerator / limit) >= 16' + * b. '(denominator / limit) >= 1' + */ + limit = min(denominator, + DIV_ROUND_CLOSEST_ULL(numerator, 16)); + + /* Let: + * norm_num = numerator / i; + * norm_denom = denominator / i; + * + * So: + * delta = numerator * norm_denom - + * denominator * norm_num + */ + for (i = 2; i <= limit; i++) { + norm_num = DIV_ROUND_CLOSEST_ULL(numerator, i); + if (norm_num > 255) + continue; + + norm_denom = DIV_ROUND_CLOSEST_ULL(denominator, i); + + /* 'norm_num <= 255' && 'norm_num > norm_denom' + * so, 'norm_denom < 256' + */ + delta = numerator * norm_denom - + denominator * norm_num; + delta = abs(delta); + if (delta < least_delta) { + least_delta = delta; + best_div = i; + } else if (delta == least_delta) { + /* choose better one IF: + * 'norm_denom' derived from last 'best_div' + * needs later split, i.e, 'norm_denom > 32'. + */ + if (DIV_ROUND_CLOSEST_ULL(denominator, best_div) > 32) { + least_delta = delta; + best_div = i; + } + } + } + } else { + /* 'denominator > 32 * 8'; + * 'limit' should meet below conditions: + * a. '(numerator / limit >= 16' + * b. '(denominator / limit >= 1': obviously. + */ + limit = DIV_ROUND_CLOSEST_ULL(numerator, 16); + if (!limit || + DIV_ROUND_CLOSEST_ULL(denominator, limit) > 32 * 8) + return -EINVAL; + + for (i = 2; i <= limit; i++) { + norm_denom = DIV_ROUND_CLOSEST_ULL(denominator, i); + if (norm_denom > 32 * 8) + continue; + + norm_num = DIV_ROUND_CLOSEST_ULL(numerator, i); + + /* 'norm_denom <= 256' && 'norm_num < norm_denom' + * so, 'norm_num <= 255' + */ + delta = numerator * norm_denom - + denominator * norm_num; + delta = abs(delta); + if (delta < least_delta) { + least_delta = delta; + best_div = i; + } else if (delta == least_delta) { + if (DIV_ROUND_CLOSEST_ULL(denominator, best_div) > 32) { + least_delta = delta; + best_div = i; + } + } + } + } + + numerator = DIV_ROUND_CLOSEST_ULL(numerator, best_div); + denominator = DIV_ROUND_CLOSEST_ULL(denominator, best_div); + } else if (numerator < 16) { + /* precise */ + + /* 'limit' should meet below conditions: + * a. 'denominator * limit <= 32 * 8' + * b. '16 <= numerator * limit <= 255' + * Choose 'limit' to be the least value + * which makes 'numerator * limit' to be + * in [16, 255]. + */ + limit = min(256 / (uint32_t)denominator, + 255 / (uint32_t)numerator); + if (limit == 1 || limit < DIV_ROUND_UP_ULL(16, numerator)) + return -EINVAL; + + /* choose the least available value for 'limit' */ + limit = DIV_ROUND_UP_ULL(16, numerator); + numerator = numerator * limit; + denominator = denominator * limit; + + WARN_ON(numerator < 16 || denominator > 32 * 8); + } + + div.cm = cm_map_table[numerator - 16]; + + /* split 'denominator' to 'CN' and 'CO' */ + if (denominator > 32) { + /* traverse four possible values of 'CO' + * there must be some value of 'CO' can be used + */ + least_delta = ~0U; + for (i = 0; i < 4; i++) { + split_denom = DIV_ROUND_CLOSEST_ULL(denominator, 1 << i); + if (split_denom > 32) + continue; + + /* calc deviation to choose the best one */ + delta = denominator - split_denom * (1 << i); + delta = abs(delta); + if (delta < least_delta) { + least_delta = delta; + div.co = co_map_table[i]; + div.cn = cn_map_table[split_denom - 1]; + } + } + } else { + div.co = co_map_table[1 >> 1]; + div.cn = cn_map_table[denominator - 1]; + } + + debug("cn 0x%x, cm 0x%x, co 0x%x\n", div.cn, div.cm, div.co); + + writel(div.cn, mipi_dsi->mmio_base + DPHY_CN); + writel(div.cm, mipi_dsi->mmio_base + DPHY_CM); + writel(div.co, mipi_dsi->mmio_base + DPHY_CO); + + writel(0x25, mipi_dsi->mmio_base + DPHY_TST); + writel(0x0, mipi_dsi->mmio_base + DPHY_PD_PLL); + + while (!(lock = readl(mipi_dsi->mmio_base + DPHY_LOCK))) { + udelay(10); + time_out--; + if (time_out == 0) { + printf("cannot get the dphy lock = 0x%x\n", lock); + return -EINVAL; + } + } + debug("%s: dphy lock = 0x%x\n", __func__, lock); + + writel(0x0, mipi_dsi->mmio_base + DPHY_LOCK_BYP); + writel(0x1, mipi_dsi->mmio_base + DPHY_RTERM_SEL); + writel(0x0, mipi_dsi->mmio_base + DPHY_AUTO_PD_EN); + writel(0x1, mipi_dsi->mmio_base + DPHY_RXLPRP); + writel(0x1, mipi_dsi->mmio_base + DPHY_RXCDRP); + writel(0x0, mipi_dsi->mmio_base + DPHY_M_PRG_HS_PREPARE); + writel(0x0, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_PREPARE); + writel(0x9, mipi_dsi->mmio_base + DPHY_M_PRG_HS_ZERO); + writel(0x20, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_ZERO); + writel(0x5, mipi_dsi->mmio_base + DPHY_M_PRG_HS_TRAIL); + writel(0x5, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_TRAIL); + writel(0x0, mipi_dsi->mmio_base + DPHY_PD_DPHY); + + setbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_PLL_EN); + return 0; +} + +static int mipi_dsi_host_init(struct mipi_dsi_northwest_info *mipi_dsi) +{ + uint32_t lane_num; + + switch (mipi_dsi->dsi_panel_dev->lanes) { + case 1: + lane_num = 0x0; + break; + case 2: + lane_num = 0x1; + break; + default: + /* Invalid lane num */ + return -EINVAL; + } + + writel(lane_num, mipi_dsi->mmio_base + HOST_CFG_NUM_LANES); + writel(0x1, mipi_dsi->mmio_base + HOST_CFG_NONCONTINUOUS_CLK); + writel(0x1, mipi_dsi->mmio_base + HOST_CFG_T_PRE); + writel(52, mipi_dsi->mmio_base + HOST_CFG_T_POST); + writel(13, mipi_dsi->mmio_base + HOST_CFG_TX_GAP); + writel(0x1, mipi_dsi->mmio_base + HOST_CFG_AUTOINSERT_EOTP); + writel(0x0, mipi_dsi->mmio_base + HOST_CFG_EXTRA_CMDS_AFTER_EOTP); + writel(0x0, mipi_dsi->mmio_base + HOST_CFG_HTX_TO_COUNT); + writel(0x0, mipi_dsi->mmio_base + HOST_CFG_LRX_H_TO_COUNT); + writel(0x0, mipi_dsi->mmio_base + HOST_CFG_BTA_H_TO_COUNT); + writel(0x3A98, mipi_dsi->mmio_base + HOST_CFG_TWAKEUP); + + return 0; +} + +static int mipi_dsi_dpi_init(struct mipi_dsi_northwest_info *mipi_dsi) +{ + uint32_t bpp, color_coding, pixel_fmt; + struct fb_videomode *mode = &(mipi_dsi->mode); + + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_panel_dev->format); + if (bpp < 0) + return -EINVAL; + + writel(mode->xres, mipi_dsi->mmio_base + DPI_PIXEL_PAYLOAD_SIZE); + writel(mode->xres, mipi_dsi->mmio_base + DPI_PIXEL_FIFO_SEND_LEVEL); + + switch (bpp) { + case 24: + color_coding = 5; + pixel_fmt = 3; + break; + case 16: + case 18: + default: + /* Not supported */ + return -EINVAL; + } + writel(color_coding, mipi_dsi->mmio_base + DPI_INTERFACE_COLOR_CODING); + writel(pixel_fmt, mipi_dsi->mmio_base + DPI_PIXEL_FORMAT); + writel(0x0, mipi_dsi->mmio_base + DPI_VSYNC_POLARITY); + writel(0x0, mipi_dsi->mmio_base + DPI_HSYNC_POLARITY); + writel(0x2, mipi_dsi->mmio_base + DPI_VIDEO_MODE); + + writel(mode->right_margin * (bpp >> 3), mipi_dsi->mmio_base + DPI_HFP); + writel(mode->left_margin * (bpp >> 3), mipi_dsi->mmio_base + DPI_HBP); + writel(mode->hsync_len * (bpp >> 3), mipi_dsi->mmio_base + DPI_HSA); + writel(0x0, mipi_dsi->mmio_base + DPI_ENABLE_MULT_PKTS); + + writel(mode->upper_margin, mipi_dsi->mmio_base + DPI_VBP); + writel(mode->lower_margin, mipi_dsi->mmio_base + DPI_VFP); + writel(0x1, mipi_dsi->mmio_base + DPI_BLLP_MODE); + writel(0x0, mipi_dsi->mmio_base + DPI_USE_NULL_PKT_BLLP); + + writel(mode->yres - 1, mipi_dsi->mmio_base + DPI_VACTIVE); + + writel(0x0, mipi_dsi->mmio_base + DPI_VC); + + return 0; +} + +static void mipi_dsi_init_interrupt(struct mipi_dsi_northwest_info *mipi_dsi) +{ + /* disable all the irqs */ + writel(0xffffffff, mipi_dsi->mmio_base + HOST_IRQ_MASK); + writel(0x7, mipi_dsi->mmio_base + HOST_IRQ_MASK2); +} + +static int mipi_display_enter_sleep(struct mipi_dsi_northwest_info *mipi_dsi) +{ + int err; + + err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_SET_DISPLAY_OFF, + NULL, 0); + if (err) + return -EINVAL; + mdelay(50); + + err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_ENTER_SLEEP_MODE, + NULL, 0); + if (err) + printf("MIPI DSI DCS Command sleep in error!\n"); + + mdelay(MIPI_LCD_SLEEP_MODE_DELAY); + + return err; +} + +static int mipi_dsi_enable(struct mipi_dsi_northwest_info *mipi_dsi) +{ + int ret; + + /* Assert resets */ + /* escape domain */ + clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_ESC_N); + + /* byte domain */ + clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_BYTE_N); + + /* dpi domain */ + clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_DPI_N); + + /* Enable mipi relevant clocks */ + enable_mipi_dsi_clk(1); + + ret = mipi_dsi_dphy_init(mipi_dsi); + if (ret < 0) + return ret; + + ret = mipi_dsi_host_init(mipi_dsi); + if (ret < 0) + return ret; + + ret = mipi_dsi_dpi_init(mipi_dsi); + if (ret < 0) + return ret; + + /* Deassert resets */ + /* escape domain */ + setbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_ESC_N); + + /* byte domain */ + setbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_BYTE_N); + + /* dpi domain */ + setbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_DPI_N); + + /* display_en */ + clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_SD); + + /* normal cm */ + clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_CM); + mdelay(20); + + /* Reset mipi panel */ + board_mipi_panel_reset(); + mdelay(60); + + /* Disable all interrupts, since we use polling */ + mipi_dsi_init_interrupt(mipi_dsi); + + /* Call panel driver's setup */ + if (mipi_dsi->dsi_panel_drv->dsi_client_setup) { + ret = mipi_dsi->dsi_panel_drv->dsi_client_setup(mipi_dsi->dsi_panel_dev); + if (ret < 0) { + printf("failed to init mipi lcd.\n"); + return ret; + } + } + + /* Enter the HS mode for video stream */ + mipi_dsi_set_mode(mipi_dsi, DSI_HS_MODE); + + return 0; +} + +static void mipi_dsi_wr_tx_header(struct mipi_dsi_northwest_info *mipi_dsi, + u8 di, u8 data0, u8 data1, u8 mode, u8 need_bta) +{ + uint32_t pkt_control = 0; + uint16_t word_count = 0; + + word_count = data0 | (data1 << 8); + pkt_control = HOST_PKT_CONTROL_WC(word_count) | + HOST_PKT_CONTROL_VC(0) | + HOST_PKT_CONTROL_DT(di) | + HOST_PKT_CONTROL_HS_SEL(mode) | + HOST_PKT_CONTROL_BTA_TX(need_bta); + + debug("pkt_control = %x\n", pkt_control); + writel(pkt_control, mipi_dsi->mmio_base + HOST_PKT_CONTROL); +} + +static void mipi_dsi_wr_tx_data(struct mipi_dsi_northwest_info *mipi_dsi, + uint32_t tx_data) +{ + writel(tx_data, mipi_dsi->mmio_base + HOST_TX_PAYLOAD); +} + +static void mipi_dsi_long_data_wr(struct mipi_dsi_northwest_info *mipi_dsi, + const uint8_t *data0, uint32_t data_size) +{ + uint32_t data_cnt = 0, payload = 0; + + /* in case that data count is more than 4 */ + for (data_cnt = 0; data_cnt < data_size; data_cnt += 4) { + /* + * after sending 4bytes per one time, + * send remainder data less then 4. + */ + if ((data_size - data_cnt) < 4) { + if ((data_size - data_cnt) == 3) { + payload = data0[data_cnt] | + (data0[data_cnt + 1] << 8) | + (data0[data_cnt + 2] << 16); + debug("count = 3 payload = %x, %x %x %x\n", + payload, data0[data_cnt], data0[data_cnt + 1], data0[data_cnt + 2]); + } else if ((data_size - data_cnt) == 2) { + payload = data0[data_cnt] | + (data0[data_cnt + 1] << 8); + debug("count = 2 payload = %x, %x %x\n", + payload, data0[data_cnt], data0[data_cnt + 1]); + } else if ((data_size - data_cnt) == 1) { + payload = data0[data_cnt]; + debug("count = 1 payload = %x, %x\n", + payload, data0[data_cnt]); + } + + mipi_dsi_wr_tx_data(mipi_dsi, payload); + } else { + payload = data0[data_cnt] | + (data0[data_cnt + 1] << 8) | + (data0[data_cnt + 2] << 16) | + (data0[data_cnt + 3] << 24); + + debug("count = 4 payload = %x, %x %x %x %x\n", + payload, *(u8 *)(data0 + data_cnt), + data0[data_cnt + 1], + data0[data_cnt + 2], + data0[data_cnt + 3]); + + mipi_dsi_wr_tx_data(mipi_dsi, payload); + } + } +} + +static int wait_for_pkt_done(struct mipi_dsi_northwest_info *mipi_dsi, unsigned long timeout) +{ + uint32_t irq_status; + + do { + irq_status = readl(mipi_dsi->mmio_base + HOST_PKT_STATUS); + if (irq_status & HOST_IRQ_STATUS_TX_PKT_DONE) + return timeout; + + udelay(1); + } while (--timeout); + + return 0; +} + +static int mipi_dsi_pkt_write(struct mipi_dsi_northwest_info *mipi_dsi, + u8 data_type, const u8 *buf, int len) +{ + int ret = 0; + const uint8_t *data = (const uint8_t *)buf; + + debug("mipi_dsi_pkt_write data_type 0x%x, buf 0x%x, len %u\n", data_type, (u32)buf, len); + + if (len == 0) + /* handle generic long write command */ + mipi_dsi_wr_tx_header(mipi_dsi, data_type, data[0], data[1], DSI_LP_MODE, 0); + else { + /* handle generic long write command */ + mipi_dsi_long_data_wr(mipi_dsi, data, len); + mipi_dsi_wr_tx_header(mipi_dsi, data_type, len & 0xff, + (len & 0xff00) >> 8, DSI_LP_MODE, 0); + } + + /* send packet */ + writel(0x1, mipi_dsi->mmio_base + HOST_SEND_PACKET); + ret = wait_for_pkt_done(mipi_dsi, MIPI_FIFO_TIMEOUT); + + if (!ret) { + printf("wait tx done timeout!\n"); + return -ETIMEDOUT; + } + mdelay(10); + + return 0; +} + +static int mipi_dsi_dcs_cmd(struct mipi_dsi_northwest_info *mipi_dsi, + u8 cmd, const u32 *param, int num) +{ + int err = 0; + u32 buf[DSI_CMD_BUF_MAXSIZE]; + + switch (cmd) { + case MIPI_DCS_EXIT_SLEEP_MODE: + case MIPI_DCS_ENTER_SLEEP_MODE: + case MIPI_DCS_SET_DISPLAY_ON: + case MIPI_DCS_SET_DISPLAY_OFF: + buf[0] = cmd; + buf[1] = 0x0; + err = mipi_dsi_pkt_write(mipi_dsi, + MIPI_DSI_DCS_SHORT_WRITE, (u8 *)buf, 0); + break; + + default: + printf("MIPI DSI DCS Command:0x%x Not supported!\n", cmd); + break; + } + + return err; +} + +static void mipi_dsi_shutdown(struct mipi_dsi_northwest_info *mipi_dsi) +{ + mipi_display_enter_sleep(mipi_dsi); + + writel(0x1, mipi_dsi->mmio_base + DPHY_PD_PLL); + writel(0x1, mipi_dsi->mmio_base + DPHY_PD_DPHY); + + enable_mipi_dsi_clk(0); + + /* Assert resets */ + /* escape domain */ + clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_ESC_N); + + /* byte domain */ + clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_BYTE_N); + + /* dpi domain */ + clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_DPI_N); +} + +/* Attach a LCD panel device */ +int mipi_dsi_northwest_bridge_attach(struct mipi_dsi_bridge_driver *bridge_driver, struct mipi_dsi_client_dev *panel_dev) +{ + struct mipi_dsi_northwest_info *dsi_info = (struct mipi_dsi_northwest_info *)bridge_driver->driver_private; + + if (!panel_dev) { + printf("mipi_dsi_northwest_panel_device is NULL.\n"); + return -EFAULT; + } + + if (!panel_dev->name) { + printf("mipi_dsi_northwest_panel_device name is NULL.\n"); + return -EFAULT; + } + + if (dsi_info->dsi_panel_drv) { + if (strcmp(panel_dev->name, dsi_info->dsi_panel_drv->name)) { + printf("The panel device name %s is not for LCD driver %s\n", + panel_dev->name, dsi_info->dsi_panel_drv->name); + return -EFAULT; + } + } + + dsi_info->dsi_panel_dev = panel_dev; + + return 0; +} + + +/* Add a LCD panel driver, will search the panel device to bind with them */ +int mipi_dsi_northwest_bridge_add_client_driver(struct mipi_dsi_bridge_driver *bridge_driver, + struct mipi_dsi_client_driver *panel_drv) +{ + struct mipi_dsi_northwest_info *dsi_info = (struct mipi_dsi_northwest_info *)bridge_driver->driver_private; + + if (!panel_drv) { + printf("mipi_dsi_northwest_panel_driver is NULL.\n"); + return -EFAULT; + } + + if (!panel_drv->name) { + printf("mipi_dsi_northwest_panel_driver name is NULL.\n"); + return -EFAULT; + } + + if (dsi_info->dsi_panel_dev) { + if (strcmp(panel_drv->name, dsi_info->dsi_panel_dev->name)) { + printf("The panel driver name %s is not for LCD device %s\n", + panel_drv->name, dsi_info->dsi_panel_dev->name); + return -EFAULT; + } + } + + dsi_info->dsi_panel_drv = panel_drv; + + return 0; +} + +/* Enable the mipi dsi display */ +static int mipi_dsi_northwest_bridge_enable(struct mipi_dsi_bridge_driver *bridge_driver) +{ + struct mipi_dsi_northwest_info *dsi_info = (struct mipi_dsi_northwest_info *)bridge_driver->driver_private; + + if (!dsi_info->dsi_panel_dev || !dsi_info->dsi_panel_drv) + return -ENODEV; + + mipi_dsi_enable(dsi_info); + + dsi_info->enabled = 1; + + return 0; +} + +/* Disable and shutdown the mipi dsi display */ +static int mipi_dsi_northwest_bridge_disable(struct mipi_dsi_bridge_driver *bridge_driver) +{ + struct mipi_dsi_northwest_info *dsi_info = (struct mipi_dsi_northwest_info *)bridge_driver->driver_private; + + if (!dsi_info->enabled) + return 0; + + mipi_dsi_shutdown(dsi_info); + board_mipi_panel_shutdown(); + + dsi_info->enabled = 0; + + return 0; +} + +static int mipi_dsi_northwest_bridge_mode_set(struct mipi_dsi_bridge_driver *bridge_driver, + struct fb_videomode *fbmode) +{ + struct mipi_dsi_northwest_info *dsi_info = (struct mipi_dsi_northwest_info *)bridge_driver->driver_private; + + dsi_info->mode = *fbmode; + + return 0; +} + +static int mipi_dsi_northwest_bridge_pkt_write(struct mipi_dsi_bridge_driver *bridge_driver, + u8 data_type, const u8 *buf, int len) +{ + struct mipi_dsi_northwest_info *mipi_dsi = (struct mipi_dsi_northwest_info *)bridge_driver->driver_private; + + return mipi_dsi_pkt_write(mipi_dsi, data_type, buf, len); +} + +struct mipi_dsi_bridge_driver imx_northwest_dsi_driver = { + .attach = mipi_dsi_northwest_bridge_attach, + .enable = mipi_dsi_northwest_bridge_enable, + .disable = mipi_dsi_northwest_bridge_disable, + .mode_set = mipi_dsi_northwest_bridge_mode_set, + .pkt_write = mipi_dsi_northwest_bridge_pkt_write, + .add_client_driver = mipi_dsi_northwest_bridge_add_client_driver, + .name = "imx_northwest_mipi_dsi", +}; + +int mipi_dsi_northwest_setup(u32 base_addr, u32 sim_addr) +{ + struct mipi_dsi_northwest_info *dsi_info; + + dsi_info = (struct mipi_dsi_northwest_info *)malloc(sizeof(struct mipi_dsi_northwest_info)); + if (!dsi_info) { + printf("failed to allocate mipi_dsi_northwest_info object.\n"); + return -ENOMEM; + } + + dsi_info->mmio_base = base_addr; + dsi_info->sim_base = sim_addr; + dsi_info->dsi_panel_dev = NULL; + dsi_info->dsi_panel_drv = NULL; + dsi_info->enabled = 0; + + imx_northwest_dsi_driver.driver_private = dsi_info; + return imx_mipi_dsi_bridge_register_driver(&imx_northwest_dsi_driver); +} diff --git a/drivers/video/mipi_dsi_northwest_regs.h b/drivers/video/mipi_dsi_northwest_regs.h new file mode 100644 index 00000000000..6493403a0c4 --- /dev/null +++ b/drivers/video/mipi_dsi_northwest_regs.h @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __MIPI_DSI_NORTHWEST_REGS_H +#define __MIPI_DSI_NORTHWEST_REGS_H + +/* ---------------------------- register offsets --------------------------- */ + +/* sim */ +#define SIM_SOPT1 0x0 +#define MIPI_ISO_DISABLE 0x8 + +#define SIM_SOPT1CFG 0x4 +#define DSI_RST_DPI_N 0x80000000 +#define DSI_RST_ESC_N 0x40000000 +#define DSI_RST_BYTE_N 0x20000000 +#define DSI_SD 0x200 +#define DSI_CM 0x100 +#define DSI_PLL_EN 0x80 + +/* dphy */ +#define DPHY_PD_DPHY 0x300 +#define DPHY_M_PRG_HS_PREPARE 0x304 +#define DPHY_MC_PRG_HS_PREPARE 0x308 +#define DPHY_M_PRG_HS_ZERO 0x30c +#define DPHY_MC_PRG_HS_ZERO 0x310 +#define DPHY_M_PRG_HS_TRAIL 0x314 +#define DPHY_MC_PRG_HS_TRAIL 0x318 +#define DPHY_PD_PLL 0x31c +#define DPHY_TST 0x320 +#define DPHY_CN 0x324 +#define DPHY_CM 0x328 +#define DPHY_CO 0x32c +#define DPHY_LOCK 0x330 +#define DPHY_LOCK_BYP 0x334 +#define DPHY_RTERM_SEL 0x338 +#define DPHY_AUTO_PD_EN 0x33c +#define DPHY_RXLPRP 0x340 +#define DPHY_RXCDRP 0x344 + +/* host */ +#define HOST_CFG_NUM_LANES 0x0 +#define HOST_CFG_NONCONTINUOUS_CLK 0x4 +#define HOST_CFG_T_PRE 0x8 +#define HOST_CFG_T_POST 0xc +#define HOST_CFG_TX_GAP 0x10 +#define HOST_CFG_AUTOINSERT_EOTP 0x14 +#define HOST_CFG_EXTRA_CMDS_AFTER_EOTP 0x18 +#define HOST_CFG_HTX_TO_COUNT 0x1c +#define HOST_CFG_LRX_H_TO_COUNT 0x20 +#define HOST_CFG_BTA_H_TO_COUNT 0x24 +#define HOST_CFG_TWAKEUP 0x28 +#define HOST_CFG_STATUS_OUT 0x2c +#define HOST_RX_ERROR_STATUS 0x30 + +/* dpi */ +#define DPI_PIXEL_PAYLOAD_SIZE 0x200 +#define DPI_PIXEL_FIFO_SEND_LEVEL 0x204 +#define DPI_INTERFACE_COLOR_CODING 0x208 +#define DPI_PIXEL_FORMAT 0x20c +#define DPI_VSYNC_POLARITY 0x210 +#define DPI_HSYNC_POLARITY 0x214 +#define DPI_VIDEO_MODE 0x218 +#define DPI_HFP 0x21c +#define DPI_HBP 0x220 +#define DPI_HSA 0x224 +#define DPI_ENABLE_MULT_PKTS 0x228 +#define DPI_VBP 0x22c +#define DPI_VFP 0x230 +#define DPI_BLLP_MODE 0x234 +#define DPI_USE_NULL_PKT_BLLP 0x238 +#define DPI_VACTIVE 0x23c +#define DPI_VC 0x240 + +/* apb pkt */ +#define HOST_TX_PAYLOAD 0x280 + +#define HOST_PKT_CONTROL 0x284 +#define HOST_PKT_CONTROL_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_CONTROL_VC(x) (((x) & 0x3) << 16) +#define HOST_PKT_CONTROL_DT(x) (((x) & 0x3f) << 18) +#define HOST_PKT_CONTROL_HS_SEL(x) (((x) & 0x1) << 24) +#define HOST_PKT_CONTROL_BTA_TX(x) (((x) & 0x1) << 25) +#define HOST_PKT_CONTROL_BTA_NO_TX(x) (((x) & 0x1) << 26) + +#define HOST_SEND_PACKET 0x288 +#define HOST_PKT_STATUS 0x28c +#define HOST_PKT_FIFO_WR_LEVEL 0x290 +#define HOST_PKT_FIFO_RD_LEVEL 0x294 +#define HOST_PKT_RX_PAYLOAD 0x298 + +#define HOST_PKT_RX_PKT_HEADER 0x29c +#define HOST_PKT_RX_PKT_HEADER_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_RX_PKT_HEADER_DT(x) (((x) & 0x3f) << 16) +#define HOST_PKT_RX_PKT_HEADER_VC(x) (((x) & 0x3) << 22) + +#define HOST_IRQ_STATUS 0x2a0 +#define HOST_IRQ_STATUS_SM_NOT_IDLE (1 << 0) +#define HOST_IRQ_STATUS_TX_PKT_DONE (1 << 1) +#define HOST_IRQ_STATUS_DPHY_DIRECTION (1 << 2) +#define HOST_IRQ_STATUS_TX_FIFO_OVFLW (1 << 3) +#define HOST_IRQ_STATUS_TX_FIFO_UDFLW (1 << 4) +#define HOST_IRQ_STATUS_RX_FIFO_OVFLW (1 << 5) +#define HOST_IRQ_STATUS_RX_FIFO_UDFLW (1 << 6) +#define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD (1 << 7) +#define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD (1 << 8) +#define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT (1 << 29) +#define HOST_IRQ_STATUS_LP_RX_TIMEOUT (1 << 30) +#define HOST_IRQ_STATUS_HS_TX_TIMEOUT (1 << 31) + +#define HOST_IRQ_STATUS2 0x2a4 +#define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR (1 << 0) +#define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR (1 << 1) +#define HOST_IRQ_STATUS2_CRC_ERR (1 << 2) + +#define HOST_IRQ_MASK 0x2a8 +#define HOST_IRQ_MASK_SM_NOT_IDLE_MASK (1 << 0) +#define HOST_IRQ_MASK_TX_PKT_DONE_MASK (1 << 1) +#define HOST_IRQ_MASK_DPHY_DIRECTION_MASK (1 << 2) +#define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK (1 << 3) +#define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK (1 << 4) +#define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK (1 << 5) +#define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK (1 << 6) +#define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK (1 << 7) +#define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK (1 << 8) +#define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK (1 << 29) +#define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK (1 << 30) +#define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK (1 << 31) + +#define HOST_IRQ_MASK2 0x2ac +#define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK (1 << 0) +#define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK (1 << 1) +#define HOST_IRQ_MASK2_CRC_ERR_MASK (1 << 2) + +/* ------------------------------------- end -------------------------------- */ + +#endif diff --git a/drivers/video/mxc_csi.c b/drivers/video/mxc_csi.c new file mode 100644 index 00000000000..311f05f0492 --- /dev/null +++ b/drivers/video/mxc_csi.c @@ -0,0 +1,272 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * @file fsl_csi.c, this file is derived from mx27_csi.c + * + * @brief mx25 CMOS Sensor interface functions + * + * @ingroup CSI + */ +#include +#include + +#include +#include +#include + +#include +#include + +#include "mxc_csi.h" + +enum { + STD_NTSC = 0, + STD_PAL, +}; + +void __iomem *csi_regbase; + +static void csihw_reset_frame_count(void) +{ + __raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, CSI_CSICR3); +} + +static void csihw_reset(void) +{ + csihw_reset_frame_count(); + __raw_writel(CSICR1_RESET_VAL, CSI_CSICR1); + __raw_writel(CSICR2_RESET_VAL, CSI_CSICR2); + __raw_writel(CSICR3_RESET_VAL, CSI_CSICR3); +} + +/*! + * csi_init_interface + * Init csi interface + */ +void csi_init_interface(void) +{ + unsigned int val = 0; + unsigned int imag_para; + + val |= BIT_SOF_POL; + val |= BIT_REDGE; + val |= BIT_GCLK_MODE; + val |= BIT_HSYNC_POL; + val |= BIT_FCC; + val |= 1 << SHIFT_MCLKDIV; + val |= BIT_MCLKEN; + __raw_writel(val, CSI_CSICR1); + + imag_para = (640 << 16) | 960; + __raw_writel(imag_para, CSI_CSIIMAG_PARA); + + val = 0x1010; + val |= BIT_DMA_REFLASH_RFF; + __raw_writel(val, CSI_CSICR3); +} + +void csi_format_swap16(bool enable) +{ + unsigned int val; + + val = __raw_readl(CSI_CSICR1); + if (enable) { + val |= BIT_PACK_DIR; + val |= BIT_SWAP16_EN; + } else { + val &= ~BIT_PACK_DIR; + val &= ~BIT_SWAP16_EN; + } + + __raw_writel(val, CSI_CSICR1); +} + +void csi_enable_int(int arg) +{ + unsigned long cr1 = __raw_readl(CSI_CSICR1); + + if (arg == 1) { + /* still capture needs DMA intterrupt */ + cr1 |= BIT_FB1_DMA_DONE_INTEN; + cr1 |= BIT_FB2_DMA_DONE_INTEN; + } + __raw_writel(cr1, CSI_CSICR1); +} + +void csi_disable_int(void) +{ + unsigned long cr1 = __raw_readl(CSI_CSICR1); + + cr1 &= ~BIT_FB1_DMA_DONE_INTEN; + cr1 &= ~BIT_FB2_DMA_DONE_INTEN; + __raw_writel(cr1, CSI_CSICR1); +} + +void csi_enable(int arg) +{ + unsigned long cr = __raw_readl(CSI_CSICR18); + + if (arg == 1) + cr |= BIT_CSI_ENABLE; + else + cr &= ~BIT_CSI_ENABLE; + __raw_writel(cr, CSI_CSICR18); +} + +void csi_buf_stride_set(u32 stride) +{ + __raw_writel(stride, CSI_CSIFBUF_PARA); +} + +void csi_deinterlace_enable(bool enable) +{ + unsigned long cr18 = __raw_readl(CSI_CSICR18); + + if (enable == true) + cr18 |= BIT_DEINTERLACE_EN; + else + cr18 &= ~BIT_DEINTERLACE_EN; + + __raw_writel(cr18, CSI_CSICR18); +} + +void csi_deinterlace_mode(int mode) +{ + unsigned long cr18 = __raw_readl(CSI_CSICR18); + + if (mode == STD_NTSC) + cr18 |= BIT_NTSC_EN; + else + cr18 &= ~BIT_NTSC_EN; + + __raw_writel(cr18, CSI_CSICR18); +} + +void csi_tvdec_enable(bool enable) +{ + unsigned long cr18 = __raw_readl(CSI_CSICR18); + unsigned long cr1 = __raw_readl(CSI_CSICR1); + + if (enable == true) { + cr18 |= (BIT_TVDECODER_IN_EN | BIT_BASEADDR_SWITCH_EN); + cr1 |= BIT_CCIR_MODE | BIT_EXT_VSYNC; + cr1 &= ~(BIT_SOF_POL | BIT_REDGE); + } else { + cr18 &= ~(BIT_TVDECODER_IN_EN | BIT_BASEADDR_SWITCH_EN); + cr1 &= ~(BIT_CCIR_MODE | BIT_EXT_VSYNC); + cr1 |= BIT_SOF_POL | BIT_REDGE; + } + + __raw_writel(cr18, CSI_CSICR18); + __raw_writel(cr1, CSI_CSICR1); +} + +void csi_set_32bit_imagpara(int width, int height) +{ + int imag_para = 0; + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + imag_para = (width << 16) | height; + __raw_writel(imag_para, CSI_CSIIMAG_PARA); + + + /* reflash the embeded DMA controller */ + __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); +} + +void csi_set_16bit_imagpara(int width, int height) +{ + int imag_para = 0; + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + imag_para = (width << 16) | (height * 2); + __raw_writel(imag_para, CSI_CSIIMAG_PARA); + + /* reflash the embeded DMA controller */ + __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); +} + +void csi_set_12bit_imagpara(int width, int height) +{ + int imag_para = 0; + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + imag_para = (width << 16) | (height * 3 / 2); + __raw_writel(imag_para, CSI_CSIIMAG_PARA); + + /* reflash the embeded DMA controller */ + __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); +} + +void csi_dmareq_rff_enable(void) +{ + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + cr3 |= BIT_DMA_REQ_EN_RFF; + cr3 |= BIT_HRESP_ERR_EN; + __raw_writel(cr3, CSI_CSICR3); +} + +void csi_dmareq_rff_disable(void) +{ + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + cr3 &= ~BIT_DMA_REQ_EN_RFF; + cr3 &= ~BIT_HRESP_ERR_EN; + __raw_writel(cr3, CSI_CSICR3); +} + +void csi_disable(void) +{ + csi_dmareq_rff_disable(); + csi_disable_int(); + csi_buf_stride_set(0); + csi_deinterlace_enable(false); + csi_tvdec_enable(false); + csi_enable(0); +} + +void csi_config(struct csi_conf_param *csi_conf) +{ + csi_regbase = (u32 *)CSI1_BASE_ADDR; + + csihw_reset(); + + csi_init_interface(); + csi_dmareq_rff_disable(); + + switch (csi_conf->bpp) { + case 32: + csi_set_32bit_imagpara(csi_conf->width, csi_conf->height); + break; + case 16: + csi_set_16bit_imagpara(csi_conf->width, csi_conf->height); + break; + default: + printf(" %s case not supported, bpp=%d\n", + __func__, csi_conf->bpp); + return; + } + + __raw_writel((u32)csi_conf->fb0addr, CSI_CSIDMASA_FB1); + __raw_writel((u32)csi_conf->fb1addr, CSI_CSIDMASA_FB2); + + csi_buf_stride_set(0); + if (csi_conf->btvmode) { + /* Enable csi PAL/NTSC deinterlace mode */ + csi_buf_stride_set(csi_conf->width); + csi_deinterlace_mode(csi_conf->std); + csi_deinterlace_enable(true); + csi_tvdec_enable(true); + } + + /* start csi */ + csi_dmareq_rff_enable(); + csi_enable_int(1); + csi_enable(1); +} + diff --git a/drivers/video/mxc_csi.h b/drivers/video/mxc_csi.h new file mode 100644 index 00000000000..ef671e46366 --- /dev/null +++ b/drivers/video/mxc_csi.h @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * @file mxc_csi.h + * + * @brief mxc CMOS Sensor interface functions + * + * @ingroup CSI + */ + +#ifndef MXC_CSI_H +#define MXC_CSI_H + +/* reset values */ +#define CSICR1_RESET_VAL 0x40000800 +#define CSICR2_RESET_VAL 0x0 +#define CSICR3_RESET_VAL 0x0 + +/* csi control reg 1 */ +#define BIT_SWAP16_EN (0x1 << 31) +#define BIT_EXT_VSYNC (0x1 << 30) +#define BIT_EOF_INT_EN (0x1 << 29) +#define BIT_PRP_IF_EN (0x1 << 28) +#define BIT_CCIR_MODE (0x1 << 27) +#define BIT_COF_INT_EN (0x1 << 26) +#define BIT_SF_OR_INTEN (0x1 << 25) +#define BIT_RF_OR_INTEN (0x1 << 24) +#define BIT_SFF_DMA_DONE_INTEN (0x1 << 22) +#define BIT_STATFF_INTEN (0x1 << 21) +#define BIT_FB2_DMA_DONE_INTEN (0x1 << 20) +#define BIT_FB1_DMA_DONE_INTEN (0x1 << 19) +#define BIT_RXFF_INTEN (0x1 << 18) +#define BIT_SOF_POL (0x1 << 17) +#define BIT_SOF_INTEN (0x1 << 16) +#define BIT_MCLKDIV (0xF << 12) +#define BIT_HSYNC_POL (0x1 << 11) +#define BIT_CCIR_EN (0x1 << 10) +#define BIT_MCLKEN (0x1 << 9) +#define BIT_FCC (0x1 << 8) +#define BIT_PACK_DIR (0x1 << 7) +#define BIT_CLR_STATFIFO (0x1 << 6) +#define BIT_CLR_RXFIFO (0x1 << 5) +#define BIT_GCLK_MODE (0x1 << 4) +#define BIT_INV_DATA (0x1 << 3) +#define BIT_INV_PCLK (0x1 << 2) +#define BIT_REDGE (0x1 << 1) +#define BIT_PIXEL_BIT (0x1 << 0) + +#define SHIFT_MCLKDIV 12 + +/* control reg 3 */ +#define BIT_FRMCNT (0xFFFF << 16) +#define BIT_FRMCNT_RST (0x1 << 15) +#define BIT_DMA_REFLASH_RFF (0x1 << 14) +#define BIT_DMA_REFLASH_SFF (0x1 << 13) +#define BIT_DMA_REQ_EN_RFF (0x1 << 12) +#define BIT_DMA_REQ_EN_SFF (0x1 << 11) +#define BIT_STATFF_LEVEL (0x7 << 8) +#define BIT_HRESP_ERR_EN (0x1 << 7) +#define BIT_RXFF_LEVEL (0x7 << 4) +#define BIT_TWO_8BIT_SENSOR (0x1 << 3) +#define BIT_ZERO_PACK_EN (0x1 << 2) +#define BIT_ECC_INT_EN (0x1 << 1) +#define BIT_ECC_AUTO_EN (0x1 << 0) + +#define SHIFT_FRMCNT 16 + +/* csi status reg */ +#define BIT_SFF_OR_INT (0x1 << 25) +#define BIT_RFF_OR_INT (0x1 << 24) +#define BIT_DMA_TSF_DONE_SFF (0x1 << 22) +#define BIT_STATFF_INT (0x1 << 21) +#define BIT_DMA_TSF_DONE_FB2 (0x1 << 20) +#define BIT_DMA_TSF_DONE_FB1 (0x1 << 19) +#define BIT_RXFF_INT (0x1 << 18) +#define BIT_EOF_INT (0x1 << 17) +#define BIT_SOF_INT (0x1 << 16) +#define BIT_F2_INT (0x1 << 15) +#define BIT_F1_INT (0x1 << 14) +#define BIT_COF_INT (0x1 << 13) +#define BIT_HRESP_ERR_INT (0x1 << 7) +#define BIT_ECC_INT (0x1 << 1) +#define BIT_DRDY (0x1 << 0) + +/* csi control reg 18 */ +#define BIT_CSI_ENABLE (0x1 << 31) +#define BIT_BASEADDR_SWITCH_SEL (0x1 << 5) +#define BIT_BASEADDR_SWITCH_EN (0x1 << 4) +#define BIT_PARALLEL24_EN (0x1 << 3) +#define BIT_DEINTERLACE_EN (0x1 << 2) +#define BIT_TVDECODER_IN_EN (0x1 << 1) +#define BIT_NTSC_EN (0x1 << 0) + +#define CSI_MCLK_VF 1 +#define CSI_MCLK_ENC 2 +#define CSI_MCLK_RAW 4 +#define CSI_MCLK_I2C 8 + +#define CSI_CSICR1 (csi_regbase) +#define CSI_CSICR2 (csi_regbase + 0x4) +#define CSI_CSICR3 (csi_regbase + 0x8) +#define CSI_STATFIFO (csi_regbase + 0xC) +#define CSI_CSIRXFIFO (csi_regbase + 0x10) +#define CSI_CSIRXCNT (csi_regbase + 0x14) +#define CSI_CSISR (csi_regbase + 0x18) +#define CSI_CSIDBG (csi_regbase + 0x1C) +#define CSI_CSIDMASA_STATFIFO (csi_regbase + 0x20) +#define CSI_CSIDMATS_STATFIFO (csi_regbase + 0x24) +#define CSI_CSIDMASA_FB1 (csi_regbase + 0x28) +#define CSI_CSIDMASA_FB2 (csi_regbase + 0x2C) +#define CSI_CSIFBUF_PARA (csi_regbase + 0x30) +#define CSI_CSIIMAG_PARA (csi_regbase + 0x34) +#define CSI_CSICR18 (csi_regbase + 0x48) +#define CSI_CSICR19 (csi_regbase + 0x4c) + +struct mxs_csi_regs { + u32 csi_csicr1; /* 0x0 */ + u32 csi_csicr2; /* 0x4 */ + u32 csi_csicr3; /* 0x8 */ + u32 csi_statfifo; /* 0xC */ + u32 csi_csirxfifo; /* 0x10 */ + u32 csi_csirxcnt; /* 0x14 */ + u32 csi_csisr; /* 0x18 */ + u32 csi_csidbg; /* 0x1C */ + u32 csi_csidmasa_statfifo; /* 0x20 */ + u32 csi_csidmats_statfifo; /* 0x24 */ + u32 csi_csidmasa_fb1; /* 0x28 */ + u32 csi_csidmasa_fb2; /* 0x2C */ + u32 csi_csifbuf_para; /* 0x30 */ + u32 csi_csiimag_para; /* 0x34 */ + u32 reserver[4]; + u32 csi_csicr18; /* 0x48 */ + u32 csi_csicr19; /* 0x4c */ +}; + +struct csi_conf_param { + unsigned short width; + unsigned short height; + unsigned int pixel_fmt; + unsigned int bpp; + bool btvmode; + unsigned int std; + void *fb0addr; + void *fb1addr; +}; + +void csi_config(struct csi_conf_param *csi_conf); +void csi_disable(void); +#endif diff --git a/drivers/video/mxc_epdc_fb.c b/drivers/video/mxc_epdc_fb.c new file mode 100644 index 00000000000..d569c0ed4e3 --- /dev/null +++ b/drivers/video/mxc_epdc_fb.c @@ -0,0 +1,484 @@ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/* + * Based on STMP378X LCDIF + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +int lcd_color_fg; +int lcd_color_bg; + +short console_col; +short console_row; + +int rev; + +void lcd_initcolregs(void) +{ +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +#define TEMP_USE_DEFAULT 8 + +#define UPDATE_MODE_PARTIAL 0x0 +#define UPDATE_MODE_FULL 0x1 + +#define TRUE 1 +#define FALSE 0 + +#define msleep(a) udelay(a * 1000) + + +/******************************************************** + * Start Low-Level EPDC Functions + ********************************************************/ + +static inline void epdc_set_screen_res(u32 width, u32 height) +{ + u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width; + + REG_WR(EPDC_BASE, EPDC_RES, val); +} + +static inline void epdc_set_update_coord(u32 x, u32 y) +{ + u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x; + + REG_WR(EPDC_BASE, EPDC_UPD_CORD, val); +} + +static inline void epdc_set_update_dimensions(u32 width, u32 height) +{ + u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width; + + REG_WR(EPDC_BASE, EPDC_UPD_SIZE, val); +} + +static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode, + int use_test_mode, u32 np_val) +{ + u32 reg_val = 0; + + if (use_test_mode) { + reg_val |= + ((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) & + EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN; + + REG_WR(EPDC_BASE, EPDC_UPD_FIXED, reg_val); + + reg_val = EPDC_UPD_CTRL_USE_FIXED; + } else { + REG_WR(EPDC_BASE, EPDC_UPD_FIXED, reg_val); + } + + reg_val |= + ((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) & + EPDC_UPD_CTRL_LUT_SEL_MASK) | + ((waveform_mode << EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) & + EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) | + update_mode; + + REG_WR(EPDC_BASE, EPDC_UPD_CTRL, reg_val); +} + +static inline int epdc_is_lut_active(u32 lut_num) +{ + u32 val = REG_RD(EPDC_BASE, EPDC_STATUS_LUTS); + int is_active = val & (1 << lut_num) ? TRUE : FALSE; + + return is_active; +} + +static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end, + u32 hsync_width, u32 hsync_line_length) +{ + u32 reg_val = + ((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) & + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK) + | ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) & + EPDC_TCE_HSCAN1_LINE_SYNC_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_HSCAN1, reg_val); + + reg_val = + ((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) & + EPDC_TCE_HSCAN2_LINE_BEGIN_MASK) + | ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) & + EPDC_TCE_HSCAN2_LINE_END_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_HSCAN2, reg_val); +} + +static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end, + u32 vsync_width) +{ + u32 reg_val = + ((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) & + EPDC_TCE_VSCAN_FRAME_BEGIN_MASK) + | ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) & + EPDC_TCE_VSCAN_FRAME_END_MASK) + | ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) & + EPDC_TCE_VSCAN_FRAME_SYNC_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_VSCAN, reg_val); +} + +static void epdc_init_settings(void) +{ + u32 reg_val; + int num_ce; + + /* EPDC_CTRL */ + reg_val = REG_RD(EPDC_BASE, EPDC_CTRL); + reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK; + reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP; + reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK; + reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP; + REG_SET(EPDC_BASE, EPDC_CTRL, reg_val); + + /* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */ + reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT + | EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N + | ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) & + EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK); + REG_WR(EPDC_BASE, EPDC_FORMAT, reg_val); + + /* EPDC_FIFOCTRL (disabled) */ + reg_val = + ((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK) + | ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK) + | ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK); + REG_WR(EPDC_BASE, EPDC_FIFOCTRL, reg_val); + + /* EPDC_TEMP - Use default temperature */ + REG_WR(EPDC_BASE, EPDC_TEMP, TEMP_USE_DEFAULT); + + /* EPDC_RES */ + epdc_set_screen_res(panel_info.vl_col, panel_info.vl_row); + + /* + * EPDC_TCE_CTRL + * VSCAN_HOLDOFF = 4 + * VCOM_MODE = MANUAL + * VCOM_VAL = 0 + * DDR_MODE = DISABLED + * LVDS_MODE_CE = DISABLED + * LVDS_MODE = DISABLED + * DUAL_SCAN = DISABLED + * SDDO_WIDTH = 8bit + * PIXELS_PER_SDCLK = 4 + */ + reg_val = + ((panel_info.epdc_data.epdc_timings.vscan_holdoff << + EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) & + EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK) + | EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4; + REG_WR(EPDC_BASE, EPDC_TCE_CTRL, reg_val); + + /* EPDC_TCE_HSCAN */ + epdc_set_horizontal_timing(panel_info.vl_left_margin, + panel_info.vl_right_margin, + panel_info.vl_hsync, + panel_info.vl_hsync); + + /* EPDC_TCE_VSCAN */ + epdc_set_vertical_timing(panel_info.vl_upper_margin, + panel_info.vl_lower_margin, + panel_info.vl_vsync); + + /* EPDC_TCE_OE */ + reg_val = + ((panel_info.epdc_data.epdc_timings.sdoed_width << + EPDC_TCE_OE_SDOED_WIDTH_OFFSET) & + EPDC_TCE_OE_SDOED_WIDTH_MASK) + | ((panel_info.epdc_data.epdc_timings.sdoed_delay << + EPDC_TCE_OE_SDOED_DLY_OFFSET) & + EPDC_TCE_OE_SDOED_DLY_MASK) + | ((panel_info.epdc_data.epdc_timings.sdoez_width << + EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) & + EPDC_TCE_OE_SDOEZ_WIDTH_MASK) + | ((panel_info.epdc_data.epdc_timings.sdoez_delay << + EPDC_TCE_OE_SDOEZ_DLY_OFFSET) & + EPDC_TCE_OE_SDOEZ_DLY_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_OE, reg_val); + + /* EPDC_TCE_TIMING1 */ + REG_WR(EPDC_BASE, EPDC_TCE_TIMING1, 0x0); + + /* EPDC_TCE_TIMING2 */ + reg_val = + ((panel_info.epdc_data.epdc_timings.gdclk_hp_offs << + EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) & + EPDC_TCE_TIMING2_GDCLK_HP_MASK) + | ((panel_info.epdc_data.epdc_timings.gdsp_offs << + EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) & + EPDC_TCE_TIMING2_GDSP_OFFSET_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_TIMING2, reg_val); + + /* EPDC_TCE_TIMING3 */ + reg_val = + ((panel_info.epdc_data.epdc_timings.gdoe_offs << + EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) & + EPDC_TCE_TIMING3_GDOE_OFFSET_MASK) + | ((panel_info.epdc_data.epdc_timings.gdclk_offs << + EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) & + EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_TIMING3, reg_val); + + /* + * EPDC_TCE_SDCFG + * SDCLK_HOLD = 1 + * SDSHR = 1 + * NUM_CE = 1 + * SDDO_REFORMAT = FLIP_PIXELS + * SDDO_INVERT = DISABLED + * PIXELS_PER_CE = display horizontal resolution + */ + num_ce = panel_info.epdc_data.epdc_timings.num_ce; + if (num_ce == 0) + num_ce = 1; + reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR + | ((num_ce << EPDC_TCE_SDCFG_NUM_CE_OFFSET) & EPDC_TCE_SDCFG_NUM_CE_MASK) + | EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS + | ((panel_info.vl_col << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) & + EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_SDCFG, reg_val); + + /* + * EPDC_TCE_GDCFG + * GDRL = 1 + * GDOE_MODE = 0; + * GDSP_MODE = 0; + */ + reg_val = EPDC_TCE_SDCFG_GDRL; + REG_WR(EPDC_BASE, EPDC_TCE_GDCFG, reg_val); + + /* + * EPDC_TCE_POLARITY + * SDCE_POL = ACTIVE LOW + * SDLE_POL = ACTIVE HIGH + * SDOE_POL = ACTIVE HIGH + * GDOE_POL = ACTIVE HIGH + * GDSP_POL = ACTIVE LOW + */ + reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH + | EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH + | EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH; + REG_WR(EPDC_BASE, EPDC_TCE_POLARITY, reg_val); + + /* EPDC_IRQ_MASK */ + REG_WR(EPDC_BASE, EPDC_IRQ_MASK, + EPDC_IRQ_TCE_UNDERRUN_IRQ); + + /* + * EPDC_GPIO + * PWRCOM = ? + * PWRCTRL = ? + * BDR = ? + */ + reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK) + | ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK); + REG_WR(EPDC_BASE, EPDC_GPIO, reg_val); +} + +static void draw_mode0(void) +{ + int i; + + /* Program EPDC update to process buffer */ + epdc_set_update_coord(0, 0); + epdc_set_update_dimensions(panel_info.vl_col, panel_info.vl_row); + epdc_submit_update(0, panel_info.epdc_data.wv_modes.mode_init, + UPDATE_MODE_FULL, FALSE, 0); + + debug("Mode0 update - Waiting for LUT to complete...\n"); + + /* Will timeout after ~4-5 seconds */ + + for (i = 0; i < 40; i++) { + if (!epdc_is_lut_active(0)) { + debug("Mode0 init complete\n"); + return; + } + msleep(100); + } + + debug("Mode0 init failed!\n"); + +} + +static void draw_splash_screen(void) +{ + int i; + int lut_num = 0; + + /* Program EPDC update to process buffer */ + epdc_set_update_coord(0, 0); + epdc_set_update_dimensions(panel_info.vl_col, panel_info.vl_row); + epdc_submit_update(lut_num, panel_info.epdc_data.wv_modes.mode_gc16, + UPDATE_MODE_FULL, FALSE, 0); + + for (i = 0; i < 40; i++) { + if (!epdc_is_lut_active(lut_num)) { + debug("Splash screen update complete\n"); + return; + } + msleep(100); + } + debug("Splash screen update failed!\n"); +} + +void lcd_enable(void) +{ +#ifdef CONFIG_MX6 + if (check_module_fused(MX6_MODULE_EPDC)) { + return; + } +#endif + + if (board_setup_logo_file(lcd_base)) { + debug("Load logo failed!\n"); + return; + } + + epdc_power_on(); + + flush_cache((ulong)lcd_base, panel_info.vl_col * panel_info.vl_row); + + /* Draw data to display */ + draw_mode0(); + + draw_splash_screen(); +} + +void lcd_disable(void) +{ +#ifdef CONFIG_MX6 + if (check_module_fused(MX6_MODULE_EPDC)) { + return; + } +#endif + + debug("lcd_disable\n"); + + /* Disable clocks to EPDC */ + REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE); +} + +void lcd_panel_disable(void) +{ + epdc_power_off(); +} + +void lcd_ctrl_init(void *lcdbase) +{ + unsigned int val; + +#ifdef CONFIG_MX6 + if (check_module_fused(MX6_MODULE_EPDC)) { + printf("EPDC@0x%x is fused, disable it\n", EPDC_BASE_ADDR); + return; + } +#endif + + /* + * We rely on lcdbase being a physical address, i.e., either MMU off, + * or 1-to-1 mapping. Might want to add some virt2phys here. + */ + if (!lcdbase) + return; + + panel_info.epdc_data.working_buf_addr = (u_long)memalign(ARCH_DMA_MINALIGN, + panel_info.vl_col * panel_info.vl_row * 2); + + if (!panel_info.epdc_data.working_buf_addr) { + printf("EPDC: Error allocating working buffer!\n"); + return; + } + + panel_info.epdc_data.waveform_buf_addr = (u_long)memalign(ARCH_DMA_MINALIGN, + CONFIG_WAVEFORM_BUF_SIZE); + + if (!panel_info.epdc_data.waveform_buf_addr) { + printf("EPDC: Error allocating waveform buffer!\n"); + return; + } + + lcd_color_fg = 0xFF; + lcd_color_bg = 0xFF; + + /* Reset */ + REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST); + while (!(REG_RD(EPDC_BASE, EPDC_CTRL) & EPDC_CTRL_CLKGATE)) + ; + REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST); + + /* Enable clock gating (clear to enable) */ + REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE); + while (REG_RD(EPDC_BASE, EPDC_CTRL) & + (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE)) + ; + + debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col, + (int)panel_info.vl_row, NBITS(panel_info.vl_bpix)); + + /* Get EPDC version */ + val = REG_RD(EPDC_BASE, EPDC_VERSION); + rev = ((val & EPDC_VERSION_MAJOR_MASK) >> + EPDC_VERSION_MAJOR_OFFSET) * 10 + + ((val & EPDC_VERSION_MINOR_MASK) >> + EPDC_VERSION_MINOR_OFFSET); + + /* Set framebuffer pointer */ + REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase); + + /* Set Working Buffer pointer */ + REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr); + if (rev > 20) + REG_WR(EPDC_BASE, EPDC_WB_ADDR_TCE, panel_info.epdc_data.working_buf_addr); + + /* Get waveform data address and offset */ + if (board_setup_waveform_file(panel_info.epdc_data.waveform_buf_addr)) { + printf("Can't load waveform data!\n"); + return; + } + + /* Set Waveform Buffer pointer */ + REG_WR(EPDC_BASE, EPDC_WVADDR, + panel_info.epdc_data.waveform_buf_addr); + + /* Initialize EPDC, passing pointer to EPDC registers */ + epdc_init_settings(); + + lcd_base = lcdbase; + + return; +} + +ulong calc_fbsize(void) +{ + return panel_info.vl_row * panel_info.vl_col * 2 \ + * NBITS(panel_info.vl_bpix) / 8; +} + diff --git a/drivers/video/mxc_gis.c b/drivers/video/mxc_gis.c new file mode 100644 index 00000000000..a312fe0c8c1 --- /dev/null +++ b/drivers/video/mxc_gis.c @@ -0,0 +1,406 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "mxc_gis.h" +#include "mxc_csi.h" +#include "mxc_pxp.h" +#include "mxc_vadc.h" + +#define CHANNEL_OFFSET 36 +#define COMMAND_OFFSET 8 +#define REG_OFFSET 4 +#define COMMAND_OPCODE_SHIFT 8 + +enum { + CMD_SET_ACC = 0, + CMD_WR_DATA, + CMD_WR_ACC, + CMD_WR_ALU, + CMD_MOV_ACC, + CMD_RD_DATA, + CMD_RD_ALU, + CMD_WR_FB_CSI, + CMD_WR_FB_PXP_IN, + CMD_WR_FB_PXP_OUT, + CMD_WR_FB_LCDIF, +}; + +enum { + ALU_AND = 0, + ALU_OR, + ALU_XOR, + ALU_ADD, + ALU_SUB, +}; + +enum { + CH_MAPPING_CSI_ISR = 0, + CH_MAPPING_CSI_FB_UPDATE, + CH_MAPPING_PXP_ISR, + CH_MAPPING_LCDIF_FB_UPDATE, + CH_MAPPING_PXP_KICK, + CH_MAPPING_CHANNEL_UNUSED = 0xf, +}; + +enum { + LCDIF1_SEL = 0x10, + LCDIF0_SEL = 0x8, + PXP_SEL = 0x4, + CSI1_SEL = 0x2, + CSI0_SEL = 0x1, +}; + +struct command_opcode { + unsigned opcode:4; + unsigned alu:3; + unsigned acc_neg:1; +}; + +struct command_param { + union { + struct command_opcode cmd_bits; + u8 cmd_opc; + }; + u32 addr; + u32 data; +}; + +struct channel_param { + u32 ch_num; + u32 ch_map; + u32 cmd_num; + struct command_param cmd_data[4]; +}; + +static void *csibuf0, *csibuf1, *fb0, *fb1; +static struct mxs_gis_regs *gis_regs; +static struct mxs_pxp_regs *pxp_regs; +static struct mxs_csi_regs *csi_regs; +static struct mxs_lcdif_regs *lcdif_regs; +static u32 lcdif_sel; +static bool gis_running; + +static void config_channel(struct channel_param *ch) +{ + u32 val, i; + u32 reg_offset; + + /* Config channel map and command */ + switch (ch->ch_num) { + case 0: + val = readl(&gis_regs->hw_gis_config0); + val &= ~(GIS_CONFIG0_CH0_MAPPING_MASK | GIS_CONFIG0_CH0_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG0_CH0_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG0_CH0_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config0); + break; + case 1: + val = readl(&gis_regs->hw_gis_config0); + val &= ~(GIS_CONFIG0_CH1_MAPPING_MASK | GIS_CONFIG0_CH1_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG0_CH1_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG0_CH1_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config0); + break; + case 2: + val = readl(&gis_regs->hw_gis_config0); + val &= ~(GIS_CONFIG0_CH2_MAPPING_MASK | GIS_CONFIG0_CH2_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG0_CH2_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG0_CH2_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config0); + break; + case 3: + val = readl(&gis_regs->hw_gis_config0); + val &= ~(GIS_CONFIG0_CH3_MAPPING_MASK | GIS_CONFIG0_CH3_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG0_CH3_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG0_CH3_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config0); + break; + case 4: + val = readl(&gis_regs->hw_gis_config1); + val &= ~(GIS_CONFIG1_CH4_MAPPING_MASK | GIS_CONFIG1_CH4_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG1_CH4_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG1_CH4_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config1); + break; + case 5: + val = readl(&gis_regs->hw_gis_config1); + val &= ~(GIS_CONFIG1_CH5_MAPPING_MASK | GIS_CONFIG1_CH5_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG1_CH5_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG1_CH5_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config1); + break; + default: + printf("Error channel num\n"); + } + + /* Config command */ + for (i = 0; i < ch->cmd_num; i++) { + val = readl(&gis_regs->hw_gis_ch0_ctrl + ch->ch_num * CHANNEL_OFFSET); + val &= ~(0xFF << (COMMAND_OPCODE_SHIFT * i)); + val |= ch->cmd_data[i].cmd_opc << (COMMAND_OPCODE_SHIFT * i); + writel(val, &gis_regs->hw_gis_ch0_ctrl + ch->ch_num * CHANNEL_OFFSET); + + reg_offset = ch->ch_num * CHANNEL_OFFSET + i * COMMAND_OFFSET; + writel(ch->cmd_data[i].addr, &gis_regs->hw_gis_ch0_addr0 + reg_offset); + writel(ch->cmd_data[i].data, &gis_regs->hw_gis_ch0_data0 + reg_offset); + } +} + +static void gis_channel_init(void) +{ + struct channel_param ch; + int ret; + u32 addr0, data0, addr1, data1; + u32 val; + + /* Restart the GIS block */ + ret = mxs_reset_block(&gis_regs->hw_gis_ctrl_reg); + if (ret) { + debug("MXS GIS: Block reset timeout\n"); + return; + } + + writel((u32)csibuf0, &gis_regs->hw_gis_fb0); + writel((u32)csibuf1, &gis_regs->hw_gis_fb1); + writel((u32)fb0, &gis_regs->hw_gis_pxp_fb0); + writel((u32)fb1, &gis_regs->hw_gis_pxp_fb1); + + /* Config channel 0 -- CSI clean interrupt */ + addr0 = (u32)&csi_regs->csi_csisr; + data0 = BIT_DMA_TSF_DONE_FB1 | BIT_DMA_TSF_DONE_FB2 | BIT_SOF_INT; + ch.ch_num = 0; + ch.ch_map = CH_MAPPING_CSI_ISR; + ch.cmd_num = 1; + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_DATA; + ch.cmd_data[0].cmd_bits.alu = ALU_AND; + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[0].addr = CSI0_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0; + ch.cmd_data[0].data = data0; + config_channel(&ch); + + /* Config channel 1 -- CSI set next framebuffer addr */ + addr0 = (u32)&csi_regs->csi_csidmasa_fb1; + data0 = (u32)&csi_regs->csi_csidmasa_fb2; + ch.ch_num = 1; + ch.ch_map = CH_MAPPING_CSI_FB_UPDATE; + ch.cmd_num = 1; + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_CSI; + ch.cmd_data[0].cmd_bits.alu = ALU_AND; + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[0].addr = CSI0_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0; + ch.cmd_data[0].data = data0; + config_channel(&ch); + + /* Config channel 2 -- PXP clear interrupt and set framebuffer */ + addr0 = (u32)&pxp_regs->pxp_stat_clr; + data0 = BM_PXP_STAT_IRQ; + addr1 = (u32)&pxp_regs->pxp_out_buf; + data1 = 0; + ch.ch_num = 2; + ch.ch_map = CH_MAPPING_PXP_ISR; + ch.cmd_num = 2; + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_DATA; + ch.cmd_data[0].cmd_bits.alu = ALU_AND; + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[0].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0; + ch.cmd_data[0].data = data0; + ch.cmd_data[1].cmd_bits.opcode = CMD_WR_FB_PXP_OUT; + ch.cmd_data[1].cmd_bits.alu = ALU_AND; + ch.cmd_data[1].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[1].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr1; + ch.cmd_data[1].data = data1; + config_channel(&ch); + + /* Config channel 3 -- LCDIF set framebuffer to display */ + addr0 = (u32)&lcdif_regs->hw_lcdif_next_buf; + data0 = 0; + ch.ch_num = 3; + ch.ch_map = CH_MAPPING_LCDIF_FB_UPDATE; + ch.cmd_num = 1; + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_LCDIF; + ch.cmd_data[0].cmd_bits.alu = ALU_AND; + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[0].addr = ((lcdif_sel == 0) ? LCDIF0_SEL : LCDIF1_SEL) << GIS_CH_ADDR_SEL_SHIFT | addr0; + ch.cmd_data[0].data = data0; + config_channel(&ch); + + /* Config channel 4 -- PXP kick to process next framebuffer */ + addr0 = (u32)&pxp_regs->pxp_ps_buf; + data0 = 0; + addr1 = (u32)&pxp_regs->pxp_ctrl; + data1 = BM_PXP_CTRL_IRQ_ENABLE | BM_PXP_CTRL_ENABLE; + ch.ch_num = 4; + ch.ch_map = CH_MAPPING_PXP_KICK; + ch.cmd_num = 2; + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_PXP_IN; + ch.cmd_data[0].cmd_bits.alu = ALU_AND; + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[0].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0; + ch.cmd_data[0].data = data0; + ch.cmd_data[1].cmd_bits.opcode = CMD_WR_DATA; + ch.cmd_data[1].cmd_bits.alu = ALU_AND; + ch.cmd_data[1].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[1].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr1; + ch.cmd_data[1].data = data1; + config_channel(&ch); + + /* start gis */ + val = readl(&gis_regs->hw_gis_ctrl); + if (lcdif_sel == 1) + val |= GIS_CTRL_ENABLE_SET | GIS_CTRL_LCDIF_SEL_LCDIF1; + else + val |= GIS_CTRL_ENABLE_SET | GIS_CTRL_LCDIF_SEL_LCDIF0; + writel(val, &gis_regs->hw_gis_ctrl); +} + +void mxc_disable_gis(void) +{ + u32 val; + + if (!gis_running) + return; + + /* Stop gis */ + val = GIS_CTRL_SFTRST_SET | GIS_CTRL_CLK_GATE_SET; + writel(val, &gis_regs->hw_gis_ctrl); + + /* Stop pxp */ + mxs_reset_block(&pxp_regs->pxp_ctrl_reg); + val = BM_PXP_CTRL_SFTRST | BM_PXP_CTRL_CLKGATE; + writel(val , &pxp_regs->pxp_ctrl); + + csi_disable(); + + vadc_power_down(); +} + +void mxc_enable_gis(void) +{ + struct sensor_data sensor; + struct csi_conf_param csi_conf; + struct pxp_config_data pxp_conf; + struct display_panel panel; + u32 csimemsize, pxpmemsize; + char const *gis_input = env_get("gis"); + +#ifdef CONFIG_MX6 + if (check_module_fused(MX6_MODULE_CSI)) { + printf("CSI@0x%x is fused, disable it\n", CSI1_BASE_ADDR); + return; + } +#endif + +#ifdef CONFIG_MX6 + if (check_module_fused(MX6_MODULE_PXP)) { + printf("PXP@0x%x is fused, disable it\n", PXP_BASE_ADDR); + return; + } +#endif + + gis_regs = (struct mxs_gis_regs *)GIS_BASE_ADDR; + pxp_regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR; + csi_regs = (struct mxs_csi_regs *)CSI1_BASE_ADDR; + + gis_running = false; + + if (gis_input != NULL && !strcmp(gis_input, "vadc")) { + printf("gis input --- vadc\n"); + /* vadc_in 0 */ + vadc_config(0); + + /* Get vadc mode */ + vadc_get_std(&sensor); + } else { + printf("gis input --- No input\n"); + return; + } + + /* Get display mode */ + mxs_lcd_get_panel(&panel); + + lcdif_regs = (struct mxs_lcdif_regs *)panel.reg_base; + if (panel.reg_base == LCDIF2_BASE_ADDR) + lcdif_sel = 1; + else + lcdif_sel = 0; + + /* Allocate csi buffer */ + if (sensor.pixel_fmt == FMT_YUV444) { + csimemsize = sensor.width * sensor.height * 4; + csi_conf.bpp = 32; + } else { + csimemsize = sensor.width * sensor.height * 2; + csi_conf.bpp = 16; + } + + pxpmemsize = panel.width * panel.height * panel.gdfbytespp; + csibuf0 = malloc(csimemsize); + csibuf1 = malloc(csimemsize); + fb0 = malloc(pxpmemsize); + fb1 = malloc(pxpmemsize); + if (!csibuf0 || !csibuf1 || !fb0 || !fb1) { + printf("MXSGIS: Error allocating csibuffer!\n"); + return; + } + /* Wipe framebuffer */ + memset(csibuf0, 0, csimemsize); + memset(csibuf1, 0, csimemsize); + memset(fb0, 0, pxpmemsize); + memset(fb1, 0, pxpmemsize); + + /*config csi */ + csi_conf.width = sensor.width; + csi_conf.height = sensor.height; + csi_conf.btvmode = true; + csi_conf.std = sensor.std_id; + csi_conf.fb0addr = csibuf0; + csi_conf.fb1addr = csibuf1; + csi_config(&csi_conf); + + /* config pxp */ + pxp_conf.s0_param.pixel_fmt = sensor.pixel_fmt; + pxp_conf.s0_param.width = sensor.width; + pxp_conf.s0_param.height = sensor.height; + pxp_conf.s0_param.stride = sensor.width * csi_conf.bpp/8; + pxp_conf.s0_param.paddr = csibuf0; + + switch (panel.gdfindex) { + case GDF_32BIT_X888RGB: + pxp_conf.out_param.pixel_fmt = FMT_RGB888; + break; + case GDF_16BIT_565RGB: + pxp_conf.out_param.pixel_fmt = FMT_RGB565; + break; + default: + printf("GIS unsupported format!"); + } + + pxp_conf.out_param.width = panel.width; + pxp_conf.out_param.height = panel.height; + pxp_conf.out_param.stride = pxp_conf.out_param.width * panel.gdfbytespp; + pxp_conf.out_param.paddr = fb0; + pxp_config(&pxp_conf); + + gis_running = true; + + /* Config gis */ + gis_channel_init(); +} diff --git a/drivers/video/mxc_gis.h b/drivers/video/mxc_gis.h new file mode 100644 index 00000000000..b0e6fa8365d --- /dev/null +++ b/drivers/video/mxc_gis.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef MXC_GIS_H +#define MXC_GIS_H + +#include + +struct mxs_gis_regs { + mxs_reg_32(hw_gis_ctrl) /* 0x00 */ + mxs_reg_32(hw_gis_config0) /* 0x10 */ + mxs_reg_32(hw_gis_config1) /* 0x20 */ + mxs_reg_32(hw_gis_fb0) /* 0x30 */ + mxs_reg_32(hw_gis_fb1) /* 0x40 */ + mxs_reg_32(hw_gis_pxp_fb0) /* 0x50 */ + mxs_reg_32(hw_gis_pxp_fb1) /* 0x60 */ + + mxs_reg_32(hw_gis_ch0_ctrl) /* 0x70 */ + mxs_reg_32(hw_gis_ch0_addr0) /* 0x80 */ + mxs_reg_32(hw_gis_ch0_data0) /* 0x90 */ + mxs_reg_32(hw_gis_ch0_addr1) /* 0xa0 */ + mxs_reg_32(hw_gis_ch0_data1) /* 0xb0 */ + mxs_reg_32(hw_gis_ch0_addr2) /* 0xc0 */ + mxs_reg_32(hw_gis_ch0_data2) /* 0xd0 */ + mxs_reg_32(hw_gis_ch0_addr3) /* 0xe0 */ + mxs_reg_32(hw_gis_ch0_data3) /* 0xf0 */ + + mxs_reg_32(hw_gis_ch1_ctrl) /* 0x100 */ + mxs_reg_32(hw_gis_ch1_addr0) /* 0x110 */ + mxs_reg_32(hw_gis_ch1_data0) /* 0x120 */ + mxs_reg_32(hw_gis_ch1_addr1) /* 0x130 */ + mxs_reg_32(hw_gis_ch1_data1) /* 0x140 */ + mxs_reg_32(hw_gis_ch1_addr2) /* 0x150 */ + mxs_reg_32(hw_gis_ch1_data2) /* 0x160 */ + mxs_reg_32(hw_gis_ch1_addr3) /* 0x170 */ + mxs_reg_32(hw_gis_ch1_data3) /* 0x180 */ + + mxs_reg_32(hw_gis_ch2_ctrl) /* 0x190 */ + mxs_reg_32(hw_gis_ch2_addr0) /* 0x1a0 */ + mxs_reg_32(hw_gis_ch2_data0) /* 0x1b0 */ + mxs_reg_32(hw_gis_ch2_addr1) /* 0x1c0 */ + mxs_reg_32(hw_gis_ch2_data1) /* 0x1d0 */ + mxs_reg_32(hw_gis_ch2_addr2) /* 0x1e0 */ + mxs_reg_32(hw_gis_ch2_data2) /* 0x1f0 */ + mxs_reg_32(hw_gis_ch2_addr3) /* 0x200 */ + mxs_reg_32(hw_gis_ch2_data3) /* 0x210 */ + + mxs_reg_32(hw_gis_ch3_ctrl) /* 0x220 */ + mxs_reg_32(hw_gis_ch3_addr0) /* 0x230 */ + mxs_reg_32(hw_gis_ch3_data0) /* 0x240 */ + mxs_reg_32(hw_gis_ch3_addr1) /* 0x250 */ + mxs_reg_32(hw_gis_ch3_data1) /* 0x260 */ + mxs_reg_32(hw_gis_ch3_addr2) /* 0x270 */ + mxs_reg_32(hw_gis_ch3_data2) /* 0x280 */ + mxs_reg_32(hw_gis_ch3_addr3) /* 0x290 */ + mxs_reg_32(hw_gis_ch3_data3) /* 0x2a0 */ + + mxs_reg_32(hw_gis_ch4_ctrl) /* 0x2b0 */ + mxs_reg_32(hw_gis_ch4_addr0) /* 0x2c0 */ + mxs_reg_32(hw_gis_ch4_data0) /* 0x2d0 */ + mxs_reg_32(hw_gis_ch4_addr1) /* 0x2e0 */ + mxs_reg_32(hw_gis_ch4_data1) /* 0x2f0 */ + mxs_reg_32(hw_gis_ch4_addr2) /* 0x300 */ + mxs_reg_32(hw_gis_ch4_data2) /* 0x310 */ + mxs_reg_32(hw_gis_ch4_addr3) /* 0x320 */ + mxs_reg_32(hw_gis_ch4_data3) /* 0x330 */ + + mxs_reg_32(hw_gis_ch5_ctrl) /* 0x340 */ + mxs_reg_32(hw_gis_ch5_addr0) /* 0x350 */ + mxs_reg_32(hw_gis_ch5_data0) /* 0x360 */ + mxs_reg_32(hw_gis_ch5_addr1) /* 0x370 */ + mxs_reg_32(hw_gis_ch5_data1) /* 0x380 */ + mxs_reg_32(hw_gis_ch5_addr2) /* 0x390 */ + mxs_reg_32(hw_gis_ch5_data2) /* 0x3a0 */ + mxs_reg_32(hw_gis_ch5_addr3) /* 0x3b0 */ + mxs_reg_32(hw_gis_ch5_data3) /* 0x3c0 */ + + mxs_reg_32(hw_gis_debug0) /* 0x3d0 */ + mxs_reg_32(hw_gis_debug1) /* 0x3e0 */ + mxs_reg_32(hw_gis_version) /* 0x3f0 */ +}; + +/* register bit */ +#define GIS_CTRL_SFTRST_CLR 0 +#define GIS_CTRL_SFTRST_SET (1 << 31) +#define GIS_CTRL_CLK_GATE_CLR 0 +#define GIS_CTRL_CLK_GATE_SET (1 << 30) +#define GIS_CTRL_LCDIF1_IRQ_POL_LOW 0 +#define GIS_CTRL_LCDIF1_IRQ_POL_HIGH (1 << 8) +#define GIS_CTRL_LCDIF0_IRQ_POL_LOW 0 +#define GIS_CTRL_LCDIF0_IRQ_POL_HIGH (1 << 7) +#define GIS_CTRL_PXP_IRQ_POL_LOW 0 +#define GIS_CTRL_PXP_IRQ_POL_HIGH (1 << 6) +#define GIS_CTRL_CSI1_IRQ_POL_LOW 0 +#define GIS_CTRL_CSI1_IRQ_POL_HIGH (1 << 5) +#define GIS_CTRL_CSI0_IRQ_POL_LOW 0 +#define GIS_CTRL_CSI0_IRQ_POL_HIGH (1 << 4) +#define GIS_CTRL_CSI_SEL_CSI0 0 +#define GIS_CTRL_CSI_SEL_CSI1 (1 << 3) +#define GIS_CTRL_LCDIF_SEL_LCDIF0 0 +#define GIS_CTRL_LCDIF_SEL_LCDIF1 (1 << 2) +#define GIS_CTRL_FB_START_FB0 0 +#define GIS_CTRL_FB_START_FB1 (1 << 1) +#define GIS_CTRL_ENABLE_CLR 0 +#define GIS_CTRL_ENABLE_SET (1 << 0) + +#define GIS_CONFIG0_CH3_NUM_MASK (0x7 << 27) +#define GIS_CONFIG0_CH3_NUM_SHIFT 27 +#define GIS_CONFIG0_CH3_MAPPING_MASK (0x7 << 24) +#define GIS_CONFIG0_CH3_MAPPING_SHIFT 24 +#define GIS_CONFIG0_CH2_NUM_MASK (0x7 << 19) +#define GIS_CONFIG0_CH2_NUM_SHIFT 19 +#define GIS_CONFIG0_CH2_MAPPING_MASK (0x7 << 16) +#define GIS_CONFIG0_CH2_MAPPING_SHIFT 16 +#define GIS_CONFIG0_CH1_NUM_MASK (0x7 << 11) +#define GIS_CONFIG0_CH1_NUM_SHIFT 11 +#define GIS_CONFIG0_CH1_MAPPING_MASK (0x7 << 8) +#define GIS_CONFIG0_CH1_MAPPING_SHIFT 8 +#define GIS_CONFIG0_CH0_NUM_MASK (0x7 << 3) +#define GIS_CONFIG0_CH0_NUM_SHIFT 3 +#define GIS_CONFIG0_CH0_MAPPING_MASK (0x7 << 0) +#define GIS_CONFIG0_CH0_MAPPING_SHIFT 0 + +#define GIS_CONFIG1_CH5_NUM_MASK (0x7 << 11) +#define GIS_CONFIG1_CH5_NUM_SHIFT 11 +#define GIS_CONFIG1_CH5_MAPPING_MASK (0x7 << 8) +#define GIS_CONFIG1_CH5_MAPPING_SHIFT 8 +#define GIS_CONFIG1_CH4_NUM_MASK (0x7 << 3) +#define GIS_CONFIG1_CH4_NUM_SHIFT 3 +#define GIS_CONFIG1_CH4_MAPPING_MASK (0x7 << 0) +#define GIS_CONFIG1_CH4_MAPPING_SHIFT 0 + +#define GIS_CH_CTRL_CMD3_ACC_MASK (0x1 << 31) +#define GIS_CH_CTRL_CMD3_ACC_SHIFT 31 +#define GIS_CH_CTRL_CMD3_ALU_MASK (0x7 << 28) +#define GIS_CH_CTRL_CMD3_ALU_SHIFT 28 +#define GIS_CH_CTRL_CMD3_OPCODE_MASK (0xF << 24) +#define GIS_CH_CTRL_CMD3_OPCODE_SHIFT 24 +#define GIS_CH_CTRL_CMD2_ACC_MASK (0x1 << 23) +#define GIS_CH_CTRL_CMD2_ACC_SHIFT 23 +#define GIS_CH_CTRL_CMD2_ALU_MASK (0xF << 20) +#define GIS_CH_CTRL_CMD2_ALU_SHIFT 20 +#define GIS_CH_CTRL_CMD2_OPCODE_MASK (0xF << 16) +#define GIS_CH_CTRL_CMD2_OPCODE_SHIFT 16 +#define GIS_CH_CTRL_CMD1_ACC_MASK (0x1 << 15) +#define GIS_CH_CTRL_CMD1_ACC_SHIFT 15 +#define GIS_CH_CTRL_CMD1_ALU_MASK (0x7 << 12) +#define GIS_CH_CTRL_CMD1_ALU_SHIFT 12 +#define GIS_CH_CTRL_CMD1_OPCODE_MASK (0xF << 8) +#define GIS_CH_CTRL_CMD1_OPCODE_SHIFT 8 +#define GIS_CH_CTRL_CMD0_ACC_MASK (0x1 << 7) +#define GIS_CH_CTRL_CMD0_ACC_SHIFT 7 +#define GIS_CH_CTRL_CMD0_ALU_MASK (0x7 << 4) +#define GIS_CH_CTRL_CMD0_ALU_SHIFT 4 +#define GIS_CH_CTRL_CMD0_OPCODE_MASK (0xF << 0) +#define GIS_CH_CTRL_CMD0_OPCODE_SHIFT 0 + +#define GIS_CH_CTRL_CMD_ACC_NO_NEGATE 0 +#define GIS_CH_CTRL_CMD_ACC_NEGATE 1 + +#define GIS_CH_ADDR_SEL_MASK (0xF8 << 27) +#define GIS_CH_ADDR_SEL_LCDIF1 (0x1 << 31) +#define GIS_CH_ADDR_SEL_LCDIF0 (0x1 << 30) +#define GIS_CH_ADDR_SEL_PXP (0x1 << 29) +#define GIS_CH_ADDR_SEL_CSI1 (0x1 << 28) +#define GIS_CH_ADDR_SEL_CSI0 (0x1 << 27) +#define GIS_CH_ADDR_SEL_SHIFT 27 +#define GIS_CH_ADDR_ADDR_MASK 0x7FFFFFF +#define GIS_CH_ADDR_ADDR_SHIFT 0 + +#endif + diff --git a/drivers/video/mxc_pxp.c b/drivers/video/mxc_pxp.c new file mode 100644 index 00000000000..c0446268769 --- /dev/null +++ b/drivers/video/mxc_pxp.c @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "mxc_pxp.h" + +#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 + +#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 + +#define BP_PXP_PS_CTRL_SWAP 5 +#define BM_PXP_PS_CTRL_SWAP 0x000000E0 +#define BF_PXP_PS_CTRL_SWAP(v) \ + (((v) << 5) & BM_PXP_PS_CTRL_SWAP) + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +static void pxp_set_ctrl(struct pxp_config_data *pxp_conf) +{ + u32 ctrl; + u32 fmt_ctrl; + int need_swap = 0; /* to support YUYV and YVYU formats */ + struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR; + + /* Configure S0 input format */ + switch (pxp_conf->s0_param.pixel_fmt) { + case FMT_YUV444: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; + break; + case FMT_UYVY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case FMT_YUYV: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + need_swap = 1; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_PS_CTRL_FORMAT(fmt_ctrl) | BF_PXP_PS_CTRL_SWAP(need_swap); + writel(ctrl, ®s->pxp_ps_ctrl); + + /* Configure output format based on out_channel format */ + switch (pxp_conf->out_param.pixel_fmt) { + case FMT_RGB565: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; + break; + case FMT_RGB888: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_OUT_CTRL_FORMAT(fmt_ctrl); + writel(ctrl, ®s->pxp_out_ctrl); +} + +static int pxp_set_scaling(struct pxp_config_data *pxp_conf) +{ + int ret = 0; + u32 xscale, yscale, s0scale; + u32 decx, decy, xdec = 0, ydec = 0; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR; + + decx = s0_params->width / out_params->width; + decy = s0_params->height / out_params->height; + if (decx > 1) { + if (decx >= 2 && decx < 4) { + decx = 2; + xdec = 1; + } else if (decx >= 4 && decx < 8) { + decx = 4; + xdec = 2; + } else if (decx >= 8) { + decx = 8; + xdec = 3; + } + xscale = s0_params->width * 0x1000 / + (out_params->width * decx); + } else { + if ((s0_params->pixel_fmt == FMT_YUYV) || + (s0_params->pixel_fmt == FMT_UYVY) || + (s0_params->pixel_fmt == FMT_YUV444)) + xscale = (s0_params->width - 1) * 0x1000 / + (out_params->width - 1); + else + xscale = (s0_params->width - 2) * 0x1000 / + (out_params->width - 1); + } + if (decy > 1) { + if (decy >= 2 && decy < 4) { + decy = 2; + ydec = 1; + } else if (decy >= 4 && decy < 8) { + decy = 4; + ydec = 2; + } else if (decy >= 8) { + decy = 8; + ydec = 3; + } + yscale = s0_params->height * 0x1000 / + (out_params->height * decy); + } else + yscale = (s0_params->height - 1) * 0x1000 / + (out_params->height - 1); + + writel((xdec << 10) | (ydec << 8), ®s->pxp_ps_ctrl); + + if (xscale > PXP_DOWNSCALE_THRESHOLD) + xscale = PXP_DOWNSCALE_THRESHOLD; + if (yscale > PXP_DOWNSCALE_THRESHOLD) + yscale = PXP_DOWNSCALE_THRESHOLD; + s0scale = BF_PXP_PS_SCALE_YSCALE(yscale) | + BF_PXP_PS_SCALE_XSCALE(xscale); + writel(s0scale, ®s->pxp_ps_scale); + + pxp_set_ctrl(pxp_conf); + + return ret; +} + +void pxp_power_down(void) +{ + struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR; + u32 val; + + val = BM_PXP_CTRL_SFTRST | BM_PXP_CTRL_CLKGATE; + writel(val , ®s->pxp_ctrl); +} + +void pxp_config(struct pxp_config_data *pxp_conf) +{ + struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR; + + /* reset */ + mxs_reset_block(®s->pxp_ctrl_reg); + + /* output buffer */ + if (pxp_conf->out_param.pixel_fmt == FMT_RGB888) + writel(BV_PXP_OUT_CTRL_FORMAT__RGB888, ®s->pxp_out_ctrl); + else + writel(BV_PXP_OUT_CTRL_FORMAT__RGB565, ®s->pxp_out_ctrl); + + writel((u32)pxp_conf->out_param.paddr, ®s->pxp_out_buf); + + writel(pxp_conf->out_param.stride, ®s->pxp_out_pitch); + writel((pxp_conf->out_param.width - 1) << 16 | + (pxp_conf->out_param.height - 1), + ®s->pxp_out_lrc); + + /* scale needed */ + writel(0, ®s->pxp_out_ps_ulc); + writel((pxp_conf->out_param.width - 1) << 16 | + (pxp_conf->out_param.height - 1), + ®s->pxp_out_ps_lrc); + pxp_set_scaling(pxp_conf); + + writel(0, ®s->pxp_out_as_ulc); + writel(0, ®s->pxp_out_as_lrc); + + /* input buffer */ + if (pxp_conf->s0_param.pixel_fmt == FMT_YUV444) + writel(BV_PXP_PS_CTRL_FORMAT__YUV1P444, ®s->pxp_ps_ctrl); + else if (pxp_conf->s0_param.pixel_fmt == FMT_YUYV) + writel(BV_PXP_PS_CTRL_FORMAT__UYVY1P422 | BF_PXP_PS_CTRL_SWAP(1), + ®s->pxp_ps_ctrl); + else if (pxp_conf->s0_param.pixel_fmt == FMT_UYVY) + writel(BV_PXP_PS_CTRL_FORMAT__UYVY1P422, ®s->pxp_ps_ctrl); + else + printf("%s, unsupport fmt\n", __func__); + + writel((u32)pxp_conf->s0_param.paddr, ®s->pxp_ps_buf); + writel(pxp_conf->s0_param.stride, ®s->pxp_ps_pitch); + writel(0, ®s->pxp_ps_background); + writel(0x84ab01f0, ®s->pxp_csc1_coef0); + writel(0x01980204, ®s->pxp_csc1_coef1); + writel(0x0730079c, ®s->pxp_csc1_coef2); + + /* pxp start */ + writel(BM_PXP_CTRL_IRQ_ENABLE | BM_PXP_CTRL_ENABLE, ®s->pxp_ctrl); +} diff --git a/drivers/video/mxc_pxp.h b/drivers/video/mxc_pxp.h new file mode 100644 index 00000000000..0d992ad474c --- /dev/null +++ b/drivers/video/mxc_pxp.h @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef MXC_PXP_H +#define MXC_PXP_H + +#include + +struct mxs_pxp_regs{ + mxs_reg_32(pxp_ctrl) /* 0x00 */ + mxs_reg_32(pxp_stat) /* 0x10 */ + mxs_reg_32(pxp_out_ctrl) /* 0x20 */ + mxs_reg_32(pxp_out_buf) /* 0x30 */ + mxs_reg_32(pxp_out_buf2) /* 0x40 */ + mxs_reg_32(pxp_out_pitch) /* 0x50 */ + mxs_reg_32(pxp_out_lrc) /* 0x60 */ + mxs_reg_32(pxp_out_ps_ulc) /* 0x70 */ + mxs_reg_32(pxp_out_ps_lrc) /* 0x80 */ + mxs_reg_32(pxp_out_as_ulc) /* 0x90 */ + mxs_reg_32(pxp_out_as_lrc) /* 0xa0 */ + mxs_reg_32(pxp_ps_ctrl) /* 0xb0 */ + mxs_reg_32(pxp_ps_buf) /* 0xc0 */ + mxs_reg_32(pxp_ps_ubuf) /* 0xd0 */ + mxs_reg_32(pxp_ps_vbuf) /* 0xe0 */ + mxs_reg_32(pxp_ps_pitch) /* 0xf0 */ + mxs_reg_32(pxp_ps_background) /* 0x100 */ + mxs_reg_32(pxp_ps_scale) /* 0x110 */ + mxs_reg_32(pxp_ps_offset) /* 0x120 */ + mxs_reg_32(pxp_ps_clrkeylow) /* 0x130 */ + mxs_reg_32(pxp_ps_clrkeyhigh) /* 0x140 */ + mxs_reg_32(pxp_as_ctrl) /* 0x150 */ + mxs_reg_32(pxp_as_buf) /* 0x160 */ + mxs_reg_32(pxp_as_pitch) /* 0x170 */ + mxs_reg_32(pxp_as_clrkeylow) /* 0x180 */ + mxs_reg_32(pxp_as_clrkeyhigh) /* 0x190 */ + mxs_reg_32(pxp_csc1_coef0) /* 0x1a0 */ + mxs_reg_32(pxp_csc1_coef1) /* 0x1b0 */ + mxs_reg_32(pxp_csc1_coef2) /* 0x1c0 */ + mxs_reg_32(pxp_csc2_ctrl) /* 0x1d0 */ + mxs_reg_32(pxp_csc2_coef0) /* 0x1e0 */ + mxs_reg_32(pxp_csc2_coef1) /* 0x1f0 */ + mxs_reg_32(pxp_csc2_coef2) /* 0x200 */ + mxs_reg_32(pxp_csc2_coef3) /* 0x210 */ + mxs_reg_32(pxp_csc2_coef4) /* 0x220 */ + mxs_reg_32(pxp_csc2_coef5) /* 0x230 */ + mxs_reg_32(pxp_lut_ctrl) /* 0x240 */ + mxs_reg_32(pxp_lut_addr) /* 0x250 */ + mxs_reg_32(pxp_lut_data) /* 0x260 */ + mxs_reg_32(pxp_lut_extmem) /* 0x270 */ + mxs_reg_32(pxp_cfa) /* 0x280 */ + mxs_reg_32(pxp_hist_ctrl) /* 0x290 */ + mxs_reg_32(pxp_hist2_param) /* 0x2a0 */ + mxs_reg_32(pxp_hist4_param) /* 0x2b0 */ + mxs_reg_32(pxp_hist8_param0) /* 0x2c0 */ + mxs_reg_32(pxp_hist8_param1) /* 0x2d0 */ + mxs_reg_32(pxp_hist16_param0) /* 0x2e0 */ + mxs_reg_32(pxp_hist16_param1) /* 0x2f0 */ + mxs_reg_32(pxp_hist16_param2) /* 0x300 */ + mxs_reg_32(pxp_hist16_param3) /* 0x310 */ + mxs_reg_32(pxp_power) /* 0x320 */ + uint32_t reserved1[4*13]; + mxs_reg_32(pxp_next) /* 0x400 */ +}; + +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define BM_PXP_STAT_IRQ 0x00000001 + +#define BP_PXP_OUT_CTRL_FORMAT 0 +#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F +#define BF_PXP_OUT_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) + +#define HW_PXP_PS_SCALE (0x00000110) + +#define BM_PXP_PS_SCALE_RSVD2 0x80000000 +#define BP_PXP_PS_SCALE_YSCALE 16 +#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_PS_SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) +#define BM_PXP_PS_SCALE_RSVD1 0x00008000 +#define BP_PXP_PS_SCALE_XSCALE 0 +#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF +#define BF_PXP_PS_SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) + +#define BP_PXP_PS_CTRL_SWAP 5 +#define BM_PXP_PS_CTRL_SWAP 0x000000E0 +#define BF_PXP_PS_CTRL_SWAP(v) \ + (((v) << 5) & BM_PXP_PS_CTRL_SWAP) +#define BP_PXP_PS_CTRL_FORMAT 0 +#define BM_PXP_PS_CTRL_FORMAT 0x0000001F +#define BF_PXP_PS_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 + +struct pxp_layer_param { + unsigned short width; + unsigned short height; + unsigned short stride; /* aka pitch */ + unsigned int pixel_fmt; + void *paddr; +}; + +struct pxp_config_data { + struct pxp_layer_param s0_param; + struct pxp_layer_param out_param; +}; + +void pxp_config(struct pxp_config_data *pxp_conf); + +#endif diff --git a/drivers/video/mxc_vadc.c b/drivers/video/mxc_vadc.c new file mode 100644 index 00000000000..06070d073b4 --- /dev/null +++ b/drivers/video/mxc_vadc.c @@ -0,0 +1,373 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "mxc_vadc.h" + +#define reg32_write(addr, val) __raw_writel(val, addr) +#define reg32_read(addr) __raw_readl(addr) +#define reg32setbit(addr, bitpos) \ + reg32_write((addr), (reg32_read((addr)) | (1<<(bitpos)))) + +#define reg32clrbit(addr, bitpos) \ + reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos))))) + +void __iomem *vafe_regbase; +void __iomem *vdec_regbase; + +enum { + STD_NTSC = 0, + STD_PAL, +}; + +/* Video format structure. */ +struct video_fmt_t{ + int v4l2_id; /* Video for linux ID. */ + char name[16]; /* Name (e.g., "NTSC", "PAL", etc.) */ + u16 active_width; /* Active width. */ + u16 active_height; /* Active height. */ +}; + +/* Description of video formats supported. + * + * PAL: active=720x576. + * NTSC:active=720x480. + */ +static struct video_fmt_t video_fmts[] = { + /* NTSC */ + { + .v4l2_id = STD_NTSC, + .name = "NTSC", + .active_width = 720, + .active_height = 480, + }, + /* (B, G, H, I, N) PAL */ + { + .v4l2_id = STD_PAL, + .name = "PAL", + .active_width = 720, + .active_height = 576, + }, +}; + +static void afe_voltage_clampingmode(void) +{ + reg32_write(AFE_CLAMP, 0x07); + reg32_write(AFE_CLMPAMP, 0x60); + reg32_write(AFE_CLMPDAT, 0xF0); +} + +static void afe_alwayson_clampingmode(void) +{ + reg32_write(AFE_CLAMP, 0x15); + reg32_write(AFE_CLMPDAT, 0x08); + reg32_write(AFE_CLMPAMP, 0x00); +} + +static void afe_init(void) +{ + reg32_write(AFE_PDBUF, 0x1f); + reg32_write(AFE_PDADC, 0x0f); + reg32_write(AFE_PDSARH, 0x01); + reg32_write(AFE_PDSARL, 0xff); + reg32_write(AFE_PDADCRFH, 0x01); + reg32_write(AFE_PDADCRFL, 0xff); + reg32_write(AFE_ICTRL, 0x3a); + reg32_write(AFE_ICTLSTG, 0x1e); + + reg32_write(AFE_RCTRLSTG, 0x1e); + reg32_write(AFE_INPBUF, 0x035); + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_ADCDGN, 0x40); + reg32_write(AFE_TSTSEL, 0x10); + + reg32_write(AFE_ACCTST, 0x07); + + reg32_write(AFE_BGREG, 0x08); + + reg32_write(AFE_ADCGN, 0x09); + + /* set current controlled clamping + * always on, low current */ + reg32_write(AFE_CLAMP, 0x11); + reg32_write(AFE_CLMPAMP, 0x08); +} + +static void vdec_mode_timing_init(u32 std) +{ + if (std == STD_NTSC) { + /* NTSC 720x480 */ + printf("NTSC\n"); + reg32_write(VDEC_HACTS, 0x66); + reg32_write(VDEC_HACTE, 0x24); + + reg32_write(VDEC_VACTS, 0x29); + reg32_write(VDEC_VACTE, 0x04); + + /* set V Position */ + reg32_write(VDEC_VRTPOS, 0x2); + } else if (std == STD_PAL) { + /* PAL 720x576 */ + printf("PAL\n"); + reg32_write(VDEC_HACTS, 0x66); + reg32_write(VDEC_HACTE, 0x24); + + reg32_write(VDEC_VACTS, 0x29); + reg32_write(VDEC_VACTE, 0x04); + + /* set V Position */ + reg32_write(VDEC_VRTPOS, 0x6); + } else + printf("Error not support video mode\n"); + + /* set H Position */ + reg32_write(VDEC_HZPOS, 0x60); + + /* set H ignore start */ + reg32_write(VDEC_HSIGS, 0xf8); + + /* set H ignore end */ + reg32_write(VDEC_HSIGE, 0x18); +} + +/* +* vdec_init() +* Initialises the VDEC registers +* Returns: nothing +*/ +static void vdec_init(struct sensor_data *vadc) +{ + /* Get work mode PAL or NTSC + * delay 500ms wait vdec detect input format*/ + udelay(500*1000); + vadc_get_std(vadc); + + vdec_mode_timing_init(vadc->std_id); + + /* vcr detect threshold high, automatic detections */ + reg32_write(VDEC_VSCON2, 0); + + reg32_write(VDEC_BASE + 0x110, 0x01); + + /* set the noramp mode on the Hloop PLL. */ + reg32_write(VDEC_BASE+(0x14*4), 0x10); + + /* set the YC relative delay.*/ + reg32_write(VDEC_YCDEL, 0x90); + + /* setup the Hpll */ + reg32_write(VDEC_BASE+(0x13*4), 0x13); + + /* setup the 2d comb */ + /* set the gain of the Hdetail output to 3 + * set the notch alpha gain to 1 */ + reg32_write(VDEC_CFC2, 0x34); + + /* setup various 2d comb bits.*/ + reg32_write(VDEC_BASE+(0x02*4), 0x01); + reg32_write(VDEC_BASE+(0x03*4), 0x18); + reg32_write(VDEC_BASE+(0x04*4), 0x34); + + /* set the start of the burst gate */ + reg32_write(VDEC_BRSTGT, 0x30); + + /* set 1f motion gain */ + reg32_write(VDEC_BASE+(0x0f*4), 0x20); + + /* set the 1F chroma motion detector thresh for colour reverse detection */ + reg32_write(VDEC_THSH1, 0x02); + reg32_write(VDEC_BASE+(0x4a*4), 0x20); + reg32_write(VDEC_BASE+(0x4b*4), 0x08); + + reg32_write(VDEC_BASE+(0x4c*4), 0x08); + + /* set the threshold for the narrow/wide adaptive chroma BW */ + reg32_write(VDEC_BASE+(0x20*4), 0x20); + + /* turn up the colour with the new colour gain reg */ + /* hue: */ + reg32_write(VDEC_HUE, 0x00); + + /* cbgain: 22 B4 */ + reg32_write(VDEC_CBGN, 0xb4); + /* cr gain 80 */ + reg32_write(VDEC_CRGN, 0x80); + /* luma gain (contrast) */ + reg32_write(VDEC_CNTR, 0x80); + + /* setup the signed black level register, brightness */ + reg32_write(VDEC_BRT, 0x00); + + /* filter the standard detection + * enable the comb for the ntsc443 */ + reg32_write(VDEC_STDDBG, 0x23); + + /* setup chroma kill thresh for no chroma */ + reg32_write(VDEC_CHBTH, 0x0); + + /* set chroma loop to wider BW + * no set it to normal BW. i fixed the bw problem.*/ + reg32_write(VDEC_YCDEL, 0x00); + + /* set the compensation in the chroma loop for the Hloop + * set the ratio for the nonarithmetic 3d comb modes.*/ + reg32_write(VDEC_BASE + (0x1d*4), 0x90); + + /* set the threshold for the nonarithmetic mode for the 2d comb + * the higher the value the more Fc Fh offset we will tolerate before turning off the comb. */ + reg32_write(VDEC_BASE + (0x33*4), 0xa0); + + /* setup the bluescreen output colour */ + reg32_write(VDEC_BASE + (0x3d*4), 35); + reg32_write(VDEC_BLSCRCR, 114); + reg32_write(VDEC_BLSCRCB, 212); + + /* disable the active blanking */ + reg32_write(VDEC_BASE + (0x15*4), 0x02); + + /* setup the luma agc for automatic gain. */ + reg32_write(VDEC_LMAGC2, 0x5e); + reg32_write(VDEC_BASE + (0x40*4), 0x81); + + /* setup chroma agc */ + reg32_write(VDEC_CHAGC2, 0xa0); + reg32_write(VDEC_CHAGC1, 0x01); + + /* setup the MV thresh lower nibble + * setup the sync top cap, upper nibble */ + reg32_write(VDEC_BASE + (0x3a*4), 0x80); + reg32_write(VDEC_SHPIMP, 0x00); + + /* setup the vsync block */ + reg32_write(VDEC_VSCON1, 0x87); + + /* set the nosignal threshold + * set the vsync threshold */ + reg32_write(VDEC_VSSGTH, 0x35); + + /* set length for min hphase filter (or saturate limit if saturate is chosen) */ + reg32_write(VDEC_BASE + (0x45*4), 0x40); + + /* enable the internal resampler, + * select min filter not saturate for hphase noise filter for vcr detect. + * enable vcr pause mode different field lengths */ + reg32_write(VDEC_BASE + (0x46*4), 0x90); + + /* disable VCR detection, lock to the Hsync rather than the Vsync */ + reg32_write(VDEC_VSCON2, 0x04); + + /* set tiplevel goal for dc clamp. */ + reg32_write(VDEC_BASE + (0x3c*4), 0xB0); + + /* override SECAM detection and force SECAM off */ + reg32_write(VDEC_BASE + (0x2f*4), 0x20); + + /* Set r3d_hardblend in 3D control2 reg */ + reg32_write(VDEC_BASE + (0x0c*4), 0x04); +} + +/* set Input selector & input pull-downs */ +static void vadc_select_input(int vadc_in) +{ + switch (vadc_in) { + case 0: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x1e); + break; + case 1: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x2d); + break; + case 2: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x4b); + break; + case 3: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x87); + break; + default: + printf("error video input %d\n", vadc_in); + } +} + +/*! + * Return attributes of current video standard. + * Since this device autodetects the current standard, this function also + * sets the values that need to be changed if the standard changes. + * There is no set std equivalent function. + * + * @return None. + */ +void vadc_get_std(struct sensor_data *vadc) +{ + int tmp; + int idx; + + /* Read PAL mode detected result */ + tmp = reg32_read(VDEC_VIDMOD); + tmp &= (VDEC_VIDMOD_PAL_MASK | VDEC_VIDMOD_M625_MASK); + + if (tmp) + idx = STD_PAL; + else + idx = STD_NTSC; + + vadc->std_id = idx; + vadc->pixel_fmt = FMT_YUV444; + vadc->width = video_fmts[idx].active_width; + vadc->height = video_fmts[idx].active_height; +} + +void vadc_config(u32 vadc_in) +{ + struct sensor_data vadc; + + /* map vafe,vdec,gpr,gpc address */ + vafe_regbase = (u32 *)VADC_BASE_ADDR; + vdec_regbase = (u32 *)VDEC_BASE_ADDR; + + vadc_power_up(); + + /* clock config for vadc */ + reg32_write(VDEC_BASE + 0x320, 0xe3); + reg32_write(VDEC_BASE + 0x324, 0x38); + reg32_write(VDEC_BASE + 0x328, 0x8e); + reg32_write(VDEC_BASE + 0x32c, 0x23); + mxs_set_vadcclk(); + + afe_init(); + + /* select Video Input 0-3 */ + vadc_select_input(vadc_in); + + afe_voltage_clampingmode(); + + vdec_init(&vadc); + + /* + * current control loop will move sinewave input off below + * the bottom of the signal range visible when the testbus is viewed as magnitude, + * so have to break before this point while capturing ENOB data: + */ + afe_alwayson_clampingmode(); +} + diff --git a/drivers/video/mxc_vadc.h b/drivers/video/mxc_vadc.h new file mode 100644 index 00000000000..7134b1e4328 --- /dev/null +++ b/drivers/video/mxc_vadc.h @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef MXC_VADC_H +#define MXC_VADC_H + +/*** define base address ***/ +#define VDEC_BASE vdec_regbase +#define AFE_BASE vafe_regbase + +/* AFE - Register offsets */ +#define AFE_BLOCK_ID_OFFSET 0x00000000 +#define AFE_PDBUF_OFFSET 0x00000004 +#define AFE_SWRST_OFFSET 0x00000008 +#define AFE_TSTSEL_OFFSET 0x0000000c +#define AFE_TSTMSC_OFFSET 0x00000010 +#define AFE_ENPADIO_OFFSET 0x00000014 +#define AFE_BGREG_OFFSET 0x00000018 +#define AFE_ACCESSAR_ID_OFFSET 0x00000400 +#define AFE_PDADC_OFFSET 0x00000404 +#define AFE_PDSARH_OFFSET 0x00000408 +#define AFE_PDSARL_OFFSET 0x0000040C +#define AFE_PDADCRFH_OFFSET 0x00000410 +#define AFE_PDADCRFL_OFFSET 0x00000414 +#define AFE_ACCTST_OFFSET 0x00000418 +#define AFE_ADCGN_OFFSET 0x0000041C +#define AFE_ICTRL_OFFSET 0x00000420 +#define AFE_ICTLSTG_OFFSET 0x00000424 +#define AFE_RCTRLSTG_OFFSET 0x00000428 +#define AFE_TCTRLSTG_OFFSET 0x0000042c +#define AFE_REFMOD_OFFSET 0x00000430 +#define AFE_REFTRIML_OFFSET 0x00000434 +#define AFE_REFTRIMH_OFFSET 0x00000438 +#define AFE_ADCR_OFFSET 0x0000043c +#define AFE_DUMMY0_OFFSET 0x00000440 +#define AFE_DUMMY1_OFFSET 0x00000444 +#define AFE_DUMMY2_OFFSET 0x00000448 +#define AFE_DACAMP_OFFSET 0x0000044c +#define AFE_CLMPTST_OFFSET 0x00000450 +#define AFE_CLMPDAT_OFFSET 0x00000454 +#define AFE_CLMPAMP_OFFSET 0x00000458 +#define AFE_CLAMP_OFFSET 0x0000045c +#define AFE_INPBUF_OFFSET 0x00000460 +#define AFE_INPFLT_OFFSET 0x00000464 +#define AFE_ADCDGN_OFFSET 0x00000468 +#define AFE_OFFDRV_OFFSET 0x0000046c +#define AFE_INPCONFIG_OFFSET 0x00000470 +#define AFE_PROGDELAY_OFFSET 0x00000474 +#define AFE_ADCOMT_OFFSET 0x00000478 +#define AFE_ALGDELAY_OFFSET 0x0000047c +#define AFE_ACC_ID_OFFSET 0x00000800 +#define AFE_ACCSTA_OFFSET 0x00000804 +#define AFE_ACCNOSLI_OFFSET 0x00000808 +#define AFE_ACCCALCON_OFFSET 0x0000080c +#define AFE_BWEWRICTRL_OFFSET 0x00000810 +#define AFE_SELSLI_OFFSET 0x00000814 +#define AFE_SELBYT_OFFSET 0x00000818 +#define AFE_REDVAL_OFFSET 0x00000820 +#define AFE_WRIBYT_OFFSET 0x00000824 + +/* AFE Register per module */ +#define AFE_BLOCK_ID (AFE_BASE + AFE_BLOCK_ID_OFFSET) +#define AFE_PDBUF (AFE_BASE + AFE_PDBUF_OFFSET) +#define AFE_SWRST (AFE_BASE + AFE_SWRST_OFFSET) +#define AFE_TSTSEL (AFE_BASE + AFE_TSTSEL_OFFSET) +#define AFE_TSTMSC (AFE_BASE + AFE_TSTMSC_OFFSET) +#define AFE_ENPADIO (AFE_BASE + AFE_ENPADIO_OFFSET) +#define AFE_BGREG (AFE_BASE + AFE_BGREG_OFFSET) +#define AFE_ACCESSAR_ID (AFE_BASE + AFE_ACCESSAR_ID_OFFSET) +#define AFE_PDADC (AFE_BASE + AFE_PDADC_OFFSET) +#define AFE_PDSARH (AFE_BASE + AFE_PDSARH_OFFSET) +#define AFE_PDSARL (AFE_BASE + AFE_PDSARL_OFFSET) +#define AFE_PDADCRFH (AFE_BASE + AFE_PDADCRFH_OFFSET) +#define AFE_PDADCRFL (AFE_BASE + AFE_PDADCRFL_OFFSET) +#define AFE_ACCTST (AFE_BASE + AFE_ACCTST_OFFSET) +#define AFE_ADCGN (AFE_BASE + AFE_ADCGN_OFFSET) +#define AFE_ICTRL (AFE_BASE + AFE_ICTRL_OFFSET) +#define AFE_ICTLSTG (AFE_BASE + AFE_ICTLSTG_OFFSET) +#define AFE_RCTRLSTG (AFE_BASE + AFE_RCTRLSTG_OFFSET) +#define AFE_TCTRLSTG (AFE_BASE + AFE_TCTRLSTG_OFFSET) +#define AFE_REFMOD (AFE_BASE + AFE_REFMOD_OFFSET) +#define AFE_REFTRIML (AFE_BASE + AFE_REFTRIML_OFFSET) +#define AFE_REFTRIMH (AFE_BASE + AFE_REFTRIMH_OFFSET) +#define AFE_ADCR (AFE_BASE + AFE_ADCR_OFFSET) +#define AFE_DUMMY0 (AFE_BASE + AFE_DUMMY0_OFFSET) +#define AFE_DUMMY1 (AFE_BASE + AFE_DUMMY1_OFFSET) +#define AFE_DUMMY2 (AFE_BASE + AFE_DUMMY2_OFFSET) +#define AFE_DACAMP (AFE_BASE + AFE_DACAMP_OFFSET) +#define AFE_CLMPTST (AFE_BASE + AFE_CLMPTST_OFFSET) +#define AFE_CLMPDAT (AFE_BASE + AFE_CLMPDAT_OFFSET) +#define AFE_CLMPAMP (AFE_BASE + AFE_CLMPAMP_OFFSET) +#define AFE_CLAMP (AFE_BASE + AFE_CLAMP_OFFSET) +#define AFE_INPBUF (AFE_BASE + AFE_INPBUF_OFFSET) +#define AFE_INPFLT (AFE_BASE + AFE_INPFLT_OFFSET) +#define AFE_ADCDGN (AFE_BASE + AFE_ADCDGN_OFFSET) +#define AFE_OFFDRV (AFE_BASE + AFE_OFFDRV_OFFSET) +#define AFE_INPCONFIG (AFE_BASE + AFE_INPCONFIG_OFFSET) +#define AFE_PROGDELAY (AFE_BASE + AFE_PROGDELAY_OFFSET) +#define AFE_ADCOMT (AFE_BASE + AFE_ADCOMT_OFFSET) +#define AFE_ALGDELAY (AFE_BASE + AFE_ALGDELAY_OFFSET) +#define AFE_ACC_ID (AFE_BASE + AFE_ACC_ID_OFFSET) +#define AFE_ACCSTA (AFE_BASE + AFE_ACCSTA_OFFSET) +#define AFE_ACCNOSLI (AFE_BASE + AFE_ACCNOSLI_OFFSET) +#define AFE_ACCCALCON (AFE_BASE + AFE_ACCCALCON_OFFSET) +#define AFE_BWEWRICTRL (AFE_BASE + AFE_BWEWRICTRL_OFFSET) +#define AFE_SELSLI (AFE_BASE + AFE_SELSLI_OFFSET) +#define AFE_SELBYT (AFE_BASE + AFE_SELBYT_OFFSET) +#define AFE_REDVAL (AFE_BASE + AFE_REDVAL_OFFSET) +#define AFE_WRIBYT (AFE_BASE + AFE_WRIBYT_OFFSET) + +/* VDEC - Register offsets */ +#define VDEC_CFC1_OFFSET 0x00000000 +#define VDEC_CFC2_OFFSET 0x00000004 +#define VDEC_BRSTGT_OFFSET 0x00000024 +#define VDEC_HZPOS_OFFSET 0x00000040 +#define VDEC_VRTPOS_OFFSET 0x00000044 +#define VDEC_HVSHIFT_OFFSET 0x00000054 +#define VDEC_HSIGS_OFFSET 0x00000058 +#define VDEC_HSIGE_OFFSET 0x0000005C +#define VDEC_VSCON1_OFFSET 0x00000060 +#define VDEC_VSCON2_OFFSET 0x00000064 +#define VDEC_YCDEL_OFFSET 0x0000006C +#define VDEC_AFTCLP_OFFSET 0x00000070 +#define VDEC_DCOFF_OFFSET 0x00000078 +#define VDEC_CSID_OFFSET 0x00000084 +#define VDEC_CBGN_OFFSET 0x00000088 +#define VDEC_CRGN_OFFSET 0x0000008C +#define VDEC_CNTR_OFFSET 0x00000090 +#define VDEC_BRT_OFFSET 0x00000094 +#define VDEC_HUE_OFFSET 0x00000098 +#define VDEC_CHBTH_OFFSET 0x0000009C +#define VDEC_SHPIMP_OFFSET 0x000000A4 +#define VDEC_CHPLLIM_OFFSET 0x000000A8 +#define VDEC_VIDMOD_OFFSET 0x000000AC +#define VDEC_VIDSTS_OFFSET 0x000000B0 +#define VDEC_NOISE_OFFSET 0x000000B4 +#define VDEC_STDDBG_OFFSET 0x000000B8 +#define VDEC_MANOVR_OFFSET 0x000000BC +#define VDEC_VSSGTH_OFFSET 0x000000C8 +#define VDEC_DBGFBH_OFFSET 0x000000D0 +#define VDEC_DBGFBL_OFFSET 0x000000D4 +#define VDEC_HACTS_OFFSET 0x000000D8 +#define VDEC_HACTE_OFFSET 0x000000DC +#define VDEC_VACTS_OFFSET 0x000000E0 +#define VDEC_VACTE_OFFSET 0x000000E4 +#define VDEC_HSTIP_OFFSET 0x000000EC +#define VDEC_BLSCRY_OFFSET 0x000000F4 +#define VDEC_BLSCRCR_OFFSET 0x000000F8 +#define VDEC_BLSCRCB_OFFSET 0x000000FC +#define VDEC_LMAGC2_OFFSET 0x00000104 +#define VDEC_CHAGC1_OFFSET 0x00000108 +#define VDEC_CHAGC2_OFFSET 0x0000010C +#define VDEC_MINTH_OFFSET 0x00000114 +#define VDEC_VFRQOH_OFFSET 0x0000011C +#define VDEC_VFRQOL_OFFSET 0x00000120 +#define VDEC_THSH1_OFFSET 0x00000124 +#define VDEC_THSH2_OFFSET 0x00000128 +#define VDEC_NCHTH_OFFSET 0x0000012C +#define VDEC_TH1F_OFFSET 0x00000130 + +/* VDEC Register per module */ +#define VDEC_CFC1 (VDEC_BASE + VDEC_CFC1_OFFSET) +#define VDEC_CFC2 (VDEC_BASE + VDEC_CFC2_OFFSET) +#define VDEC_BRSTGT (VDEC_BASE + VDEC_BRSTGT_OFFSET) +#define VDEC_HZPOS (VDEC_BASE + VDEC_HZPOS_OFFSET) +#define VDEC_VRTPOS (VDEC_BASE + VDEC_VRTPOS_OFFSET) +#define VDEC_HVSHIFT (VDEC_BASE + VDEC_HVSHIFT_OFFSET) +#define VDEC_HSIGS (VDEC_BASE + VDEC_HSIGS_OFFSET) +#define VDEC_HSIGE (VDEC_BASE + VDEC_HSIGE_OFFSET) +#define VDEC_VSCON1 (VDEC_BASE + VDEC_VSCON1_OFFSET) +#define VDEC_VSCON2 (VDEC_BASE + VDEC_VSCON2_OFFSET) +#define VDEC_YCDEL (VDEC_BASE + VDEC_YCDEL_OFFSET) +#define VDEC_AFTCLP (VDEC_BASE + VDEC_AFTCLP_OFFSET) +#define VDEC_DCOFF (VDEC_BASE + VDEC_DCOFF_OFFSET) +#define VDEC_CSID (VDEC_BASE + VDEC_CSID_OFFSET) +#define VDEC_CBGN (VDEC_BASE + VDEC_CBGN_OFFSET) +#define VDEC_CRGN (VDEC_BASE + VDEC_CRGN_OFFSET) +#define VDEC_CNTR (VDEC_BASE + VDEC_CNTR_OFFSET) +#define VDEC_BRT (VDEC_BASE + VDEC_BRT_OFFSET) +#define VDEC_HUE (VDEC_BASE + VDEC_HUE_OFFSET) +#define VDEC_CHBTH (VDEC_BASE + VDEC_CHBTH_OFFSET) +#define VDEC_SHPIMP (VDEC_BASE + VDEC_SHPIMP_OFFSET) +#define VDEC_CHPLLIM (VDEC_BASE + VDEC_CHPLLIM_OFFSET) +#define VDEC_VIDMOD (VDEC_BASE + VDEC_VIDMOD_OFFSET) +#define VDEC_VIDSTS (VDEC_BASE + VDEC_VIDSTS_OFFSET) +#define VDEC_NOISE (VDEC_BASE + VDEC_NOISE_OFFSET) +#define VDEC_STDDBG (VDEC_BASE + VDEC_STDDBG_OFFSET) +#define VDEC_MANOVR (VDEC_BASE + VDEC_MANOVR_OFFSET) +#define VDEC_VSSGTH (VDEC_BASE + VDEC_VSSGTH_OFFSET) +#define VDEC_DBGFBH (VDEC_BASE + VDEC_DBGFBH_OFFSET) +#define VDEC_DBGFBL (VDEC_BASE + VDEC_DBGFBL_OFFSET) +#define VDEC_HACTS (VDEC_BASE + VDEC_HACTS_OFFSET) +#define VDEC_HACTE (VDEC_BASE + VDEC_HACTE_OFFSET) +#define VDEC_VACTS (VDEC_BASE + VDEC_VACTS_OFFSET) +#define VDEC_VACTE (VDEC_BASE + VDEC_VACTE_OFFSET) +#define VDEC_HSTIP (VDEC_BASE + VDEC_HSTIP_OFFSET) +#define VDEC_BLSCRY (VDEC_BASE + VDEC_BLSCRY_OFFSET) +#define VDEC_BLSCRCR (VDEC_BASE + VDEC_BLSCRCR_OFFSET) +#define VDEC_BLSCRCB (VDEC_BASE + VDEC_BLSCRCB_OFFSET) +#define VDEC_LMAGC2 (VDEC_BASE + VDEC_LMAGC2_OFFSET) +#define VDEC_CHAGC1 (VDEC_BASE + VDEC_CHAGC1_OFFSET) +#define VDEC_CHAGC2 (VDEC_BASE + VDEC_CHAGC2_OFFSET) +#define VDEC_MINTH (VDEC_BASE + VDEC_MINTH_OFFSET) +#define VDEC_VFRQOH (VDEC_BASE + VDEC_VFRQOH_OFFSET) +#define VDEC_VFRQOL (VDEC_BASE + VDEC_VFRQOL_OFFSET) +#define VDEC_THSH1 (VDEC_BASE + VDEC_THSH1_OFFSET) +#define VDEC_THSH2 (VDEC_BASE + VDEC_THSH2_OFFSET) +#define VDEC_NCHTH (VDEC_BASE + VDEC_NCHTH_OFFSET) +#define VDEC_TH1F (VDEC_BASE + VDEC_TH1F_OFFSET) + +#define VDEC_VIDMOD_M625_SHIFT 4 +#define VDEC_VIDMOD_M625_MASK (1 << VDEC_VIDMOD_M625_SHIFT) + +#define VDEC_VIDMOD_PAL_SHIFT 7 +#define VDEC_VIDMOD_PAL_MASK (1 << VDEC_VIDMOD_PAL_SHIFT) + +struct sensor_data { + u32 width; + u32 height; + u32 pixel_fmt; + u32 std_id; +}; + +void vadc_config(u32 vadc_in); +void vadc_get_std(struct sensor_data *vadc); + +#endif diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 9d810bab31d..838c037e5b9 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -3,6 +3,9 @@ * * Copyright (C) 2011-2013 Marek Vasut * + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -18,6 +21,18 @@ #include #include "videomodes.h" +#include +#include +#include +#include + +#ifdef CONFIG_VIDEO_GIS +#include +#endif + +#ifdef CONFIG_IMX_MIPI_DSI_BRIDGE +#include +#endif #define PS2KHZ(ps) (1000000000UL / (ps)) @@ -35,6 +50,31 @@ __weak void mxsfb_system_setup(void) { } +static int setup; +static struct fb_videomode fbmode; +static int depth; + +int mxs_lcd_panel_setup(struct fb_videomode mode, int bpp, + uint32_t base_addr) +{ + fbmode = mode; + depth = bpp; + panel.isaBase = base_addr; + + setup = 1; + + return 0; +} + +void mxs_lcd_get_panel(struct display_panel *dispanel) +{ + dispanel->width = fbmode.xres; + dispanel->height = fbmode.yres; + dispanel->reg_base = panel.isaBase; + dispanel->gdfindex = panel.gdfIndex; + dispanel->gdfbytespp = panel.gdfBytesPP; +} + /* * ARIES M28EVK: * setenv videomode @@ -50,12 +90,12 @@ __weak void mxsfb_system_setup(void) static void mxs_lcd_init(GraphicDevice *panel, struct ctfb_res_modes *mode, int bpp) { - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)(ulong)(panel->isaBase); uint32_t word_len = 0, bus_width = 0; uint8_t valid_data = 0; /* Kick in the LCDIF clock */ - mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock)); + mxs_set_lcdclk(panel->isaBase, PS2KHZ(mode->pixclock)); /* Restart the LCDIF block */ mxs_reset_block(®s->hw_lcdif_ctrl_reg); @@ -90,15 +130,26 @@ static void mxs_lcd_init(GraphicDevice *panel, writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET, ®s->hw_lcdif_ctrl1); +#ifdef CONFIG_IMX_MIPI_DSI_BRIDGE + writel(LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16, ®s->hw_lcdif_ctrl2); +#endif + mxsfb_system_setup(); writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres, ®s->hw_lcdif_transfer_count); +#ifdef CONFIG_IMX_SEC_MIPI_DSI + writel(LCDIF_VDCTRL0_ENABLE_PRESENT | + LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | + mode->vsync_len, ®s->hw_lcdif_vdctrl0); +#else writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL | LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | mode->vsync_len, ®s->hw_lcdif_vdctrl0); +#endif writel(mode->upper_margin + mode->lower_margin + mode->vsync_len + mode->yres, ®s->hw_lcdif_vdctrl1); @@ -133,12 +184,20 @@ static void mxs_lcd_init(GraphicDevice *panel, void lcdif_power_down(void) { - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)(ulong)(panel.isaBase); int timeout = 1000000; +#ifdef CONFIG_MX6 + if (check_module_fused(MX6_MODULE_LCDIF)) + return; +#endif if (!panel.frameAdrs) return; +#ifdef CONFIG_IMX_MIPI_DSI_BRIDGE + imx_mipi_dsi_bridge_disable(); +#endif + writel(panel.frameAdrs, ®s->hw_lcdif_cur_buf_reg); writel(panel.frameAdrs, ®s->hw_lcdif_next_buf_reg); writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr); @@ -160,19 +219,43 @@ void *video_hw_init(void) puts("Video: "); - /* Suck display configuration from "videomode" variable */ - penv = env_get("videomode"); - if (!penv) { - puts("MXSFB: 'videomode' variable not set!\n"); - return NULL; + if (!setup) { + + /* Suck display configuration from "videomode" variable */ + penv = env_get("videomode"); + if (!penv) { + printf("MXSFB: 'videomode' variable not set!\n"); + return NULL; + } + + bpp = video_get_params(&mode, penv); + panel.isaBase = MXS_LCDIF_BASE; + } else { + mode.xres = fbmode.xres; + mode.yres = fbmode.yres; + mode.pixclock = fbmode.pixclock; + mode.left_margin = fbmode.left_margin; + mode.right_margin = fbmode.right_margin; + mode.upper_margin = fbmode.upper_margin; + mode.lower_margin = fbmode.lower_margin; + mode.hsync_len = fbmode.hsync_len; + mode.vsync_len = fbmode.vsync_len; + mode.sync = fbmode.sync; + mode.vmode = fbmode.vmode; + bpp = depth; } - bpp = video_get_params(&mode, penv); - +#ifdef CONFIG_MX6 + if (check_module_fused(MX6_MODULE_LCDIF)) { + printf("LCDIF@0x%x is fused, disable it\n", MXS_LCDIF_BASE); + return NULL; + } +#endif /* fill in Graphic device struct */ sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp); + panel.winSizeX = mode.xres; panel.winSizeY = mode.yres; panel.plnSizeX = mode.xres; @@ -199,6 +282,7 @@ void *video_hw_init(void) panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP; + /* Allocate framebuffer */ fb = memalign(ARCH_DMA_MINALIGN, roundup(panel.memSize, ARCH_DMA_MINALIGN)); @@ -210,10 +294,15 @@ void *video_hw_init(void) /* Wipe framebuffer */ memset(fb, 0, panel.memSize); - panel.frameAdrs = (u32)fb; + panel.frameAdrs = (ulong)fb; printf("%s\n", panel.modeIdent); +#ifdef CONFIG_IMX_MIPI_DSI_BRIDGE + imx_mipi_dsi_bridge_mode_set(&fbmode); + imx_mipi_dsi_bridge_enable(); +#endif + /* Start framebuffer */ mxs_lcd_init(&panel, &mode, bpp); @@ -240,5 +329,10 @@ void *video_hw_init(void) mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc); #endif +#ifdef CONFIG_VIDEO_GIS + /* Entry for GIS */ + mxc_enable_gis(); +#endif + return (void *)&panel; } diff --git a/drivers/video/rm67191.c b/drivers/video/rm67191.c new file mode 100644 index 00000000000..4ef907f5ddd --- /dev/null +++ b/drivers/video/rm67191.c @@ -0,0 +1,362 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define CMD_TABLE_LEN 2 +typedef u8 cmd_set_table[CMD_TABLE_LEN]; + +/* Write Manufacture Command Set Control */ +#define WRMAUCCTR 0xFE + +/* Manufacturer Command Set pages (CMD2) */ +static const cmd_set_table manufacturer_cmd_set[] = { + {0xFE, 0x0B}, + {0x28, 0x40}, + {0x29, 0x4F}, + {0xFE, 0x0E}, + {0x4B, 0x00}, + {0x4C, 0x0F}, + {0x4D, 0x20}, + {0x4E, 0x40}, + {0x4F, 0x60}, + {0x50, 0xA0}, + {0x51, 0xC0}, + {0x52, 0xE0}, + {0x53, 0xFF}, + {0xFE, 0x0D}, + {0x18, 0x08}, + {0x42, 0x00}, + {0x08, 0x41}, + {0x46, 0x02}, + {0x72, 0x09}, + {0xFE, 0x0A}, + {0x24, 0x17}, + {0x04, 0x07}, + {0x1A, 0x0C}, + {0x0F, 0x44}, + {0xFE, 0x04}, + {0x00, 0x0C}, + {0x05, 0x08}, + {0x06, 0x08}, + {0x08, 0x08}, + {0x09, 0x08}, + {0x0A, 0xE6}, + {0x0B, 0x8C}, + {0x1A, 0x12}, + {0x1E, 0xE0}, + {0x29, 0x93}, + {0x2A, 0x93}, + {0x2F, 0x02}, + {0x31, 0x02}, + {0x33, 0x05}, + {0x37, 0x2D}, + {0x38, 0x2D}, + {0x3A, 0x1E}, + {0x3B, 0x1E}, + {0x3D, 0x27}, + {0x3F, 0x80}, + {0x40, 0x40}, + {0x41, 0xE0}, + {0x4F, 0x2F}, + {0x50, 0x1E}, + {0xFE, 0x06}, + {0x00, 0xCC}, + {0x05, 0x05}, + {0x07, 0xA2}, + {0x08, 0xCC}, + {0x0D, 0x03}, + {0x0F, 0xA2}, + {0x32, 0xCC}, + {0x37, 0x05}, + {0x39, 0x83}, + {0x3A, 0xCC}, + {0x41, 0x04}, + {0x43, 0x83}, + {0x44, 0xCC}, + {0x49, 0x05}, + {0x4B, 0xA2}, + {0x4C, 0xCC}, + {0x51, 0x03}, + {0x53, 0xA2}, + {0x75, 0xCC}, + {0x7A, 0x03}, + {0x7C, 0x83}, + {0x7D, 0xCC}, + {0x82, 0x02}, + {0x84, 0x83}, + {0x85, 0xEC}, + {0x86, 0x0F}, + {0x87, 0xFF}, + {0x88, 0x00}, + {0x8A, 0x02}, + {0x8C, 0xA2}, + {0x8D, 0xEA}, + {0x8E, 0x01}, + {0x8F, 0xE8}, + {0xFE, 0x06}, + {0x90, 0x0A}, + {0x92, 0x06}, + {0x93, 0xA0}, + {0x94, 0xA8}, + {0x95, 0xEC}, + {0x96, 0x0F}, + {0x97, 0xFF}, + {0x98, 0x00}, + {0x9A, 0x02}, + {0x9C, 0xA2}, + {0xAC, 0x04}, + {0xFE, 0x06}, + {0xB1, 0x12}, + {0xB2, 0x17}, + {0xB3, 0x17}, + {0xB4, 0x17}, + {0xB5, 0x17}, + {0xB6, 0x11}, + {0xB7, 0x08}, + {0xB8, 0x09}, + {0xB9, 0x06}, + {0xBA, 0x07}, + {0xBB, 0x17}, + {0xBC, 0x17}, + {0xBD, 0x17}, + {0xBE, 0x17}, + {0xBF, 0x17}, + {0xC0, 0x17}, + {0xC1, 0x17}, + {0xC2, 0x17}, + {0xC3, 0x17}, + {0xC4, 0x0F}, + {0xC5, 0x0E}, + {0xC6, 0x00}, + {0xC7, 0x01}, + {0xC8, 0x10}, + {0xFE, 0x06}, + {0x95, 0xEC}, + {0x8D, 0xEE}, + {0x44, 0xEC}, + {0x4C, 0xEC}, + {0x32, 0xEC}, + {0x3A, 0xEC}, + {0x7D, 0xEC}, + {0x75, 0xEC}, + {0x00, 0xEC}, + {0x08, 0xEC}, + {0x85, 0xEC}, + {0xA6, 0x21}, + {0xA7, 0x05}, + {0xA9, 0x06}, + {0x82, 0x06}, + {0x41, 0x06}, + {0x7A, 0x07}, + {0x37, 0x07}, + {0x05, 0x06}, + {0x49, 0x06}, + {0x0D, 0x04}, + {0x51, 0x04}, +}; + +static u8 color_format_from_dsi_format(enum mipi_dsi_pixel_format format) +{ + switch (format) { + case MIPI_DSI_FMT_RGB565: + return 0x55; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + return 0x66; + case MIPI_DSI_FMT_RGB888: + return 0x77; + default: + return 0x77; /* for backward compatibility */ + } +}; + +static int mipi_dsi_generic_write(const void *payload, size_t size) +{ + int ret; + u16 tx_buf; + u8 *tx; + + tx_buf = 0; + tx = (u8 *)&tx_buf; + + switch (size) { + case 0: + ret = imx_mipi_dsi_bridge_pkt_write(MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, tx, 0); + break; + + case 1: + tx[0] = *(u8 *)payload; + ret = imx_mipi_dsi_bridge_pkt_write(MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM, tx, 0); + break; + + case 2: + ret = imx_mipi_dsi_bridge_pkt_write(MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM, (const u8 *)payload, 0); + break; + + default: + ret = imx_mipi_dsi_bridge_pkt_write(MIPI_DSI_GENERIC_LONG_WRITE, (const u8 *)payload, size); + break; + } + + return ret; +} + +static int mipi_dsi_dcs_write(u8 cmd, const void *data, size_t len) +{ + u32 size; + u8 *tx; + u16 tx_buf; + int ret; + + if (len > 0) { + size = 1 + len; + + tx = kmalloc(size, GFP_KERNEL); + if (!tx) + return -ENOMEM; + + /* concatenate the DCS command byte and the payload */ + tx[0] = cmd; + memcpy(&tx[1], data, len); + } else { + tx = (u8 *)&tx_buf; + tx[0] = cmd; + tx[1] = 0; + size = 1; + } + + switch (size) { + case 1: + ret = imx_mipi_dsi_bridge_pkt_write(MIPI_DSI_DCS_SHORT_WRITE, tx, 0); + break; + + case 2: + ret = imx_mipi_dsi_bridge_pkt_write(MIPI_DSI_DCS_SHORT_WRITE_PARAM, tx, 0); + break; + + default: + ret = imx_mipi_dsi_bridge_pkt_write(MIPI_DSI_DCS_LONG_WRITE, tx, size); + break; + } + + if (len > 0) + kfree(tx); + + return ret; +} + +static int rad_panel_push_cmd_list(void) +{ + size_t i; + const u8 *cmd; + size_t count = sizeof(manufacturer_cmd_set) / CMD_TABLE_LEN; + int ret = 0; + + for (i = 0; i < count ; i++) { + cmd = manufacturer_cmd_set[i]; + ret = mipi_dsi_generic_write(cmd, CMD_TABLE_LEN); + if (ret < 0) + return ret; + } + + return ret; +}; + +int rm67191_lcd_setup(struct mipi_dsi_client_dev *panel_dev) +{ + u8 color_format = color_format_from_dsi_format(panel_dev->format); + u16 brightness; + int ret; + + ret = rad_panel_push_cmd_list(); + if (ret < 0) { + printf("Failed to send MCS (%d)\n", ret); + return -EIO; + } + + /* Select User Command Set table (CMD1) */ + ret = mipi_dsi_generic_write((u8[]){ WRMAUCCTR, 0x00 }, 2); + if (ret < 0) + return -EIO; + + /* Software reset */ + ret = mipi_dsi_dcs_write(MIPI_DCS_SOFT_RESET, NULL, 0); + if (ret < 0) { + printf("Failed to do Software Reset (%d)\n", ret); + return -EIO; + } + + mdelay(10); + + /* Set DSI mode */ + ret = mipi_dsi_generic_write((u8[]){ 0xC2, 0x0B }, 2); + if (ret < 0) { + printf("Failed to set DSI mode (%d)\n", ret); + return -EIO; + } + + /* Set tear ON */ + ret = mipi_dsi_dcs_write(MIPI_DCS_SET_TEAR_ON, (u8[]){ 0x0 }, 1); + if (ret < 0) { + printf("Failed to set tear ON (%d)\n", ret); + return -EIO; + } + + /* Set tear scanline */ + ret = mipi_dsi_generic_write((u8[]){ MIPI_DCS_SET_TEAR_SCANLINE, 0x3, 0x80 }, 3); + if (ret < 0) { + printf("Failed to set tear scanline (%d)\n", ret); + return -EIO; + } + + /* Set pixel format */ + ret = mipi_dsi_dcs_write(MIPI_DCS_SET_PIXEL_FORMAT, &color_format, 1); + if (ret < 0) { + printf("Failed to set pixel format (%d)\n", ret); + return -EIO; + } + + + /* Set display brightness */ + brightness = 255; /* Max brightness */ + ret = mipi_dsi_dcs_write(MIPI_DCS_SET_DISPLAY_BRIGHTNESS, &brightness, 2); + if (ret < 0) { + printf("Failed to set display brightness (%d)\n", + ret); + return -EIO; + } + + /* Exit sleep mode */ + ret = mipi_dsi_dcs_write(MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0); + if (ret < 0) { + printf("Failed to exit sleep mode (%d)\n", ret); + return -EIO; + } + + mdelay(5); + + ret = mipi_dsi_dcs_write(MIPI_DCS_SET_DISPLAY_ON, NULL, 0); + if (ret < 0) { + printf("Failed to set display ON (%d)\n", ret); + return -EIO; + } + + return 0; +} + +static struct mipi_dsi_client_driver rm67191_drv = { + .name = "RM67191_OLED", + .dsi_client_setup = rm67191_lcd_setup, +}; + +void rm67191_init(void) +{ + imx_mipi_dsi_bridge_add_client_driver(&rm67191_drv); +} diff --git a/drivers/video/rm68200.c b/drivers/video/rm68200.c new file mode 100644 index 00000000000..4a0a7130def --- /dev/null +++ b/drivers/video/rm68200.c @@ -0,0 +1,362 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + + +#define CHECK_RETCODE(ret) \ +do { \ + if (ret < 0) { \ + printf("%s ERR: ret:%d, line:%d.\n", \ + __func__, ret, __LINE__); \ + return ret; \ + } \ +} while (0) + +static void parse_variadic(int n, u8 *buf, ...) +{ + int i = 0; + va_list args; + + if (unlikely(!n)) + return; + + va_start(args, buf); + + for (i = 0; i < n; i++) + buf[i + 1] = (u8)va_arg(args, int); + + va_end(args); +} + +#define RM68200_DCS_write_1A_nP(n, addr, ...) { \ + int err; \ + \ + buf[0] = addr; \ + parse_variadic(n, buf, ##__VA_ARGS__); \ + \ + if (n >= 2) \ + err = imx_mipi_dsi_bridge_pkt_write( \ + MIPI_DSI_DCS_LONG_WRITE, (u8 *)buf, n + 1); \ + else if (n == 1) \ + err = imx_mipi_dsi_bridge_pkt_write( \ + MIPI_DSI_DCS_SHORT_WRITE_PARAM, (u8 *)buf, 0); \ + else if (n == 0) { \ + buf[1] = 0; \ + err = imx_mipi_dsi_bridge_pkt_write( \ + MIPI_DSI_DCS_SHORT_WRITE, (u8 *)buf, 0); \ + } \ + CHECK_RETCODE(err); \ +} + +#define RM68200_DCS_write_1A_0P(addr) \ + RM68200_DCS_write_1A_nP(0, addr) + +#define RM68200_DCS_write_1A_1P(addr, ...) \ + RM68200_DCS_write_1A_nP(1, addr, __VA_ARGS__) + + +int mipid_rm68200_lcd_setup(struct mipi_dsi_client_dev *panel_dev) +{ + u8 buf[DSI_CMD_BUF_MAXSIZE]; + + debug("MIPI DSI LCD RM68200 setup.\n"); + + /* change to MCS Page 0 */ + RM68200_DCS_write_1A_1P(0xFE, 0x01); + RM68200_DCS_write_1A_1P(0x24, 0xc0); /* External PWR IC Control */ + RM68200_DCS_write_1A_1P(0x25, 0x53); + RM68200_DCS_write_1A_1P(0x26, 0x00); + RM68200_DCS_write_1A_1P(0x2B, 0xE5); + RM68200_DCS_write_1A_1P(0x27, 0x0A); + RM68200_DCS_write_1A_1P(0x29, 0x0A); + RM68200_DCS_write_1A_1P(0x16, 0x52); + RM68200_DCS_write_1A_1P(0x2F, 0x53); + RM68200_DCS_write_1A_1P(0x34, 0x5A); + RM68200_DCS_write_1A_1P(0x1B, 0x00); + RM68200_DCS_write_1A_1P(0x12, 0x0A); + RM68200_DCS_write_1A_1P(0x1A, 0x06); + RM68200_DCS_write_1A_1P(0x46, 0x56); + RM68200_DCS_write_1A_1P(0x52, 0xA0); + RM68200_DCS_write_1A_1P(0x53, 0x00); + RM68200_DCS_write_1A_1P(0x54, 0xA0); + RM68200_DCS_write_1A_1P(0x55, 0x00); + RM68200_DCS_write_1A_1P(0x5F, 0x11); /* 2 data lanes */ + + /* change to MCS Page 2 */ + RM68200_DCS_write_1A_1P(0xFE, 0x03); + RM68200_DCS_write_1A_1P(0x00, 0x05); + RM68200_DCS_write_1A_1P(0x02, 0x0B); + RM68200_DCS_write_1A_1P(0x03, 0x0F); + RM68200_DCS_write_1A_1P(0x04, 0x7D); + RM68200_DCS_write_1A_1P(0x05, 0x00); + RM68200_DCS_write_1A_1P(0x06, 0x50); + RM68200_DCS_write_1A_1P(0x07, 0x05); + RM68200_DCS_write_1A_1P(0x08, 0x16); + RM68200_DCS_write_1A_1P(0x09, 0x0D); + RM68200_DCS_write_1A_1P(0x0A, 0x11); + RM68200_DCS_write_1A_1P(0x0B, 0x7D); + RM68200_DCS_write_1A_1P(0x0C, 0x00); + RM68200_DCS_write_1A_1P(0x0D, 0x50); + RM68200_DCS_write_1A_1P(0x0E, 0x07); + RM68200_DCS_write_1A_1P(0x0F, 0x08); + RM68200_DCS_write_1A_1P(0x10, 0x01); + RM68200_DCS_write_1A_1P(0x11, 0x02); + RM68200_DCS_write_1A_1P(0x12, 0x00); + RM68200_DCS_write_1A_1P(0x13, 0x7D); + RM68200_DCS_write_1A_1P(0x14, 0x00); + RM68200_DCS_write_1A_1P(0x15, 0x85); + RM68200_DCS_write_1A_1P(0x16, 0x08); + RM68200_DCS_write_1A_1P(0x17, 0x03); + RM68200_DCS_write_1A_1P(0x18, 0x04); + RM68200_DCS_write_1A_1P(0x19, 0x05); + RM68200_DCS_write_1A_1P(0x1A, 0x06); + RM68200_DCS_write_1A_1P(0x1B, 0x00); + RM68200_DCS_write_1A_1P(0x1C, 0x7D); + RM68200_DCS_write_1A_1P(0x1D, 0x00); + RM68200_DCS_write_1A_1P(0x1E, 0x85); + RM68200_DCS_write_1A_1P(0x1F, 0x08); + RM68200_DCS_write_1A_1P(0x20, 0x00); + RM68200_DCS_write_1A_1P(0x21, 0x00); + RM68200_DCS_write_1A_1P(0x22, 0x00); + RM68200_DCS_write_1A_1P(0x23, 0x00); + RM68200_DCS_write_1A_1P(0x24, 0x00); + RM68200_DCS_write_1A_1P(0x25, 0x00); + RM68200_DCS_write_1A_1P(0x26, 0x00); + RM68200_DCS_write_1A_1P(0x27, 0x00); + RM68200_DCS_write_1A_1P(0x28, 0x00); + RM68200_DCS_write_1A_1P(0x29, 0x00); + RM68200_DCS_write_1A_1P(0x2A, 0x07); + RM68200_DCS_write_1A_1P(0x2B, 0x08); + RM68200_DCS_write_1A_1P(0x2D, 0x01); + RM68200_DCS_write_1A_1P(0x2F, 0x02); + RM68200_DCS_write_1A_1P(0x30, 0x00); + RM68200_DCS_write_1A_1P(0x31, 0x40); + RM68200_DCS_write_1A_1P(0x32, 0x05); + RM68200_DCS_write_1A_1P(0x33, 0x08); + RM68200_DCS_write_1A_1P(0x34, 0x54); + RM68200_DCS_write_1A_1P(0x35, 0x7D); + RM68200_DCS_write_1A_1P(0x36, 0x00); + RM68200_DCS_write_1A_1P(0x37, 0x03); + RM68200_DCS_write_1A_1P(0x38, 0x04); + RM68200_DCS_write_1A_1P(0x39, 0x05); + RM68200_DCS_write_1A_1P(0x3A, 0x06); + RM68200_DCS_write_1A_1P(0x3B, 0x00); + RM68200_DCS_write_1A_1P(0x3D, 0x40); + RM68200_DCS_write_1A_1P(0x3F, 0x05); + RM68200_DCS_write_1A_1P(0x40, 0x08); + RM68200_DCS_write_1A_1P(0x41, 0x54); + RM68200_DCS_write_1A_1P(0x42, 0x7D); + RM68200_DCS_write_1A_1P(0x43, 0x00); + RM68200_DCS_write_1A_1P(0x44, 0x00); + RM68200_DCS_write_1A_1P(0x45, 0x00); + RM68200_DCS_write_1A_1P(0x46, 0x00); + RM68200_DCS_write_1A_1P(0x47, 0x00); + RM68200_DCS_write_1A_1P(0x48, 0x00); + RM68200_DCS_write_1A_1P(0x49, 0x00); + RM68200_DCS_write_1A_1P(0x4A, 0x00); + RM68200_DCS_write_1A_1P(0x4B, 0x00); + RM68200_DCS_write_1A_1P(0x4C, 0x00); + RM68200_DCS_write_1A_1P(0x4D, 0x00); + RM68200_DCS_write_1A_1P(0x4E, 0x00); + RM68200_DCS_write_1A_1P(0x4F, 0x00); + RM68200_DCS_write_1A_1P(0x50, 0x00); + RM68200_DCS_write_1A_1P(0x51, 0x00); + RM68200_DCS_write_1A_1P(0x52, 0x00); + RM68200_DCS_write_1A_1P(0x53, 0x00); + RM68200_DCS_write_1A_1P(0x54, 0x00); + RM68200_DCS_write_1A_1P(0x55, 0x00); + RM68200_DCS_write_1A_1P(0x56, 0x00); + RM68200_DCS_write_1A_1P(0x58, 0x00); + RM68200_DCS_write_1A_1P(0x59, 0x00); + RM68200_DCS_write_1A_1P(0x5A, 0x00); + RM68200_DCS_write_1A_1P(0x5B, 0x00); + RM68200_DCS_write_1A_1P(0x5C, 0x00); + RM68200_DCS_write_1A_1P(0x5D, 0x00); + RM68200_DCS_write_1A_1P(0x5E, 0x00); + RM68200_DCS_write_1A_1P(0x5F, 0x00); + RM68200_DCS_write_1A_1P(0x60, 0x00); + RM68200_DCS_write_1A_1P(0x61, 0x00); + RM68200_DCS_write_1A_1P(0x62, 0x00); + RM68200_DCS_write_1A_1P(0x63, 0x00); + RM68200_DCS_write_1A_1P(0x64, 0x00); + RM68200_DCS_write_1A_1P(0x65, 0x00); + RM68200_DCS_write_1A_1P(0x66, 0x00); + RM68200_DCS_write_1A_1P(0x67, 0x00); + RM68200_DCS_write_1A_1P(0x68, 0x00); + RM68200_DCS_write_1A_1P(0x69, 0x00); + RM68200_DCS_write_1A_1P(0x6A, 0x00); + RM68200_DCS_write_1A_1P(0x6B, 0x00); + RM68200_DCS_write_1A_1P(0x6C, 0x00); + RM68200_DCS_write_1A_1P(0x6D, 0x00); + RM68200_DCS_write_1A_1P(0x6E, 0x00); + RM68200_DCS_write_1A_1P(0x6F, 0x00); + RM68200_DCS_write_1A_1P(0x70, 0x00); + RM68200_DCS_write_1A_1P(0x71, 0x00); + RM68200_DCS_write_1A_1P(0x72, 0x20); + RM68200_DCS_write_1A_1P(0x73, 0x00); + RM68200_DCS_write_1A_1P(0x74, 0x08); + RM68200_DCS_write_1A_1P(0x75, 0x08); + RM68200_DCS_write_1A_1P(0x76, 0x08); + RM68200_DCS_write_1A_1P(0x77, 0x08); + RM68200_DCS_write_1A_1P(0x78, 0x08); + RM68200_DCS_write_1A_1P(0x79, 0x08); + RM68200_DCS_write_1A_1P(0x7A, 0x00); + RM68200_DCS_write_1A_1P(0x7B, 0x00); + RM68200_DCS_write_1A_1P(0x7C, 0x00); + RM68200_DCS_write_1A_1P(0x7D, 0x00); + RM68200_DCS_write_1A_1P(0x7E, 0xBF); + RM68200_DCS_write_1A_1P(0x7F, 0x02); + RM68200_DCS_write_1A_1P(0x80, 0x06); + RM68200_DCS_write_1A_1P(0x81, 0x14); + RM68200_DCS_write_1A_1P(0x82, 0x10); + RM68200_DCS_write_1A_1P(0x83, 0x16); + RM68200_DCS_write_1A_1P(0x84, 0x12); + RM68200_DCS_write_1A_1P(0x85, 0x08); + RM68200_DCS_write_1A_1P(0x86, 0x3F); + RM68200_DCS_write_1A_1P(0x87, 0x3F); + RM68200_DCS_write_1A_1P(0x88, 0x3F); + RM68200_DCS_write_1A_1P(0x89, 0x3F); + RM68200_DCS_write_1A_1P(0x8A, 0x3F); + RM68200_DCS_write_1A_1P(0x8B, 0x0C); + RM68200_DCS_write_1A_1P(0x8C, 0x0A); + RM68200_DCS_write_1A_1P(0x8D, 0x0E); + RM68200_DCS_write_1A_1P(0x8E, 0x3F); + RM68200_DCS_write_1A_1P(0x8F, 0x3F); + RM68200_DCS_write_1A_1P(0x90, 0x00); + RM68200_DCS_write_1A_1P(0x91, 0x04); + RM68200_DCS_write_1A_1P(0x92, 0x3F); + RM68200_DCS_write_1A_1P(0x93, 0x3F); + RM68200_DCS_write_1A_1P(0x94, 0x3F); + RM68200_DCS_write_1A_1P(0x95, 0x3F); + RM68200_DCS_write_1A_1P(0x96, 0x05); + RM68200_DCS_write_1A_1P(0x97, 0x01); + RM68200_DCS_write_1A_1P(0x98, 0x3F); + RM68200_DCS_write_1A_1P(0x99, 0x3F); + RM68200_DCS_write_1A_1P(0x9A, 0x0F); + RM68200_DCS_write_1A_1P(0x9B, 0x0B); + RM68200_DCS_write_1A_1P(0x9C, 0x0D); + RM68200_DCS_write_1A_1P(0x9D, 0x3F); + RM68200_DCS_write_1A_1P(0x9E, 0x3F); + RM68200_DCS_write_1A_1P(0x9F, 0x3F); + RM68200_DCS_write_1A_1P(0xA0, 0x3F); + RM68200_DCS_write_1A_1P(0xA2, 0x3F); + RM68200_DCS_write_1A_1P(0xA3, 0x09); + RM68200_DCS_write_1A_1P(0xA4, 0x13); + RM68200_DCS_write_1A_1P(0xA5, 0x17); + RM68200_DCS_write_1A_1P(0xA6, 0x11); + RM68200_DCS_write_1A_1P(0xA7, 0x15); + RM68200_DCS_write_1A_1P(0xA9, 0x07); + RM68200_DCS_write_1A_1P(0xAA, 0x03); + RM68200_DCS_write_1A_1P(0xAB, 0x3F); + RM68200_DCS_write_1A_1P(0xAC, 0x3F); + RM68200_DCS_write_1A_1P(0xAD, 0x05); + RM68200_DCS_write_1A_1P(0xAE, 0x01); + RM68200_DCS_write_1A_1P(0xAF, 0x17); + RM68200_DCS_write_1A_1P(0xB0, 0x13); + RM68200_DCS_write_1A_1P(0xB1, 0x15); + RM68200_DCS_write_1A_1P(0xB2, 0x11); + RM68200_DCS_write_1A_1P(0xB3, 0x0F); + RM68200_DCS_write_1A_1P(0xB4, 0x3F); + RM68200_DCS_write_1A_1P(0xB5, 0x3F); + RM68200_DCS_write_1A_1P(0xB6, 0x3F); + RM68200_DCS_write_1A_1P(0xB7, 0x3F); + RM68200_DCS_write_1A_1P(0xB8, 0x3F); + RM68200_DCS_write_1A_1P(0xB9, 0x0B); + RM68200_DCS_write_1A_1P(0xBA, 0x0D); + RM68200_DCS_write_1A_1P(0xBB, 0x09); + RM68200_DCS_write_1A_1P(0xBC, 0x3F); + RM68200_DCS_write_1A_1P(0xBD, 0x3F); + RM68200_DCS_write_1A_1P(0xBE, 0x07); + RM68200_DCS_write_1A_1P(0xBF, 0x03); + RM68200_DCS_write_1A_1P(0xC0, 0x3F); + RM68200_DCS_write_1A_1P(0xC1, 0x3F); + RM68200_DCS_write_1A_1P(0xC2, 0x3F); + RM68200_DCS_write_1A_1P(0xC3, 0x3F); + RM68200_DCS_write_1A_1P(0xC4, 0x02); + RM68200_DCS_write_1A_1P(0xC5, 0x06); + RM68200_DCS_write_1A_1P(0xC6, 0x3F); + RM68200_DCS_write_1A_1P(0xC7, 0x3F); + RM68200_DCS_write_1A_1P(0xC8, 0x08); + RM68200_DCS_write_1A_1P(0xC9, 0x0C); + RM68200_DCS_write_1A_1P(0xCA, 0x0A); + RM68200_DCS_write_1A_1P(0xCB, 0x3F); + RM68200_DCS_write_1A_1P(0xCC, 0x3F); + RM68200_DCS_write_1A_1P(0xCD, 0x3F); + RM68200_DCS_write_1A_1P(0xCE, 0x3F); + RM68200_DCS_write_1A_1P(0xCF, 0x3F); + RM68200_DCS_write_1A_1P(0xD0, 0x0E); + RM68200_DCS_write_1A_1P(0xD1, 0x10); + RM68200_DCS_write_1A_1P(0xD2, 0x14); + RM68200_DCS_write_1A_1P(0xD3, 0x12); + RM68200_DCS_write_1A_1P(0xD4, 0x16); + RM68200_DCS_write_1A_1P(0xD5, 0x00); + RM68200_DCS_write_1A_1P(0xD6, 0x04); + RM68200_DCS_write_1A_1P(0xD7, 0x3F); + RM68200_DCS_write_1A_1P(0xDC, 0x02); + RM68200_DCS_write_1A_1P(0xDE, 0x12); + RM68200_DCS_write_1A_1P(0xFE, 0x0E); + RM68200_DCS_write_1A_1P(0x01, 0x75); + + /* change to MCS Page 3: Gamma Settings */ + RM68200_DCS_write_1A_1P(0xFE, 0x04); + RM68200_DCS_write_1A_1P(0x60, 0x00); + RM68200_DCS_write_1A_1P(0x61, 0x0C); + RM68200_DCS_write_1A_1P(0x62, 0x12); + RM68200_DCS_write_1A_1P(0x63, 0x0E); + RM68200_DCS_write_1A_1P(0x64, 0x06); + RM68200_DCS_write_1A_1P(0x65, 0x12); + RM68200_DCS_write_1A_1P(0x66, 0x0E); + RM68200_DCS_write_1A_1P(0x67, 0x0B); + RM68200_DCS_write_1A_1P(0x68, 0x15); + RM68200_DCS_write_1A_1P(0x69, 0x0B); + RM68200_DCS_write_1A_1P(0x6A, 0x10); + RM68200_DCS_write_1A_1P(0x6B, 0x07); + RM68200_DCS_write_1A_1P(0x6C, 0x0F); + RM68200_DCS_write_1A_1P(0x6D, 0x12); + RM68200_DCS_write_1A_1P(0x6E, 0x0C); + RM68200_DCS_write_1A_1P(0x6F, 0x00); + RM68200_DCS_write_1A_1P(0x70, 0x00); + RM68200_DCS_write_1A_1P(0x71, 0x0C); + RM68200_DCS_write_1A_1P(0x72, 0x12); + RM68200_DCS_write_1A_1P(0x73, 0x0E); + RM68200_DCS_write_1A_1P(0x74, 0x06); + RM68200_DCS_write_1A_1P(0x75, 0x12); + RM68200_DCS_write_1A_1P(0x76, 0x0E); + RM68200_DCS_write_1A_1P(0x77, 0x0B); + RM68200_DCS_write_1A_1P(0x78, 0x15); + RM68200_DCS_write_1A_1P(0x79, 0x0B); + RM68200_DCS_write_1A_1P(0x7A, 0x10); + RM68200_DCS_write_1A_1P(0x7B, 0x07); + RM68200_DCS_write_1A_1P(0x7C, 0x0F); + RM68200_DCS_write_1A_1P(0x7D, 0x12); + RM68200_DCS_write_1A_1P(0x7E, 0x0C); + RM68200_DCS_write_1A_1P(0x7F, 0x00); + + /* change to MCS Page 0 */ + RM68200_DCS_write_1A_1P(0xFE, 0x00); + RM68200_DCS_write_1A_1P(0x11, 0x00); + mdelay(200); + RM68200_DCS_write_1A_1P(0x29, 0x00); + mdelay(100); + RM68200_DCS_write_1A_0P(0x2C); + RM68200_DCS_write_1A_1P(0x35, 0x00); + mdelay(200); + + return 0; +} + +static struct mipi_dsi_client_driver rm68200_drv = { + .name = "RM68200_WXGA", + .dsi_client_setup = mipid_rm68200_lcd_setup, +}; + +void rm68200_init(void) +{ + imx_mipi_dsi_bridge_add_client_driver(&rm68200_drv); +} diff --git a/drivers/video/sec_mipi_dsim.c b/drivers/video/sec_mipi_dsim.c new file mode 100644 index 00000000000..7329d23dbfd --- /dev/null +++ b/drivers/video/sec_mipi_dsim.c @@ -0,0 +1,902 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MIPI_FIFO_TIMEOUT 250000 /* 250ms */ + +#define DRIVER_NAME "imx_sec_mipi_dsim" + +/* dsim registers */ +#define DSIM_VERSION 0x00 +#define DSIM_STATUS 0x04 +#define DSIM_RGB_STATUS 0x08 +#define DSIM_SWRST 0x0c +#define DSIM_CLKCTRL 0x10 +#define DSIM_TIMEOUT 0x14 +#define DSIM_CONFIG 0x18 +#define DSIM_ESCMODE 0x1c +#define DSIM_MDRESOL 0x20 +#define DSIM_MVPORCH 0x24 +#define DSIM_MHPORCH 0x28 +#define DSIM_MSYNC 0x2c +#define DSIM_SDRESOL 0x30 +#define DSIM_INTSRC 0x34 +#define DSIM_INTMSK 0x38 + +/* packet */ +#define DSIM_PKTHDR 0x3c +#define DSIM_PAYLOAD 0x40 +#define DSIM_RXFIFO 0x44 +#define DSIM_FIFOTHLD 0x48 +#define DSIM_FIFOCTRL 0x4c +#define DSIM_MEMACCHR 0x50 +#define DSIM_MULTI_PKT 0x78 + +/* pll control */ +#define DSIM_PLLCTRL_1G 0x90 +#define DSIM_PLLCTRL 0x94 +#define DSIM_PLLCTRL1 0x98 +#define DSIM_PLLCTRL2 0x9c +#define DSIM_PLLTMR 0xa0 + +/* dphy */ +#define DSIM_PHYTIMING 0xb4 +#define DSIM_PHYTIMING1 0xb8 +#define DSIM_PHYTIMING2 0xbc + +/* reg bit manipulation */ +#define REG_MASK(e, s) (((1 << ((e) - (s) + 1)) - 1) << (s)) +#define REG_PUT(x, e, s) (((x) << (s)) & REG_MASK(e, s)) +#define REG_GET(x, e, s) (((x) & REG_MASK(e, s)) >> (s)) + +/* register bit fields */ +#define STATUS_PLLSTABLE BIT(31) +#define STATUS_SWRSTRLS BIT(20) +#define STATUS_TXREADYHSCLK BIT(10) +#define STATUS_ULPSCLK BIT(9) +#define STATUS_STOPSTATECLK BIT(8) +#define STATUS_GET_ULPSDAT(x) REG_GET(x, 7, 4) +#define STATUS_GET_STOPSTATEDAT(x) REG_GET(x, 3, 0) + +#define RGB_STATUS_CMDMODE_INSEL BIT(31) +#define RGB_STATUS_GET_RGBSTATE(x) REG_GET(x, 12, 0) + +#define CLKCTRL_TXREQUESTHSCLK BIT(31) +#define CLKCTRL_DPHY_SEL_1G BIT(29) +#define CLKCTRL_DPHY_SEL_1P5G (0x0 << 29) +#define CLKCTRL_ESCCLKEN BIT(28) +#define CLKCTRL_PLLBYPASS BIT(29) +#define CLKCTRL_BYTECLKSRC_DPHY_PLL REG_PUT(0, 26, 25) +#define CLKCTRL_BYTECLKEN BIT(24) +#define CLKCTRL_SET_LANEESCCLKEN(x) REG_PUT(x, 23, 19) +#define CLKCTRL_SET_ESCPRESCALER(x) REG_PUT(x, 15, 0) + +#define TIMEOUT_SET_BTAOUT(x) REG_PUT(x, 23, 16) +#define TIMEOUT_SET_LPDRTOUT(x) REG_PUT(x, 15, 0) + +#define CONFIG_NON_CONTINOUS_CLOCK_LANE BIT(31) +#define CONFIG_CLKLANE_STOP_START BIT(30) +#define CONFIG_MFLUSH_VS BIT(29) +#define CONFIG_EOT_R03 BIT(28) +#define CONFIG_SYNCINFORM BIT(27) +#define CONFIG_BURSTMODE BIT(26) +#define CONFIG_VIDEOMODE BIT(25) +#define CONFIG_AUTOMODE BIT(24) +#define CONFIG_HSEDISABLEMODE BIT(23) +#define CONFIG_HFPDISABLEMODE BIT(22) +#define CONFIG_HBPDISABLEMODE BIT(21) +#define CONFIG_HSADISABLEMODE BIT(20) +#define CONFIG_SET_MAINVC(x) REG_PUT(x, 19, 18) +#define CONFIG_SET_SUBVC(x) REG_PUT(x, 17, 16) +#define CONFIG_SET_MAINPIXFORMAT(x) REG_PUT(x, 14, 12) +#define CONFIG_SET_SUBPIXFORMAT(x) REG_PUT(x, 10, 8) +#define CONFIG_SET_NUMOFDATLANE(x) REG_PUT(x, 6, 5) +#define CONFIG_SET_LANEEN(x) REG_PUT(x, 4, 0) + +#define MDRESOL_MAINSTANDBY BIT(31) +#define MDRESOL_SET_MAINVRESOL(x) REG_PUT(x, 27, 16) +#define MDRESOL_SET_MAINHRESOL(x) REG_PUT(x, 11, 0) + +#define MVPORCH_SET_CMDALLOW(x) REG_PUT(x, 31, 28) +#define MVPORCH_SET_STABLEVFP(x) REG_PUT(x, 26, 16) +#define MVPORCH_SET_MAINVBP(x) REG_PUT(x, 10, 0) + +#define MHPORCH_SET_MAINHFP(x) REG_PUT(x, 31, 16) +#define MHPORCH_SET_MAINHBP(x) REG_PUT(x, 15, 0) + +#define MSYNC_SET_MAINVSA(x) REG_PUT(x, 31, 22) +#define MSYNC_SET_MAINHSA(x) REG_PUT(x, 15, 0) + +#define INTSRC_PLLSTABLE BIT(31) +#define INTSRC_SWRSTRELEASE BIT(30) +#define INTSRC_SFRPLFIFOEMPTY BIT(29) +#define INTSRC_SFRPHFIFOEMPTY BIT(28) +#define INTSRC_FRAMEDONE BIT(24) +#define INTSRC_LPDRTOUT BIT(21) +#define INTSRC_TATOUT BIT(20) +#define INTSRC_RXDATDONE BIT(18) +#define INTSRC_MASK (INTSRC_PLLSTABLE | \ + INTSRC_SWRSTRELEASE | \ + INTSRC_SFRPLFIFOEMPTY | \ + INTSRC_SFRPHFIFOEMPTY | \ + INTSRC_FRAMEDONE | \ + INTSRC_LPDRTOUT | \ + INTSRC_TATOUT | \ + INTSRC_RXDATDONE) + +#define INTMSK_MSKPLLSTABLE BIT(31) +#define INTMSK_MSKSWRELEASE BIT(30) +#define INTMSK_MSKSFRPLFIFOEMPTY BIT(29) +#define INTMSK_MSKSFRPHFIFOEMPTY BIT(28) +#define INTMSK_MSKFRAMEDONE BIT(24) +#define INTMSK_MSKLPDRTOUT BIT(21) +#define INTMSK_MSKTATOUT BIT(20) +#define INTMSK_MSKRXDATDONE BIT(18) + +#define PLLCTRL_DPDNSWAP_CLK BIT(25) +#define PLLCTRL_DPDNSWAP_DAT BIT(24) +#define PLLCTRL_PLLEN BIT(23) +#define PLLCTRL_SET_PMS(x) REG_PUT(x, 19, 1) + +#define PHYTIMING_SET_M_TLPXCTL(x) REG_PUT(x, 15, 8) +#define PHYTIMING_SET_M_THSEXITCTL(x) REG_PUT(x, 7, 0) + +#define PHYTIMING1_SET_M_TCLKPRPRCTL(x) REG_PUT(x, 31, 24) +#define PHYTIMING1_SET_M_TCLKZEROCTL(x) REG_PUT(x, 23, 16) +#define PHYTIMING1_SET_M_TCLKPOSTCTL(x) REG_PUT(x, 15, 8) +#define PHYTIMING1_SET_M_TCLKTRAILCTL(x) REG_PUT(x, 7, 0) + +#define PHYTIMING2_SET_M_THSPRPRCTL(x) REG_PUT(x, 23, 16) +#define PHYTIMING2_SET_M_THSZEROCTL(x) REG_PUT(x, 15, 8) +#define PHYTIMING2_SET_M_THSTRAILCTL(x) REG_PUT(x, 7, 0) + +#define dsim_read(dsim, reg) readl(dsim->base + reg) +#define dsim_write(dsim, val, reg) writel(val, dsim->base + reg) + +/* fixed phy ref clk rate */ +#define PHY_REF_CLK 27000000 + +#define MAX_MAIN_HRESOL 2047 +#define MAX_MAIN_VRESOL 2047 +#define MAX_SUB_HRESOL 1024 +#define MAX_SUB_VRESOL 1024 + +/* in KHZ */ +#define MAX_ESC_CLK_FREQ 20000 + +/* dsim all irqs index */ +#define PLLSTABLE 1 +#define SWRSTRELEASE 2 +#define SFRPLFIFOEMPTY 3 +#define SFRPHFIFOEMPTY 4 +#define SYNCOVERRIDE 5 +#define BUSTURNOVER 6 +#define FRAMEDONE 7 +#define LPDRTOUT 8 +#define TATOUT 9 +#define RXDATDONE 10 +#define RXTE 11 +#define RXACK 12 +#define ERRRXECC 13 +#define ERRRXCRC 14 +#define ERRESC3 15 +#define ERRESC2 16 +#define ERRESC1 17 +#define ERRESC0 18 +#define ERRSYNC3 19 +#define ERRSYNC2 20 +#define ERRSYNC1 21 +#define ERRSYNC0 22 +#define ERRCONTROL3 23 +#define ERRCONTROL2 24 +#define ERRCONTROL1 25 +#define ERRCONTROL0 26 + +/* Dispmix Control & GPR Registers */ +#define DISPLAY_MIX_SFT_RSTN_CSR 0x00 + #define MIPI_DSI_I_PRESETn_SFT_EN BIT(5) +#define DISPLAY_MIX_CLK_EN_CSR 0x04 + #define MIPI_DSI_PCLK_SFT_EN BIT(8) + #define MIPI_DSI_CLKREF_SFT_EN BIT(9) +#define GPR_MIPI_RESET_DIV 0x08 + /* Clock & Data lanes reset: Active Low */ + #define GPR_MIPI_S_RESETN BIT(16) + #define GPR_MIPI_M_RESETN BIT(17) + +#define PS2KHZ(ps) (1000000000UL / (ps)) + +/* DSIM PLL configuration from spec: + * + * Fout(DDR) = (M * Fin) / (P * 2^S), so Fout / Fin = M / (P * 2^S) + * Fin_pll = Fin / P (6 ~ 12 MHz) + * S: [2:0], M: [12:3], P: [18:13], so + * TODO: 'S' is in [0 ~ 3], 'M' is in, 'P' is in [1 ~ 33] + * + */ + +struct sec_mipi_dsim { + void __iomem *base; + void __iomem *disp_mix_gpr_base; + + /* kHz clocks */ + uint64_t pix_clk; + uint64_t bit_clk; + + unsigned int lanes; + unsigned int channel; /* virtual channel */ + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; + unsigned int pms; + unsigned int p; + unsigned int m; + unsigned int s; + struct fb_videomode vmode; + + const struct sec_mipi_dsim_plat_data *pdata; + + struct mipi_dsi_client_dev *dsi_panel_dev; + struct mipi_dsi_client_driver *dsi_panel_drv; +}; + +static void disp_mix_dsim_soft_reset_release(struct sec_mipi_dsim *dsim, bool release) +{ + if (release) + /* release dsi blk reset */ + setbits_le32(dsim->disp_mix_gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, MIPI_DSI_I_PRESETn_SFT_EN); + + else + clrbits_le32(dsim->disp_mix_gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, MIPI_DSI_I_PRESETn_SFT_EN); +} + +static void disp_mix_dsim_clks_enable(struct sec_mipi_dsim *dsim, bool enable) +{ + if (enable) + setbits_le32(dsim->disp_mix_gpr_base + DISPLAY_MIX_CLK_EN_CSR, MIPI_DSI_PCLK_SFT_EN | MIPI_DSI_CLKREF_SFT_EN); + else + clrbits_le32(dsim->disp_mix_gpr_base + DISPLAY_MIX_CLK_EN_CSR, MIPI_DSI_PCLK_SFT_EN | MIPI_DSI_CLKREF_SFT_EN); +} + +static void disp_mix_dsim_lanes_reset(struct sec_mipi_dsim *dsim, bool reset) +{ + if (!reset) + /* release lanes reset */ + setbits_le32(dsim->disp_mix_gpr_base + GPR_MIPI_RESET_DIV, GPR_MIPI_S_RESETN | GPR_MIPI_M_RESETN); + else + /* reset lanes */ + clrbits_le32(dsim->disp_mix_gpr_base + GPR_MIPI_RESET_DIV, GPR_MIPI_S_RESETN | GPR_MIPI_M_RESETN); +} + +static void sec_mipi_dsim_wr_tx_header(struct sec_mipi_dsim *dsim, + u8 di, u8 data0, u8 data1) +{ + unsigned int reg; + + reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0); + + dsim_write(dsim, reg, DSIM_PKTHDR); +} + +static void sec_mipi_dsim_wr_tx_data(struct sec_mipi_dsim *dsim, + unsigned int tx_data) +{ + dsim_write(dsim, tx_data, DSIM_PAYLOAD); +} + +static void sec_mipi_dsim_long_data_wr(struct sec_mipi_dsim *dsim, + const unsigned char *data0, unsigned int data_size) +{ + unsigned int data_cnt = 0, payload = 0; + + /* in case that data count is more then 4 */ + for (data_cnt = 0; data_cnt < data_size; data_cnt += 4) { + /* + * after sending 4bytes per one time, + * send remainder data less then 4. + */ + if ((data_size - data_cnt) < 4) { + if ((data_size - data_cnt) == 3) { + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8 | + data0[data_cnt + 2] << 16; + debug("count = 3 payload = %x, %x %x %x\n", + payload, data0[data_cnt], + data0[data_cnt + 1], + data0[data_cnt + 2]); + } else if ((data_size - data_cnt) == 2) { + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8; + debug("count = 2 payload = %x, %x %x\n", payload, + data0[data_cnt], + data0[data_cnt + 1]); + } else if ((data_size - data_cnt) == 1) { + payload = data0[data_cnt]; + } + + sec_mipi_dsim_wr_tx_data(dsim, payload); + /* send 4bytes per one time. */ + } else { + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8 | + data0[data_cnt + 2] << 16 | + data0[data_cnt + 3] << 24; + + debug("count = 4 payload = %x, %x %x %x %x\n", + payload, *(u8 *)(data0 + data_cnt), + data0[data_cnt + 1], + data0[data_cnt + 2], + data0[data_cnt + 3]); + + sec_mipi_dsim_wr_tx_data(dsim, payload); + } + } +} + +static int sec_mipi_dsim_wait_for_pkt_done(struct sec_mipi_dsim *dsim, unsigned long timeout) +{ + uint32_t intsrc; + + do { + intsrc = dsim_read(dsim, DSIM_INTSRC); + if (intsrc & INTSRC_SFRPLFIFOEMPTY) { + dsim_write(dsim, INTSRC_SFRPLFIFOEMPTY, DSIM_INTSRC); + return 0; + } + + udelay(1); + } while (--timeout); + + return -ETIMEDOUT; +} + +static int sec_mipi_dsim_pkt_write(struct sec_mipi_dsim *dsim, + u8 data_type, const u8 *buf, int len) +{ + int ret = 0; + const unsigned char *data = (const unsigned char*)buf; + + if (len == 0) + /* handle generic short write command */ + sec_mipi_dsim_wr_tx_header(dsim, data_type, data[0], data[1]); + else { + /* handle generic long write command */ + sec_mipi_dsim_long_data_wr(dsim, data, len); + sec_mipi_dsim_wr_tx_header(dsim, data_type, len & 0xff, (len & 0xff00) >> 8); + + ret = sec_mipi_dsim_wait_for_pkt_done(dsim, MIPI_FIFO_TIMEOUT); + if (ret) { + printf("wait tx done timeout!\n"); + return -ETIMEDOUT; + } + } + mdelay(10); + + return 0; +} + +static int sec_mipi_dsim_wait_pll_stable(struct sec_mipi_dsim *dsim) +{ + uint32_t status; + ulong start; + + start = get_timer(0); /* Get current timestamp */ + + do { + status = dsim_read(dsim, DSIM_STATUS); + if (status & STATUS_PLLSTABLE) + return 0; + } while (get_timer(0) < (start + 100)); /* Wait 100ms */ + + return -ETIMEDOUT; +} + +static int sec_mipi_dsim_config_pll(struct sec_mipi_dsim *dsim) +{ + int ret; + uint32_t pllctrl = 0, status, data_lanes_en, stop; + + dsim_write(dsim, 0x8000, DSIM_PLLTMR); + + /* TODO: config dp/dn swap if requires */ + + pllctrl |= PLLCTRL_SET_PMS(dsim->pms) | PLLCTRL_PLLEN; + dsim_write(dsim, pllctrl, DSIM_PLLCTRL); + + ret = sec_mipi_dsim_wait_pll_stable(dsim); + if (ret) { + printf("wait for pll stable time out\n"); + return ret; + } + + /* wait for clk & data lanes to go to stop state */ + mdelay(1); + + data_lanes_en = (0x1 << dsim->lanes) - 1; + status = dsim_read(dsim, DSIM_STATUS); + if (!(status & STATUS_STOPSTATECLK)) { + printf("clock is not in stop state\n"); + return -EBUSY; + } + + stop = STATUS_GET_STOPSTATEDAT(status); + if ((stop & data_lanes_en) != data_lanes_en) { + printf("one or more data lanes is not in stop state\n"); + return -EBUSY; + } + + return 0; +} + +static void sec_mipi_dsim_set_main_mode(struct sec_mipi_dsim *dsim) +{ + uint32_t bpp, hfp_wc, hbp_wc, hsa_wc; + uint32_t mdresol = 0, mvporch = 0, mhporch = 0, msync = 0; + struct fb_videomode *vmode = &dsim->vmode; + + mdresol |= MDRESOL_SET_MAINVRESOL(vmode->yres) | + MDRESOL_SET_MAINHRESOL(vmode->xres); + dsim_write(dsim, mdresol, DSIM_MDRESOL); + + mvporch |= MVPORCH_SET_MAINVBP(vmode->upper_margin) | + MVPORCH_SET_STABLEVFP(vmode->lower_margin) | + MVPORCH_SET_CMDALLOW(0x0); + dsim_write(dsim, mvporch, DSIM_MVPORCH); + + bpp = mipi_dsi_pixel_format_to_bpp(dsim->format); + + /* calculate hfp & hbp word counts */ + if (dsim->dsi_panel_drv) { + /* Panel driver is registered, will work with panel */ + hfp_wc = vmode->right_margin * (bpp >> 3); + hbp_wc = vmode->left_margin * (bpp >> 3); + } else { + hfp_wc = vmode->right_margin * (bpp >> 3) / dsim->lanes - 6; + hbp_wc = vmode->left_margin * (bpp >> 3) / dsim->lanes - 6; + } + + mhporch |= MHPORCH_SET_MAINHFP(hfp_wc) | + MHPORCH_SET_MAINHBP(hbp_wc); + + dsim_write(dsim, mhporch, DSIM_MHPORCH); + + /* calculate hsa word counts */ + if (dsim->dsi_panel_drv) { + hsa_wc = vmode->hsync_len * (bpp >> 3); + } else { + hsa_wc = vmode->hsync_len * (bpp >> 3) / dsim->lanes - 6; + } + + msync |= MSYNC_SET_MAINVSA(vmode->vsync_len) | + MSYNC_SET_MAINHSA(hsa_wc); + + debug("hfp_wc %u hbp_wc %u hsa_wc %u\n", hfp_wc, hbp_wc, hsa_wc); + + dsim_write(dsim, msync, DSIM_MSYNC); +} + +static void sec_mipi_dsim_config_dpi(struct sec_mipi_dsim *dsim) +{ + uint32_t config = 0, rgb_status = 0, data_lanes_en; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) + rgb_status &= ~RGB_STATUS_CMDMODE_INSEL; + else + rgb_status |= RGB_STATUS_CMDMODE_INSEL; + + dsim_write(dsim, rgb_status, DSIM_RGB_STATUS); + + if (dsim->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + config |= CONFIG_CLKLANE_STOP_START; + + if (dsim->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH) + config |= CONFIG_MFLUSH_VS; + + /* disable EoT packets in HS mode */ + if (dsim->mode_flags & MIPI_DSI_MODE_EOT_PACKET) + config |= CONFIG_EOT_R03; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) { + config |= CONFIG_VIDEOMODE; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + config |= CONFIG_BURSTMODE; + + else if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + config |= CONFIG_SYNCINFORM; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) + config |= CONFIG_AUTOMODE; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) + config |= CONFIG_HSEDISABLEMODE; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) + config |= CONFIG_HFPDISABLEMODE; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) + config |= CONFIG_HBPDISABLEMODE; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) + config |= CONFIG_HSADISABLEMODE; + } + + config |= CONFIG_SET_MAINVC(dsim->channel); + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) { + switch (dsim->format) { + case MIPI_DSI_FMT_RGB565: + config |= CONFIG_SET_MAINPIXFORMAT(0x4); + break; + case MIPI_DSI_FMT_RGB666_PACKED: + config |= CONFIG_SET_MAINPIXFORMAT(0x5); + break; + case MIPI_DSI_FMT_RGB666: + config |= CONFIG_SET_MAINPIXFORMAT(0x6); + break; + case MIPI_DSI_FMT_RGB888: + config |= CONFIG_SET_MAINPIXFORMAT(0x7); + break; + default: + config |= CONFIG_SET_MAINPIXFORMAT(0x7); + break; + } + } + + /* config data lanes number and enable lanes */ + data_lanes_en = (0x1 << dsim->lanes) - 1; + config |= CONFIG_SET_NUMOFDATLANE(dsim->lanes - 1); + config |= CONFIG_SET_LANEEN(0x1 | data_lanes_en << 1); + + dsim_write(dsim, config, DSIM_CONFIG); +} + +static void sec_mipi_dsim_config_dphy(struct sec_mipi_dsim *dsim) +{ + uint32_t phytiming = 0, phytiming1 = 0, phytiming2 = 0, timeout = 0; + + /* TODO: add a PHY timing table arranged by the pll Fout */ + + phytiming |= PHYTIMING_SET_M_TLPXCTL(6) | + PHYTIMING_SET_M_THSEXITCTL(11); + dsim_write(dsim, phytiming, DSIM_PHYTIMING); + + phytiming1 |= PHYTIMING1_SET_M_TCLKPRPRCTL(7) | + PHYTIMING1_SET_M_TCLKZEROCTL(38) | + PHYTIMING1_SET_M_TCLKPOSTCTL(13) | + PHYTIMING1_SET_M_TCLKTRAILCTL(8); + dsim_write(dsim, phytiming1, DSIM_PHYTIMING1); + + phytiming2 |= PHYTIMING2_SET_M_THSPRPRCTL(8) | + PHYTIMING2_SET_M_THSZEROCTL(13) | + PHYTIMING2_SET_M_THSTRAILCTL(11); + dsim_write(dsim, phytiming2, DSIM_PHYTIMING2); + + timeout |= TIMEOUT_SET_BTAOUT(0xf) | + TIMEOUT_SET_LPDRTOUT(0xf); + dsim_write(dsim, 0xf000f, DSIM_TIMEOUT); +} + +static void sec_mipi_dsim_config_clkctrl(struct sec_mipi_dsim *dsim) +{ + uint32_t clkctrl = 0, data_lanes_en; + uint64_t byte_clk, esc_prescaler; + + clkctrl |= CLKCTRL_TXREQUESTHSCLK; + + /* using 1.5Gbps PHY */ + clkctrl |= CLKCTRL_DPHY_SEL_1P5G; + + clkctrl |= CLKCTRL_ESCCLKEN; + + clkctrl &= ~CLKCTRL_PLLBYPASS; + + clkctrl |= CLKCTRL_BYTECLKSRC_DPHY_PLL; + + clkctrl |= CLKCTRL_BYTECLKEN; + + data_lanes_en = (0x1 << dsim->lanes) - 1; + clkctrl |= CLKCTRL_SET_LANEESCCLKEN(0x1 | data_lanes_en << 1); + + /* calculate esc prescaler from byte clock: + * EscClk = ByteClk / EscPrescaler; + */ + byte_clk = dsim->bit_clk >> 3; + esc_prescaler = DIV_ROUND_UP_ULL(byte_clk, MAX_ESC_CLK_FREQ); + + clkctrl |= CLKCTRL_SET_ESCPRESCALER(esc_prescaler); + + dsim_write(dsim, clkctrl, DSIM_CLKCTRL); +} + +static void sec_mipi_dsim_set_standby(struct sec_mipi_dsim *dsim, + bool standby) +{ + uint32_t mdresol = 0; + + mdresol = dsim_read(dsim, DSIM_MDRESOL); + + if (standby) + mdresol |= MDRESOL_MAINSTANDBY; + else + mdresol &= ~MDRESOL_MAINSTANDBY; + + dsim_write(dsim, mdresol, DSIM_MDRESOL); +} + +static void sec_mipi_dsim_disable_clkctrl(struct sec_mipi_dsim *dsim) +{ + uint32_t clkctrl; + + clkctrl = dsim_read(dsim, DSIM_CLKCTRL); + + clkctrl &= ~CLKCTRL_TXREQUESTHSCLK; + + clkctrl &= ~CLKCTRL_ESCCLKEN; + + clkctrl &= ~CLKCTRL_BYTECLKEN; + + dsim_write(dsim, clkctrl, DSIM_CLKCTRL); +} + +static void sec_mipi_dsim_disable_pll(struct sec_mipi_dsim *dsim) +{ + uint32_t pllctrl; + + pllctrl = dsim_read(dsim, DSIM_PLLCTRL); + + pllctrl &= ~PLLCTRL_PLLEN; + + dsim_write(dsim, pllctrl, DSIM_PLLCTRL); +} + +/* For now, dsim only support one device attached */ +static int sec_mipi_dsim_bridge_attach(struct mipi_dsi_bridge_driver *bridge_driver, + struct mipi_dsi_client_dev *dsi_dev) +{ + struct sec_mipi_dsim *dsim_host = (struct sec_mipi_dsim *)bridge_driver->driver_private; + + if (!dsi_dev->lanes || dsi_dev->lanes > dsim_host->pdata->max_data_lanes) { + printf("invalid data lanes number\n"); + return -EINVAL; + } + + if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO) || + !((dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) || + (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))) { + printf("unsupported dsi mode\n"); + return -EINVAL; + } + + if (dsi_dev->format != MIPI_DSI_FMT_RGB888 && + dsi_dev->format != MIPI_DSI_FMT_RGB565 && + dsi_dev->format != MIPI_DSI_FMT_RGB666 && + dsi_dev->format != MIPI_DSI_FMT_RGB666_PACKED) { + printf("unsupported pixel format: %#x\n", dsi_dev->format); + return -EINVAL; + } + + if (!dsi_dev->name) { + printf("panel_device name is NULL.\n"); + return -EFAULT; + } + + if (dsim_host->dsi_panel_drv) { + if (strcmp(dsi_dev->name, dsim_host->dsi_panel_drv->name)) { + printf("The panel device name %s is not for LCD driver %s\n", + dsi_dev->name, dsim_host->dsi_panel_drv->name); + return -EFAULT; + } + } + + dsim_host->dsi_panel_dev = dsi_dev; + + dsim_host->lanes = dsi_dev->lanes; + dsim_host->channel = dsi_dev->channel; + dsim_host->format = dsi_dev->format; + dsim_host->mode_flags = dsi_dev->mode_flags; + + return 0; +} + +static int sec_mipi_dsim_bridge_enable(struct mipi_dsi_bridge_driver *bridge_driver) +{ + int ret; + struct sec_mipi_dsim *dsim_host = (struct sec_mipi_dsim *)bridge_driver->driver_private; + + /* At this moment, the dsim bridge's preceding encoder has + * already been enabled. So the dsim can be configed here + */ + + /* config main display mode */ + sec_mipi_dsim_set_main_mode(dsim_host); + + /* config dsim dpi */ + sec_mipi_dsim_config_dpi(dsim_host); + + /* config dsim pll */ + ret = sec_mipi_dsim_config_pll(dsim_host); + if (ret) { + printf("dsim pll config failed: %d\n", ret); + return -EPERM; + } + + /* config dphy timings */ + sec_mipi_dsim_config_dphy(dsim_host); + + /* config esc clock, byte clock and etc */ + sec_mipi_dsim_config_clkctrl(dsim_host); + + /* enable data transfer of dsim */ + sec_mipi_dsim_set_standby(dsim_host, true); + + /* Call panel driver's setup */ + if (dsim_host->dsi_panel_drv && dsim_host->dsi_panel_drv->dsi_client_setup) { + ret = dsim_host->dsi_panel_drv->dsi_client_setup(dsim_host->dsi_panel_dev); + if (ret < 0) { + printf("failed to init mipi lcd.\n"); + return ret; + } + } + + return 0; +} + +static int sec_mipi_dsim_bridge_disable(struct mipi_dsi_bridge_driver *bridge_driver) +{ + uint32_t intsrc; + struct sec_mipi_dsim *dsim_host = (struct sec_mipi_dsim *)bridge_driver->driver_private; + + /* disable data transfer of dsim */ + sec_mipi_dsim_set_standby(dsim_host, false); + + /* disable esc clock & byte clock */ + sec_mipi_dsim_disable_clkctrl(dsim_host); + + /* disable dsim pll */ + sec_mipi_dsim_disable_pll(dsim_host); + + /* Clear all intsrc */ + intsrc = dsim_read(dsim_host, DSIM_INTSRC); + dsim_write(dsim_host, intsrc, DSIM_INTSRC); + + return 0; +} + +static int sec_mipi_dsim_bridge_mode_set(struct mipi_dsi_bridge_driver *bridge_driver, + struct fb_videomode *fbmode) +{ + int bpp; + uint64_t pix_clk, bit_clk; + struct sec_mipi_dsim *dsim_host = (struct sec_mipi_dsim *)bridge_driver->driver_private; + + dsim_host->vmode = *fbmode; + + bpp = mipi_dsi_pixel_format_to_bpp(dsim_host->format); + if (bpp < 0) + return -EINVAL; + + pix_clk = PS2KHZ(fbmode->pixclock) * 1000; + bit_clk = DIV_ROUND_UP_ULL(pix_clk * bpp, dsim_host->lanes); + + if (bit_clk > dsim_host->pdata->max_data_rate) { + printf("request bit clk freq exceeds lane's maximum value\n"); + return -EINVAL; + } + + dsim_host->pix_clk = DIV_ROUND_UP_ULL(pix_clk, 1000); + dsim_host->bit_clk = DIV_ROUND_UP_ULL(bit_clk, 1000); + + if (dsim_host->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { + /* TODO: add PMS calculate and check + * Only support '1080p@60Hz' for now, + * add other modes support later + */ + dsim_host->pms = 0x4210; + } + + debug("%s: bitclk %llu pixclk %llu\n", __func__, dsim_host->bit_clk, dsim_host->pix_clk); + + return 0; +} + +/* Add a LCD panel driver, will search the panel device to bind with them */ +int sec_mipi_dsim_bridge_add_client_driver(struct mipi_dsi_bridge_driver *bridge_driver, + struct mipi_dsi_client_driver *panel_drv) +{ + struct sec_mipi_dsim *dsim_host = (struct sec_mipi_dsim *)bridge_driver->driver_private; + + if (!panel_drv) { + printf("mipi_dsi_northwest_panel_driver is NULL.\n"); + return -EFAULT; + } + + if (!panel_drv->name) { + printf("mipi_dsi_northwest_panel_driver name is NULL.\n"); + return -EFAULT; + } + + if (dsim_host->dsi_panel_dev) { + if (strcmp(panel_drv->name, dsim_host->dsi_panel_dev->name)) { + printf("The panel driver name %s is not for LCD device %s\n", + panel_drv->name, dsim_host->dsi_panel_dev->name); + return -EFAULT; + } + } + + dsim_host->dsi_panel_drv = panel_drv; + + return 0; +} + +static int sec_mipi_dsim_bridge_pkt_write(struct mipi_dsi_bridge_driver *bridge_driver, + u8 data_type, const u8 *buf, int len) +{ + struct sec_mipi_dsim *dsim_host = (struct sec_mipi_dsim *)bridge_driver->driver_private; + +#ifdef DEBUG + int i = 0; + printf("sec_mipi_dsim_bridge_pkt_write, data_type %u, len %d buf: \n", data_type, len); + + if (len == 0) + len = 2; + + for (i; i < len; i++) { + printf("0x%.2x ", buf[i]); + } + printf("\n"); +#endif + + return sec_mipi_dsim_pkt_write(dsim_host, data_type, buf, len); +} + +struct mipi_dsi_bridge_driver imx_sec_dsim_driver = { + .attach = sec_mipi_dsim_bridge_attach, + .enable = sec_mipi_dsim_bridge_enable, + .disable = sec_mipi_dsim_bridge_disable, + .mode_set = sec_mipi_dsim_bridge_mode_set, + .pkt_write = sec_mipi_dsim_bridge_pkt_write, + .add_client_driver = sec_mipi_dsim_bridge_add_client_driver, + .name = DRIVER_NAME, +}; + +int sec_mipi_dsim_setup(const struct sec_mipi_dsim_plat_data *plat_data) +{ + struct sec_mipi_dsim *dsim_host; + + if (!plat_data) { + printf("Invalid platform data \n"); + return -EINVAL; + } + + dsim_host = (struct sec_mipi_dsim *)malloc(sizeof(struct sec_mipi_dsim)); + if (!dsim_host) { + printf("failed to allocate sec_mipi_dsim object.\n"); + return -ENOMEM; + } + + dsim_host->base = (void __iomem *)plat_data->reg_base; + dsim_host->disp_mix_gpr_base = (void __iomem *)plat_data->gpr_base; + dsim_host->pdata = plat_data; + dsim_host->dsi_panel_drv = NULL; + dsim_host->dsi_panel_dev = NULL; + + /* Pull dsim out of reset */ + disp_mix_dsim_soft_reset_release(dsim_host, true); + disp_mix_dsim_clks_enable(dsim_host, true); + disp_mix_dsim_lanes_reset(dsim_host, false); + + imx_sec_dsim_driver.driver_private = dsim_host; + return imx_mipi_dsi_bridge_register_driver(&imx_sec_dsim_driver); +} diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index ab6a6b79e1d..6439024e379 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610)) +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610 imx8m)) obj-y += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o diff --git a/env/Kconfig b/env/Kconfig index a3c6298273e..73332ceeb0e 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -10,6 +10,7 @@ config ENV_IS_NOWHERE depends on !ENV_IS_IN_NVRAM depends on !ENV_IS_IN_ONENAND depends on !ENV_IS_IN_REMOTE + depends on !ENV_IS_IN_SATA depends on !ENV_IS_IN_SPI_FLASH depends on !ENV_IS_IN_UBI default y @@ -291,6 +292,20 @@ config ENV_IS_IN_REMOTE local device can get the environment from remote memory space by SRIO or PCIE links. +config ENV_IS_IN_SATA + bool "Environment is in SATA disk" + depends on !CHAIN_OF_TRUST + help + Define this if you have a SATA disk device which you + want to use for the environment. + + - CONFIG_ENV_OFFSET: + - CONFIG_ENV_SIZE: + + These two #defines specify the offset and size of the + environment area within the SATA disk. CONFIG_ENV_OFFSET must be + aligned to an disk sector boundary. + config ENV_IS_IN_SPI_FLASH bool "Environment is in SPI flash" depends on !CHAIN_OF_TRUST diff --git a/env/env.c b/env/env.c index 3795dbc24e2..042a8c65fad 100644 --- a/env/env.c +++ b/env/env.c @@ -51,6 +51,9 @@ static enum env_location env_locations[] = { #ifdef CONFIG_ENV_IS_IN_REMOTE ENVL_REMOTE, #endif +#ifdef CONFIG_ENV_IS_IN_SATA + ENVL_ESATA, +#endif #ifdef CONFIG_ENV_IS_IN_SPI_FLASH ENVL_SPI_FLASH, #endif @@ -191,16 +194,16 @@ int env_load(void) int env_save(void) { struct env_driver *drv; - int prio; - for (prio = 0; (drv = env_driver_lookup(ENVOP_SAVE, prio)); prio++) { + drv = env_driver_lookup(ENVOP_SAVE, 0); + if (drv) { int ret; if (!drv->save) - continue; + return -ENODEV; if (!env_has_inited(drv->location)) - continue; + return -EPERM; printf("Saving Environment to %s... ", drv->name); ret = drv->save(); diff --git a/env/sata.c b/env/sata.c index 4bfe0119df8..fed799b817b 100644 --- a/env/sata.c +++ b/env/sata.c @@ -68,7 +68,7 @@ static int env_sata_save(void) return 1; printf("Writing to SATA(%d)...", env_sata); - if (write_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, &env_new)) { + if (write_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, (u_char *)env_new)) { puts("failed\n"); return 1; } @@ -91,7 +91,7 @@ static inline int read_env(struct blk_desc *sata, unsigned long size, return (n == blk_cnt) ? 0 : -1; } -static void env_sata_load(void) +static int env_sata_load(void) { ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); struct blk_desc *sata = NULL; diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 2b753df2820..25f6df38202 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -299,11 +299,20 @@ get_long_file_name(fsdata *mydata, int curclust, __u8 *cluster, if ((__u8 *)slotptr >= buflimit) { if (curclust == 0) return -1; - curclust = get_fatent(mydata, dir_curclust); - if (CHECK_CLUST(curclust, mydata->fatsize)) { - debug("curclust: 0x%x\n", curclust); - printf("Invalid FAT entry\n"); - return -1; + + if (mydata->fatsize == 32 ) { + curclust = get_fatent(mydata, dir_curclust); + if (CHECK_CLUST(curclust, mydata->fatsize)) { + debug("curclust: 0x%x\n", curclust); + printf("Invalid FAT entry\n"); + return -1; + } + } else { + /* + * In FAT16/12, the root dir is locate before data area + * curclust may negative number + */ + curclust++; } dir_curclust = curclust; @@ -582,14 +591,18 @@ static void flush_dir_table(fsdata *mydata, dir_entry **dentptr) printf("error: wrinting directory entry\n"); return; } - dir_newclust = find_empty_cluster(mydata); - set_fatent_value(mydata, dir_curclust, dir_newclust); - if (mydata->fatsize == 32) + + if (mydata->fatsize == 32) { + dir_newclust = find_empty_cluster(mydata); + set_fatent_value(mydata, dir_curclust, dir_newclust); set_fatent_value(mydata, dir_newclust, 0xffffff8); - else if (mydata->fatsize == 16) - set_fatent_value(mydata, dir_newclust, 0xfff8); - else if (mydata->fatsize == 12) - set_fatent_value(mydata, dir_newclust, 0xff8); + } else { + dir_newclust = dir_curclust + 1; + if (dir_newclust > 1) { + printf("error: fail to get empty clust for directory entry\n"); + return; + } + } dir_curclust = dir_newclust; diff --git a/include/android_image.h b/include/android_image.h index dfd4d9d72c7..91cbbbf6fd5 100644 --- a/include/android_image.h +++ b/include/android_image.h @@ -20,6 +20,19 @@ typedef struct andr_img_hdr andr_img_hdr; #define ANDR_BOOT_ARGS_SIZE 512 #define ANDR_BOOT_EXTRA_ARGS_SIZE 1024 +/* Boot metric variables (in millisecond) */ +struct boot_metric +{ + u32 bll_1; /* 1th bootloader load duration */ + u32 ble_1; /* 1th bootloader exec duration */ + u32 kl; /* kernel image load duration */ + u32 kd; /* kernel image decompress duration */ + u32 avb; /* avb verify boot.img duration */ + u32 odt; /* overlay device tree duration */ + u32 sw; /* system wait for UI interaction duration*/ +}; +typedef struct boot_metric boot_metric; + struct andr_img_hdr { char magic[ANDR_BOOT_MAGIC_SIZE]; @@ -34,7 +47,7 @@ struct andr_img_hdr { u32 tags_addr; /* physical addr for kernel tags */ u32 page_size; /* flash page size we assume */ - u32 unused; /* reserved for future expansion: MUST be 0 */ + u32 header_version; /* operating system version and security patch level; for * version "A.B.C" and patch level "Y-M-D": @@ -52,22 +65,28 @@ struct andr_img_hdr { /* Supplemental command line data; kept here to maintain * binary compatibility with older versions of mkbootimg */ char extra_cmdline[ANDR_BOOT_EXTRA_ARGS_SIZE]; + uint32_t recovery_dtbo_size; /* size of recovery dtbo image */ + uint64_t recovery_dtbo_offset; /* offset in boot image */ + uint32_t header_size; /* size of boot image header in bytes */ } __attribute__((packed)); /* * +-----------------+ * | boot header | 1 page * +-----------------+ - * | kernel | n pages + * | kernel | i pages * +-----------------+ * | ramdisk | m pages * +-----------------+ - * | second stage | o pages + * | second stage | n pages + * +-----------------+ + * | recovery dtbo | o pages * +-----------------+ * - * n = (kernel_size + page_size - 1) / page_size + * i = (kernel_size + page_size - 1) / page_size * m = (ramdisk_size + page_size - 1) / page_size - * o = (second_size + page_size - 1) / page_size + * n = (second_size + page_size - 1) / page_size + * o = (recovery_dtbo_size + page_size - 1) / page_size * * 0. all entities are page_size aligned in flash * 1. kernel and ramdisk are required (size != 0) @@ -80,4 +99,16 @@ struct andr_img_hdr { * 6. if second_size != 0: jump to second_addr * else: jump to kernel_addr */ +struct header_image { + uint32_t code0; /* Executable code */ + uint32_t code1; /* Executable code */ + uint64_t text_offset; /* Image load offset, LE */ + uint64_t image_size; /* Effective Image size, LE */ + uint64_t res1; /* reserved */ + uint64_t res2; /* reserved */ + uint64_t res3; /* reserved */ + uint64_t res4; /* reserved */ + uint32_t magic; /* Magic number */ + uint32_t res5; +}; #endif diff --git a/include/axp152.h b/include/axp152.h index 1643266f9ad..58727ba2e95 100644 --- a/include/axp152.h +++ b/include/axp152.h @@ -6,14 +6,84 @@ enum axp152_reg { AXP152_CHIP_VERSION = 0x3, + AXP152_POWER_CONTROL = 0x12, + AXP152_LDO0_VOLTAGE = 0x15, AXP152_DCDC2_VOLTAGE = 0x23, + AXP152_DCDC1_VOLTAGE = 0x26, AXP152_DCDC3_VOLTAGE = 0x27, AXP152_DCDC4_VOLTAGE = 0x2B, + AXP152_LDO1_VOLTAGE = 0x29, AXP152_LDO2_VOLTAGE = 0x2A, + AXP152_ALDO1_ALDO2_VOLTAGE = 0x28, + AXP152_POWER_RECOVERY = 0x31, AXP152_SHUTDOWN = 0x32, + AXP152_GPIO0 = 0x90, }; +enum axp152_ldo0_volts { + AXP152_LDO0_5V = 0, + AXP152_LDO0_3V3 = 1, + AXP152_LDO0_2V8 = 2, + AXP152_LDO0_2V5 = 3, +}; + +enum axp152_ldo0_curr_limit { + AXP152_LDO0_CURR_NOLMIT = 0, + AXP152_LDO0_CURR_1500MA = 1, + AXP152_LDO0_CURR_900MA = 2, + AXP152_LDO0_CURR_500MA = 3, +}; + +enum axp152_dcdc1_voltages { + AXP152_DCDC1_1V7 = 0, + AXP152_DCDC1_1V8 = 1, + AXP152_DCDC1_1V9 = 2, + AXP152_DCDC1_2V0 = 3, + AXP152_DCDC1_2V1 = 4, + AXP152_DCDC1_2V4 = 5, + AXP152_DCDC1_2V5 = 6, + AXP152_DCDC1_2V6 = 7, + AXP152_DCDC1_2V7 = 8, + AXP152_DCDC1_2V8 = 9, + AXP152_DCDC1_3V0 = 10, + AXP152_DCDC1_3V1 = 11, + AXP152_DCDC1_3V2 = 12, + AXP152_DCDC1_3V3 = 13, + AXP152_DCDC1_3V4 = 14, + AXP152_DCDC1_3V5 = 15, +}; + +enum axp152_aldo_voltages { + AXP152_ALDO_1V2 = 0, + AXP152_ALDO_1V3 = 1, + AXP152_ALDO_1V4 = 2, + AXP152_ALDO_1V5 = 3, + AXP152_ALDO_1V6 = 4, + AXP152_ALDO_1V7 = 5, + AXP152_ALDO_1V8 = 6, + AXP152_ALDO_1V9 = 7, + AXP152_ALDO_2V0 = 8, + AXP152_ALDO_2V5 = 9, + AXP152_ALDO_2V7 = 10, + AXP152_ALDO_2V8 = 11, + AXP152_ALDO_3V0 = 12, + AXP152_ALDO_3V1 = 13, + AXP152_ALDO_3V2 = 14, + AXP152_ALDO_3V3 = 15, +}; + +#define AXP152_POWEROUT_DC_DC1 BIT(7) +#define AXP152_POWEROUT_DC_DC2 BIT(6) +#define AXP152_POWEROUT_DC_DC3 BIT(5) +#define AXP152_POWEROUT_DC_DC4 BIT(4) +#define AXP152_POWEROUT_ALDO1 BIT(3) +#define AXP152_POWEROUT_ALDO2 BIT(2) +#define AXP152_POWEROUT_DLDO1 BIT(1) +#define AXP152_POWEROUT_DLDO2 BIT(0) + #define AXP152_POWEROFF (1 << 7) +#define AXP152_POWEROFF_SEQ (1 << 2) +#define AXP152_POWER_RECOVERY_EN (1 << 3) /* For axp_gpio.c */ #define AXP_GPIO0_CTRL 0x90 @@ -25,3 +95,16 @@ enum axp152_reg { #define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ #define AXP_GPIO_STATE 0x97 #define AXP_GPIO_STATE_OFFSET 0 + +int axp_set_dcdc1(enum axp152_dcdc1_voltages volt); +int axp_set_dcdc2(unsigned int mvolt); +int axp_set_dcdc3(unsigned int mvolt); +int axp_set_dcdc4(unsigned int mvolt); +int axp_set_ldo0(enum axp152_ldo0_volts volt, enum axp152_ldo0_curr_limit curr_limit); +int axp_disable_ldo0(void); +int axp_set_ldo1(unsigned int mvolt); +int axp_set_ldo2(unsigned int mvolt); +int axp_set_aldo1(enum axp152_aldo_voltages volt); +int axp_set_aldo2(enum axp152_aldo_voltages volt); +int axp_set_power_output(int val); +int axp_init(void); diff --git a/include/cdns3-uboot.h b/include/cdns3-uboot.h new file mode 100644 index 00000000000..c3593086a8b --- /dev/null +++ b/include/cdns3-uboot.h @@ -0,0 +1,25 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __CDNS3_UBOOT_H_ +#define __CDNS3_UBOOT_H_ + +#include + +struct cdns3_device { + unsigned long none_core_base; + unsigned long xhci_base; + unsigned long dev_base; + unsigned long phy_base; + unsigned long otg_base; + enum usb_dr_mode dr_mode; + int index; +}; + +int cdns3_uboot_init(struct cdns3_device *dev); +void cdns3_uboot_exit(int index); +void cdns3_uboot_handle_interrupt(int index); +#endif /* __CDNS3_UBOOT_H_ */ diff --git a/include/common.h b/include/common.h index 0fe9439a933..0554752abfc 100644 --- a/include/common.h +++ b/include/common.h @@ -164,6 +164,10 @@ int print_cpuinfo(void); int update_flash_size(int flash_size); int arch_early_init_r(void); +#ifdef CONFIG_ANDROID_BOOT_IMAGE +void get_reboot_reason(char *ret); +#endif + /* * setup_board_extra() - Fill in extra details in the bd_t structure * @@ -242,6 +246,9 @@ extern ulong save_size; /* Default Save Size */ /* common/cmd_net.c */ int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +/* common/cmd_fat.c */ +int do_fat_size(cmd_tbl_t *, int, int, char * const []); + /* common/cmd_fat.c */ int do_fat_fsload(cmd_tbl_t *, int, int, char * const []); @@ -682,6 +689,10 @@ int cpu_disable(int nr); int cpu_release(int nr, int argc, char * const argv[]); #endif +#ifdef CONFIG_CMD_READ +int do_raw_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +#endif + #else /* __ASSEMBLY__ */ /* Drop a C type modifier (like in 3UL) for constants used in assembly. */ diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index 3c1499c6fb1..a9d7e78f24a 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -16,6 +16,8 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#undef CONFIG_DM_USB #endif #undef CONFIG_DM_WARN diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h new file mode 100644 index 00000000000..68d0643c07d --- /dev/null +++ b/include/configs/imx8mm_evk.h @@ -0,0 +1,400 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8MM_EVK_H +#define __IMX8MM_EVK_H + +#include +#include + +#include "imx_env.h" + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x91fff0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00910000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_BD71837 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DMA_SUPPORT +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ + +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) +#endif + +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_BOARD_LATE_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +/* + * Another approach is add the clocks for inmates into clks_init_on + * in clk-imx8mm.c, then clk_ingore_unused could be removed. + */ +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb;" \ + "setenv jh_clk clk_ignore_unused; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 " + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) " +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=1\0"\ + "sd_dev=0\0" \ + +/* Initial environment variables */ +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "mtdparts=" MFG_NAND_PARTITION "\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=5 " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\ + "nand read ${fdt_addr} 0x7000000 0x100000;"\ + "booti ${loadaddr} - ${fdt_addr}" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + JAILHOUSE_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" +#endif + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_ENV_OFFSET (60 << 20) +#endif +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +/* USDHC */ +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +#ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_FSL_FSPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_FSPI_FLASH_SIZE SZ_32M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x30bb0000 +#define FSPI0_AMBA_BASE 0x0 +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_FSPI_QUAD_SUPPORT + +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +/* Enable SPI */ +#ifndef CONFIG_NAND_MXS +#ifndef CONFIG_FSL_FSPI +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif +#endif +#endif + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +#ifdef CONFIG_CMD_UBI +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#endif +#endif /* CONFIG_CMD_NAND */ + + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_CI_UDC + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_RM67191 +#endif + +#define CONFIG_OF_SYSTEM_SETUP + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "imx8mm_evk_android.h" +#endif +#endif diff --git a/include/configs/imx8mm_evk_android.h b/include/configs/imx8mm_evk_android.h new file mode 100644 index 00000000000..1bb37cc3bb5 --- /dev/null +++ b/include/configs/imx8mm_evk_android.h @@ -0,0 +1,77 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8MM_EVK_ANDROID_H +#define IMX8MM_EVK_ANDROID_H + +#define CONFIG_BCB_SUPPORT +#define CONFIG_CMD_READ + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_FLASH +#define CONFIG_FASTBOOT_STORAGE_MMC + +#define CONFIG_FSL_FASTBOOT +#define CONFIG_ANDROID_RECOVERY + +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +/* Enable mcu firmware flash */ +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC +#define ANDROID_MCU_FIRMWARE_START 0x500000 +#define ANDROID_MCU_FIRMWARE_SIZE 0x40000 +#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000 +#endif + +#ifdef CONFIG_FSL_CAAM_KB +#undef CONFIG_FSL_CAAM_KB +#endif +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#ifdef CONFIG_IMX_TRUSTY_OS +#define AVB_RPMB +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x1FFF +#define NS_ARCH_ARM64 1 + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_BLK +#endif + +#endif + +#endif /* IMX8MM_EVK_ANDROID_H */ diff --git a/include/configs/imx8mm_val.h b/include/configs/imx8mm_val.h new file mode 100644 index 00000000000..f1c9122cc9c --- /dev/null +++ b/include/configs/imx8mm_val.h @@ -0,0 +1,333 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8MM_VAL_H +#define __IMX8MM_VAL_H + +#include +#include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x91FFF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00910000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00911000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_BD71837 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_BOARD_LATE_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define FEC_QUIRK_ENET_MAC + +#define IMX_FEC_BASE 0x30BE0000 +#define CONFIG_PHYLIB + +#ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_PHY_REALTEK +#define CONFIG_FEC_MXC_PHYADDR 3 +#else +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_PHY_ATHEROS +#define CONFIG_PHY_GIGE +#endif + +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +/* USDHC */ +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +#ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_FSL_FSPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_FSPI_FLASH_SIZE SZ_32M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x30bb0000 +#define FSPI0_AMBA_BASE 0x0 +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_FSPI_QUAD_SUPPORT + +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +/* Enable SPI */ +#ifdef CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 8000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +#ifdef CONFIG_CMD_UBI +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#endif +#endif /* CONFIG_CMD_NAND */ + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_CI_UDC + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + + +#define CONFIG_OF_SYSTEM_SETUP + +#endif diff --git a/include/configs/imx8mq_aiy.h b/include/configs/imx8mq_aiy.h new file mode 100644 index 00000000000..5138df8c14d --- /dev/null +++ b/include/configs/imx8mq_aiy.h @@ -0,0 +1,288 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8M_PHANBELL_ +#define __IMX8M_PHANBELL_ + +#include +#include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NS_ARCH_ARM64 1 +#endif +#ifdef CONFIG_AVB_ATX +#define PERMANENT_ATTRIBUTE_HASH_OFFSET 0 +#endif +#define CONFIG_MMC_RPMB_TRACE + +#define CONFIG_SPL_TEXT_BASE 0x7E1000 +/* 124k spl max size */ +#define CONFIG_SPL_MAX_SIZE 126976 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x800000 /* 8 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_BD71837 +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_BOARD_LATE_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8mq-phanbell.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0xC0000000 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */ +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#define FSL_QSPI_FLASH_SIZE (SZ_32M) +#define FSL_QSPI_FLASH_NUM 1 +#endif + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD + +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE + + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_OF_SYSTEM_SETUP + +#if defined (CONFIG_ANDROID_SUPPORT) +#include "imx8mq_aiy_android.h" +#endif + +#define PRODUCT_NAME "imx8m" +#define VARIANT_NAME "imx8m_aiy" +#endif diff --git a/include/configs/imx8mq_aiy_android.h b/include/configs/imx8mq_aiy_android.h new file mode 100644 index 00000000000..5b5a86c2c59 --- /dev/null +++ b/include/configs/imx8mq_aiy_android.h @@ -0,0 +1,102 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8MQ_AIY_ANDROID_H +#define IMX8MQ_AIY_ANDROID_H + +#define CONFIG_CMD_READ + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE_BANK_SIZEW 4 +#define CONFIG_AVB_FUSE_BANK_START 14 +#define CONFIG_AVB_FUSE_BANK_END 14 +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +#ifdef CONFIG_AVB_ATX +#define UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD 0 +#define UNLOCK_VBOOT_STATUS_OFFSET_IN_BIT 0 +#endif + +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +#define CONFIG_ANDROID_RECOVERY + +/* Use below address to store the bootloader rbindex, + * it's 4k offset to CONFIG_SYS_SPL_PTE_RAM_BASE + * */ +#if defined(CONFIG_AVB_ATX) && defined(CONFIG_DUAL_BOOTLOADER) +#define BL_RBINDEX_LOAD_ADDR 0x4157F000 +#endif + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#define AIY_MICRON_3G 0x1 +#define AIY_MICRON_1G 0x5 +#define AIY_HYNIX_1G 0x3 + +#define TEE_LOAD_ADDR_1G 0x7e000000 +#define TEE_LOAD_ADDR_3G 0xfe000000 + + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_IMX_TRUSTY_OS) +#define AVB_RPMB +#endif + +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x1FFF + +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_SPL_SHA256 +#undef CONFIG_ENV_IS_IN_MMC +#undef CONFIG_BLK +#define CONFIG_ENV_IS_NOWHERE + +#ifdef AVB_RPMB +#define BOOTLOADER_RBIDX_OFFSET 0x1E000 +#define BOOTLOADER_RBIDX_START 0x1F000 +#define BOOTLOADER_RBIDX_LEN 0x08 +#define BOOTLOADER_RBIDX_INITVAL 0 +#endif + +#else +/* imx8m won't touch CAAM in non-secure world. */ +#undef CONFIG_FSL_CAAM_KB +#endif + +/* Enlarge the spl max size to 172k */ +#ifdef CONFIG_SPL_MAX_SIZE +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE 176128 +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#ifdef CONFIG_DUAL_BOOTLOADER +#define ANDROID_SPL_SIZE 0x80000 +#endif +#endif + +#endif /* IMX8MQ_AIY_ANDROID_H */ diff --git a/include/configs/imx8mq_arm2.h b/include/configs/imx8mq_arm2.h new file mode 100644 index 00000000000..d60160127b6 --- /dev/null +++ b/include/configs/imx8mq_arm2.h @@ -0,0 +1,351 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8M_ARM2_H +#define __IMX8M_ARM2_H + +#include +#include +#include "imx_env.h" + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif + +#define CONFIG_SPL_TEXT_BASE 0x7E1000 +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DMA_SUPPORT +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ + +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) +#endif + +#endif /* CONFIG_SPL_BUILD*/ + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_BOARD_LATE_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define FEC_QUIRK_ENET_MAC + +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB + +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_PHY_REALTEK +#define CONFIG_FEC_MXC_PHYADDR 3 +#else +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_PHY_ATHEROS +#define CONFIG_PHY_GIGE +#endif + +#endif + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) " +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "mtdparts=" MFG_NAND_PARTITION "\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "bootargs=console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200 ubi.mtd=5 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\ + "nand read ${fdt_addr} 0x7000000 0x100000;"\ + "booti ${loadaddr} - ${fdt_addr}" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" +#endif + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + + +#define CONFIG_ENV_SIZE 0x1000 +#ifdef CONFIG_NAND_BOOT +#define CONFIG_ENV_OFFSET (60 << 20) +#else +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR3L for two rank */ +#define CONFIG_NR_DRAM_BANKS 1 +#else +#define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1GB */ +#define CONFIG_NR_DRAM_BANKS 2 +#endif + + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 1 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#define FSL_QSPI_FLASH_SIZE (SZ_2M) +#define FSL_QSPI_FLASH_NUM 2 +#endif + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +#ifdef CONFIG_CMD_UBI +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#endif + +#endif + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE + +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_OF_SYSTEM_SETUP + +#endif diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h new file mode 100644 index 00000000000..6cff7fea2b1 --- /dev/null +++ b/include/configs/imx8mq_evk.h @@ -0,0 +1,312 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8M_EVK_H +#define __IMX8M_EVK_H + +#include +#include +#include "imx_env.h" + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif + +#define CONFIG_SPL_TEXT_BASE 0x7E1000 +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_BOARD_LATE_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +/* + * Another approach is add the clocks for inmates into clks_init_on + * in clk-imx8mq.c, then clk_ingore_unused could be removed. + */ +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_mmcboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; " \ + "setenv jh_clk clk_ignore_unused; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 " + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + JAILHOUSE_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8mq-evk.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */ +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#define FSL_QSPI_FLASH_SIZE (SZ_32M) +#define FSL_QSPI_FLASH_NUM 1 +#endif + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD + +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#define CONFIG_CMD_READ + +#endif + +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_OF_SYSTEM_SETUP + +/* Framebuffer */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IMXDCSS +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "imx8mq_evk_android.h" +#elif defined (CONFIG_ANDROID_THINGS_SUPPORT) +#include "imx8mq_evk_androidthings.h" +#endif +#endif diff --git a/include/configs/imx8mq_evk_android.h b/include/configs/imx8mq_evk_android.h new file mode 100644 index 00000000000..fa06e01cc39 --- /dev/null +++ b/include/configs/imx8mq_evk_android.h @@ -0,0 +1,54 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8MQ_EVK_ANDROID_H +#define IMX8MQ_EVK_ANDROID_H + +#define CONFIG_CMD_READ + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +#define CONFIG_ANDROID_RECOVERY + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +/* Enable mcu firmware flash */ +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC +#define ANDROID_MCU_FIRMWARE_START 0x500000 +#define ANDROID_MCU_FIRMWARE_SIZE 0x40000 +#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000 +#endif + +#ifdef CONFIG_FSL_CAAM_KB +#undef CONFIG_FSL_CAAM_KB +#endif +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif /* IMX8MQ_EVK_ANDROID_H */ diff --git a/include/configs/imx8mq_evk_androidthings.h b/include/configs/imx8mq_evk_androidthings.h new file mode 100644 index 00000000000..a67b5d4180f --- /dev/null +++ b/include/configs/imx8mq_evk_androidthings.h @@ -0,0 +1,104 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8MQ_EVK_ANDROID_THINGS_H +#define IMX8MQ_EVK_ANDROID_THINGS_H + +#define CONFIG_CMD_READ + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE_BANK_SIZEW 4 +#define CONFIG_AVB_FUSE_BANK_START 14 +#define CONFIG_AVB_FUSE_BANK_END 14 +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +#ifdef CONFIG_AVB_ATX +#define UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD 0 +#define UNLOCK_VBOOT_STATUS_OFFSET_IN_BIT 0 +#endif + +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) +#endif + +#define CONFIG_ANDROID_RECOVERY + +/* Use below address to store the bootloader rbindex, + * it's 4k offset to CONFIG_SYS_SPL_PTE_RAM_BASE + * */ +#if defined(CONFIG_AVB_ATX) && defined(CONFIG_DUAL_BOOTLOADER) +#define BL_RBINDEX_LOAD_ADDR 0x4157F000 +#endif + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#define ENTERPRISE_MICRON_1G 0x5c +#define ENTERPRISE_HYNIX_1G 0x56 +#define ENTERPRISE_MIRCONB_3G 0x40 +#define WIBO_3G 0x00 +#define IMX8M_REF_3G 0x00 + +#define TEE_LOAD_ADDR_1G 0x7e000000 +#define TEE_LOAD_ADDR_3G 0xfe000000 + + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_IMX_TRUSTY_OS) +#define AVB_RPMB +#endif + +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x1FFF + +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_SPL_SHA256 +#undef CONFIG_ENV_IS_IN_MMC +#undef CONFIG_BLK +#define CONFIG_ENV_IS_NOWHERE + +#ifdef AVB_RPMB +#define BOOTLOADER_RBIDX_OFFSET 0x1E000 +#define BOOTLOADER_RBIDX_START 0x1F000 +#define BOOTLOADER_RBIDX_LEN 0x08 +#define BOOTLOADER_RBIDX_INITVAL 0 +#endif + +#else +/* imx8m won't touch CAAM in non-secure world. */ +#undef CONFIG_FSL_CAAM_KB +#endif + +/* Enlarge the spl max size to 172k */ +#ifdef CONFIG_SPL_MAX_SIZE +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE 176128 +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#ifdef CONFIG_DUAL_BOOTLOADER +#define ANDROID_SPL_SIZE 0x80000 +#endif +#endif + +#endif /* IMX8MQ_EVK_ANDROID_THINGS_H */ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h new file mode 100644 index 00000000000..bb29ebc186c --- /dev/null +++ b/include/configs/imx8mq_phanbell.h @@ -0,0 +1,288 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8M_PHANBELL_ +#define __IMX8M_PHANBELL_ + +#include +#include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NS_ARCH_ARM64 1 +#endif +#ifdef CONFIG_AVB_ATX +#define PERMANENT_ATTRIBUTE_HASH_OFFSET 0 +#endif +#define CONFIG_MMC_RPMB_TRACE + +#define CONFIG_SPL_TEXT_BASE 0x7E1000 +/* 124k spl max size */ +#define CONFIG_SPL_MAX_SIZE 126976 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x800000 /* 8 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_BD71837 +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_BOARD_LATE_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8mq-phanbell.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0xBE000000 /* (3GB - 32M) DDR for uboot */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */ +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#define FSL_QSPI_FLASH_SIZE (SZ_32M) +#define FSL_QSPI_FLASH_NUM 1 +#endif + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD + +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE + + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_OF_SYSTEM_SETUP + +#if defined (CONFIG_ANDROID_THINGS_SUPPORT) +#include "imx8mq_evk_androidthings.h" +#endif + +#define PRODUCT_NAME "imx8m" +#define VARIANT_NAME "imx8m_phanbell" +#endif diff --git a/include/configs/imx8qm_arm2.h b/include/configs/imx8qm_arm2.h new file mode 100644 index 00000000000..bf87664e37e --- /dev/null +++ b/include/configs/imx8qm_arm2.h @@ -0,0 +1,441 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8QM_ARM2_H +#define __IMX8QM_ARM2_H + +#include +#include + +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_PARSE_CONTAINER +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (flash.bin_offset + 2Mb)/sector_size */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 +#define CONFIG_SYS_UBOOT_BASE 0x08281000 + +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#define CONFIG_OF_EMBED +#define CONFIG_ATF_TEXT_BASE 0x80000000 +#define CONFIG_SYS_ATF_START 0x80000000 +/* #define CONFIG_FIT */ + +/* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */ +#define SC_IPC_CH SC_IPC_AP_CH0 + +#endif + + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#endif + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SCSI +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_SATA_IMX + +#define CONFIG_FSL_HSIO +#define CONFIG_PCIE_IMX8X +#define CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* FUSE command */ +#define CONFIG_CMD_FUSE + +/* GPIO configs */ +#define CONFIG_MXC_GPIO + +/* ENET Config */ +#define CONFIG_MII + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */ +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE 0x5B040000 +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE 0x5B050000 +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_ENABLE_MAX7322 +#define CONFIG_ETHPRIME "eth1" +#endif + +/* ENET0 MDIO are shared */ +#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000 + +#define CONFIG_LIB_RAND +#define CONFIG_NET_RANDOM_ETHADDR + +/* MAX7322 */ +#ifdef CONFIG_FEC_ENABLE_MAX7322 +#define CONFIG_MAX7322_I2C_ADDR 0x68 +#define CONFIG_MAX7322_I2C_BUS 2 /* I2C2 */ +#endif + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#define XEN_BOOT_ENV \ + "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true hmp-unsafe=true\0" \ + "xenlinux_bootargs= \0" \ + "xenlinux_console=hvc0 earlycon=xen\0" \ + "xenlinux_addr=0x85000000\0" \ + "dom0fdt_file=fsl-imx8qm-lpddr4-arm2-dom0.dtb\0" \ + "xenboot_common=" \ + "${get_cmd} ${loadaddr} xen;" \ + "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ + "${get_cmd} ${xenlinux_addr} ${image};" \ + "fdt addr ${fdt_addr};" \ + "fdt resize 256;" \ + "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ + "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ + "setenv bootargs ${xenhyper_bootargs};" \ + "scu_rm dtb ${fdt_addr};" \ + "booti ${loadaddr} - ${fdt_addr};" \ + "\0" \ + "xennetboot=" \ + "setenv get_cmd dhcp;" \ + "setenv console ${xenlinux_console};" \ + "run netargs;" \ + "run xenboot_common;" \ + "\0" \ + "xenmmcboot=" \ + "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ + "setenv console ${xenlinux_console};" \ + "run mmcargs;" \ + "run xenboot_common;" \ + "\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + XEN_BOOT_ENV \ + M4_BOOT_ENV \ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "earlycon=lpuart32,0x5a060000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fdt=try\0" \ + "fdt_file="__stringify(CONFIG_DEFAULT_DEVICE_TREE)".dtb\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "hdp_addr=0x84000000\0" \ + "hdp_file=dpfw.bin\0" \ + "loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "if run loadhdp; then; hdp load ${hdp_addr}; fi;" \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + + +/* Default environment is in SD */ +#define CONFIG_ENV_SIZE 0x2000 + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#else +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board, USDHC3 is for SD on base board + * On DDR4 board, USDHC1 is mux for NAND, USDHC2 is for SD, USDHC3 is for SD on base board + */ +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC1 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC1 */ +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +#else + +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 4 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +/* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4GB */ +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ +#else +#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#endif + +#define CONFIG_IMX_SMMU + +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ +#ifdef CONFIG_FSL_FSPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_FSPI_FLASH_SIZE SZ_64M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x5d120000 +#define FSPI0_AMBA_BASE 0 +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +/* USB Config */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif +#endif /* CONFIG_CMD_USB */ + +#ifdef CONFIG_USB_GADGET +#define CONFIG_USBD_HS +#endif + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "imx8qm_arm2_android.h" +#endif + +/* Framebuffer */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IMXDPUV1 +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +#define CONFIG_OF_SYSTEM_SETUP + +#endif /* __IMX8QM_ARM2_H */ diff --git a/include/configs/imx8qm_arm2_android.h b/include/configs/imx8qm_arm2_android.h new file mode 100644 index 00000000000..32cd12cb640 --- /dev/null +++ b/include/configs/imx8qm_arm2_android.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QM_ARM2_ANDROID_H +#define IMX8QM_ARM2_ANDROID_H + +#define CONFIG_USBD_HS + +#define CONFIG_BCB_SUPPORT +#define CONFIG_CMD_READ +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) +#endif + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_FLASH + +#define CONFIG_FSL_FASTBOOT +#define CONFIG_FASTBOOT_USB_DEV 1 +#define CONFIG_ANDROID_RECOVERY + +#if defined CONFIG_SYS_BOOT_SATA +#define CONFIG_FASTBOOT_STORAGE_SATA +#define CONFIG_FASTBOOT_SATA_NO 0 +#else +#define CONFIG_FASTBOOT_STORAGE_MMC +#endif + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif /* MX6_SABRE_ANDROID_COMMON_H */ diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h new file mode 100644 index 00000000000..ce12bd6f4cf --- /dev/null +++ b/include/configs/imx8qm_mek.h @@ -0,0 +1,453 @@ +/* + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8QM_MEK_H +#define __IMX8QM_MEK_H + +#include +#include +#include "imx_env.h" + +#ifdef CONFIG_SPL_BUILD + +#ifdef CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#endif + +#define CONFIG_PARSE_CONTAINER +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (flash.bin_offset + 2Mb)/sector_size */ +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x200000 + +/* + * 0x08081000 - 0x08180FFF is for m4_0 xip image, + * 0x08181000 - 0x008280FFF is for m4_1 xip image + * So 3rd container image may start from 0x8281000 + */ +#define CONFIG_SYS_UBOOT_BASE 0x08281000 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + + +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00138000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#define CONFIG_OF_EMBED +#define CONFIG_ATF_TEXT_BASE 0x80000000 +#define CONFIG_SYS_ATF_START 0x80000000 +/* #define CONFIG_FIT */ + +/* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */ +#define SC_IPC_CH SC_IPC_AP_CH0 + +#endif + + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT + +#define CONFIG_CMD_READ + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SCSI +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_SATA_IMX + +#define CONFIG_FSL_HSIO +#define CONFIG_PCIE_IMX8X +#define CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* FUSE command */ +#define CONFIG_CMD_FUSE + +/* GPIO configs */ +#define CONFIG_MXC_GPIO + +/* ENET Config */ +#define CONFIG_MII + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */ +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE 0x5B040000 +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE 0x5B050000 +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_ETHPRIME "eth1" +#endif + +/* ENET0 MDIO are shared */ +#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000 + +#define CONFIG_LIB_RAND +#define CONFIG_NET_RANDOM_ETHADDR + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +#define JAILHOUSE_ENV \ + "jh_mmcboot=" \ + "setenv fdt_file fsl-imx8qm-mek-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run mmcboot; \0" \ + "jh_netboot=" \ + "setenv fdt_file fsl-imx8qm-mek-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run netboot; \0" + +#define XEN_BOOT_ENV \ + "domu-android-auto=no\0" \ + "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true hmp-unsafe=true\0" \ + "xenlinux_bootargs= \0" \ + "xenlinux_console=hvc0 earlycon=xen\0" \ + "xenlinux_addr=0x92000000\0" \ + "dom0fdt_file=fsl-imx8qm-mek-dom0.dtb\0" \ + "xenboot_common=" \ + "${get_cmd} ${loadaddr} xen;" \ + "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ + "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ + "if ${get_cmd} ${hdprx_addr} ${hdprx_file}; then; hdprx load ${hdprx_addr}; fi;" \ + "${get_cmd} ${xenlinux_addr} ${image};" \ + "fdt addr ${fdt_addr};" \ + "fdt resize 256;" \ + "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ + "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ + "if test ${domu-android-auto} = yes; then; " \ + "fdt set /domu/doma android-auto <1>;" \ + "fdt rm /gpio@5d090000 power-domains;" \ + "fi;" \ + "setenv bootargs ${xenhyper_bootargs};" \ + "booti ${loadaddr} - ${fdt_addr};" \ + "\0" \ + "xennetboot=" \ + "setenv get_cmd dhcp;" \ + "setenv console ${xenlinux_console};" \ + "run netargs;" \ + "run xenboot_common;" \ + "\0" \ + "xenmmcboot=" \ + "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ + "setenv console ${xenlinux_console};" \ + "run mmcargs;" \ + "run xenboot_common;" \ + "\0" \ +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + XEN_BOOT_ENV \ + JAILHOUSE_ENV\ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "earlycon=lpuart32,0x5a060000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fdt=try\0" \ + "fdt_file=undefined\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "hdp_addr=0x84000000\0" \ + "hdprx_addr=0x84800000\0" \ + "hdp_file=hdmitxfw.bin\0" \ + "hdprx_file=hdmirxfw.bin\0" \ + "loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \ + "loadhdprx=fatload mmc ${mmcdev}:${mmcpart} ${hdprx_addr} ${hdprx_file}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "if run loadhdp; then; hdp load ${hdp_addr}; fi;" \ + "if run loadhdprx; then; hdprx load ${hdprx_addr}; fi;" \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ + "if ${get_cmd} ${hdprx_addr} ${hdprx_file}; then; hdprx load ${hdprx_addr}; fi;" \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + + +/* Default environment is in SD */ +#define CONFIG_ENV_SIZE 0x2000 + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#else +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 4 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#define CONFIG_IMX_SMMU + +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ +#ifdef CONFIG_FSL_FSPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_FSPI_FLASH_SIZE SZ_64M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x5d120000 +#define FSPI0_AMBA_BASE 0 +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +#define CONFIG_SERIAL_TAG + +/* USB Config */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#define CONFIG_USB_EHCI_HCD +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +/* Framebuffer */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IMXDPUV1 +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +#define CONFIG_OF_SYSTEM_SETUP + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "imx8qm_mek_android.h" +#elif defined (CONFIG_ANDROID_AUTO_SUPPORT) +#include "imx8qm_mek_android_auto.h" +#elif defined (CONFIG_IMX8_TRUSTY_XEN) +#include "imx8qm_mek_trusty_xen.h" +#endif + +#endif /* __IMX8QM_MEK_H */ diff --git a/include/configs/imx8qm_mek_android.h b/include/configs/imx8qm_mek_android.h new file mode 100644 index 00000000000..42a261f020b --- /dev/null +++ b/include/configs/imx8qm_mek_android.h @@ -0,0 +1,71 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QM_MEK_ANDROID_H +#define IMX8QM_MEK_ANDROID_H + +#define CONFIG_USBD_HS + +#define CONFIG_BCB_SUPPORT +#define CONFIG_CMD_READ +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +#define IMX_LOAD_HDMI_FIMRWARE +#define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M) +#define IMX_HDMITX_FIRMWARE_SIZE 0x20000 +#define IMX_HDMIRX_FIRMWARE_SIZE 0x20000 + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (76 * SZ_1M) +#endif + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT + +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_FLASH + +#define CONFIG_FSL_FASTBOOT +#define CONFIG_FASTBOOT_USB_DEV 1 +#define CONFIG_ANDROID_RECOVERY + +#if defined CONFIG_SYS_BOOT_SATA +#define CONFIG_FASTBOOT_STORAGE_SATA +#define CONFIG_FASTBOOT_SATA_NO 0 +#else +#define CONFIG_FASTBOOT_STORAGE_MMC +#endif + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "panel=NULL\0" \ + +#define CONFIG_FASTBOOT_BUF_ADDR 0x98000000 +#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif /* IMX8QM_MEK_ANDROID_H */ diff --git a/include/configs/imx8qm_mek_android_auto.h b/include/configs/imx8qm_mek_android_auto.h new file mode 100644 index 00000000000..c0a0683ad3c --- /dev/null +++ b/include/configs/imx8qm_mek_android_auto.h @@ -0,0 +1,127 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QM_MEK_ANDROID_AUTO_H +#define IMX8QM_MEK_ANDROID_AUTO_H + +#define CONFIG_USBD_HS + +#define CONFIG_BCB_SUPPORT +#define CONFIG_CMD_READ +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NS_ARCH_ARM64 1 +#endif + +#define CONFIG_SKIP_RESOURCE_CHECING +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#ifndef CONFIG_MXC_USB_PORTSC +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x3FFF + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT + +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_FLASH + +#define CONFIG_FSL_FASTBOOT +#define CONFIG_FASTBOOT_USB_DEV 1 +#define CONFIG_ANDROID_RECOVERY + +#if defined CONFIG_SYS_BOOT_SATA +#define CONFIG_FASTBOOT_STORAGE_SATA +#define CONFIG_FASTBOOT_SATA_NO 0 +#else +#define CONFIG_FASTBOOT_STORAGE_MMC +#endif + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +#define CONFIG_FASTBOOT_BUF_ADDR 0x98000000 +#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 + +/* Undefine some macros to save boot time */ +#undef CONFIG_FEC_MXC +#undef CONFIG_USB_HOST_ETHER +#undef CONFIG_ARCH_MISC_INIT +#undef CONFIG_SCSI +#undef CONFIG_SCSI_AHCI +#undef CONFIG_SCSI_AHCI_PLAT +#undef CONFIG_CMD_SCSI +#undef CONFIG_LIBATA +#undef CONFIG_SATA_IMX +#undef CONFIG_FSL_HSIO +#undef CONFIG_PCIE_IMX8X +#undef CONFIG_CMD_PCI +#undef CONFIG_PCI +#undef CONFIG_SYS_LONGHELP +#undef CONFIG_HUSH_PARSER +#undef CONFIG_AUTO_COMPLETE +#undef CONFIG_MII +#undef CONFIG_PHYLIB +#undef CONFIG_PHY_ATHEROS +#undef CONFIG_CMD_FUSE +#undef CONFIG_CMD_USB_MASS_STORAGE +#undef CONFIG_USB_FUNCTION_MASS_STORAGE +#undef CONFIG_FAT_WRITE + +#if defined(CONFIG_XEN) +#include "imx8qm_mek_android_auto_xen.h" +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#define AVB_RPMB +#ifdef CONFIG_DUAL_BOOTLOADER +#define BOOTLOADER_RBIDX_OFFSET 0x3FE000 +#define BOOTLOADER_RBIDX_START 0x3FF000 +#define BOOTLOADER_RBIDX_LEN 0x08 +#define BOOTLOADER_RBIDX_INITVAL 0 +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x801F8000 +#endif +#endif + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_BLK +#define CONFIG_FSL_CAAM_KB +#define CONFIG_SPL_CRYPTO_SUPPORT +#define CONFIG_SYS_FSL_SEC_LE +#endif + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif /* IMX8QM_MEK_ANDROID_AUTO_H */ diff --git a/include/configs/imx8qm_mek_android_auto_xen.h b/include/configs/imx8qm_mek_android_auto_xen.h new file mode 100644 index 00000000000..e754ca0b159 --- /dev/null +++ b/include/configs/imx8qm_mek_android_auto_xen.h @@ -0,0 +1,59 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QM_MEK_ANDROID_AUTO_XEN_H +#define IMX8QM_MEK_ANDROID_AUTO_XEN_H + +#undef CONFIG_SYS_SDRAM_BASE +#undef CONFIG_NR_DRAM_BANKS +#undef PHYS_SDRAM_1 +#undef PHYS_SDRAM_2 +#undef PHYS_SDRAM_1_SIZE +#undef PHYS_SDRAM_2_SIZE + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x200000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x50000000 /* 1280 MB */ + +#undef CONFIG_LOADADDR +#define CONFIG_LOADADDR 0x80080000 +#undef CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_INIT_SP_ADDR 0x81200000 + +#undef CONFIG_REQUIRE_SERIAL_CONSOLE +#undef CONFIG_IMX_SMMU + +#undef CONFIG_FASTBOOT_USB_DEV +#define CONFIG_FASTBOOT_USB_DEV 0 /* Use OTG port, not typec port */ + +/* This needs to be stay same in iomem in domu.cfg */ +#ifdef SC_IPC_CH +#undef SC_IPC_CH +#endif +#define SC_IPC_CH 0x5d1d0000 + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_SPL_BSS_START_ADDR +#undef CONFIG_SYS_SPL_MALLOC_START +#undef CONFIG_MALLOC_F_ADDR +#undef CONFIG_SPL_TEXT_BASE +#undef CONFIG_SPL_STACK + +#define CONFIG_SPL_TEXT_BASE 0x80080000 +#define CONFIG_MALLOC_F_ADDR 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SPL_BSS_START_ADDR 0x80300000 +#define CONFIG_SPL_STACK 0x80400000 + +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x80500000 +#endif + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif /* IMX8QM_MEK_ANDROID_AUTO_XEN_H */ diff --git a/include/configs/imx8qm_mek_trusty_xen.h b/include/configs/imx8qm_mek_trusty_xen.h new file mode 100644 index 00000000000..601b5165ba7 --- /dev/null +++ b/include/configs/imx8qm_mek_trusty_xen.h @@ -0,0 +1,23 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8QM_MEK_TRUSTY_XEN_H +#define __IMX8QM_MEK_TRUSTY_XEN_H + +#ifdef CONFIG_SPL_BUILD + +#undef CONFIG_BLK +#define CONFIG_AVB_SUPPORT +#define AVB_RPMB +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x3FFF +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#define CONFIG_SUPPORT_EMMC_RPMB + +#endif + +#endif diff --git a/include/configs/imx8qxp_arm2.h b/include/configs/imx8qxp_arm2.h new file mode 100644 index 00000000000..a2e94944964 --- /dev/null +++ b/include/configs/imx8qxp_arm2.h @@ -0,0 +1,443 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8QXP_ARM2_H +#define __IMX8QXP_ARM2_H + +#include +#include + +#include "imx_env.h" + +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_PARSE_CONTAINER + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SPL_SPI_LOAD +#endif + +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) + +#ifdef CONFIG_NAND_BOOT +#ifndef CONFIG_PARSE_CONTAINER +#define CONFIG_SPL_NAND_RAW_ONLY +#endif +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DMA_SUPPORT +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0x8000000) /*Put the FIT out of first 128MB boot area */ +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SYS_NAND_U_BOOT_DST 0x80000000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 * 1024 ) + +#define CONFIG_SYS_NAND_U_BOOT_START 0x80000000 +#endif + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + + +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00138000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x8000 /* 20 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 60 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#define CONFIG_OF_EMBED +#define CONFIG_ATF_TEXT_BASE 0x80000000 +#define CONFIG_SYS_ATF_START 0x80000000 +/* #define CONFIG_FIT */ + +/* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */ +#define SC_IPC_CH SC_IPC_AP_CH0 + +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + + +#define CONFIG_FSL_HSIO +#ifdef CONFIG_FSL_HSIO +#define CONFIG_PCIE_IMX8X +#define CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* FUSE command */ +#define CONFIG_CMD_FUSE + +/* GPIO configs */ +#define CONFIG_MXC_GPIO + +/* ENET Config */ +#define CONFIG_MII + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */ +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE 0x5B040000 +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE 0x5B050000 +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_ENABLE_MAX7322 +#define CONFIG_ETHPRIME "eth1" +#endif + +/* ENET0 MDIO are shared */ +#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000 + +#define CONFIG_LIB_RAND +#define CONFIG_NET_RANDOM_ETHADDR + +/* MAX7322 */ +#ifdef CONFIG_FEC_ENABLE_MAX7322 +#define CONFIG_MAX7322_I2C_ADDR 0x68 +#define CONFIG_MAX7322_I2C_BUS 0 /* I2C1 */ +#endif + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) " +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#ifdef CONFIG_NAND_BOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "bootargs=console=ttyLP0,115200 ubi.mtd=6 " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0"\ + "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \ + "mtdparts=" MFG_NAND_PARTITION "\0" \ + "fdt_addr=0x83000000\0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "earlycon=lpuart32,0x5a060000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_BOOTCOMMAND \ + "nand read ${loadaddr} 0x9000000 0x2000000;"\ + "nand read ${fdt_addr} 0xB000000 0x100000;"\ + "booti ${loadaddr} - ${fdt_addr}" +#else +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" +#endif + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + + +/* Default environment is in SD */ +#define CONFIG_ENV_SIZE 0x2000 + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_ENV_OFFSET (120 << 20) +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#else +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board + */ +#ifdef CONFIG_TARGET_IMX8X_17X17_VAL +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 4 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#if defined(CONFIG_TARGET_IMX8QXP_DDR3_ARM2) || defined(CONFIG_TARGET_IMX8X_17X17_VAL) +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB totally */ +#define PHYS_SDRAM_2_SIZE 0x00000000 +#else +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +/* LPDDR4 board total DDR is 3GB */ +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#endif + +#define CONFIG_IMX_SMMU + +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ +#ifdef CONFIG_FSL_FSPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_FSPI_FLASH_SIZE SZ_64M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x5d120000 +#define FSPI0_AMBA_BASE 0 +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +/* USB Config */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif +#endif /* CONFIG_CMD_USB */ + +#ifdef CONFIG_USB_GADGET +#define CONFIG_USBD_HS +#endif + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "imx8qxp_arm2_android.h" +#endif + +/* Framebuffer */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IMXDPUV1 +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +#define CONFIG_OF_SYSTEM_SETUP + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG + +#endif /* __IMX8QXP_ARM2_H */ diff --git a/include/configs/imx8qxp_arm2_android.h b/include/configs/imx8qxp_arm2_android.h new file mode 100644 index 00000000000..590fb329cd3 --- /dev/null +++ b/include/configs/imx8qxp_arm2_android.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QXP_ARM2_ANDROID_H +#define IMX8QXP_ARM2_ANDROID_H + +#define CONFIG_USBD_HS + +#define CONFIG_BCB_SUPPORT +#define CONFIG_CMD_READ +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_FLASH + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) +#endif + +#define CONFIG_FSL_FASTBOOT +#define CONFIG_FASTBOOT_USB_DEV 1 +#define CONFIG_ANDROID_RECOVERY + +#if defined CONFIG_SYS_BOOT_SATA +#define CONFIG_FASTBOOT_STORAGE_SATA +#define CONFIG_FASTBOOT_SATA_NO 0 +#else +#define CONFIG_FASTBOOT_STORAGE_MMC +#endif + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif /* IMX8QXP_ARM2_ANDROID_H */ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h new file mode 100644 index 00000000000..298f80eec19 --- /dev/null +++ b/include/configs/imx8qxp_mek.h @@ -0,0 +1,430 @@ +/* + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8QXP_MEK_H +#define __IMX8QXP_MEK_H + +#include +#include + +#include "imx_env.h" + +#ifdef CONFIG_SPL_BUILD + +#ifdef CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#endif + +#define CONFIG_PARSE_CONTAINER +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */ +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x200000 + +/* + * 0x08081000 - 0x08180FFF is for m4_0 xip image, + * So 3rd container image may start from 0x8181000 + */ +#define CONFIG_SYS_UBOOT_BASE 0x08181000 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + + +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00138000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#define CONFIG_OF_EMBED +#define CONFIG_ATF_TEXT_BASE 0x80000000 +#define CONFIG_SYS_ATF_START 0x80000000 +/* #define CONFIG_FIT */ + +/* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */ +#define SC_IPC_CH SC_IPC_AP_CH0 + +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT + +#define CONFIG_CMD_READ + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + + +#define CONFIG_FSL_HSIO +#ifdef CONFIG_FSL_HSIO +#define CONFIG_PCIE_IMX8X +#define CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* FUSE command */ +#define CONFIG_CMD_FUSE + +/* GPIO configs */ +#define CONFIG_MXC_GPIO + +/* ENET Config */ +#define CONFIG_MII + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */ +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE 0x5B040000 +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE 0x5B050000 +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_ETHPRIME "eth1" +#endif + +/* ENET0 MDIO are shared */ +#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000 + +#define CONFIG_LIB_RAND +#define CONFIG_NET_RANDOM_ETHADDR + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" \ + +#define JAILHOUSE_ENV \ + "jh_mmcboot=" \ + "setenv fdt_file fsl-imx8qxp-mek-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run mmcboot; \0" \ + "jh_netboot=" \ + "setenv fdt_file fsl-imx8qxp-mek-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run netboot; \0" + +#define XEN_BOOT_ENV \ + "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true\0" \ + "xenlinux_bootargs= \0" \ + "xenlinux_console=hvc0 earlycon=xen\0" \ + "xenlinux_addr=0x92000000\0" \ + "dom0fdt_file=fsl-imx8qxp-mek-dom0.dtb\0" \ + "xenboot_common=" \ + "${get_cmd} ${loadaddr} xen;" \ + "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ + "${get_cmd} ${xenlinux_addr} ${image};" \ + "fdt addr ${fdt_addr};" \ + "fdt resize 256;" \ + "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ + "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ + "setenv bootargs ${xenhyper_bootargs};" \ + "booti ${loadaddr} - ${fdt_addr};" \ + "\0" \ + "xennetboot=" \ + "setenv get_cmd dhcp;" \ + "setenv console ${xenlinux_console};" \ + "run netargs;" \ + "run xenboot_common;" \ + "\0" \ + "xenmmcboot=" \ + "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ + "setenv console ${xenlinux_console};" \ + "run mmcargs;" \ + "run xenboot_common;" \ + "\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + XEN_BOOT_ENV \ + JAILHOUSE_ENV\ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "earlycon=lpuart32,0x5a060000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fdt=try\0" \ + "fdt_file=undefined\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + + +/* Default environment is in SD */ +#define CONFIG_ENV_SIZE 0x2000 +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#else +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board + */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 4 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +/* LPDDR4 board total DDR is 3GB */ +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#endif + +#define CONFIG_IMX_SMMU + +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ +#ifdef CONFIG_FSL_FSPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_FSPI_FLASH_SIZE SZ_64M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x5d120000 +#define FSPI0_AMBA_BASE 0 +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +#define CONFIG_SERIAL_TAG + +/* USB Config */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#define CONFIG_USB_EHCI_HCD +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +/* Framebuffer */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IMXDPUV1 +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +#define CONFIG_OF_SYSTEM_SETUP + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "imx8qxp_mek_android.h" +#elif defined (CONFIG_ANDROID_AUTO_SUPPORT) +#include "imx8qxp_mek_android_auto.h" +#endif + +#endif /* __IMX8QXP_MEK_H */ diff --git a/include/configs/imx8qxp_mek_android.h b/include/configs/imx8qxp_mek_android.h new file mode 100644 index 00000000000..dddcf454e98 --- /dev/null +++ b/include/configs/imx8qxp_mek_android.h @@ -0,0 +1,66 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QXP_MEK_ANDROID_H +#define IMX8QXP_MEK_ANDROID_H + +#define CONFIG_USBD_HS + +#define CONFIG_BCB_SUPPORT +#define CONFIG_CMD_READ +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (76 * SZ_1M) +#endif + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT + +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_FLASH + +#define CONFIG_FSL_FASTBOOT +#define CONFIG_FASTBOOT_USB_DEV 1 +#define CONFIG_ANDROID_RECOVERY + +#if defined CONFIG_SYS_BOOT_SATA +#define CONFIG_FASTBOOT_STORAGE_SATA +#define CONFIG_FASTBOOT_SATA_NO 0 +#else +#define CONFIG_FASTBOOT_STORAGE_MMC +#endif + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "panel=NULL\0" \ + +#define CONFIG_FASTBOOT_BUF_ADDR 0x98000000 +#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif /* IMX8QXP_MEK_ANDROID_H */ diff --git a/include/configs/imx8qxp_mek_android_auto.h b/include/configs/imx8qxp_mek_android_auto.h new file mode 100644 index 00000000000..1ebd7ff7d0e --- /dev/null +++ b/include/configs/imx8qxp_mek_android_auto.h @@ -0,0 +1,119 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QXP_MEK_ANDROID_AUTO_H +#define IMX8QXP_MEK_ANDROID_AUTO_H + +#define CONFIG_USBD_HS + +#define CONFIG_BCB_SUPPORT +#define CONFIG_CMD_READ +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NS_ARCH_ARM64 1 +#endif + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#ifndef CONFIG_MXC_USB_PORTSC +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x3FFF + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT + +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_FLASH + +#define CONFIG_SKIP_RESOURCE_CHECING +#define CONFIG_FSL_FASTBOOT +#define CONFIG_FASTBOOT_USB_DEV 1 +#define CONFIG_ANDROID_RECOVERY + +#if defined CONFIG_SYS_BOOT_SATA +#define CONFIG_FASTBOOT_STORAGE_SATA +#define CONFIG_FASTBOOT_SATA_NO 0 +#else +#define CONFIG_FASTBOOT_STORAGE_MMC +#endif + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +#define CONFIG_FASTBOOT_BUF_ADDR 0x98000000 +#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 + +/* Undefine some macros to save boot time */ +#undef CONFIG_ARCH_MISC_INIT +#undef CONFIG_FSL_HSIO +#undef CONFIG_CMD_PCI +#undef CONFIG_PCI +#undef CONFIG_PCIE_IMX8X +#undef CONFIG_PCI_PNP +#undef CONFIG_PCI_SCAN_SHOW +#undef CONFIG_CMD_FUSE +#undef CONFIG_MII +#undef CONFIG_FEC_MXC +#undef CONFIG_PHYLIB +#undef CONFIG_PHY_ATHEROS +#undef CONFIG_SYS_LONGHELP +#undef CONFIG_HUSH_PARSER +#undef CONFIG_AUTO_COMPLETE +#undef CONFIG_USB_HOST_ETHER +#undef CONFIG_CMD_USB_MASS_STORAGE +#undef CONFIG_USB_FUNCTION_MASS_STORAGE +#undef CONFIG_FAT_WRITE + +#ifdef CONFIG_IMX_TRUSTY_OS +#define AVB_RPMB +#ifdef CONFIG_DUAL_BOOTLOADER +#define BOOTLOADER_RBIDX_OFFSET 0x3FE000 +#define BOOTLOADER_RBIDX_START 0x3FF000 +#define BOOTLOADER_RBIDX_LEN 0x08 +#define BOOTLOADER_RBIDX_INITVAL 0 +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x801F8000 +#endif +#endif + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_BLK +#define CONFIG_FSL_CAAM_KB +#define CONFIG_SPL_CRYPTO_SUPPORT +#define CONFIG_SYS_FSL_SEC_LE +#endif + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif /* IMX8QXP_MEK_ANDROID_AUTO_H */ diff --git a/include/configs/imx_env.h b/include/configs/imx_env.h new file mode 100644 index 00000000000..9b731382187 --- /dev/null +++ b/include/configs/imx_env.h @@ -0,0 +1,34 @@ +/* Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_COMMON_CONFIG_H +#define __IMX_COMMON_CONFIG_H + +#ifdef CONFIG_ARM64 + #define MFG_BOOT_CMD "booti " +#else + #define MFG_BOOT_CMD "bootz " +#endif + +#define CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "clk_ignore_unused "\ + "\0" \ + "kboot="MFG_BOOT_CMD"\0"\ + "bootcmd_mfg=run mfgtool_args;" \ + "if iminfo ${initrd_addr}; then " \ + "if test ${tee} = yes; then " \ + "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \ + "else " \ + MFG_BOOT_CMD "${loadaddr} ${initrd_addr} ${fdt_addr}; " \ + "fi; " \ + "else " \ + "echo \"Run fastboot ...\"; fastboot 0; " \ + "fi;\0" \ + +#endif + +#define CONFIG_FAT_WRITE diff --git a/include/configs/multa-imx7d.h b/include/configs/multa-imx7d.h new file mode 100644 index 00000000000..65f0b3e82b3 --- /dev/null +++ b/include/configs/multa-imx7d.h @@ -0,0 +1,345 @@ +/* + * Copyright 2017 NXP + * + * Configuration settings for the Freescale i.MX7D MULTA board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MULTA_IMX7D__CONFIG_H +#define __MULTA_IMX7D__CONFIG_H + +#include "mx7_common.h" + +#define PHYS_SDRAM_SIZE SZ_512M + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* Network */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + +#define CONFIG_FEC_ENET_DEV 1 +#define CONFIG_FEC_MXC_PHYADDR 0x0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR +#endif + +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_IPS_BASE_ADDR + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_AXP152_POWER + +/* I2C configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_SPD_BUS_NUM 3 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_IMX_BOOTAUX +/* Set to QSPI1 A flash at default */ +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60100000 /* Set to QSPI1 A flash, offset 1M */ +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x7F8000 /* Set to TCML address */ +#endif + +#ifdef CONFIG_FSL_QSPI +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 0:0; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x100000 ${fw_sz}; " \ + "sf write ${loadaddr} 0x100000 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)" ${m4image}\0" \ + "m4boot=run loadm4image; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#endif +#else +#define UPDATE_M4_ENV "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=image raw 0 0x800000;"\ + "u-boot raw 0 0x4000;"\ + "bootimg part 0 1;"\ + "rootfs part 0 2\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + UPDATE_M4_ENV \ + CONFIG_MFG_ENV_SETTINGS \ + CONFIG_DFU_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx7d-sdb.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "panel=TFT43AB\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_256M) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_ENV_SIZE SZ_8K + +/* + * If want to use nand, define CONFIG_NAND_MXS and rework board + * to support nand, since emmc has pin conflicts with nand + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_QSPI_BASE QSPI1_IPS_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI0_ARB_BASE_ADDR +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (12 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +/* USB Configs */ +#define CONFIG_USB_EHCI_HCD +#define CONFIG_USB_EHCI_MX7 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_IMX_THERMAL + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* #define CONFIG_SPLASH_SCREEN*/ +/* #define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ +#define CONFIG_CMD_BMP +#define CONFIG_LCD +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_FSL_QSPI) +#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!" +#endif + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "multa-imx7d_androidthings.h" +#endif + +#define PRODUCT_NAME "imx7d" +#define VARIANT_NAME "imx7d_multa" + +#endif /* __CONFIG_H */ diff --git a/include/configs/multa-imx7d_androidthings.h b/include/configs/multa-imx7d_androidthings.h new file mode 100644 index 00000000000..23d05fca2cd --- /dev/null +++ b/include/configs/multa-imx7d_androidthings.h @@ -0,0 +1,66 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MULTA_IMX7D_ANDROIDTHINGS_H +#define __MULTA_IMX7D_ANDROIDTHINGS_H +#define TRUSTY_OS_ENTRY 0x9e000000 +#define TRUSTY_OS_RAM_SIZE 0x2000000 +#define TEE_HWPARTITION_ID 2 +#define TRUSTY_OS_MMC_BLKS 0xFFF + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NON_SECURE_FASTBOOT +#define TRUSTY_KEYSLOT_PACKAGE +#endif +#include "mx_android_common.h" + +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define FASTBOOT_ENCRYPT_LOCK + +#define CONFIG_SHA1 +#define CONFIG_SHA256 + + +#ifdef CONFIG_SYS_MMC_ENV_DEV +#undef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#endif + +#ifdef CONFIG_SYS_MMC_ENV_PART +#undef CONFIG_SYS_MMC_ENV_PART +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */ +#endif + +#define CONFIG_SYSTEM_RAMDISK_SUPPORT + + + +#define CONFIG_AVB_SUPPORT +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif +/* fuse bank size in word */ +/* infact 7D have no enough bits + * set this size to 0 will disable + * program/read FUSE */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#endif + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index bc58ca5c62d..79d4c9b2ce3 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -65,6 +65,7 @@ /* FEC Ethernet on SoC */ #ifdef CONFIG_CMD_NET #define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE #define CONFIG_MX28_FEC_MAC_IN_OCOTP #endif diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 2dc10c6d646..866d158c4a2 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -1,5 +1,7 @@ /* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0 */ @@ -43,7 +45,7 @@ #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6SX) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) -#define CONFIG_LOADADDR 0x82000000 +#define CONFIG_LOADADDR 0x80800000 #else #define CONFIG_LOADADDR 0x12000000 #endif @@ -52,27 +54,39 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 /* Filesystems and image support */ +#define CONFIG_SUPPORT_RAW_INITRD /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#ifndef CONFIG_SYS_DCACHE_OFF +#endif /* MMC */ #define CONFIG_BOUNCE_BUFFER #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC +#define CONFIG_SUPPORT_EMMC_BOOT /* Fuses */ #define CONFIG_MXC_OCOTP /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE 0x2000 +#define CONFIG_CSF_SIZE 0x4000 #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #endif #endif +#ifdef CONFIG_IMX_OPTEE +#define TEE_ENV "tee=yes\0" +#else +#define TEE_ENV "tee=no\0" +#endif #endif diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 610d643712b..a8be4c49d0a 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -11,6 +11,8 @@ #include "mx6_common.h" +#define CONFIG_IMX_THERMAL + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) @@ -27,19 +29,23 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc3\0" \ - "fdt_file=imx6q-arm2.dtb\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x18000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=1\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ @@ -108,7 +114,13 @@ #define CONFIG_SYS_MEMTEST_END 0x10010000 /* Physical Memory Map */ +#if defined(CONFIG_MX6DQ_POP_LPDDR2) +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_0 MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_1 MMDC1_ARB_BASE_ADDR +#else #define CONFIG_NR_DRAM_BANKS 1 +#endif #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM @@ -121,9 +133,11 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Environment organization */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_OFFSET (14 * 64 * 1024) #define CONFIG_ENV_SIZE (8 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ +#define CONFIG_MMCROOT "/dev/mmcblk3p2" /* SDHC4 */ /* USB Configs */ #ifdef CONFIG_CMD_USB @@ -133,4 +147,8 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif -#endif /* __CONFIG_H */ +#if defined(CONFIG_FASTBOOT) +#include "mx6qarm2_android.h" +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx6qarm2_android.h b/include/configs/mx6qarm2_android.h new file mode 100644 index 00000000000..7bc25262362 --- /dev/null +++ b/include/configs/mx6qarm2_android.h @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX6Q_ARM2_ANDROID_H +#define IMX6Q_ARM2_ANDROID_H + +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_USB_GADGET_VENDOR_NUM 0x18d1 +#define CONFIG_USB_GADGET_PRODUCT_NUM 0x0d02 +#define CONFIG_USB_GADGET_MANUFACTURER "FSL" + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_CMD_READ +#define CONFIG_BCB_SUPPORT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_FLASH + +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#endif + +#define FSL_FASTBOOT_FB_DEV "mmc" +#define FSL_FASTBOOT_DATA_PART_NUM 4 +#define FSL_FASTBOOT_FB_PART_NUM 11 +#define FSL_FASTBOOT_PR_DATA_PART_NUM 12 + +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_FSL_FASTBOOT +#define CONFIG_ANDROID_RECOVERY + +#if defined CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_STORAGE_NAND +#elif defined CONFIG_SYS_BOOT_SATA +#define CONFIG_FASTBOOT_STORAGE_SATA +#else +#define CONFIG_FASTBOOT_STORAGE_MMC +#endif + +#if defined(CONFIG_FASTBOOT_STORAGE_NAND) +#define ANDROID_FASTBOOT_NAND_PARTS "16m@64m(boot) 16m@80m(recovery) 810m@96m(android_root)ubifs" +#endif + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 + +#endif /* IMX6Q_ARM2_ANDROID_H */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index d976e77aef7..40014ed6a5e 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Configuration settings for the Freescale i.MX6Q SabreSD board. * @@ -10,11 +11,12 @@ #define __MX6QSABRE_COMMON_CONFIG_H #include "mx6_common.h" +#include "imx_env.h" #define CONFIG_IMX_THERMAL /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) #define CONFIG_MXC_UART @@ -25,18 +27,45 @@ #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RGMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else #define CONFIG_ETHPRIME "FEC" +#endif #define CONFIG_FEC_MXC_PHYADDR 1 +#define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS -#ifdef CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 20000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#ifdef CONFIG_MX6S +#define SYS_NOSMP "nosmp" +#else +#define SYS_NOSMP #endif +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=8000000.nor:1m(boot),-(rootfs)\\;gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x12C00000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + "weim_uboot=0x08001000\0"\ + "weim_base=0x08000000\0"\ + "spi_bus=1\0"\ + "spi_uboot=0x400\0" \ + "mtdparts=" MFG_NAND_PARTITION \ + "\0"\ + #ifdef CONFIG_SUPPORT_EMMC_BOOT #define EMMC_ENV \ "emmcdev=2\0" \ @@ -59,11 +88,107 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#if defined(CONFIG_NAND_BOOT) + /* + * The dts also enables the WEIN NOR which is mtd0. + * So the partions' layout for NAND is: + * mtd1: 16M (uboot) + * mtd2: 16M (kernel) + * mtd3: 16M (dtb) + * mtd4: left (rootfs) + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=" CONSOLE_DEV "\0" \ + "bootargs=console=" CONSOLE_DEV ",115200 ubi.mtd=6 " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "if test ${tee} = yes; then " \ + "nand read ${tee_addr} 0x4000000 0x400000;"\ + "bootm ${teeaddr} - ${fdt_addr};" \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr};" \ + "fi\0" + +#elif defined(CONFIG_SATA_BOOT) + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "image=zImage\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "tee_addr=0x20000000\0" \ + "tee_file=undefined\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ + "setenv fdt_file imx6qp-sabreauto.dtb; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ + "setenv fdt_file imx6q-sabreauto.dtb; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ + "setenv fdt_file imx6dl-sabreauto.dtb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ + "setenv fdt_file imx6qp-sabresd.dtb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ + "setenv fdt_file imx6q-sabresd.dtb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ + "setenv fdt_file imx6dl-sabresd.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; " \ + "fi; " \ + "fi;\0" \ + "findtee="\ + "if test $tee_file = undefined; then " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ + "setenv tee_file uTee-6qpauto; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ + "setenv tee_file uTee-6qauto; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ + "setenv tee_file uTee-6dlauto; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ + "setenv tee_file uTee-6qpsdb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ + "setenv tee_file uTee-6qsdb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ + "setenv tee_file uTee-6dlsdb; fi; " \ + "if test $tee_file = undefined; then " \ + "echo WARNING: Could not determine tee to use; fi; " \ + "fi;\0" \ + "bootargs=console=" CONSOLE_DEV ",115200 \0"\ + "bootargs_sata=setenv bootargs ${bootargs} " \ + "root=/dev/sda2 rootwait rw \0" \ + "bootcmd_sata=run bootargs_sata; sata init; " \ + "run findfdt; run findtee;" \ + "fatload sata 0:1 ${loadaddr} ${image}; " \ + "fatload sata 0:1 ${fdt_addr} ${fdt_file}; " \ + "if test ${tee} = yes; then " \ + "fatload sata 0:1 ${tee_addr} ${tee_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "fi \0"\ + "bootcmd=run bootcmd_sata \0" + +#else + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "epdc_waveform=epdc_splash.bin\0" \ "script=boot.scr\0" \ "image=zImage\0" \ "fdt_file=undefined\0" \ "fdt_addr=0x18000000\0" \ + "tee_addr=0x20000000\0" \ + "tee_file=undefined\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "console=" CONSOLE_DEV "\0" \ @@ -76,6 +201,8 @@ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "update_sd_firmware=" \ "if test ${ip_dyn} = yes; then " \ "setenv get_cmd dhcp; " \ @@ -90,31 +217,36 @@ "fi; " \ "fi\0" \ EMMC_ENV \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ + "smp=" SYS_NOSMP "\0"\ + "mmcargs=setenv bootargs console=${console},${baudrate} ${smp} " \ + "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ + "else " \ + "bootz; " \ + "fi;" \ "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ + "netargs=setenv bootargs console=${console},${baudrate} ${smp} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ @@ -125,18 +257,24 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "findfdt="\ "if test $fdt_file = undefined; then " \ @@ -153,11 +291,30 @@ "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ "setenv fdt_file imx6dl-sabresd.dtb; fi; " \ "if test $fdt_file = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; " \ + "echo WARNING: Could not determine dtb to use; " \ + "fi; " \ + "fi;\0" \ + "findtee="\ + "if test $tee_file = undefined; then " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ + "setenv tee_file uTee-6qpauto; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ + "setenv tee_file uTee-6qauto; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ + "setenv tee_file uTee-6dlauto; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ + "setenv tee_file uTee-6qpsdb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ + "setenv tee_file uTee-6qsdb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ + "setenv tee_file uTee-6dlsdb; fi; " \ + "if test $tee_file = undefined; then " \ + "echo WARNING: Could not determine tee to use; fi; " \ "fi;\0" \ #define CONFIG_BOOTCOMMAND \ "run findfdt;" \ + "run findtee;" \ "mmc dev ${mmcdev};" \ "if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -169,6 +326,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" +#endif #define CONFIG_ARP_TIMEOUT 200UL @@ -192,8 +350,96 @@ /* Environment organization */ #define CONFIG_ENV_SIZE (8 * 1024) +#ifdef CONFIG_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#endif + +#ifdef CONFIG_CMD_NAND +/* NAND flash command */ +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + #if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_OFFSET (896 * 1024) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_FLASH) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_FLASH_SECT_SIZE) +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#elif defined(CONFIG_ENV_IS_IN_SATA) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_SYS_SATA_ENV_DEV 0 +#define CONFIG_SYS_DCACHE_OFF /* remove when sata driver support cache */ +#endif + +/* I2C Configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* Framebuffer */ @@ -207,6 +453,10 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mx6sabreandroid_common.h" +#else #define CONFIG_USBD_HS +#endif /* CONFIG_ANDROID_SUPPORT */ #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx6sabreandroid_common.h b/include/configs/mx6sabreandroid_common.h new file mode 100644 index 00000000000..a45d0fe0b4a --- /dev/null +++ b/include/configs/mx6sabreandroid_common.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef MX6_SABRE_ANDROID_COMMON_H +#define MX6_SABRE_ANDROID_COMMON_H +#include "mx_android_common.h" + +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" +#define FASTBOOT_ENCRYPT_LOCK +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_AVB_SUPPORT +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_ANDROID_RECOVERY + +#ifdef CONFIG_SYS_CBSIZE +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 2048 +#endif + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +#endif /* CONFIG_AVB_SUPPORT */ + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif /* MX6_SABRE_ANDROID_COMMON_H */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index bba15a79432..4f82008e6ec 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Configuration settings for the Freescale i.MX6Q SabreAuto board. * @@ -16,17 +17,38 @@ #define CONFIG_MACH_TYPE 3529 #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */ +#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) +#ifdef CONFIG_MX6S +#undef PHYS_SDRAM_SIZE +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#endif + +#include "mx6sabre_common.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ +#ifdef CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_CS 1 +#endif + +/*Since the pin conflicts on EIM D18, disable the USB host if the NOR flash is enabled */ +#ifdef CONFIG_USB /* USB Configs */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 +#if !defined(CONFIG_DM_PCA953X) && defined(CONFIG_SYS_I2C) #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } - -#include "mx6sabre_common.h" +#endif +#endif /* Falcon Mode */ #ifdef CONFIG_SPL_OS_BOOT @@ -40,43 +62,4 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ #endif -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR -#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#endif - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - #endif /* __MX6SABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 8c06512dc72..eabb6da7291 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * Configuration settings for the Freescale i.MX6Q SabreSD board. * @@ -16,8 +17,15 @@ #define CONFIG_MACH_TYPE 3980 #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */ -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#if defined(CONFIG_MX6Q) +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#elif defined(CONFIG_MX6DL) +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#elif defined(CONFIG_MX6S) +#define PHYS_SDRAM_SIZE (512u * 1024 * 1024) +#endif #include "mx6sabre_common.h" @@ -34,8 +42,26 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ +#ifndef CONFIG_SYS_MMC_ENV_PART +#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ +#endif +#endif + +#ifdef CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_CS 0 #endif +/* + * imx6 q/dl/solo pcie would be failed to work properly in kernel, if + * the pcie module is iniialized/enumerated both in uboot and linux + * kernel. + * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism. + * it is only be RESET by the POR. So, the pcie module only be + * initialized/enumerated once in one POR. + * Set to use pcie in kernel defaultly, mask the pcie config here. + * Remove the mask freely, if the uboot pcie functions, rather than + * the kernel's, are required. + */ #ifdef CONFIG_CMD_PCI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCIE_IMX @@ -43,26 +69,33 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - /* USB Configs */ #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif +/*#define CONFIG_SPLASH_SCREEN*/ +/*#define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC) + /* + * Framebuffer and LCD + */ + #define CONFIG_CMD_BMP + #undef LCD_TEST_PATTERN + /* #define CONFIG_SPLASH_IS_IN_MMC 1 */ + #define LCD_BPP LCD_MONOCHROME + /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + + #define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */ + #endif /* __MX6SABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index aa2952084aa..e8435491734 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -10,6 +10,7 @@ #define __CONFIG_H #include "mx6_common.h" +#include "imx_env.h" #ifdef CONFIG_SPL #include "imx6_spl.h" @@ -18,7 +19,7 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MX6SL_EVK /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR @@ -27,56 +28,97 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR /* I2C Configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif #define CONFIG_FEC_MXC #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC" +#endif #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_PHY_SMSC +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + "spi_bus=1\0"\ + "spi_uboot=0x400\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "epdc_waveform=epdc_splash.bin\0" \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sl-evk.dtb\0" \ - "fdt_addr=0x88000000\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=uTee-6slevk\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=1\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "finduuid=part uuid mmc 1:2 uuid\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ + "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -89,21 +131,32 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" + "else " \ + "bootz; " \ + "fi;" \ + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "setenv fdt_file imx6sl-evk.dtb; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -137,14 +190,14 @@ #define CONFIG_ENV_SIZE SZ_8K #if defined CONFIG_SPI_BOOT -#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_OFFSET (896 * 1024) #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #else -#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) #endif #ifdef CONFIG_CMD_SF @@ -162,11 +215,31 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_FSL_USDHC_NUM 3 -#if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/ -#endif #define CONFIG_IMX_THERMAL +/*#define CONFIG_SPLASH_SCREEN*/ + +/* + * SPLASH SCREEN Configs + */ +#ifdef CONFIG_MXC_EPDC + /* + * Framebuffer and LCD + */ + #define CONFIG_CMD_BMP + #define CONFIG_SPLASH_SCREEN + #undef LCD_TEST_PATTERN + #define LCD_BPP LCD_MONOCHROME + + #define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif /* CONFIG_SPLASH_SCREEN */ + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mx6slevkandroid.h" +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/mx6slevkandroid.h b/include/configs/mx6slevkandroid.h new file mode 100644 index 00000000000..9895211b24c --- /dev/null +++ b/include/configs/mx6slevkandroid.h @@ -0,0 +1,54 @@ + +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef MX6SL_EVK_ANDROID_H +#define MX6SL_EVK_ANDROID_H +#include "mx_android_common.h" + +#include + +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +/* lock/unlock stuff */ +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +/*keyboard mapping*/ +#define CONFIG_VOL_DOWN_KEY KEY_BACK +#define CONFIG_POWER_KEY KEY_5 + +#define CONFIG_MXC_KPD +#define CONFIG_MXC_KEYMAPPING \ + { \ + KEY_SELECT, KEY_BACK, KEY_1, KEY_2, \ + KEY_3, KEY_4, KEY_5, KEY_MENU, \ + KEY_6, KEY_7, KEY_8, KEY_9, \ + KEY_UP, KEY_LEFT, KEY_RIGHT, KEY_DOWN, \ + } +#define CONFIG_MXC_KPD_COLMAX 4 +#define CONFIG_MXC_KPD_ROWMAX 4 + +#define CONFIG_AVB_SUPPORT +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_ANDROID_RECOVERY + +#ifdef CONFIG_SYS_CBSIZE +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 2048 +#endif + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +#endif /* CONFIG_AVB_SUPPORT */ + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif diff --git a/include/configs/mx6sll_arm2.h b/include/configs/mx6sll_arm2.h new file mode 100644 index 00000000000..8bc7ae42ecc --- /dev/null +++ b/include/configs/mx6sll_arm2.h @@ -0,0 +1,220 @@ +/* + * Copyright 2013-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SL EVK board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ + +/* I2C Configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "\0" \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "epdc_waveform=epdc_splash.bin\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "usb start; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#ifdef CONFIG_LPDDR2_BOARD +#define PHYS_SDRAM_SIZE SZ_1G +#else +#define PHYS_SDRAM_SIZE SZ_2G +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#define CONFIG_IMX_THERMAL + +#define CONFIG_IOMUX_LPSR + +#ifdef CONFIG_CMD_SF +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + + +/*#define CONFIG_MXC_EPDC 1*/ + +/* + * EPDC SPLASH SCREEN Configs + */ +#ifdef CONFIG_MXC_EPDC + /* + * Framebuffer and LCD + */ + #define CONFIG_SPLASH_SCREEN + #undef LCD_TEST_PATTERN + #define LCD_BPP LCD_MONOCHROME + + #define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif /* CONFIG_MXC_EPDC */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 0cf34c477bb..4df66f9b94c 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -10,6 +10,7 @@ #define __CONFIG_H #include "mx6_common.h" +#include "imx_env.h" #ifdef CONFIG_SECURE_BOOT #ifndef CONFIG_CSF_SIZE @@ -17,6 +18,10 @@ #endif #endif +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) @@ -32,15 +37,26 @@ #define CONFIG_SYS_I2C_SPEED 100000 #endif +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=1\0"\ + "sd_dev=0\0" \ + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ "epdc_waveform=epdc_splash.bin\0" \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sll-evk.dtb\0" \ + "fdt_file=undefined\0" \ "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=uTee-6sllevk\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ @@ -55,20 +71,25 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -82,21 +103,32 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" + "else " \ + "bootz; " \ + "fi;" \ + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "setenv fdt_file imx6sll-evk.dtb; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -132,7 +164,7 @@ #define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ -#define CONFIG_ENV_OFFSET (12 * SZ_64K) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR @@ -148,4 +180,31 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* + * EPDC SPLASH SCREEN Configs + */ +#ifdef CONFIG_MXC_EPDC + /* + * Framebuffer and LCD + */ + #define CONFIG_SPLASH_SCREEN + #define CONFIG_CMD_BMP + #undef LCD_TEST_PATTERN + #define LCD_BPP LCD_MONOCHROME + + #define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif /* CONFIG_MXC_EPDC */ + #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sx_17x17_arm2.h b/include/configs/mx6sx_17x17_arm2.h new file mode 100644 index 00000000000..f2a9b27b9a5 --- /dev/null +++ b/include/configs/mx6sx_17x17_arm2.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX 17x17 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_17X17_ARM2_CONFIG_H +#define __MX6SX_17X17_ARM2_CONFIG_H + +#include "mx6sx_arm2.h" + +#ifdef CONFIG_MXC_SPI /* Pin conflict between SPI-NOR and SD2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC3 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ +#else +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC3 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ +#endif + +#ifdef CONFIG_MXC_SPI +#undef CONFIG_SYS_FLASH_SECT_SIZE +#undef CONFIG_SYS_MAX_FLASH_SECT +#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024) +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_PROTECTION +#endif + +#endif diff --git a/include/configs/mx6sx_19x19_arm2.h b/include/configs/mx6sx_19x19_arm2.h new file mode 100644 index 00000000000..4abb2efe59b --- /dev/null +++ b/include/configs/mx6sx_19x19_arm2.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX 19x19 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_19X19_ARM2_CONFIG_H +#define __MX6SX_19X19_ARM2_CONFIG_H + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_GIS +#endif + +#include "mx6sx_arm2.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#endif diff --git a/include/configs/mx6sx_arm2.h b/include/configs/mx6sx_arm2.h new file mode 100644 index 00000000000..9c16748cd6d --- /dev/null +++ b/include/configs/mx6sx_arm2.h @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_ARM2_CONFIG_H +#define __MX6SX_ARM2_CONFIG_H + +#include "mx6_common.h" + +#define CONFIG_DBG_MONITOR + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_IMX_THERMAL + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC" +#endif +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* I2C configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif + +#ifdef CONFIG_IMX_BOOTAUX +#ifdef CONFIG_DM_SPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 /* Set to QSPI2 B flash at default */ +#define SF_QSPI2_B_CS_NUM 2 +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000 /* Set to QSPI2 B flash at default */ +#define SF_QSPI2_B_CS_NUM 1 +#endif + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 1:${m4_qspi_cs}; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "\0" \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=Hannstar-XGA\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + UPDATE_M4_ENV \ + "panel=Hannstar-XGA\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_1G + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_CMD_NAND +#elif defined CONFIG_SPI_BOOT +#define CONFIG_MXC_SPI +#elif defined CONFIG_NOR_BOOT +#define CONFIG_MTD_NOR_FLASH +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB +#define FSL_QSPI_FLASH_SIZE SZ_32M +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + + +#ifdef CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 3 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +#ifdef CONFIG_NOR_BOOT +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +#ifdef CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#elif defined(CONFIG_ENV_IS_IN_FLASH) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_FLASH_SECT_SIZE) +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_SYS_CONSOLE_BG_COL 0x00 +#define CONFIG_SYS_CONSOLE_FG_COL 0xa0 +#ifdef CONFIG_VIDEO_GIS +#define CONFIG_VIDEO_CSI +#define CONFIG_VIDEO_PXP +#define CONFIG_VIDEO_VADC +#endif +#endif + + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#ifndef CONFIG_DM_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_FLAGS 0 +/*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 06e416bb59d..d464f869680 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -10,26 +10,104 @@ #define __CONFIG_H #include "mx6_common.h" +#include "imx_env.h" + +#define CONFIG_DBG_MONITOR /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#ifdef CONFIG_IMX_BOOTAUX + +/* Set to QSPI1 B flash at default */ +#ifdef CONFIG_DM_SPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x68000000 +#define SF_QSPI1_B_CS_NUM 2 +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x62000000 +#define SF_QSPI1_B_CS_NUM 1 +#endif + + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "m4_qspi_cs="__stringify(SF_QSPI1_B_CS_NUM)"\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 0:${m4_qspi_cs}; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 0:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "sd_dev=0\0" \ + "mtdparts=" MFG_NAND_PARTITION \ + "\0"\ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "panel=Hannstar-XGA\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=6 " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "if test ${tee} = yes; then " \ + "nand read ${tee_addr} 0x6000000 0x400000;"\ + "bootm ${teeaddr} - ${fdt_addr};" \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr};" \ + "fi\0" + +#else #define CONFIG_EXTRA_ENV_SETTINGS \ + UPDATE_M4_ENV \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sx-sabreauto.dtb\0" \ - "fdt_addr=0x88000000\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=uTee-6sxauto\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=0\0" \ + "panel=Hannstar-XGA\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ @@ -38,20 +116,25 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -64,22 +147,32 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" + "else " \ + "bootz; " \ + "fi;" \ + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "setenv fdt_file imx6sx-sabreauto.dtb; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ + "run findfdt;" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ @@ -90,6 +183,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" +#endif /* Miscellaneous configurable options */ #define CONFIG_SYS_MEMTEST_START 0x80000000 @@ -131,13 +225,32 @@ #define CONFIG_FEC_MXC #define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 /* Use onboard ethernet as default */ + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC0" +#endif +#elif (CONFIG_FEC_ENET_DEV == 1) #define IMX_FEC_BASE ENET2_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth1" +#else +#define CONFIG_ETHPRIME "FEC1" +#endif +#endif #define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" #define CONFIG_PHY_ATHEROS +#define CONFIG_FEC_MXC_MDIO_BASE ENET_BASE_ADDR + +#define CONFIG_SERIAL_TAG #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -158,12 +271,56 @@ #define FSL_QSPI_FLASH_NUM 2 #endif -#define CONFIG_ENV_OFFSET (8 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_SYS_FSL_USDHC_NUM 2 -#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ #define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_GIS +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_SYS_CONSOLE_BG_COL 0x00 +#define CONFIG_SYS_CONSOLE_FG_COL 0xa0 +#ifdef CONFIG_VIDEO_GIS +#define CONFIG_VIDEO_CSI +#define CONFIG_VIDEO_PXP +#define CONFIG_VIDEO_VADC +#endif +#endif + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mx6sxsabreautoandroid.h" #endif #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabreautoandroid.h b/include/configs/mx6sxsabreautoandroid.h new file mode 100644 index 00000000000..b00730ee4b2 --- /dev/null +++ b/include/configs/mx6sxsabreautoandroid.h @@ -0,0 +1,40 @@ + +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_SABREAUTO_ANDROID_H +#define __MX6SX_SABREAUTO_ANDROID_H +#include "mx_android_common.h" + +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" +#define FASTBOOT_ENCRYPT_LOCK +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_AVB_SUPPORT +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_ANDROID_RECOVERY + +#ifdef CONFIG_SYS_CBSIZE +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 2048 +#endif + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +#endif /* CONFIG_AVB_SUPPORT */ + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 1eaaf013f7a..2806f47128b 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -1,5 +1,6 @@ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Configuration settings for the Freescale i.MX6SX Sabresd board. * @@ -10,26 +11,45 @@ #define __CONFIG_H #include "mx6_common.h" +#include "imx_env.h" + +#define CONFIG_DBG_MONITOR #ifdef CONFIG_SPL #include "imx6_spl.h" #endif /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + #ifdef CONFIG_IMX_BOOTAUX /* Set to QSPI2 B flash at default */ +#ifdef CONFIG_DM_SPI #define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 +#define SF_QSPI2_B_CS_NUM 2 +#elif defined(CONFIG_MX6SX_SABRESD_REVA) +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x71000000 +#define SF_QSPI2_B_CS_NUM 1 +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000 +#define SF_QSPI2_B_CS_NUM 1 +#endif +/* When using M4 fastup demo, no need these M4 env, since QSPI is used by M4 */ +#ifndef CONFIG_SYS_AUXCORE_FASTUP #define UPDATE_M4_ENV \ "m4image=m4_qspi.bin\0" \ + "m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \ "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ "update_m4_from_sd=" \ - "if sf probe 1:0; then " \ + "if sf probe 1:${m4_qspi_cs}; then " \ "if run loadm4image; then " \ "setexpr fw_sz ${filesize} + 0xffff; " \ "setexpr fw_sz ${fw_sz} / 0x10000; " \ @@ -38,50 +58,71 @@ "sf write ${loadaddr} 0x0 ${filesize}; " \ "fi; " \ "fi\0" \ - "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" + "m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" #else #define UPDATE_M4_ENV "" -#endif +#endif /* CONFIG_SYS_AUXCORE_FASTUP */ + +#else +#define UPDATE_M4_ENV "" +#endif /* CONFIG_IMX_BOOTAUX */ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ UPDATE_M4_ENV \ + TEE_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sx-sdb.dtb\0" \ - "fdt_addr=0x88000000\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=uTee-6sxsdb\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \ - "mmcdev=2\0" \ + "panel=Hannstar-XGA\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "finduuid=part uuid mmc 2:2 uuid\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ + "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -94,22 +135,29 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ + "else " \ + "bootz; " \ + "fi;" \ "fi;\0" \ "findfdt="\ - "if test test $board_rev = REVA ; then " \ - "setenv fdt_file imx6sx-sdb-reva.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "setenv fdt_file " CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ "run findfdt; " \ @@ -142,26 +190,57 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* MMC Configuration */ + #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR /* I2C Configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif /* Network */ #define CONFIG_FEC_MXC #define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC0" +#endif +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth1" +#else +#define CONFIG_ETHPRIME "FEC1" +#endif +#endif #define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" #define CONFIG_PHY_ATHEROS +#define CONFIG_FEC_MXC_MDIO_BASE ENET_BASE_ADDR #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -180,7 +259,6 @@ #define CONFIG_IMX_THERMAL #ifdef CONFIG_FSL_QSPI -#define CONFIG_SYS_FSL_QSPI_LE #define CONFIG_SYS_FSL_QSPI_AHB #ifdef CONFIG_MX6SX_SABRESD_REVA #define FSL_QSPI_FLASH_SIZE SZ_16M @@ -188,6 +266,10 @@ #define FSL_QSPI_FLASH_SIZE SZ_32M #endif #define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #endif #ifndef CONFIG_SPL_BUILD @@ -199,16 +281,31 @@ #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_VIDEO_BMP_LOGO -#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_SYS_CONSOLE_BG_COL 0x00 +#define CONFIG_SYS_CONSOLE_FG_COL 0xa0 #endif #endif -#define CONFIG_ENV_OFFSET (14 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif #define CONFIG_SYS_FSL_USDHC_NUM 3 -#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_MMCROOT "/dev/mmcblk3p2" /* USDHC4 */ #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mx6sxsabresdandroid.h" #endif #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresdandroid.h b/include/configs/mx6sxsabresdandroid.h new file mode 100644 index 00000000000..9e4a5bf7dca --- /dev/null +++ b/include/configs/mx6sxsabresdandroid.h @@ -0,0 +1,43 @@ + +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_SABRESD_ANDROID_H +#define __MX6SX_SABRESD_ANDROID_H +#include "mx_android_common.h" + +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" +#define FASTBOOT_ENCRYPT_LOCK +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 +#endif + +#define CONFIG_AVB_SUPPORT +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_ANDROID_RECOVERY + +#ifdef CONFIG_SYS_CBSIZE +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 2048 +#endif + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +#endif /* CONFIG_AVB_SUPPORT */ + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif diff --git a/include/configs/mx6ul_14x14_ddr3_arm2.h b/include/configs/mx6ul_14x14_ddr3_arm2.h new file mode 100644 index 00000000000..d8b0f56d1f0 --- /dev/null +++ b/include/configs/mx6ul_14x14_ddr3_arm2.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_14X14_DDR3_ARM2_CONFIG_H +#define __MX6UL_14X14_DDR3_ARM2_CONFIG_H + +#ifdef CONFIG_SPI_BOOT +#define CONFIG_MXC_SPI +#elif defined(CONFIG_NOR_BOOT) +#define CONFIG_MTD_NOR_FLASH +#elif defined CONFIG_NAND_BOOT +#define CONFIG_CMD_NAND +#endif + +#define BOOTARGS_CMA_SIZE "" + +#include "mx6ul_arm2.h" + +#define PHYS_SDRAM_SIZE SZ_1G + +#ifdef CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +#ifdef CONFIG_DM_ETH +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC0" +#endif +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE MII100 +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth1" +#else +#define CONFIG_ETHPRIME "FEC1" +#endif +#endif + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR +#endif + +#define CONFIG_MODULE_FUSE +#define CONFIG_OF_SYSTEM_SETUP +#endif diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 1c1671e30f9..7c4b659acf6 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. * @@ -12,9 +13,23 @@ #include #include "mx6_common.h" #include +#include "imx_env.h" + +/* uncomment for BEE support, needs to enable CONFIG_CMD_FUSE */ +/* #define CONFIG_CMD_BEE */ #define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) +#ifdef CONFIG_TARGET_MX6UL_9X9_EVK +#define PHYS_SDRAM_SIZE SZ_256M +#define BOOTARGS_CMA_SIZE "cma=96M " +#else +#define PHYS_SDRAM_SIZE SZ_512M +#define BOOTARGS_CMA_SIZE "" +/* DCDC used on 14x14 EVK, no PMIC */ +#undef CONFIG_LDO_BYPASS_CHECK +#endif + /* SPL options */ #include "imx6_spl.h" @@ -31,7 +46,7 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR /* NAND pin conflicts with usdhc2 */ -#ifdef CONFIG_NAND_MXS +#ifdef CONFIG_CMD_NAND #define CONFIG_SYS_FSL_USDHC_NUM 1 #else #define CONFIG_SYS_FSL_USDHC_NUM 2 @@ -41,11 +56,15 @@ /* I2C configs */ #ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* Only use DM I2C driver for 14x14 EVK. Because the PFUZE3000 driver does not support DM */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C /* PMIC only for 9X9 EVK */ #define CONFIG_POWER @@ -56,7 +75,50 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),16m(tee),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=1\0"\ + "emmc_ack=1\0"\ + "sd_dev=1\0" \ + +#if defined(CONFIG_NAND_BOOT) #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + BOOTARGS_CMA_SIZE \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "if test ${tee} = yes; then " \ + "nand read ${tee_addr} 0x6000000 0x400000;"\ + "bootm ${teeaddr} - ${fdt_addr};" \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr};" \ + "fi\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ @@ -64,14 +126,17 @@ "initrd_high=0xffffffff\0" \ "fdt_file=undefined\0" \ "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=undefined\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + "panel=TFT43AB\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ @@ -79,22 +144,28 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ @@ -105,19 +176,34 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ + "findtee="\ + "if test $tee_file = undefined; then " \ + "if test $board_name = EVK && test $board_rev = 9X9; then " \ + "setenv tee_file uTee-6ul9x9; fi; " \ + "if test $board_name = EVK && test $board_rev = 14X14; then " \ + "setenv tee_file uTee-6ulevk; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine tee to use; fi; " \ + "fi;\0" \ "findfdt="\ "if test $fdt_file = undefined; then " \ "if test $board_name = EVK && test $board_rev = 9X9; then " \ @@ -125,11 +211,13 @@ "if test $board_name = EVK && test $board_rev = 14X14; then " \ "setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \ "if test $fdt_file = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; " \ + "echo WARNING: Could not determine dtb to use; " \ + "fi; " \ "fi;\0" \ #define CONFIG_BOOTCOMMAND \ "run findfdt;" \ + "run findtee;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -141,6 +229,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" +#endif /* Miscellaneous configurable options */ #define CONFIG_SYS_MEMTEST_START 0x80000000 @@ -161,18 +250,15 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (8 * SZ_64K) #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#ifndef CONFIG_SYS_DCACHE_OFF -#endif + +#define CONFIG_SOFT_SPI #ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 @@ -181,6 +267,39 @@ #define FSL_QSPI_FLASH_SIZE SZ_32M #endif +/* NAND stuff */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#define CONFIG_ENV_SIZE SZ_8K +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + /* USB Configs */ #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -190,6 +309,7 @@ #endif #ifdef CONFIG_CMD_NET +#define CONFIG_CMD_MII #define CONFIG_FEC_MXC #define CONFIG_MII #define CONFIG_FEC_ENET_DEV 1 @@ -198,12 +318,22 @@ #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x2 #define CONFIG_FEC_XCV_TYPE RMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC0" +#endif #elif (CONFIG_FEC_ENET_DEV == 1) #define IMX_FEC_BASE ENET2_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 #define CONFIG_FEC_XCV_TYPE RMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth1" +#else +#define CONFIG_ETHPRIME "FEC1" +#endif #endif -#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR #endif #define CONFIG_IMX_THERMAL @@ -217,8 +347,18 @@ #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_VIDEO_BMP_LOGO -#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR +#define CONFIG_IMX_VIDEO_SKIP +#endif #endif + +#define CONFIG_MODULE_FUSE +#define CONFIG_OF_SYSTEM_SETUP + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mx6ul_14x14_evk_android.h" #endif +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "mx6ul_14x14_evkandroidthings.h" +#endif #endif diff --git a/include/configs/mx6ul_14x14_evk_android.h b/include/configs/mx6ul_14x14_evk_android.h new file mode 100644 index 00000000000..26a7ac5d653 --- /dev/null +++ b/include/configs/mx6ul_14x14_evk_android.h @@ -0,0 +1,16 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6UL_EVK_ANDROID_H +#define __MX6UL_EVK_ANDROID_H +#include "mx_android_common.h" + +#if defined(CONFIG_FASTBOOT_STORAGE_NAND) +#define ANDROID_FASTBOOT_NAND_PARTS "16m@64m(boot) 16m@80m(recovery) 810m@96m(android_root)ubifs" +#endif + +#endif diff --git a/include/configs/mx6ul_14x14_evkandroidthings.h b/include/configs/mx6ul_14x14_evkandroidthings.h new file mode 100644 index 00000000000..84c67efa9ef --- /dev/null +++ b/include/configs/mx6ul_14x14_evkandroidthings.h @@ -0,0 +1,38 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6UL_14x14_EVKANDROIDTHINGS_H +#define __MX6UL_14x14_EVKANDROIDTHINGS_H +#include "mx_android_common.h" +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define FASTBOOT_ENCRYPT_LOCK +#ifdef CONFIG_AVB_SUPPORT + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_PARTITION_UUIDS +/* fuse bank size in word */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 8 +#define CONFIG_AVB_FUSE_BANK_START 10 +#define CONFIG_AVB_FUSE_BANK_END 15 +#endif + +#endif diff --git a/include/configs/mx6ul_14x14_lpddr2_arm2.h b/include/configs/mx6ul_14x14_lpddr2_arm2.h new file mode 100644 index 00000000000..b3154b26f73 --- /dev/null +++ b/include/configs/mx6ul_14x14_lpddr2_arm2.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 LPDDR2 ARM2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_14X14_LPDDR2_ARM2_CONFIG_H +#define __MX6UL_14X14_LPDDR2_ARM2_CONFIG_H + +#ifdef CONFIG_SPI_BOOT +#define CONFIG_MXC_SPI +#elif defined(CONFIG_NOR_BOOT) +#define CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_PROTECTION +#elif defined CONFIG_NAND_BOOT +#define CONFIG_CMD_NAND +#endif +#ifdef CONFIG_MTD_NOR_FLASH +/* + * Conflicts with SD1/SD2/VIDEO/ENET + * ENET is keeped, since only RXER conflicts. + * If removed ENET, we can not boot kernel, since sd1/sd2 is disabled + * when support weimnor. + */ +#undef CONFIG_FSL_USDHC +#undef CONFIG_VIDEO +#endif + +#define BOOTARGS_CMA_SIZE "cma=96M " + +#include "mx6ul_arm2.h" + +#define PHYS_SDRAM_SIZE SZ_256M + +#ifdef CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +#ifdef CONFIG_DM_ETH +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 /* The ENET1 has pin conflict with UART1 */ + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE MII100 +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC0" +#endif +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth1" +#else +#define CONFIG_ETHPRIME "FEC1" +#endif +#endif + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR +#endif + +#endif diff --git a/include/configs/mx6ul_arm2.h b/include/configs/mx6ul_arm2.h new file mode 100644 index 00000000000..150aaf9cb8f --- /dev/null +++ b/include/configs/mx6ul_arm2.h @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL ARM2 common. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_ARM2_CONFIG_H +#define __MX6UL_ARM2_CONFIG_H + + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* I2C configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=MCIMX28LCD\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + BOOTARGS_CMA_SIZE \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=MCIMX28LCD\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_32M +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_FLASH) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_FLASH_SECT_SIZE) +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#endif diff --git a/include/configs/mx6ul_nxpu_iopb.h b/include/configs/mx6ul_nxpu_iopb.h new file mode 100644 index 00000000000..a4ff655e17c --- /dev/null +++ b/include/configs/mx6ul_nxpu_iopb.h @@ -0,0 +1,283 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL NXPU IOPB board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_NXPU_IOPB_CONFIG_H +#define __MX6UL_NXPU_IOPB_CONFIG_H + +#include "mx6_common.h" + +#if !defined(CONFIG_MX6UL_9X9_LPDDR2) +/* DCDC used on 14x14 EVK, no PMIC */ +#undef CONFIG_LDO_BYPASS_CHECK +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART3_BASE + +/* MMC Configs */ +#define CONFIG_FSL_USDHC +#ifdef CONFIG_FSL_USDHC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 0 +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_PHYLIB +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 + +/* I2C configs */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define PHYS_SDRAM_SIZE SZ_512M + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + + + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=3 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc2\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_QSPI_BASE QSPI1_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI1_ARB_BASE_ADDR + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (13 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_MODULE_FUSE +#define CONFIG_OF_SYSTEM_SETUP + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "mx6ul_nxpu_iopb_android_things.h" +#endif + + +#define PRODUCT_NAME "imx6ul" +#define VARIANT_NAME "imx6ul_iopb" + +#endif diff --git a/include/configs/mx6ul_nxpu_iopb_android_things.h b/include/configs/mx6ul_nxpu_iopb_android_things.h new file mode 100644 index 00000000000..4cefd8e45a2 --- /dev/null +++ b/include/configs/mx6ul_nxpu_iopb_android_things.h @@ -0,0 +1,61 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6UL_NXPU_IOPB_ANDROID_THINGS_H +#define __MX6UL_NXPU_IOPB_ANDROID_THINGS_H +#include "mx_android_common.h" +#define TRUSTY_OS_ENTRY 0x9e000000 +#define TRUSTY_OS_RAM_SIZE 0x2000000 +#define TRUSTY_OS_MMC_BLKS 0xFFF +#define TEE_HWPARTITION_ID 2 + +#define AVB_RPMB +#ifdef AVB_RPMB +#define KEYSLOT_BLKS 0xFFF +#define KEYSLOT_HWPARTITION_ID 2 +#endif + +#ifdef CONFIG_AVB_ATX +#define PERMANENT_ATTRIBUTE_HASH_OFFSET 32 +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NON_SECURE_FASTBOOT +#define TRUSTY_KEYSLOT_PACKAGE +#endif + +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_AVB_SUPPORT +#ifdef CONFIG_AVB_SUPPORT +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif +#define CONFIG_SUPPORT_EMMC_RPMB +/* fuse bank size in word */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 8 +#define CONFIG_AVB_FUSE_BANK_START 10 +#define CONFIG_AVB_FUSE_BANK_END 15 +#endif + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif +/* __MX6UL_NXPU_IOPB_ANDROID_THINGS_H */ diff --git a/include/configs/mx6ul_spriot.h b/include/configs/mx6ul_spriot.h new file mode 100644 index 00000000000..03893254d9b --- /dev/null +++ b/include/configs/mx6ul_spriot.h @@ -0,0 +1,300 @@ +/* + * Copyright (C) 2017 Murata Electronics + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * Configuration settings for the Murata SPRIOT + i.MX6UL-BB board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_SPRIOT_CONFIG_H +#define __MX6UL_SPRIOT_CONFIG_H + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + + +/* MMC Configs */ +#define CONFIG_FSL_USDHC +#ifdef CONFIG_FSL_USDHC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#endif + +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_PARTITION_UUIDS +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE RMII +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 /* need board rework */ +#define CONFIG_FEC_XCV_TYPE RMII +#endif +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 + +/* I2C configs */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define PHYS_SDRAM_SIZE SZ_512M + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + +#undef CONFIG_CMD_IMLS + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=3 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" imx6ul-spriot.dtb "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_QSPI_BASE QSPI1_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI1_ARB_BASE_ADDR + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (13 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (37 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_MODULE_FUSE +#define CONFIG_OF_SYSTEM_SETUP + +#ifdef CONFIG_USB_FASTBOOT_BUF_SIZE +#undef CONFIG_USB_FASTBOOT_BUF_SIZE +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0xc800000 +#endif + +#define PRODUCT_NAME "imx6ul_spriot" +#define VARIANT_NAME "imx6ul_spriot" + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "mx6ul_spriot_android_things.h" +#endif + +#endif diff --git a/include/configs/mx6ul_spriot_android_things.h b/include/configs/mx6ul_spriot_android_things.h new file mode 100644 index 00000000000..278bda765c7 --- /dev/null +++ b/include/configs/mx6ul_spriot_android_things.h @@ -0,0 +1,54 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6UL_SPRIOT_ANDROID_THINGS_H +#define __MX6UL_SPRIOT_ANDROID_THINGS_H +#include "mx_android_common.h" + +#ifdef CONFIG_AVB_ATX +#define PERMANENT_ATTRIBUTE_HASH_OFFSET 32 +#endif + +#define AVB_RPMB +#ifdef AVB_RPMB +#define KEYSLOT_BLKS 0xFFF +#define KEYSLOT_HWPARTITION_ID 2 +#endif + +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_AVB_SUPPORT +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#ifdef CONFIG_AVB_SUPPORT + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#define CONFIG_SUPPORT_EMMC_RPMB +/* fuse bank size in word */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 8 +#define CONFIG_AVB_FUSE_BANK_START 10 +#define CONFIG_AVB_FUSE_BANK_END 15 +#endif + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif +/* __MX6UL_SPRIOT_ANDROID_THINGS_H */ diff --git a/include/configs/mx6ull_ddr3_arm2.h b/include/configs/mx6ull_ddr3_arm2.h new file mode 100644 index 00000000000..183e11b1c6e --- /dev/null +++ b/include/configs/mx6ull_ddr3_arm2.h @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6ULL_DDR3_ARM2_CONFIG_H +#define __MX6ULL_DDR3_ARM2_CONFIG_H + +#ifdef CONFIG_SPI_BOOT + +#define CONFIG_MXC_SPI +#elif defined CONFIG_NAND_BOOT +#define CONFIG_CMD_NAND +#endif + +#define BOOTARGS_CMA_SIZE "" + +#include "mx6ul_arm2.h" + +#define CONFIG_IOMUX_LPSR + +#define PHYS_SDRAM_SIZE SZ_1G + +/* + * TSC pins conflict with I2C1 bus, so after TSC + * hardware rework, need to disable i2c1 bus, also + * need to disable PMIC and ldo bypass check. + */ +#ifdef CONFIG_MX6ULL_DDR3_ARM2_TSC_REWORK +#undef CONFIG_LDO_BYPASS_CHECK +#undef CONFIG_SYS_I2C_MXC +#undef CONFIG_SYS_I2C +#undef CONFIG_CMD_I2C +#undef CONFIG_POWER_PFUZE100_I2C_ADDR +#undef CONFIG_POWER_PFUZE100 +#undef CONFIG_POWER_I2C +#undef CONFIG_POWER +#endif + +#ifdef CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +#ifdef CONFIG_DM_ETH +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC0" +#endif +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE MII100 +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth1" +#else +#define CONFIG_ETHPRIME "FEC1" +#endif +#endif + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR +#endif + + +/* #define CONFIG_SPLASH_SCREEN*/ +/* #define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ +#define CONFIG_SPLASH_SCREEN + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +#define CONFIG_MODULE_FUSE +#define CONFIG_OF_SYSTEM_SETUP + +#endif diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 21429134ba2..b4984a4cd22 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. * @@ -13,6 +14,7 @@ #include #include "mx6_common.h" #include +#include "imx_env.h" #ifdef CONFIG_SECURE_BOOT #ifndef CONFIG_CSF_SIZE @@ -20,7 +22,17 @@ #endif #endif -#define PHYS_SDRAM_SIZE SZ_512M +#define is_mx6ull_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6ULL_9X9_EVK) + +#ifdef CONFIG_TARGET_MX6ULL_9X9_EVK +#define PHYS_SDRAM_SIZE SZ_256M +#define BOOTARGS_CMA_SIZE "cma=96M " +#else +#define PHYS_SDRAM_SIZE SZ_512M +#define BOOTARGS_CMA_SIZE "" +/* DCDC used on 14x14 EVK, no PMIC */ +#undef CONFIG_LDO_BYPASS_CHECK +#endif #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -35,7 +47,7 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR /* NAND pin conflicts with usdhc2 */ -#ifdef CONFIG_SYS_USE_NAND +#ifdef CONFIG_CMD_NAND #define CONFIG_SYS_FSL_USDHC_NUM 1 #else #define CONFIG_SYS_FSL_USDHC_NUM 2 @@ -50,24 +62,81 @@ #define CONFIG_SYS_I2C_SPEED 100000 #endif +/* Only use DM I2C driver for 14x14 EVK. Because the PFUZE3000 driver does not support DM */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C + +/* PMIC only for 9X9 EVK */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#endif + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),16m(tee),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=1\0"\ + "emmc_ack=1\0"\ + "sd_dev=1\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + BOOTARGS_CMA_SIZE \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "if test ${tee} = yes; then " \ + "nand read ${tee_addr} 0x6000000 0x400000;"\ + "bootm ${teeaddr} - ${fdt_addr};" \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr};" \ + "fi\0" + +#else #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6ull-14x14-evk.dtb\0" \ + "fdt_file=undefined\0" \ "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=undefined\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + "panel=TFT43AB\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ @@ -75,25 +144,32 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ + "${usb_net_cmd}; " \ "run netargs; " \ "if test ${ip_dyn} = yes; then " \ "setenv get_cmd dhcp; " \ @@ -101,21 +177,53 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ + "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \ + "if test $board_name = EVK && test $board_rev = 9X9; then " \ + "setenv fdt_file imx6ull-9x9-evk.dtb; fi; " \ + "if test $board_name = EVK && test $board_rev = 14X14; then " \ + "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; " \ + "fi; " \ + "fi;\0" \ + "findtee="\ + "if test $tee_file = undefined; then " \ + "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ + "setenv tee_file uTee-6ulzevk; fi; " \ + "if test $board_name = EVK && test $board_rev = 9X9; then " \ + "setenv tee_file uTee-6ullevk; fi; " \ + "if test $board_name = EVK && test $board_rev = 14X14; then " \ + "setenv tee_file uTee-6ullevk; fi; " \ + "if test $tee_file = undefined; then " \ + "echo WARNING: Could not determine tee to use; " \ + "fi; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ + "run findtee;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -127,6 +235,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" +#endif /* Miscellaneous configurable options */ #define CONFIG_SYS_MEMTEST_START 0x80000000 @@ -153,9 +262,6 @@ #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (12 * SZ_64K) - #define CONFIG_IMX_THERMAL #define CONFIG_IOMUX_LPSR @@ -172,4 +278,81 @@ #define FSL_QSPI_FLASH_SIZE SZ_32M #endif +#ifdef CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#define CONFIG_ENV_SIZE SZ_8K +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#ifdef CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE RMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC0" +#endif +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth1" +#else +#define CONFIG_ETHPRIME "FEC1" +#endif +#endif +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +#define CONFIG_MODULE_FUSE +#define CONFIG_OF_SYSTEM_SETUP + #endif diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index defb38c5b33..718cf16991d 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -33,10 +33,12 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #ifndef CONFIG_SYS_DCACHE_OFF #endif @@ -58,7 +60,12 @@ /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE 0x2000 +#define CONFIG_CSF_SIZE 0x4000 #endif +#ifdef CONFIG_IMX_OPTEE +#define TEE_ENV "tee=yes\0" +#else +#define TEE_ENV "tee=no\0" +#endif #endif diff --git a/include/configs/mx7d_12x12_ddr3_arm2.h b/include/configs/mx7d_12x12_ddr3_arm2.h new file mode 100644 index 00000000000..46bc5b0c97a --- /dev/null +++ b/include/configs/mx7d_12x12_ddr3_arm2.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * Configuration settings for the Freescale i.MX7D 12x12 DDR3 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_12X12_DDR3_ARM2_CONFIG_H +#define __MX7D_12X12_DDR3_ARM2_CONFIG_H + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC3 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC3 */ + +#define PHYS_SDRAM_SIZE SZ_1G + +#ifdef CONFIG_SPI_BOOT +#define CONFIG_MXC_SPI +#endif + +#ifdef CONFIG_MXC_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 3 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +#include "mx7d_arm2.h" + +#endif diff --git a/include/configs/mx7d_12x12_lpddr3_arm2.h b/include/configs/mx7d_12x12_lpddr3_arm2.h new file mode 100644 index 00000000000..428dbc53c45 --- /dev/null +++ b/include/configs/mx7d_12x12_lpddr3_arm2.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D 12x12 LPDDR3 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_12X12_LPDDR3_ARM2_CONFIG_H +#define __MX7D_12X12_LPDDR3_ARM2_CONFIG_H + +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#define PHYS_SDRAM_SIZE SZ_2G + +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC" +#endif +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* ENET1 */ +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#elif defined CONFIG_SPI_BOOT +#define CONFIG_MXC_SPI +#endif + +#ifdef CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +/* #define CONFIG_SPLASH_SCREEN*/ +/* #define CONFIG_MXC_EPDC*/ + +#include "mx7d_arm2.h" + +#endif diff --git a/include/configs/mx7d_19x19_ddr3_arm2.h b/include/configs/mx7d_19x19_ddr3_arm2.h new file mode 100644 index 00000000000..d319e36f12b --- /dev/null +++ b/include/configs/mx7d_19x19_ddr3_arm2.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D 19x19 DDR3 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_19X19_DDR3_ARM2_CONFIG_H +#define __MX7D_19X19_DDR3_ARM2_CONFIG_H + +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define PHYS_SDRAM_SIZE SZ_1G + +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC" +#endif +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* ENET2 */ +#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR + +#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR + +/* For QSPI, not use DM driver, because DTS does not have it supported */ +#ifdef CONFIG_SPI_BOOT +#define CONFIG_MXC_SPI +#endif + +#define CONFIG_FSL_QSPI /* Enable the QSPI flash at default */ + +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#endif + +#ifdef CONFIG_MXC_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +#include "mx7d_arm2.h" + +#endif diff --git a/include/configs/mx7d_19x19_lpddr3_arm2.h b/include/configs/mx7d_19x19_lpddr3_arm2.h new file mode 100644 index 00000000000..2822e8bac7a --- /dev/null +++ b/include/configs/mx7d_19x19_lpddr3_arm2.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D 19x19 LPDDR3 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_19X19_LPDDR3_ARM2_CONFIG_H +#define __MX7D_19X19_LPDDR3_ARM2_CONFIG_H + +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#ifdef CONFIG_TARGET_MX7D_19X19_LPDDR2_ARM2 +#define PHYS_SDRAM_SIZE SZ_512M +#else +#define PHYS_SDRAM_SIZE SZ_2G +#endif + +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC" +#endif +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* ENET2 */ +#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR + +#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR + +/* QSPI conflict with EIMNOR */ +/* FEC0 conflict with EIMNOR */ +/* ECSPI conflict with UART */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#elif defined CONFIG_SPI_BOOT +#define CONFIG_MXC_SPI +#elif defined CONFIG_NOR_BOOT +#define CONFIG_MTD_NOR_FLASH +#undef CONFIG_FEC_MXC +#elif defined CONFIG_NAND_BOOT +#define CONFIG_NAND_MXS +#else +#define CONFIG_MTD_NOR_FLASH +#undef CONFIG_FEC_MXC +#endif + +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#endif + +#ifdef CONFIG_MXC_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +#include "mx7d_arm2.h" + +#endif diff --git a/include/configs/mx7d_arm2.h b/include/configs/mx7d_arm2.h new file mode 100644 index 00000000000..08cf32d753b --- /dev/null +++ b/include/configs/mx7d_arm2.h @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_ARM2_CONFIG_H +#define __MX7D_ARM2_CONFIG_H + +#include "mx7_common.h" + +#define CONFIG_DBG_MONITOR + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +#define CONFIG_IMX_THERMAL + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_BAUDRATE 115200 + +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 + +/* I2C configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +#undef CONFIG_CMD_IMLS + +#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000 + +#ifdef CONFIG_DM_SPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x68000000 /* Set to QSPI1 B flash at default */ +#define SF_QSPI1_B_CS_NUM 2 +#define SF_QSPI1_B_BUS_NUM 1 +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x62000000 /* Set to QSPI1 B flash at default */ +#define SF_QSPI1_B_CS_NUM 1 +#define SF_QSPI1_B_BUS_NUM 0 +#endif + +#ifdef CONFIG_IMX_BOOTAUX + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "m4_qspi_cs="__stringify(SF_QSPI1_B_CS_NUM)"\0" \ + "m4_qspi_bus="__stringify(SF_QSPI1_B_BUS_NUM)"\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe ${m4_qspi_bus}:${m4_qspi_cs}; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe ${m4_qspi_bus}:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=MCIMX28LCD\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=5 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + UPDATE_M4_ENV \ + "epdc_waveform=epdc_splash.bin\0" \ + "panel=MCIMX28LCD\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x40000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#ifdef CONFIG_DM_SPI +#define FSL_QSPI_FLASH_NUM 4 +#define CONFIG_SF_DEFAULT_BUS 1 /* Have set the QSPI to SPI 1 in imx7d.dtsi alias*/ +#else +#define FSL_QSPI_FLASH_NUM 2 /* Non-DM driver only supports 2 flash, one is on A port, another is on B port*/ +#define CONFIG_SF_DEFAULT_BUS 0 +#endif +#define FSL_QSPI_FLASH_SIZE SZ_64M +#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR +#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_PROTECTION +#endif + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_FLASH) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_FLASH_SECT_SIZE) +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +#if defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 3a9eaf9f4c4..f5171bb579a 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * Configuration settings for the Freescale i.MX7D SABRESD board. * @@ -10,6 +11,7 @@ #define __MX7D_SABRESD_CONFIG_H #include "mx7_common.h" +#include "imx_env.h" #define CONFIG_DBG_MONITOR #define PHYS_SDRAM_SIZE SZ_1G @@ -20,15 +22,26 @@ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) /* Network */ +#ifdef CONFIG_DM_ETH #define CONFIG_FEC_MXC #define CONFIG_MII #define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_ENET_DEV 0 #define CONFIG_PHY_BROADCOM /* ENET1 */ +#if (CONFIG_FEC_ENET_DEV == 0) #define IMX_FEC_BASE ENET_IPS_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_ETHPRIME "eth1" +#endif + +#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR +#endif /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -45,38 +58,50 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #ifdef CONFIG_IMX_BOOTAUX -/* Set to QSPI1 A flash at default */ -#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 +#ifdef CONFIG_FSL_QSPI #define UPDATE_M4_ENV \ "m4image=m4_qspi.bin\0" \ "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ "update_m4_from_sd=" \ - "if sf probe 0:0; then " \ + "if sf probe 1:0; then " \ "if run loadm4image; then " \ "setexpr fw_sz ${filesize} + 0xffff; " \ "setexpr fw_sz ${fw_sz} / 0x10000; " \ "setexpr fw_sz ${fw_sz} * 0x10000; " \ - "sf erase 0x0 ${fw_sz}; " \ - "sf write ${loadaddr} 0x0 ${filesize}; " \ + "sf erase 0x100000 ${fw_sz}; " \ + "sf write ${loadaddr} 0x100000 ${filesize}; " \ "fi; " \ "fi\0" \ - "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" + "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)" ${m4image}\0" \ + "m4boot=run loadm4image; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#endif #else #define UPDATE_M4_ENV "" #endif +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + #define CONFIG_MFG_ENV_SETTINGS \ - "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ - "rdinit=/linuxrc " \ - "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ - "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ - "g_mass_storage.iSerialNumber=\"\" "\ - "clk_ignore_unused "\ - "\0" \ - "initrd_addr=0x83800000\0" \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ "initrd_high=0xffffffff\0" \ - "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + "emmc_dev=1\0"\ + "sd_dev=0\0" \ + "mtdparts=" MFG_NAND_PARTITION \ + "\0"\ #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=image raw 0 0x800000;"\ @@ -84,20 +109,45 @@ "bootimg part 0 1;"\ "rootfs part 0 2\0" \ +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "if test ${tee} = yes; then " \ + "nand read ${tee_addr} 0x6000000 0x400000;"\ + "bootm ${teeaddr} - ${fdt_addr};" \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr};" \ + "fi\0" + +#else #define CONFIG_EXTRA_ENV_SETTINGS \ UPDATE_M4_ENV \ CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ CONFIG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx7d-sdb.dtb\0" \ + "fdt_file=undefined\0" \ "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=uTee-7dsdb\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + "panel=TFT43AB\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ @@ -110,20 +160,25 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -136,21 +191,32 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "setenv fdt_file imx7d-sdb.dtb; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -162,6 +228,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" +#endif #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) @@ -185,11 +252,35 @@ /* environment organization */ #define CONFIG_ENV_SIZE SZ_8K +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60100000 /* Set to QSPI1 A flash, offset 1M */ +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x7F8000 /* Set to TCML address */ +#endif /* - * If want to use nand, define CONFIG_NAND_MXS and rework board + * If want to use nand, define CONFIG_CMD_NAND and rework board * to support nand, since emmc has pin conflicts with nand */ -#ifdef CONFIG_NAND_MXS +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 @@ -197,15 +288,19 @@ #define CONFIG_SYS_NAND_ONFI_DETECTION /* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 #endif -#define CONFIG_ENV_OFFSET (12 * SZ_64K) #ifdef CONFIG_NAND_MXS #define CONFIG_SYS_FSL_USDHC_NUM 1 #else #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ @@ -215,8 +310,6 @@ #define CONFIG_IMX_THERMAL -#define CONFIG_USBD_HS - #ifdef CONFIG_VIDEO #define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO @@ -225,13 +318,37 @@ #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* #define CONFIG_SPLASH_SCREEN*/ +/* #define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_FSL_QSPI) +#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!" #endif #ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_BAR -#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SYS_FSL_QSPI_AHB +#define CONFIG_SF_DEFAULT_BUS 1 /* SOFT SPI occupies the BUS 0, so change the QSPI1 to BUS 1*/ #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 @@ -241,4 +358,12 @@ #define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR #endif +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mx7dsabresdandroid.h" +#elif defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "mx7dsabresd_androidthings.h" +#else +#define CONFIG_USBD_HS +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/mx7dsabresd_androidthings.h b/include/configs/mx7dsabresd_androidthings.h new file mode 100644 index 00000000000..51b0a84173f --- /dev/null +++ b/include/configs/mx7dsabresd_androidthings.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7DSABRESDBRSD_ANDROIDTHINGS_H +#define __MX7DSABRESDBRSD_ANDROIDTHINGS_H +#include "mx_android_common.h" + +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_ANDROID_AB_SUPPORT +#define FASTBOOT_ENCRYPT_LOCK + +#define CONFIG_SHA1 +#define CONFIG_SHA256 + + +#ifdef CONFIG_SYS_MMC_ENV_DEV +#undef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#endif + +#ifdef CONFIG_SYS_MMC_ENV_PART +#undef CONFIG_SYS_MMC_ENV_PART +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */ +#endif + +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_CMD_FS_GENERIC + +#define CONFIG_AVB_SUPPORT +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +/* fuse bank size in word */ +/* infact 7D have no enough bits + * set this size to 0 will disable + * program/read FUSE */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#endif + +#endif + diff --git a/include/configs/mx7dsabresdandroid.h b/include/configs/mx7dsabresdandroid.h new file mode 100644 index 00000000000..10e169af9b9 --- /dev/null +++ b/include/configs/mx7dsabresdandroid.h @@ -0,0 +1,38 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_SABRESD_ANDROID_H +#define __MX7D_SABRESD_ANDROID_H +#include "mx_android_common.h" + +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +/* lock/unlock stuff */ +#define FASTBOOT_ENCRYPT_LOCK +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" +#define CONFIG_SHA1 + +#define CONFIG_AVB_SUPPORT +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_ANDROID_RECOVERY + +#ifdef CONFIG_SYS_CBSIZE +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 2048 +#endif + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +#endif /* CONFIG_AVB_SUPPORT */ + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif /* __MX7D_SABRESD_ANDROID_H */ diff --git a/include/configs/mx7ulp_arm2.h b/include/configs/mx7ulp_arm2.h new file mode 100644 index 00000000000..41310262bd9 --- /dev/null +++ b/include/configs/mx7ulp_arm2.h @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7ULP ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7ULP_ARM2_CONFIG_H +#define __MX7ULP_ARM2_CONFIG_H + +#include +#include + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_CSF_SIZE +#define CONFIG_CSF_SIZE 0x4000 +#endif +#endif + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +#define SRC_BASE_ADDR CMC1_RBASE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IOMUXC_BASE_ADDR IOMUXC1_RBASE + +/* Fuses */ +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#ifndef CONFIG_DM_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#else +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ +#endif +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG1_RBASE + + +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ + +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +/*#define CONFIG_REVISION_TAG*/ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) + +/* UART */ +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 +#define LPUART_BASE LPUART6_RBASE +#else +#define LPUART_BASE LPUART4_RBASE +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 256 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_TEXT_BASE 0x67800000 +#define PHYS_SDRAM 0x60000000 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 +#define PHYS_SDRAM_SIZE SZ_1G /*LPDDR2 1G*/ +#define CONFIG_SYS_MEMTEST_END 0x9E000000 +#else +#define PHYS_SDRAM_SIZE SZ_512M +#define CONFIG_SYS_MEMTEST_END 0x7E000000 +#endif +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +#define CONFIG_LOADADDR 0x60800000 + +#define CONFIG_CMD_MEMTEST + +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 +#define CONFIG_DEFAULT_FDT_FILE "imx7ulp-10x10-arm2.dtb" +#else +#define CONFIG_DEFAULT_FDT_FILE "imx7ulp-14x14-arm2.dtb" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "\0" \ + "initrd_addr=0x66800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttyLP0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x63000000\0" \ + "boot_fdt=try\0" \ + "earlycon=lpuart32,0x402D0010\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +/* QSPI configs */ +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 +#define FSL_QSPI_FLASH_NUM 2 +#define FSL_QSPI_FLASH_SIZE SZ_32M +#else +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_64M +#endif +#define QSPI0_BASE_ADDR 0x410A5000 +#define QSPI0_AMBA_BASE 0xC0000000 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 31b6d3e448e..7d49672af65 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Configuration settings for the Freescale i.MX7ULP EVK board. * @@ -11,9 +12,7 @@ #include #include - -/*Uncomment it to use secure boot*/ -/*#define CONFIG_SECURE_BOOT*/ +#include "configs/imx_env.h" #ifdef CONFIG_SECURE_BOOT #ifndef CONFIG_CSF_SIZE @@ -28,6 +27,12 @@ #define IRAM_BASE_ADDR OCRAM_0_BASE #define IOMUXC_BASE_ADDR IOMUXC1_RBASE +/* Fuses */ +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +#define CONFIG_SERIAL_TAG + #define CONFIG_BOUNCE_BUFFER #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC @@ -41,7 +46,7 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_ENV_OFFSET (12 * SZ_64K) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K /* Using ULP WDOG for reset */ @@ -58,8 +63,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) -#define CONFIG_BOARD_EARLY_INIT_F - /* UART */ #define LPUART_BASE LPUART4_RBASE @@ -79,7 +82,7 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x60000000 +#define PHYS_SDRAM 0x60000000ul #define PHYS_SDRAM_SIZE SZ_1G #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM @@ -87,16 +90,27 @@ #define CONFIG_LOADADDR 0x60800000 #define CONFIG_CMD_MEMTEST -#define CONFIG_SYS_MEMTEST_END 0x9E000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x66800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=0\0" #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttyLP0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx7ulp-evk.dtb\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE ".dtb\0" \ "fdt_addr=0x63000000\0" \ + "tee_addr=0x64000000\0" \ + "tee_file=uTee-7ulp\0" \ "boot_fdt=try\0" \ "earlycon=lpuart32,0x402D0010\0" \ "ip_dyn=yes\0" \ @@ -112,20 +126,25 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -139,18 +158,24 @@ "fi; " \ "usb start; "\ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ #define CONFIG_BOOTCOMMAND \ @@ -160,6 +185,7 @@ "else " \ "if run loadimage; then " \ "run mmcboot; " \ + "else run netboot; " \ "fi; " \ "fi; " \ "fi" @@ -179,4 +205,46 @@ #define CONFIG_CMD_CACHE #endif +/* QSPI configs */ +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_8M +#define QSPI0_BASE_ADDR 0x410A5000 +#define QSPI0_AMBA_BASE 0xC0000000 +#endif + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP + +#define CONFIG_HX8363 +#define CONFIG_RM68200 +#endif + +#define CONFIG_OF_SYSTEM_SETUP + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mx7ulp_evk_android.h" +#endif + +#ifdef CONFIG_IMX_OPTEE +#define TEE_ENV "tee=yes\0" +#else +#define TEE_ENV "tee=no\0" +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_evk_android.h b/include/configs/mx7ulp_evk_android.h new file mode 100644 index 00000000000..e4c774ffbfe --- /dev/null +++ b/include/configs/mx7ulp_evk_android.h @@ -0,0 +1,44 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7ULP_EVK_ANDROID_H +#define __MX7ULP_EVK_ANDROID_H +#include "mx_android_common.h" + +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +#define CONFIG_AVB_SUPPORT +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" + +#define CONFIG_ANDROID_RECOVERY +#define CONFIG_SHA1 + +#ifdef CONFIG_SYS_CBSIZE +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 2048 +#endif + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +/* Enable mcu firmware flash */ +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_SF +#define ANDROID_MCU_FIRMWARE_START 0 +#define ANDROID_MCU_FIRMWARE_SIZE 0x20000 +#endif + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif diff --git a/include/configs/mx_android_common.h b/include/configs/mx_android_common.h new file mode 100644 index 00000000000..3e1e96e4b26 --- /dev/null +++ b/include/configs/mx_android_common.h @@ -0,0 +1,55 @@ +/* + * Copyright 2017 NXP + */ + +#ifndef __MX_ANDROID_COMMON_H +#define __MX_ANDROID_COMMON_H + +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_BCB_SUPPORT +#define CONFIG_CMD_READ + +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_USB_GADGET_VENDOR_NUM 0x18d1 +#define CONFIG_USB_GADGET_PRODUCT_NUM 0x0d02 +#define CONFIG_USB_GADGET_MANUFACTURER "FSL" + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_FASTBOOT_FLASH + +#define CONFIG_FSL_FASTBOOT +#define CONFIG_ANDROID_RECOVERY + +#if defined CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_STORAGE_NAND +#elif defined CONFIG_SATA_BOOT +#define CONFIG_FASTBOOT_STORAGE_SATA +#else +#define CONFIG_FASTBOOT_STORAGE_MMC +#endif + +#define CONFIG_CMD_BOOTA +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SERIAL_TAG + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x19000000 +#define CONFIG_APPEND_BOOTARGS + +#endif /*MX_ANDROID_COMMON_H*/ diff --git a/include/configs/pico-imx6dl.h b/include/configs/pico-imx6dl.h new file mode 100644 index 00000000000..b2037dbd748 --- /dev/null +++ b/include/configs/pico-imx6dl.h @@ -0,0 +1,239 @@ +/* + * Copyright (C) 2015 Technexion Ltd. + * Copyright 2017-2018 NXP + * + * Configuration settings for the Technexion Pico i.mx6DL board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __PICO_IMX6DL_CONFIG_H +#define __PICO_IMX6DL_CONFIG_H + +#include "mx6_common.h" + +#undef CONFIG_LDO_BYPASS_CHECK + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +/* #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR */ +/* #define CONFIG_SYS_FSL_USDHC_NUM 1 */ + + +/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR + + + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE RMII +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 /* need board rework */ +#define CONFIG_FEC_XCV_TYPE RMII +#endif +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#endif + +/* I2C configs */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#ifdef CONFIG_DEFAULT_FDT_FILE +#undef CONFIG_DEFAULT_FDT_FILE +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-pico.dtb" +#endif + +#define PHYS_SDRAM_SIZE SZ_512M + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + + +/* Framebuffer */ +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "loadaddr=0x12000000\0" \ + "fdt_addr=0x18000000\0" \ + "initrd_addr=0x12C00000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "splashpos=m,m\0" \ + "som=autodetect\0" \ + "baseboard=dwarf\0" \ + "default_baseboard=dwarf\0" \ + "fdtfile=undefined\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x18000000\0" \ + "boot_fdt=try\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (12 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (384 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC3 */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ + + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define PRODUCT_NAME "imx6dl_pico" +#define VARIANT_NAME "imx6dl_pico" + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "pico-imx6dl_android_things.h" +#endif + +#endif diff --git a/include/configs/pico-imx6dl_android_things.h b/include/configs/pico-imx6dl_android_things.h new file mode 100644 index 00000000000..469d7aff9b9 --- /dev/null +++ b/include/configs/pico-imx6dl_android_things.h @@ -0,0 +1,40 @@ + +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PICO_IMX6DL_ANDROID_THINGS_H +#define __PICO_IMX6DL_ANDROID_THINGS_H +#include "mx_android_common.h" +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_AVB_SUPPORT +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#ifdef CONFIG_AVB_SUPPORT + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#define CONFIG_SUPPORT_EMMC_RPMB +/* fuse bank size in word */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 8 +#define CONFIG_AVB_FUSE_BANK_START 10 +#define CONFIG_AVB_FUSE_BANK_END 15 +#endif + +#endif +/* __PICO_IMX6DL_ANDROID_THINGS_H */ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index ee483635906..7fe238bcdda 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -11,13 +11,10 @@ #include "mx7_common.h" -#define PHYS_SDRAM_SIZE SZ_1G - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR - /* Network */ #define CONFIG_FEC_MXC #define CONFIG_MII @@ -25,40 +22,106 @@ #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 1 -#define CONFIG_PHY_ATHEROS +#define CONFIG_PHYLIB +#define CONFIG_PHY_BROADCOM /* ENET1 */ #define IMX_FEC_BASE ENET_IPS_BASE_ADDR +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_IPS_BASE_ADDR /* MMC Config */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 /* Set to QSPI1 A flash at default */ +#ifdef CONFIG_CMD_BOOTAUX + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 0:0; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=EJ050NA\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc4\0" \ + "bootargs=console=ttymxc4,115200 ubi.mtd=3 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + UPDATE_M4_ENV \ + "panel=EJ050NA\0" \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc4\0" \ + "splashpos=m,m\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx7d-pico.dtb\0" \ + "fdt_file=imx7d-pico_dwarf.dtb\0" \ "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "finduuid=part uuid mmc 0:2 uuid\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ + "root=${mmcroot} 2\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ "run mmcargs; " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -71,19 +134,33 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ - "if mmc rescan; then " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "else run netboot; fi" + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) @@ -122,13 +199,50 @@ /* FLASH and environment organization */ #define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_ENV_OFFSET (13 * SZ_64K) #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +/* #define CONFIG_SPLASH_SCREEN*/ +/* #define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ +#define CONFIG_CFB_CONSOLE +#define CONFIG_CMD_BMP +#define CONFIG_LCD +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif /* USB Configs */ +#define CONFIG_USB_EHCI_HCD +#define CONFIG_USB_EHCI_MX7 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 @@ -136,4 +250,15 @@ #define CONFIG_IMX_THERMAL +#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_FSL_QSPI) +#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!" #endif + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "pico-imx7dandroidthings.h" +#endif + +#define PRODUCT_NAME "imx7d" +#define VARIANT_NAME "imx7d_pico" + +#endif /* __CONFIG_H */ diff --git a/include/configs/pico-imx7dandroidthings.h b/include/configs/pico-imx7dandroidthings.h new file mode 100644 index 00000000000..d06e0c13059 --- /dev/null +++ b/include/configs/pico-imx7dandroidthings.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PICO_IMX7DANDROIDTHINGS_H +#define __PICO_IMX7DANDROIDTHINGS_H + +#define TRUSTY_OS_ENTRY 0x9e000000 +#define TRUSTY_OS_RAM_SIZE 0x2000000 +#define TEE_HWPARTITION_ID 2 +#define TRUSTY_OS_MMC_BLKS 0xFFF +#define TRUSTY_OS_PADDED_SZ 0x180000 + +#define CONFIG_USB_GADGET +#define CONFIG_CMD_FASTBOOT + +#ifdef CONFIG_AVB_ATX +#define PERMANENT_ATTRIBUTE_HASH_OFFSET 0 +#define UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD 3 +#define UNLOCK_VBOOT_STATUS_OFFSET_IN_BIT 16 +#endif + +#define AVB_RPMB +#ifdef AVB_RPMB +#define KEYSLOT_BLKS 0xFFF +#define KEYSLOT_HWPARTITION_ID 2 +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NON_SECURE_FASTBOOT +#define TRUSTY_KEYSLOT_PACKAGE +#endif +#include "mx_android_common.h" + + +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT + +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_SYSTEM_RAMDISK_SUPPORT + +#ifdef CONFIG_SYS_MMC_ENV_DEV +#undef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#endif + +#ifdef CONFIG_SYS_MMC_ENV_PART +#undef CONFIG_SYS_MMC_ENV_PART +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */ +#endif + + +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) +#endif +/* fuse bank size in word */ +/* infact 7D have no enough bits + * set this size to 0 will disable + * program/read FUSE */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 4 +#define CONFIG_AVB_FUSE_BANK_START 14 +#define CONFIG_AVB_FUSE_BANK_END 14 +#endif + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +/* Disable U-Boot logo */ +#undef CONFIG_VIDEO_LOGO + +#endif +/* __PICO_IMX7DANDROIDTHINGS_H */ diff --git a/include/configs/picosom-imx6ul.h b/include/configs/picosom-imx6ul.h new file mode 100644 index 00000000000..727b0dd3518 --- /dev/null +++ b/include/configs/picosom-imx6ul.h @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2015 Technexion Ltd. + * Copyright 2018 NXP + * + * Configuration settings for the Technexion PicoSOM i.mx6UL board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __PICOSOM_IMX6UL_CONFIG_H +#define __PICOSOM_IMX6UL_CONFIG_H + + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE MX6UL_UART6_BASE_ADDR + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE RMII +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 /* need board rework */ +#define CONFIG_FEC_XCV_TYPE RMII +#endif +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#endif + +/* I2C configs */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + + +#define PHYS_SDRAM_SIZE SZ_512M + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + + +/* #define CONFIG_VIDEO */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc5\0" \ + "bootargs=console=ttymxc5,115200 ubi.mtd=3 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc5\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_QSPI_BASE QSPI0_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI0_AMBA_BASE + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_32M +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (13 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (384 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define PRODUCT_NAME "imx6ul_pico" +#define VARIANT_NAME "imx6ul_pico" + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "picosom-imx6ul_android_things.h" +#endif + +#endif diff --git a/include/configs/picosom-imx6ul_android_things.h b/include/configs/picosom-imx6ul_android_things.h new file mode 100644 index 00000000000..d75222544a8 --- /dev/null +++ b/include/configs/picosom-imx6ul_android_things.h @@ -0,0 +1,61 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PICOSOM_IMX6UL_ANDROID_THINGS_H +#define __PICOSOM_IMX6UL_ANDROID_THINGS_H + +#ifdef CONFIG_AVB_ATX +#define PERMANENT_ATTRIBUTE_HASH_OFFSET 32 +#endif + +#define AVB_RPMB +#ifdef AVB_RPMB +#define KEYSLOT_BLKS 0xFFF +#define KEYSLOT_HWPARTITION_ID 2 +#endif + +#include "mx_android_common.h" +#define TRUSTY_OS_ENTRY 0x9e000000 +#define TRUSTY_OS_RAM_SIZE 0x2000000 +#define TRUSTY_OS_MMC_BLKS 0xFFF +#define TEE_HWPARTITION_ID 2 + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NON_SECURE_FASTBOOT +#endif +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_AVB_SUPPORT +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#ifdef CONFIG_AVB_SUPPORT + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#define CONFIG_SUPPORT_EMMC_RPMB +/* fuse bank size in word */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 8 +#define CONFIG_AVB_FUSE_BANK_START 10 +#define CONFIG_AVB_FUSE_BANK_END 15 +#endif + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif +/* __PICOSOM_IMX6UL_ANDROID_THINGS_H */ diff --git a/include/dm/device.h b/include/dm/device.h index 7786b1cf4e6..d2b19899d2c 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -62,6 +62,9 @@ struct driver_info; */ #define DM_FLAG_OS_PREPARE (1 << 10) +/* DM should ignore the power domain on for this driver */ +#define DM_FLAG_IGNORE_POWER_ON (1 << 11) + /* * One or multiple of these flags are passed to device_remove() so that * a selective device removal as specified by the remove-stage and the diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 07fabc3ce6c..d28fb3e23f0 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -19,6 +19,7 @@ enum uclass_id { UCLASS_TEST_FDT, UCLASS_TEST_BUS, UCLASS_TEST_PROBE, + UCLASS_TEST_DUMMY, UCLASS_SPI_EMUL, /* sandbox SPI device emulator */ UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ UCLASS_PCI_EMUL, /* sandbox PCI device emulator */ diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index 29050337d9d..6915b25ed37 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -62,8 +62,8 @@ #define IMX6QDL_CLK_USDHC3_SEL 50 #define IMX6QDL_CLK_USDHC4_SEL 51 #define IMX6QDL_CLK_ENFC_SEL 52 -#define IMX6QDL_CLK_EIM_SEL 53 -#define IMX6QDL_CLK_EIM_SLOW_SEL 54 +#define IMX6QDL_CLK_EMI_SEL 53 +#define IMX6QDL_CLK_EMI_SLOW_SEL 54 #define IMX6QDL_CLK_VDO_AXI_SEL 55 #define IMX6QDL_CLK_VPU_AXI_SEL 56 #define IMX6QDL_CLK_CKO1_SEL 57 @@ -86,8 +86,6 @@ #define IMX6QDL_CLK_GPU3D_SHADER 74 #define IMX6QDL_CLK_IPU1_PODF 75 #define IMX6QDL_CLK_IPU2_PODF 76 -#define IMX6QDL_CLK_LDB_DI0_PODF 77 -#define IMX6QDL_CLK_LDB_DI1_PODF 78 #define IMX6QDL_CLK_IPU1_DI0_PRE 79 #define IMX6QDL_CLK_IPU1_DI1_PRE 80 #define IMX6QDL_CLK_IPU2_DI0_PRE 81 @@ -106,13 +104,11 @@ #define IMX6QDL_CLK_USDHC4_PODF 94 #define IMX6QDL_CLK_ENFC_PRED 95 #define IMX6QDL_CLK_ENFC_PODF 96 -#define IMX6QDL_CLK_EIM_PODF 97 -#define IMX6QDL_CLK_EIM_SLOW_PODF 98 +#define IMX6QDL_CLK_EMI_PODF 97 +#define IMX6QDL_CLK_EMI_SLOW_PODF 98 #define IMX6QDL_CLK_VPU_AXI_PODF 99 #define IMX6QDL_CLK_CKO1_PODF 100 #define IMX6QDL_CLK_AXI 101 -#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 -#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 #define IMX6QDL_CLK_ARM 104 #define IMX6QDL_CLK_AHB 105 #define IMX6QDL_CLK_APBH_DMA 106 @@ -218,57 +214,62 @@ #define IMX6QDL_CLK_LVDS2_SEL 205 #define IMX6QDL_CLK_LVDS1_GATE 206 #define IMX6QDL_CLK_LVDS2_GATE 207 -#define IMX6QDL_CLK_ESAI_IPG 208 -#define IMX6QDL_CLK_ESAI_MEM 209 -#define IMX6QDL_CLK_ASRC_IPG 210 -#define IMX6QDL_CLK_ASRC_MEM 211 -#define IMX6QDL_CLK_LVDS1_IN 212 -#define IMX6QDL_CLK_LVDS2_IN 213 -#define IMX6QDL_CLK_ANACLK1 214 -#define IMX6QDL_CLK_ANACLK2 215 -#define IMX6QDL_PLL1_BYPASS_SRC 216 -#define IMX6QDL_PLL2_BYPASS_SRC 217 -#define IMX6QDL_PLL3_BYPASS_SRC 218 -#define IMX6QDL_PLL4_BYPASS_SRC 219 -#define IMX6QDL_PLL5_BYPASS_SRC 220 -#define IMX6QDL_PLL6_BYPASS_SRC 221 -#define IMX6QDL_PLL7_BYPASS_SRC 222 -#define IMX6QDL_CLK_PLL1 223 -#define IMX6QDL_CLK_PLL2 224 -#define IMX6QDL_CLK_PLL3 225 -#define IMX6QDL_CLK_PLL4 226 -#define IMX6QDL_CLK_PLL5 227 -#define IMX6QDL_CLK_PLL6 228 -#define IMX6QDL_CLK_PLL7 229 -#define IMX6QDL_PLL1_BYPASS 230 -#define IMX6QDL_PLL2_BYPASS 231 -#define IMX6QDL_PLL3_BYPASS 232 -#define IMX6QDL_PLL4_BYPASS 233 -#define IMX6QDL_PLL5_BYPASS 234 -#define IMX6QDL_PLL6_BYPASS 235 -#define IMX6QDL_PLL7_BYPASS 236 -#define IMX6QDL_CLK_GPT_3M 237 -#define IMX6QDL_CLK_VIDEO_27M 238 -#define IMX6QDL_CLK_MIPI_CORE_CFG 239 -#define IMX6QDL_CLK_MIPI_IPG 240 -#define IMX6QDL_CLK_CAAM_MEM 241 -#define IMX6QDL_CLK_CAAM_ACLK 242 -#define IMX6QDL_CLK_CAAM_IPG 243 -#define IMX6QDL_CLK_SPDIF_GCLK 244 -#define IMX6QDL_CLK_UART_SEL 245 -#define IMX6QDL_CLK_IPG_PER_SEL 246 -#define IMX6QDL_CLK_ECSPI_SEL 247 -#define IMX6QDL_CLK_CAN_SEL 248 -#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249 -#define IMX6QDL_CLK_PRE0 250 -#define IMX6QDL_CLK_PRE1 251 -#define IMX6QDL_CLK_PRE2 252 -#define IMX6QDL_CLK_PRE3 253 -#define IMX6QDL_CLK_PRG0_AXI 254 -#define IMX6QDL_CLK_PRG1_AXI 255 -#define IMX6QDL_CLK_PRG0_APB 256 -#define IMX6QDL_CLK_PRG1_APB 257 -#define IMX6QDL_CLK_PRE_AXI 258 -#define IMX6QDL_CLK_END 259 +#define IMX6QDL_CLK_ESAI_MEM 208 +#define IMX6QDL_CLK_LDB_DI0_DIV_7 209 +#define IMX6QDL_CLK_LDB_DI1_DIV_7 210 +#define IMX6QDL_CLK_LDB_DI0_DIV_SEL 211 +#define IMX6QDL_CLK_LDB_DI1_DIV_SEL 212 +#define IMX6QDL_CLK_VIDEO_27M 213 +#define IMX6QDL_CLK_DCIC1 214 +#define IMX6QDL_CLK_DCIC2 215 +#define IMX6QDL_CLK_GPT_3M 216 +#define IMX6QDL_CLK_ESAI_IPG 217 +#define IMX6QDL_CLK_ASRC_IPG 218 +#define IMX6QDL_CLK_ASRC_MEM 219 +#define IMX6QDL_CLK_LVDS1_IN 220 +#define IMX6QDL_CLK_LVDS2_IN 221 +#define IMX6QDL_CLK_ANACLK1 222 +#define IMX6QDL_CLK_ANACLK2 223 +#define IMX6QDL_PLL1_BYPASS_SRC 224 +#define IMX6QDL_PLL2_BYPASS_SRC 225 +#define IMX6QDL_PLL3_BYPASS_SRC 226 +#define IMX6QDL_PLL4_BYPASS_SRC 227 +#define IMX6QDL_PLL5_BYPASS_SRC 228 +#define IMX6QDL_PLL6_BYPASS_SRC 229 +#define IMX6QDL_PLL7_BYPASS_SRC 230 +#define IMX6QDL_CLK_PLL1 231 +#define IMX6QDL_CLK_PLL2 232 +#define IMX6QDL_CLK_PLL3 233 +#define IMX6QDL_CLK_PLL4 234 +#define IMX6QDL_CLK_PLL5 235 +#define IMX6QDL_CLK_PLL6 236 +#define IMX6QDL_CLK_PLL7 237 +#define IMX6QDL_PLL1_BYPASS 238 +#define IMX6QDL_PLL2_BYPASS 239 +#define IMX6QDL_PLL3_BYPASS 240 +#define IMX6QDL_PLL4_BYPASS 241 +#define IMX6QDL_PLL5_BYPASS 242 +#define IMX6QDL_PLL6_BYPASS 243 +#define IMX6QDL_PLL7_BYPASS 244 +#define IMX6QDL_CLK_AXI_ALT_SEL 245 +#define IMX6QDL_CAAM_MEM 246 +#define IMX6QDL_CAAM_ACLK 247 +#define IMX6QDL_CAAM_IPG 248 +#define IMX6QDL_CLK_SPDIF_GCLK 249 +#define IMX6QDL_CLK_UART_SEL 250 +#define IMX6QDL_CLK_IPG_PER_SEL 251 +#define IMX6QDL_CLK_ECSPI_SEL 252 +#define IMX6QDL_CLK_CAN_SEL 253 +#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 254 +#define IMX6QDL_CLK_PRE0 255 +#define IMX6QDL_CLK_PRE1 256 +#define IMX6QDL_CLK_PRE2 257 +#define IMX6QDL_CLK_PRE3 258 +#define IMX6QDL_CLK_PRG0_AXI 259 +#define IMX6QDL_CLK_PRG1_AXI 260 +#define IMX6QDL_CLK_PRG0_APB 261 +#define IMX6QDL_CLK_PRG1_APB 262 +#define IMX6QDL_CLK_PRE_AXI 263 +#define IMX6QDL_CLK_END 264 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h index 36f0324902a..cd2d6c570e8 100644 --- a/include/dt-bindings/clock/imx6sx-clock.h +++ b/include/dt-bindings/clock/imx6sx-clock.h @@ -275,6 +275,10 @@ #define IMX6SX_PLL6_BYPASS 262 #define IMX6SX_PLL7_BYPASS 263 #define IMX6SX_CLK_SPDIF_GCLK 264 -#define IMX6SX_CLK_CLK_END 265 +#define IMX6SX_CLK_LVDS2_SEL 265 +#define IMX6SX_CLK_LVDS2_OUT 266 +#define IMX6SX_CLK_LVDS2_IN 267 +#define IMX6SX_CLK_ANACLK2 268 +#define IMX6SX_CLK_CLK_END 269 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index a7a1a50f33e..feb3a3031e0 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -80,375 +81,379 @@ #define IMX7D_ARM_M4_ROOT_SRC 67 #define IMX7D_ARM_M4_ROOT_CG 68 #define IMX7D_ARM_M4_ROOT_DIV 69 -#define IMX7D_ARM_M0_ROOT_CLK 70 -#define IMX7D_ARM_M0_ROOT_SRC 71 -#define IMX7D_ARM_M0_ROOT_CG 72 -#define IMX7D_ARM_M0_ROOT_DIV 73 -#define IMX7D_MAIN_AXI_ROOT_CLK 74 -#define IMX7D_MAIN_AXI_ROOT_SRC 75 -#define IMX7D_MAIN_AXI_ROOT_CG 76 -#define IMX7D_MAIN_AXI_ROOT_DIV 77 -#define IMX7D_DISP_AXI_ROOT_CLK 78 -#define IMX7D_DISP_AXI_ROOT_SRC 79 -#define IMX7D_DISP_AXI_ROOT_CG 80 -#define IMX7D_DISP_AXI_ROOT_DIV 81 -#define IMX7D_ENET_AXI_ROOT_CLK 82 -#define IMX7D_ENET_AXI_ROOT_SRC 83 -#define IMX7D_ENET_AXI_ROOT_CG 84 -#define IMX7D_ENET_AXI_ROOT_DIV 85 -#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 -#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 -#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 -#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 -#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 -#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 -#define IMX7D_AHB_CHANNEL_ROOT_CG 92 -#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 -#define IMX7D_DRAM_PHYM_ROOT_CLK 94 -#define IMX7D_DRAM_PHYM_ROOT_SRC 95 -#define IMX7D_DRAM_PHYM_ROOT_CG 96 -#define IMX7D_DRAM_PHYM_ROOT_DIV 97 -#define IMX7D_DRAM_ROOT_CLK 98 -#define IMX7D_DRAM_ROOT_SRC 99 -#define IMX7D_DRAM_ROOT_CG 100 -#define IMX7D_DRAM_ROOT_DIV 101 -#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 -#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 -#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 -#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 -#define IMX7D_DRAM_ALT_ROOT_CLK 106 -#define IMX7D_DRAM_ALT_ROOT_SRC 107 -#define IMX7D_DRAM_ALT_ROOT_CG 108 -#define IMX7D_DRAM_ALT_ROOT_DIV 109 -#define IMX7D_USB_HSIC_ROOT_CLK 110 -#define IMX7D_USB_HSIC_ROOT_SRC 111 -#define IMX7D_USB_HSIC_ROOT_CG 112 -#define IMX7D_USB_HSIC_ROOT_DIV 113 -#define IMX7D_PCIE_CTRL_ROOT_CLK 114 -#define IMX7D_PCIE_CTRL_ROOT_SRC 115 -#define IMX7D_PCIE_CTRL_ROOT_CG 116 -#define IMX7D_PCIE_CTRL_ROOT_DIV 117 -#define IMX7D_PCIE_PHY_ROOT_CLK 118 -#define IMX7D_PCIE_PHY_ROOT_SRC 119 -#define IMX7D_PCIE_PHY_ROOT_CG 120 -#define IMX7D_PCIE_PHY_ROOT_DIV 121 -#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 -#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 -#define IMX7D_EPDC_PIXEL_ROOT_CG 124 -#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 -#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 -#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 -#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 -#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 -#define IMX7D_MIPI_DSI_ROOT_CLK 130 -#define IMX7D_MIPI_DSI_ROOT_SRC 131 -#define IMX7D_MIPI_DSI_ROOT_CG 132 -#define IMX7D_MIPI_DSI_ROOT_DIV 133 -#define IMX7D_MIPI_CSI_ROOT_CLK 134 -#define IMX7D_MIPI_CSI_ROOT_SRC 135 -#define IMX7D_MIPI_CSI_ROOT_CG 136 -#define IMX7D_MIPI_CSI_ROOT_DIV 137 -#define IMX7D_MIPI_DPHY_ROOT_CLK 138 -#define IMX7D_MIPI_DPHY_ROOT_SRC 139 -#define IMX7D_MIPI_DPHY_ROOT_CG 140 -#define IMX7D_MIPI_DPHY_ROOT_DIV 141 -#define IMX7D_SAI1_ROOT_CLK 142 -#define IMX7D_SAI1_ROOT_SRC 143 -#define IMX7D_SAI1_ROOT_CG 144 -#define IMX7D_SAI1_ROOT_DIV 145 -#define IMX7D_SAI2_ROOT_CLK 146 -#define IMX7D_SAI2_ROOT_SRC 147 -#define IMX7D_SAI2_ROOT_CG 148 -#define IMX7D_SAI2_ROOT_DIV 149 -#define IMX7D_SAI3_ROOT_CLK 150 -#define IMX7D_SAI3_ROOT_SRC 151 -#define IMX7D_SAI3_ROOT_CG 152 -#define IMX7D_SAI3_ROOT_DIV 153 -#define IMX7D_SPDIF_ROOT_CLK 154 -#define IMX7D_SPDIF_ROOT_SRC 155 -#define IMX7D_SPDIF_ROOT_CG 156 -#define IMX7D_SPDIF_ROOT_DIV 157 -#define IMX7D_ENET1_REF_ROOT_CLK 158 -#define IMX7D_ENET1_REF_ROOT_SRC 159 -#define IMX7D_ENET1_REF_ROOT_CG 160 -#define IMX7D_ENET1_REF_ROOT_DIV 161 -#define IMX7D_ENET1_TIME_ROOT_CLK 162 -#define IMX7D_ENET1_TIME_ROOT_SRC 163 -#define IMX7D_ENET1_TIME_ROOT_CG 164 -#define IMX7D_ENET1_TIME_ROOT_DIV 165 -#define IMX7D_ENET2_REF_ROOT_CLK 166 -#define IMX7D_ENET2_REF_ROOT_SRC 167 -#define IMX7D_ENET2_REF_ROOT_CG 168 -#define IMX7D_ENET2_REF_ROOT_DIV 169 -#define IMX7D_ENET2_TIME_ROOT_CLK 170 -#define IMX7D_ENET2_TIME_ROOT_SRC 171 -#define IMX7D_ENET2_TIME_ROOT_CG 172 -#define IMX7D_ENET2_TIME_ROOT_DIV 173 -#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 -#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 -#define IMX7D_ENET_PHY_REF_ROOT_CG 176 -#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 -#define IMX7D_EIM_ROOT_CLK 178 -#define IMX7D_EIM_ROOT_SRC 179 -#define IMX7D_EIM_ROOT_CG 180 -#define IMX7D_EIM_ROOT_DIV 181 -#define IMX7D_NAND_ROOT_CLK 182 -#define IMX7D_NAND_ROOT_SRC 183 -#define IMX7D_NAND_ROOT_CG 184 -#define IMX7D_NAND_ROOT_DIV 185 -#define IMX7D_QSPI_ROOT_CLK 186 -#define IMX7D_QSPI_ROOT_SRC 187 -#define IMX7D_QSPI_ROOT_CG 188 -#define IMX7D_QSPI_ROOT_DIV 189 -#define IMX7D_USDHC1_ROOT_CLK 190 -#define IMX7D_USDHC1_ROOT_SRC 191 -#define IMX7D_USDHC1_ROOT_CG 192 -#define IMX7D_USDHC1_ROOT_DIV 193 -#define IMX7D_USDHC2_ROOT_CLK 194 -#define IMX7D_USDHC2_ROOT_SRC 195 -#define IMX7D_USDHC2_ROOT_CG 196 -#define IMX7D_USDHC2_ROOT_DIV 197 -#define IMX7D_USDHC3_ROOT_CLK 198 -#define IMX7D_USDHC3_ROOT_SRC 199 -#define IMX7D_USDHC3_ROOT_CG 200 -#define IMX7D_USDHC3_ROOT_DIV 201 -#define IMX7D_CAN1_ROOT_CLK 202 -#define IMX7D_CAN1_ROOT_SRC 203 -#define IMX7D_CAN1_ROOT_CG 204 -#define IMX7D_CAN1_ROOT_DIV 205 -#define IMX7D_CAN2_ROOT_CLK 206 -#define IMX7D_CAN2_ROOT_SRC 207 -#define IMX7D_CAN2_ROOT_CG 208 -#define IMX7D_CAN2_ROOT_DIV 209 -#define IMX7D_I2C1_ROOT_CLK 210 -#define IMX7D_I2C1_ROOT_SRC 211 -#define IMX7D_I2C1_ROOT_CG 212 -#define IMX7D_I2C1_ROOT_DIV 213 -#define IMX7D_I2C2_ROOT_CLK 214 -#define IMX7D_I2C2_ROOT_SRC 215 -#define IMX7D_I2C2_ROOT_CG 216 -#define IMX7D_I2C2_ROOT_DIV 217 -#define IMX7D_I2C3_ROOT_CLK 218 -#define IMX7D_I2C3_ROOT_SRC 219 -#define IMX7D_I2C3_ROOT_CG 220 -#define IMX7D_I2C3_ROOT_DIV 221 -#define IMX7D_I2C4_ROOT_CLK 222 -#define IMX7D_I2C4_ROOT_SRC 223 -#define IMX7D_I2C4_ROOT_CG 224 -#define IMX7D_I2C4_ROOT_DIV 225 -#define IMX7D_UART1_ROOT_CLK 226 -#define IMX7D_UART1_ROOT_SRC 227 -#define IMX7D_UART1_ROOT_CG 228 -#define IMX7D_UART1_ROOT_DIV 229 -#define IMX7D_UART2_ROOT_CLK 230 -#define IMX7D_UART2_ROOT_SRC 231 -#define IMX7D_UART2_ROOT_CG 232 -#define IMX7D_UART2_ROOT_DIV 233 -#define IMX7D_UART3_ROOT_CLK 234 -#define IMX7D_UART3_ROOT_SRC 235 -#define IMX7D_UART3_ROOT_CG 236 -#define IMX7D_UART3_ROOT_DIV 237 -#define IMX7D_UART4_ROOT_CLK 238 -#define IMX7D_UART4_ROOT_SRC 239 -#define IMX7D_UART4_ROOT_CG 240 -#define IMX7D_UART4_ROOT_DIV 241 -#define IMX7D_UART5_ROOT_CLK 242 -#define IMX7D_UART5_ROOT_SRC 243 -#define IMX7D_UART5_ROOT_CG 244 -#define IMX7D_UART5_ROOT_DIV 245 -#define IMX7D_UART6_ROOT_CLK 246 -#define IMX7D_UART6_ROOT_SRC 247 -#define IMX7D_UART6_ROOT_CG 248 -#define IMX7D_UART6_ROOT_DIV 249 -#define IMX7D_UART7_ROOT_CLK 250 -#define IMX7D_UART7_ROOT_SRC 251 -#define IMX7D_UART7_ROOT_CG 252 -#define IMX7D_UART7_ROOT_DIV 253 -#define IMX7D_ECSPI1_ROOT_CLK 254 -#define IMX7D_ECSPI1_ROOT_SRC 255 -#define IMX7D_ECSPI1_ROOT_CG 256 -#define IMX7D_ECSPI1_ROOT_DIV 257 -#define IMX7D_ECSPI2_ROOT_CLK 258 -#define IMX7D_ECSPI2_ROOT_SRC 259 -#define IMX7D_ECSPI2_ROOT_CG 260 -#define IMX7D_ECSPI2_ROOT_DIV 261 -#define IMX7D_ECSPI3_ROOT_CLK 262 -#define IMX7D_ECSPI3_ROOT_SRC 263 -#define IMX7D_ECSPI3_ROOT_CG 264 -#define IMX7D_ECSPI3_ROOT_DIV 265 -#define IMX7D_ECSPI4_ROOT_CLK 266 -#define IMX7D_ECSPI4_ROOT_SRC 267 -#define IMX7D_ECSPI4_ROOT_CG 268 -#define IMX7D_ECSPI4_ROOT_DIV 269 -#define IMX7D_PWM1_ROOT_CLK 270 -#define IMX7D_PWM1_ROOT_SRC 271 -#define IMX7D_PWM1_ROOT_CG 272 -#define IMX7D_PWM1_ROOT_DIV 273 -#define IMX7D_PWM2_ROOT_CLK 274 -#define IMX7D_PWM2_ROOT_SRC 275 -#define IMX7D_PWM2_ROOT_CG 276 -#define IMX7D_PWM2_ROOT_DIV 277 -#define IMX7D_PWM3_ROOT_CLK 278 -#define IMX7D_PWM3_ROOT_SRC 279 -#define IMX7D_PWM3_ROOT_CG 280 -#define IMX7D_PWM3_ROOT_DIV 281 -#define IMX7D_PWM4_ROOT_CLK 282 -#define IMX7D_PWM4_ROOT_SRC 283 -#define IMX7D_PWM4_ROOT_CG 284 -#define IMX7D_PWM4_ROOT_DIV 285 -#define IMX7D_FLEXTIMER1_ROOT_CLK 286 -#define IMX7D_FLEXTIMER1_ROOT_SRC 287 -#define IMX7D_FLEXTIMER1_ROOT_CG 288 -#define IMX7D_FLEXTIMER1_ROOT_DIV 289 -#define IMX7D_FLEXTIMER2_ROOT_CLK 290 -#define IMX7D_FLEXTIMER2_ROOT_SRC 291 -#define IMX7D_FLEXTIMER2_ROOT_CG 292 -#define IMX7D_FLEXTIMER2_ROOT_DIV 293 -#define IMX7D_SIM1_ROOT_CLK 294 -#define IMX7D_SIM1_ROOT_SRC 295 -#define IMX7D_SIM1_ROOT_CG 296 -#define IMX7D_SIM1_ROOT_DIV 297 -#define IMX7D_SIM2_ROOT_CLK 298 -#define IMX7D_SIM2_ROOT_SRC 299 -#define IMX7D_SIM2_ROOT_CG 300 -#define IMX7D_SIM2_ROOT_DIV 301 -#define IMX7D_GPT1_ROOT_CLK 302 -#define IMX7D_GPT1_ROOT_SRC 303 -#define IMX7D_GPT1_ROOT_CG 304 -#define IMX7D_GPT1_ROOT_DIV 305 -#define IMX7D_GPT2_ROOT_CLK 306 -#define IMX7D_GPT2_ROOT_SRC 307 -#define IMX7D_GPT2_ROOT_CG 308 -#define IMX7D_GPT2_ROOT_DIV 309 -#define IMX7D_GPT3_ROOT_CLK 310 -#define IMX7D_GPT3_ROOT_SRC 311 -#define IMX7D_GPT3_ROOT_CG 312 -#define IMX7D_GPT3_ROOT_DIV 313 -#define IMX7D_GPT4_ROOT_CLK 314 -#define IMX7D_GPT4_ROOT_SRC 315 -#define IMX7D_GPT4_ROOT_CG 316 -#define IMX7D_GPT4_ROOT_DIV 317 -#define IMX7D_TRACE_ROOT_CLK 318 -#define IMX7D_TRACE_ROOT_SRC 319 -#define IMX7D_TRACE_ROOT_CG 320 -#define IMX7D_TRACE_ROOT_DIV 321 -#define IMX7D_WDOG1_ROOT_CLK 322 -#define IMX7D_WDOG_ROOT_SRC 323 -#define IMX7D_WDOG_ROOT_CG 324 -#define IMX7D_WDOG_ROOT_DIV 325 -#define IMX7D_CSI_MCLK_ROOT_CLK 326 -#define IMX7D_CSI_MCLK_ROOT_SRC 327 -#define IMX7D_CSI_MCLK_ROOT_CG 328 -#define IMX7D_CSI_MCLK_ROOT_DIV 329 -#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 -#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 -#define IMX7D_AUDIO_MCLK_ROOT_CG 332 -#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 -#define IMX7D_WRCLK_ROOT_CLK 334 -#define IMX7D_WRCLK_ROOT_SRC 335 -#define IMX7D_WRCLK_ROOT_CG 336 -#define IMX7D_WRCLK_ROOT_DIV 337 -#define IMX7D_CLKO1_ROOT_SRC 338 -#define IMX7D_CLKO1_ROOT_CG 339 -#define IMX7D_CLKO1_ROOT_DIV 340 -#define IMX7D_CLKO2_ROOT_SRC 341 -#define IMX7D_CLKO2_ROOT_CG 342 -#define IMX7D_CLKO2_ROOT_DIV 343 -#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 -#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 -#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 -#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 -#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 -#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 -#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 -#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 -#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 -#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 -#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 -#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 -#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 -#define IMX7D_SAI1_ROOT_PRE_DIV 357 -#define IMX7D_SAI2_ROOT_PRE_DIV 358 -#define IMX7D_SAI3_ROOT_PRE_DIV 359 -#define IMX7D_SPDIF_ROOT_PRE_DIV 360 -#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 -#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 -#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 -#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 -#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 -#define IMX7D_EIM_ROOT_PRE_DIV 366 -#define IMX7D_NAND_ROOT_PRE_DIV 367 -#define IMX7D_QSPI_ROOT_PRE_DIV 368 -#define IMX7D_USDHC1_ROOT_PRE_DIV 369 -#define IMX7D_USDHC2_ROOT_PRE_DIV 370 -#define IMX7D_USDHC3_ROOT_PRE_DIV 371 -#define IMX7D_CAN1_ROOT_PRE_DIV 372 -#define IMX7D_CAN2_ROOT_PRE_DIV 373 -#define IMX7D_I2C1_ROOT_PRE_DIV 374 -#define IMX7D_I2C2_ROOT_PRE_DIV 375 -#define IMX7D_I2C3_ROOT_PRE_DIV 376 -#define IMX7D_I2C4_ROOT_PRE_DIV 377 -#define IMX7D_UART1_ROOT_PRE_DIV 378 -#define IMX7D_UART2_ROOT_PRE_DIV 379 -#define IMX7D_UART3_ROOT_PRE_DIV 380 -#define IMX7D_UART4_ROOT_PRE_DIV 381 -#define IMX7D_UART5_ROOT_PRE_DIV 382 -#define IMX7D_UART6_ROOT_PRE_DIV 383 -#define IMX7D_UART7_ROOT_PRE_DIV 384 -#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 -#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 -#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 -#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 -#define IMX7D_PWM1_ROOT_PRE_DIV 389 -#define IMX7D_PWM2_ROOT_PRE_DIV 390 -#define IMX7D_PWM3_ROOT_PRE_DIV 391 -#define IMX7D_PWM4_ROOT_PRE_DIV 392 -#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 -#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 -#define IMX7D_SIM1_ROOT_PRE_DIV 395 -#define IMX7D_SIM2_ROOT_PRE_DIV 396 -#define IMX7D_GPT1_ROOT_PRE_DIV 397 -#define IMX7D_GPT2_ROOT_PRE_DIV 398 -#define IMX7D_GPT3_ROOT_PRE_DIV 399 -#define IMX7D_GPT4_ROOT_PRE_DIV 400 -#define IMX7D_TRACE_ROOT_PRE_DIV 401 -#define IMX7D_WDOG_ROOT_PRE_DIV 402 -#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 -#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 -#define IMX7D_WRCLK_ROOT_PRE_DIV 405 -#define IMX7D_CLKO1_ROOT_PRE_DIV 406 -#define IMX7D_CLKO2_ROOT_PRE_DIV 407 -#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 -#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 -#define IMX7D_LVDS1_IN_CLK 410 -#define IMX7D_LVDS1_OUT_SEL 411 -#define IMX7D_LVDS1_OUT_CLK 412 -#define IMX7D_CLK_DUMMY 413 -#define IMX7D_GPT_3M_CLK 414 -#define IMX7D_OCRAM_CLK 415 -#define IMX7D_OCRAM_S_CLK 416 -#define IMX7D_WDOG2_ROOT_CLK 417 -#define IMX7D_WDOG3_ROOT_CLK 418 -#define IMX7D_WDOG4_ROOT_CLK 419 -#define IMX7D_SDMA_CORE_CLK 420 -#define IMX7D_USB1_MAIN_480M_CLK 421 -#define IMX7D_USB_CTRL_CLK 422 -#define IMX7D_USB_PHY1_CLK 423 -#define IMX7D_USB_PHY2_CLK 424 -#define IMX7D_IPG_ROOT_CLK 425 -#define IMX7D_SAI1_IPG_CLK 426 -#define IMX7D_SAI2_IPG_CLK 427 -#define IMX7D_SAI3_IPG_CLK 428 -#define IMX7D_PLL_AUDIO_TEST_DIV 429 -#define IMX7D_PLL_AUDIO_POST_DIV 430 -#define IMX7D_PLL_VIDEO_TEST_DIV 431 -#define IMX7D_PLL_VIDEO_POST_DIV 432 -#define IMX7D_MU_ROOT_CLK 433 -#define IMX7D_SEMA4_HS_ROOT_CLK 434 -#define IMX7D_PLL_DRAM_TEST_DIV 435 -#define IMX7D_ADC_ROOT_CLK 436 -#define IMX7D_CLK_ARM 437 -#define IMX7D_CKIL 438 -#define IMX7D_OCOTP_CLK 439 -#define IMX7D_CLK_END 440 +#define IMX7D_MAIN_AXI_ROOT_CLK 70 +#define IMX7D_MAIN_AXI_ROOT_SRC 71 +#define IMX7D_MAIN_AXI_ROOT_CG 72 +#define IMX7D_MAIN_AXI_ROOT_DIV 73 +#define IMX7D_DISP_AXI_ROOT_CLK 74 +#define IMX7D_DISP_AXI_ROOT_SRC 75 +#define IMX7D_DISP_AXI_ROOT_CG 76 +#define IMX7D_DISP_AXI_ROOT_DIV 77 +#define IMX7D_ENET_AXI_ROOT_CLK 78 +#define IMX7D_ENET_AXI_ROOT_SRC 79 +#define IMX7D_ENET_AXI_ROOT_CG 80 +#define IMX7D_ENET_AXI_ROOT_DIV 81 +#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 82 +#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 83 +#define IMX7D_NAND_USDHC_BUS_ROOT_CG 84 +#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 85 +#define IMX7D_AHB_CHANNEL_ROOT_CLK 86 +#define IMX7D_AHB_CHANNEL_ROOT_SRC 87 +#define IMX7D_AHB_CHANNEL_ROOT_CG 88 +#define IMX7D_AHB_CHANNEL_ROOT_DIV 89 +#define IMX7D_DRAM_PHYM_ROOT_CLK 90 +#define IMX7D_DRAM_PHYM_ROOT_SRC 91 +#define IMX7D_DRAM_PHYM_ROOT_CG 92 +#define IMX7D_DRAM_PHYM_ROOT_DIV 93 +#define IMX7D_DRAM_ROOT_CLK 94 +#define IMX7D_DRAM_ROOT_SRC 95 +#define IMX7D_DRAM_ROOT_CG 96 +#define IMX7D_DRAM_ROOT_DIV 97 +#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 98 +#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 99 +#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 100 +#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 101 +#define IMX7D_DRAM_ALT_ROOT_CLK 102 +#define IMX7D_DRAM_ALT_ROOT_SRC 103 +#define IMX7D_DRAM_ALT_ROOT_CG 104 +#define IMX7D_DRAM_ALT_ROOT_DIV 105 +#define IMX7D_USB_HSIC_ROOT_CLK 106 +#define IMX7D_USB_HSIC_ROOT_SRC 107 +#define IMX7D_USB_HSIC_ROOT_CG 108 +#define IMX7D_USB_HSIC_ROOT_DIV 109 +#define IMX7D_PCIE_CTRL_ROOT_CLK 110 +#define IMX7D_PCIE_CTRL_ROOT_SRC 111 +#define IMX7D_PCIE_CTRL_ROOT_CG 112 +#define IMX7D_PCIE_CTRL_ROOT_DIV 113 +#define IMX7D_PCIE_PHY_ROOT_CLK 114 +#define IMX7D_PCIE_PHY_ROOT_SRC 115 +#define IMX7D_PCIE_PHY_ROOT_CG 116 +#define IMX7D_PCIE_PHY_ROOT_DIV 117 +#define IMX7D_EPDC_PIXEL_ROOT_CLK 118 +#define IMX7D_EPDC_PIXEL_ROOT_SRC 119 +#define IMX7D_EPDC_PIXEL_ROOT_CG 120 +#define IMX7D_EPDC_PIXEL_ROOT_DIV 121 +#define IMX7D_LCDIF_PIXEL_ROOT_CLK 122 +#define IMX7D_LCDIF_PIXEL_ROOT_SRC 123 +#define IMX7D_LCDIF_PIXEL_ROOT_CG 124 +#define IMX7D_LCDIF_PIXEL_ROOT_DIV 125 +#define IMX7D_MIPI_DSI_ROOT_CLK 126 +#define IMX7D_MIPI_DSI_ROOT_SRC 127 +#define IMX7D_MIPI_DSI_ROOT_CG 128 +#define IMX7D_MIPI_DSI_ROOT_DIV 129 +#define IMX7D_MIPI_CSI_ROOT_CLK 130 +#define IMX7D_MIPI_CSI_ROOT_SRC 131 +#define IMX7D_MIPI_CSI_ROOT_CG 132 +#define IMX7D_MIPI_CSI_ROOT_DIV 133 +#define IMX7D_MIPI_DPHY_ROOT_CLK 134 +#define IMX7D_MIPI_DPHY_ROOT_SRC 135 +#define IMX7D_MIPI_DPHY_ROOT_CG 136 +#define IMX7D_MIPI_DPHY_ROOT_DIV 137 +#define IMX7D_SAI1_ROOT_CLK 138 +#define IMX7D_SAI1_ROOT_SRC 139 +#define IMX7D_SAI1_ROOT_CG 140 +#define IMX7D_SAI1_ROOT_DIV 141 +#define IMX7D_SAI2_ROOT_CLK 142 +#define IMX7D_SAI2_ROOT_SRC 143 +#define IMX7D_SAI2_ROOT_CG 144 +#define IMX7D_SAI2_ROOT_DIV 145 +#define IMX7D_SAI3_ROOT_CLK 146 +#define IMX7D_SAI3_ROOT_SRC 147 +#define IMX7D_SAI3_ROOT_CG 148 +#define IMX7D_SAI3_ROOT_DIV 149 +#define IMX7D_SPDIF_ROOT_CLK 150 +#define IMX7D_SPDIF_ROOT_SRC 151 +#define IMX7D_SPDIF_ROOT_CG 152 +#define IMX7D_SPDIF_ROOT_DIV 153 +#define IMX7D_ENET1_REF_ROOT_CLK 154 +#define IMX7D_ENET1_REF_ROOT_SRC 155 +#define IMX7D_ENET1_REF_ROOT_CG 156 +#define IMX7D_ENET1_REF_ROOT_DIV 157 +#define IMX7D_ENET1_TIME_ROOT_CLK 158 +#define IMX7D_ENET1_TIME_ROOT_SRC 159 +#define IMX7D_ENET1_TIME_ROOT_CG 160 +#define IMX7D_ENET1_TIME_ROOT_DIV 161 +#define IMX7D_ENET2_REF_ROOT_CLK 162 +#define IMX7D_ENET2_REF_ROOT_SRC 163 +#define IMX7D_ENET2_REF_ROOT_CG 164 +#define IMX7D_ENET2_REF_ROOT_DIV 165 +#define IMX7D_ENET2_TIME_ROOT_CLK 166 +#define IMX7D_ENET2_TIME_ROOT_SRC 167 +#define IMX7D_ENET2_TIME_ROOT_CG 168 +#define IMX7D_ENET2_TIME_ROOT_DIV 169 +#define IMX7D_ENET_PHY_REF_ROOT_CLK 170 +#define IMX7D_ENET_PHY_REF_ROOT_SRC 171 +#define IMX7D_ENET_PHY_REF_ROOT_CG 172 +#define IMX7D_ENET_PHY_REF_ROOT_DIV 173 +#define IMX7D_EIM_ROOT_CLK 174 +#define IMX7D_EIM_ROOT_SRC 175 +#define IMX7D_EIM_ROOT_CG 176 +#define IMX7D_EIM_ROOT_DIV 177 +#define IMX7D_NAND_ROOT_CLK 178 +#define IMX7D_NAND_ROOT_SRC 179 +#define IMX7D_NAND_ROOT_CG 180 +#define IMX7D_NAND_ROOT_DIV 181 +#define IMX7D_QSPI_ROOT_CLK 182 +#define IMX7D_QSPI_ROOT_SRC 183 +#define IMX7D_QSPI_ROOT_CG 184 +#define IMX7D_QSPI_ROOT_DIV 185 +#define IMX7D_USDHC1_ROOT_CLK 186 +#define IMX7D_USDHC1_ROOT_SRC 187 +#define IMX7D_USDHC1_ROOT_CG 188 +#define IMX7D_USDHC1_ROOT_DIV 189 +#define IMX7D_USDHC2_ROOT_CLK 190 +#define IMX7D_USDHC2_ROOT_SRC 191 +#define IMX7D_USDHC2_ROOT_CG 192 +#define IMX7D_USDHC2_ROOT_DIV 193 +#define IMX7D_USDHC3_ROOT_CLK 194 +#define IMX7D_USDHC3_ROOT_SRC 195 +#define IMX7D_USDHC3_ROOT_CG 196 +#define IMX7D_USDHC3_ROOT_DIV 197 +#define IMX7D_CAN1_ROOT_CLK 198 +#define IMX7D_CAN1_ROOT_SRC 199 +#define IMX7D_CAN1_ROOT_CG 200 +#define IMX7D_CAN1_ROOT_DIV 201 +#define IMX7D_CAN2_ROOT_CLK 202 +#define IMX7D_CAN2_ROOT_SRC 203 +#define IMX7D_CAN2_ROOT_CG 204 +#define IMX7D_CAN2_ROOT_DIV 205 +#define IMX7D_I2C1_ROOT_CLK 206 +#define IMX7D_I2C1_ROOT_SRC 207 +#define IMX7D_I2C1_ROOT_CG 208 +#define IMX7D_I2C1_ROOT_DIV 209 +#define IMX7D_I2C2_ROOT_CLK 210 +#define IMX7D_I2C2_ROOT_SRC 211 +#define IMX7D_I2C2_ROOT_CG 212 +#define IMX7D_I2C2_ROOT_DIV 213 +#define IMX7D_I2C3_ROOT_CLK 214 +#define IMX7D_I2C3_ROOT_SRC 215 +#define IMX7D_I2C3_ROOT_CG 216 +#define IMX7D_I2C3_ROOT_DIV 217 +#define IMX7D_I2C4_ROOT_CLK 218 +#define IMX7D_I2C4_ROOT_SRC 219 +#define IMX7D_I2C4_ROOT_CG 220 +#define IMX7D_I2C4_ROOT_DIV 221 +#define IMX7D_UART1_ROOT_CLK 222 +#define IMX7D_UART1_ROOT_SRC 223 +#define IMX7D_UART1_ROOT_CG 224 +#define IMX7D_UART1_ROOT_DIV 225 +#define IMX7D_UART2_ROOT_CLK 226 +#define IMX7D_UART2_ROOT_SRC 227 +#define IMX7D_UART2_ROOT_CG 228 +#define IMX7D_UART2_ROOT_DIV 229 +#define IMX7D_UART3_ROOT_CLK 230 +#define IMX7D_UART3_ROOT_SRC 231 +#define IMX7D_UART3_ROOT_CG 232 +#define IMX7D_UART3_ROOT_DIV 233 +#define IMX7D_UART4_ROOT_CLK 234 +#define IMX7D_UART4_ROOT_SRC 235 +#define IMX7D_UART4_ROOT_CG 236 +#define IMX7D_UART4_ROOT_DIV 237 +#define IMX7D_UART5_ROOT_CLK 238 +#define IMX7D_UART5_ROOT_SRC 239 +#define IMX7D_UART5_ROOT_CG 240 +#define IMX7D_UART5_ROOT_DIV 241 +#define IMX7D_UART6_ROOT_CLK 242 +#define IMX7D_UART6_ROOT_SRC 243 +#define IMX7D_UART6_ROOT_CG 244 +#define IMX7D_UART6_ROOT_DIV 245 +#define IMX7D_UART7_ROOT_CLK 246 +#define IMX7D_UART7_ROOT_SRC 247 +#define IMX7D_UART7_ROOT_CG 248 +#define IMX7D_UART7_ROOT_DIV 249 +#define IMX7D_ECSPI1_ROOT_CLK 250 +#define IMX7D_ECSPI1_ROOT_SRC 251 +#define IMX7D_ECSPI1_ROOT_CG 252 +#define IMX7D_ECSPI1_ROOT_DIV 253 +#define IMX7D_ECSPI2_ROOT_CLK 254 +#define IMX7D_ECSPI2_ROOT_SRC 255 +#define IMX7D_ECSPI2_ROOT_CG 256 +#define IMX7D_ECSPI2_ROOT_DIV 257 +#define IMX7D_ECSPI3_ROOT_CLK 258 +#define IMX7D_ECSPI3_ROOT_SRC 259 +#define IMX7D_ECSPI3_ROOT_CG 260 +#define IMX7D_ECSPI3_ROOT_DIV 261 +#define IMX7D_ECSPI4_ROOT_CLK 262 +#define IMX7D_ECSPI4_ROOT_SRC 263 +#define IMX7D_ECSPI4_ROOT_CG 264 +#define IMX7D_ECSPI4_ROOT_DIV 265 +#define IMX7D_PWM1_ROOT_CLK 266 +#define IMX7D_PWM1_ROOT_SRC 267 +#define IMX7D_PWM1_ROOT_CG 268 +#define IMX7D_PWM1_ROOT_DIV 269 +#define IMX7D_PWM2_ROOT_CLK 270 +#define IMX7D_PWM2_ROOT_SRC 271 +#define IMX7D_PWM2_ROOT_CG 272 +#define IMX7D_PWM2_ROOT_DIV 273 +#define IMX7D_PWM3_ROOT_CLK 274 +#define IMX7D_PWM3_ROOT_SRC 275 +#define IMX7D_PWM3_ROOT_CG 276 +#define IMX7D_PWM3_ROOT_DIV 277 +#define IMX7D_PWM4_ROOT_CLK 278 +#define IMX7D_PWM4_ROOT_SRC 279 +#define IMX7D_PWM4_ROOT_CG 280 +#define IMX7D_PWM4_ROOT_DIV 281 +#define IMX7D_FLEXTIMER1_ROOT_CLK 282 +#define IMX7D_FLEXTIMER1_ROOT_SRC 283 +#define IMX7D_FLEXTIMER1_ROOT_CG 284 +#define IMX7D_FLEXTIMER1_ROOT_DIV 285 +#define IMX7D_FLEXTIMER2_ROOT_CLK 286 +#define IMX7D_FLEXTIMER2_ROOT_SRC 287 +#define IMX7D_FLEXTIMER2_ROOT_CG 288 +#define IMX7D_FLEXTIMER2_ROOT_DIV 289 +#define IMX7D_SIM1_ROOT_CLK 290 +#define IMX7D_SIM1_ROOT_SRC 291 +#define IMX7D_SIM1_ROOT_CG 292 +#define IMX7D_SIM1_ROOT_DIV 293 +#define IMX7D_SIM2_ROOT_CLK 294 +#define IMX7D_SIM2_ROOT_SRC 295 +#define IMX7D_SIM2_ROOT_CG 296 +#define IMX7D_SIM2_ROOT_DIV 297 +#define IMX7D_GPT1_ROOT_CLK 298 +#define IMX7D_GPT1_ROOT_SRC 299 +#define IMX7D_GPT1_ROOT_CG 300 +#define IMX7D_GPT1_ROOT_DIV 301 +#define IMX7D_GPT2_ROOT_CLK 302 +#define IMX7D_GPT2_ROOT_SRC 303 +#define IMX7D_GPT2_ROOT_CG 304 +#define IMX7D_GPT2_ROOT_DIV 305 +#define IMX7D_GPT3_ROOT_CLK 306 +#define IMX7D_GPT3_ROOT_SRC 307 +#define IMX7D_GPT3_ROOT_CG 308 +#define IMX7D_GPT3_ROOT_DIV 309 +#define IMX7D_GPT4_ROOT_CLK 310 +#define IMX7D_GPT4_ROOT_SRC 311 +#define IMX7D_GPT4_ROOT_CG 312 +#define IMX7D_GPT4_ROOT_DIV 313 +#define IMX7D_TRACE_ROOT_CLK 314 +#define IMX7D_TRACE_ROOT_SRC 315 +#define IMX7D_TRACE_ROOT_CG 316 +#define IMX7D_TRACE_ROOT_DIV 317 +#define IMX7D_WDOG1_ROOT_CLK 318 +#define IMX7D_WDOG_ROOT_SRC 319 +#define IMX7D_WDOG_ROOT_CG 320 +#define IMX7D_WDOG_ROOT_DIV 321 +#define IMX7D_CSI_MCLK_ROOT_CLK 322 +#define IMX7D_CSI_MCLK_ROOT_SRC 323 +#define IMX7D_CSI_MCLK_ROOT_CG 324 +#define IMX7D_CSI_MCLK_ROOT_DIV 325 +#define IMX7D_AUDIO_MCLK_ROOT_CLK 326 +#define IMX7D_AUDIO_MCLK_ROOT_SRC 327 +#define IMX7D_AUDIO_MCLK_ROOT_CG 328 +#define IMX7D_AUDIO_MCLK_ROOT_DIV 329 +#define IMX7D_WRCLK_ROOT_CLK 330 +#define IMX7D_WRCLK_ROOT_SRC 331 +#define IMX7D_WRCLK_ROOT_CG 332 +#define IMX7D_WRCLK_ROOT_DIV 333 +#define IMX7D_CLKO1_ROOT_SRC 334 +#define IMX7D_CLKO1_ROOT_CG 335 +#define IMX7D_CLKO1_ROOT_DIV 336 +#define IMX7D_CLKO2_ROOT_SRC 337 +#define IMX7D_CLKO2_ROOT_CG 338 +#define IMX7D_CLKO2_ROOT_DIV 339 +#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 340 +#define IMX7D_DISP_AXI_ROOT_PRE_DIV 341 +#define IMX7D_ENET_AXI_ROOT_PRE_DIV 342 +#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 343 +#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 344 +#define IMX7D_USB_HSIC_ROOT_PRE_DIV 345 +#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 346 +#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 347 +#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 348 +#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 349 +#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 350 +#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 351 +#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 352 +#define IMX7D_SAI1_ROOT_PRE_DIV 353 +#define IMX7D_SAI2_ROOT_PRE_DIV 354 +#define IMX7D_SAI3_ROOT_PRE_DIV 355 +#define IMX7D_SPDIF_ROOT_PRE_DIV 356 +#define IMX7D_ENET1_REF_ROOT_PRE_DIV 357 +#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 358 +#define IMX7D_ENET2_REF_ROOT_PRE_DIV 359 +#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 360 +#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 361 +#define IMX7D_EIM_ROOT_PRE_DIV 362 +#define IMX7D_NAND_ROOT_PRE_DIV 363 +#define IMX7D_QSPI_ROOT_PRE_DIV 364 +#define IMX7D_USDHC1_ROOT_PRE_DIV 365 +#define IMX7D_USDHC2_ROOT_PRE_DIV 366 +#define IMX7D_USDHC3_ROOT_PRE_DIV 367 +#define IMX7D_CAN1_ROOT_PRE_DIV 368 +#define IMX7D_CAN2_ROOT_PRE_DIV 369 +#define IMX7D_I2C1_ROOT_PRE_DIV 370 +#define IMX7D_I2C2_ROOT_PRE_DIV 371 +#define IMX7D_I2C3_ROOT_PRE_DIV 372 +#define IMX7D_I2C4_ROOT_PRE_DIV 373 +#define IMX7D_UART1_ROOT_PRE_DIV 374 +#define IMX7D_UART2_ROOT_PRE_DIV 375 +#define IMX7D_UART3_ROOT_PRE_DIV 376 +#define IMX7D_UART4_ROOT_PRE_DIV 377 +#define IMX7D_UART5_ROOT_PRE_DIV 378 +#define IMX7D_UART6_ROOT_PRE_DIV 379 +#define IMX7D_UART7_ROOT_PRE_DIV 380 +#define IMX7D_ECSPI1_ROOT_PRE_DIV 381 +#define IMX7D_ECSPI2_ROOT_PRE_DIV 382 +#define IMX7D_ECSPI3_ROOT_PRE_DIV 383 +#define IMX7D_ECSPI4_ROOT_PRE_DIV 384 +#define IMX7D_PWM1_ROOT_PRE_DIV 385 +#define IMX7D_PWM2_ROOT_PRE_DIV 386 +#define IMX7D_PWM3_ROOT_PRE_DIV 387 +#define IMX7D_PWM4_ROOT_PRE_DIV 388 +#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 389 +#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 390 +#define IMX7D_SIM1_ROOT_PRE_DIV 391 +#define IMX7D_SIM2_ROOT_PRE_DIV 392 +#define IMX7D_GPT1_ROOT_PRE_DIV 393 +#define IMX7D_GPT2_ROOT_PRE_DIV 394 +#define IMX7D_GPT3_ROOT_PRE_DIV 395 +#define IMX7D_GPT4_ROOT_PRE_DIV 396 +#define IMX7D_TRACE_ROOT_PRE_DIV 397 +#define IMX7D_WDOG_ROOT_PRE_DIV 398 +#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 399 +#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 400 +#define IMX7D_WRCLK_ROOT_PRE_DIV 401 +#define IMX7D_CLKO1_ROOT_PRE_DIV 402 +#define IMX7D_CLKO2_ROOT_PRE_DIV 403 +#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 404 +#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 405 +#define IMX7D_LVDS1_IN_CLK 406 +#define IMX7D_LVDS1_OUT_SEL 407 +#define IMX7D_LVDS1_OUT_CLK 408 +#define IMX7D_CLK_DUMMY 409 +#define IMX7D_GPT_3M_CLK 410 +#define IMX7D_OCRAM_CLK 411 +#define IMX7D_OCRAM_S_CLK 412 +#define IMX7D_WDOG2_ROOT_CLK 413 +#define IMX7D_WDOG3_ROOT_CLK 414 +#define IMX7D_WDOG4_ROOT_CLK 415 +#define IMX7D_SDMA_CORE_CLK 416 +#define IMX7D_USB1_MAIN_480M_CLK 417 +#define IMX7D_USB_CTRL_CLK 418 +#define IMX7D_USB_PHY1_CLK 419 +#define IMX7D_USB_PHY2_CLK 420 +#define IMX7D_IPG_ROOT_CLK 421 +#define IMX7D_SAI1_IPG_CLK 422 +#define IMX7D_SAI2_IPG_CLK 423 +#define IMX7D_SAI3_IPG_CLK 424 +#define IMX7D_PLL_AUDIO_TEST_DIV 425 +#define IMX7D_PLL_AUDIO_POST_DIV 426 +#define IMX7D_PLL_VIDEO_TEST_DIV 427 +#define IMX7D_PLL_VIDEO_POST_DIV 428 +#define IMX7D_MU_ROOT_CLK 429 +#define IMX7D_SEMA4_HS_ROOT_CLK 430 +#define IMX7D_PLL_DRAM_TEST_DIV 431 +#define IMX7D_ADC_ROOT_CLK 432 +#define IMX7D_CLK_ARM 433 +#define IMX7D_CKIL 434 +#define IMX7D_OCOTP_CLK 435 +#define IMX7D_CAAM_CLK 436 +#define IMX7D_PXP_IPG_CLK 437 +#define IMX7D_PXP_AXI_CLK 438 +#define IMX7D_ENET1_IPG_ROOT_CLK 439 +#define IMX7D_ENET2_IPG_ROOT_CLK 440 +#define IMX7D_NAND_RAWNAND_CLK 441 +#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 442 +#define IMX7D_CLK_END 443 + #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h new file mode 100644 index 00000000000..3533c263871 --- /dev/null +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -0,0 +1,460 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H +#define __DT_BINDINGS_CLOCK_IMX8MM_H + +#define IMX8MM_CLK_DUMMY 0 +#define IMX8MM_CLK_32K 1 +#define IMX8MM_CLK_24M 2 +#define IMX8MM_OSC_HDMI_CLK 3 +#define IMX8MM_CLK_EXT1 4 +#define IMX8MM_CLK_EXT2 5 +#define IMX8MM_CLK_EXT3 6 +#define IMX8MM_CLK_EXT4 7 +#define IMX8MM_AUDIO_PLL1_REF_SEL 8 +#define IMX8MM_AUDIO_PLL2_REF_SEL 9 +#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +#define IMX8MM_DRAM_PLL_REF_SEL 11 +#define IMX8MM_GPU_PLL_REF_SEL 12 +#define IMX8MM_VPU_PLL_REF_SEL 13 +#define IMX8MM_ARM_PLL_REF_SEL 14 +#define IMX8MM_SYS_PLL1_REF_SEL 15 +#define IMX8MM_SYS_PLL2_REF_SEL 16 +#define IMX8MM_SYS_PLL3_REF_SEL 17 +#define IMX8MM_AUDIO_PLL1 18 +#define IMX8MM_AUDIO_PLL2 19 +#define IMX8MM_VIDEO_PLL1 20 +#define IMX8MM_DRAM_PLL 21 +#define IMX8MM_GPU_PLL 22 +#define IMX8MM_VPU_PLL 23 +#define IMX8MM_ARM_PLL 24 +#define IMX8MM_SYS_PLL1 25 +#define IMX8MM_SYS_PLL2 26 +#define IMX8MM_SYS_PLL3 27 +#define IMX8MM_AUDIO_PLL1_BYPASS 28 +#define IMX8MM_AUDIO_PLL2_BYPASS 29 +#define IMX8MM_VIDEO_PLL1_BYPASS 30 +#define IMX8MM_DRAM_PLL_BYPASS 31 +#define IMX8MM_GPU_PLL_BYPASS 32 +#define IMX8MM_VPU_PLL_BYPASS 33 +#define IMX8MM_ARM_PLL_BYPASS 34 +#define IMX8MM_SYS_PLL1_BYPASS 35 +#define IMX8MM_SYS_PLL2_BYPASS 36 +#define IMX8MM_SYS_PLL3_BYPASS 37 +#define IMX8MM_AUDIO_PLL1_OUT 38 +#define IMX8MM_AUDIO_PLL2_OUT 39 +#define IMX8MM_VIDEO_PLL1_OUT 40 +#define IMX8MM_DRAM_PLL_OUT 41 +#define IMX8MM_GPU_PLL_OUT 42 +#define IMX8MM_VPU_PLL_OUT 43 +#define IMX8MM_ARM_PLL_OUT 44 +#define IMX8MM_SYS_PLL1_OUT 45 +#define IMX8MM_SYS_PLL2_OUT 46 +#define IMX8MM_SYS_PLL3_OUT 47 +#define IMX8MM_SYS_PLL1_40M 48 +#define IMX8MM_SYS_PLL1_80M 49 +#define IMX8MM_SYS_PLL1_100M 50 +#define IMX8MM_SYS_PLL1_133M 51 +#define IMX8MM_SYS_PLL1_160M 52 +#define IMX8MM_SYS_PLL1_200M 53 +#define IMX8MM_SYS_PLL1_266M 54 +#define IMX8MM_SYS_PLL1_400M 55 +#define IMX8MM_SYS_PLL1_800M 56 +#define IMX8MM_SYS_PLL2_50M 57 +#define IMX8MM_SYS_PLL2_100M 58 +#define IMX8MM_SYS_PLL2_125M 59 +#define IMX8MM_SYS_PLL2_166M 60 +#define IMX8MM_SYS_PLL2_200M 61 +#define IMX8MM_SYS_PLL2_250M 62 +#define IMX8MM_SYS_PLL2_333M 63 +#define IMX8MM_SYS_PLL2_500M 64 +#define IMX8MM_SYS_PLL2_1000M 65 +#define IMX8MM_CLK_A53_SRC 66 +#define IMX8MM_CLK_M4_SRC 67 +#define IMX8MM_CLK_VPU_SRC 68 +#define IMX8MM_CLK_GPU3D_SRC 69 +#define IMX8MM_CLK_GPU2D_SRC 70 +#define IMX8MM_CLK_A53_CG 71 +#define IMX8MM_CLK_M4_CG 72 +#define IMX8MM_CLK_VPU_CG 73 +#define IMX8MM_CLK_GPU3D_CG 74 +#define IMX8MM_CLK_GPU2D_CG 75 +#define IMX8MM_CLK_A53_DIV 76 +#define IMX8MM_CLK_M4_DIV 77 +#define IMX8MM_CLK_VPU_DIV 78 +#define IMX8MM_CLK_GPU3D_DIV 79 +#define IMX8MM_CLK_GPU2D_DIV 80 +#define IMX8MM_CLK_MAIN_AXI_SRC 81 +#define IMX8MM_CLK_ENET_AXI_SRC 82 +#define IMX8MM_CLK_NAND_USDHC_BUS_SRC 83 +#define IMX8MM_CLK_VPU_BUS_SRC 84 +#define IMX8MM_CLK_DISP_AXI_SRC 85 +#define IMX8MM_CLK_DISP_APB_SRC 86 +#define IMX8MM_CLK_DISP_RTRM_SRC 87 +#define IMX8MM_CLK_USB_BUS_SRC 88 +#define IMX8MM_CLK_GPU_AXI_SRC 89 +#define IMX8MM_CLK_GPU_AHB_SRC 90 +#define IMX8MM_CLK_NOC_SRC 91 +#define IMX8MM_CLK_NOC_APB_SRC 92 +#define IMX8MM_CLK_MAIN_AXI_CG 93 +#define IMX8MM_CLK_ENET_AXI_CG 94 +#define IMX8MM_CLK_NAND_USDHC_BUS_CG 95 +#define IMX8MM_CLK_VPU_BUS_CG 96 +#define IMX8MM_CLK_DISP_AXI_CG 97 +#define IMX8MM_CLK_DISP_APB_CG 98 +#define IMX8MM_CLK_DISP_RTRM_CG 99 +#define IMX8MM_CLK_USB_BUS_CG 100 +#define IMX8MM_CLK_GPU_AXI_CG 101 +#define IMX8MM_CLK_GPU_AHB_CG 102 +#define IMX8MM_CLK_NOC_CG 103 +#define IMX8MM_CLK_NOC_APB_CG 104 +#define IMX8MM_CLK_MAIN_AXI_PRE_DIV 105 +#define IMX8MM_CLK_ENET_AXI_PRE_DIV 106 +#define IMX8MM_CLK_NAND_USDHC_BUS_PRE_DIV 107 +#define IMX8MM_CLK_VPU_BUS_PRE_DIV 108 +#define IMX8MM_CLK_DISP_AXI_PRE_DIV 109 +#define IMX8MM_CLK_DISP_APB_PRE_DIV 110 +#define IMX8MM_CLK_DISP_RTRM_PRE_DIV 111 +#define IMX8MM_CLK_USB_BUS_PRE_DIV 112 +#define IMX8MM_CLK_GPU_AXI_PRE_DIV 113 +#define IMX8MM_CLK_GPU_AHB_PRE_DIV 114 +#define IMX8MM_CLK_NOC_PRE_DIV 115 +#define IMX8MM_CLK_NOC_APB_PRE_DIV 116 +#define IMX8MM_CLK_MAIN_AXI_DIV 117 +#define IMX8MM_CLK_ENET_AXI_DIV 118 +#define IMX8MM_CLK_NAND_USDHC_BUS_DIV 119 +#define IMX8MM_CLK_VPU_BUS_DIV 120 +#define IMX8MM_CLK_DISP_AXI_DIV 121 +#define IMX8MM_CLK_DISP_APB_DIV 122 +#define IMX8MM_CLK_DISP_RTRM_DIV 123 +#define IMX8MM_CLK_USB_BUS_DIV 124 +#define IMX8MM_CLK_GPU_AXI_DIV 125 +#define IMX8MM_CLK_GPU_AHB_DIV 126 +#define IMX8MM_CLK_NOC_DIV 127 +#define IMX8MM_CLK_NOC_APB_DIV 128 +#define IMX8MM_CLK_AHB_SRC 129 +#define IMX8MM_CLK_AUDIO_AHB_SRC 130 +#define IMX8MM_CLK_DSI_ESC_RX_SRC 131 +#define IMX8MM_CLK_AHB_CG 132 +#define IMX8MM_CLK_AUDIO_AHB_CG 133 +#define IMX8MM_CLK_DSI_ESC_RX_CG 134 +#define IMX8MM_CLK_AHB_PRE_DIV 135 +#define IMX8MM_CLK_AUDIO_AHB_PRE_DIV 136 +#define IMX8MM_CLK_DSI_ESC_RX_PRE_DIV 137 +#define IMX8MM_CLK_AHB_DIV 138 +#define IMX8MM_CLK_AUDIO_AHB_DIV 139 +#define IMX8MM_CLK_DSI_ESC_RX_DIV 140 +#define IMX8MM_CLK_IPG_ROOT 141 +#define IMX8MM_CLK_IPG_AUDIO_ROOT 142 +#define IMX8MM_CLK_IPG_DSI_ESC_RX_ROOT 143 +#define IMX8MM_CLK_DRAM_ALT_SRC 144 +#define IMX8MM_CLK_DRAM_APB_SRC 145 +#define IMX8MM_CLK_VPU_G1_SRC 146 +#define IMX8MM_CLK_VPU_G2_SRC 147 +#define IMX8MM_CLK_DISP_DTRC_SRC 148 +#define IMX8MM_CLK_DISP_DC8000_SRC 149 +#define IMX8MM_CLK_PCIE1_CTRL_SRC 150 +#define IMX8MM_CLK_PCIE1_PHY_SRC 151 +#define IMX8MM_CLK_PCIE1_AUX_SRC 152 +#define IMX8MM_CLK_DC_PIXEL_SRC 153 +#define IMX8MM_CLK_LCDIF_PIXEL_SRC 154 +#define IMX8MM_CLK_SAI1_SRC 155 +#define IMX8MM_CLK_SAI2_SRC 156 +#define IMX8MM_CLK_SAI3_SRC 157 +#define IMX8MM_CLK_SAI4_SRC 158 +#define IMX8MM_CLK_SAI5_SRC 159 +#define IMX8MM_CLK_SAI6_SRC 160 +#define IMX8MM_CLK_SPDIF1_SRC 161 +#define IMX8MM_CLK_SPDIF2_SRC 162 +#define IMX8MM_CLK_ENET_REF_SRC 163 +#define IMX8MM_CLK_ENET_TIMER_SRC 164 +#define IMX8MM_CLK_ENET_PHY_REF_SRC 165 +#define IMX8MM_CLK_NAND_SRC 166 +#define IMX8MM_CLK_QSPI_SRC 167 +#define IMX8MM_CLK_USDHC1_SRC 168 +#define IMX8MM_CLK_USDHC2_SRC 169 +#define IMX8MM_CLK_I2C1_SRC 170 +#define IMX8MM_CLK_I2C2_SRC 171 +#define IMX8MM_CLK_I2C3_SRC 172 +#define IMX8MM_CLK_I2C4_SRC 173 +#define IMX8MM_CLK_UART1_SRC 174 +#define IMX8MM_CLK_UART2_SRC 175 +#define IMX8MM_CLK_UART3_SRC 176 +#define IMX8MM_CLK_UART4_SRC 177 +#define IMX8MM_CLK_USB_CORE_REF_SRC 178 +#define IMX8MM_CLK_USB_PHY_REF_SRC 179 +#define IMX8MM_CLK_ECSPI1_SRC 180 +#define IMX8MM_CLK_ECSPI2_SRC 181 +#define IMX8MM_CLK_PWM1_SRC 182 +#define IMX8MM_CLK_PWM2_SRC 183 +#define IMX8MM_CLK_PWM3_SRC 184 +#define IMX8MM_CLK_PWM4_SRC 185 +#define IMX8MM_CLK_GPT1_SRC 186 +#define IMX8MM_CLK_WDOG_SRC 187 +#define IMX8MM_CLK_WRCLK_SRC 188 +#define IMX8MM_CLK_DSI_CORE_SRC 189 +#define IMX8MM_CLK_DSI_PHY_REF_SRC 190 +#define IMX8MM_CLK_DSI_DBI_SRC 191 +#define IMX8MM_CLK_USDHC3_SRC 192 +#define IMX8MM_CLK_CSI1_CORE_SRC 193 +#define IMX8MM_CLK_CSI1_PHY_REF_SRC 194 +#define IMX8MM_CLK_CSI1_ESC_SRC 195 +#define IMX8MM_CLK_CSI2_CORE_SRC 196 +#define IMX8MM_CLK_CSI2_PHY_REF_SRC 197 +#define IMX8MM_CLK_CSI2_ESC_SRC 198 +#define IMX8MM_CLK_PCIE2_CTRL_SRC 199 +#define IMX8MM_CLK_PCIE2_PHY_SRC 200 +#define IMX8MM_CLK_PCIE2_AUX_SRC 201 +#define IMX8MM_CLK_ECSPI3_SRC 202 +#define IMX8MM_CLK_PDM_SRC 203 +#define IMX8MM_CLK_VPU_H1_SRC 204 +#define IMX8MM_CLK_DRAM_ALT_CG 205 +#define IMX8MM_CLK_DRAM_APB_CG 206 +#define IMX8MM_CLK_VPU_G1_CG 207 +#define IMX8MM_CLK_VPU_G2_CG 208 +#define IMX8MM_CLK_DISP_DTRC_CG 209 +#define IMX8MM_CLK_DISP_DC8000_CG 210 +#define IMX8MM_CLK_PCIE1_CTRL_CG 211 +#define IMX8MM_CLK_PCIE1_PHY_CG 212 +#define IMX8MM_CLK_PCIE1_AUX_CG 213 +#define IMX8MM_CLK_DC_PIXEL_CG 214 +#define IMX8MM_CLK_LCDIF_PIXEL_CG 215 +#define IMX8MM_CLK_SAI1_CG 216 +#define IMX8MM_CLK_SAI2_CG 217 +#define IMX8MM_CLK_SAI3_CG 218 +#define IMX8MM_CLK_SAI4_CG 219 +#define IMX8MM_CLK_SAI5_CG 220 +#define IMX8MM_CLK_SAI6_CG 221 +#define IMX8MM_CLK_SPDIF1_CG 222 +#define IMX8MM_CLK_SPDIF2_CG 223 +#define IMX8MM_CLK_ENET_REF_CG 224 +#define IMX8MM_CLK_ENET_TIMER_CG 225 +#define IMX8MM_CLK_ENET_PHY_REF_CG 226 +#define IMX8MM_CLK_NAND_CG 227 +#define IMX8MM_CLK_QSPI_CG 228 +#define IMX8MM_CLK_USDHC1_CG 229 +#define IMX8MM_CLK_USDHC2_CG 230 +#define IMX8MM_CLK_I2C1_CG 231 +#define IMX8MM_CLK_I2C2_CG 232 +#define IMX8MM_CLK_I2C3_CG 233 +#define IMX8MM_CLK_I2C4_CG 234 +#define IMX8MM_CLK_UART1_CG 235 +#define IMX8MM_CLK_UART2_CG 236 +#define IMX8MM_CLK_UART3_CG 237 +#define IMX8MM_CLK_UART4_CG 238 +#define IMX8MM_CLK_USB_CORE_REF_CG 239 +#define IMX8MM_CLK_USB_PHY_REF_CG 240 +#define IMX8MM_CLK_ECSPI1_CG 241 +#define IMX8MM_CLK_ECSPI2_CG 242 +#define IMX8MM_CLK_PWM1_CG 243 +#define IMX8MM_CLK_PWM2_CG 244 +#define IMX8MM_CLK_PWM3_CG 245 +#define IMX8MM_CLK_PWM4_CG 246 +#define IMX8MM_CLK_GPT1_CG 247 +#define IMX8MM_CLK_WDOG_CG 248 +#define IMX8MM_CLK_WRCLK_CG 249 +#define IMX8MM_CLK_DSI_CORE_CG 250 +#define IMX8MM_CLK_DSI_PHY_REF_CG 251 +#define IMX8MM_CLK_DSI_DBI_CG 252 +#define IMX8MM_CLK_USDHC3_CG 253 +#define IMX8MM_CLK_CSI1_CORE_CG 254 +#define IMX8MM_CLK_CSI1_PHY_REF_CG 255 +#define IMX8MM_CLK_CSI1_ESC_CG 256 +#define IMX8MM_CLK_CSI2_CORE_CG 257 +#define IMX8MM_CLK_CSI2_PHY_REF_CG 258 +#define IMX8MM_CLK_CSI2_ESC_CG 259 +#define IMX8MM_CLK_PCIE2_CTRL_CG 260 +#define IMX8MM_CLK_PCIE2_PHY_CG 261 +#define IMX8MM_CLK_PCIE2_AUX_CG 262 +#define IMX8MM_CLK_ECSPI3_CG 263 +#define IMX8MM_CLK_PDM_CG 264 +#define IMX8MM_CLK_VPU_H1_CG 265 +#define IMX8MM_CLK_DRAM_ALT_PRE_DIV 266 +#define IMX8MM_CLK_DRAM_APB_PRE_DIV 267 +#define IMX8MM_CLK_VPU_G1_PRE_DIV 268 +#define IMX8MM_CLK_VPU_G2_PRE_DIV 269 +#define IMX8MM_CLK_DISP_DTRC_PRE_DIV 270 +#define IMX8MM_CLK_DISP_DC8000_PRE_DIV 271 +#define IMX8MM_CLK_PCIE1_CTRL_PRE_DIV 272 +#define IMX8MM_CLK_PCIE1_PHY_PRE_DIV 273 +#define IMX8MM_CLK_PCIE1_AUX_PRE_DIV 274 +#define IMX8MM_CLK_DC_PIXEL_PRE_DIV 275 +#define IMX8MM_CLK_LCDIF_PIXEL_PRE_DIV 276 +#define IMX8MM_CLK_SAI1_PRE_DIV 277 +#define IMX8MM_CLK_SAI2_PRE_DIV 278 +#define IMX8MM_CLK_SAI3_PRE_DIV 279 +#define IMX8MM_CLK_SAI4_PRE_DIV 280 +#define IMX8MM_CLK_SAI5_PRE_DIV 281 +#define IMX8MM_CLK_SAI6_PRE_DIV 282 +#define IMX8MM_CLK_SPDIF1_PRE_DIV 283 +#define IMX8MM_CLK_SPDIF2_PRE_DIV 284 +#define IMX8MM_CLK_ENET_REF_PRE_DIV 285 +#define IMX8MM_CLK_ENET_TIMER_PRE_DIV 286 +#define IMX8MM_CLK_ENET_PHY_REF_PRE_DIV 287 +#define IMX8MM_CLK_NAND_PRE_DIV 288 +#define IMX8MM_CLK_QSPI_PRE_DIV 289 +#define IMX8MM_CLK_USDHC1_PRE_DIV 290 +#define IMX8MM_CLK_USDHC2_PRE_DIV 291 +#define IMX8MM_CLK_I2C1_PRE_DIV 292 +#define IMX8MM_CLK_I2C2_PRE_DIV 293 +#define IMX8MM_CLK_I2C3_PRE_DIV 294 +#define IMX8MM_CLK_I2C4_PRE_DIV 295 +#define IMX8MM_CLK_UART1_PRE_DIV 296 +#define IMX8MM_CLK_UART2_PRE_DIV 297 +#define IMX8MM_CLK_UART3_PRE_DIV 298 +#define IMX8MM_CLK_UART4_PRE_DIV 299 +#define IMX8MM_CLK_USB_CORE_REF_PRE_DIV 300 +#define IMX8MM_CLK_USB_PHY_REF_PRE_DIV 301 +#define IMX8MM_CLK_ECSPI1_PRE_DIV 302 +#define IMX8MM_CLK_ECSPI2_PRE_DIV 303 +#define IMX8MM_CLK_PWM1_PRE_DIV 304 +#define IMX8MM_CLK_PWM2_PRE_DIV 305 +#define IMX8MM_CLK_PWM3_PRE_DIV 306 +#define IMX8MM_CLK_PWM4_PRE_DIV 307 +#define IMX8MM_CLK_GPT1_PRE_DIV 308 +#define IMX8MM_CLK_WDOG_PRE_DIV 309 +#define IMX8MM_CLK_WRCLK_PRE_DIV 310 +#define IMX8MM_CLK_DSI_CORE_PRE_DIV 311 +#define IMX8MM_CLK_DSI_PHY_REF_PRE_DIV 312 +#define IMX8MM_CLK_DSI_DBI_PRE_DIV 313 +#define IMX8MM_CLK_USDHC3_PRE_DIV 314 +#define IMX8MM_CLK_CSI1_CORE_PRE_DIV 315 +#define IMX8MM_CLK_CSI1_PHY_REF_PRE_DIV 316 +#define IMX8MM_CLK_CSI1_ESC_PRE_DIV 317 +#define IMX8MM_CLK_CSI2_CORE_PRE_DIV 318 +#define IMX8MM_CLK_CSI2_PHY_REF_PRE_DIV 319 +#define IMX8MM_CLK_CSI2_ESC_PRE_DIV 320 +#define IMX8MM_CLK_PCIE2_CTRL_PRE_DIV 321 +#define IMX8MM_CLK_PCIE2_PHY_PRE_DIV 322 +#define IMX8MM_CLK_PCIE2_AUX_PRE_DIV 323 +#define IMX8MM_CLK_ECSPI3_PRE_DIV 324 +#define IMX8MM_CLK_PDM_PRE_DIV 325 +#define IMX8MM_CLK_VPU_H1_PRE_DIV 326 +#define IMX8MM_CLK_DRAM_ALT_DIV 327 +#define IMX8MM_CLK_DRAM_APB_DIV 328 +#define IMX8MM_CLK_VPU_G1_DIV 329 +#define IMX8MM_CLK_VPU_G2_DIV 330 +#define IMX8MM_CLK_DISP_DTRC_DIV 331 +#define IMX8MM_CLK_DISP_DC8000_DIV 332 +#define IMX8MM_CLK_PCIE1_CTRL_DIV 333 +#define IMX8MM_CLK_PCIE1_PHY_DIV 334 +#define IMX8MM_CLK_PCIE1_AUX_DIV 335 +#define IMX8MM_CLK_DC_PIXEL_DIV 336 +#define IMX8MM_CLK_LCDIF_PIXEL_DIV 337 +#define IMX8MM_CLK_SAI1_DIV 338 +#define IMX8MM_CLK_SAI2_DIV 339 +#define IMX8MM_CLK_SAI3_DIV 340 +#define IMX8MM_CLK_SAI4_DIV 341 +#define IMX8MM_CLK_SAI5_DIV 342 +#define IMX8MM_CLK_SAI6_DIV 343 +#define IMX8MM_CLK_SPDIF1_DIV 344 +#define IMX8MM_CLK_SPDIF2_DIV 345 +#define IMX8MM_CLK_ENET_REF_DIV 346 +#define IMX8MM_CLK_ENET_TIMER_DIV 347 +#define IMX8MM_CLK_ENET_PHY_REF_DIV 348 +#define IMX8MM_CLK_NAND_DIV 349 +#define IMX8MM_CLK_QSPI_DIV 350 +#define IMX8MM_CLK_USDHC1_DIV 351 +#define IMX8MM_CLK_USDHC2_DIV 352 +#define IMX8MM_CLK_I2C1_DIV 353 +#define IMX8MM_CLK_I2C2_DIV 354 +#define IMX8MM_CLK_I2C3_DIV 355 +#define IMX8MM_CLK_I2C4_DIV 356 +#define IMX8MM_CLK_UART1_DIV 357 +#define IMX8MM_CLK_UART2_DIV 358 +#define IMX8MM_CLK_UART3_DIV 359 +#define IMX8MM_CLK_UART4_DIV 360 +#define IMX8MM_CLK_USB_CORE_REF_DIV 361 +#define IMX8MM_CLK_USB_PHY_REF_DIV 362 +#define IMX8MM_CLK_ECSPI1_DIV 363 +#define IMX8MM_CLK_ECSPI2_DIV 364 +#define IMX8MM_CLK_PWM1_DIV 365 +#define IMX8MM_CLK_PWM2_DIV 366 +#define IMX8MM_CLK_PWM3_DIV 367 +#define IMX8MM_CLK_PWM4_DIV 368 +#define IMX8MM_CLK_GPT1_DIV 369 +#define IMX8MM_CLK_WDOG_DIV 370 +#define IMX8MM_CLK_WRCLK_DIV 371 +#define IMX8MM_CLK_DSI_CORE_DIV 372 +#define IMX8MM_CLK_DSI_PHY_REF_DIV 373 +#define IMX8MM_CLK_DSI_DBI_DIV 374 +#define IMX8MM_CLK_USDHC3_DIV 375 +#define IMX8MM_CLK_CSI1_CORE_DIV 376 +#define IMX8MM_CLK_CSI1_PHY_REF_DIV 377 +#define IMX8MM_CLK_CSI1_ESC_DIV 378 +#define IMX8MM_CLK_CSI2_CORE_DIV 379 +#define IMX8MM_CLK_CSI2_PHY_REF_DIV 380 +#define IMX8MM_CLK_CSI2_ESC_DIV 381 +#define IMX8MM_CLK_PCIE2_CTRL_DIV 382 +#define IMX8MM_CLK_PCIE2_PHY_DIV 383 +#define IMX8MM_CLK_PCIE2_AUX_DIV 384 +#define IMX8MM_CLK_ECSPI3_DIV 385 +#define IMX8MM_CLK_PDM_DIV 386 +#define IMX8MM_CLK_VPU_H1_DIV 387 +#define IMX8MM_CLK_ECSPI1_ROOT 388 +#define IMX8MM_CLK_ECSPI2_ROOT 389 +#define IMX8MM_CLK_ECSPI3_ROOT 390 +#define IMX8MM_CLK_ENET1_ROOT 391 +#define IMX8MM_CLK_GPT1_ROOT 392 +#define IMX8MM_CLK_I2C1_ROOT 393 +#define IMX8MM_CLK_I2C2_ROOT 394 +#define IMX8MM_CLK_I2C3_ROOT 395 +#define IMX8MM_CLK_I2C4_ROOT 396 +#define IMX8MM_CLK_OCOTP_ROOT 397 +#define IMX8MM_CLK_PCIE1_ROOT 398 +#define IMX8MM_CLK_PWM1_ROOT 399 +#define IMX8MM_CLK_PWM2_ROOT 400 +#define IMX8MM_CLK_PWM3_ROOT 401 +#define IMX8MM_CLK_PWM4_ROOT 402 +#define IMX8MM_CLK_QSPI_ROOT 403 +#define IMX8MM_CLK_NAND_ROOT 404 +#define IMX8MM_CLK_SAI1_ROOT 405 +#define IMX8MM_CLK_SAI1_IPG 406 +#define IMX8MM_CLK_SAI2_ROOT 407 +#define IMX8MM_CLK_SAI2_IPG 408 +#define IMX8MM_CLK_SAI3_ROOT 409 +#define IMX8MM_CLK_SAI3_IPG 410 +#define IMX8MM_CLK_SAI4_ROOT 411 +#define IMX8MM_CLK_SAI4_IPG 412 +#define IMX8MM_CLK_SAI5_ROOT 413 +#define IMX8MM_CLK_SAI5_IPG 414 +#define IMX8MM_CLK_SAI6_ROOT 415 +#define IMX8MM_CLK_SAI6_IPG 416 +#define IMX8MM_CLK_UART1_ROOT 417 +#define IMX8MM_CLK_UART2_ROOT 418 +#define IMX8MM_CLK_UART3_ROOT 419 +#define IMX8MM_CLK_UART4_ROOT 420 +#define IMX8MM_CLK_USB1_CTRL_ROOT 421 +#define IMX8MM_CLK_GPU3D_ROOT 422 +#define IMX8MM_CLK_USDHC1_ROOT 423 +#define IMX8MM_CLK_USDHC2_ROOT 424 +#define IMX8MM_CLK_WDOG1_ROOT 425 +#define IMX8MM_CLK_WDOG2_ROOT 426 +#define IMX8MM_CLK_WDOG3_ROOT 427 +#define IMX8MM_CLK_VPU_G1_ROOT 428 +#define IMX8MM_CLK_GPU_ROOT 429 +#define IMX8MM_CLK_VPU_H1_ROOT 430 +#define IMX8MM_CLK_VPU_G2_ROOT 431 +#define IMX8MM_CLK_PDM_ROOT 432 +#define IMX8MM_CLK_DISP_ROOT 433 +#define IMX8MM_CLK_DISP_AXI_ROOT 434 +#define IMX8MM_CLK_DISP_APB_ROOT 435 +#define IMX8MM_CLK_DISP_RTRM_ROOT 436 +#define IMX8MM_CLK_USDHC3_ROOT 437 +#define IMX8MM_CLK_TMU_ROOT 438 +#define IMX8MM_CLK_VPU_DEC_ROOT 439 +#define IMX8MM_CLK_SDMA1_ROOT 440 +#define IMX8MM_CLK_SDMA2_ROOT 441 +#define IMX8MM_CLK_SDMA3_ROOT 442 +#define IMX8MM_CLK_GPT_3M 443 +#define IMX8MM_CLK_ARM 444 +#define IMX8MM_CLK_PDM_IPG 445 + +#define IMX8MM_CLK_END 446 +#endif diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h new file mode 100644 index 00000000000..7360e312560 --- /dev/null +++ b/include/dt-bindings/clock/imx8qm-clock.h @@ -0,0 +1,816 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H +#define __DT_BINDINGS_CLOCK_IMX8QM_H + +#define IMX8QM_CLK_DUMMY 0 + +#define IMX8QM_A53_DIV 1 +#define IMX8QM_A53_CLK 2 +#define IMX8QM_A72_DIV 3 +#define IMX8QM_A72_CLK 4 + +/* SC Clocks. */ +#define IMX8QM_SC_I2C_DIV 5 +#define IMX8QM_SC_I2C_CLK 6 +#define IMX8QM_SC_PID0_DIV 7 +#define IMX8QM_SC_PID0_CLK 8 +#define IMX8QM_SC_PIT_DIV 9 +#define IMX8QM_SC_PIT_CLK 10 +#define IMX8QM_SC_TPM_DIV 11 +#define IMX8QM_SC_TPM_CLK 12 +#define IMX8QM_SC_UART_DIV 13 +#define IMX8QM_SC_UART_CLK 14 + +/* LSIO */ +#define IMX8QM_PWM0_DIV 15 +#define IMX8QM_PWM0_CLK 16 +#define IMX8QM_PWM1_DIV 17 +#define IMX8QM_PWM1_CLK 18 +#define IMX8QM_PWM2_DIV 19 +#define IMX8QM_PWM2_CLK 20 +#define IMX8QM_PWM3_DIV 21 +#define IMX8QM_PWM3_CLK 22 +#define IMX8QM_PWM4_DIV 23 +#define IMX8QM_PWM4_CLK 24 +#define IMX8QM_PWM5_DIV 26 +#define IMX8QM_PWM5_CLK 27 +#define IMX8QM_PWM6_DIV 28 +#define IMX8QM_PWM6_CLK 29 +#define IMX8QM_PWM7_DIV 30 +#define IMX8QM_PWM7_CLK 31 +#define IMX8QM_FSPI0_DIV 32 +#define IMX8QM_FSPI0_CLK 33 +#define IMX8QM_FSPI1_DIV 34 +#define IMX8QM_FSPI1_CLK 35 +#define IMX8QM_GPT0_DIV 36 +#define IMX8QM_GPT0_CLK 37 +#define IMX8QM_GPT1_DIV 38 +#define IMX8QM_GPT1_CLK 39 +#define IMX8QM_GPT2_DIV 40 +#define IMX8QM_GPT2_CLK 41 +#define IMX8QM_GPT3_DIV 42 +#define IMX8QM_GPT3_CLK 43 +#define IMX8QM_GPT4_DIV 44 +#define IMX8QM_GPT4_CLK 45 + +/* Connectivity */ +#define IMX8QM_APBHDMA_CLK 46 +#define IMX8QM_GPMI_APB_CLK 47 +#define IMX8QM_GPMI_APB_BCH_CLK 48 +#define IMX8QM_GPMI_BCH_IO_DIV 49 +#define IMX8QM_GPMI_BCH_IO_CLK 50 +#define IMX8QM_GPMI_BCH_DIV 51 +#define IMX8QM_GPMI_BCH_CLK 52 +#define IMX8QM_SDHC0_IPG_CLK 53 +#define IMX8QM_SDHC0_DIV 54 +#define IMX8QM_SDHC0_CLK 55 +#define IMX8QM_SDHC1_IPG_CLK 56 +#define IMX8QM_SDHC1_DIV 57 +#define IMX8QM_SDHC1_CLK 58 +#define IMX8QM_SDHC2_IPG_CLK 59 +#define IMX8QM_SDHC2_DIV 60 +#define IMX8QM_SDHC2_CLK 61 +#define IMX8QM_USB2_OH_AHB_CLK 62 +#define IMX8QM_USB2_OH_IPG_S_CLK 63 +#define IMX8QM_USB2_OH_IPG_S_PL301_CLK 64 +#define IMX8QM_USB2_PHY_IPG_CLK 65 +#define IMX8QM_USB3_IPG_CLK 66 +#define IMX8QM_USB3_CORE_PCLK 67 +#define IMX8QM_USB3_PHY_CLK 68 +#define IMX8QM_USB3_ACLK_DIV 69 +#define IMX8QM_USB3_ACLK 70 +#define IMX8QM_USB3_BUS_DIV 71 +#define IMX8QM_USB3_BUS_CLK 72 +#define IMX8QM_USB3_LPM_DIV 73 +#define IMX8QM_USB3_LPM_CLK 74 +#define IMX8QM_ENET0_AHB_CLK 75 +#define IMX8QM_ENET0_IPG_S_CLK 76 +#define IMX8QM_ENET0_IPG_CLK 77 +#define IMX8QM_ENET0_RGMII_DIV 78 +#define IMX8QM_ENET0_RGMII_TX_CLK 79 +#define IMX8QM_ENET0_ROOT_DIV 80 +#define IMX8QM_ENET0_TX_CLK 81 +#define IMX8QM_ENET0_ROOT_CLK 82 +#define IMX8QM_ENET0_PTP_CLK 83 +#define IMX8QM_ENET0_BYPASS_DIV 84 +#define IMX8QM_ENET1_AHB_CLK 85 +#define IMX8QM_ENET1_IPG_S_CLK 86 +#define IMX8QM_ENET1_IPG_CLK 87 +#define IMX8QM_ENET1_RGMII_DIV 88 +#define IMX8QM_ENET1_RGMII_TX_CLK 89 +#define IMX8QM_ENET1_ROOT_DIV 90 +#define IMX8QM_ENET1_TX_CLK 91 +#define IMX8QM_ENET1_ROOT_CLK 92 +#define IMX8QM_ENET1_PTP_CLK 93 +#define IMX8QM_ENET1_BYPASS_DIV 94 +#define IMX8QM_MLB_CLK 95 +#define IMX8QM_MLB_HCLK 96 +#define IMX8QM_MLB_IPG_CLK 97 +#define IMX8QM_EDMA_CLK 98 +#define IMX8QM_EDMA_IPG_CLK 99 + +/* DMA */ +#define IMX8QM_SPI0_IPG_CLK 100 +#define IMX8QM_SPI0_DIV 101 +#define IMX8QM_SPI0_CLK 102 +#define IMX8QM_SPI1_IPG_CLK 103 +#define IMX8QM_SPI1_DIV 104 +#define IMX8QM_SPI1_CLK 105 +#define IMX8QM_SPI2_IPG_CLK 106 +#define IMX8QM_SPI2_DIV 107 +#define IMX8QM_SPI2_CLK 108 +#define IMX8QM_SPI3_IPG_CLK 109 +#define IMX8QM_SPI3_DIV 110 +#define IMX8QM_SPI3_CLK 111 +#define IMX8QM_UART0_IPG_CLK 112 +#define IMX8QM_UART0_DIV 113 +#define IMX8QM_UART0_CLK 114 +#define IMX8QM_UART1_IPG_CLK 115 +#define IMX8QM_UART1_DIV 116 +#define IMX8QM_UART1_CLK 117 +#define IMX8QM_UART2_IPG_CLK 118 +#define IMX8QM_UART2_DIV 119 +#define IMX8QM_UART2_CLK 120 +#define IMX8QM_UART3_IPG_CLK 121 +#define IMX8QM_UART3_DIV 122 +#define IMX8QM_UART3_CLK 123 +#define IMX8QM_UART4_IPG_CLK 124 +#define IMX8QM_UART4_DIV 125 +#define IMX8QM_EMVSIM0_IPG_CLK 126 +#define IMX8QM_UART4_CLK 127 +#define IMX8QM_EMVSIM0_DIV 128 +#define IMX8QM_EMVSIM0_CLK 129 +#define IMX8QM_EMVSIM1_IPG_CLK 130 +#define IMX8QM_EMVSIM1_DIV 131 +#define IMX8QM_EMVSIM1_CLK 132 +#define IMX8QM_CAN0_IPG_CHI_CLK 133 +#define IMX8QM_CAN0_IPG_CLK 134 +#define IMX8QM_CAN0_DIV 135 +#define IMX8QM_CAN0_CLK 136 +#define IMX8QM_CAN1_IPG_CHI_CLK 137 +#define IMX8QM_CAN1_IPG_CLK 138 +#define IMX8QM_CAN1_DIV 139 +#define IMX8QM_CAN1_CLK 140 +#define IMX8QM_CAN2_IPG_CHI_CLK 141 +#define IMX8QM_CAN2_IPG_CLK 142 +#define IMX8QM_CAN2_DIV 143 +#define IMX8QM_CAN2_CLK 144 +#define IMX8QM_I2C0_IPG_CLK 145 +#define IMX8QM_I2C0_DIV 146 +#define IMX8QM_I2C0_CLK 147 +#define IMX8QM_I2C1_IPG_CLK 148 +#define IMX8QM_I2C1_DIV 149 +#define IMX8QM_I2C1_CLK 150 +#define IMX8QM_I2C2_IPG_CLK 151 +#define IMX8QM_I2C2_DIV 152 +#define IMX8QM_I2C2_CLK 153 +#define IMX8QM_I2C3_IPG_CLK 154 +#define IMX8QM_I2C3_DIV 155 +#define IMX8QM_I2C3_CLK 156 +#define IMX8QM_I2C4_IPG_CLK 157 +#define IMX8QM_I2C4_DIV 158 +#define IMX8QM_I2C4_CLK 159 +#define IMX8QM_FTM0_IPG_CLK 160 +#define IMX8QM_FTM0_DIV 161 +#define IMX8QM_FTM0_CLK 162 +#define IMX8QM_FTM1_IPG_CLK 163 +#define IMX8QM_FTM1_DIV 164 +#define IMX8QM_FTM1_CLK 165 +#define IMX8QM_ADC0_IPG_CLK 166 +#define IMX8QM_ADC0_DIV 167 +#define IMX8QM_ADC0_CLK 168 +#define IMX8QM_ADC1_IPG_CLK 169 +#define IMX8QM_ADC1_DIV 170 +#define IMX8QM_ADC1_CLK 171 + +/* Audio */ +#define IMX8QM_AUD_PLL0_DIV 172 +#define IMX8QM_AUD_PLL0 173 +#define IMX8QM_AUD_PLL1_DIV 174 +#define IMX8QM_AUD_PLL1 175 +#define IMX8QM_AUD_AMIX_IPG 182 +#define IMX8QM_AUD_ESAI_0_IPG 183 +#define IMX8QM_AUD_ESAI_1_IPG 184 +#define IMX8QM_AUD_ESAI_0_EXTAL_IPG 185 +#define IMX8QM_AUD_ESAI_1_EXTAL_IPG 186 +#define IMX8QM_AUD_SAI_0_IPG 187 +#define IMX8QM_AUD_SAI_0_IPG_S 188 +#define IMX8QM_AUD_SAI_0_MCLK 189 +#define IMX8QM_AUD_SAI_1_IPG 190 +#define IMX8QM_AUD_SAI_1_IPG_S 191 +#define IMX8QM_AUD_SAI_1_MCLK 192 +#define IMX8QM_AUD_SAI_2_IPG 193 +#define IMX8QM_AUD_SAI_2_IPG_S 194 +#define IMX8QM_AUD_SAI_2_MCLK 195 +#define IMX8QM_AUD_SAI_3_IPG 196 +#define IMX8QM_AUD_SAI_3_IPG_S 197 +#define IMX8QM_AUD_SAI_3_MCLK 198 +#define IMX8QM_AUD_SAI_6_IPG 199 +#define IMX8QM_AUD_SAI_6_IPG_S 200 +#define IMX8QM_AUD_SAI_6_MCLK 201 +#define IMX8QM_AUD_SAI_7_IPG 202 +#define IMX8QM_AUD_SAI_7_IPG_S 203 +#define IMX8QM_AUD_SAI_7_MCLK 204 +#define IMX8QM_AUD_SAI_HDMIRX0_IPG 205 +#define IMX8QM_AUD_SAI_HDMIRX0_IPG_S 206 +#define IMX8QM_AUD_SAI_HDMIRX0_MCLK 207 +#define IMX8QM_AUD_SAI_HDMITX0_IPG 208 +#define IMX8QM_AUD_SAI_HDMITX0_IPG_S 209 +#define IMX8QM_AUD_SAI_HDMITX0_MCLK 210 +#define IMX8QM_AUD_MQS_IPG 211 +#define IMX8QM_AUD_MQS_HMCLK 212 +#define IMX8QM_AUD_GPT5_IPG_S 213 +#define IMX8QM_AUD_GPT5_CLKIN 214 +#define IMX8QM_AUD_GPT5_24M_CLK 215 +#define IMX8QM_AUD_GPT6_IPG_S 216 +#define IMX8QM_AUD_GPT6_CLKIN 217 +#define IMX8QM_AUD_GPT6_24M_CLK 218 +#define IMX8QM_AUD_GPT7_IPG_S 219 +#define IMX8QM_AUD_GPT7_CLKIN 220 +#define IMX8QM_AUD_GPT7_24M_CLK 221 +#define IMX8QM_AUD_GPT8_IPG_S 222 +#define IMX8QM_AUD_GPT8_CLKIN 223 +#define IMX8QM_AUD_GPT8_24M_CLK 224 +#define IMX8QM_AUD_GPT9_IPG_S 225 +#define IMX8QM_AUD_GPT9_CLKIN 226 +#define IMX8QM_AUD_GPT9_24M_CLK 227 +#define IMX8QM_AUD_GPT10_IPG_S 228 +#define IMX8QM_AUD_GPT10_CLKIN 229 +#define IMX8QM_AUD_GPT10_24M_CLK 230 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV 232 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK 233 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV 234 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK 235 +#define IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV 236 +#define IMX8QM_AUD_ACM_AUD_REC_CLK0_CLK 237 +#define IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV 238 +#define IMX8QM_AUD_ACM_AUD_REC_CLK1_CLK 239 +#define IMX8QM_AUD_MCLKOUT0 240 +#define IMX8QM_AUD_MCLKOUT1 241 +#define IMX8QM_AUD_SPDIF_0_TX_CLK 242 +#define IMX8QM_AUD_SPDIF_0_GCLKW 243 +#define IMX8QM_AUD_SPDIF_0_IPG_S 244 +#define IMX8QM_AUD_SPDIF_1_TX_CLK 245 +#define IMX8QM_AUD_SPDIF_1_GCLKW 246 +#define IMX8QM_AUD_SPDIF_1_IPG_S 247 +#define IMX8QM_AUD_ASRC_0_IPG 248 +#define IMX8QM_AUD_ASRC_0_MEM 249 +#define IMX8QM_AUD_ASRC_1_IPG 250 +#define IMX8QM_AUD_ASRC_1_MEM 251 + + +/* VPU */ +#define IMX8QM_VPU_CORE_DIV 252 +#define IMX8QM_VPU_CORE_CLK 253 +#define IMX8QM_VPU_UART_DIV 254 +#define IMX8QM_VPU_UART_CLK 255 +#define IMX8QM_VPU_DDR_DIV 256 +#define IMX8QM_VPU_DDR_CLK 257 +#define IMX8QM_VPU_SYS_DIV 258 +#define IMX8QM_VPU_SYS_CLK 259 +#define IMX8QM_VPU_XUVI_DIV 260 +#define IMX8QM_VPU_XUVI_CLK 261 + +/* GPU Clocks. */ +#define IMX8QM_GPU0_CORE_DIV 262 +#define IMX8QM_GPU0_CORE_CLK 263 +#define IMX8QM_GPU0_SHADER_DIV 264 +#define IMX8QM_GPU0_SHADER_CLK 265 +#define IMX8QM_GPU1_CORE_DIV 266 +#define IMX8QM_GPU1_CORE_CLK 267 +#define IMX8QM_GPU1_SHADER_DIV 268 +#define IMX8QM_GPU1_SHADER_CLK 269 + + +/* MIPI CSI */ +#define IMX8QM_CSI0_IPG_CLK_S 270 +#define IMX8QM_CSI0_LIS_IPG_CLK 271 +#define IMX8QM_CSI0_APB_CLK 272 +#define IMX8QM_CSI0_I2C0_DIV 273 +#define IMX8QM_CSI0_I2C0_CLK 274 +#define IMX8QM_CSI0_PWM0_DIV 275 +#define IMX8QM_CSI0_PWM0_CLK 276 +#define IMX8QM_CSI0_CORE_DIV 277 +#define IMX8QM_CSI0_CORE_CLK 278 +#define IMX8QM_CSI0_ESC_DIV 279 +#define IMX8QM_CSI0_ESC_CLK 280 +#define IMX8QM_CSI1_IPG_CLK_S 281 +#define IMX8QM_CSI1_LIS_IPG_CLK 282 +#define IMX8QM_CSI1_APB_CLK 283 +#define IMX8QM_CSI1_I2C0_DIV 284 +#define IMX8QM_CSI1_I2C0_CLK 285 +#define IMX8QM_CSI1_PWM0_DIV 286 +#define IMX8QM_CSI1_PWM0_CLK 287 +#define IMX8QM_CSI1_CORE_DIV 288 +#define IMX8QM_CSI1_CORE_CLK 289 +#define IMX8QM_CSI1_ESC_DIV 290 +#define IMX8QM_CSI1_ESC_CLK 291 + + +/* Display */ +#define IMX8QM_DC0_PLL0_DIV 292 +#define IMX8QM_DC0_PLL0_CLK 293 +#define IMX8QM_DC0_PLL1_DIV 294 +#define IMX8QM_DC0_PLL1_CLK 295 +#define IMX8QM_DC0_DISP0_DIV 296 +#define IMX8QM_DC0_DISP0_CLK 297 +#define IMX8QM_DC0_DISP1_DIV 298 +#define IMX8QM_DC0_DISP1_CLK 299 +#define IMX8QM_DC0_BYPASS_0_DIV 300 +#define IMX8QM_DC0_BYPASS_1_DIV 301 +#define IMX8QM_DC0_IRIS_AXI_CLK 302 +#define IMX8AM_DC0_IRIS_MVPL_CLK 303 +#define IMX8QM_DC0_DISP0_MSI_CLK 304 +#define IMX8QM_DC0_LIS_IPG_CLK 305 +#define IMX8QM_DC0_PXL_CMB_APB_CLK 306 +#define IMX8QM_DC0_PRG0_RTRAM_CLK 307 +#define IMX8QM_DC0_PRG1_RTRAM_CLK 308 +#define IMX8QM_DC0_PRG2_RTRAM_CLK 309 +#define IMX8QM_DC0_PRG3_RTRAM_CLK 310 +#define IMX8QM_DC0_PRG4_RTRAM_CLK 311 +#define IMX8QM_DC0_PRG5_RTRAM_CLK 312 +#define IMX8QM_DC0_PRG6_RTRAM_CLK 313 +#define IMX8QM_DC0_PRG7_RTRAM_CLK 314 +#define IMX8QM_DC0_PRG8_RTRAM_CLK 315 +#define IMX8QM_DC0_PRG0_APB_CLK 316 +#define IMX8QM_DC0_PRG1_APB_CLK 317 +#define IMX8QM_DC0_PRG2_APB_CLK 318 +#define IMX8QM_DC0_PRG3_APB_CLK 319 +#define IMX8QM_DC0_PRG4_APB_CLK 320 +#define IMX8QM_DC0_PRG5_APB_CLK 321 +#define IMX8QM_DC0_PRG6_APB_CLK 322 +#define IMX8QM_DC0_PRG7_APB_CLK 323 +#define IMX8QM_DC0_PRG8_APB_CLK 324 +#define IMX8QM_DC0_DPR0_APB_CLK 325 +#define IMX8QM_DC0_DPR1_APB_CLK 326 +#define IMX8QM_DC0_RTRAM0_CLK 327 +#define IMX8QM_DC0_RTRAM1_CLK 328 +#define IMX8QM_DC1_PLL0_DIV 329 +#define IMX8QM_DC1_PLL0_CLK 330 +#define IMX8QM_DC1_PLL1_DIV 331 +#define IMX8QM_DC1_PLL1_CLK 332 +#define IMX8QM_DC1_DISP0_DIV 333 +#define IMX8QM_DC1_DISP0_CLK 334 +#define IMX8QM_DC1_BYPASS_0_DIV 335 +#define IMX8QM_DC1_BYPASS_1_DIV 336 +#define IMX8QM_DC1_DISP1_DIV 337 +#define IMX8QM_DC1_DISP1_CLK 338 +#define IMX8QM_DC1_IRIS_AXI_CLK 339 +#define IMX8AM_DC1_IRIS_MVPL_CLK 340 +#define IMX8QM_DC1_DISP0_MSI_CLK 341 +#define IMX8QM_DC1_LIS_IPG_CLK 342 +#define IMX8QM_DC1_PXL_CMB_APB_CLK 343 +#define IMX8QM_DC1_PRG0_RTRAM_CLK 344 +#define IMX8QM_DC1_PRG1_RTRAM_CLK 345 +#define IMX8QM_DC1_PRG2_RTRAM_CLK 346 +#define IMX8QM_DC1_PRG3_RTRAM_CLK 347 +#define IMX8QM_DC1_PRG4_RTRAM_CLK 348 +#define IMX8QM_DC1_PRG5_RTRAM_CLK 349 +#define IMX8QM_DC1_PRG6_RTRAM_CLK 350 +#define IMX8QM_DC1_PRG7_RTRAM_CLK 351 +#define IMX8QM_DC1_PRG8_RTRAM_CLK 352 +#define IMX8QM_DC1_PRG0_APB_CLK 353 +#define IMX8QM_DC1_PRG1_APB_CLK 354 +#define IMX8QM_DC1_PRG2_APB_CLK 355 +#define IMX8QM_DC1_PRG3_APB_CLK 356 +#define IMX8QM_DC1_PRG4_APB_CLK 357 +#define IMX8QM_DC1_PRG5_APB_CLK 358 +#define IMX8QM_DC1_PRG6_APB_CLK 359 +#define IMX8QM_DC1_PRG7_APB_CLK 360 +#define IMX8QM_DC1_PRG8_APB_CLK 361 +#define IMX8QM_DC1_DPR0_APB_CLK 362 +#define IMX8QM_DC1_DPR1_APB_CLK 363 +#define IMX8QM_DC1_RTRAM0_CLK 364 +#define IMX8QM_DC1_RTRAM1_CLK 365 + +/* DRC */ +#define IMX8QM_DRC0_PLL0_DIV 366 +#define IMX8QM_DRC0_PLL0_CLK 367 +#define IMX8QM_DRC0_DIV 368 +#define IMX8QM_DRC0_CLK 369 +#define IMX8QM_DRC1_PLL0_DIV 370 +#define IMX8QM_DRC1_PLL0_CLK 371 +#define IMX8QM_DRC1_DIV 372 +#define IMX8QM_DRC1_CLK 373 + + +/* HDMI */ +#define IMX8QM_HDMI_AV_PLL_DIV 374 +#define IMX8QM_HDMI_AV_PLL_CLK 375 +#define IMX8QM_HDMI_I2S_BYPASS_CLK 376 +#define IMX8QM_HDMI_I2C0_DIV 377 +#define IMX8QM_HDMI_I2C0_CLK 378 +#define IMX8QM_HDMI_PXL_DIV 379 +#define IMX8QM_HDMI_PXL_CLK 380 +#define IMX8QM_HDMI_PXL_LINK_DIV 381 +#define IMX8QM_HDMI_PXL_LINK_CLK 382 +#define IMX8QM_HDMI_PXL_MUX_DIV 383 +#define IMX8QM_HDMI_PXL_MUX_CLK 384 +#define IMX8QM_HDMI_I2S_DIV 385 +#define IMX8QM_HDMI_I2S_CLK 386 +#define IMX8QM_HDMI_HDP_CORE_DIV 387 +#define IMX8QM_HDMI_HDP_CORE_CLK 388 +#define IMX8QM_HDMI_I2C_IPG_S_CLK 389 +#define IMX8QM_HDMI_I2C_IPG_CLK 390 +#define IMX8QM_HDMI_PWM_IPG_S_CLK 391 +#define IMX8QM_HDMI_PWM_IPG_CLK 392 +#define IMX8QM_HDMI_PWM_32K_CLK 393 +#define IMX8QM_HDMI_GPIO_IPG_CLK 394 +#define IMX8QM_HDMI_PXL_LINK_SLV_ODD_CLK 395 +#define IMX8QM_HDMI_PXL_LINK_SLV_EVEN_CLK 396 +#define IMX8QM_HDMI_LIS_IPG_CLK 397 +#define IMX8QM_HDMI_MSI_HCLK 398 +#define IMX8QM_HDMI_PXL_EVEN_CLK 399 +#define IMX8QM_HDMI_HDP_CLK 400 +#define IMX8QM_HDMI_PXL_DBL_CLK 401 +#define IMX8QM_HDMI_APB_CLK 402 +#define IMX8QM_HDMI_PXL_LPCG_CLK 403 +#define IMX8QM_HDMI_HDP_PHY_CLK 404 +#define IMX8QM_HDMI_IPG_DIV 405 +#define IMX8QM_HDMI_VIF_CLK 406 +#define IMX8QM_HDMI_DIG_PLL_DIV 407 +#define IMX8QM_HDMI_DIG_PLL_CLK 408 +#define IMX8QM_HDMI_APB_MUX_CSR_CLK 409 +#define IMX8QM_HDMI_APB_MUX_CTRL_CLK 410 + +/* RX-HDMI */ +#define IMX8QM_HDMI_RX_I2S_BYPASS_CLK 411 +#define IMX8QM_HDMI_RX_BYPASS_CLK 412 +#define IMX8QM_HDMI_RX_SPDIF_BYPASS_CLK 413 +#define IMX8QM_HDMI_RX_I2C0_DIV 414 +#define IMX8QM_HDMI_RX_I2C0_CLK 415 +#define IMX8QM_HDMI_RX_SPDIF_DIV 416 +#define IMX8QM_HDMI_RX_SPDIF_CLK 417 +#define IMX8QM_HDMI_RX_HD_REF_DIV 418 +#define IMX8QM_HDMI_RX_HD_REF_CLK 419 +#define IMX8QM_HDMI_RX_HD_CORE_DIV 420 +#define IMX8QM_HDMI_RX_HD_CORE_CLK 421 +#define IMX8QM_HDMI_RX_PXL_DIV 422 +#define IMX8QM_HDMI_RX_PXL_CLK 423 +#define IMX8QM_HDMI_RX_I2S_DIV 424 +#define IMX8QM_HDMI_RX_I2S_CLK 425 +#define IMX8QM_HDMI_RX_PWM_DIV 426 +#define IMX8QM_HDMI_RX_PWM_CLK 427 + +/* LVDS */ +#define IMX8QM_LVDS0_BYPASS_CLK 428 +#define IMX8QM_LVDS0_PIXEL_DIV 429 +#define IMX8QM_LVDS0_PIXEL_CLK 430 +#define IMX8QM_LVDS0_PHY_DIV 431 +#define IMX8QM_LVDS0_PHY_CLK 432 +#define IMX8QM_LVDS0_I2C0_IPG_CLK 433 +#define IMX8QM_LVDS0_I2C0_DIV 434 +#define IMX8QM_LVDS0_I2C0_CLK 435 +#define IMX8QM_LVDS0_I2C1_IPG_CLK 436 +#define IMX8QM_LVDS0_I2C1_DIV 437 +#define IMX8QM_LVDS0_I2C1_CLK 438 +#define IMX8QM_LVDS0_PWM0_IPG_CLK 439 +#define IMX8QM_LVDS0_PWM0_DIV 440 +#define IMX8QM_LVDS0_PWM0_CLK 441 +#define IMX8QM_LVDS0_GPIO_IPG_CLK 444 +#define IMX8QM_LVDS1_BYPASS_DIV 445 +#define IMX8QM_LVDS1_BYPASS_CLK 446 +#define IMX8QM_LVDS1_PIXEL_DIV 447 +#define IMX8QM_LVDS1_PIXEL_CLK 448 +#define IMX8QM_LVDS1_PHY_DIV 449 +#define IMX8QM_LVDS1_PHY_CLK 450 +#define IMX8QM_LVDS1_I2C0_IPG_CLK 451 +#define IMX8QM_LVDS1_I2C0_DIV 452 +#define IMX8QM_LVDS1_I2C0_CLK 453 +#define IMX8QM_LVDS1_I2C1_IPG_CLK 454 +#define IMX8QM_LVDS1_I2C1_DIV 455 +#define IMX8QM_LVDS1_I2C1_CLK 456 +#define IMX8QM_LVDS1_PWM0_IPG_CLK 457 +#define IMX8QM_LVDS1_PWM0_DIV 458 +#define IMX8QM_LVDS1_PWM0_CLK 459 +#define IMX8QM_LVDS1_GPIO_IPG_CLK 462 + +/* MIPI */ +#define IMX8QM_MIPI0_BYPASS_CLK 465 +#define IMX8QM_MIPI0_I2C0_DIV 466 +#define IMX8QM_MIPI0_I2C0_CLK 467 +#define IMX8QM_MIPI0_I2C1_DIV 468 +#define IMX8QM_MIPI0_I2C1_CLK 469 +#define IMX8QM_MIPI0_PWM0_DIV 470 +#define IMX8QM_MIPI0_PWM0_CLK 471 +#define IMX8QM_MIPI0_DSI_TX_ESC_DIV 472 +#define IMX8QM_MIPI0_DSI_TX_ESC_CLK 473 +#define IMX8QM_MIPI0_DSI_RX_ESC_DIV 474 +#define IMX8QM_MIPI0_DSI_RX_ESC_CLK 475 +#define IMX8QM_MIPI0_PXL_DIV 476 +#define IMX8QM_MIPI0_PXL_CLK 477 +#define IMX8QM_MIPI1_BYPASS_CLK 479 +#define IMX8QM_MIPI1_I2C0_DIV 480 +#define IMX8QM_MIPI1_I2C0_CLK 481 +#define IMX8QM_MIPI1_I2C1_DIV 482 +#define IMX8QM_MIPI1_I2C1_CLK 483 +#define IMX8QM_MIPI1_PWM0_DIV 484 +#define IMX8QM_MIPI1_PWM0_CLK 485 +#define IMX8QM_MIPI1_DSI_TX_ESC_DIV 486 +#define IMX8QM_MIPI1_DSI_TX_ESC_CLK 487 +#define IMX8QM_MIPI1_DSI_RX_ESC_DIV 488 +#define IMX8QM_MIPI1_DSI_RX_ESC_CLK 489 +#define IMX8QM_MIPI1_PXL_DIV 490 +#define IMX8QM_MIPI1_PXL_CLK 491 + +/* Imaging */ +#define IMX8QM_IMG_JPEG_ENC_IPG_CLK 492 +#define IMX8QM_IMG_JPEG_ENC_CLK 493 +#define IMX8QM_IMG_JPEG_DEC_IPG_CLK 494 +#define IMX8QM_IMG_JPEG_DEC_CLK 495 +#define IMX8QM_IMG_PXL_LINK_DC0_CLK 496 +#define IMX8QM_IMG_PXL_LINK_DC1_CLK 497 +#define IMX8QM_IMG_PXL_LINK_CSI0_CLK 498 +#define IMX8QM_IMG_PXL_LINK_CSI1_CLK 499 +#define IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK 500 +#define IMX8QM_IMG_PDMA_0_CLK 501 +#define IMX8QM_IMG_PDMA_1_CLK 502 +#define IMX8QM_IMG_PDMA_2_CLK 503 +#define IMX8QM_IMG_PDMA_3_CLK 504 +#define IMX8QM_IMG_PDMA_4_CLK 505 +#define IMX8QM_IMG_PDMA_5_CLK 506 +#define IMX8QM_IMG_PDMA_6_CLK 507 +#define IMX8QM_IMG_PDMA_7_CLK 508 + +/* HSIO */ +#define IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK 509 +#define IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK 510 +#define IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK 511 +#define IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK 512 +#define IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK 513 +#define IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK 514 +#define IMX8QM_HSIO_PCIE_X1_PER_CLK 515 +#define IMX8QM_HSIO_PCIE_X2_PER_CLK 516 +#define IMX8QM_HSIO_SATA_PER_CLK 517 +#define IMX8QM_HSIO_PHY_X1_PER_CLK 518 +#define IMX8QM_HSIO_PHY_X2_PER_CLK 519 +#define IMX8QM_HSIO_MISC_PER_CLK 520 +#define IMX8QM_HSIO_PHY_X1_APB_CLK 521 +#define IMX8QM_HSIO_PHY_X2_APB_0_CLK 522 +#define IMX8QM_HSIO_PHY_X2_APB_1_CLK 523 +#define IMX8QM_HSIO_SATA_CLK 524 +#define IMX8QM_HSIO_GPIO_CLK 525 +#define IMX8QM_HSIO_PHY_X1_PCLK 526 +#define IMX8QM_HSIO_PHY_X2_PCLK_0 527 +#define IMX8QM_HSIO_PHY_X2_PCLK_1 528 +#define IMX8QM_HSIO_SATA_EPCS_RX_CLK 529 +#define IMX8QM_HSIO_SATA_EPCS_TX_CLK 530 + + +/* M4 */ +#define IMX8QM_M4_0_CORE_DIV 531 +#define IMX8QM_M4_0_CORE_CLK 532 +#define IMX8QM_M4_0_I2C_DIV 533 +#define IMX8QM_M4_0_I2C_CLK 534 +#define IMX8QM_M4_0_PIT_DIV 535 +#define IMX8QM_M4_0_PIT_CLK 536 +#define IMX8QM_M4_0_TPM_DIV 537 +#define IMX8QM_M4_0_TPM_CLK 538 +#define IMX8QM_M4_0_UART_DIV 539 +#define IMX8QM_M4_0_UART_CLK 540 +#define IMX8QM_M4_0_WDOG_DIV 541 +#define IMX8QM_M4_0_WDOG_CLK 542 +#define IMX8QM_M4_1_CORE_DIV 543 +#define IMX8QM_M4_1_CORE_CLK 544 +#define IMX8QM_M4_1_I2C_DIV 545 +#define IMX8QM_M4_1_I2C_CLK 546 +#define IMX8QM_M4_1_PIT_DIV 547 +#define IMX8QM_M4_1_PIT_CLK 548 +#define IMX8QM_M4_1_TPM_DIV 549 +#define IMX8QM_M4_1_TPM_CLK 550 +#define IMX8QM_M4_1_UART_DIV 551 +#define IMX8QM_M4_1_UART_CLK 552 +#define IMX8QM_M4_1_WDOG_DIV 553 +#define IMX8QM_M4_1_WDOG_CLK 554 + +/* IPG clocks */ +#define IMX8QM_24MHZ 555 +#define IMX8QM_GPT_3M 556 +#define IMX8QM_IPG_DMA_CLK_ROOT 557 +#define IMX8QM_IPG_AUD_CLK_ROOT 558 +#define IMX8QM_IPG_CONN_CLK_ROOT 559 +#define IMX8QM_AHB_CONN_CLK_ROOT 560 +#define IMX8QM_AXI_CONN_CLK_ROOT 561 +#define IMX8QM_IPG_MIPI_CSI_CLK_ROOT 562 +#define IMX8QM_DC_AXI_EXT_CLK 563 +#define IMX8QM_DC_AXI_INT_CLK 564 +#define IMX8QM_DC_CFG_CLK 565 +#define IMX8QM_HDMI_IPG_CLK 566 +#define IMX8QM_LVDS_IPG_CLK 567 +#define IMX8QM_IMG_AXI_CLK 568 +#define IMX8QM_IMG_IPG_CLK 569 +#define IMX8QM_IMG_PXL_CLK 570 +#define IMX8QM_CSI0_I2C0_IPG_CLK 571 +#define IMX8QM_CSI0_PWM0_IPG_CLK 572 +#define IMX8QM_CSI1_I2C0_IPG_CLK 573 +#define IMX8QM_CSI1_PWM0_IPG_CLK 574 +#define IMX8QM_DC0_DPR0_B_CLK 575 +#define IMX8QM_DC0_DPR1_B_CLK 576 +#define IMX8QM_DC1_DPR0_B_CLK 577 +#define IMX8QM_DC1_DPR1_B_CLK 578 +#define IMX8QM_32KHZ 579 +#define IMX8QM_HSIO_AXI_CLK 580 +#define IMX8QM_HSIO_PER_CLK 581 +#define IMX8QM_HDMI_RX_GPIO_IPG_S_CLK 582 +#define IMX8QM_HDMI_RX_PWM_IPG_S_CLK 583 +#define IMX8QM_HDMI_RX_PWM_IPG_CLK 584 +#define IMX8QM_HDMI_RX_I2C_DIV_CLK 585 +#define IMX8QM_HDMI_RX_I2C_IPG_S_CLK 586 +#define IMX8QM_HDMI_RX_I2C_IPG_CLK 587 +#define IMX8QM_HDMI_RX_SINK_PCLK 588 +#define IMX8QM_HDMI_RX_SINK_SCLK 589 +#define IMX8QM_HDMI_RX_PXL_ENC_CLK 590 +#define IMX8QM_HDMI_RX_IPG_CLK 591 + +/* ACM */ +#define IMX8QM_HDMI_RX_MCLK 592 +#define IMX8QM_EXT_AUD_MCLK0 593 +#define IMX8QM_EXT_AUD_MCLK1 594 +#define IMX8QM_ESAI0_RX_CLK 595 +#define IMX8QM_ESAI0_RX_HF_CLK 596 +#define IMX8QM_ESAI0_TX_CLK 597 +#define IMX8QM_ESAI0_TX_HF_CLK 598 +#define IMX8QM_ESAI1_RX_CLK 599 +#define IMX8QM_ESAI1_RX_HF_CLK 600 +#define IMX8QM_ESAI1_TX_CLK 601 +#define IMX8QM_ESAI1_TX_HF_CLK 602 +#define IMX8QM_SPDIF0_RX 603 +#define IMX8QM_SPDIF1_RX 604 +#define IMX8QM_SAI0_RX_BCLK 605 +#define IMX8QM_SAI0_TX_BCLK 606 +#define IMX8QM_SAI1_RX_BCLK 607 +#define IMX8QM_SAI1_TX_BCLK 608 +#define IMX8QM_SAI2_RX_BCLK 609 +#define IMX8QM_SAI3_RX_BCLK 610 +#define IMX8QM_HDMI_RX_SAI0_RX_BCLK 611 +#define IMX8QM_SAI6_RX_BCLK 612 +#define IMX8QM_HDMI_TX_SAI0_TX_BCLK 613 + +#define IMX8QM_ACM_AUD_CLK0_SEL 614 +#define IMX8QM_ACM_AUD_CLK0_CLK 615 +#define IMX8QM_ACM_AUD_CLK1_SEL 616 +#define IMX8QM_ACM_AUD_CLK1_CLK 617 +#define IMX8QM_ACM_MCLKOUT0_SEL 618 +#define IMX8QM_ACM_MCLKOUT0_CLK 619 +#define IMX8QM_ACM_MCLKOUT1_SEL 620 +#define IMX8QM_ACM_MCLKOUT1_CLK 621 +#define IMX8QM_ACM_ASRC0_MUX_CLK_SEL 622 +#define IMX8QM_ACM_ASRC0_MUX_CLK_CLK 623 +#define IMX8QM_ACM_ASRC1_MUX_CLK_SEL 624 +#define IMX8QM_ACM_ASRC1_MUX_CLK_CLK 625 +#define IMX8QM_ACM_ESAI0_MCLK_SEL 626 +#define IMX8QM_ACM_ESAI0_MCLK_CLK 627 +#define IMX8QM_ACM_ESAI1_MCLK_SEL 628 +#define IMX8QM_ACM_ESAI1_MCLK_CLK 629 +#define IMX8QM_ACM_GPT0_MUX_CLK_SEL 630 +#define IMX8QM_ACM_GPT0_MUX_CLK_CLK 631 +#define IMX8QM_ACM_GPT1_MUX_CLK_SEL 632 +#define IMX8QM_ACM_GPT1_MUX_CLK_CLK 633 +#define IMX8QM_ACM_GPT2_MUX_CLK_SEL 634 +#define IMX8QM_ACM_GPT2_MUX_CLK_CLK 635 +#define IMX8QM_ACM_GPT3_MUX_CLK_SEL 636 +#define IMX8QM_ACM_GPT3_MUX_CLK_CLK 637 +#define IMX8QM_ACM_GPT4_MUX_CLK_SEL 638 +#define IMX8QM_ACM_GPT4_MUX_CLK_CLK 639 +#define IMX8QM_ACM_GPT5_MUX_CLK_SEL 640 +#define IMX8QM_ACM_GPT5_MUX_CLK_CLK 641 +#define IMX8QM_ACM_SAI0_MCLK_SEL 642 +#define IMX8QM_ACM_SAI0_MCLK_CLK 643 +#define IMX8QM_ACM_SAI1_MCLK_SEL 644 +#define IMX8QM_ACM_SAI1_MCLK_CLK 645 +#define IMX8QM_ACM_SAI2_MCLK_SEL 646 +#define IMX8QM_ACM_SAI2_MCLK_CLK 647 +#define IMX8QM_ACM_SAI3_MCLK_SEL 648 +#define IMX8QM_ACM_SAI3_MCLK_CLK 649 +#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_SEL 650 +#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_CLK 651 +#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL 652 +#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_CLK 653 +#define IMX8QM_ACM_SAI6_MCLK_SEL 654 +#define IMX8QM_ACM_SAI6_MCLK_CLK 655 +#define IMX8QM_ACM_SAI7_MCLK_SEL 656 +#define IMX8QM_ACM_SAI7_MCLK_CLK 657 +#define IMX8QM_ACM_SPDIF0_TX_CLK_SEL 658 +#define IMX8QM_ACM_SPDIF0_TX_CLK_CLK 659 +#define IMX8QM_ACM_SPDIF1_TX_CLK_SEL 660 +#define IMX8QM_ACM_SPDIF1_TX_CLK_CLK 661 +#define IMX8QM_ACM_MQS_TX_CLK_SEL 662 +#define IMX8QM_ACM_MQS_TX_CLK_CLK 663 + +#define IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL 664 +#define IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK 665 +#define IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL 666 +#define IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK 667 +#define IMX8QM_ENET0_REF_50MHZ_CLK 668 +#define IMX8QM_ENET1_REF_50MHZ_CLK 669 +#define IMX8QM_ENET_25MHZ_CLK 670 +#define IMX8QM_ENET_125MHZ_CLK 671 +#define IMX8QM_ENET0_REF_DIV 672 +#define IMX8QM_ENET0_REF_CLK 673 +#define IMX8QM_ENET1_REF_DIV 674 +#define IMX8QM_ENET1_REF_CLK 675 +#define IMX8QM_ENET0_RMII_TX_CLK 676 +#define IMX8QM_ENET1_RMII_TX_CLK 677 +#define IMX8QM_ENET0_RMII_TX_SEL 678 +#define IMX8QM_ENET1_RMII_TX_SEL 679 +#define IMX8QM_ENET0_RMII_RX_CLK 680 +#define IMX8QM_ENET1_RMII_RX_CLK 681 + +#define IMX8QM_KPP_CLK 683 +#define IMX8QM_GPT0_HF_CLK 684 +#define IMX8QM_GPT0_IPG_S_CLK 685 +#define IMX8QM_GPT0_IPG_SLV_CLK 686 +#define IMX8QM_GPT0_IPG_MSTR_CLK 687 +#define IMX8QM_GPT1_HF_CLK 688 +#define IMX8QM_GPT1_IPG_S_CLK 689 +#define IMX8QM_GPT1_IPG_SLV_CLK 690 +#define IMX8QM_GPT1_IPG_MSTR_CLK 691 +#define IMX8QM_GPT2_HF_CLK 692 +#define IMX8QM_GPT2_IPG_S_CLK 693 +#define IMX8QM_GPT2_IPG_SLV_CLK 694 +#define IMX8QM_GPT2_IPG_MSTR_CLK 695 +#define IMX8QM_GPT3_HF_CLK 696 +#define IMX8QM_GPT3_IPG_S_CLK 697 +#define IMX8QM_GPT3_IPG_SLV_CLK 698 +#define IMX8QM_GPT3_IPG_MSTR_CLK 699 +#define IMX8QM_GPT4_HF_CLK 700 +#define IMX8QM_GPT4_IPG_S_CLK 701 +#define IMX8QM_GPT4_IPG_SLV_CLK 702 +#define IMX8QM_GPT4_IPG_MSTR_CLK 703 +#define IMX8QM_PWM0_HF_CLK 704 +#define IMX8QM_PWM0_IPG_S_CLK 705 +#define IMX8QM_PWM0_IPG_SLV_CLK 706 +#define IMX8QM_PWM0_IPG_MSTR_CLK 707 +#define IMX8QM_PWM1_HF_CLK 708 +#define IMX8QM_PWM1_IPG_S_CLK 709 +#define IMX8QM_PWM1_IPG_SLV_CLK 710 +#define IMX8QM_PWM1_IPG_MSTR_CLK 711 +#define IMX8QM_PWM2_HF_CLK 712 +#define IMX8QM_PWM2_IPG_S_CLK 713 +#define IMX8QM_PWM2_IPG_SLV_CLK 714 +#define IMX8QM_PWM2_IPG_MSTR_CLK 715 +#define IMX8QM_PWM3_HF_CLK 716 +#define IMX8QM_PWM3_IPG_S_CLK 717 +#define IMX8QM_PWM3_IPG_SLV_CLK 718 +#define IMX8QM_PWM3_IPG_MSTR_CLK 719 +#define IMX8QM_PWM4_HF_CLK 720 +#define IMX8QM_PWM4_IPG_S_CLK 721 +#define IMX8QM_PWM4_IPG_SLV_CLK 722 +#define IMX8QM_PWM4_IPG_MSTR_CLK 723 +#define IMX8QM_PWM5_HF_CLK 724 +#define IMX8QM_PWM5_IPG_S_CLK 725 +#define IMX8QM_PWM5_IPG_SLV_CLK 726 +#define IMX8QM_PWM5_IPG_MSTR_CLK 727 +#define IMX8QM_PWM6_HF_CLK 728 +#define IMX8QM_PWM6_IPG_S_CLK 729 +#define IMX8QM_PWM6_IPG_SLV_CLK 730 +#define IMX8QM_PWM6_IPG_MSTR_CLK 731 +#define IMX8QM_PWM7_HF_CLK 732 +#define IMX8QM_PWM7_IPG_S_CLK 733 +#define IMX8QM_PWM7_IPG_SLV_CLK 734 +#define IMX8QM_PWM7_IPG_MSTR_CLK 735 +#define IMX8QM_FSPI0_HCLK 736 +#define IMX8QM_FSPI0_IPG_CLK 737 +#define IMX8QM_FSPI0_IPG_S_CLK 738 +#define IMX8QM_FSPI1_HCLK 736 +#define IMX8QM_FSPI1_IPG_CLK 737 +#define IMX8QM_FSPI1_IPG_S_CLK 738 +#define IMX8QM_GPIO0_IPG_S_CLK 739 +#define IMX8QM_GPIO1_IPG_S_CLK 740 +#define IMX8QM_GPIO2_IPG_S_CLK 741 +#define IMX8QM_GPIO3_IPG_S_CLK 742 +#define IMX8QM_GPIO4_IPG_S_CLK 743 +#define IMX8QM_GPIO5_IPG_S_CLK 744 +#define IMX8QM_GPIO6_IPG_S_CLK 745 +#define IMX8QM_GPIO7_IPG_S_CLK 746 +#define IMX8QM_ROMCP_CLK 747 +#define IMX8QM_ROMCP_REG_CLK 748 +#define IMX8QM_96KROM_CLK 749 +#define IMX8QM_OCRAM_MEM_CLK 750 +#define IMX8QM_OCRAM_CTRL_CLK 751 +#define IMX8QM_LSIO_BUS_CLK 752 +#define IMX8QM_LSIO_MEM_CLK 753 +#define IMX8QM_LVDS0_LIS_IPG_CLK 754 +#define IMX8QM_LVDS1_LIS_IPG_CLK 755 +#define IMX8QM_DSI0_LIS_IPG_CLK 756 +#define IMX8QM_MIPI0_I2C0_IPG_S_CLK 757 +#define IMX8QM_MIPI0_I2C0_IPG_CLK 758 +#define IMX8QM_MIPI0_CLK_ROOT 759 + +#define IMX8QM_CLK_END 760 + +#endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */ diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h new file mode 100644 index 00000000000..a31c120dc0a --- /dev/null +++ b/include/dt-bindings/clock/imx8qxp-clock.h @@ -0,0 +1,533 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H +#define __DT_BINDINGS_CLOCK_IMX8QXP_H + +#define IMX8QXP_CLK_DUMMY 0 + +#define IMX8QXP_UART0_IPG_CLK 1 +#define IMX8QXP_UART0_DIV 2 +#define IMX8QXP_UART0_CLK 3 + +#define IMX8QXP_IPG_DMA_CLK_ROOT 4 + +/* GPU Clocks. */ +#define IMX8QXP_GPU0_CORE_DIV 5 +#define IMX8QXP_GPU0_CORE_CLK 6 +#define IMX8QXP_GPU0_SHADER_DIV 7 +#define IMX8QXP_GPU0_SHADER_CLK 8 + +#define IMX8QXP_24MHZ 9 +#define IMX8QXP_GPT_3M 10 +#define IMX8QXP_32KHZ 11 + +/* LSIO SS */ +#define IMX8QXP_LSIO_MEM_CLK 12 +#define IMX8QXP_LSIO_BUS_CLK 13 +#define IMX8QXP_LSIO_PWM0_DIV 14 +#define IMX8QXP_LSIO_PWM0_IPG_S_CLK 15 +#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK 16 +#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK 17 +#define IMX8QXP_LSIO_PWM0_HF_CLK 18 +#define IMX8QXP_LSIO_PWM0_CLK 19 +#define IMX8QXP_LSIO_PWM1_DIV 20 +#define IMX8QXP_LSIO_PWM1_IPG_S_CLK 21 +#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK 22 +#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK 23 +#define IMX8QXP_LSIO_PWM1_HF_CLK 24 +#define IMX8QXP_LSIO_PWM1_CLK 25 +#define IMX8QXP_LSIO_PWM2_DIV 26 +#define IMX8QXP_LSIO_PWM2_IPG_S_CLK 27 +#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK 28 +#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK 29 +#define IMX8QXP_LSIO_PWM2_HF_CLK 30 +#define IMX8QXP_LSIO_PWM2_CLK 31 +#define IMX8QXP_LSIO_PWM3_DIV 32 +#define IMX8QXP_LSIO_PWM3_IPG_S_CLK 33 +#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK 34 +#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK 35 +#define IMX8QXP_LSIO_PWM3_HF_CLK 36 +#define IMX8QXP_LSIO_PWM3_CLK 37 +#define IMX8QXP_LSIO_PWM4_DIV 38 +#define IMX8QXP_LSIO_PWM4_IPG_S_CLK 39 +#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK 40 +#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK 42 +#define IMX8QXP_LSIO_PWM4_HF_CLK 43 +#define IMX8QXP_LSIO_PWM4_CLK 44 +#define IMX8QXP_LSIO_PWM5_DIV 45 +#define IMX8QXP_LSIO_PWM5_IPG_S_CLK 46 +#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK 47 +#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK 48 +#define IMX8QXP_LSIO_PWM5_HF_CLK 49 +#define IMX8QXP_LSIO_PWM5_CLK 50 +#define IMX8QXP_LSIO_PWM6_DIV 51 +#define IMX8QXP_LSIO_PWM6_IPG_S_CLK 52 +#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK 53 +#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK 54 +#define IMX8QXP_LSIO_PWM6_HF_CLK 55 +#define IMX8QXP_LSIO_PWM6_CLK 56 +#define IMX8QXP_LSIO_PWM7_DIV 57 +#define IMX8QXP_LSIO_PWM7_IPG_S_CLK 58 +#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK 59 +#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK 60 +#define IMX8QXP_LSIO_PWM7_HF_CLK 61 +#define IMX8QXP_LSIO_PWM7_CLK 62 +#define IMX8QXP_LSIO_GPT0_DIV 63 +#define IMX8QXP_LSIO_GPT0_IPG_S_CLK 64 +#define IMX8QXP_LSIO_GPT0_IPG_SLV_CLK 65 +#define IMX8QXP_LSIO_GPT0_IPG_MSTR_CLK 66 +#define IMX8QXP_LSIO_GPT0_HF_CLK 67 +#define IMX8QXP_LSIO_GPT0_CLK 68 +#define IMX8QXP_LSIO_GPT1_DIV 69 +#define IMX8QXP_LSIO_GPT1_IPG_S_CLK 70 +#define IMX8QXP_LSIO_GPT1_IPG_SLV_CLK 71 +#define IMX8QXP_LSIO_GPT1_IPG_MSTR_CLK 72 +#define IMX8QXP_LSIO_GPT1_HF_CLK 73 +#define IMX8QXP_LSIO_GPT1_CLK 74 +#define IMX8QXP_LSIO_GPT2_DIV 75 +#define IMX8QXP_LSIO_GPT2_IPG_S_CLK 76 +#define IMX8QXP_LSIO_GPT2_IPG_SLV_CLK 77 +#define IMX8QXP_LSIO_GPT2_IPG_MSTR_CLK 78 +#define IMX8QXP_LSIO_GPT2_HF_CLK 79 +#define IMX8QXP_LSIO_GPT2_CLK 80 +#define IMX8QXP_LSIO_GPT3_DIV 81 +#define IMX8QXP_LSIO_GPT3_IPG_S_CLK 82 +#define IMX8QXP_LSIO_GPT3_IPG_SLV_CLK 83 +#define IMX8QXP_LSIO_GPT3_IPG_MSTR_CLK 84 +#define IMX8QXP_LSIO_GPT3_HF_CLK 85 +#define IMX8QXP_LSIO_GPT3_CLK 86 +#define IMX8QXP_LSIO_GPT4_DIV 87 +#define IMX8QXP_LSIO_GPT4_IPG_S_CLK 88 +#define IMX8QXP_LSIO_GPT4_IPG_SLV_CLK 89 +#define IMX8QXP_LSIO_GPT4_IPG_MSTR_CLK 90 +#define IMX8QXP_LSIO_GPT4_HF_CLK 91 +#define IMX8QXP_LSIO_GPT4_CLK 92 +#define IMX8QXP_LSIO_FSPI0_DIV 93 +#define IMX8QXP_LSIO_FSPI0_HCLK 94 +#define IMX8QXP_LSIO_FSPI0_IPG_S_CLK 95 +#define IMX8QXP_LSIO_FSPI0_IPG_CLK 96 +#define IMX8QXP_LSIO_FSPI0_CLK 97 +#define IMX8QXP_LSIO_FSPI1_DIV 98 +#define IMX8QXP_LSIO_FSPI1_HCLK 99 +#define IMX8QXP_LSIO_FSPI1_IPG_S_CLK 100 +#define IMX8QXP_LSIO_FSPI1_IPG_CLK 101 +#define IMX8QXP_LSIO_FSPI1_CLK 102 +#define IMX8QXP_LSIO_GPIO0_IPG_S_CLK 103 +#define IMX8QXP_LSIO_GPIO1_IPG_S_CLK 104 +#define IMX8QXP_LSIO_GPIO2_IPG_S_CLK 105 +#define IMX8QXP_LSIO_GPIO3_IPG_S_CLK 106 +#define IMX8QXP_LSIO_GPIO4_IPG_S_CLK 107 +#define IMX8QXP_LSIO_GPIO5_IPG_S_CLK 108 +#define IMX8QXP_LSIO_GPIO6_IPG_S_CLK 109 +#define IMX8QXP_LSIO_GPIO7_IPG_S_CLK 110 +#define IMX8QXP_LSIO_ROMCP_REG_CLK 111 +#define IMX8QXP_LSIO_ROMCP_CLK 112 +#define IMX8QXP_LSIO_96KROM_CLK 113 +#define IMX8QXP_LSIO_OCRAM_MEM_CLK 114 +#define IMX8QXP_LSIO_OCRAM_CTRL_CLK 115 + +/* ADMA SS */ +#define IMX8QXP_UART1_IPG_CLK 116 +#define IMX8QXP_UART2_IPG_CLK 117 +#define IMX8QXP_UART3_IPG_CLK 118 +#define IMX8QXP_UART1_DIV 119 +#define IMX8QXP_UART2_DIV 120 +#define IMX8QXP_UART3_DIV 121 +#define IMX8QXP_UART1_CLK 122 +#define IMX8QXP_UART2_CLK 123 +#define IMX8QXP_UART3_CLK 124 +#define IMX8QXP_SPI0_IPG_CLK 125 +#define IMX8QXP_SPI1_IPG_CLK 126 +#define IMX8QXP_SPI2_IPG_CLK 127 +#define IMX8QXP_SPI3_IPG_CLK 128 +#define IMX8QXP_SPI0_DIV 129 +#define IMX8QXP_SPI1_DIV 130 +#define IMX8QXP_SPI2_DIV 131 +#define IMX8QXP_SPI3_DIV 132 +#define IMX8QXP_SPI0_CLK 133 +#define IMX8QXP_SPI1_CLK 134 +#define IMX8QXP_SPI2_CLK 135 +#define IMX8QXP_SPI3_CLK 136 +#define IMX8QXP_CAN0_IPG_CHI_CLK 137 +#define IMX8QXP_CAN1_IPG_CHI_CLK 138 +#define IMX8QXP_CAN2_IPG_CHI_CLK 139 +#define IMX8QXP_CAN0_IPG_CLK 140 +#define IMX8QXP_CAN1_IPG_CLK 141 +#define IMX8QXP_CAN2_IPG_CLK 142 +#define IMX8QXP_CAN0_DIV 143 +#define IMX8QXP_CAN1_DIV 144 +#define IMX8QXP_CAN2_DIV 145 +#define IMX8QXP_CAN0_CLK 146 +#define IMX8QXP_CAN1_CLK 147 +#define IMX8QXP_CAN2_CLK 148 +#define IMX8QXP_I2C0_IPG_CLK 149 +#define IMX8QXP_I2C1_IPG_CLK 150 +#define IMX8QXP_I2C2_IPG_CLK 151 +#define IMX8QXP_I2C3_IPG_CLK 152 +#define IMX8QXP_I2C0_DIV 153 +#define IMX8QXP_I2C1_DIV 154 +#define IMX8QXP_I2C2_DIV 155 +#define IMX8QXP_I2C3_DIV 156 +#define IMX8QXP_I2C0_CLK 157 +#define IMX8QXP_I2C1_CLK 158 +#define IMX8QXP_I2C2_CLK 159 +#define IMX8QXP_I2C3_CLK 160 +#define IMX8QXP_FTM0_IPG_CLK 161 +#define IMX8QXP_FTM1_IPG_CLK 162 +#define IMX8QXP_FTM0_DIV 163 +#define IMX8QXP_FTM1_DIV 164 +#define IMX8QXP_FTM0_CLK 165 +#define IMX8QXP_FTM1_CLK 166 +#define IMX8QXP_ADC0_IPG_CLK 167 +#define IMX8QXP_ADC0_DIV 168 +#define IMX8QXP_ADC0_CLK 169 +#define IMX8QXP_PWM_IPG_CLK 170 +#define IMX8QXP_PWM_DIV 171 +#define IMX8QXP_PWM_CLK 172 +#define IMX8QXP_LCD_IPG_CLK 173 +#define IMX8QXP_LCD_DIV 174 +#define IMX8QXP_LCD_CLK 175 + +/* Connectivity SS */ +#define IMX8QXP_AXI_CONN_CLK_ROOT 176 +#define IMX8QXP_AHB_CONN_CLK_ROOT 177 +#define IMX8QXP_IPG_CONN_CLK_ROOT 178 +#define IMX8QXP_SDHC0_IPG_CLK 179 +#define IMX8QXP_SDHC1_IPG_CLK 180 +#define IMX8QXP_SDHC2_IPG_CLK 181 +#define IMX8QXP_SDHC0_DIV 182 +#define IMX8QXP_SDHC1_DIV 183 +#define IMX8QXP_SDHC2_DIV 184 +#define IMX8QXP_SDHC0_CLK 185 +#define IMX8QXP_SDHC1_CLK 186 +#define IMX8QXP_SDHC2_CLK 187 +#define IMX8QXP_ENET0_ROOT_DIV 188 +#define IMX8QXP_ENET0_REF_DIV 189 +#define IMX8QXP_ENET1_REF_DIV 190 +#define IMX8QXP_ENET0_BYPASS_DIV 191 +#define IMX8QXP_ENET0_RGMII_DIV 192 +#define IMX8QXP_ENET1_ROOT_DIV 193 +#define IMX8QXP_ENET1_BYPASS_DIV 194 +#define IMX8QXP_ENET1_RGMII_DIV 195 +#define IMX8QXP_ENET0_AHB_CLK 196 +#define IMX8QXP_ENET0_IPG_S_CLK 197 +#define IMX8QXP_ENET0_IPG_CLK 198 +#define IMX8QXP_ENET1_AHB_CLK 199 +#define IMX8QXP_ENET1_IPG_S_CLK 200 +#define IMX8QXP_ENET1_IPG_CLK 201 +#define IMX8QXP_ENET0_ROOT_CLK 202 +#define IMX8QXP_ENET1_ROOT_CLK 203 +#define IMX8QXP_ENET0_TX_CLK 204 +#define IMX8QXP_ENET1_TX_CLK 205 +#define IMX8QXP_ENET0_PTP_CLK 206 +#define IMX8QXP_ENET1_PTP_CLK 207 +#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL 208 +#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL 209 +#define IMX8QXP_ENET0_RMII_TX_SEL 210 +#define IMX8QXP_ENET1_RMII_TX_SEL 211 +#define IMX8QXP_ENET0_RGMII_TX_CLK 212 +#define IMX8QXP_ENET1_RGMII_TX_CLK 213 +#define IMX8QXP_ENET0_RMII_RX_CLK 214 +#define IMX8QXP_ENET1_RMII_RX_CLK 215 +#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK 216 +#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK 217 +#define IMX8QXP_ENET0_REF_50MHZ_CLK 218 +#define IMX8QXP_ENET1_REF_50MHZ_CLK 219 +#define IMX8QXP_GPMI_BCH_IO_DIV 220 +#define IMX8QXP_GPMI_BCH_DIV 221 +#define IMX8QXP_GPMI_APB_CLK 222 +#define IMX8QXP_GPMI_APB_BCH_CLK 223 +#define IMX8QXP_GPMI_BCH_IO_CLK 224 +#define IMX8QXP_GPMI_BCH_CLK 225 +#define IMX8QXP_APBHDMA_CLK 226 +#define IMX8QXP_USB3_ACLK_DIV 227 +#define IMX8QXP_USB3_BUS_DIV 228 +#define IMX8QXP_USB3_LPM_DIV 229 +#define IMX8QXP_USB3_IPG_CLK 230 +#define IMX8QXP_USB3_CORE_PCLK 231 +#define IMX8QXP_USB3_PHY_CLK 232 +#define IMX8QXP_USB3_ACLK 233 +#define IMX8QXP_USB3_BUS_CLK 234 +#define IMX8QXP_USB3_LPM_CLK 235 +#define IMX8QXP_USB2_OH_AHB_CLK 236 +#define IMX8QXP_USB2_OH_IPG_S_CLK 237 +#define IMX8QXP_USB2_OH_IPG_S_PL301_CLK 238 +#define IMX8QXP_USB2_PHY_IPG_CLK 239 +#define IMX8QXP_EDMA_CLK 240 +#define IMX8QXP_EDMA_IPG_CLK 241 +#define IMX8QXP_MLB_HCLK 242 +#define IMX8QXP_MLB_CLK 243 +#define IMX8QXP_MLB_IPG_CLK 244 + +/* Display controller SS */ +/* DC part1 */ +#define IMX8QXP_DC_AXI_EXT_CLK 245 +#define IMX8QXP_DC_AXI_INT_CLK 246 +#define IMX8QXP_DC_CFG_CLK 247 +#define IMX8QXP_DC0_DISP0_CLK 248 +#define IMX8QXP_DC0_DISP1_CLK 249 +#define IMX8QXP_DC0_PRG0_RTRAM_CLK 250 +#define IMX8QXP_DC0_PRG0_APB_CLK 251 +#define IMX8QXP_DC0_PRG1_RTRAM_CLK 252 +#define IMX8QXP_DC0_PRG1_APB_CLK 253 +#define IMX8QXP_DC0_PRG2_RTRAM_CLK 254 +#define IMX8QXP_DC0_PRG2_APB_CLK 255 +#define IMX8QXP_DC0_PRG3_RTRAM_CLK 256 +#define IMX8QXP_DC0_PRG3_APB_CLK 257 +#define IMX8QXP_DC0_PRG4_RTRAM_CLK 258 +#define IMX8QXP_DC0_PRG4_APB_CLK 259 +#define IMX8QXP_DC0_PRG5_RTRAM_CLK 260 +#define IMX8QXP_DC0_PRG5_APB_CLK 261 +#define IMX8QXP_DC0_PRG6_RTRAM_CLK 262 +#define IMX8QXP_DC0_PRG6_APB_CLK 263 +#define IMX8QXP_DC0_PRG7_RTRAM_CLK 264 +#define IMX8QXP_DC0_PRG7_APB_CLK 265 +#define IMX8QXP_DC0_PRG8_RTRAM_CLK 266 +#define IMX8QXP_DC0_PRG8_APB_CLK 267 +#define IMX8QXP_DC0_DPR0_APB_CLK 268 +#define IMX8QXP_DC0_DPR0_B_CLK 269 +#define IMX8QXP_DC0_RTRAM0_CLK 270 +#define IMX8QXP_DC0_RTRAM1_CLK 271 + +/* MIPI-LVDS part1 */ +#define IMX8QXP_MIPI_IPG_CLK 272 +#define IMX8QXP_MIPI0_I2C0_DIV 273 +#define IMX8QXP_MIPI0_I2C1_DIV 274 +#define IMX8QXP_MIPI0_I2C0_CLK 275 +#define IMX8QXP_MIPI0_I2C1_CLK 276 +#define IMX8QXP_MIPI0_I2C0_IPG_S_CLK 277 +#define IMX8QXP_MIPI0_I2C0_IPG_CLK 278 +#define IMX8QXP_MIPI0_I2C1_IPG_S_CLK 279 +#define IMX8QXP_MIPI0_I2C1_IPG_CLK 280 +#define IMX8QXP_MIPI0_PWM_IPG_S_CLK 281 +#define IMX8QXP_MIPI0_PWM_IPG_CLK 282 +#define IMX8QXP_MIPI0_PWM_32K_CLK 283 +#define IMX8QXP_MIPI0_GPIO_IPG_CLK 284 + +#define IMX8QXP_IMG_JPEG_ENC_IPG_CLK 285 +#define IMX8QXP_IMG_JPEG_ENC_CLK 286 +#define IMX8QXP_IMG_JPEG_DEC_IPG_CLK 287 +#define IMX8QXP_IMG_JPEG_DEC_CLK 288 +#define IMX8QXP_IMG_PXL_LINK_DC0_CLK 289 +#define IMX8QXP_IMG_PXL_LINK_DC1_CLK 290 +#define IMX8QXP_IMG_PXL_LINK_CSI0_CLK 291 +#define IMX8QXP_IMG_PXL_LINK_CSI1_CLK 292 +#define IMX8QXP_IMG_PXL_LINK_HDMI_IN_CLK 293 +#define IMX8QXP_IMG_PDMA_0_CLK 294 +#define IMX8QXP_IMG_PDMA_1_CLK 295 +#define IMX8QXP_IMG_PDMA_2_CLK 296 +#define IMX8QXP_IMG_PDMA_3_CLK 297 +#define IMX8QXP_IMG_PDMA_4_CLK 298 +#define IMX8QXP_IMG_PDMA_5_CLK 299 +#define IMX8QXP_IMG_PDMA_6_CLK 300 +#define IMX8QXP_IMG_PDMA_7_CLK 301 +#define IMX8QXP_IMG_AXI_CLK 302 +#define IMX8QXP_IMG_IPG_CLK 303 +#define IMX8QXP_IMG_PXL_CLK 304 + +#define IMX8QXP_CSI0_I2C0_DIV 305 +#define IMX8QXP_CSI0_PWM0_DIV 306 +#define IMX8QXP_CSI0_CORE_DIV 307 +#define IMX8QXP_CSI0_ESC_DIV 308 +#define IMX8QXP_CSI0_IPG_CLK_S 309 +#define IMX8QXP_CSI0_IPG_CLK 310 +#define IMX8QXP_CSI0_APB_CLK 311 +#define IMX8QXP_CSI0_I2C0_IPG_CLK 312 +#define IMX8QXP_CSI0_I2C0_CLK 313 +#define IMX8QXP_CSI0_PWM0_IPG_CLK 314 +#define IMX8QXP_CSI0_PWM0_CLK 315 +#define IMX8QXP_CSI0_CORE_CLK 316 +#define IMX8QXP_CSI0_ESC_CLK 317 + +#define IMX8QXP_HSIO_AXI_CLK 318 +#define IMX8QXP_HSIO_PER_CLK 319 +#define IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK 320 +#define IMX8QXP_HSIO_PCIE_SLV_AXI_CLK 321 +#define IMX8QXP_HSIO_PCIE_DBI_AXI_CLK 322 +#define IMX8QXP_HSIO_PCIE_X1_PER_CLK 323 +#define IMX8QXP_HSIO_PHY_X1_PER_CLK 324 +#define IMX8QXP_HSIO_MISC_PER_CLK 325 +#define IMX8QXP_HSIO_PHY_X1_APB_CLK 326 +#define IMX8QXP_HSIO_GPIO_CLK 327 +#define IMX8QXP_HSIO_PHY_X1_PCLK 328 + +#define IMX8QXP_A35_DIV 329 + +/* ACM */ +#define IMX8QXP_EXT_AUD_MCLK0 330 +#define IMX8QXP_EXT_AUD_MCLK1 331 +#define IMX8QXP_ESAI0_RX_CLK 332 +#define IMX8QXP_ESAI0_RX_HF_CLK 333 +#define IMX8QXP_ESAI0_TX_CLK 334 +#define IMX8QXP_ESAI0_TX_HF_CLK 335 +#define IMX8QXP_SPDIF0_RX 336 +#define IMX8QXP_SAI0_RX_BCLK 337 +#define IMX8QXP_SAI0_TX_BCLK 338 +#define IMX8QXP_SAI1_RX_BCLK 339 +#define IMX8QXP_SAI1_TX_BCLK 340 +#define IMX8QXP_SAI2_RX_BCLK 341 +#define IMX8QXP_SAI3_RX_BCLK 342 +#define IMX8QXP_SAI4_RX_BCLK 343 + +#define IMX8QXP_ACM_AUD_CLK0_SEL 344 +#define IMX8QXP_ACM_AUD_CLK0_CLK 345 +#define IMX8QXP_ACM_AUD_CLK1_SEL 346 +#define IMX8QXP_ACM_AUD_CLK1_CLK 347 +#define IMX8QXP_ACM_MCLKOUT0_SEL 348 +#define IMX8QXP_ACM_MCLKOUT0_CLK 349 +#define IMX8QXP_ACM_MCLKOUT1_SEL 350 +#define IMX8QXP_ACM_MCLKOUT1_CLK 351 +#define IMX8QXP_ACM_ESAI0_MCLK_SEL 352 +#define IMX8QXP_ACM_ESAI0_MCLK_CLK 353 +#define IMX8QXP_ACM_GPT0_MUX_CLK_SEL 354 +#define IMX8QXP_ACM_GPT0_MUX_CLK_CLK 355 +#define IMX8QXP_ACM_GPT1_MUX_CLK_SEL 356 +#define IMX8QXP_ACM_GPT1_MUX_CLK_CLK 357 +#define IMX8QXP_ACM_GPT2_MUX_CLK_SEL 358 +#define IMX8QXP_ACM_GPT2_MUX_CLK_CLK 359 +#define IMX8QXP_ACM_GPT3_MUX_CLK_SEL 360 +#define IMX8QXP_ACM_GPT3_MUX_CLK_CLK 361 +#define IMX8QXP_ACM_GPT4_MUX_CLK_SEL 362 +#define IMX8QXP_ACM_GPT4_MUX_CLK_CLK 363 +#define IMX8QXP_ACM_GPT5_MUX_CLK_SEL 364 +#define IMX8QXP_ACM_GPT5_MUX_CLK_CLK 365 +#define IMX8QXP_ACM_SAI0_MCLK_SEL 366 +#define IMX8QXP_ACM_SAI0_MCLK_CLK 367 +#define IMX8QXP_ACM_SAI1_MCLK_SEL 368 +#define IMX8QXP_ACM_SAI1_MCLK_CLK 369 +#define IMX8QXP_ACM_SAI2_MCLK_SEL 370 +#define IMX8QXP_ACM_SAI2_MCLK_CLK 371 +#define IMX8QXP_ACM_SAI3_MCLK_SEL 372 +#define IMX8QXP_ACM_SAI3_MCLK_CLK 373 +#define IMX8QXP_ACM_SAI4_MCLK_SEL 374 +#define IMX8QXP_ACM_SAI4_MCLK_CLK 375 +#define IMX8QXP_ACM_SAI5_MCLK_SEL 376 +#define IMX8QXP_ACM_SAI5_MCLK_CLK 377 +#define IMX8QXP_ACM_SPDIF0_TX_CLK_SEL 378 +#define IMX8QXP_ACM_SPDIF0_TX_CLK_CLK 379 +#define IMX8QXP_ACM_MQS_TX_CLK_SEL 380 +#define IMX8QXP_ACM_MQS_TX_CLK_CLK 381 +#define IMX8QXP_ACM_ASRC0_MUX_CLK_SEL 382 +#define IMX8QXP_ACM_ASRC1_MUX_CLK_SEL 383 +#define IMX8QXP_ACM_ASRC0_MUX_CLK_CLK 384 +#define IMX8QXP_ACM_ASRC1_MUX_CLK_CLK 385 + +#define IMX8QXP_IPG_AUD_CLK_ROOT 386 + +/* Audio */ +#define IMX8QXP_AUD_PLL0_DIV 387 +#define IMX8QXP_AUD_PLL0 388 +#define IMX8QXP_AUD_PLL1_DIV 389 +#define IMX8QXP_AUD_PLL1 390 +#define IMX8QXP_AUD_AMIX_IPG 391 +#define IMX8QXP_AUD_ESAI_0_IPG 392 +#define IMX8QXP_AUD_ESAI_0_EXTAL_IPG 393 +#define IMX8QXP_AUD_SAI_0_IPG 394 +#define IMX8QXP_AUD_SAI_0_MCLK 395 +#define IMX8QXP_AUD_SAI_1_IPG 396 +#define IMX8QXP_AUD_SAI_1_MCLK 397 +#define IMX8QXP_AUD_SAI_2_IPG 398 +#define IMX8QXP_AUD_SAI_2_MCLK 399 +#define IMX8QXP_AUD_SAI_3_IPG 400 +#define IMX8QXP_AUD_SAI_3_MCLK 401 +#define IMX8QXP_AUD_SAI_4_IPG 402 +#define IMX8QXP_AUD_SAI_4_MCLK 403 +#define IMX8QXP_AUD_SAI_5_IPG 404 +#define IMX8QXP_AUD_SAI_5_MCLK 405 +#define IMX8QXP_AUD_MQS_IPG 406 +#define IMX8QXP_AUD_MQS_HMCLK 407 +#define IMX8QXP_AUD_GPT5_IPG 408 +#define IMX8QXP_AUD_GPT5_CLKIN 409 +#define IMX8QXP_AUD_GPT6_IPG 410 +#define IMX8QXP_AUD_GPT6_CLKIN 411 +#define IMX8QXP_AUD_GPT7_IPG 412 +#define IMX8QXP_AUD_GPT7_CLKIN 413 +#define IMX8QXP_AUD_GPT8_IPG 414 +#define IMX8QXP_AUD_GPT8_CLKIN 415 +#define IMX8QXP_AUD_GPT9_IPG 416 +#define IMX8QXP_AUD_GPT9_CLKIN 417 +#define IMX8QXP_AUD_GPT10_IPG 418 +#define IMX8QXP_AUD_GPT10_CLKIN 419 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV 420 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK 421 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV 422 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK 423 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV 424 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_CLK 425 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV 426 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_CLK 427 +#define IMX8QXP_AUD_MCLKOUT0 428 +#define IMX8QXP_AUD_MCLKOUT1 429 +#define IMX8QXP_AUD_SPDIF_0_TX_CLK 430 +#define IMX8QXP_AUD_SPDIF_0_GCLKW 431 +#define IMX8QXP_AUD_SPDIF_0_IPG 432 +#define IMX8QXP_AUD_ASRC_0_IPG 433 +#define IMX8QXP_AUD_ASRC_1_IPG 434 +#define IMX8QXP_AUD_HIFI_ADB_ACLK 435 +#define IMX8QXP_AUD_HIFI_IPG 436 +#define IMX8QXP_AUD_HIFI_CORE_CLK 437 +#define IMX8QXP_AUD_OCRAM_IPG 438 + +/* DC part2 */ +#define IMX8QXP_DC0_DISP0_DIV 439 +#define IMX8QXP_DC0_DISP1_DIV 440 +#define IMX8QXP_DC0_BYPASS_0_DIV 441 +#define IMX8QXP_DC0_BYPASS_1_DIV 442 +#define IMX8QXP_DC0_PLL0_DIV 443 +#define IMX8QXP_DC0_PLL1_DIV 444 +#define IMX8QXP_DC0_PLL0_CLK 445 +#define IMX8QXP_DC0_PLL1_CLK 446 + +/* MIPI-LVDS part2 */ +#define IMX8QXP_MIPI0_BYPASS_CLK 447 +#define IMX8QXP_MIPI0_PIXEL_DIV 448 +#define IMX8QXP_MIPI0_PIXEL_CLK 449 +#define IMX8QXP_MIPI0_LVDS_PIXEL_DIV 450 +#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 451 +#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 452 +#define IMX8QXP_MIPI0_LVDS_PHY_DIV 453 +#define IMX8QXP_MIPI0_LVDS_PHY_CLK 454 +#define IMX8QXP_MIPI0_LIS_IPG_CLK 455 +#define IMX8QXP_MIPI1_I2C0_DIV 456 +#define IMX8QXP_MIPI1_I2C1_DIV 457 +#define IMX8QXP_MIPI1_I2C0_CLK 458 +#define IMX8QXP_MIPI1_I2C1_CLK 459 +#define IMX8QXP_MIPI1_I2C0_IPG_S_CLK 460 +#define IMX8QXP_MIPI1_I2C0_IPG_CLK 461 +#define IMX8QXP_MIPI1_I2C1_IPG_S_CLK 462 +#define IMX8QXP_MIPI1_I2C1_IPG_CLK 463 +#define IMX8QXP_MIPI1_PWM_IPG_S_CLK 464 +#define IMX8QXP_MIPI1_PWM_IPG_CLK 465 +#define IMX8QXP_MIPI1_PWM_32K_CLK 466 +#define IMX8QXP_MIPI1_GPIO_IPG_CLK 467 +#define IMX8QXP_MIPI1_BYPASS_CLK 468 +#define IMX8QXP_MIPI1_PIXEL_DIV 469 +#define IMX8QXP_MIPI1_PIXEL_CLK 470 +#define IMX8QXP_MIPI1_LVDS_PIXEL_DIV 471 +#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 472 +#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 473 +#define IMX8QXP_MIPI1_LVDS_PHY_DIV 474 +#define IMX8QXP_MIPI1_LVDS_PHY_CLK 475 +#define IMX8QXP_MIPI1_LIS_IPG_CLK 476 + +/* CM40 */ +#define IMX8QXP_CM40_IPG_CLK 477 +#define IMX8QXP_CM40_I2C_DIV 478 +#define IMX8QXP_CM40_I2C_CLK 479 +#define IMX8QXP_CM40_I2C_IPG_CLK 480 + +#define IMX8QXP_CLK_END 481 +#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */ diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h new file mode 100644 index 00000000000..33a68a9f4e8 --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8qm.h @@ -0,0 +1,1003 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file used to configure SoC pad list. + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/*@{*/ +#define SC_P_SIM0_CLK 0 /*!< DMA.SIM0.CLK, LSIO.GPIO0.IO00 */ +#define SC_P_SIM0_RST 1 /*!< DMA.SIM0.RST, LSIO.GPIO0.IO01 */ +#define SC_P_SIM0_IO 2 /*!< DMA.SIM0.IO, LSIO.GPIO0.IO02 */ +#define SC_P_SIM0_PD 3 /*!< DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */ +#define SC_P_SIM0_POWER_EN 4 /*!< DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */ +#define SC_P_SIM0_GPIO0_00 5 /*!< DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /*!< */ +#define SC_P_M40_I2C0_SCL 7 /*!< M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */ +#define SC_P_M40_I2C0_SDA 8 /*!< M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */ +#define SC_P_M40_GPIO0_00 9 /*!< M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */ +#define SC_P_M40_GPIO0_01 10 /*!< M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */ +#define SC_P_M41_I2C0_SCL 11 /*!< M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */ +#define SC_P_M41_I2C0_SDA 12 /*!< M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */ +#define SC_P_M41_GPIO0_00 13 /*!< M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ +#define SC_P_M41_GPIO0_01 14 /*!< M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ +#define SC_P_GPT0_CLK 15 /*!< LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ +#define SC_P_GPT0_CAPTURE 16 /*!< LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */ +#define SC_P_GPT0_COMPARE 17 /*!< LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ +#define SC_P_GPT1_CLK 18 /*!< LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ +#define SC_P_GPT1_CAPTURE 19 /*!< LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */ +#define SC_P_GPT1_COMPARE 20 /*!< LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ +#define SC_P_UART0_RX 21 /*!< DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */ +#define SC_P_UART0_TX 22 /*!< DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */ +#define SC_P_UART0_RTS_B 23 /*!< DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */ +#define SC_P_UART0_CTS_B 24 /*!< DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */ +#define SC_P_UART1_TX 25 /*!< DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */ +#define SC_P_UART1_RX 26 /*!< DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */ +#define SC_P_UART1_RTS_B 27 /*!< DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */ +#define SC_P_UART1_CTS_B 28 /*!< DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /*!< */ +#define SC_P_SCU_PMIC_MEMC_ON 30 /*!< SCU.GPIO0.IOXX_PMIC_MEMC_ON */ +#define SC_P_SCU_WDOG_OUT 31 /*!< SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SDA 32 /*!< SCU.PMIC_I2C.SDA */ +#define SC_P_PMIC_I2C_SCL 33 /*!< SCU.PMIC_I2C.SCL */ +#define SC_P_PMIC_EARLY_WARNING 34 /*!< SCU.PMIC_EARLY_WARNING */ +#define SC_P_PMIC_INT_B 35 /*!< SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 36 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */ +#define SC_P_SCU_GPIO0_01 37 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */ +#define SC_P_SCU_GPIO0_02 38 /*!< SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */ +#define SC_P_SCU_GPIO0_03 39 /*!< SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */ +#define SC_P_SCU_GPIO0_04 40 /*!< SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */ +#define SC_P_SCU_GPIO0_05 41 /*!< SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */ +#define SC_P_SCU_GPIO0_06 42 /*!< SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */ +#define SC_P_SCU_GPIO0_07 43 /*!< SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */ +#define SC_P_SCU_BOOT_MODE0 44 /*!< SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 45 /*!< SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 46 /*!< SCU.DSC.BOOT_MODE2 */ +#define SC_P_SCU_BOOT_MODE3 47 /*!< SCU.DSC.BOOT_MODE3 */ +#define SC_P_SCU_BOOT_MODE4 48 /*!< SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */ +#define SC_P_SCU_BOOT_MODE5 49 /*!< SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */ +#define SC_P_LVDS0_GPIO00 50 /*!< LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */ +#define SC_P_LVDS0_GPIO01 51 /*!< LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ +#define SC_P_LVDS0_I2C0_SCL 52 /*!< LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ +#define SC_P_LVDS0_I2C0_SDA 53 /*!< LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ +#define SC_P_LVDS0_I2C1_SCL 54 /*!< LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */ +#define SC_P_LVDS0_I2C1_SDA 55 /*!< LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */ +#define SC_P_LVDS1_GPIO00 56 /*!< LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */ +#define SC_P_LVDS1_GPIO01 57 /*!< LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ +#define SC_P_LVDS1_I2C0_SCL 58 /*!< LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */ +#define SC_P_LVDS1_I2C0_SDA 59 /*!< LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */ +#define SC_P_LVDS1_I2C1_SCL 60 /*!< LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */ +#define SC_P_LVDS1_I2C1_SDA 61 /*!< LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /*!< */ +#define SC_P_MIPI_DSI0_I2C0_SCL 63 /*!< MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 64 /*!< MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */ +#define SC_P_MIPI_DSI0_GPIO0_00 65 /*!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */ +#define SC_P_MIPI_DSI0_GPIO0_01 66 /*!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 67 /*!< MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 68 /*!< MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */ +#define SC_P_MIPI_DSI1_GPIO0_00 69 /*!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */ +#define SC_P_MIPI_DSI1_GPIO0_01 70 /*!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /*!< */ +#define SC_P_MIPI_CSI0_MCLK_OUT 72 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 73 /*!< MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 74 /*!< MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_CSI0_GPIO0_00 75 /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_CSI0_GPIO0_01 76 /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_CSI1_MCLK_OUT 77 /*!< MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_CSI1_GPIO0_00 78 /*!< MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_CSI1_GPIO0_01 79 /*!< MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_CSI1_I2C0_SCL 80 /*!< MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */ +#define SC_P_MIPI_CSI1_I2C0_SDA 81 /*!< MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */ +#define SC_P_HDMI_TX0_TS_SCL 82 /*!< HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */ +#define SC_P_HDMI_TX0_TS_SDA 83 /*!< HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */ +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /*!< */ +#define SC_P_ESAI1_FSR 85 /*!< AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */ +#define SC_P_ESAI1_FST 86 /*!< AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */ +#define SC_P_ESAI1_SCKR 87 /*!< AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */ +#define SC_P_ESAI1_SCKT 88 /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */ +#define SC_P_ESAI1_TX0 89 /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */ +#define SC_P_ESAI1_TX1 90 /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */ +#define SC_P_ESAI1_TX2_RX3 91 /*!< AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */ +#define SC_P_ESAI1_TX3_RX2 92 /*!< AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */ +#define SC_P_ESAI1_TX4_RX1 93 /*!< AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */ +#define SC_P_ESAI1_TX5_RX0 94 /*!< AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */ +#define SC_P_SPDIF0_RX 95 /*!< AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */ +#define SC_P_SPDIF0_TX 96 /*!< AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */ +#define SC_P_SPDIF0_EXT_CLK 97 /*!< AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */ +#define SC_P_SPI3_SCK 98 /*!< DMA.SPI3.SCK, LSIO.GPIO2.IO17 */ +#define SC_P_SPI3_SDO 99 /*!< DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */ +#define SC_P_SPI3_SDI 100 /*!< DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */ +#define SC_P_SPI3_CS0 101 /*!< DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */ +#define SC_P_SPI3_CS1 102 /*!< DMA.SPI3.CS1, LSIO.GPIO2.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /*!< */ +#define SC_P_ESAI0_FSR 104 /*!< AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */ +#define SC_P_ESAI0_FST 105 /*!< AUD.ESAI0.FST, LSIO.GPIO2.IO23 */ +#define SC_P_ESAI0_SCKR 106 /*!< AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */ +#define SC_P_ESAI0_SCKT 107 /*!< AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */ +#define SC_P_ESAI0_TX0 108 /*!< AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */ +#define SC_P_ESAI0_TX1 109 /*!< AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */ +#define SC_P_ESAI0_TX2_RX3 110 /*!< AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */ +#define SC_P_ESAI0_TX3_RX2 111 /*!< AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */ +#define SC_P_ESAI0_TX4_RX1 112 /*!< AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */ +#define SC_P_ESAI0_TX5_RX0 113 /*!< AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */ +#define SC_P_MCLK_IN0 114 /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */ +#define SC_P_MCLK_OUT0 115 /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /*!< */ +#define SC_P_SPI0_SCK 117 /*!< DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */ +#define SC_P_SPI0_SDO 118 /*!< DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */ +#define SC_P_SPI0_SDI 119 /*!< DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */ +#define SC_P_SPI0_CS0 120 /*!< DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */ +#define SC_P_SPI0_CS1 121 /*!< DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */ +#define SC_P_SPI2_SCK 122 /*!< DMA.SPI2.SCK, LSIO.GPIO3.IO07 */ +#define SC_P_SPI2_SDO 123 /*!< DMA.SPI2.SDO, LSIO.GPIO3.IO08 */ +#define SC_P_SPI2_SDI 124 /*!< DMA.SPI2.SDI, LSIO.GPIO3.IO09 */ +#define SC_P_SPI2_CS0 125 /*!< DMA.SPI2.CS0, LSIO.GPIO3.IO10 */ +#define SC_P_SPI2_CS1 126 /*!< DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */ +#define SC_P_SAI1_RXC 127 /*!< AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */ +#define SC_P_SAI1_RXD 128 /*!< AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */ +#define SC_P_SAI1_RXFS 129 /*!< AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */ +#define SC_P_SAI1_TXC 130 /*!< AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */ +#define SC_P_SAI1_TXD 131 /*!< AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */ +#define SC_P_SAI1_TXFS 132 /*!< AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /*!< */ +#define SC_P_ADC_IN7 134 /*!< DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */ +#define SC_P_ADC_IN6 135 /*!< DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */ +#define SC_P_ADC_IN5 136 /*!< DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */ +#define SC_P_ADC_IN4 137 /*!< DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */ +#define SC_P_ADC_IN3 138 /*!< DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */ +#define SC_P_ADC_IN2 139 /*!< DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */ +#define SC_P_ADC_IN1 140 /*!< DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */ +#define SC_P_ADC_IN0 141 /*!< DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */ +#define SC_P_MLB_SIG 142 /*!< CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */ +#define SC_P_MLB_CLK 143 /*!< CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */ +#define SC_P_MLB_DATA 144 /*!< CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /*!< */ +#define SC_P_FLEXCAN0_RX 146 /*!< DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */ +#define SC_P_FLEXCAN0_TX 147 /*!< DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */ +#define SC_P_FLEXCAN1_RX 148 /*!< DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */ +#define SC_P_FLEXCAN1_TX 149 /*!< DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */ +#define SC_P_FLEXCAN2_RX 150 /*!< DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */ +#define SC_P_FLEXCAN2_TX 151 /*!< DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /*!< */ +#define SC_P_USB_SS3_TC0 153 /*!< DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 154 /*!< DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 155 /*!< DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 156 /*!< DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /*!< */ +#define SC_P_USDHC1_RESET_B 158 /*!< CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */ +#define SC_P_USDHC1_VSELECT 159 /*!< CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */ +#define SC_P_USDHC2_RESET_B 160 /*!< CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */ +#define SC_P_USDHC2_VSELECT 161 /*!< CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */ +#define SC_P_USDHC2_WP 162 /*!< CONN.USDHC2.WP, LSIO.GPIO4.IO11 */ +#define SC_P_USDHC2_CD_B 163 /*!< CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /*!< */ +#define SC_P_ENET0_MDIO 165 /*!< CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */ +#define SC_P_ENET0_MDC 166 /*!< CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */ +#define SC_P_ENET0_REFCLK_125M_25M 167 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */ +#define SC_P_ENET1_REFCLK_125M_25M 168 /*!< CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */ +#define SC_P_ENET1_MDIO 169 /*!< CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */ +#define SC_P_ENET1_MDC 170 /*!< CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /*!< */ +#define SC_P_QSPI1A_SS0_B 172 /*!< LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */ +#define SC_P_QSPI1A_SS1_B 173 /*!< LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */ +#define SC_P_QSPI1A_SCLK 174 /*!< LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */ +#define SC_P_QSPI1A_DQS 175 /*!< LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_QSPI1A_DATA3 176 /*!< LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */ +#define SC_P_QSPI1A_DATA2 177 /*!< LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */ +#define SC_P_QSPI1A_DATA1 178 /*!< LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */ +#define SC_P_QSPI1A_DATA0 179 /*!< LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /*!< */ +#define SC_P_QSPI0A_DATA0 181 /*!< LSIO.QSPI0A.DATA0 */ +#define SC_P_QSPI0A_DATA1 182 /*!< LSIO.QSPI0A.DATA1 */ +#define SC_P_QSPI0A_DATA2 183 /*!< LSIO.QSPI0A.DATA2 */ +#define SC_P_QSPI0A_DATA3 184 /*!< LSIO.QSPI0A.DATA3 */ +#define SC_P_QSPI0A_DQS 185 /*!< LSIO.QSPI0A.DQS */ +#define SC_P_QSPI0A_SS0_B 186 /*!< LSIO.QSPI0A.SS0_B */ +#define SC_P_QSPI0A_SS1_B 187 /*!< LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */ +#define SC_P_QSPI0A_SCLK 188 /*!< LSIO.QSPI0A.SCLK */ +#define SC_P_QSPI0B_SCLK 189 /*!< LSIO.QSPI0B.SCLK */ +#define SC_P_QSPI0B_DATA0 190 /*!< LSIO.QSPI0B.DATA0 */ +#define SC_P_QSPI0B_DATA1 191 /*!< LSIO.QSPI0B.DATA1 */ +#define SC_P_QSPI0B_DATA2 192 /*!< LSIO.QSPI0B.DATA2 */ +#define SC_P_QSPI0B_DATA3 193 /*!< LSIO.QSPI0B.DATA3 */ +#define SC_P_QSPI0B_DQS 194 /*!< LSIO.QSPI0B.DQS */ +#define SC_P_QSPI0B_SS0_B 195 /*!< LSIO.QSPI0B.SS0_B */ +#define SC_P_QSPI0B_SS1_B 196 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /*!< */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */ +#define SC_P_PCIE_CTRL0_WAKE_B 199 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */ +#define SC_P_PCIE_CTRL0_PERST_B 200 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */ +#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /*!< HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */ +#define SC_P_PCIE_CTRL1_WAKE_B 202 /*!< HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */ +#define SC_P_PCIE_CTRL1_PERST_B 203 /*!< HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /*!< */ +#define SC_P_USB_HSIC0_DATA 205 /*!< CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */ +#define SC_P_USB_HSIC0_STROBE 206 /*!< CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */ +#define SC_P_CALIBRATION_0_HSIC 207 /*!< */ +#define SC_P_CALIBRATION_1_HSIC 208 /*!< */ +#define SC_P_EMMC0_CLK 209 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B */ +#define SC_P_EMMC0_CMD 210 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */ +#define SC_P_EMMC0_DATA0 211 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */ +#define SC_P_EMMC0_DATA1 212 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */ +#define SC_P_EMMC0_DATA2 213 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */ +#define SC_P_EMMC0_DATA3 214 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */ +#define SC_P_EMMC0_DATA4 215 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */ +#define SC_P_EMMC0_DATA5 216 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */ +#define SC_P_EMMC0_DATA6 217 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */ +#define SC_P_EMMC0_DATA7 218 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */ +#define SC_P_EMMC0_STROBE 219 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */ +#define SC_P_EMMC0_RESET_B 220 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /*!< */ +#define SC_P_USDHC1_CLK 222 /*!< CONN.USDHC1.CLK, AUD.MQS.R */ +#define SC_P_USDHC1_CMD 223 /*!< CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */ +#define SC_P_USDHC1_DATA0 224 /*!< CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */ +#define SC_P_USDHC1_DATA1 225 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */ +#define SC_P_CTL_NAND_RE_P_N 226 /*!< */ +#define SC_P_USDHC1_DATA2 227 /*!< CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */ +#define SC_P_USDHC1_DATA3 228 /*!< CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */ +#define SC_P_CTL_NAND_DQS_P_N 229 /*!< */ +#define SC_P_USDHC1_DATA4 230 /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */ +#define SC_P_USDHC1_DATA5 231 /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */ +#define SC_P_USDHC1_DATA6 232 /*!< CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */ +#define SC_P_USDHC1_DATA7 233 /*!< CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */ +#define SC_P_USDHC1_STROBE 234 /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /*!< */ +#define SC_P_USDHC2_CLK 236 /*!< CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */ +#define SC_P_USDHC2_CMD 237 /*!< CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */ +#define SC_P_USDHC2_DATA0 238 /*!< CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */ +#define SC_P_USDHC2_DATA1 239 /*!< CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */ +#define SC_P_USDHC2_DATA2 240 /*!< CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */ +#define SC_P_USDHC2_DATA3 241 /*!< CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /*!< */ +#define SC_P_ENET0_RGMII_TXC 243 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */ +#define SC_P_ENET0_RGMII_TX_CTL 244 /*!< CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */ +#define SC_P_ENET0_RGMII_TXD0 245 /*!< CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */ +#define SC_P_ENET0_RGMII_TXD1 246 /*!< CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */ +#define SC_P_ENET0_RGMII_TXD2 247 /*!< CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */ +#define SC_P_ENET0_RGMII_TXD3 248 /*!< CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */ +#define SC_P_ENET0_RGMII_RXC 249 /*!< CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */ +#define SC_P_ENET0_RGMII_RX_CTL 250 /*!< CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */ +#define SC_P_ENET0_RGMII_RXD0 251 /*!< CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */ +#define SC_P_ENET0_RGMII_RXD1 252 /*!< CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */ +#define SC_P_ENET0_RGMII_RXD2 253 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */ +#define SC_P_ENET0_RGMII_RXD3 254 /*!< CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /*!< */ +#define SC_P_ENET1_RGMII_TXC 256 /*!< CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */ +#define SC_P_ENET1_RGMII_TX_CTL 257 /*!< CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */ +#define SC_P_ENET1_RGMII_TXD0 258 /*!< CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */ +#define SC_P_ENET1_RGMII_TXD1 259 /*!< CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */ +#define SC_P_ENET1_RGMII_TXD2 260 /*!< CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */ +#define SC_P_ENET1_RGMII_TXD3 261 /*!< CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */ +#define SC_P_ENET1_RGMII_RXC 262 /*!< CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */ +#define SC_P_ENET1_RGMII_RX_CTL 263 /*!< CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */ +#define SC_P_ENET1_RGMII_RXD0 264 /*!< CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */ +#define SC_P_ENET1_RGMII_RXD1 265 /*!< CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */ +#define SC_P_ENET1_RGMII_RXD2 266 /*!< CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */ +#define SC_P_ENET1_RGMII_RXD3 267 /*!< CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /*!< */ +/*@}*/ + +/*! + * @name Pad Mux Definitions + * format: name padid padmux + */ +/*@{*/ +#define SC_P_SIM0_CLK_DMA_SIM0_CLK SC_P_SIM0_CLK 0 +#define SC_P_SIM0_CLK_LSIO_GPIO0_IO00 SC_P_SIM0_CLK 3 +#define SC_P_SIM0_RST_DMA_SIM0_RST SC_P_SIM0_RST 0 +#define SC_P_SIM0_RST_LSIO_GPIO0_IO01 SC_P_SIM0_RST 3 +#define SC_P_SIM0_IO_DMA_SIM0_IO SC_P_SIM0_IO 0 +#define SC_P_SIM0_IO_LSIO_GPIO0_IO02 SC_P_SIM0_IO 3 +#define SC_P_SIM0_PD_DMA_SIM0_PD SC_P_SIM0_PD 0 +#define SC_P_SIM0_PD_DMA_I2C3_SCL SC_P_SIM0_PD 1 +#define SC_P_SIM0_PD_LSIO_GPIO0_IO03 SC_P_SIM0_PD 3 +#define SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN SC_P_SIM0_POWER_EN 0 +#define SC_P_SIM0_POWER_EN_DMA_I2C3_SDA SC_P_SIM0_POWER_EN 1 +#define SC_P_SIM0_POWER_EN_LSIO_GPIO0_IO04 SC_P_SIM0_POWER_EN 3 +#define SC_P_SIM0_GPIO0_00_DMA_SIM0_POWER_EN SC_P_SIM0_GPIO0_00 0 +#define SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 SC_P_SIM0_GPIO0_00 3 +#define SC_P_M40_I2C0_SCL_M40_I2C0_SCL SC_P_M40_I2C0_SCL 0 +#define SC_P_M40_I2C0_SCL_M40_UART0_RX SC_P_M40_I2C0_SCL 1 +#define SC_P_M40_I2C0_SCL_M40_GPIO0_IO02 SC_P_M40_I2C0_SCL 2 +#define SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 SC_P_M40_I2C0_SCL 3 +#define SC_P_M40_I2C0_SDA_M40_I2C0_SDA SC_P_M40_I2C0_SDA 0 +#define SC_P_M40_I2C0_SDA_M40_UART0_TX SC_P_M40_I2C0_SDA 1 +#define SC_P_M40_I2C0_SDA_M40_GPIO0_IO03 SC_P_M40_I2C0_SDA 2 +#define SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 SC_P_M40_I2C0_SDA 3 +#define SC_P_M40_GPIO0_00_M40_GPIO0_IO00 SC_P_M40_GPIO0_00 0 +#define SC_P_M40_GPIO0_00_M40_TPM0_CH0 SC_P_M40_GPIO0_00 1 +#define SC_P_M40_GPIO0_00_DMA_UART4_RX SC_P_M40_GPIO0_00 2 +#define SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 SC_P_M40_GPIO0_00 3 +#define SC_P_M40_GPIO0_01_M40_GPIO0_IO01 SC_P_M40_GPIO0_01 0 +#define SC_P_M40_GPIO0_01_M40_TPM0_CH1 SC_P_M40_GPIO0_01 1 +#define SC_P_M40_GPIO0_01_DMA_UART4_TX SC_P_M40_GPIO0_01 2 +#define SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 SC_P_M40_GPIO0_01 3 +#define SC_P_M41_I2C0_SCL_M41_I2C0_SCL SC_P_M41_I2C0_SCL 0 +#define SC_P_M41_I2C0_SCL_M41_UART0_RX SC_P_M41_I2C0_SCL 1 +#define SC_P_M41_I2C0_SCL_M41_GPIO0_IO02 SC_P_M41_I2C0_SCL 2 +#define SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 SC_P_M41_I2C0_SCL 3 +#define SC_P_M41_I2C0_SDA_M41_I2C0_SDA SC_P_M41_I2C0_SDA 0 +#define SC_P_M41_I2C0_SDA_M41_UART0_TX SC_P_M41_I2C0_SDA 1 +#define SC_P_M41_I2C0_SDA_M41_GPIO0_IO03 SC_P_M41_I2C0_SDA 2 +#define SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 SC_P_M41_I2C0_SDA 3 +#define SC_P_M41_GPIO0_00_M41_GPIO0_IO00 SC_P_M41_GPIO0_00 0 +#define SC_P_M41_GPIO0_00_M41_TPM0_CH0 SC_P_M41_GPIO0_00 1 +#define SC_P_M41_GPIO0_00_DMA_UART3_RX SC_P_M41_GPIO0_00 2 +#define SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 SC_P_M41_GPIO0_00 3 +#define SC_P_M41_GPIO0_01_M41_GPIO0_IO01 SC_P_M41_GPIO0_01 0 +#define SC_P_M41_GPIO0_01_M41_TPM0_CH1 SC_P_M41_GPIO0_01 1 +#define SC_P_M41_GPIO0_01_DMA_UART3_TX SC_P_M41_GPIO0_01 2 +#define SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 SC_P_M41_GPIO0_01 3 +#define SC_P_GPT0_CLK_LSIO_GPT0_CLK SC_P_GPT0_CLK 0 +#define SC_P_GPT0_CLK_DMA_I2C1_SCL SC_P_GPT0_CLK 1 +#define SC_P_GPT0_CLK_LSIO_KPP0_COL4 SC_P_GPT0_CLK 2 +#define SC_P_GPT0_CLK_LSIO_GPIO0_IO14 SC_P_GPT0_CLK 3 +#define SC_P_GPT0_CAPTURE_LSIO_GPT0_CAPTURE SC_P_GPT0_CAPTURE 0 +#define SC_P_GPT0_CAPTURE_DMA_I2C1_SDA SC_P_GPT0_CAPTURE 1 +#define SC_P_GPT0_CAPTURE_LSIO_KPP0_COL5 SC_P_GPT0_CAPTURE 2 +#define SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15 SC_P_GPT0_CAPTURE 3 +#define SC_P_GPT0_COMPARE_LSIO_GPT0_COMPARE SC_P_GPT0_COMPARE 0 +#define SC_P_GPT0_COMPARE_LSIO_PWM3_OUT SC_P_GPT0_COMPARE 1 +#define SC_P_GPT0_COMPARE_LSIO_KPP0_COL6 SC_P_GPT0_COMPARE 2 +#define SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 SC_P_GPT0_COMPARE 3 +#define SC_P_GPT1_CLK_LSIO_GPT1_CLK SC_P_GPT1_CLK 0 +#define SC_P_GPT1_CLK_DMA_I2C2_SCL SC_P_GPT1_CLK 1 +#define SC_P_GPT1_CLK_LSIO_KPP0_COL7 SC_P_GPT1_CLK 2 +#define SC_P_GPT1_CLK_LSIO_GPIO0_IO17 SC_P_GPT1_CLK 3 +#define SC_P_GPT1_CAPTURE_LSIO_GPT1_CAPTURE SC_P_GPT1_CAPTURE 0 +#define SC_P_GPT1_CAPTURE_DMA_I2C2_SDA SC_P_GPT1_CAPTURE 1 +#define SC_P_GPT1_CAPTURE_LSIO_KPP0_ROW4 SC_P_GPT1_CAPTURE 2 +#define SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18 SC_P_GPT1_CAPTURE 3 +#define SC_P_GPT1_COMPARE_LSIO_GPT1_COMPARE SC_P_GPT1_COMPARE 0 +#define SC_P_GPT1_COMPARE_LSIO_PWM2_OUT SC_P_GPT1_COMPARE 1 +#define SC_P_GPT1_COMPARE_LSIO_KPP0_ROW5 SC_P_GPT1_COMPARE 2 +#define SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 SC_P_GPT1_COMPARE 3 +#define SC_P_UART0_RX_DMA_UART0_RX SC_P_UART0_RX 0 +#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 1 +#define SC_P_UART0_RX_LSIO_GPIO0_IO20 SC_P_UART0_RX 3 +#define SC_P_UART0_TX_DMA_UART0_TX SC_P_UART0_TX 0 +#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 1 +#define SC_P_UART0_TX_LSIO_GPIO0_IO21 SC_P_UART0_TX 3 +#define SC_P_UART0_RTS_B_DMA_UART0_RTS_B SC_P_UART0_RTS_B 0 +#define SC_P_UART0_RTS_B_LSIO_PWM0_OUT SC_P_UART0_RTS_B 1 +#define SC_P_UART0_RTS_B_DMA_UART2_RX SC_P_UART0_RTS_B 2 +#define SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 SC_P_UART0_RTS_B 3 +#define SC_P_UART0_CTS_B_DMA_UART0_CTS_B SC_P_UART0_CTS_B 0 +#define SC_P_UART0_CTS_B_LSIO_PWM1_OUT SC_P_UART0_CTS_B 1 +#define SC_P_UART0_CTS_B_DMA_UART2_TX SC_P_UART0_CTS_B 2 +#define SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 SC_P_UART0_CTS_B 3 +#define SC_P_UART1_TX_DMA_UART1_TX SC_P_UART1_TX 0 +#define SC_P_UART1_TX_DMA_SPI3_SCK SC_P_UART1_TX 1 +#define SC_P_UART1_TX_LSIO_GPIO0_IO24 SC_P_UART1_TX 3 +#define SC_P_UART1_RX_DMA_UART1_RX SC_P_UART1_RX 0 +#define SC_P_UART1_RX_DMA_SPI3_SDO SC_P_UART1_RX 1 +#define SC_P_UART1_RX_LSIO_GPIO0_IO25 SC_P_UART1_RX 3 +#define SC_P_UART1_RTS_B_DMA_UART1_RTS_B SC_P_UART1_RTS_B 0 +#define SC_P_UART1_RTS_B_DMA_SPI3_SDI SC_P_UART1_RTS_B 1 +#define SC_P_UART1_RTS_B_DMA_UART1_CTS_B SC_P_UART1_RTS_B 2 +#define SC_P_UART1_RTS_B_LSIO_GPIO0_IO26 SC_P_UART1_RTS_B 3 +#define SC_P_UART1_CTS_B_DMA_UART1_CTS_B SC_P_UART1_CTS_B 0 +#define SC_P_UART1_CTS_B_DMA_SPI3_CS0 SC_P_UART1_CTS_B 1 +#define SC_P_UART1_CTS_B_DMA_UART1_RTS_B SC_P_UART1_CTS_B 2 +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO27 SC_P_UART1_CTS_B 3 +#define SC_P_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON SC_P_SCU_PMIC_MEMC_ON 0 +#define SC_P_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT SC_P_SCU_WDOG_OUT 0 +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0 +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0 +#define SC_P_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING SC_P_PMIC_EARLY_WARNING 0 +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0 +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0 +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1 +#define SC_P_SCU_GPIO0_00_LSIO_GPIO0_IO28 SC_P_SCU_GPIO0_00 3 +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0 +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1 +#define SC_P_SCU_GPIO0_01_LSIO_GPIO0_IO29 SC_P_SCU_GPIO0_01 3 +#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IO02 SC_P_SCU_GPIO0_02 0 +#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON SC_P_SCU_GPIO0_02 1 +#define SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30 SC_P_SCU_GPIO0_02 3 +#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IO03 SC_P_SCU_GPIO0_03 0 +#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON SC_P_SCU_GPIO0_03 1 +#define SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 SC_P_SCU_GPIO0_03 3 +#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IO04 SC_P_SCU_GPIO0_04 0 +#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON SC_P_SCU_GPIO0_04 1 +#define SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00 SC_P_SCU_GPIO0_04 3 +#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IO05 SC_P_SCU_GPIO0_05 0 +#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON SC_P_SCU_GPIO0_05 1 +#define SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 SC_P_SCU_GPIO0_05 3 +#define SC_P_SCU_GPIO0_06_SCU_GPIO0_IO06 SC_P_SCU_GPIO0_06 0 +#define SC_P_SCU_GPIO0_06_SCU_TPM0_CH0 SC_P_SCU_GPIO0_06 1 +#define SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 SC_P_SCU_GPIO0_06 3 +#define SC_P_SCU_GPIO0_07_SCU_GPIO0_IO07 SC_P_SCU_GPIO0_07 0 +#define SC_P_SCU_GPIO0_07_SCU_TPM0_CH1 SC_P_SCU_GPIO0_07 1 +#define SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_GPIO0_07 2 +#define SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03 SC_P_SCU_GPIO0_07 3 +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0 +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0 +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0 +#define SC_P_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 SC_P_SCU_BOOT_MODE4 0 +#define SC_P_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE4 1 +#define SC_P_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 SC_P_SCU_BOOT_MODE5 0 +#define SC_P_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE5 1 +#define SC_P_LVDS0_GPIO00_LVDS0_GPIO0_IO00 SC_P_LVDS0_GPIO00 0 +#define SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT SC_P_LVDS0_GPIO00 1 +#define SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 SC_P_LVDS0_GPIO00 3 +#define SC_P_LVDS0_GPIO01_LVDS0_GPIO0_IO01 SC_P_LVDS0_GPIO01 0 +#define SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 SC_P_LVDS0_GPIO01 3 +#define SC_P_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL SC_P_LVDS0_I2C0_SCL 0 +#define SC_P_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 SC_P_LVDS0_I2C0_SCL 1 +#define SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 SC_P_LVDS0_I2C0_SCL 3 +#define SC_P_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA SC_P_LVDS0_I2C0_SDA 0 +#define SC_P_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 SC_P_LVDS0_I2C0_SDA 1 +#define SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 SC_P_LVDS0_I2C0_SDA 3 +#define SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL SC_P_LVDS0_I2C1_SCL 0 +#define SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX SC_P_LVDS0_I2C1_SCL 1 +#define SC_P_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 SC_P_LVDS0_I2C1_SCL 3 +#define SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA SC_P_LVDS0_I2C1_SDA 0 +#define SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX SC_P_LVDS0_I2C1_SDA 1 +#define SC_P_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 SC_P_LVDS0_I2C1_SDA 3 +#define SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 SC_P_LVDS1_GPIO00 0 +#define SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT SC_P_LVDS1_GPIO00 1 +#define SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10 SC_P_LVDS1_GPIO00 3 +#define SC_P_LVDS1_GPIO01_LVDS1_GPIO0_IO01 SC_P_LVDS1_GPIO01 0 +#define SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 SC_P_LVDS1_GPIO01 3 +#define SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL SC_P_LVDS1_I2C0_SCL 0 +#define SC_P_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 SC_P_LVDS1_I2C0_SCL 1 +#define SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 SC_P_LVDS1_I2C0_SCL 3 +#define SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA SC_P_LVDS1_I2C0_SDA 0 +#define SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 SC_P_LVDS1_I2C0_SDA 1 +#define SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 SC_P_LVDS1_I2C0_SDA 3 +#define SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL SC_P_LVDS1_I2C1_SCL 0 +#define SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX SC_P_LVDS1_I2C1_SCL 1 +#define SC_P_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 SC_P_LVDS1_I2C1_SCL 3 +#define SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA SC_P_LVDS1_I2C1_SDA 0 +#define SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX SC_P_LVDS1_I2C1_SDA 1 +#define SC_P_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 SC_P_LVDS1_I2C1_SDA 3 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0 +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 SC_P_MIPI_DSI0_I2C0_SCL 3 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0 +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 SC_P_MIPI_DSI0_I2C0_SDA 3 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 1 +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 SC_P_MIPI_DSI0_GPIO0_00 3 +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0 +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 SC_P_MIPI_DSI0_GPIO0_01 3 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0 +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 SC_P_MIPI_DSI1_I2C0_SCL 3 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0 +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 SC_P_MIPI_DSI1_I2C0_SDA 3 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 1 +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 SC_P_MIPI_DSI1_GPIO0_00 3 +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0 +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 SC_P_MIPI_DSI1_GPIO0_01 3 +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0 +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 SC_P_MIPI_CSI0_MCLK_OUT 3 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0 +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_CSI0_I2C0_SCL 3 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0 +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_CSI0_I2C0_SDA 3 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0 +#define SC_P_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 2 +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_CSI0_GPIO0_00 3 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0 +#define SC_P_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 2 +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_CSI0_GPIO0_01 3 +#define SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT SC_P_MIPI_CSI1_MCLK_OUT 0 +#define SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 SC_P_MIPI_CSI1_MCLK_OUT 3 +#define SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 SC_P_MIPI_CSI1_GPIO0_00 0 +#define SC_P_MIPI_CSI1_GPIO0_00_DMA_UART4_RX SC_P_MIPI_CSI1_GPIO0_00 1 +#define SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 SC_P_MIPI_CSI1_GPIO0_00 3 +#define SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 SC_P_MIPI_CSI1_GPIO0_01 0 +#define SC_P_MIPI_CSI1_GPIO0_01_DMA_UART4_TX SC_P_MIPI_CSI1_GPIO0_01 1 +#define SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 SC_P_MIPI_CSI1_GPIO0_01 3 +#define SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI1_I2C0_SCL 0 +#define SC_P_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 SC_P_MIPI_CSI1_I2C0_SCL 3 +#define SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI1_I2C0_SDA 0 +#define SC_P_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 SC_P_MIPI_CSI1_I2C0_SDA 3 +#define SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 0 +#define SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 1 +#define SC_P_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 SC_P_HDMI_TX0_TS_SCL 3 +#define SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 0 +#define SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 1 +#define SC_P_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 SC_P_HDMI_TX0_TS_SDA 3 +#define SC_P_ESAI1_FSR_AUD_ESAI1_FSR SC_P_ESAI1_FSR 0 +#define SC_P_ESAI1_FSR_LSIO_GPIO2_IO04 SC_P_ESAI1_FSR 3 +#define SC_P_ESAI1_FST_AUD_ESAI1_FST SC_P_ESAI1_FST 0 +#define SC_P_ESAI1_FST_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_FST 1 +#define SC_P_ESAI1_FST_LSIO_GPIO2_IO05 SC_P_ESAI1_FST 3 +#define SC_P_ESAI1_SCKR_AUD_ESAI1_SCKR SC_P_ESAI1_SCKR 0 +#define SC_P_ESAI1_SCKR_LSIO_GPIO2_IO06 SC_P_ESAI1_SCKR 3 +#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT SC_P_ESAI1_SCKT 0 +#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC SC_P_ESAI1_SCKT 1 +#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_SCKT 2 +#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 SC_P_ESAI1_SCKT 3 +#define SC_P_ESAI1_TX0_AUD_ESAI1_TX0 SC_P_ESAI1_TX0 0 +#define SC_P_ESAI1_TX0_AUD_SAI2_RXD SC_P_ESAI1_TX0 1 +#define SC_P_ESAI1_TX0_AUD_SPDIF0_RX SC_P_ESAI1_TX0 2 +#define SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 SC_P_ESAI1_TX0 3 +#define SC_P_ESAI1_TX1_AUD_ESAI1_TX1 SC_P_ESAI1_TX1 0 +#define SC_P_ESAI1_TX1_AUD_SAI2_RXFS SC_P_ESAI1_TX1 1 +#define SC_P_ESAI1_TX1_AUD_SPDIF0_TX SC_P_ESAI1_TX1 2 +#define SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 SC_P_ESAI1_TX1 3 +#define SC_P_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 SC_P_ESAI1_TX2_RX3 0 +#define SC_P_ESAI1_TX2_RX3_AUD_SPDIF0_RX SC_P_ESAI1_TX2_RX3 1 +#define SC_P_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 SC_P_ESAI1_TX2_RX3 3 +#define SC_P_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 SC_P_ESAI1_TX3_RX2 0 +#define SC_P_ESAI1_TX3_RX2_AUD_SPDIF0_TX SC_P_ESAI1_TX3_RX2 1 +#define SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 SC_P_ESAI1_TX3_RX2 3 +#define SC_P_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 SC_P_ESAI1_TX4_RX1 0 +#define SC_P_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 SC_P_ESAI1_TX4_RX1 3 +#define SC_P_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 SC_P_ESAI1_TX5_RX0 0 +#define SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 SC_P_ESAI1_TX5_RX0 3 +#define SC_P_SPDIF0_RX_AUD_SPDIF0_RX SC_P_SPDIF0_RX 0 +#define SC_P_SPDIF0_RX_AUD_MQS_R SC_P_SPDIF0_RX 1 +#define SC_P_SPDIF0_RX_AUD_ACM_MCLK_IN1 SC_P_SPDIF0_RX 2 +#define SC_P_SPDIF0_RX_LSIO_GPIO2_IO14 SC_P_SPDIF0_RX 3 +#define SC_P_SPDIF0_TX_AUD_SPDIF0_TX SC_P_SPDIF0_TX 0 +#define SC_P_SPDIF0_TX_AUD_MQS_L SC_P_SPDIF0_TX 1 +#define SC_P_SPDIF0_TX_AUD_ACM_MCLK_OUT1 SC_P_SPDIF0_TX 2 +#define SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 SC_P_SPDIF0_TX 3 +#define SC_P_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0 +#define SC_P_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 SC_P_SPDIF0_EXT_CLK 1 +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 SC_P_SPDIF0_EXT_CLK 3 +#define SC_P_SPI3_SCK_DMA_SPI3_SCK SC_P_SPI3_SCK 0 +#define SC_P_SPI3_SCK_LSIO_GPIO2_IO17 SC_P_SPI3_SCK 3 +#define SC_P_SPI3_SDO_DMA_SPI3_SDO SC_P_SPI3_SDO 0 +#define SC_P_SPI3_SDO_DMA_FTM_CH0 SC_P_SPI3_SDO 1 +#define SC_P_SPI3_SDO_LSIO_GPIO2_IO18 SC_P_SPI3_SDO 3 +#define SC_P_SPI3_SDI_DMA_SPI3_SDI SC_P_SPI3_SDI 0 +#define SC_P_SPI3_SDI_DMA_FTM_CH1 SC_P_SPI3_SDI 1 +#define SC_P_SPI3_SDI_LSIO_GPIO2_IO19 SC_P_SPI3_SDI 3 +#define SC_P_SPI3_CS0_DMA_SPI3_CS0 SC_P_SPI3_CS0 0 +#define SC_P_SPI3_CS0_DMA_FTM_CH2 SC_P_SPI3_CS0 1 +#define SC_P_SPI3_CS0_LSIO_GPIO2_IO20 SC_P_SPI3_CS0 3 +#define SC_P_SPI3_CS1_DMA_SPI3_CS1 SC_P_SPI3_CS1 0 +#define SC_P_SPI3_CS1_LSIO_GPIO2_IO21 SC_P_SPI3_CS1 3 +#define SC_P_ESAI0_FSR_AUD_ESAI0_FSR SC_P_ESAI0_FSR 0 +#define SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 SC_P_ESAI0_FSR 3 +#define SC_P_ESAI0_FST_AUD_ESAI0_FST SC_P_ESAI0_FST 0 +#define SC_P_ESAI0_FST_LSIO_GPIO2_IO23 SC_P_ESAI0_FST 3 +#define SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR SC_P_ESAI0_SCKR 0 +#define SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 SC_P_ESAI0_SCKR 3 +#define SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT SC_P_ESAI0_SCKT 0 +#define SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 SC_P_ESAI0_SCKT 3 +#define SC_P_ESAI0_TX0_AUD_ESAI0_TX0 SC_P_ESAI0_TX0 0 +#define SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 SC_P_ESAI0_TX0 3 +#define SC_P_ESAI0_TX1_AUD_ESAI0_TX1 SC_P_ESAI0_TX1 0 +#define SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 SC_P_ESAI0_TX1 3 +#define SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0 +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 SC_P_ESAI0_TX2_RX3 3 +#define SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0 +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 SC_P_ESAI0_TX3_RX2 3 +#define SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0 +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 SC_P_ESAI0_TX4_RX1 3 +#define SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0 +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 SC_P_ESAI0_TX5_RX0 3 +#define SC_P_MCLK_IN0_AUD_ACM_MCLK_IN0 SC_P_MCLK_IN0 0 +#define SC_P_MCLK_IN0_AUD_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1 +#define SC_P_MCLK_IN0_AUD_ESAI1_RX_HF_CLK SC_P_MCLK_IN0 2 +#define SC_P_MCLK_IN0_LSIO_GPIO3_IO00 SC_P_MCLK_IN0 3 +#define SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0 +#define SC_P_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1 +#define SC_P_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK SC_P_MCLK_OUT0 2 +#define SC_P_MCLK_OUT0_LSIO_GPIO3_IO01 SC_P_MCLK_OUT0 3 +#define SC_P_SPI0_SCK_DMA_SPI0_SCK SC_P_SPI0_SCK 0 +#define SC_P_SPI0_SCK_AUD_SAI0_RXC SC_P_SPI0_SCK 1 +#define SC_P_SPI0_SCK_LSIO_GPIO3_IO02 SC_P_SPI0_SCK 3 +#define SC_P_SPI0_SDO_DMA_SPI0_SDO SC_P_SPI0_SDO 0 +#define SC_P_SPI0_SDO_AUD_SAI0_TXD SC_P_SPI0_SDO 1 +#define SC_P_SPI0_SDO_LSIO_GPIO3_IO03 SC_P_SPI0_SDO 3 +#define SC_P_SPI0_SDI_DMA_SPI0_SDI SC_P_SPI0_SDI 0 +#define SC_P_SPI0_SDI_AUD_SAI0_RXD SC_P_SPI0_SDI 1 +#define SC_P_SPI0_SDI_LSIO_GPIO3_IO04 SC_P_SPI0_SDI 3 +#define SC_P_SPI0_CS0_DMA_SPI0_CS0 SC_P_SPI0_CS0 0 +#define SC_P_SPI0_CS0_AUD_SAI0_RXFS SC_P_SPI0_CS0 1 +#define SC_P_SPI0_CS0_LSIO_GPIO3_IO05 SC_P_SPI0_CS0 3 +#define SC_P_SPI0_CS1_DMA_SPI0_CS1 SC_P_SPI0_CS1 0 +#define SC_P_SPI0_CS1_AUD_SAI0_TXC SC_P_SPI0_CS1 1 +#define SC_P_SPI0_CS1_LSIO_GPIO3_IO06 SC_P_SPI0_CS1 3 +#define SC_P_SPI2_SCK_DMA_SPI2_SCK SC_P_SPI2_SCK 0 +#define SC_P_SPI2_SCK_LSIO_GPIO3_IO07 SC_P_SPI2_SCK 3 +#define SC_P_SPI2_SDO_DMA_SPI2_SDO SC_P_SPI2_SDO 0 +#define SC_P_SPI2_SDO_LSIO_GPIO3_IO08 SC_P_SPI2_SDO 3 +#define SC_P_SPI2_SDI_DMA_SPI2_SDI SC_P_SPI2_SDI 0 +#define SC_P_SPI2_SDI_LSIO_GPIO3_IO09 SC_P_SPI2_SDI 3 +#define SC_P_SPI2_CS0_DMA_SPI2_CS0 SC_P_SPI2_CS0 0 +#define SC_P_SPI2_CS0_LSIO_GPIO3_IO10 SC_P_SPI2_CS0 3 +#define SC_P_SPI2_CS1_DMA_SPI2_CS1 SC_P_SPI2_CS1 0 +#define SC_P_SPI2_CS1_AUD_SAI0_TXFS SC_P_SPI2_CS1 1 +#define SC_P_SPI2_CS1_LSIO_GPIO3_IO11 SC_P_SPI2_CS1 3 +#define SC_P_SAI1_RXC_AUD_SAI1_RXC SC_P_SAI1_RXC 0 +#define SC_P_SAI1_RXC_AUD_SAI0_TXD SC_P_SAI1_RXC 1 +#define SC_P_SAI1_RXC_LSIO_GPIO3_IO12 SC_P_SAI1_RXC 3 +#define SC_P_SAI1_RXD_AUD_SAI1_RXD SC_P_SAI1_RXD 0 +#define SC_P_SAI1_RXD_AUD_SAI0_TXFS SC_P_SAI1_RXD 1 +#define SC_P_SAI1_RXD_LSIO_GPIO3_IO13 SC_P_SAI1_RXD 3 +#define SC_P_SAI1_RXFS_AUD_SAI1_RXFS SC_P_SAI1_RXFS 0 +#define SC_P_SAI1_RXFS_AUD_SAI0_RXD SC_P_SAI1_RXFS 1 +#define SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 SC_P_SAI1_RXFS 3 +#define SC_P_SAI1_TXC_AUD_SAI1_TXC SC_P_SAI1_TXC 0 +#define SC_P_SAI1_TXC_AUD_SAI0_TXC SC_P_SAI1_TXC 1 +#define SC_P_SAI1_TXC_LSIO_GPIO3_IO15 SC_P_SAI1_TXC 3 +#define SC_P_SAI1_TXD_AUD_SAI1_TXD SC_P_SAI1_TXD 0 +#define SC_P_SAI1_TXD_AUD_SAI1_RXC SC_P_SAI1_TXD 1 +#define SC_P_SAI1_TXD_LSIO_GPIO3_IO16 SC_P_SAI1_TXD 3 +#define SC_P_SAI1_TXFS_AUD_SAI1_TXFS SC_P_SAI1_TXFS 0 +#define SC_P_SAI1_TXFS_AUD_SAI1_RXFS SC_P_SAI1_TXFS 1 +#define SC_P_SAI1_TXFS_LSIO_GPIO3_IO17 SC_P_SAI1_TXFS 3 +#define SC_P_ADC_IN7_DMA_ADC1_IN3 SC_P_ADC_IN7 0 +#define SC_P_ADC_IN7_DMA_SPI1_CS1 SC_P_ADC_IN7 1 +#define SC_P_ADC_IN7_LSIO_KPP0_ROW3 SC_P_ADC_IN7 2 +#define SC_P_ADC_IN7_LSIO_GPIO3_IO25 SC_P_ADC_IN7 3 +#define SC_P_ADC_IN6_DMA_ADC1_IN2 SC_P_ADC_IN6 0 +#define SC_P_ADC_IN6_DMA_SPI1_CS0 SC_P_ADC_IN6 1 +#define SC_P_ADC_IN6_LSIO_KPP0_ROW2 SC_P_ADC_IN6 2 +#define SC_P_ADC_IN6_LSIO_GPIO3_IO24 SC_P_ADC_IN6 3 +#define SC_P_ADC_IN5_DMA_ADC1_IN1 SC_P_ADC_IN5 0 +#define SC_P_ADC_IN5_DMA_SPI1_SDI SC_P_ADC_IN5 1 +#define SC_P_ADC_IN5_LSIO_KPP0_ROW1 SC_P_ADC_IN5 2 +#define SC_P_ADC_IN5_LSIO_GPIO3_IO23 SC_P_ADC_IN5 3 +#define SC_P_ADC_IN4_DMA_ADC1_IN0 SC_P_ADC_IN4 0 +#define SC_P_ADC_IN4_DMA_SPI1_SDO SC_P_ADC_IN4 1 +#define SC_P_ADC_IN4_LSIO_KPP0_ROW0 SC_P_ADC_IN4 2 +#define SC_P_ADC_IN4_LSIO_GPIO3_IO22 SC_P_ADC_IN4 3 +#define SC_P_ADC_IN3_DMA_ADC0_IN3 SC_P_ADC_IN3 0 +#define SC_P_ADC_IN3_DMA_SPI1_SCK SC_P_ADC_IN3 1 +#define SC_P_ADC_IN3_LSIO_KPP0_COL3 SC_P_ADC_IN3 2 +#define SC_P_ADC_IN3_LSIO_GPIO3_IO21 SC_P_ADC_IN3 3 +#define SC_P_ADC_IN2_DMA_ADC0_IN2 SC_P_ADC_IN2 0 +#define SC_P_ADC_IN2_LSIO_KPP0_COL2 SC_P_ADC_IN2 2 +#define SC_P_ADC_IN2_LSIO_GPIO3_IO20 SC_P_ADC_IN2 3 +#define SC_P_ADC_IN1_DMA_ADC0_IN1 SC_P_ADC_IN1 0 +#define SC_P_ADC_IN1_LSIO_KPP0_COL1 SC_P_ADC_IN1 2 +#define SC_P_ADC_IN1_LSIO_GPIO3_IO19 SC_P_ADC_IN1 3 +#define SC_P_ADC_IN0_DMA_ADC0_IN0 SC_P_ADC_IN0 0 +#define SC_P_ADC_IN0_LSIO_KPP0_COL0 SC_P_ADC_IN0 2 +#define SC_P_ADC_IN0_LSIO_GPIO3_IO18 SC_P_ADC_IN0 3 +#define SC_P_MLB_SIG_CONN_MLB_SIG SC_P_MLB_SIG 0 +#define SC_P_MLB_SIG_AUD_SAI3_RXC SC_P_MLB_SIG 1 +#define SC_P_MLB_SIG_LSIO_GPIO3_IO26 SC_P_MLB_SIG 3 +#define SC_P_MLB_CLK_CONN_MLB_CLK SC_P_MLB_CLK 0 +#define SC_P_MLB_CLK_AUD_SAI3_RXFS SC_P_MLB_CLK 1 +#define SC_P_MLB_CLK_LSIO_GPIO3_IO27 SC_P_MLB_CLK 3 +#define SC_P_MLB_DATA_CONN_MLB_DATA SC_P_MLB_DATA 0 +#define SC_P_MLB_DATA_AUD_SAI3_RXD SC_P_MLB_DATA 1 +#define SC_P_MLB_DATA_LSIO_GPIO3_IO28 SC_P_MLB_DATA 3 +#define SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0 +#define SC_P_FLEXCAN0_RX_LSIO_GPIO3_IO29 SC_P_FLEXCAN0_RX 3 +#define SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0 +#define SC_P_FLEXCAN0_TX_LSIO_GPIO3_IO30 SC_P_FLEXCAN0_TX 3 +#define SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0 +#define SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 SC_P_FLEXCAN1_RX 3 +#define SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0 +#define SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 SC_P_FLEXCAN1_TX 3 +#define SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0 +#define SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 SC_P_FLEXCAN2_RX 3 +#define SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0 +#define SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 SC_P_FLEXCAN2_TX 3 +#define SC_P_USB_SS3_TC0_DMA_I2C1_SCL SC_P_USB_SS3_TC0 0 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1 +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 3 +#define SC_P_USB_SS3_TC1_DMA_I2C1_SCL SC_P_USB_SS3_TC1 0 +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1 +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 3 +#define SC_P_USB_SS3_TC2_DMA_I2C1_SDA SC_P_USB_SS3_TC2 0 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1 +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 3 +#define SC_P_USB_SS3_TC3_DMA_I2C1_SDA SC_P_USB_SS3_TC3 0 +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1 +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 3 +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0 +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 SC_P_USDHC1_RESET_B 3 +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0 +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 SC_P_USDHC1_VSELECT 3 +#define SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B SC_P_USDHC2_RESET_B 0 +#define SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 SC_P_USDHC2_RESET_B 3 +#define SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT SC_P_USDHC2_VSELECT 0 +#define SC_P_USDHC2_VSELECT_LSIO_GPIO4_IO10 SC_P_USDHC2_VSELECT 3 +#define SC_P_USDHC2_WP_CONN_USDHC2_WP SC_P_USDHC2_WP 0 +#define SC_P_USDHC2_WP_LSIO_GPIO4_IO11 SC_P_USDHC2_WP 3 +#define SC_P_USDHC2_CD_B_CONN_USDHC2_CD_B SC_P_USDHC2_CD_B 0 +#define SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 SC_P_USDHC2_CD_B 3 +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0 +#define SC_P_ENET0_MDIO_DMA_I2C4_SDA SC_P_ENET0_MDIO 1 +#define SC_P_ENET0_MDIO_LSIO_GPIO4_IO13 SC_P_ENET0_MDIO 3 +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0 +#define SC_P_ENET0_MDC_DMA_I2C4_SCL SC_P_ENET0_MDC 1 +#define SC_P_ENET0_MDC_LSIO_GPIO4_IO14 SC_P_ENET0_MDC 3 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1 +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 SC_P_ENET0_REFCLK_125M_25M 3 +#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M SC_P_ENET1_REFCLK_125M_25M 0 +#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET1_REFCLK_125M_25M 1 +#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 SC_P_ENET1_REFCLK_125M_25M 3 +#define SC_P_ENET1_MDIO_CONN_ENET1_MDIO SC_P_ENET1_MDIO 0 +#define SC_P_ENET1_MDIO_DMA_I2C4_SDA SC_P_ENET1_MDIO 1 +#define SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 SC_P_ENET1_MDIO 3 +#define SC_P_ENET1_MDC_CONN_ENET1_MDC SC_P_ENET1_MDC 0 +#define SC_P_ENET1_MDC_DMA_I2C4_SCL SC_P_ENET1_MDC 1 +#define SC_P_ENET1_MDC_LSIO_GPIO4_IO18 SC_P_ENET1_MDC 3 +#define SC_P_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI1A_SS0_B 0 +#define SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 SC_P_QSPI1A_SS0_B 3 +#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI1A_SS1_B 0 +#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 SC_P_QSPI1A_SS1_B 1 +#define SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 SC_P_QSPI1A_SS1_B 3 +#define SC_P_QSPI1A_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI1A_SCLK 0 +#define SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 SC_P_QSPI1A_SCLK 3 +#define SC_P_QSPI1A_DQS_LSIO_QSPI1A_DQS SC_P_QSPI1A_DQS 0 +#define SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 SC_P_QSPI1A_DQS 3 +#define SC_P_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI1A_DATA3 0 +#define SC_P_QSPI1A_DATA3_DMA_I2C1_SDA SC_P_QSPI1A_DATA3 1 +#define SC_P_QSPI1A_DATA3_CONN_USB_OTG1_OC SC_P_QSPI1A_DATA3 2 +#define SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 SC_P_QSPI1A_DATA3 3 +#define SC_P_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI1A_DATA2 0 +#define SC_P_QSPI1A_DATA2_DMA_I2C1_SCL SC_P_QSPI1A_DATA2 1 +#define SC_P_QSPI1A_DATA2_CONN_USB_OTG2_PWR SC_P_QSPI1A_DATA2 2 +#define SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 SC_P_QSPI1A_DATA2 3 +#define SC_P_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI1A_DATA1 0 +#define SC_P_QSPI1A_DATA1_DMA_I2C1_SDA SC_P_QSPI1A_DATA1 1 +#define SC_P_QSPI1A_DATA1_CONN_USB_OTG2_OC SC_P_QSPI1A_DATA1 2 +#define SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 SC_P_QSPI1A_DATA1 3 +#define SC_P_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI1A_DATA0 0 +#define SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 SC_P_QSPI1A_DATA0 3 +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0 +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0 +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0 +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0 +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0 +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 SC_P_QSPI0A_SS1_B 1 +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0 +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 SC_P_QSPI0B_SS1_B 1 +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0 +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 SC_P_PCIE_CTRL0_CLKREQ_B 3 +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0 +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 SC_P_PCIE_CTRL0_WAKE_B 3 +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0 +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 SC_P_PCIE_CTRL0_PERST_B 3 +#define SC_P_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B SC_P_PCIE_CTRL1_CLKREQ_B 0 +#define SC_P_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA SC_P_PCIE_CTRL1_CLKREQ_B 1 +#define SC_P_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC SC_P_PCIE_CTRL1_CLKREQ_B 2 +#define SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 SC_P_PCIE_CTRL1_CLKREQ_B 3 +#define SC_P_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B SC_P_PCIE_CTRL1_WAKE_B 0 +#define SC_P_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_WAKE_B 1 +#define SC_P_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR SC_P_PCIE_CTRL1_WAKE_B 2 +#define SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 SC_P_PCIE_CTRL1_WAKE_B 3 +#define SC_P_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B SC_P_PCIE_CTRL1_PERST_B 0 +#define SC_P_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_PERST_B 1 +#define SC_P_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR SC_P_PCIE_CTRL1_PERST_B 2 +#define SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 SC_P_PCIE_CTRL1_PERST_B 3 +#define SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA SC_P_USB_HSIC0_DATA 0 +#define SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA SC_P_USB_HSIC0_DATA 1 +#define SC_P_USB_HSIC0_DATA_LSIO_GPIO5_IO01 SC_P_USB_HSIC0_DATA 3 +#define SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE SC_P_USB_HSIC0_STROBE 0 +#define SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL SC_P_USB_HSIC0_STROBE 1 +#define SC_P_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 SC_P_USB_HSIC0_STROBE 3 +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0 +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1 +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0 +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1 +#define SC_P_EMMC0_CMD_AUD_MQS_R SC_P_EMMC0_CMD 2 +#define SC_P_EMMC0_CMD_LSIO_GPIO5_IO03 SC_P_EMMC0_CMD 3 +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0 +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1 +#define SC_P_EMMC0_DATA0_LSIO_GPIO5_IO04 SC_P_EMMC0_DATA0 3 +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0 +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1 +#define SC_P_EMMC0_DATA1_LSIO_GPIO5_IO05 SC_P_EMMC0_DATA1 3 +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0 +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1 +#define SC_P_EMMC0_DATA2_LSIO_GPIO5_IO06 SC_P_EMMC0_DATA2 3 +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0 +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1 +#define SC_P_EMMC0_DATA3_LSIO_GPIO5_IO07 SC_P_EMMC0_DATA3 3 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0 +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1 +#define SC_P_EMMC0_DATA4_LSIO_GPIO5_IO08 SC_P_EMMC0_DATA4 3 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0 +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1 +#define SC_P_EMMC0_DATA5_LSIO_GPIO5_IO09 SC_P_EMMC0_DATA5 3 +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0 +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1 +#define SC_P_EMMC0_DATA6_LSIO_GPIO5_IO10 SC_P_EMMC0_DATA6 3 +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0 +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1 +#define SC_P_EMMC0_DATA7_LSIO_GPIO5_IO11 SC_P_EMMC0_DATA7 3 +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0 +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1 +#define SC_P_EMMC0_STROBE_LSIO_GPIO5_IO12 SC_P_EMMC0_STROBE 3 +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0 +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1 +#define SC_P_EMMC0_RESET_B_CONN_USDHC1_VSELECT SC_P_EMMC0_RESET_B 2 +#define SC_P_EMMC0_RESET_B_LSIO_GPIO5_IO13 SC_P_EMMC0_RESET_B 3 +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0 +#define SC_P_USDHC1_CLK_AUD_MQS_R SC_P_USDHC1_CLK 1 +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0 +#define SC_P_USDHC1_CMD_AUD_MQS_L SC_P_USDHC1_CMD 1 +#define SC_P_USDHC1_CMD_LSIO_GPIO5_IO14 SC_P_USDHC1_CMD 3 +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0 +#define SC_P_USDHC1_DATA0_CONN_NAND_RE_N SC_P_USDHC1_DATA0 1 +#define SC_P_USDHC1_DATA0_LSIO_GPIO5_IO15 SC_P_USDHC1_DATA0 3 +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0 +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_P SC_P_USDHC1_DATA1 1 +#define SC_P_USDHC1_DATA1_LSIO_GPIO5_IO16 SC_P_USDHC1_DATA1 3 +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0 +#define SC_P_USDHC1_DATA2_CONN_NAND_DQS_N SC_P_USDHC1_DATA2 1 +#define SC_P_USDHC1_DATA2_LSIO_GPIO5_IO17 SC_P_USDHC1_DATA2 3 +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0 +#define SC_P_USDHC1_DATA3_CONN_NAND_DQS_P SC_P_USDHC1_DATA3 1 +#define SC_P_USDHC1_DATA3_LSIO_GPIO5_IO18 SC_P_USDHC1_DATA3 3 +#define SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 SC_P_USDHC1_DATA4 0 +#define SC_P_USDHC1_DATA4_CONN_NAND_CE0_B SC_P_USDHC1_DATA4 1 +#define SC_P_USDHC1_DATA4_AUD_MQS_R SC_P_USDHC1_DATA4 2 +#define SC_P_USDHC1_DATA4_LSIO_GPIO5_IO19 SC_P_USDHC1_DATA4 3 +#define SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 SC_P_USDHC1_DATA5 0 +#define SC_P_USDHC1_DATA5_CONN_NAND_RE_B SC_P_USDHC1_DATA5 1 +#define SC_P_USDHC1_DATA5_AUD_MQS_L SC_P_USDHC1_DATA5 2 +#define SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20 SC_P_USDHC1_DATA5 3 +#define SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 SC_P_USDHC1_DATA6 0 +#define SC_P_USDHC1_DATA6_CONN_NAND_WE_B SC_P_USDHC1_DATA6 1 +#define SC_P_USDHC1_DATA6_CONN_USDHC1_WP SC_P_USDHC1_DATA6 2 +#define SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 SC_P_USDHC1_DATA6 3 +#define SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 SC_P_USDHC1_DATA7 0 +#define SC_P_USDHC1_DATA7_CONN_NAND_ALE SC_P_USDHC1_DATA7 1 +#define SC_P_USDHC1_DATA7_CONN_USDHC1_CD_B SC_P_USDHC1_DATA7 2 +#define SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 SC_P_USDHC1_DATA7 3 +#define SC_P_USDHC1_STROBE_CONN_USDHC1_STROBE SC_P_USDHC1_STROBE 0 +#define SC_P_USDHC1_STROBE_CONN_NAND_CE1_B SC_P_USDHC1_STROBE 1 +#define SC_P_USDHC1_STROBE_CONN_USDHC1_RESET_B SC_P_USDHC1_STROBE 2 +#define SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 SC_P_USDHC1_STROBE 3 +#define SC_P_USDHC2_CLK_CONN_USDHC2_CLK SC_P_USDHC2_CLK 0 +#define SC_P_USDHC2_CLK_AUD_MQS_R SC_P_USDHC2_CLK 1 +#define SC_P_USDHC2_CLK_LSIO_GPIO5_IO24 SC_P_USDHC2_CLK 3 +#define SC_P_USDHC2_CMD_CONN_USDHC2_CMD SC_P_USDHC2_CMD 0 +#define SC_P_USDHC2_CMD_AUD_MQS_L SC_P_USDHC2_CMD 1 +#define SC_P_USDHC2_CMD_LSIO_GPIO5_IO25 SC_P_USDHC2_CMD 3 +#define SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 SC_P_USDHC2_DATA0 0 +#define SC_P_USDHC2_DATA0_DMA_UART4_RX SC_P_USDHC2_DATA0 1 +#define SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 SC_P_USDHC2_DATA0 3 +#define SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 SC_P_USDHC2_DATA1 0 +#define SC_P_USDHC2_DATA1_DMA_UART4_TX SC_P_USDHC2_DATA1 1 +#define SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 SC_P_USDHC2_DATA1 3 +#define SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 SC_P_USDHC2_DATA2 0 +#define SC_P_USDHC2_DATA2_DMA_UART4_CTS_B SC_P_USDHC2_DATA2 1 +#define SC_P_USDHC2_DATA2_LSIO_GPIO5_IO28 SC_P_USDHC2_DATA2 3 +#define SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 SC_P_USDHC2_DATA3 0 +#define SC_P_USDHC2_DATA3_DMA_UART4_RTS_B SC_P_USDHC2_DATA3 1 +#define SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29 SC_P_USDHC2_DATA3 3 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2 +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 SC_P_ENET0_RGMII_TXC 3 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0 +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 SC_P_ENET0_RGMII_TX_CTL 3 +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0 +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 SC_P_ENET0_RGMII_TXD0 3 +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0 +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 SC_P_ENET0_RGMII_TXD1 3 +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0 +#define SC_P_ENET0_RGMII_TXD2_DMA_UART3_TX SC_P_ENET0_RGMII_TXD2 1 +#define SC_P_ENET0_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET0_RGMII_TXD2 2 +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 SC_P_ENET0_RGMII_TXD2 3 +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0 +#define SC_P_ENET0_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET0_RGMII_TXD3 1 +#define SC_P_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET0_RGMII_TXD3 2 +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 SC_P_ENET0_RGMII_TXD3 3 +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0 +#define SC_P_ENET0_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET0_RGMII_RXC 1 +#define SC_P_ENET0_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET0_RGMII_RXC 2 +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 SC_P_ENET0_RGMII_RXC 3 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0 +#define SC_P_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET0_RGMII_RX_CTL 2 +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 SC_P_ENET0_RGMII_RX_CTL 3 +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0 +#define SC_P_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET0_RGMII_RXD0 2 +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 SC_P_ENET0_RGMII_RXD0 3 +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0 +#define SC_P_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET0_RGMII_RXD1 2 +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 SC_P_ENET0_RGMII_RXD1 3 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1 +#define SC_P_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET0_RGMII_RXD2 2 +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 SC_P_ENET0_RGMII_RXD2 3 +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0 +#define SC_P_ENET0_RGMII_RXD3_DMA_UART3_RX SC_P_ENET0_RGMII_RXD3 1 +#define SC_P_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET0_RGMII_RXD3 2 +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 SC_P_ENET0_RGMII_RXD3 3 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC SC_P_ENET1_RGMII_TXC 0 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT SC_P_ENET1_RGMII_TXC 1 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN SC_P_ENET1_RGMII_TXC 2 +#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 SC_P_ENET1_RGMII_TXC 3 +#define SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL SC_P_ENET1_RGMII_TX_CTL 0 +#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 SC_P_ENET1_RGMII_TX_CTL 3 +#define SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 SC_P_ENET1_RGMII_TXD0 0 +#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 SC_P_ENET1_RGMII_TXD0 3 +#define SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 SC_P_ENET1_RGMII_TXD1 0 +#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 SC_P_ENET1_RGMII_TXD1 3 +#define SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 SC_P_ENET1_RGMII_TXD2 0 +#define SC_P_ENET1_RGMII_TXD2_DMA_UART3_TX SC_P_ENET1_RGMII_TXD2 1 +#define SC_P_ENET1_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET1_RGMII_TXD2 2 +#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 SC_P_ENET1_RGMII_TXD2 3 +#define SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 SC_P_ENET1_RGMII_TXD3 0 +#define SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET1_RGMII_TXD3 1 +#define SC_P_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET1_RGMII_TXD3 2 +#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 SC_P_ENET1_RGMII_TXD3 3 +#define SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC SC_P_ENET1_RGMII_RXC 0 +#define SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET1_RGMII_RXC 1 +#define SC_P_ENET1_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET1_RGMII_RXC 2 +#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 SC_P_ENET1_RGMII_RXC 3 +#define SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL SC_P_ENET1_RGMII_RX_CTL 0 +#define SC_P_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET1_RGMII_RX_CTL 2 +#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 SC_P_ENET1_RGMII_RX_CTL 3 +#define SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 SC_P_ENET1_RGMII_RXD0 0 +#define SC_P_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET1_RGMII_RXD0 2 +#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 SC_P_ENET1_RGMII_RXD0 3 +#define SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 SC_P_ENET1_RGMII_RXD1 0 +#define SC_P_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET1_RGMII_RXD1 2 +#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 SC_P_ENET1_RGMII_RXD1 3 +#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 SC_P_ENET1_RGMII_RXD2 0 +#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER SC_P_ENET1_RGMII_RXD2 1 +#define SC_P_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET1_RGMII_RXD2 2 +#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 SC_P_ENET1_RGMII_RXD2 3 +#define SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 SC_P_ENET1_RGMII_RXD3 0 +#define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX SC_P_ENET1_RGMII_RXD3 1 +#define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET1_RGMII_RXD3 2 +#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3 +/*@}*/ + +/*! + * @name Fake Pad Mux Definitions + * format: name padid 0 + */ +/*@{*/ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0 +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO_PAD SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 0 +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD SC_P_COMP_CTL_GPIO_3V3_USB3IO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 +/*@}*/ + +#endif /* SC_PADS_H */ + diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h new file mode 100644 index 00000000000..b152ddde4fe --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h @@ -0,0 +1,794 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file used to configure SoC pad list. + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B 0 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */ +#define SC_P_PCIE_CTRL0_WAKE_B 2 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /*!< */ +#define SC_P_USB_SS3_TC0 4 /*!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 5 /*!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 6 /*!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 7 /*!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /*!< */ +#define SC_P_EMMC0_CLK 9 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ +#define SC_P_EMMC0_CMD 10 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ +#define SC_P_EMMC0_DATA0 11 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ +#define SC_P_EMMC0_DATA1 12 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ +#define SC_P_EMMC0_DATA2 13 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ +#define SC_P_EMMC0_DATA3 14 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /*!< */ +#define SC_P_EMMC0_DATA4 16 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */ +#define SC_P_EMMC0_DATA5 17 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */ +#define SC_P_EMMC0_DATA6 18 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */ +#define SC_P_EMMC0_DATA7 19 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */ +#define SC_P_EMMC0_STROBE 20 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */ +#define SC_P_EMMC0_RESET_B 21 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /*!< */ +#define SC_P_USDHC1_RESET_B 23 /*!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */ +#define SC_P_USDHC1_VSELECT 24 /*!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */ +#define SC_P_CTL_NAND_RE_P_N 25 /*!< */ +#define SC_P_USDHC1_WP 26 /*!< CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */ +#define SC_P_USDHC1_CD_B 27 /*!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_CTL_NAND_DQS_P_N 28 /*!< */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /*!< */ +#define SC_P_USDHC1_CLK 30 /*!< CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ +#define SC_P_USDHC1_CMD 31 /*!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ +#define SC_P_USDHC1_DATA0 32 /*!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */ +#define SC_P_USDHC1_DATA1 33 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */ +#define SC_P_USDHC1_DATA2 34 /*!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */ +#define SC_P_USDHC1_DATA3 35 /*!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /*!< */ +#define SC_P_ENET0_RGMII_TXC 37 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */ +#define SC_P_ENET0_RGMII_TX_CTL 38 /*!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ +#define SC_P_ENET0_RGMII_TXD0 39 /*!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */ +#define SC_P_ENET0_RGMII_TXD1 40 /*!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */ +#define SC_P_ENET0_RGMII_TXD2 41 /*!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */ +#define SC_P_ENET0_RGMII_TXD3 42 /*!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /*!< */ +#define SC_P_ENET0_RGMII_RXC 44 /*!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */ +#define SC_P_ENET0_RGMII_RX_CTL 45 /*!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */ +#define SC_P_ENET0_RGMII_RXD0 46 /*!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ +#define SC_P_ENET0_RGMII_RXD1 47 /*!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ +#define SC_P_ENET0_RGMII_RXD2 48 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */ +#define SC_P_ENET0_RGMII_RXD3 49 /*!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /*!< */ +#define SC_P_ENET0_REFCLK_125M_25M 51 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */ +#define SC_P_ENET0_MDIO 52 /*!< CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */ +#define SC_P_ENET0_MDC 53 /*!< CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /*!< */ +#define SC_P_ESAI0_FSR 55 /*!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */ +#define SC_P_ESAI0_FST 56 /*!< ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */ +#define SC_P_ESAI0_SCKR 57 /*!< ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */ +#define SC_P_ESAI0_SCKT 58 /*!< ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */ +#define SC_P_ESAI0_TX0 59 /*!< ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */ +#define SC_P_ESAI0_TX1 60 /*!< ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */ +#define SC_P_ESAI0_TX2_RX3 61 /*!< ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */ +#define SC_P_ESAI0_TX3_RX2 62 /*!< ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */ +#define SC_P_ESAI0_TX4_RX1 63 /*!< ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */ +#define SC_P_ESAI0_TX5_RX0 64 /*!< ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */ +#define SC_P_SPDIF0_RX 65 /*!< ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */ +#define SC_P_SPDIF0_TX 66 /*!< ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */ +#define SC_P_SPDIF0_EXT_CLK 67 /*!< ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /*!< */ +#define SC_P_SPI3_SCK 69 /*!< ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */ +#define SC_P_SPI3_SDO 70 /*!< ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */ +#define SC_P_SPI3_SDI 71 /*!< ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */ +#define SC_P_SPI3_CS0 72 /*!< ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */ +#define SC_P_SPI3_CS1 73 /*!< ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */ +#define SC_P_MCLK_IN1 74 /*!< ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */ +#define SC_P_MCLK_IN0 75 /*!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */ +#define SC_P_MCLK_OUT0 76 /*!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */ +#define SC_P_UART1_TX 77 /*!< ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */ +#define SC_P_UART1_RX 78 /*!< ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */ +#define SC_P_UART1_RTS_B 79 /*!< ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */ +#define SC_P_UART1_CTS_B 80 /*!< ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /*!< */ +#define SC_P_SAI0_TXD 82 /*!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */ +#define SC_P_SAI0_TXC 83 /*!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */ +#define SC_P_SAI0_RXD 84 /*!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */ +#define SC_P_SAI0_TXFS 85 /*!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */ +#define SC_P_SAI1_RXD 86 /*!< ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */ +#define SC_P_SAI1_RXC 87 /*!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */ +#define SC_P_SAI1_RXFS 88 /*!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */ +#define SC_P_SPI2_CS0 89 /*!< ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */ +#define SC_P_SPI2_SDO 90 /*!< ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */ +#define SC_P_SPI2_SDI 91 /*!< ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */ +#define SC_P_SPI2_SCK 92 /*!< ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */ +#define SC_P_SPI0_SCK 93 /*!< ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */ +#define SC_P_SPI0_SDI 94 /*!< ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */ +#define SC_P_SPI0_SDO 95 /*!< ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */ +#define SC_P_SPI0_CS1 96 /*!< ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */ +#define SC_P_SPI0_CS0 97 /*!< ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /*!< */ +#define SC_P_ADC_IN1 99 /*!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */ +#define SC_P_ADC_IN0 100 /*!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */ +#define SC_P_ADC_IN3 101 /*!< ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */ +#define SC_P_ADC_IN2 102 /*!< ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */ +#define SC_P_ADC_IN5 103 /*!< ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */ +#define SC_P_ADC_IN4 104 /*!< ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */ +#define SC_P_FLEXCAN0_RX 105 /*!< ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */ +#define SC_P_FLEXCAN0_TX 106 /*!< ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */ +#define SC_P_FLEXCAN1_RX 107 /*!< ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */ +#define SC_P_FLEXCAN1_TX 108 /*!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */ +#define SC_P_FLEXCAN2_RX 109 /*!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */ +#define SC_P_FLEXCAN2_TX 110 /*!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */ +#define SC_P_UART0_RX 111 /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */ +#define SC_P_UART0_TX 112 /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */ +#define SC_P_UART2_TX 113 /*!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */ +#define SC_P_UART2_RX 114 /*!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /*!< */ +#define SC_P_MIPI_DSI0_I2C0_SCL 116 /*!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 117 /*!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_DSI0_GPIO0_00 118 /*!< MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_DSI0_GPIO0_01 119 /*!< MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 120 /*!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 121 /*!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_DSI1_GPIO0_00 122 /*!< MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_DSI1_GPIO0_01 123 /*!< MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /*!< */ +#define SC_P_JTAG_TRST_B 125 /*!< SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SCL 126 /*!< SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */ +#define SC_P_PMIC_I2C_SDA 127 /*!< SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */ +#define SC_P_PMIC_INT_B 128 /*!< SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 129 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */ +#define SC_P_SCU_GPIO0_01 130 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */ +#define SC_P_SCU_PMIC_STANDBY 131 /*!< SCU.DSC.PMIC_STANDBY */ +#define SC_P_SCU_BOOT_MODE0 132 /*!< SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 133 /*!< SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 134 /*!< SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */ +#define SC_P_SCU_BOOT_MODE3 135 /*!< SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */ +#define SC_P_CSI_D00 136 /*!< CI_PI.D02, ADMA.SAI0.RXC */ +#define SC_P_CSI_D01 137 /*!< CI_PI.D03, ADMA.SAI0.RXD */ +#define SC_P_CSI_D02 138 /*!< CI_PI.D04, ADMA.SAI0.RXFS */ +#define SC_P_CSI_D03 139 /*!< CI_PI.D05, ADMA.SAI2.RXC */ +#define SC_P_CSI_D04 140 /*!< CI_PI.D06, ADMA.SAI2.RXD */ +#define SC_P_CSI_D05 141 /*!< CI_PI.D07, ADMA.SAI2.RXFS */ +#define SC_P_CSI_D06 142 /*!< CI_PI.D08, ADMA.SAI3.RXC */ +#define SC_P_CSI_D07 143 /*!< CI_PI.D09, ADMA.SAI3.RXD */ +#define SC_P_CSI_HSYNC 144 /*!< CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */ +#define SC_P_CSI_VSYNC 145 /*!< CI_PI.VSYNC, CI_PI.D01 */ +#define SC_P_CSI_PCLK 146 /*!< CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */ +#define SC_P_CSI_MCLK 147 /*!< CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */ +#define SC_P_CSI_EN 148 /*!< CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */ +#define SC_P_CSI_RESET 149 /*!< CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /*!< */ +#define SC_P_MIPI_CSI0_MCLK_OUT 151 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 152 /*!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 153 /*!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */ +#define SC_P_MIPI_CSI0_GPIO0_01 154 /*!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */ +#define SC_P_MIPI_CSI0_GPIO0_00 155 /*!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */ +#define SC_P_QSPI0A_DATA0 156 /*!< LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ +#define SC_P_QSPI0A_DATA1 157 /*!< LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ +#define SC_P_QSPI0A_DATA2 158 /*!< LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ +#define SC_P_QSPI0A_DATA3 159 /*!< LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ +#define SC_P_QSPI0A_DQS 160 /*!< LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ +#define SC_P_QSPI0A_SS0_B 161 /*!< LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ +#define SC_P_QSPI0A_SS1_B 162 /*!< LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */ +#define SC_P_QSPI0A_SCLK 163 /*!< LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /*!< */ +#define SC_P_QSPI0B_SCLK 165 /*!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */ +#define SC_P_QSPI0B_DATA0 166 /*!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */ +#define SC_P_QSPI0B_DATA1 167 /*!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */ +#define SC_P_QSPI0B_DATA2 168 /*!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */ +#define SC_P_QSPI0B_DATA3 169 /*!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */ +#define SC_P_QSPI0B_DQS 170 /*!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */ +#define SC_P_QSPI0B_SS0_B 171 /*!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */ +#define SC_P_QSPI0B_SS1_B 172 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /*!< */ +/*@}*/ + +/*! + * @name Pad Mux Definitions + * format: name padid padmux + */ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0 +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4 +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0 +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4 +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0 +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4 +#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2 +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4 +#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0 +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1 +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4 +#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2 +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4 +#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0 +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1 +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4 +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0 +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1 +#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4 +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0 +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1 +#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4 +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0 +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1 +#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4 +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0 +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1 +#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4 +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0 +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1 +#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4 +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0 +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1 +#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0 +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3 +#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0 +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3 +#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4 +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0 +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1 +#define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3 +#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4 +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0 +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1 +#define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3 +#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4 +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0 +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1 +#define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3 +#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4 +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0 +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1 +#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4 +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0 +#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1 +#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2 +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4 +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1 +#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3 +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4 +#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0 +#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1 +#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2 +#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4 +#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1 +#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3 +#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4 +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0 +#define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2 +#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4 +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0 +#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1 +#define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2 +#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4 +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0 +#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1 +#define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2 +#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4 +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0 +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1 +#define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2 +#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4 +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0 +#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1 +#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2 +#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4 +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0 +#define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1 +#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2 +#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2 +#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3 +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3 +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4 +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0 +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3 +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4 +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0 +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3 +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4 +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0 +#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1 +#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2 +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3 +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4 +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0 +#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1 +#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2 +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4 +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0 +#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1 +#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2 +#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3 +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3 +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4 +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0 +#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3 +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4 +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0 +#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3 +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1 +#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3 +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4 +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0 +#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2 +#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3 +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2 +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4 +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0 +#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1 +#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2 +#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4 +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0 +#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1 +#define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2 +#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4 +#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0 +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1 +#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2 +#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3 +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4 +#define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0 +#define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1 +#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2 +#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3 +#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4 +#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0 +#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2 +#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3 +#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4 +#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0 +#define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1 +#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2 +#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3 +#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4 +#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0 +#define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1 +#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2 +#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3 +#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4 +#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0 +#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2 +#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3 +#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4 +#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0 +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1 +#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2 +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3 +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4 +#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0 +#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2 +#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3 +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4 +#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0 +#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2 +#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3 +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4 +#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0 +#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2 +#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3 +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4 +#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0 +#define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1 +#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2 +#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3 +#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4 +#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0 +#define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1 +#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2 +#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3 +#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4 +#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0 +#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2 +#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3 +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4 +#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0 +#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2 +#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4 +#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0 +#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2 +#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4 +#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0 +#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2 +#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4 +#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0 +#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1 +#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2 +#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4 +#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0 +#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1 +#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2 +#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3 +#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4 +#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0 +#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1 +#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2 +#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3 +#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4 +#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0 +#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1 +#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2 +#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3 +#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4 +#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0 +#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1 +#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2 +#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3 +#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4 +#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0 +#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1 +#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2 +#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4 +#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0 +#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1 +#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2 +#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3 +#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4 +#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0 +#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1 +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2 +#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3 +#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4 +#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0 +#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1 +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2 +#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3 +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4 +#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0 +#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1 +#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2 +#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3 +#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4 +#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0 +#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1 +#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2 +#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3 +#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4 +#define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0 +#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1 +#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2 +#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3 +#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4 +#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0 +#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1 +#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2 +#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4 +#define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0 +#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1 +#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2 +#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3 +#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4 +#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0 +#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1 +#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3 +#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4 +#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0 +#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1 +#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3 +#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4 +#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0 +#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4 +#define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0 +#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4 +#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0 +#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4 +#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0 +#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4 +#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0 +#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1 +#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2 +#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3 +#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4 +#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0 +#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1 +#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2 +#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3 +#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4 +#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0 +#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1 +#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2 +#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3 +#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4 +#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0 +#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1 +#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2 +#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3 +#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4 +#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0 +#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1 +#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2 +#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3 +#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4 +#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0 +#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1 +#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2 +#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4 +#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0 +#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1 +#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2 +#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4 +#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0 +#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1 +#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2 +#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3 +#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4 +#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0 +#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1 +#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2 +#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3 +#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4 +#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0 +#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1 +#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2 +#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4 +#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0 +#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1 +#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2 +#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4 +#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0 +#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1 +#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2 +#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3 +#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4 +#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0 +#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1 +#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2 +#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3 +#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4 +#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0 +#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1 +#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2 +#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3 +#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4 +#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0 +#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1 +#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2 +#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3 +#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4 +#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0 +#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1 +#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2 +#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3 +#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4 +#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0 +#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1 +#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2 +#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3 +#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4 +#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0 +#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1 +#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2 +#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 3 +#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4 +#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0 +#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1 +#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2 +#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 3 +#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4 +#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0 +#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1 +#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2 +#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4 +#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0 +#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1 +#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2 +#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1 +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1 +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0 +#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2 +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4 +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0 +#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1 +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1 +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1 +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0 +#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2 +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4 +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0 +#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1 +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4 +#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0 +#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1 +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0 +#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1 +#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4 +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0 +#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1 +#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4 +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0 +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0 +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1 +#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2 +#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3 +#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4 +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0 +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1 +#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2 +#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3 +#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4 +#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0 +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0 +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0 +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0 +#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0 +#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3 +#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0 +#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2 +#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0 +#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2 +#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0 +#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2 +#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0 +#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2 +#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0 +#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2 +#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0 +#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2 +#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0 +#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2 +#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0 +#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2 +#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0 +#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1 +#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2 +#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0 +#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1 +#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0 +#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1 +#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3 +#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4 +#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0 +#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1 +#define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3 +#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4 +#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0 +#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1 +#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2 +#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3 +#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4 +#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0 +#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1 +#define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2 +#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3 +#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4 +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0 +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1 +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1 +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0 +#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1 +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0 +#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1 +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4 +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0 +#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4 +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0 +#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4 +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0 +#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4 +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0 +#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4 +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0 +#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4 +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0 +#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4 +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0 +#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1 +#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2 +#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1 +#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2 +#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1 +#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2 +#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1 +#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2 +#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1 +#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2 +#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4 +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0 +#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1 +#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2 +#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1 +#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2 +#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1 +#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2 +#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4 +/*@}*/ + +/*! + * @name Fake Pad Mux Definitions + * format: name padid 0 + */ +/*@{*/ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD SC_P_COMP_CTL_GPIO_3V3_USB3IO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 +/*@}*/ + +#endif /* SC_PADS_H */ + diff --git a/include/dt-bindings/pinctrl/pins-imx8mm.h b/include/dt-bindings/pinctrl/pins-imx8mm.h new file mode 100644 index 00000000000..849cb303e12 --- /dev/null +++ b/include/dt-bindings/pinctrl/pins-imx8mm.h @@ -0,0 +1,627 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DTS_IMX8MM_PINFUNC_H +#define __DTS_IMX8MM_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ + +#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 +#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 +#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x000 0x12 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 +#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 +#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 +#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 +#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 +#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 +#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 +#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 +#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 +#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 +#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 +#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 +#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 +#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 +#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 +#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 +#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 +#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 +#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 +#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 +#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 +#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 +#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 +#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 + +#endif /* __DTS_IMX8MM_PINFUNC_H */ diff --git a/include/dt-bindings/soc/imx8_hsio.h b/include/dt-bindings/soc/imx8_hsio.h new file mode 100644 index 00000000000..a237ceb8262 --- /dev/null +++ b/include/dt-bindings/soc/imx8_hsio.h @@ -0,0 +1,31 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_IMX8_HSIO_H +#define __DT_BINDINGS_IMX8_HSIO_H + +/* + * imx8qm hsio has pciea, pcieb and sata modules, and hsio + * can be configured to the following different work modes. + * 1 - pciea 2 lanes and one sata ahci port. + * 2 - pciea 1 lane, pcieb 1 lane and one sata ahci port. + * 3 - pciea 2 lanes, pcieb 1 lane. + * Choose one mode, refer to the exact hardware board design. + */ +#define PCIEAX2SATA 1 +#define PCIEAX1PCIEBX1SATA 2 +#define PCIEAX2PCIEBX1 3 + +#endif /* __DT_BINDINGS_IMX8_HSIO_H */ + diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h new file mode 100644 index 00000000000..017fbb74d4f --- /dev/null +++ b/include/dt-bindings/soc/imx8_pd.h @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_IMX8_PD_H +#define __DT_BINDINGS_IMX8_PD_H + +/*! + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +#define PD_DC_0 dc0_power_domain +#define PD_DC_0_PLL_0 dc0_pll0 +#define PD_DC_0_PLL_1 dc0_pll1 +#define PD_LVDS0 lvds0_power_domain +#define PD_LVDS0_I2C0 lvds0_i2c0 +#define PD_LVDS0_I2C1 lvds0_i2c1 +#define PD_LVDS0_PWM lvds0_pwm +#define PD_LVDS0_PWM lvds0_pwm +#define PD_LVDS0_GPIO lvds0_gpio +#define PD_DC_1 dc1_power_domain +#define PD_DC_1_PLL_0 dc1_pll0 +#define PD_DC_1_PLL_1 dc1_pll1 +#define PD_LVDS1 lvds1_power_domain +#define PD_LVDS1_I2C0 lvds1_i2c0 +#define PD_LVDS1_I2C1 lvds1_i2c1 +#define PD_LVDS1_PWM lvds1_pwm +#define PD_LVDS1_GPIO lvds1_gpio + +#define PD_DMA dma_power_domain +#define PD_DMA_SPI_0 dma_spi0 +#define PD_DMA_SPI_1 dma_spi1 +#define PD_DMA_SPI_2 dma_spi2 +#define PD_DMA_SPI_3 dma_spi3 +#define PD_DMA_UART0 dma_lpuart0 +#define PD_DMA_UART1 dma_lpuart1 +#define PD_DMA_UART2 dma_lpuart2 +#define PD_DMA_UART3 dma_lpuart3 +#define PD_DMA_UART4 dma_lpuart4 +#define PD_DMA_EMVSIM_0 dma_emvsim0 +#define PD_DMA_EMVSIM_1 dma_emvsim1 +#define PD_DMA_I2C_0 dma_lpi2c0 +#define PD_DMA_I2C_1 dma_lpi2c1 +#define PD_DMA_I2C_2 dma_lpi2c2 +#define PD_DMA_I2C_3 dma_lpi2c3 +#define PD_DMA_I2C_4 dma_lpi2c4 +#define PD_DMA_ADC_0 dma_adc0 +#define PD_DMA_ADC_1 dma_adc1 +#define PD_DMA_FTM_0 dma_ftm0 +#define PD_DMA_FTM_1 dma_ftm1 +#define PD_DMA_CAN_0 dma_flexcan0 +#define PD_DMA_CAN_1 dma_flexcan1 +#define PD_DMA_CAN_2 dma_flexcan2 +#define PD_DMA_PWM_0 dma_pwm0 +#define PD_DMA_LCD_0 dma_lcd0 + +#define PD_HSIO hsio_power_domain +#define PD_HSIO_PCIE_A hsio_pcie0 +#define PD_HSIO_PCIE_B hsio_pcie1 +#define PD_HSIO_SATA_0 hsio_sata0 +#define PD_HSIO_GPIO hsio_gpio + +#define PD_LCD_0 lcd0_power_domain +#define PD_LCD_0_I2C_0 lcd0_i2c0 +#define PD_LCD_0_I2C_1 lcd0_i2c1 +#define PD_LCD_PWM_0 lcd0_pwm0 + +#define PD_LSIO lsio_power_domain +#define PD_LSIO_GPIO_0 lsio_gpio0 +#define PD_LSIO_GPIO_1 lsio_gpio1 +#define PD_LSIO_GPIO_2 lsio_gpio2 +#define PD_LSIO_GPIO_3 lsio_gpio3 +#define PD_LSIO_GPIO_4 lsio_gpio4 +#define PD_LSIO_GPIO_5 lsio_gpio5 +#define PD_LSIO_GPIO_6 lsio_gpio6 +#define PD_LSIO_GPIO_7 lsio_gpio7 +#define PD_LSIO_GPT_0 lsio_gpt0 +#define PD_LSIO_GPT_1 lsio_gpt1 +#define PD_LSIO_GPT_2 lsio_gpt2 +#define PD_LSIO_GPT_3 lsio_gpt3 +#define PD_LSIO_GPT_4 lsio_gpt4 +#define PD_LSIO_KPP lsio_kpp +#define PD_LSIO_FSPI_0 lsio_fspi0 +#define PD_LSIO_FSPI_1 lsio_fspi1 +#define PD_LSIO_PWM_0 lsio_pwm0 +#define PD_LSIO_PWM_1 lsio_pwm1 +#define PD_LSIO_PWM_2 lsio_pwm2 +#define PD_LSIO_PWM_3 lsio_pwm3 +#define PD_LSIO_PWM_4 lsio_pwm4 +#define PD_LSIO_PWM_5 lsio_pwm5 +#define PD_LSIO_PWM_6 lsio_pwm6 +#define PD_LSIO_PWM_7 lsio_pwm7 +#define PD_LSIO_MU8A lsio_mu8a +#define PD_LSIO_MU9A lsio_mu9a + +#define PD_CONN connectivity_power_domain +#define PD_CONN_SDHC_0 conn_sdhc0 +#define PD_CONN_SDHC_1 conn_sdhc1 +#define PD_CONN_SDHC_2 conn_sdhc2 +#define PD_CONN_ENET_0 conn_enet0 +#define PD_CONN_ENET_1 conn_enet1 +#define PD_CONN_MLB_0 conn_mlb0 +#define PD_CONN_DMA_4_CH0 conn_dma4_ch0 +#define PD_CONN_DMA_4_CH1 conn_dma4_ch1 +#define PD_CONN_DMA_4_CH2 conn_dma4_ch2 +#define PD_CONN_DMA_4_CH3 conn_dma4_ch3 +#define PD_CONN_DMA_4_CH4 conn_dma4_ch4 +#define PD_CONN_USB_0 conn_usb0 +#define PD_CONN_USB_1 conn_usb1 +#define PD_CONN_USB_0_PHY conn_usb0_phy +#define PD_CONN_USB_2 conn_usb2 +#define PD_CONN_USB_2_PHY conn_usb2_phy +#define PD_CONN_NAND conn_nand + +#define PD_AUDIO audio_power_domain +#define PD_AUD_SAI_0 audio_sai0 +#define PD_AUD_SAI_1 audio_sai1 +#define PD_AUD_SAI_2 audio_sai2 +#define PD_AUD_ASRC_0 audio_asrc0 +#define PD_AUD_ASRC_1 audio_asrc1 +#define PD_AUD_ESAI_0 audio_esai0 +#define PD_AUD_ESAI_1 audio_esai1 +#define PD_AUD_SPDIF_0 audio_spdif0 +#define PD_AUD_SPDIF_1 audio_spdif1 +#define PD_AUD_SAI_3 audio_sai3 +#define PD_AUD_SAI_4 audio_sai4 +#define PD_AUD_SAI_5 audio_sai5 +#define PD_AUD_SAI_6 audio_sai6 +#define PD_AUD_SAI_7 audio_sai7 +#define PD_AUD_GPT_5 audio_gpt5 +#define PD_AUD_GPT_6 audio_gpt6 +#define PD_AUD_GPT_7 audio_gpt7 +#define PD_AUD_GPT_8 audio_gpt8 +#define PD_AUD_GPT_9 audio_gpt9 +#define PD_AUD_GPT_10 audio_gpt10 +#define PD_AUD_AMIX audio_amix +#define PD_AUD_MQS_0 audio_mqs0 +#define PD_AUD_HIFI audio_hifi +#define PD_AUD_OCRAM audio_ocram +#define PD_AUD_MCLK_OUT_0 audio_mclkout0 +#define PD_AUD_MCLK_OUT_1 audio_mclkout1 +#define PD_AUD_AUDIO_PLL_0 audio_audiopll0 +#define PD_AUD_AUDIO_PLL_1 audio_audiopll1 +#define PD_AUD_AUDIO_CLK_0 audio_audioclk0 +#define PD_AUD_AUDIO_CLK_1 audio_audioclk1 + +#define PD_IMAGING imaging_power_domain +#define PD_IMAGING_JPEG_DEC imaging_jpeg_dec +#define PD_IMAGING_JPEG_ENC imaging_jpeg_enc +#define PD_IMAGING_PDMA0 PD_IMAGING +#define PD_IMAGING_PDMA1 imaging_pdma1 +#define PD_IMAGING_PDMA2 imaging_pdma2 +#define PD_IMAGING_PDMA3 imaging_pdma3 +#define PD_IMAGING_PDMA4 imaging_pdma4 +#define PD_IMAGING_PDMA5 imaging_pdma5 +#define PD_IMAGING_PDMA6 imaging_pdma6 +#define PD_IMAGING_PDMA7 imaging_pdma7 + +#define PD_MIPI_0_DSI mipi0_dsi_power_domain +#define PD_MIPI_0_DSI_I2C0 mipi0_dsi_i2c0 +#define PD_MIPI_0_DSI_I2C1 mipi0_dsi_i2c1 +#define PD_MIPI_0_DSI_PWM0 mipi0_dsi_pwm0 +#define PD_MIPI_1_DSI mipi1_dsi_power_domain +#define PD_MIPI_1_DSI_I2C0 mipi1_dsi_i2c0 +#define PD_MIPI_1_DSI_I2C1 mipi1_dsi_i2c1 +#define PD_MIPI_1_DSI_PWM0 mipi1_dsi_pwm0 + +#define PD_MIPI_CSI0 mipi_csi0_power_domain +#define PD_MIPI_CSI0_PWM mipi_csi0_pwm +#define PD_MIPI_CSI0_I2C mipi_csi0_i2c +#define PD_MIPI_CSI1 mipi_csi1_power_domain +#define PD_MIPI_CSI1_PWM_0 mipi_csi1_pwm +#define PD_MIPI_CSI1_I2C_0 mipi_csi1_i2c + +#define PD_HDMI hdmi_power_domain +#define PD_HDMI_I2C_0 hdmi_i2c +#define PD_HDMI_PWM_0 hdmi_pwm +#define PD_HDMI_GPIO_0 hdmi_gpio + +#define PD_HDMI_RX hdmi_rx_power_domain +#define PD_HDMI_RX_I2C hdmi_rx_i2c +#define PD_HDMI_RX_PWM hdmi_rx_pwm + +#define PD_CM40 cm40_power_domain +#define PD_CM40_I2C cm40_i2c +#define PD_CM40_INTMUX cm40_intmux + +#endif /* __DT_BINDINGS_IMX8_PD_H */ + diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h new file mode 100644 index 00000000000..6eb0eb0c7d8 --- /dev/null +++ b/include/dt-bindings/soc/imx_rsrc.h @@ -0,0 +1,566 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef DT_BINDINGS_RSCRC_IMX_H +#define DT_BINDINGS_RSCRC_IMX_H + +/*! + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +#define SC_R_A53 0 +#define SC_R_A53_0 1 +#define SC_R_A53_1 2 +#define SC_R_A53_2 3 +#define SC_R_A53_3 4 +#define SC_R_A72 5 +#define SC_R_A72_0 6 +#define SC_R_A72_1 7 +#define SC_R_A72_2 8 +#define SC_R_A72_3 9 +#define SC_R_CCI 10 +#define SC_R_DB 11 +#define SC_R_DRC_0 12 +#define SC_R_DRC_1 13 +#define SC_R_GIC_SMMU 14 +#define SC_R_IRQSTR_M4_0 15 +#define SC_R_IRQSTR_M4_1 16 +#define SC_R_SMMU 17 +#define SC_R_GIC 18 +#define SC_R_DC_0_BLIT0 19 +#define SC_R_DC_0_BLIT1 20 +#define SC_R_DC_0_BLIT2 21 +#define SC_R_DC_0_BLIT_OUT 22 +#define SC_R_PERF 23 +#define SC_R_UNUSED5 24 +#define SC_R_DC_0_WARP 25 +#define SC_R_UNUSED7 26 +#define SC_R_UNUSED8 27 +#define SC_R_DC_0_VIDEO0 28 +#define SC_R_DC_0_VIDEO1 29 +#define SC_R_DC_0_FRAC0 30 +#define SC_R_UNUSED6 31 +#define SC_R_DC_0 32 +#define SC_R_GPU_2_PID0 33 +#define SC_R_DC_0_PLL_0 34 +#define SC_R_DC_0_PLL_1 35 +#define SC_R_DC_1_BLIT0 36 +#define SC_R_DC_1_BLIT1 37 +#define SC_R_DC_1_BLIT2 38 +#define SC_R_DC_1_BLIT_OUT 39 +#define SC_R_UNUSED9 40 +#define SC_R_UNUSED10 41 +#define SC_R_DC_1_WARP 42 +#define SC_R_UNUSED11 43 +#define SC_R_UNUSED12 44 +#define SC_R_DC_1_VIDEO0 45 +#define SC_R_DC_1_VIDEO1 46 +#define SC_R_DC_1_FRAC0 47 +#define SC_R_UNUSED13 48 +#define SC_R_DC_1 49 +#define SC_R_UNUSED14 50 +#define SC_R_DC_1_PLL_0 51 +#define SC_R_DC_1_PLL_1 52 +#define SC_R_SPI_0 53 +#define SC_R_SPI_1 54 +#define SC_R_SPI_2 55 +#define SC_R_SPI_3 56 +#define SC_R_UART_0 57 +#define SC_R_UART_1 58 +#define SC_R_UART_2 59 +#define SC_R_UART_3 60 +#define SC_R_UART_4 61 +#define SC_R_EMVSIM_0 62 +#define SC_R_EMVSIM_1 63 +#define SC_R_DMA_0_CH0 64 +#define SC_R_DMA_0_CH1 65 +#define SC_R_DMA_0_CH2 66 +#define SC_R_DMA_0_CH3 67 +#define SC_R_DMA_0_CH4 68 +#define SC_R_DMA_0_CH5 69 +#define SC_R_DMA_0_CH6 70 +#define SC_R_DMA_0_CH7 71 +#define SC_R_DMA_0_CH8 72 +#define SC_R_DMA_0_CH9 73 +#define SC_R_DMA_0_CH10 74 +#define SC_R_DMA_0_CH11 75 +#define SC_R_DMA_0_CH12 76 +#define SC_R_DMA_0_CH13 77 +#define SC_R_DMA_0_CH14 78 +#define SC_R_DMA_0_CH15 79 +#define SC_R_DMA_0_CH16 80 +#define SC_R_DMA_0_CH17 81 +#define SC_R_DMA_0_CH18 82 +#define SC_R_DMA_0_CH19 83 +#define SC_R_DMA_0_CH20 84 +#define SC_R_DMA_0_CH21 85 +#define SC_R_DMA_0_CH22 86 +#define SC_R_DMA_0_CH23 87 +#define SC_R_DMA_0_CH24 88 +#define SC_R_DMA_0_CH25 89 +#define SC_R_DMA_0_CH26 90 +#define SC_R_DMA_0_CH27 91 +#define SC_R_DMA_0_CH28 92 +#define SC_R_DMA_0_CH29 93 +#define SC_R_DMA_0_CH30 94 +#define SC_R_DMA_0_CH31 95 +#define SC_R_I2C_0 96 +#define SC_R_I2C_1 97 +#define SC_R_I2C_2 98 +#define SC_R_I2C_3 99 +#define SC_R_I2C_4 100 +#define SC_R_ADC_0 101 +#define SC_R_ADC_1 102 +#define SC_R_FTM_0 103 +#define SC_R_FTM_1 104 +#define SC_R_CAN_0 105 +#define SC_R_CAN_1 106 +#define SC_R_CAN_2 107 +#define SC_R_DMA_1_CH0 108 +#define SC_R_DMA_1_CH1 109 +#define SC_R_DMA_1_CH2 110 +#define SC_R_DMA_1_CH3 111 +#define SC_R_DMA_1_CH4 112 +#define SC_R_DMA_1_CH5 113 +#define SC_R_DMA_1_CH6 114 +#define SC_R_DMA_1_CH7 115 +#define SC_R_DMA_1_CH8 116 +#define SC_R_DMA_1_CH9 117 +#define SC_R_DMA_1_CH10 118 +#define SC_R_DMA_1_CH11 119 +#define SC_R_DMA_1_CH12 120 +#define SC_R_DMA_1_CH13 121 +#define SC_R_DMA_1_CH14 122 +#define SC_R_DMA_1_CH15 123 +#define SC_R_DMA_1_CH16 124 +#define SC_R_DMA_1_CH17 125 +#define SC_R_DMA_1_CH18 126 +#define SC_R_DMA_1_CH19 127 +#define SC_R_DMA_1_CH20 128 +#define SC_R_DMA_1_CH21 129 +#define SC_R_DMA_1_CH22 130 +#define SC_R_DMA_1_CH23 131 +#define SC_R_DMA_1_CH24 132 +#define SC_R_DMA_1_CH25 133 +#define SC_R_DMA_1_CH26 134 +#define SC_R_DMA_1_CH27 135 +#define SC_R_DMA_1_CH28 136 +#define SC_R_DMA_1_CH29 137 +#define SC_R_DMA_1_CH30 138 +#define SC_R_DMA_1_CH31 139 +#define SC_R_UNUSED1 140 +#define SC_R_UNUSED2 141 +#define SC_R_UNUSED3 142 +#define SC_R_UNUSED4 143 +#define SC_R_GPU_0_PID0 144 +#define SC_R_GPU_0_PID1 145 +#define SC_R_GPU_0_PID2 146 +#define SC_R_GPU_0_PID3 147 +#define SC_R_GPU_1_PID0 148 +#define SC_R_GPU_1_PID1 149 +#define SC_R_GPU_1_PID2 150 +#define SC_R_GPU_1_PID3 151 +#define SC_R_PCIE_A 152 +#define SC_R_SERDES_0 153 +#define SC_R_MATCH_0 154 +#define SC_R_MATCH_1 155 +#define SC_R_MATCH_2 156 +#define SC_R_MATCH_3 157 +#define SC_R_MATCH_4 158 +#define SC_R_MATCH_5 159 +#define SC_R_MATCH_6 160 +#define SC_R_MATCH_7 161 +#define SC_R_MATCH_8 162 +#define SC_R_MATCH_9 163 +#define SC_R_MATCH_10 164 +#define SC_R_MATCH_11 165 +#define SC_R_MATCH_12 166 +#define SC_R_MATCH_13 167 +#define SC_R_MATCH_14 168 +#define SC_R_PCIE_B 169 +#define SC_R_SATA_0 170 +#define SC_R_SERDES_1 171 +#define SC_R_HSIO_GPIO 172 +#define SC_R_MATCH_15 173 +#define SC_R_MATCH_16 174 +#define SC_R_MATCH_17 175 +#define SC_R_MATCH_18 176 +#define SC_R_MATCH_19 177 +#define SC_R_MATCH_20 178 +#define SC_R_MATCH_21 179 +#define SC_R_MATCH_22 180 +#define SC_R_MATCH_23 181 +#define SC_R_MATCH_24 182 +#define SC_R_MATCH_25 183 +#define SC_R_MATCH_26 184 +#define SC_R_MATCH_27 185 +#define SC_R_MATCH_28 186 +#define SC_R_LCD_0 187 +#define SC_R_LCD_0_PWM_0 188 +#define SC_R_LCD_0_I2C_0 189 +#define SC_R_LCD_0_I2C_1 190 +#define SC_R_PWM_0 191 +#define SC_R_PWM_1 192 +#define SC_R_PWM_2 193 +#define SC_R_PWM_3 194 +#define SC_R_PWM_4 195 +#define SC_R_PWM_5 196 +#define SC_R_PWM_6 197 +#define SC_R_PWM_7 198 +#define SC_R_GPIO_0 199 +#define SC_R_GPIO_1 200 +#define SC_R_GPIO_2 201 +#define SC_R_GPIO_3 202 +#define SC_R_GPIO_4 203 +#define SC_R_GPIO_5 204 +#define SC_R_GPIO_6 205 +#define SC_R_GPIO_7 206 +#define SC_R_GPT_0 207 +#define SC_R_GPT_1 208 +#define SC_R_GPT_2 209 +#define SC_R_GPT_3 210 +#define SC_R_GPT_4 211 +#define SC_R_KPP 212 +#define SC_R_MU_0A 213 +#define SC_R_MU_1A 214 +#define SC_R_MU_2A 215 +#define SC_R_MU_3A 216 +#define SC_R_MU_4A 217 +#define SC_R_MU_5A 218 +#define SC_R_MU_6A 219 +#define SC_R_MU_7A 220 +#define SC_R_MU_8A 221 +#define SC_R_MU_9A 222 +#define SC_R_MU_10A 223 +#define SC_R_MU_11A 224 +#define SC_R_MU_12A 225 +#define SC_R_MU_13A 226 +#define SC_R_MU_5B 227 +#define SC_R_MU_6B 228 +#define SC_R_MU_7B 229 +#define SC_R_MU_8B 230 +#define SC_R_MU_9B 231 +#define SC_R_MU_10B 232 +#define SC_R_MU_11B 233 +#define SC_R_MU_12B 234 +#define SC_R_MU_13B 235 +#define SC_R_ROM_0 236 +#define SC_R_FSPI_0 237 +#define SC_R_FSPI_1 238 +#define SC_R_IEE 239 +#define SC_R_IEE_R0 240 +#define SC_R_IEE_R1 241 +#define SC_R_IEE_R2 242 +#define SC_R_IEE_R3 243 +#define SC_R_IEE_R4 244 +#define SC_R_IEE_R5 245 +#define SC_R_IEE_R6 246 +#define SC_R_IEE_R7 247 +#define SC_R_SDHC_0 248 +#define SC_R_SDHC_1 249 +#define SC_R_SDHC_2 250 +#define SC_R_ENET_0 251 +#define SC_R_ENET_1 252 +#define SC_R_MLB_0 253 +#define SC_R_DMA_2_CH0 254 +#define SC_R_DMA_2_CH1 255 +#define SC_R_DMA_2_CH2 256 +#define SC_R_DMA_2_CH3 257 +#define SC_R_DMA_2_CH4 258 +#define SC_R_USB_0 259 +#define SC_R_USB_1 260 +#define SC_R_USB_0_PHY 261 +#define SC_R_USB_2 262 +#define SC_R_USB_2_PHY 263 +#define SC_R_DTCP 264 +#define SC_R_NAND 265 +#define SC_R_LVDS_0 266 +#define SC_R_LVDS_0_PWM_0 267 +#define SC_R_LVDS_0_I2C_0 268 +#define SC_R_LVDS_0_I2C_1 269 +#define SC_R_LVDS_1 270 +#define SC_R_LVDS_1_PWM_0 271 +#define SC_R_LVDS_1_I2C_0 272 +#define SC_R_LVDS_1_I2C_1 273 +#define SC_R_LVDS_2 274 +#define SC_R_LVDS_2_PWM_0 275 +#define SC_R_LVDS_2_I2C_0 276 +#define SC_R_LVDS_2_I2C_1 277 +#define SC_R_M4_0_PID0 278 +#define SC_R_M4_0_PID1 279 +#define SC_R_M4_0_PID2 280 +#define SC_R_M4_0_PID3 281 +#define SC_R_M4_0_PID4 282 +#define SC_R_M4_0_RGPIO 283 +#define SC_R_M4_0_SEMA42 284 +#define SC_R_M4_0_TPM 285 +#define SC_R_M4_0_PIT 286 +#define SC_R_M4_0_UART 287 +#define SC_R_M4_0_I2C 288 +#define SC_R_M4_0_INTMUX 289 +#define SC_R_UNUSED15 290 +#define SC_R_UNUSED16 291 +#define SC_R_M4_0_MU_0B 292 +#define SC_R_M4_0_MU_0A0 293 +#define SC_R_M4_0_MU_0A1 294 +#define SC_R_M4_0_MU_0A2 295 +#define SC_R_M4_0_MU_0A3 296 +#define SC_R_M4_0_MU_1A 297 +#define SC_R_M4_1_PID0 298 +#define SC_R_M4_1_PID1 299 +#define SC_R_M4_1_PID2 300 +#define SC_R_M4_1_PID3 301 +#define SC_R_M4_1_PID4 302 +#define SC_R_M4_1_RGPIO 303 +#define SC_R_M4_1_SEMA42 304 +#define SC_R_M4_1_TPM 305 +#define SC_R_M4_1_PIT 306 +#define SC_R_M4_1_UART 307 +#define SC_R_M4_1_I2C 308 +#define SC_R_M4_1_INTMUX 309 +#define SC_R_UNUSED17 310 +#define SC_R_UNUSED18 311 +#define SC_R_M4_1_MU_0B 312 +#define SC_R_M4_1_MU_0A0 313 +#define SC_R_M4_1_MU_0A1 314 +#define SC_R_M4_1_MU_0A2 315 +#define SC_R_M4_1_MU_0A3 316 +#define SC_R_M4_1_MU_1A 317 +#define SC_R_SAI_0 318 +#define SC_R_SAI_1 319 +#define SC_R_SAI_2 320 +#define SC_R_IRQSTR_SCU2 321 +#define SC_R_IRQSTR_DSP 322 +#define SC_R_ELCDIF_PLL 323 +#define SC_R_OCRAM 324 +#define SC_R_AUDIO_PLL_0 325 +#define SC_R_PI_0 326 +#define SC_R_PI_0_PWM_0 327 +#define SC_R_PI_0_PWM_1 328 +#define SC_R_PI_0_I2C_0 329 +#define SC_R_PI_0_PLL 330 +#define SC_R_PI_1 331 +#define SC_R_PI_1_PWM_0 332 +#define SC_R_PI_1_PWM_1 333 +#define SC_R_PI_1_I2C_0 334 +#define SC_R_PI_1_PLL 335 +#define SC_R_SC_PID0 336 +#define SC_R_SC_PID1 337 +#define SC_R_SC_PID2 338 +#define SC_R_SC_PID3 339 +#define SC_R_SC_PID4 340 +#define SC_R_SC_SEMA42 341 +#define SC_R_SC_TPM 342 +#define SC_R_SC_PIT 343 +#define SC_R_SC_UART 344 +#define SC_R_SC_I2C 345 +#define SC_R_SC_MU_0B 346 +#define SC_R_SC_MU_0A0 347 +#define SC_R_SC_MU_0A1 348 +#define SC_R_SC_MU_0A2 349 +#define SC_R_SC_MU_0A3 350 +#define SC_R_SC_MU_1A 351 +#define SC_R_SYSCNT_RD 352 +#define SC_R_SYSCNT_CMP 353 +#define SC_R_DEBUG 354 +#define SC_R_SYSTEM 355 +#define SC_R_SNVS 356 +#define SC_R_OTP 357 +#define SC_R_VPU_PID0 358 +#define SC_R_VPU_PID1 359 +#define SC_R_VPU_PID2 360 +#define SC_R_VPU_PID3 361 +#define SC_R_VPU_PID4 362 +#define SC_R_VPU_PID5 363 +#define SC_R_VPU_PID6 364 +#define SC_R_VPU_PID7 365 +#define SC_R_VPU_UART 366 +#define SC_R_VPUCORE 367 +#define SC_R_VPUCORE_0 368 +#define SC_R_VPUCORE_1 369 +#define SC_R_VPUCORE_2 370 +#define SC_R_VPUCORE_3 371 +#define SC_R_DMA_4_CH0 372 +#define SC_R_DMA_4_CH1 373 +#define SC_R_DMA_4_CH2 374 +#define SC_R_DMA_4_CH3 375 +#define SC_R_DMA_4_CH4 376 +#define SC_R_ISI_CH0 377 +#define SC_R_ISI_CH1 378 +#define SC_R_ISI_CH2 379 +#define SC_R_ISI_CH3 380 +#define SC_R_ISI_CH4 381 +#define SC_R_ISI_CH5 382 +#define SC_R_ISI_CH6 383 +#define SC_R_ISI_CH7 384 +#define SC_R_MJPEG_DEC_S0 385 +#define SC_R_MJPEG_DEC_S1 386 +#define SC_R_MJPEG_DEC_S2 387 +#define SC_R_MJPEG_DEC_S3 388 +#define SC_R_MJPEG_ENC_S0 389 +#define SC_R_MJPEG_ENC_S1 390 +#define SC_R_MJPEG_ENC_S2 391 +#define SC_R_MJPEG_ENC_S3 392 +#define SC_R_MIPI_0 393 +#define SC_R_MIPI_0_PWM_0 394 +#define SC_R_MIPI_0_I2C_0 395 +#define SC_R_MIPI_0_I2C_1 396 +#define SC_R_MIPI_1 397 +#define SC_R_MIPI_1_PWM_0 398 +#define SC_R_MIPI_1_I2C_0 399 +#define SC_R_MIPI_1_I2C_1 400 +#define SC_R_CSI_0 401 +#define SC_R_CSI_0_PWM_0 402 +#define SC_R_CSI_0_I2C_0 403 +#define SC_R_CSI_1 404 +#define SC_R_CSI_1_PWM_0 405 +#define SC_R_CSI_1_I2C_0 406 +#define SC_R_HDMI 407 +#define SC_R_HDMI_I2S 408 +#define SC_R_HDMI_I2C_0 409 +#define SC_R_HDMI_PLL_0 410 +#define SC_R_HDMI_RX 411 +#define SC_R_HDMI_RX_BYPASS 412 +#define SC_R_HDMI_RX_I2C_0 413 +#define SC_R_ASRC_0 414 +#define SC_R_ESAI_0 415 +#define SC_R_SPDIF_0 416 +#define SC_R_SPDIF_1 417 +#define SC_R_SAI_3 418 +#define SC_R_SAI_4 419 +#define SC_R_SAI_5 420 +#define SC_R_GPT_5 421 +#define SC_R_GPT_6 422 +#define SC_R_GPT_7 423 +#define SC_R_GPT_8 424 +#define SC_R_GPT_9 425 +#define SC_R_GPT_10 426 +#define SC_R_DMA_2_CH5 427 +#define SC_R_DMA_2_CH6 428 +#define SC_R_DMA_2_CH7 429 +#define SC_R_DMA_2_CH8 430 +#define SC_R_DMA_2_CH9 431 +#define SC_R_DMA_2_CH10 432 +#define SC_R_DMA_2_CH11 433 +#define SC_R_DMA_2_CH12 434 +#define SC_R_DMA_2_CH13 435 +#define SC_R_DMA_2_CH14 436 +#define SC_R_DMA_2_CH15 437 +#define SC_R_DMA_2_CH16 438 +#define SC_R_DMA_2_CH17 439 +#define SC_R_DMA_2_CH18 440 +#define SC_R_DMA_2_CH19 441 +#define SC_R_DMA_2_CH20 442 +#define SC_R_DMA_2_CH21 443 +#define SC_R_DMA_2_CH22 444 +#define SC_R_DMA_2_CH23 445 +#define SC_R_DMA_2_CH24 446 +#define SC_R_DMA_2_CH25 447 +#define SC_R_DMA_2_CH26 448 +#define SC_R_DMA_2_CH27 449 +#define SC_R_DMA_2_CH28 450 +#define SC_R_DMA_2_CH29 451 +#define SC_R_DMA_2_CH30 452 +#define SC_R_DMA_2_CH31 453 +#define SC_R_ASRC_1 454 +#define SC_R_ESAI_1 455 +#define SC_R_SAI_6 456 +#define SC_R_SAI_7 457 +#define SC_R_AMIX 458 +#define SC_R_MQS_0 459 +#define SC_R_DMA_3_CH0 460 +#define SC_R_DMA_3_CH1 461 +#define SC_R_DMA_3_CH2 462 +#define SC_R_DMA_3_CH3 463 +#define SC_R_DMA_3_CH4 464 +#define SC_R_DMA_3_CH5 465 +#define SC_R_DMA_3_CH6 466 +#define SC_R_DMA_3_CH7 467 +#define SC_R_DMA_3_CH8 468 +#define SC_R_DMA_3_CH9 469 +#define SC_R_DMA_3_CH10 470 +#define SC_R_DMA_3_CH11 471 +#define SC_R_DMA_3_CH12 472 +#define SC_R_DMA_3_CH13 473 +#define SC_R_DMA_3_CH14 474 +#define SC_R_DMA_3_CH15 475 +#define SC_R_DMA_3_CH16 476 +#define SC_R_DMA_3_CH17 477 +#define SC_R_DMA_3_CH18 478 +#define SC_R_DMA_3_CH19 479 +#define SC_R_DMA_3_CH20 480 +#define SC_R_DMA_3_CH21 481 +#define SC_R_DMA_3_CH22 482 +#define SC_R_DMA_3_CH23 483 +#define SC_R_DMA_3_CH24 484 +#define SC_R_DMA_3_CH25 485 +#define SC_R_DMA_3_CH26 486 +#define SC_R_DMA_3_CH27 487 +#define SC_R_DMA_3_CH28 488 +#define SC_R_DMA_3_CH29 489 +#define SC_R_DMA_3_CH30 490 +#define SC_R_DMA_3_CH31 491 +#define SC_R_AUDIO_PLL_1 492 +#define SC_R_AUDIO_CLK_0 493 +#define SC_R_AUDIO_CLK_1 494 +#define SC_R_MCLK_OUT_0 495 +#define SC_R_MCLK_OUT_1 496 +#define SC_R_PMIC_0 497 +#define SC_R_PMIC_1 498 +#define SC_R_SECO 499 +#define SC_R_CAAM_JR1 500 +#define SC_R_CAAM_JR2 501 +#define SC_R_CAAM_JR3 502 +#define SC_R_SECO_MU_2 503 +#define SC_R_SECO_MU_3 504 +#define SC_R_SECO_MU_4 505 +#define SC_R_HDMI_RX_PWM_0 506 +#define SC_R_A35 507 +#define SC_R_A35_0 508 +#define SC_R_A35_1 509 +#define SC_R_A35_2 510 +#define SC_R_A35_3 511 +#define SC_R_DSP 512 +#define SC_R_DSP_RAM 513 +#define SC_R_CAAM_JR1_OUT 514 +#define SC_R_CAAM_JR2_OUT 515 +#define SC_R_CAAM_JR3_OUT 516 +#define SC_R_VPU_DEC_0 517 +#define SC_R_VPU_ENC_0 518 +#define SC_R_CAAM_JR0 519 +#define SC_R_CAAM_JR0_OUT 520 +#define SC_R_PMIC_2 521 +#define SC_R_DBLOGIC 522 +#define SC_R_HDMI_PLL_1 523 +#define SC_R_BOARD_R0 524 +#define SC_R_BOARD_R1 525 +#define SC_R_BOARD_R2 526 +#define SC_R_BOARD_R3 527 +#define SC_R_BOARD_R4 528 +#define SC_R_BOARD_R5 529 +#define SC_R_BOARD_R6 530 +#define SC_R_BOARD_R7 531 +#define SC_R_MJPEG_DEC_MP 532 +#define SC_R_MJPEG_ENC_MP 533 +#define SC_R_VPU_TS_0 534 +#define SC_R_VPU_MU_0 535 +#define SC_R_VPU_MU_1 536 +#define SC_R_VPU_MU_2 537 +#define SC_R_VPU_MU_3 538 +#define SC_R_VPU_ENC_1 539 +#define SC_R_VPU 540 +#define SC_R_DMA_5_CH0 541 +#define SC_R_DMA_5_CH1 542 +#define SC_R_DMA_5_CH2 543 +#define SC_R_DMA_5_CH3 544 +#define SC_R_ATTESTATION 545 +#define SC_R_LAST 546 +#define SC_R_NONE 0xFFF0 + +#endif /* DT_BINDINGS_RSCRC_IMX_H */ + diff --git a/include/dt_table.h b/include/dt_table.h new file mode 100644 index 00000000000..b59098b3743 --- /dev/null +++ b/include/dt_table.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2018 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _DT_TABLE_H_ +#define _DT_TABLE_H_ + +#include + +/* https://android.googlesource.com/platform/system/libufdt/+/master/utils/README.md */ + +#define DT_TABLE_MAGIC 0xd7b7ab1e + +struct dt_table_header { + __be32 magic; + __be32 total_size; + __be32 header_size; + __be32 dt_entry_size; + __be32 dt_entry_count; + __be32 dt_entries_offset; + __be32 page_size; + __be32 version; +}; + +struct dt_table_entry { + __be32 dt_size; + __be32 dt_offset; + __be32 id; + __be32 rev; + __be32 custom[4]; +}; +#endif /* _DT_TABLE_H_ */ diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index 7af2ad11e4e..e75f3985df4 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -16,6 +16,7 @@ struct dwc3_device { unsigned long base; enum usb_dr_mode dr_mode; u32 maximum_speed; + u16 power_down_scale; unsigned tx_fifo_resize:1; unsigned has_lpm_erratum; u8 lpm_nyet_threshold; diff --git a/include/environment.h b/include/environment.h index 7986a242778..ec12af55c19 100644 --- a/include/environment.h +++ b/include/environment.h @@ -190,6 +190,7 @@ enum env_valid { enum env_location { ENVL_UNKNOWN, ENVL_EEPROM, + ENVL_ESATA, ENVL_EXT4, ENVL_FAT, ENVL_FLASH, diff --git a/include/fat.h b/include/fat.h index fa956441c65..6a25fac47fd 100644 --- a/include/fat.h +++ b/include/fat.h @@ -181,7 +181,7 @@ static inline u32 clust_to_sect(fsdata *fsdata, u32 clust) return fsdata->data_begin + clust * fsdata->clust_size; } -static inline u32 sect_to_clust(fsdata *fsdata, u32 sect) +static inline u32 sect_to_clust(fsdata *fsdata, int sect) { return (sect - fsdata->data_begin) / fsdata->clust_size; } diff --git a/include/fsl_avb.h b/include/fsl_avb.h new file mode 100644 index 00000000000..225f42ab096 --- /dev/null +++ b/include/fsl_avb.h @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_AVB_H__ +#define __FSL_AVB_H__ + +#include "../lib/avb/libavb_ab/libavb_ab.h" +#include "../lib/avb/libavb_atx/libavb_atx.h" +/* Reads |num_bytes| from offset |offset| from partition with name + * |partition| (NUL-terminated UTF-8 string). If |offset| is + * negative, its absolute value should be interpreted as the number + * of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * |offset| is outside the partition, and AVB_IO_RESULT_ERROR_IO if + * there was an I/O error from the underlying I/O subsystem. If the + * operation succeeds as requested AVB_IO_RESULT_OK is returned and + * the data is available in |buffer|. + * + * The only time partial I/O may occur is if reading beyond the end + * of the partition. In this case the value returned in + * |out_num_read| may be smaller than |num_bytes|. + */ +AvbIOResult fsl_read_from_partition(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + void* buffer, size_t* out_num_read); + +/* multi block read version + * */ +AvbIOResult fsl_read_from_partition_multi(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + void* buffer, size_t* out_num_read); + +/* Writes |num_bytes| from |bffer| at offset |offset| to partition + * with name |partition| (NUL-terminated UTF-8 string). If |offset| + * is negative, its absolute value should be interpreted as the + * number of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * byterange goes outside the partition, and AVB_IO_RESULT_ERROR_IO + * if there was an I/O error from the underlying I/O subsystem. If + * the operation succeeds as requested AVB_IO_RESULT_OK is + * returned. + * + * This function never does any partial I/O, it either transfers all + * of the requested bytes or returns an error. + */ +AvbIOResult fsl_write_to_partition(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + const void* buffer); + +/* Reads A/B metadata from persistent storage. Returned data is + * properly byteswapped. Returns AVB_IO_RESULT_OK on success, error + * code otherwise. + * + * If the data read is invalid (e.g. wrong magic or CRC checksum + * failure), the metadata shoule be reset using avb_ab_data_init() + * and then written to persistent storage. + * + * Implementations will typically want to use avb_ab_data_read() + * here to use the 'misc' partition for persistent storage. + */ +AvbIOResult fsl_read_ab_metadata(AvbABOps* ab_ops, struct AvbABData* data); + +/* Writes A/B metadata to persistent storage. This will byteswap and + * update the CRC as needed. Returns AVB_IO_RESULT_OK on success, + * error code otherwise. + * + * Implementations will typically want to use avb_ab_data_write() + * here to use the 'misc' partition for persistent storage. + */ +AvbIOResult fsl_write_ab_metadata(AvbABOps* ab_ops, const struct AvbABData* data); + +/* Checks if the given public key used to sign the 'vbmeta' + * partition is trusted. Boot loaders typically compare this with + * embedded key material generated with 'avbtool + * extract_public_key'. + * + * If AVB_IO_RESULT_OK is returned then |out_is_trusted| is set - + * true if trusted or false if untrusted. + */ +AvbIOResult fsl_validate_vbmeta_public_key_rpmb(AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted); + +/* Gets the rollback index corresponding to the slot given by + * |rollback_index_slot|. The value is returned in + * |out_rollback_index|. Returns AVB_IO_RESULT_OK if the rollback + * index was retrieved, otherwise an error code. + * + * A device may have a limited amount of rollback index slots (say, + * one or four) so may error out if |rollback_index_slot| exceeds + * this number. + */ +AvbIOResult fsl_read_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t* out_rollback_index); + +/* Sets the rollback index corresponding to the slot given by + * |rollback_index_slot| to |rollback_index|. Returns + * AVB_IO_RESULT_OK if the rollback index was set, otherwise an + * error code. + * + * A device may have a limited amount of rollback index slots (say, + * one or four) so may error out if |rollback_index_slot| exceeds + * this number. + */ +AvbIOResult fsl_write_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t rollback_index); + +/* Gets whether the device is unlocked. The value is returned in + * |out_is_unlocked| (true if unlocked, false otherwise). Returns + * AVB_IO_RESULT_OK if the state was retrieved, otherwise an error + * code. + */ +AvbIOResult fsl_read_is_device_unlocked(AvbOps* ops, bool* out_is_unlocked); + +/* Gets the unique partition GUID for a partition with name in + * |partition| (NUL-terminated UTF-8 string). The GUID is copied as + * a string into |guid_buf| of size |guid_buf_size| and will be NUL + * terminated. The string must be lower-case and properly + * hyphenated. For example: + * + * 527c1c6d-6361-4593-8842-3c78fcd39219 + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_unique_guid_for_partition(AvbOps* ops, + const char* partition, + char* guid_buf, + size_t guid_buf_size); + +/* Gets the size of a partition with the name in |partition| + * (NUL-terminated UTF-8 string). Returns the value in + * |out_size_num_bytes|. + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_size_of_partition(AvbOps* ops, + const char* partition, + uint64_t* out_size_num_bytes); +/* check if the fastboot getvar cmd is for query [avb] bootctl's slot var + * cmd is the fastboot getvar's cmd in + * return true if it is a bootctl related cmd, false if it's not. + * */ +bool is_slotvar_avb(char *cmd); + +/* Get current bootable slot with higher priority. + * return 0 for the first slot + * return 1 for the second slot + * return -1 for not supported slot + * */ +int get_curr_slot(AvbABData *ab_data); + +/* return 0 for the first slot + * return 1 for the second slot + * return -1 for not supported slot + * */ +int slotidx_from_suffix(char *suffix); + +/* return fastboot's getvar cmd response + * cmd is the fastboot getvar's cmd in + * if return 0, buffer is bootctl's slot var out + * if return -1, buffer is error string + * */ +int get_slotvar_avb(AvbABOps *ab_ops, char *cmd, char *buffer, size_t size); + +/* reset rollback_index part in avbkey partition + * used in the switch from LOCK to UNLOCK + * return 0 if success, non 0 if fail. + * */ +int rbkidx_erase(void); + +/* init the avbkey in rpmb partition, include the header/public key/rollback index + * for public key/rollback index part, use caam to do encrypt + * return 0 if success, non 0 if fail. + * */ +int avbkey_init(uint8_t *plainkey, uint32_t keylen); + +/* read a/b metadata to get curr slot + * return slot suffix '_a'/'_b' or NULL */ +char *select_slot(AvbABOps *ab_ops); + +/* Reads permanent |attributes| data. There are no restrictions on where this + * data is stored. On success, returns AVB_IO_RESULT_OK and populates + * |attributes|. + */ +AvbIOResult fsl_read_permanent_attributes( + AvbAtxOps* atx_ops, AvbAtxPermanentAttributes* attributes); + +/* Reads a |hash| of permanent attributes. This hash MUST be retrieved from a + * permanently read-only location (e.g. fuses) when a device is LOCKED. On + * success, returned AVB_IO_RESULT_OK and populates |hash|. + */ +AvbIOResult fsl_read_permanent_attributes_hash(AvbAtxOps* atx_ops, + uint8_t hash[AVB_SHA256_DIGEST_SIZE]); + +/* Provides the key version of a key used during verification. This may be + * useful for managing the minimum key version. + */ +void fsl_set_key_version(AvbAtxOps* atx_ops, + size_t rollback_index_location, + uint64_t key_version); + +/* This is the fast version of avb_ab_flow(), this function will + * not check another slot if one slot can pass the verify (or verify + * fail is acceptable). + */ +AvbABFlowResult avb_ab_flow_fast(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data); + +/* This is for legacy i.mx6/7 which don't enable A/B but want to + * verify boot/recovery with AVB */ +AvbABFlowResult avb_single_flow(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data); + +/* Avb verify flow for dual bootloader, only the slot chosen by SPL will + * be verified. + */ +AvbABFlowResult avb_flow_dual_uboot(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data); +/* Generates |num_bytes| random bytes and stores them in |output|, + * which must point to a buffer large enough to store the bytes. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_random(AvbAtxOps* atx_ops, + size_t num_bytes, + uint8_t* output); + +/* Program ATX perm_attr into RPMB partition */ +int avb_atx_fuse_perm_attr(uint8_t *staged_buffer, uint32_t size); + +/* Initialize rpmb key with the staged key */ +int fastboot_set_rpmb_key(uint8_t *staged_buf, uint32_t key_size); + +/* Initialize rpmb key with random key which is generated by caam rng */ +int fastboot_set_rpmb_random_key(void); + +/* Generate ATX unlock challenge */ +int avb_atx_get_unlock_challenge(struct AvbAtxOps* atx_ops, + uint8_t *upload_buffer, uint32_t *size); +/* Verify ATX unlock credential */ +int avb_atx_verify_unlock_credential(struct AvbAtxOps* atx_ops, + uint8_t *staged_buffer); +/* Check if the perm-attr have been fused. */ +bool perm_attr_are_fused(void); + +/* Check if the unlock vboot is already disabled */ +bool at_unlock_vboot_is_disabled(void); + +/* disable at unlock vboot */ +int at_disable_vboot_unlock(void); + +/* Set vbmeta public key */ +int avb_set_public_key(uint8_t *staged_buffer, uint32_t size); +#endif /* __FSL_AVB_H__ */ diff --git a/include/fsl_caam.h b/include/fsl_caam.h new file mode 100644 index 00000000000..4650bf2d70f --- /dev/null +++ b/include/fsl_caam.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * Copyright 2018 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CAAM_H__ +#define __CAAM_H__ + +//! @name Error codes +//@{ +#if !defined(SUCCESS) +#define SUCCESS (0) +#endif + +#define ERROR_ANY (-1) +#define ERROR_IN_PAGE_ALLOC (1) + + +//////////////////////////////////////////////////////////////////////////////// +//! @brief Enable and initialize the CAAM driver. +//! +//! This function enables the clock to the CAAM. It initializes the RNG, and +//! instantiate it to allow generation of key for blob. +//! +//////////////////////////////////////////////////////////////////////////////// +void caam_open(void); +void imx_sec_init(void); + +//////////////////////////////////////////////////////////////////////////////// +//! @brief Generate a blob of a secure key. +//! +//! @param[in] plain_data_addr Location address of the plain text data. +//! @param[in] blob_addr Location address of the blob. +//! @param[in] size Size in bytes of the data to encrypt. +//! +//! @return SUCCESS +//! @return ERROR_XXX +//////////////////////////////////////////////////////////////////////////////// +uint32_t caam_gen_blob(uint32_t plain_data_addr, uint32_t blob_addr, uint32_t size); + +//////////////////////////////////////////////////////////////////////////////// +//! @brief Decapsulate a blob of a secure key. +//! +//! @param[in] blob_addr Location address of the blob. +//! +//! @return SUCCESS +//! @return ERROR_XXX +//////////////////////////////////////////////////////////////////////////////// +uint32_t caam_decap_blob(uint32_t plain_text, uint32_t blob_addr, uint32_t size); +uint32_t caam_hwrng(uint8_t *output_ptr, uint32_t output_len); + +#endif /* __CAAM_H__ */ diff --git a/include/fsl_fastboot.h b/include/fsl_fastboot.h new file mode 100644 index 00000000000..68ac0916407 --- /dev/null +++ b/include/fsl_fastboot.h @@ -0,0 +1,278 @@ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef FSL_FASTBOOT_H +#define FSL_FASTBOOT_H +#include +#include + +#define FASTBOOT_PTENTRY_FLAGS_REPEAT(n) (n & 0x0f) +#define FASTBOOT_PTENTRY_FLAGS_REPEAT_MASK 0x0000000F + +/* Writes happen a block at a time. + If the write fails, go to next block + NEXT_GOOD_BLOCK and CONTIGOUS_BLOCK can not both be set */ +#define FASTBOOT_PTENTRY_FLAGS_WRITE_NEXT_GOOD_BLOCK 0x00000010 + +/* Find a contiguous block big enough for a the whole file + NEXT_GOOD_BLOCK and CONTIGOUS_BLOCK can not both be set */ +#define FASTBOOT_PTENTRY_FLAGS_WRITE_CONTIGUOUS_BLOCK 0x00000020 + +/* Write the file with write.i */ +#define FASTBOOT_PTENTRY_FLAGS_WRITE_I 0x00000100 + +/* Write the file with write.trimffs */ +#define FASTBOOT_PTENTRY_FLAGS_WRITE_TRIMFFS 0x00000200 + +/* Write the file as a series of variable/value pairs + using the setenv and saveenv commands */ +#define FASTBOOT_PTENTRY_FLAGS_WRITE_ENV 0x00000400 + +/* Uneraseable partition */ +#define FASTBOOT_PTENTRY_FLAGS_UNERASEABLE 0x00000800 + +#define FASTBOOT_MMC_BOOT_PARTITION_ID 1 +#define FASTBOOT_MMC_USER_PARTITION_ID 0 +#define FASTBOOT_MMC_NONE_PARTITION_ID -1 +#define FASTBOOT_MMC_BOOT1_PARTITION_ID 2 + +#define FASTBOOT_PARTITION_TEE "tos" +#define FASTBOOT_PARTITION_PRDATA "presistdata" + +#ifdef CONFIG_AVB_SUPPORT +#define FASTBOOT_PARTITION_AVBKEY "avbkey" +#endif + +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +#define FASTBOOT_MCU_FIRMWARE_PARTITION "m4_os" +#endif + +#ifdef CONFIG_ANDROID_AB_SUPPORT +#define FASTBOOT_PARTITION_BOOT_A "boot_a" +#define FASTBOOT_PARTITION_RECOVERY "recovery" +#define FASTBOOT_PARTITION_SYSTEM_A "system_a" +#define FASTBOOT_PARTITION_BOOTLOADER "bootloader0" +#define FASTBOOT_PARTITION_DATA "userdata" +#define FASTBOOT_PARTITION_BOOT_B "boot_b" +#define FASTBOOT_PARTITION_SYSTEM_B "system_b" +#define FASTBOOT_PARTITION_OEM_A "oem_a" +#define FASTBOOT_PARTITION_VENDOR_A "vendor_a" +#define FASTBOOT_PARTITION_OEM_B "oem_b" +#define FASTBOOT_PARTITION_VENDOR_B "vendor_b" +#ifdef CONFIG_AVB_SUPPORT +#define FASTBOOT_PARTITION_VBMETA_A "vbmeta_a" +#define FASTBOOT_PARTITION_VBMETA_B "vbmeta_b" +#endif +#define FASTBOOT_PARTITION_MISC "misc" +#define FASTBOOT_PARTITION_GPT "gpt" +#define FASTBOOT_PARTITION_FBMISC "fbmisc" +#else +#define FASTBOOT_PARTITION_BOOT "boot" +#define FASTBOOT_PARTITION_RECOVERY "recovery" +#define FASTBOOT_PARTITION_SYSTEM "system" +#define FASTBOOT_PARTITION_CACHE "cache" +#define FASTBOOT_PARTITION_DEVICE "device" +#define FASTBOOT_PARTITION_BOOTLOADER "bootloader" +#define FASTBOOT_PARTITION_DATA "userdata" +#define FASTBOOT_PARTITION_GPT "gpt" +#define FASTBOOT_PARTITION_MISC "misc" +#define FASTBOOT_PARTITION_FBMISC "fbmisc" +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#ifndef CONFIG_AVB_ATX +#define FASTBOOT_SET_RPMB_KEY "set-rpmb-key" +#define FASTBOOT_SET_RPMB_RANDOM_KEY "set-rpmb-random-key" +#define FASTBOOT_SET_VBMETA_PUBLIC_KEY "set-public-key" +#endif + +#define FASTBOOT_SET_CA_RESP "at-set-ca-response" +#define FASTBOOT_GET_CA_REQ "at-get-ca-request" +#define FASTBOOT_SET_RSA_ATTESTATION_KEY "set-rsa-atte-key" +#define FASTBOOT_SET_EC_ATTESTATION_KEY "set-ec-atte-key" +#define FASTBOOT_APPEND_RSA_ATTESTATION_CERT "append-rsa-atte-cert" +#define FASTBOOT_APPEND_EC_ATTESTATION_CERT "append-ec-atte-cert" +#endif + +#ifdef CONFIG_ANDROID_THINGS_SUPPORT +#define FASTBOOT_BOOTLOADER_VBOOT_KEY "fuse at-bootloader-vboot-key" +#ifdef CONFIG_AVB_ATX +#define FASTBOOT_AVB_AT_PERM_ATTR "fuse at-perm-attr" +#define FASTBOOT_AT_UNLOCK_VBOOT "at-unlock-vboot" +#define FASTBOOT_AT_LOCK_VBOOT "at-lock-vboot" +#define FASTBOOT_AT_DISABLE_UNLOCK_VBOOT "at-disable-unlock-vboot" +#define FASTBOOT_AT_GET_UNLOCK_CHALLENGE "at-get-vboot-unlock-challenge" +#endif /* CONFIG_AVB_ATX */ +#endif /* CONFIG_ANDROID_THINGS_SUPPORT */ + +enum { + DEV_SATA, + DEV_MMC, + DEV_NAND, +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT + /* SPI Flash */ + DEV_SF +#endif +}; + +typedef enum { +#ifdef CONFIG_ANDROID_RECOVERY + /* Revoery boot due to combo keys pressed */ + BOOTMODE_RECOVERY_KEY_PRESSED, + /* Recovery boot due to boot-recovery cmd in misc parition */ + BOOTMODE_RECOVERY_BCB_CMD, +#endif + /* Fastboot boot due to bootonce-bootloader cmd in misc parition */ + BOOTMODE_FASTBOOT_BCB_CMD, + /* Normal boot */ + BOOTMODE_NORMAL +}FbBootMode; + + +struct cmd_fastboot_interface { + /* This function is called when a buffer has been + recieved from the client app. + The buffer is a supplied by the board layer and must be unmodified. + The buffer_size is how much data is passed in. + Returns 0 on success + Returns 1 on failure + + Set by cmd_fastboot */ + int (*rx_handler)(const unsigned char *buffer, + unsigned int buffer_size); + + /* This function is called when an exception has + occurred in the device code and the state + off fastboot needs to be reset + + Set by cmd_fastboot */ + void (*reset_handler)(void); + + /* A getvar string for the product name + It can have a maximum of 60 characters + + Set by board */ + char *product_name; + + /* A getvar string for the serial number + It can have a maximum of 60 characters + + Set by board */ + char *serial_no; + + /* Nand block size + Supports the write option WRITE_NEXT_GOOD_BLOCK + + Set by board */ + unsigned int nand_block_size; + + /* Nand oob size + Set by board */ + unsigned int nand_oob_size; + + /* Transfer buffer, for handling flash updates + Should be multiple of the nand_block_size + Care should be take so it does not overrun bootloader memory + Controlled by the configure variable CFG_FASTBOOT_TRANSFER_BUFFER + + Set by board */ + unsigned char *transfer_buffer; + + /* How big is the transfer buffer + Controlled by the configure variable + CFG_FASTBOOT_TRANSFER_BUFFER_SIZE + + Set by board */ + unsigned int transfer_buffer_size; + +}; + +/* flash partitions are defined in terms of blocks +** (flash erase units) +*/ +struct fastboot_ptentry { + /* The logical name for this partition, null terminated */ + char name[20]; + /* The start wrt the nand part, must be multiple of nand block size */ + unsigned int start; + /* The length of the partition, must be multiple of nand block size */ + unsigned int length; + /* Controls the details of how operations are done on the partition + See the FASTBOOT_PTENTRY_FLAGS_*'s defined below */ + unsigned int flags; + /* partition id: 0 - normal partition; 1 - boot partition */ + unsigned int partition_id; + /* partition number in block device */ + unsigned int partition_index; + /* partition file system type in string */ + char fstype[16]; + /* filesystem UUID as string, if exists */ +#ifdef CONFIG_PARTITION_UUIDS + char uuid[37]; +#endif +}; + +struct fastboot_device_info { + unsigned char type; + unsigned char dev_id; +}; + +extern struct fastboot_device_info fastboot_devinfo; + +/* Prepare the fastboot environments, + * should be executed before "fastboot" cmd + */ +void fastboot_setup(void); + + +/* The Android-style flash handling */ + +/* tools to populate and query the partition table */ +void fastboot_flash_add_ptn(struct fastboot_ptentry *ptn); +struct fastboot_ptentry *fastboot_flash_find_ptn(const char *name); +struct fastboot_ptentry *fastboot_flash_get_ptn(unsigned n); +unsigned int fastboot_flash_get_ptn_count(void); +void fastboot_flash_dump_ptn(void); + +/* Make board into special boot mode */ +void fastboot_run_bootmode(void); + +/*Setup board-relative fastboot environment */ +void board_fastboot_setup(void); + +/*return partition index according name*/ +int fastboot_flash_find_index(const char *name); + +/*check whether bootloader is overlay with GPT table*/ +bool bootloader_gpt_overlay(void); +/* Check whether the combo keys pressed + * Return 1 if combo keys pressed for recovery boot + * Return 0 if no combo keys pressed + */ +int is_recovery_key_pressing(void); + +#ifdef CONFIG_FASTBOOT_STORAGE_NAND +/*Save parameters for NAND storage partitions */ +void save_parts_values(struct fastboot_ptentry *ptn, + unsigned int offset, unsigned int size); + +/* Checks parameters for NAND storage partitions + * Return 1 if the parameter is not set + * Return 0 if the parameter has been set + */ +int check_parts_values(struct fastboot_ptentry *ptn); +#endif /*CONFIG_FASTBOOT_STORAGE_NAND*/ + +/* Reads |num_bytes| from offset |offset| from partition with name + * |partition| (NUL-terminated UTF-8 string). If |offset| is + * negative, its absolute value should be interpreted as the number + * of bytes from the end of the partition. + * It's basically copied from fsl_read_from_partition_multi() because + * we may want to read partition when AVB is not enabled. */ +int read_from_partition_multi(const char* partition, + int64_t offset, size_t num_bytes,void* buffer, size_t* out_num_read); +#endif /* FSL_FASTBOOT_H */ diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h index 4643ee79ee9..ce9f4cc21bb 100644 --- a/include/fsl_lpuart.h +++ b/include/fsl_lpuart.h @@ -5,7 +5,7 @@ * */ -#ifdef CONFIG_ARCH_MX7ULP +#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_IMX8) struct lpuart_fsl_reg32 { u32 verid; u32 param; diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 4cbdb2d65a0..71f4e829b18 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -2,6 +2,7 @@ * Common internal memory map for some Freescale SoCs * * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,8 +14,8 @@ #include #ifdef CONFIG_SYS_FSL_SEC_LE -#define sec_in32(a) in_le32(a) -#define sec_out32(a, v) out_le32(a, v) +#define sec_in32(a) in_le32((ulong *)(ulong)(a)) +#define sec_out32(a, v) out_le32((ulong *)(ulong)(a), v) #define sec_in16(a) in_le16(a) #define sec_clrbits32 clrbits_le32 #define sec_setbits32 setbits_le32 @@ -152,7 +153,8 @@ typedef struct ccsr_sec { struct jr_regs { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) u32 irba_l; u32 irba_h; #else @@ -166,7 +168,8 @@ struct jr_regs { u32 rsvd3; u32 irja; #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) u32 orba_l; u32 orba_h; #else @@ -199,7 +202,8 @@ struct jr_regs { */ struct sg_entry { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) uint32_t addr_lo; /* Memory Address - lo */ uint32_t addr_hi; /* Memory Address of start of buffer - hi */ #else @@ -220,7 +224,8 @@ struct sg_entry { #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ -#if defined(CONFIG_MX6) || defined(CONFIG_MX7) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) /* Job Ring Base Address */ #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) /* Secure Memory Offset varies accross versions */ @@ -228,7 +233,8 @@ struct sg_entry { #define SM_V2_OFFSET 0xa00 /*Secure Memory Versioning */ #define SMVID_V2 0x20105 -#define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2) +#define SM_VERSION(x) ({typeof(x) _x = x; \ + _x < SMVID_V2 ? 1 : (_x < 0x20300 ? 2 : 3); }) #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET) /* CAAM Job Ring 0 Registers */ /* Secure Memory Partition Owner register */ @@ -255,8 +261,10 @@ struct sg_entry { #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4) #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC) #define SM_PERM(v) (v == 1 ? 0x10 : 0x4) -#define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8) -#define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC) +#define SM_GROUP2(v) ({typeof(v) _v = v; \ + _v == 1 ? 0x14 : (_v == 2 ? 0x8 : 0xC); }) +#define SM_GROUP1(v) ({typeof(v) _v = v; \ + _v == 1 ? 0x18 : (_v == 2 ? 0xC : 0x8); }) #define CMD_PAGE_ALLOC 0x1 #define CMD_PAGE_DEALLOC 0x2 #define CMD_PART_DEALLOC 0x3 @@ -274,10 +282,15 @@ struct sg_entry { #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000) #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000) -#define JR_MID 2 /* Matches ROM configuration */ -#define KS_G1 (1 << JR_MID) /* CAAM only */ -#define PERM 0x0000B008 /* Clear on release, lock SMAP - * lock SMAG group 1 Blob */ +#ifdef CONFIG_IMX8M +#define JR_MID (1) /* Matches ATF configuration */ +#define KS_G1 (0x10000 << JR_MID) /* CAAM only */ +#define PERM (0xB080) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */ +#else +#define JR_MID (2) /* Matches ROM configuration */ +#define KS_G1 BIT(JR_MID) /* CAAM only */ +#define PERM (0xB008) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */ +#endif /* CONFIG_IMX8M */ /* HAB WRAPPED KEY header */ #define WRP_HDR_SIZE 0x08 @@ -297,6 +310,13 @@ struct sg_entry { #endif +#define FSL_CAAM_MP_PUBK_BYTES 64 +#define FSL_CAAM_MP_PRVK_BYTES 32 +#define FSL_CAAM_MP_MES_DGST_BYTES 32 + +#define FSL_CAAM_ORSR_JRa_OFFSET 0x102c +#define FSL_CAAM_MAX_JR_SIZE 4 + /* blob_dek: * Encapsulates the src in a secure blob and stores it dst * @src: reference to the plaintext @@ -306,6 +326,10 @@ struct sg_entry { */ int blob_dek(const u8 *src, u8 *dst, u8 len); +int gen_mppubk(u8 *dst); + +int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d); + #if defined(CONFIG_ARCH_C29X) int sec_init_idx(uint8_t); #endif diff --git a/include/gis.h b/include/gis.h new file mode 100644 index 00000000000..e156743407a --- /dev/null +++ b/include/gis.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef GIS_H +#define GIS_H + +#define FMT_YUV444 0 +#define FMT_YUYV 1 +#define FMT_UYVY 2 +#define FMT_RGB565 3 +#define FMT_RGB888 4 + +void mxc_enable_gis(void); +void mxc_disable_gis(void); + +#endif diff --git a/include/hypercall.h b/include/hypercall.h new file mode 100644 index 00000000000..7279e298125 --- /dev/null +++ b/include/hypercall.h @@ -0,0 +1,7 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +int HYPERVISOR_console_io(int cmd, int count, const char *str); diff --git a/include/image.h b/include/image.h index dbdaecbfdd3..bb54b4cc561 100644 --- a/include/image.h +++ b/include/image.h @@ -1277,6 +1277,7 @@ int android_image_get_second(const struct andr_img_hdr *hdr, ulong android_image_get_end(const struct andr_img_hdr *hdr); ulong android_image_get_kload(const struct andr_img_hdr *hdr); void android_print_contents(const struct andr_img_hdr *hdr); +bool image_arm64(void *images); #endif /* CONFIG_ANDROID_BOOT_IMAGE */ diff --git a/include/imx8_hdmi.h b/include/imx8_hdmi.h new file mode 100644 index 00000000000..eb1253cf51f --- /dev/null +++ b/include/imx8_hdmi.h @@ -0,0 +1,13 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8_HDMI_H__ +#define __IMX8_HDMI_H__ + +int imx8_hdmi_enable(int encoding, struct video_mode_settings *vms); +void imx8_hdmi_disable(void); + +#endif /* __IMX8_HDMI_H__*/ diff --git a/include/imx8_hsio.h b/include/imx8_hsio.h new file mode 100644 index 00000000000..13cc881966c --- /dev/null +++ b/include/imx8_hsio.h @@ -0,0 +1,215 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _IMX8_HSIO_H_ +#define _IMX8_HSIO_H_ + +#define PCIEA_CFG_CPU_BASE 0x60000000 +#define PCIEA_CFG_PCI_BASE 0x40000000 +#define PCIEB_CFG_CPU_BASE 0x70000000 +#define PCIEB_CFG_PCI_BASE 0x80000000 +#define PCIE_CFG_MEM_SIZE 0x4000 + +#define PCIE_DBI_BASE_ADDR 0x5f000000 +#define PCIE_CTRLA_BASE_ADDR PCIE_DBI_BASE_ADDR +#define PCIE_CTRLB_BASE_ADDR (PCIE_DBI_BASE_ADDR + 0x10000) + +/* For 8DV */ +#define DEVICE_TYPE_RC BIT(14) +#define REFCLK_SEL BIT(4) +#define CMN_REG_RST BIT(3) + +#define HSIO_BASE_ADDR 0x5F070000 +#define HSIO_GPR_PCIE_CTRL0_ADDR (HSIO_BASE_ADDR + 0x00000000) +#define HSIO_GPR_PCIE_CTRL1_ADDR (HSIO_BASE_ADDR + 0x00000004) +#define HSIO_GPR_PCIE_STATUS0_ADDR (HSIO_BASE_ADDR + 0x00000008) + +/* For 8QM */ +#define AHCI_BASE_ADDR 0x5F020000 +#define HW_SATA_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00040000) +#define HW_SATA_CTRL0_ADDR_MASK 0x000017fb +#define HW_SATA_CTRL0_ADDR_RESET 0x0 +#define HW_SATA_CTRL0_PHY_FOMREQ BIT(0) +#define HW_SATA_CTRL0_PHY_PMA_DRVN BIT(1) +#define HW_SATA_CTRL0_EPCS_SKIPBIT BIT(3) +#define HW_SATA_CTRL0_EPCS_RXERR BIT(4) +#define HW_SATA_CTRL0_EPCS_TXDEEMP BIT(5) +#define HW_SATA_CTRL0_EPCS_TXDEEMP_SEL BIT(6) +#define HW_SATA_CTRL0_PHY_RESET BIT(7) +#define HW_SATA_CTRL0_EPCS_PHYRESET_SEL BIT(8) +#define HW_SATA_CTRL0_EPCS_RXOOB BIT(9) +#define HW_SATA_CTRL0_EPCS_RXOOB_SEL BIT(10) +#define HW_SATA_CTRL0_RESET BIT(12) + +#define HSIO_LPCG_BASE_ADDR 0x5F050000 +#define HSIO_GPIO_BASE_ADDR 0x5F170000 + +#define GPR_LPCG_PCIEA_CTRL_MSTR_ACLK (HSIO_LPCG_BASE_ADDR + 0x00000000) +#define GPR_LPCG_PCIEB_CTRL_MSTR_ACLK (HSIO_LPCG_BASE_ADDR + 0x00010000) +#define GPR_LPCG_PHYX2APB_0_APB (HSIO_LPCG_BASE_ADDR + 0x00030000) +#define GPR_LPCG_PHYX1_APB (HSIO_LPCG_BASE_ADDR + 0x00040000) +#define GPR_LPCG_CRR_0 (HSIO_LPCG_BASE_ADDR + 0x00050000) +#define GPR_LPCG_CRR_1 (HSIO_LPCG_BASE_ADDR + 0x00060000) +#define GPR_LPCG_CRR_2 (HSIO_LPCG_BASE_ADDR + 0x00070000) +#define GPR_LPCG_CRR_3 (HSIO_LPCG_BASE_ADDR + 0x00080000) +#define GPR_LPCG_CRR_4 (HSIO_LPCG_BASE_ADDR + 0x00090000) +#define GPR_LPCG_CRR_5 (HSIO_LPCG_BASE_ADDR + 0x000a0000) +#define GPR_LPCG_GPIO (HSIO_LPCG_BASE_ADDR + 0x000b0000) + +#define HSIO_CRR_BASE_ADDR 0x5F110000 + +#define HW_PHYX2_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00000000) +#define HW_PHYX2_CTRL0_APB_RSTN_0 BIT(0) +#define HW_PHYX2_CTRL0_APB_RSTN_1 BIT(1) +#define HW_PHYX2_CTRL0_PIPE_LN2LK_MASK (0xF << 13) +#define HW_PHYX2_CTRL0_PIPE_LN2LK_0 BIT(13) +#define HW_PHYX2_CTRL0_PIPE_LN2LK_1 BIT(14) +#define HW_PHYX2_CTRL0_PIPE_LN2LK_2 BIT(15) +#define HW_PHYX2_CTRL0_PIPE_LN2LK_3 BIT(16) + +#define HW_PHYX2_STTS0_ADDR (HSIO_CRR_BASE_ADDR + 0x00000004) +#define HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK BIT(4) +#define HW_PHYX2_STTS0_LANE1_TX_PLL_LOCK BIT(12) + +#define HW_PHYX1_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00010000) +#define HW_PHYX1_CTRL0_APB_RSTN BIT(0) +#define HW_PHYX1_CTRL0_PIPE_LN2LK_MASK (0xF << 13) +#define HW_PHYX1_CTRL0_PIPE_LN2LK_0 BIT(13) +#define HW_PHYX1_CTRL0_PIPE_LN2LK_1 BIT(14) +#define HW_PHYX1_CTRL0_PIPE_LN2LK_2 BIT(15) +#define HW_PHYX1_CTRL0_PIPE_LN2LK_3 BIT(16) + +#define HW_PHYX1_STTS0_ADDR (HSIO_CRR_BASE_ADDR + 0x00010004) +#define HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK BIT(4) +#define HW_PHYX1_STTS0_LANE0_RX_PLL_LOCK BIT(5) + +#define HW_MISC_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00050000) +#define HW_MISC_CTRL0_IOB_RXENA BIT(0) +#define HW_MISC_CTRL0_IOB_TXENA BIT(1) +#define HW_MISC_CTRL0_FAST_INIT BIT(11) +#define HW_MISC_CTRL0_PHY_X1_EPCS_SEL BIT(12) +#define HW_MISC_CTRL0_PCIE_AB_SELECT BIT(13) + +#define HW_PCIEX2_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00020000) +#define HW_PCIEX2_CTRL0_DEVICE_TYPE_MASK (0xF << 24) +#define HW_PCIEX2_CTRL0_DEVICE_TYPE_RC BIT(26) + +#define HW_PCIEX2_CTRL2_ADDR (HSIO_CRR_BASE_ADDR + 0x00020008) +#define HW_PCIEX2_CTRL2_APP_LTSSM_ENABLE BIT(4) +#define HW_PCIEX2_CTRL2_BUTTON_RST_N BIT(21) +#define HW_PCIEX2_CTRL2_PERST_N BIT(22) +#define HW_PCIEX2_CTRL2_POWER_UP_RST_N BIT(23) + +#define HW_PCIEX2_STTS0_ADDR (HSIO_CRR_BASE_ADDR + 0x0002000C) +#define HW_PCIEX2_STTS0_PM_REQ_CORE_RST BIT(19) + +#define HW_PCIEX1_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00030000) +#define HW_PCIEX1_CTRL0_DEVICE_TYPE_MASK (0xF << 24) +#define HW_PCIEX1_CTRL0_DEVICE_TYPE_RC BIT(26) + +#define HW_PCIEX1_CTRL2_ADDR (HSIO_CRR_BASE_ADDR + 0x00030008) +#define HW_PCIEX1_CTRL2_APP_LTSSM_ENABLE BIT(4) +#define HW_PCIEX1_CTRL2_BUTTON_RST_N BIT(21) +#define HW_PCIEX1_CTRL2_PERST_N BIT(22) +#define HW_PCIEX1_CTRL2_POWER_UP_RST_N BIT(23) + +#define HW_PCIEX1_STTS0_ADDR (HSIO_CRR_BASE_ADDR + 0x0003000c) +#define HW_PCIEX1_STTS0_PM_REQ_CORE_RST BIT(19) + +/* PCIe Port Logic registers (memory-mapped) */ +#define PF0_PORT_LOGIC (PCIE_CTRLA_BASE_ADDR + 0x700) +#define PF1_PORT_LOGIC (PCIE_CTRLB_BASE_ADDR + 0x700) + +#define PORT0_LINK_CTRL (PF0_PORT_LOGIC + 0x10) +#define PORT1_LINK_CTRL (PF1_PORT_LOGIC + 0x10) +#define PORT_LINK_CTRL_LNK_EN_MASK (0x3F << 16) +#define PORT_LINK_CTRL_LNK_LANE1 (0x1 << 16) +#define PORT_LINK_CTRL_LNK_LANE2 (0x3 << 16) +#define PORT_LINK_CTRL_LNK_FAST_LNK BIT(7) + +#define PORT0_LINK_DEBUG1 (PF0_PORT_LOGIC + 0x2C) +#define PORT1_LINK_DEBUG1 (PF1_PORT_LOGIC + 0x2C) +#define PORT_LINK_DEBUG1_LINK_UP BIT(4) + +#define PORT0_GEN2_CTRL (PF0_PORT_LOGIC + 0x10C) +#define PORT1_GEN2_CTRL (PF1_PORT_LOGIC + 0x10C) +#define PORT_GEN2_CTRL_NUM_LANES_MASK (0xFF << 8) +#define PORT_GEN2_CTRL_NUM_LANES_1 (0x1 << 8) +#define PORT_GEN2_CTRL_NUM_LANES_2 (0x2 << 8) + +#define PORT0_MISC_CONTROL_1 (PF0_PORT_LOGIC + 0x1BC) +#define PORT1_MISC_CONTROL_1 (PF1_PORT_LOGIC + 0x1BC) + +#define PORT0_DBI_LNK_STS_CTRL2 (PCIE_CTRLA_BASE_ADDR + 0xA0) + +#define PF0_TYPE1_HDR (PCIE_CTRLA_BASE_ADDR + 0x0) +#define PF0_TYPE1_STATUS_COMMAND_REG (PF0_TYPE1_HDR + 0x4) +#define PF1_TYPE1_HDR (PCIE_CTRLB_BASE_ADDR + 0x0) +#define PF1_TYPE1_STATUS_COMMAND_REG (PF1_TYPE1_HDR + 0x4) + +#define PF0_PCIE_CAP (PCIE_CTRLA_BASE_ADDR + 0x70) +#define PF0_LINK_CONTROL_LINK_STATUS_REG (PF0_PCIE_CAP + 0x10) +#define PF1_PCIE_CAP (PCIE_CTRLB_BASE_ADDR + 0x70) +#define PF1_LINK_CONTROL_LINK_STATUS_REG (PF1_PCIE_CAP + 0x10) + +#define PF0_SPICE_CAP (PCIE_CTRLA_BASE_ADDR + 0x148) +#define PF0_SPCIE_CAP_OFF_0CH_REG (PF0_SPICE_CAP + 0xC) +#define PF1_SPICE_CAP (PCIE_CTRLB_BASE_ADDR + 0x148) +#define PF1_SPCIE_CAP_OFF_0CH_REG (PF1_SPICE_CAP + 0xC) + +/* iATU registers */ +#define PCIE0_ATU_VIEWPORT (PCIE_CTRLA_BASE_ADDR + 0x900) +#define PCIE1_ATU_VIEWPORT (PCIE_CTRLB_BASE_ADDR + 0x900) +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE0_ATU_CR1 (PCIE_CTRLA_BASE_ADDR + 0x904) +#define PCIE1_ATU_CR1 (PCIE_CTRLB_BASE_ADDR + 0x904) +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE0_ATU_CR2 (PCIE_CTRLA_BASE_ADDR + 0x908) +#define PCIE1_ATU_CR2 (PCIE_CTRLB_BASE_ADDR + 0x908) +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE0_ATU_LOWER_BASE (PCIE_CTRLA_BASE_ADDR + 0x90C) +#define PCIE0_ATU_UPPER_BASE (PCIE_CTRLA_BASE_ADDR + 0x910) +#define PCIE0_ATU_LIMIT (PCIE_CTRLA_BASE_ADDR + 0x914) +#define PCIE0_ATU_LOWER_TARGET (PCIE_CTRLA_BASE_ADDR + 0x918) +#define PCIE0_ATU_UPPER_TARGET (PCIE_CTRLA_BASE_ADDR + 0x91C) +#define PCIE1_ATU_LOWER_BASE (PCIE_CTRLB_BASE_ADDR + 0x90C) +#define PCIE1_ATU_UPPER_BASE (PCIE_CTRLB_BASE_ADDR + 0x910) +#define PCIE1_ATU_LIMIT (PCIE_CTRLB_BASE_ADDR + 0x914) +#define PCIE1_ATU_LOWER_TARGET (PCIE_CTRLB_BASE_ADDR + 0x918) +#define PCIE1_ATU_UPPER_TARGET (PCIE_CTRLB_BASE_ADDR + 0x91C) + +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ + +#define pcie_readl(x) readl((unsigned long)x) +#define pcie_writel(v, c) writel(v, (unsigned long)c) +#define pcie_clrbits_le32(addr, clear) clrbits_le32((unsigned long)addr, clear) + +void mx8x_pcie_controller_reset(sc_ipc_t ipc, u32 SC_R_PCIE); +void mx8x_pcie_ctrla_setup_regions(void); +void mx8x_pcie_ctrlb_setup_regions(void); + +void mx8dv_pcie_init(void); +void mx8qm_pcie_init(void); +void mx8qxp_pcie_init(void); + +int sata_init(void); + +#endif /* _IMX8_HSIO_H_ */ diff --git a/arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h b/include/imx_lpi2c.h similarity index 100% rename from arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h rename to include/imx_lpi2c.h diff --git a/include/imx_m4_mu.h b/include/imx_m4_mu.h new file mode 100644 index 00000000000..b53e9e8b231 --- /dev/null +++ b/include/imx_m4_mu.h @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + */ + +#ifndef __IMX_M4_MU_H__ +#define __IMX_M4_MU_H__ + +enum imx_m4_msg_type { + MU_MSG_REQ = 0x1, /* request message sent from A side */ + MU_MSG_RESP = 0x2, /* response message from B side for request */ + MU_MSG_READY_A = 0x3, /* A side notifies ready */ + MU_MSG_READY_B = 0x4, /* B side notifies ready */ +}; + +union imx_m4_msg { + struct { + u32 seq; + u32 type; + u32 buffer; + u32 size; + } format; + u32 data[4]; +}; +#endif diff --git a/include/imx_mipi_dsi_bridge.h b/include/imx_mipi_dsi_bridge.h new file mode 100644 index 00000000000..a6f73c10436 --- /dev/null +++ b/include/imx_mipi_dsi_bridge.h @@ -0,0 +1,95 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_MIPI_DSIM_BRIDGE_H__ +#define __IMX_MIPI_DSIM_BRIDGE_H__ + +#include + +/* video mode */ +#define MIPI_DSI_MODE_VIDEO BIT(0) +/* video burst mode */ +#define MIPI_DSI_MODE_VIDEO_BURST BIT(1) +/* video pulse mode */ +#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2) +/* enable auto vertical count mode */ +#define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3) +/* enable hsync-end packets in vsync-pulse and v-porch area */ +#define MIPI_DSI_MODE_VIDEO_HSE BIT(4) +/* disable hfront-porch area */ +#define MIPI_DSI_MODE_VIDEO_HFP BIT(5) +/* disable hback-porch area */ +#define MIPI_DSI_MODE_VIDEO_HBP BIT(6) +/* disable hsync-active area */ +#define MIPI_DSI_MODE_VIDEO_HSA BIT(7) +/* flush display FIFO on vsync pulse */ +#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) +/* disable EoT packets in HS mode */ +#define MIPI_DSI_MODE_EOT_PACKET BIT(9) +/* device supports non-continuous clock behavior (DSI spec 5.6.1) */ +#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) +/* transmit data in low power */ +#define MIPI_DSI_MODE_LPM BIT(11) + +#define DSI_CMD_BUF_MAXSIZE (128) + +enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB888, + MIPI_DSI_FMT_RGB666, + MIPI_DSI_FMT_RGB666_PACKED, + MIPI_DSI_FMT_RGB565, +}; + +struct mipi_dsi_client_dev { + unsigned int channel; + unsigned int lanes; + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; + const char *name; +}; + +struct mipi_dsi_client_driver { + int (*dsi_client_setup)(struct mipi_dsi_client_dev *panel_dev); + const char *name; +}; + +struct mipi_dsi_bridge_driver { + int (*attach)(struct mipi_dsi_bridge_driver *bridge_driver, struct mipi_dsi_client_dev *dsi_dev); + int (*enable)(struct mipi_dsi_bridge_driver *bridge_driver); + int (*disable)(struct mipi_dsi_bridge_driver *bridge_driver); + int (*mode_set)(struct mipi_dsi_bridge_driver *bridge_driver, struct fb_videomode *pvmode); + int (*pkt_write)(struct mipi_dsi_bridge_driver *bridge_driver, u8 data_type, const u8 *buf, int len); + int (*add_client_driver)(struct mipi_dsi_bridge_driver *bridge_driver, struct mipi_dsi_client_driver *client_driver); + const char *name; + void *driver_private; +}; + +static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt) +{ + switch (fmt) { + case MIPI_DSI_FMT_RGB888: + case MIPI_DSI_FMT_RGB666: + return 24; + + case MIPI_DSI_FMT_RGB666_PACKED: + return 18; + + case MIPI_DSI_FMT_RGB565: + return 16; + } + + return -EINVAL; +} + +int imx_mipi_dsi_bridge_attach(struct mipi_dsi_client_dev *dsi_dev); +int imx_mipi_dsi_bridge_mode_set(struct fb_videomode *pvmode); +int imx_mipi_dsi_bridge_enable(void); +int imx_mipi_dsi_bridge_disable(void); +int imx_mipi_dsi_bridge_pkt_write(u8 data_type, const u8 *buf, int len); +int imx_mipi_dsi_bridge_add_client_driver(struct mipi_dsi_client_driver *client_driver); +int imx_mipi_dsi_bridge_register_driver(struct mipi_dsi_bridge_driver *driver); + +#endif diff --git a/include/imxdpuv1.h b/include/imxdpuv1.h new file mode 100644 index 00000000000..cb12bb8c0f1 --- /dev/null +++ b/include/imxdpuv1.h @@ -0,0 +1,998 @@ +/* + * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMXDPUV1_H +#define IMXDPUV1_H + +#include +#include + +/* these will be removed */ +#undef IMXDPUV1_VERSION_0 +#define IMXDPUV1_VERSION_1 + +/* #define DEBUG */ +/* #define ENABLE_IMXDPUV1_TRACE */ +/* #define ENABLE_IMXDPUV1_TRACE_REG */ +/* #define ENABLE_IMXDPUV1_TRACE_IRQ */ +/* #define ENABLE_IMXDPUV1_TRACE_IRQ_READ */ +/* #define ENABLE_IMXDPUV1_TRACE_IRQ_WRITE */ + +#ifdef ENABLE_IMXDPUV1_TRACE +#define IMXDPUV1_TRACE(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) +#else +#define IMXDPUV1_TRACE(fmt, ...) do {} while (0) +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ +#define IMXDPUV1_TRACE_IRQ(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) +#else +#define IMXDPUV1_TRACE_IRQ(fmt, ...) do {} while (0) +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_REG +#define IMXDPUV1_TRACE_REG(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) +#else +#define IMXDPUV1_TRACE_REG(fmt, ...) do {} while (0) +#endif + +#define IMXDPUV1_PRINT(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) + +/* #define IMXDPUV1_TCON0_MAP_24BIT_0_23 */ +/* #define IMXDPUV1_TCON1_MAP_24BIT_0_23 */ + +/* todo: this need to come from device tree */ +#define IMXDPUV1_NUM_DI_MAX 2 +#define IMXDPUV1_MAX_NUM 2 +#define IMXDPUV1_NUM_DI 2 +#define IMXDPUV1_NUM_CI 2 +#define IMXDPUV1_REGS_BASE_PHY0 0x56180000 +#define IMXDPUV1_REGS_BASE_PHY1 0x57180000 +#define IMXDPUV1_REGS_BASE_SIZE 0x14000 + +#ifdef IMXDPUV1_VERSION_0 +#define IMXDPUV1_ENABLE_INTSTAT2 +#endif +#define IMXDPUV1_SET_FIELD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +#define IMXDPUV1_GET_FIELD(field, reg) (((reg)&(field ## _MASK)) >> (field ## _SHIFT)) + +/* + IMXDPU windows, planes, layers, streams + + IMXDPU hardware documentation confuses the meaning of layers and + planes. These are software usages of these terms. + + window - a logical buffer of pixels in a rectangular arrangment. + Image, Integral and video planes suport one window. + Fractional and warp plane support 8 windows. Blending is not + supported between the sub-windows of a fractional or warp plane. + + sub-window - one of the eight logical windows of a fractional or warp + plane. + + channel - the logical DMA configuration for etiher a fetch or store unit + + plane - a plane is a hardware supported feature. There are four types + of display planes: + + video x2 + fractional x2 + intergral x2 + warp + + layer - each of the 7 planes is fed to a layer blender. Full Alpha + blending is supported for all of the planes fed to the layer + blender. + + streams - the layer bleder produces four streams: two normal streams + (0 and 1) and two panic streams (4 and 5). + + In normal mode, streams 0 and 1 are fed to the displays. + In panic mode, streams 4 and 5 are fed to the displays. +*/ + + +/*! + * Enumeration of IMXDPU blend mode flags + */ +typedef enum { + IMXDPUV1_PLANE_CLUT = 1 << 0, /* Color lookup */ + IMXDPUV1_PLANE_DECODE = 1 << 1, /* Decode compressed bufers */ + IMXDPUV1_PLANE_ETERNAL_ALPHA = 1 << 2, /* supports external alpha buffer */ + IMXDPUV1_PLANE_VIDEO_PROC = 1 << 2, /* Gamma, Matrix, Scaler, histogram */ + IMXDPUV1_PLANE_PLANAR = 1 << 3, /* Support Planar pixel buffers*/ + IMXDPUV1_PLANE_WARP = 1 << 4, /* Warping */ + IMXDPUV1_PLANE_MULTIWINDOW = 1 << 5, /* Support multiple buffers per plane */ + IMXDPUV1_PLANE_CAPTURE = 1 << 6, /* Video capture */ +} imxdpuv1_plane_features_t; + +/*! + * Enumeration of IMXDPU layer blend mode flags + */ +typedef enum { + IMXDPUV1_LAYER_NONE = 1 << 0, /* Disable blending */ + IMXDPUV1_LAYER_TRANSPARENCY = 1 << 1, /* Transparency */ + IMXDPUV1_LAYER_GLOBAL_ALPHA = 1 << 2, /* Global alpha mode */ + IMXDPUV1_LAYER_LOCAL_ALPHA = 1 << 3, /* Alpha contained in source buffer */ + IMXDPUV1_LAYER_EXTERN_ALPHA = 1 << 4, /* Alpha is contained in a separate plane */ + IMXDPUV1_LAYER_PRE_MULITPLY = 1 << 5, /* Pre-multiply alpha mode */ +} imxdpuv1_layer_blend_modes_t; + +/*! + * Enumeration of IMXDPU layers + */ +typedef enum { + IMXDPUV1_LAYER_0 = 0, + IMXDPUV1_LAYER_1, + IMXDPUV1_LAYER_2, + IMXDPUV1_LAYER_3, + IMXDPUV1_LAYER_4, +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_LAYER_5, + IMXDPUV1_LAYER_6, +#endif + IMXDPUV1_LAYER_MAX, +} imxdpuv1_layer_idx_t; + +/*! + * Enumeration of IMXDPU sub-windows + */ +typedef enum { + IMXDPUV1_SUBWINDOW_NONE = 0, + IMXDPUV1_SUBWINDOW_1, + IMXDPUV1_SUBWINDOW_2, + IMXDPUV1_SUBWINDOW_3, + IMXDPUV1_SUBWINDOW_4, + IMXDPUV1_SUBWINDOW_5, + IMXDPUV1_SUBWINDOW_6, + IMXDPUV1_SUBWINDOW_7, + IMXDPUV1_SUBWINDOW_8, +} imxdpuv1_subwindow_id_t; + +/*! + * Enumeration of IMXDPU display streams + */ +typedef enum { + IMXDPUV1_DISPLAY_STREAM_NONE = (0), + IMXDPUV1_DISPLAY_STREAM_0 = (1U<<0), + IMXDPUV1_DISPLAY_STREAM_1 = (1U<<1), + IMXDPUV1_DISPLAY_STREAM_4 = (1U<<4), + IMXDPUV1_DISPLAY_STREAM_5 = (1U<<5), +} imxdpuv1_display_stream_t; + +/*! + * Enumeration of IMXDPU rotation modes + */ +typedef enum { + /* todo: these need to aligh to imxdpu scan direction */ + IMXDPUV1_ROTATE_NONE = 0, + IMXDPUV1_ROTATE_VERT_FLIP = 1, + IMXDPUV1_ROTATE_HORIZ_FLIP = 2, + IMXDPUV1_ROTATE_180 = 3, + IMXDPUV1_ROTATE_90_RIGHT = 4, + IMXDPUV1_ROTATE_90_RIGHT_VFLIP = 5, + IMXDPUV1_ROTATE_90_RIGHT_HFLIP = 6, + IMXDPUV1_ROTATE_90_LEFT = 7, +} imxdpuv1_rotate_mode_t; + + +/*! + * Enumeration of types of buffers for a logical channel. + */ +typedef enum { + IMXDPUV1_OUTPUT_BUFFER = 0, /*!< Buffer for output from IMXDPU BLIT or capture */ + IMXDPUV1_ALPHA_IN_BUFFER = 1, /*!< Buffer for alpha input to IMXDPU */ + IMXDPUV1_GRAPH_IN_BUFFER = 2, /*!< Buffer for graphics input to IMXDPU */ + IMXDPUV1_VIDEO_IN_BUFFER = 3, /*!< Buffer for video input to IMXDPU */ +} imxdpuv1_buffer_t; + +#ifdef IMXDPUV1_VERSION_0 +/*! + * Enumeration of IMXDPU logical block ids + * NOTE: these match the hardware layout and are not arbitrary + */ +typedef enum { + IMXDPUV1_ID_NONE = 0, + IMXDPUV1_ID_FETCHDECODE9, + IMXDPUV1_ID_FETCHPERSP9, + IMXDPUV1_ID_FETCHECO9, + IMXDPUV1_ID_ROP9, + IMXDPUV1_ID_CLUT9, + IMXDPUV1_ID_MATRIX9, + IMXDPUV1_ID_HSCALER9, + IMXDPUV1_ID_VSCALER9, + IMXDPUV1_ID_FILTER9, + IMXDPUV1_ID_BLITBLEND9, + IMXDPUV1_ID_STORE9, + IMXDPUV1_ID_CONSTFRAME0, + IMXDPUV1_ID_EXTDST0, + IMXDPUV1_ID_CONSTFRAME4, + IMXDPUV1_ID_EXTDST4, + IMXDPUV1_ID_CONSTFRAME1, + IMXDPUV1_ID_EXTDST1, + IMXDPUV1_ID_CONSTFRAME5, + IMXDPUV1_ID_EXTDST5, + IMXDPUV1_ID_EXTSRC4, + IMXDPUV1_ID_STORE4, + IMXDPUV1_ID_EXTSRC5, + IMXDPUV1_ID_STORE5, + IMXDPUV1_ID_FETCHDECODE2, + IMXDPUV1_ID_FETCHDECODE3, + IMXDPUV1_ID_FETCHWARP2, + IMXDPUV1_ID_FETCHECO2, + IMXDPUV1_ID_FETCHDECODE0, + IMXDPUV1_ID_FETCHECO0, + IMXDPUV1_ID_FETCHDECODE1, + IMXDPUV1_ID_FETCHECO1, + IMXDPUV1_ID_FETCHLAYER0, + IMXDPUV1_ID_FETCHLAYER1, + IMXDPUV1_ID_GAMMACOR4, + IMXDPUV1_ID_MATRIX4, + IMXDPUV1_ID_HSCALER4, + IMXDPUV1_ID_VSCALER4, + IMXDPUV1_ID_HISTOGRAM4, + IMXDPUV1_ID_GAMMACOR5, + IMXDPUV1_ID_MATRIX5, + IMXDPUV1_ID_HSCALER5, + IMXDPUV1_ID_VSCALER5, + IMXDPUV1_ID_HISTOGRAM5, + IMXDPUV1_ID_LAYERBLEND0, + IMXDPUV1_ID_LAYERBLEND1, + IMXDPUV1_ID_LAYERBLEND2, + IMXDPUV1_ID_LAYERBLEND3, + IMXDPUV1_ID_LAYERBLEND4, + IMXDPUV1_ID_LAYERBLEND5, + IMXDPUV1_ID_LAYERBLEND6, + IMXDPUV1_ID_EXTSRC0, + IMXDPUV1_ID_EXTSRC1, + IMXDPUV1_ID_DISENGCFG, + IMXDPUV1_ID_FRAMEDUMP0, + IMXDPUV1_ID_FRAMEDUMP1, + IMXDPUV1_ID_FRAMEGEN0, + IMXDPUV1_ID_MATRIX0, + IMXDPUV1_ID_GAMMACOR0, + IMXDPUV1_ID_DITHER0, + IMXDPUV1_ID_TCON0, + IMXDPUV1_ID_SIG0, + IMXDPUV1_ID_FRAMEGEN1, + IMXDPUV1_ID_MATRIX1, + IMXDPUV1_ID_GAMMACOR1, + IMXDPUV1_ID_DITHER1, + IMXDPUV1_ID_TCON1, + IMXDPUV1_ID_SIG1, + IMXDPUV1_ID_CAPENGCFG, + IMXDPUV1_ID_FRAMECAP4, + IMXDPUV1_ID_FRAMECAP5, + IMXDPUV1_ID_ANALYSER4, + IMXDPUV1_ID_ANALYSER5, + /* the following are added arbitrarily */ + IMXDPUV1_ID_DPUXPC, + +} imxdpuv1_id_t; +#else +/*! + * Enumeration of IMXDPU logical block ids + * NOTE: these match the hardware layout and are not arbitrary + */ +typedef enum { + IMXDPUV1_ID_NONE = 0, + IMXDPUV1_ID_FETCHDECODE9, + IMXDPUV1_ID_FETCHWARP9, + IMXDPUV1_ID_FETCHECO9, + IMXDPUV1_ID_ROP9, + IMXDPUV1_ID_CLUT9, + IMXDPUV1_ID_MATRIX9, + IMXDPUV1_ID_HSCALER9, + IMXDPUV1_ID_VSCALER9, + IMXDPUV1_ID_FILTER9, + IMXDPUV1_ID_BLITBLEND9, + IMXDPUV1_ID_STORE9, + IMXDPUV1_ID_CONSTFRAME0, + IMXDPUV1_ID_EXTDST0, + IMXDPUV1_ID_CONSTFRAME4, + IMXDPUV1_ID_EXTDST4, + IMXDPUV1_ID_CONSTFRAME1, + IMXDPUV1_ID_EXTDST1, + IMXDPUV1_ID_CONSTFRAME5, + IMXDPUV1_ID_EXTDST5, + IMXDPUV1_ID_FETCHWARP2, + IMXDPUV1_ID_FETCHECO2, + IMXDPUV1_ID_FETCHDECODE0, + IMXDPUV1_ID_FETCHECO0, + IMXDPUV1_ID_FETCHDECODE1, + IMXDPUV1_ID_FETCHECO1, + IMXDPUV1_ID_FETCHLAYER0, + IMXDPUV1_ID_MATRIX4, + IMXDPUV1_ID_HSCALER4, + IMXDPUV1_ID_VSCALER4, + IMXDPUV1_ID_MATRIX5, + IMXDPUV1_ID_HSCALER5, + IMXDPUV1_ID_VSCALER5, + IMXDPUV1_ID_LAYERBLEND0, + IMXDPUV1_ID_LAYERBLEND1, + IMXDPUV1_ID_LAYERBLEND2, + IMXDPUV1_ID_LAYERBLEND3, + IMXDPUV1_ID_DISENGCFG, + IMXDPUV1_ID_FRAMEGEN0, + IMXDPUV1_ID_MATRIX0, + IMXDPUV1_ID_GAMMACOR0, + IMXDPUV1_ID_DITHER0, + IMXDPUV1_ID_TCON0, + IMXDPUV1_ID_SIG0, + IMXDPUV1_ID_FRAMEGEN1, + IMXDPUV1_ID_MATRIX1, + IMXDPUV1_ID_GAMMACOR1, + IMXDPUV1_ID_DITHER1, + IMXDPUV1_ID_TCON1, + IMXDPUV1_ID_SIG1, + IMXDPUV1_ID_DPUXPC, +} imxdpuv1_id_t; +#endif + +#ifdef IMXDPUV1_VERSION_0 +typedef enum { + IMXDPUV1_SHDLD_CONSTFRAME0 = 1U << 4, + IMXDPUV1_SHDLD_CONSTFRAME4 = 1U << 5, + IMXDPUV1_SHDLD_CONSTFRAME1 = 1U << 6, + IMXDPUV1_SHDLD_CONSTFRAME5 = 1U << 7, + IMXDPUV1_SHDLD_EXTSRC4 = 1U << 8, + IMXDPUV1_SHDLD_EXTSRC5 = 1U << 9, + IMXDPUV1_SHDLD_FETCHDECODE2 = 1U << 10, + IMXDPUV1_SHDLD_FETCHDECODE3 = 1U << 11, + IMXDPUV1_SHDLD_FETCHWARP2 = 1U << 12, + IMXDPUV1_SHDLD_FETCHECO2 = 1U << 13, + IMXDPUV1_SHDLD_FETCHDECODE0 = 1U << 14, + IMXDPUV1_SHDLD_FETCHECO0 = 1U << 15, + IMXDPUV1_SHDLD_FETCHDECODE1 = 1U << 16, + IMXDPUV1_SHDLD_FETCHECO1 = 1U << 17, + IMXDPUV1_SHDLD_FETCHLAYER0 = 1U << 18, + IMXDPUV1_SHDLD_FETCHLAYER1 = 1U << 19, + IMXDPUV1_SHDLD_EXTSRC0 = 1U << 20, + IMXDPUV1_SHDLD_EXTSRC1 = 1U << 21, +} imxdpuv1_shadow_load_req_id_t; +#else +typedef enum { + IMXDPUV1_SHDLD_CONSTFRAME0 = 1U << 4, + IMXDPUV1_SHDLD_CONSTFRAME4 = 1U << 5, + IMXDPUV1_SHDLD_CONSTFRAME1 = 1U << 6, + IMXDPUV1_SHDLD_CONSTFRAME5 = 1U << 7, + IMXDPUV1_SHDLD_FETCHWARP2 = 1U << 8, + IMXDPUV1_SHDLD_FETCHECO2 = 1U << 9, + IMXDPUV1_SHDLD_FETCHDECODE0 = 1U << 10, + IMXDPUV1_SHDLD_FETCHECO0 = 1U << 11, + IMXDPUV1_SHDLD_FETCHDECODE1 = 1U << 12, + IMXDPUV1_SHDLD_FETCHECO1 = 1U << 13, + IMXDPUV1_SHDLD_FETCHLAYER0 = 1U << 14, + + IMXDPUV1_SHDLD_EXTSRC4 = 0, + IMXDPUV1_SHDLD_EXTSRC5 = 0, + IMXDPUV1_SHDLD_FETCHDECODE2 = 0, + IMXDPUV1_SHDLD_FETCHDECODE3 = 0, + IMXDPUV1_SHDLD_FETCHLAYER1 = 0, + IMXDPUV1_SHDLD_EXTSRC0 = 0, + IMXDPUV1_SHDLD_EXTSRC1 = 0, + +} imxdpuv1_shadow_load_req_id_t; + + +#endif +typedef struct { + imxdpuv1_id_t primary; + imxdpuv1_id_t secondary; + imxdpuv1_display_stream_t stream; + bool enable; +} imxdpuv1_layer_t; + +typedef enum { + /* Fetch Channels */ + IMXDPUV1_CHAN_IDX_IN_FIRST = 0, + IMXDPUV1_CHAN_IDX_00 = 0, /* IMXDPUV1_ID_SRC_FETCHDECODE2 */ + IMXDPUV1_CHAN_IDX_01, /* IMXDPUV1_ID_SRC_FETCHDECODE0 */ + IMXDPUV1_CHAN_IDX_02, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_03, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_04, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_05, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_06, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_07, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_08, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_09, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_10, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_11, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_12, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_13, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_14, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_15, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_16, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_17, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_18, /* IMXDPUV1_ID_SRC_FETCHDECODE3 */ + IMXDPUV1_CHAN_IDX_19, /* IMXDPUV1_ID_SRC_FETCHDECODE1 */ + IMXDPUV1_CHAN_IDX_20, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_21, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_22, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_23, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_24, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_25, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_26, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_27, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_28, /* IMXDPUV1_ID_SRC_ECO0 */ + IMXDPUV1_CHAN_IDX_29, /* IMXDPUV1_ID_SRC_ECO1 */ + IMXDPUV1_CHAN_IDX_30, /* IMXDPUV1_ID_SRC_ECO2 */ + IMXDPUV1_CHAN_IDX_IN_MAX, /* Last fetch channel + 1 */ + + /* Store Channels */ + IMXDPUV1_CHAN_IDX_OUT_FIRST = 32, + IMXDPUV1_CHAN_IDX_32 = 32,/* IMXDPUV1_ID_DST_STORE4 */ + IMXDPUV1_CHAN_IDX_33, /* IMXDPUV1_ID_DST_STORE5 */ + IMXDPUV1_CHAN_IDX_OUT_MAX,/* Last fetch channel + 1 */ + IMXDPUV1_CHAN_IDX_MAX = IMXDPUV1_CHAN_IDX_OUT_MAX, +} imxdpuv1_chan_idx_t; + +typedef enum { + IMXDPUV1_SUB_NONE = 0, + IMXDPUV1_SUB_1 = 1U << 0, /* IMXDPUV1_ID_FETCHLAYER0, layer 1 */ + IMXDPUV1_SUB_2 = 1U << 1, /* IMXDPUV1_ID_FETCHLAYER0, layer 2 */ + IMXDPUV1_SUB_3 = 1U << 2, /* IMXDPUV1_ID_FETCHLAYER0, layer 3 */ + IMXDPUV1_SUB_4 = 1U << 3, /* IMXDPUV1_ID_FETCHLAYER0, layer 4 */ + IMXDPUV1_SUB_5 = 1U << 4, /* IMXDPUV1_ID_FETCHLAYER0, layer 5 */ + IMXDPUV1_SUB_6 = 1U << 5, /* IMXDPUV1_ID_FETCHLAYER0, layer 6 */ + IMXDPUV1_SUB_7 = 1U << 6, /* IMXDPUV1_ID_FETCHLAYER0, layer 7 */ + IMXDPUV1_SUB_8 = 1U << 7, /* IMXDPUV1_ID_FETCHLAYER0, layer 8 */ +} imxdpuv1_chan_sub_idx_t; + +/* IMXDPU Channel + * Consistist of four fields + * src - block id of source or destination + * sec - block id of secondary source for fetcheco + * sub - sub index of block for fetchlayer or fetchwarp + * idx - logical channel index + * + */ +#define make_channel(__blk_id, __eco_id, __sub, __idx) \ +(((__u32)(__idx)<<0)|((__u32)(__eco_id)<<8)|((__u32)(__sub)<<16)|((__u32)(__blk_id)<<24)) + +#define get_channel_blk(chan) (((__u32)(chan) >> 24) & 0xff) +#define get_channel_sub(chan) (((__u32)(chan) >> 16) & 0xff) +#define get_eco_idx(chan) (((__u32)(chan) >> 8) & 0xff) +#define get_channel_idx(chan) (((__u32)(chan) >> 0) & 0xff) +#define IMXDPUV1_SUBCHAN_LAYER_OFFSET 0x28 + +typedef enum { +#ifdef IMXDPUV1_VERSION_0 + /* Fetch Channels */ + IMXDPUV1_CHAN_00 = make_channel(IMXDPUV1_ID_FETCHDECODE2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 0), + IMXDPUV1_CHAN_01 = make_channel(IMXDPUV1_ID_FETCHDECODE0, 28, IMXDPUV1_SUB_NONE, 1), + IMXDPUV1_CHAN_02 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 2), + IMXDPUV1_CHAN_03 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 3), + IMXDPUV1_CHAN_04 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 4), + IMXDPUV1_CHAN_05 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 5), + IMXDPUV1_CHAN_06 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 6), + IMXDPUV1_CHAN_07 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 7), + IMXDPUV1_CHAN_08 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 8), + IMXDPUV1_CHAN_09 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 9), + IMXDPUV1_CHAN_10 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_1, 10), + IMXDPUV1_CHAN_11 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_2, 11), + IMXDPUV1_CHAN_12 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_3, 12), + IMXDPUV1_CHAN_13 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_4, 13), + IMXDPUV1_CHAN_14 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_5, 14), + IMXDPUV1_CHAN_15 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_6, 15), + IMXDPUV1_CHAN_16 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_7, 16), + IMXDPUV1_CHAN_17 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_8, 17), + IMXDPUV1_CHAN_18 = make_channel(IMXDPUV1_ID_FETCHDECODE3, 30, IMXDPUV1_SUB_NONE, 18), + IMXDPUV1_CHAN_19 = make_channel(IMXDPUV1_ID_FETCHDECODE1, 29, IMXDPUV1_SUB_NONE, 19), + IMXDPUV1_CHAN_20 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 20), + IMXDPUV1_CHAN_21 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 21), + IMXDPUV1_CHAN_22 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 22), + IMXDPUV1_CHAN_23 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 23), + IMXDPUV1_CHAN_24 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 24), + IMXDPUV1_CHAN_25 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 25), + IMXDPUV1_CHAN_26 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 26), + IMXDPUV1_CHAN_27 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 27), + IMXDPUV1_CHAN_28 = make_channel(IMXDPUV1_ID_FETCHECO0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 28), + IMXDPUV1_CHAN_29 = make_channel(IMXDPUV1_ID_FETCHECO1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 29), + IMXDPUV1_CHAN_30 = make_channel(IMXDPUV1_ID_FETCHECO2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 30), + /* Store Channels */ + IMXDPUV1_CHAN_32 = make_channel(IMXDPUV1_ID_STORE4, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 32), + IMXDPUV1_CHAN_33 = make_channel(IMXDPUV1_ID_STORE5, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 33), +#else + /* Fetch Channels */ + IMXDPUV1_CHAN_00 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_01 = make_channel(IMXDPUV1_ID_FETCHDECODE0, 28, IMXDPUV1_SUB_NONE, 1), + IMXDPUV1_CHAN_02 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 2), + IMXDPUV1_CHAN_03 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 3), + IMXDPUV1_CHAN_04 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 4), + IMXDPUV1_CHAN_05 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 5), + IMXDPUV1_CHAN_06 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 6), + IMXDPUV1_CHAN_07 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 7), + IMXDPUV1_CHAN_08 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 8), + IMXDPUV1_CHAN_09 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 9), + IMXDPUV1_CHAN_10 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_1, 10), + IMXDPUV1_CHAN_11 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_2, 11), + IMXDPUV1_CHAN_12 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_3, 12), + IMXDPUV1_CHAN_13 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_4, 13), + IMXDPUV1_CHAN_14 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_5, 14), + IMXDPUV1_CHAN_15 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_6, 15), + IMXDPUV1_CHAN_16 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_7, 16), + IMXDPUV1_CHAN_17 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_8, 17), + IMXDPUV1_CHAN_18 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_19 = make_channel(IMXDPUV1_ID_FETCHDECODE1, 29, IMXDPUV1_SUB_NONE, 19), + IMXDPUV1_CHAN_20 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_21 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_22 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_23 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_24 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_25 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_26 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_27 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_28 = make_channel(IMXDPUV1_ID_FETCHECO0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 28), + IMXDPUV1_CHAN_29 = make_channel(IMXDPUV1_ID_FETCHECO1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 29), + IMXDPUV1_CHAN_30 = make_channel(IMXDPUV1_ID_FETCHECO2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 30), + /* Store Channels */ + IMXDPUV1_CHAN_32 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_33 = make_channel(0, 0, 0, 0), +#endif +} imxdpuv1_chan_t; + +/* Aliases for Channels */ +#define IMXDPUV1_CHAN_VIDEO_0 IMXDPUV1_CHAN_01 +#define IMXDPUV1_CHAN_VIDEO_1 IMXDPUV1_CHAN_19 + +#define IMXDPUV1_CHAN_INTEGRAL_0 IMXDPUV1_CHAN_00 +#define IMXDPUV1_CHAN_INTEGRAL_1 IMXDPUV1_CHAN_18 + +#define IMXDPUV1_CHAN_FRACTIONAL_0_1 IMXDPUV1_CHAN_02 +#define IMXDPUV1_CHAN_FRACTIONAL_0_2 IMXDPUV1_CHAN_03 +#define IMXDPUV1_CHAN_FRACTIONAL_0_3 IMXDPUV1_CHAN_04 +#define IMXDPUV1_CHAN_FRACTIONAL_0_4 IMXDPUV1_CHAN_05 +#define IMXDPUV1_CHAN_FRACTIONAL_0_5 IMXDPUV1_CHAN_06 +#define IMXDPUV1_CHAN_FRACTIONAL_0_6 IMXDPUV1_CHAN_07 +#define IMXDPUV1_CHAN_FRACTIONAL_0_7 IMXDPUV1_CHAN_08 +#define IMXDPUV1_CHAN_FRACTIONAL_0_8 IMXDPUV1_CHAN_09 + +#define IMXDPUV1_CHAN_FRACTIONAL_1_1 IMXDPUV1_CHAN_20 +#define IMXDPUV1_CHAN_FRACTIONAL_1_2 IMXDPUV1_CHAN_21 +#define IMXDPUV1_CHAN_FRACTIONAL_1_3 IMXDPUV1_CHAN_22 +#define IMXDPUV1_CHAN_FRACTIONAL_1_4 IMXDPUV1_CHAN_23 +#define IMXDPUV1_CHAN_FRACTIONAL_1_5 IMXDPUV1_CHAN_24 +#define IMXDPUV1_CHAN_FRACTIONAL_1_6 IMXDPUV1_CHAN_25 +#define IMXDPUV1_CHAN_FRACTIONAL_1_7 IMXDPUV1_CHAN_26 +#define IMXDPUV1_CHAN_FRACTIONAL_1_8 IMXDPUV1_CHAN_27 + +#define IMXDPUV1_CHAN_WARP_2_1 IMXDPUV1_CHAN_10 +#define IMXDPUV1_CHAN_WARP_2_2 IMXDPUV1_CHAN_11 +#define IMXDPUV1_CHAN_WARP_2_3 IMXDPUV1_CHAN_12 +#define IMXDPUV1_CHAN_WARP_2_4 IMXDPUV1_CHAN_13 +#define IMXDPUV1_CHAN_WARP_2_5 IMXDPUV1_CHAN_14 +#define IMXDPUV1_CHAN_WARP_2_6 IMXDPUV1_CHAN_15 +#define IMXDPUV1_CHAN_WARP_2_7 IMXDPUV1_CHAN_16 +#define IMXDPUV1_CHAN_WARP_2_8 IMXDPUV1_CHAN_17 + +#define IMXDPUV1_CHAN_CAPTURE_0 IMXDPUV1_CHAN_32 +#define IMXDPUV1_CHAN_CAPTURE_1 IMXDPUV1_CHAN_33 + + +/* IMXDPU Pixel format definitions */ +/* Four-character-code (FOURCC) */ +#ifdef fourcc +#warning "fourcc is already defined ... redeifining it here!" +#undef fourcc +#endif +#define fourcc(a, b, c, d)\ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + + +/*! @} */ +/*! @name Generic Formats */ +/*! @{ */ +#define IMXDPUV1_PIX_FMT_GENERIC fourcc('D', 'P', 'U', '0') /*!< IPU Generic Data */ +#define IMXDPUV1_PIX_FMT_GENERIC_32 fourcc('D', 'P', 'U', '1') /*!< IPU Generic Data */ +#define IMXDPUV1_PIX_FMT_GENERIC_16 fourcc('D', 'P', 'U', '2') /*!< IPU Generic Data */ + +/*! @} */ +/*! @name RGB Formats */ +/*! @{ */ +#define IMXDPUV1_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */ +#define IMXDPUV1_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */ +#define IMXDPUV1_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 16 RGB-5-6-5 */ +#define IMXDPUV1_PIX_FMT_BGRA4444 fourcc('4', '4', '4', '4') /*!< 16 RGBA-4-4-4-4 */ +#define IMXDPUV1_PIX_FMT_BGRA5551 fourcc('5', '5', '5', '1') /*!< 16 RGBA-5-5-5-1 */ +#define IMXDPUV1_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */ +#define IMXDPUV1_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */ +#define IMXDPUV1_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */ +#define IMXDPUV1_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */ +#define IMXDPUV1_PIX_FMT_GBR24 fourcc('G', 'B', 'R', '3') /*!< 24 GBR-8-8-8 */ +#define IMXDPUV1_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_ARGB32 fourcc('A', 'R', 'G', 'B') /*!< 32 ARGB-8-8-8-8 */ + +/*! @} */ +/*! @name YUV Interleaved Formats */ +/*! @{ */ +#define IMXDPUV1_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */ +#define IMXDPUV1_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */ +#define IMXDPUV1_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVYU 4:2:2 */ +#define IMXDPUV1_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 VYYU 4:2:2 */ +#define IMXDPUV1_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */ +#define IMXDPUV1_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */ +#define IMXDPUV1_PIX_FMT_VYU444 fourcc('V', '4', '4', '4') /*!< 24 VYU 4:4:4 */ +#define IMXDPUV1_PIX_FMT_AYUV fourcc('A', 'Y', 'U', 'V') /*!< 32 AYUV 4:4:4:4 */ + +/* two planes -- one Y, one Cb + Cr interleaved */ +#define IMXDPUV1_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ +#define IMXDPUV1_PIX_FMT_NV16 fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ + +#define IMXDPUV1_CAP_FMT_RGB24 fourcc('R', 'G', 'B', '3') +#define IMXDPUV1_CAP_FMT_BT656 fourcc('B', '6', '5', '6') +#define IMXDPUV1_CAP_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') + +struct imxdpuv1_soc; +/*! + * Definition of IMXDPU rectangle structure + */ +typedef struct { + int16_t top; /* y coordinate of top/left pixel */ + int16_t left; /* x coordinate top/left pixel */ + int16_t width; + int16_t height; +} imxdpuv1_rect_t; + + +/*! + * Union of initialization parameters for a logical channel. + */ +typedef union { + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; /* capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + } common; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t capture_id; /* disp_id/capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + uint32_t h_scale_factor; /* downscaling out/in */ + uint32_t h_phase; + uint32_t v_scale_factor; /* downscaling out/in */ + uint32_t v_phase[2][2]; + bool use_video_proc; + bool interlaced; + } store; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + uint32_t h_scale_factor; /* downscaling out/in */ + uint32_t h_phase; + uint32_t v_scale_factor; /* downscaling out/in */ + uint32_t v_phase[2][2]; + bool use_video_proc; + bool interlaced; + } fetch_decode; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; /* capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + } fetch_layer; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; /* capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + } fetch_warp; +} imxdpuv1_channel_params_t; + +/*! + * Enumeration of IMXDPU video mode flags + */ +enum imxdpuv1_mode_flags { + /* 1 is active high 0 is active low */ + IMXDPUV1_MODE_FLAGS_HSYNC_POL = 1 << 0, + IMXDPUV1_MODE_FLAGS_VSYNC_POL = 1 << 1, + IMXDPUV1_MODE_FLAGS_DE_POL = 1 << 2, + + /* drive data on positive .edge */ + IMXDPUV1_MODE_FLAGS_CLK_POL = 1 << 3, + + IMXDPUV1_MODE_FLAGS_INTERLACED = 1 << 4 , + + /* Left/Right Synchronous display mode, both display pipe are + combined to make one display. All mode timings are divided by + two for each half screen. + Note: This may not be needed we may force this for any width + over ~2048 + */ + IMXDPUV1_MODE_FLAGS_LRSYNC = 1 << 8, + + /* Split mode each pipe is split into two displays */ + IMXDPUV1_MODE_FLAGS_SPLIT = 1 << 9, + + IMXDPUV1_MODE_FLAGS_32BIT = 1 << 16, + IMXDPUV1_MODE_FLAGS_BT656_10BIT = 1 << 17, + IMXDPUV1_MODE_FLAGS_BT656_8BIT = 1 << 18, +}; + +struct imxdpuv1_videomode { + char name[64]; /* may not be needed */ + + uint32_t pixelclock; /* Hz */ + + /* htotal (pixels) = hlen + hfp + hsync + hbp */ + uint32_t hlen; + uint32_t hfp; + uint32_t hbp; + uint32_t hsync; + + /* field0 - vtotal (lines) = vlen + vfp + vsync + vbp */ + uint32_t vlen; + uint32_t vfp; + uint32_t vbp; + uint32_t vsync; + + /* field1 */ + uint32_t vlen1; + uint32_t vfp1; + uint32_t vbp1; + uint32_t vsync1; + + uint32_t flags; + uint32_t format; + uint32_t dest_format; /*buffer format for capture*/ + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + +}; + +#define IMXDPUV1_ENABLE 1 +#define IMXDPUV1_DISABLE 0 + +#define IMXDPUV1_TRUE 1 +#define IMXDPUV1_FALSE 0 +#define IMXDPUV1_OFFSET_INVALID 0x10000000 /* this should force an access error */ +#define IMXDPUV1_CHANNEL_INVALID 0x0 /* this should force an access error */ + +#define IMXDPUV1_MIN(_X, _Y) ((_X) < (_Y) ? (_X) : (_Y)) + +/* Native color type */ +#define IMXDPUV1_COLOR_CONSTALPHA_MASK 0xFFU +#define IMXDPUV1_COLOR_CONSTALPHA_SHIFT 0U +#define IMXDPUV1_COLOR_CONSTBLUE_MASK 0xFF00U +#define IMXDPUV1_COLOR_CONSTBLUE_SHIFT 8U +#define IMXDPUV1_COLOR_CONSTGREEN_MASK 0xFF0000U +#define IMXDPUV1_COLOR_CONSTGREEN_SHIFT 16U +#define IMXDPUV1_COLOR_CONSTRED_MASK 0xFF000000U +#define IMXDPUV1_COLOR_CONSTRED_SHIFT 24U + +#define IMXDPUV1_IRQF_NONE 0x0 +#define IMXDPUV1_IRQF_ONESHOT 0x1 +#define IMXDPUV1_INTERRUPT_MAX (66 + 1) /* IMXDPUV1_FRAMECAP5_SYNC_OFF_IRQ + (66) is last interrupt */ + +int imxdpuv1_enable_irq(int8_t imxdpuv1_id, uint32_t irq); +int imxdpuv1_disable_irq(int8_t imxdpuv1_id, uint32_t irq); +int imxdpuv1_clear_all_irqs(int8_t imxdpuv1_id); +int imxdpuv1_clear_irq(int8_t imxdpuv1_id, uint32_t irq); +int imxdpuv1_init_irqs(int8_t imxdpuv1_id); +int imxdpuv1_request_irq(int8_t imxdpuv1_id, + uint32_t irq, + int(*handler) (int, void *), + uint32_t irq_flags, + const char *devname, void *data) ; +int imxdpuv1_free_irq(int8_t imxdpuv1_id, uint32_t irq, void *data); +int imxdpuv1_uninit_interrupts(int8_t imxdpuv1_id); +int imxdpuv1_handle_irq(int32_t imxdpuv1_id); +struct imxdpuv1_soc *imxdpuv1_get_soc(int8_t imxdpuv1_id); +int imxdpuv1_init(int8_t imxdpuv1_id); +int imxdpuv1_init_sync_panel(int8_t imxdpuv1_id, int8_t disp, + uint32_t pixel_fmt, + struct imxdpuv1_videomode mode); +int imxdpuv1_uninit_sync_panel(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_reset_disp_panel(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_disp_init(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_disp_setup_frame_gen( + int8_t imxdpuv1_id, + int8_t disp, + const struct imxdpuv1_videomode *mode, + uint16_t cc_red, /* 10 bits */ + uint16_t cc_green, /* 10 bits */ + uint16_t cc_blue, /* 10 bits */ + uint8_t cc_alpha, + bool test_mode_enable); +int imxdpuv1_disp_enable_frame_gen(int8_t imxdpuv1_id, + int8_t disp, + bool enable); +int imxdpuv1_disp_setup_constframe(int8_t imxdpuv1_id, + int8_t disp, + uint8_t bg_red, + uint8_t bg_green, + uint8_t bg_blue, + uint8_t bg_alpha); +int imxdpuv1_disp_setup_layer(int8_t imxdpuv1_id, + const imxdpuv1_layer_t *layer, + imxdpuv1_layer_idx_t layer_idx, + bool is_top_layer); +void imxdpuv1_disp_dump_mode(const struct imxdpuv1_videomode *mode); +int imxdpuv1_bytes_per_pixel(uint32_t fmt); +int imxdpuv1_init_channel_buffer(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t stride, + imxdpuv1_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, + uint32_t u_offset, + uint32_t v_offset); +int32_t imxdpuv1_update_channel_buffer(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + dma_addr_t phyaddr_0); +int imxdpuv1_init_channel(int8_t imxdpuv1_id, + imxdpuv1_channel_params_t *params); +int imxdpuv1_disp_set_layer_global_alpha(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + uint8_t alpha); +int imxdpuv1_disp_set_layer_position(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + int16_t x, int16_t y); +int imxdpuv1_disp_set_chan_position(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + int16_t x, int16_t y); +int imxdpuv1_disp_update_fgen_status(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_disp_show_fgen_status(int8_t imxdpuv1_id); +void imxdpuv1_dump_int_stat(int8_t imxdpuv1_id); +void imxdpuv1_dump_layerblend(int8_t imxdpuv1_id); +int imxdpuv1_disp_force_shadow_load(int8_t imxdpuv1_id, + int8_t disp, + uint64_t mask); +int imxdpuv1_disp_set_chan_crop(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height); +void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id); +int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan); +uint32_t imxdpuv1_get_planes(uint32_t fmt); + +int imxdpuv1_disp_setup_channel(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t src_pixel_fmt, + uint16_t src_width, + uint16_t src_height, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + uint16_t stride, + uint8_t disp_id, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height, + uint32_t const_color, + bool use_global_alpha, + bool use_local_alpha, + unsigned int disp_addr); +int imxdpuv1_disp_check_shadow_loads(int8_t imxdpuv1_id, int8_t disp); + +int imxdpuv1_cap_setup_frame( + int8_t imxdpuv1_id, + int8_t src_id, + int8_t dest_id, + int8_t sync_count, + const struct imxdpuv1_videomode *cap_mode); +int imxdpuv1_cap_setup_crop( + int8_t imxdpuv1_id, + int8_t src_id, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height); + +int imxdpuv1_cap_enable(int8_t imxdpuv1_id, int8_t cap, bool enable); +int imxdpuv1_cap_request_shadow_load(int8_t imxdpuv1_id, int8_t dest_id, uint32_t mask); + +/* FIXME: add api if needed */ +static inline int32_t imxdpuv1_csi_enable_mclk_if(int8_t imxdpuv1_id, int src, uint32_t cap, + bool flag, bool wait) +{ + printf("%s(): %s:%d stubbed feature\n", __func__, __FILE__, __LINE__); + return 0; +} +#endif /* IMXDPUV1_H */ diff --git a/include/imxdpuv1_events.h b/include/imxdpuv1_events.h new file mode 100644 index 00000000000..7f8ed8157d0 --- /dev/null +++ b/include/imxdpuv1_events.h @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2005-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMXDPUV1_EVENTS_H +#define IMXDPUV1_EVENTS_H + +/* Shadow load (Blit Engine) */ +#define IMXDPUV1_STORE9_SHDLOAD_IRQ 0U +#define IMXDPUV1_STORE9_SHDLOAD_CMD 0U + +/* Frame complete (Blit Engine) */ +#define IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ 1U +#define IMXDPUV1_STORE9_FRAMECOMPLETE_CMD 1U + +/* Sequence complete (Blit Engine) */ +#define IMXDPUV1_STORE9_SEQCOMPLETE_IRQ 2U +#define IMXDPUV1_STORE9_SEQCOMPLETE_CMD 2U + +/* Shadow load (Display Controller Content Stream 0) */ +#define IMXDPUV1_EXTDST0_SHDLOAD_IRQ 3U +#define IMXDPUV1_EXTDST0_SHDLOAD_CMD 3U + +/* Frame complete (Display Controller Content Stream 0) */ +#define IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ 4U +#define IMXDPUV1_EXTDST0_FRAMECOMPLETE_CMD 4U + +/* Sequence complete (Display Controller Content Stream 0) */ +#define IMXDPUV1_EXTDST0_SEQCOMPLETE_IRQ 5U +#define IMXDPUV1_EXTDST0_SEQCOMPLETE_CMD 5U + +/* Shadow load (Display Controller Safety Stream 0) */ +#define IMXDPUV1_EXTDST4_SHDLOAD_IRQ 6U +#define IMXDPUV1_EXTDST4_SHDLOAD_CMD 6U + +/* Frame complete (Display Controller Safety Stream 0) */ +#define IMXDPUV1_EXTDST4_FRAMECOMPLETE_IRQ 7U +#define IMXDPUV1_EXTDST4_FRAMECOMPLETE_CMD 7U + +/* Sequence complete (Display Controller Safety Stream 0) */ +#define IMXDPUV1_EXTDST4_SEQCOMPLETE_IRQ 8U +#define IMXDPUV1_EXTDST4_SEQCOMPLETE_CMD 8U + +/* Shadow load (Display Controller Content Stream 1) */ +#define IMXDPUV1_EXTDST1_SHDLOAD_IRQ 9U +#define IMXDPUV1_EXTDST1_SHDLOAD_CMD 9U + +/* Frame complete (Display Controller Content Stream 1) */ +#define IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ 10U +#define IMXDPUV1_EXTDST1_FRAMECOMPLETE_CMD 10U + +/* Sequence complete (Display Controller Content Stream 1) */ +#define IMXDPUV1_EXTDST1_SEQCOMPLETE_IRQ 11U +#define IMXDPUV1_EXTDST1_SEQCOMPLETE_CMD 11U + +/* Shadow load (Display Controller Safety Stream 1) */ +#define IMXDPUV1_EXTDST5_SHDLOAD_IRQ 12U +#define IMXDPUV1_EXTDST5_SHDLOAD_CMD 12U + +/* Frame complete (Display Controller Safety Stream 1) */ +#define IMXDPUV1_EXTDST5_FRAMECOMPLETE_IRQ 13U +#define IMXDPUV1_EXTDST5_FRAMECOMPLETE_CMD 13U + +/* Sequence complete (Display Controller Safety Stream 1) */ +#define IMXDPUV1_EXTDST5_SEQCOMPLETE_IRQ 14U +#define IMXDPUV1_EXTDST5_SEQCOMPLETE_CMD 14U + +/* Shadow load (Display Controller Display Stream 0) */ +#define IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ 15U +#define IMXDPUV1_DISENGCFG_SHDLOAD0_CMD 15U + +/* Frame complete (Display Controller Display Stream 0) */ +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ 16U +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_CMD 16U + +/* Sequence complete (Display Controller Display Stream 0) */ +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE0_IRQ 17U +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE0_CMD 17U + +/* Programmable interrupt 0 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT0_IRQ 18U +#define IMXDPUV1_FRAMEGEN0_INT0_CMD 18U + +/* Programmable interrupt 1 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT1_IRQ 19U +#define IMXDPUV1_FRAMEGEN0_INT1_CMD 19U + +/* Programmable interrupt 2 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT2_IRQ 20U +#define IMXDPUV1_FRAMEGEN0_INT2_CMD 20U + +/* Programmable interrupt 3 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT3_IRQ 21U +#define IMXDPUV1_FRAMEGEN0_INT3_CMD 21U + +/* Shadow load (Display Controller Display Stream 0 Sig #0 unit) */ +#define IMXDPUV1_SIG0_SHDLOAD_IRQ 22U +#define IMXDPUV1_SIG0_SHDLOAD_CMD 22U + +/* Measurement valid (Display Controller Display Stream 0 Sig #0 unit) */ +#define IMXDPUV1_SIG0_VALID_IRQ 23U +#define IMXDPUV1_SIG0_VALID_CMD 23U + +/* Error condition (Display Controller Display Stream 0 Sig #0 unit) */ +#define IMXDPUV1_SIG0_ERROR_IRQ 24U +#define IMXDPUV1_SIG0_ERROR_CMD 24U + +/* Shadow load (Display Controller Display Stream 1) */ +#define IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ 25U +#define IMXDPUV1_DISENGCFG_SHDLOAD1_CMD 25U + +/* Frame complete (Display Controller Display Stream 1) */ +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE1_IRQ 26U +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE1_CMD 26U + +/* Sequence complete (Display Controller Display Stream 1) */ +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE1_IRQ 27U +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE1_CMD 27U + +/* Programmable interrupt 0 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT0_IRQ 28U +#define IMXDPUV1_FRAMEGEN1_INT0_CMD 28U + +/* Programmable interrupt 1 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT1_IRQ 29U +#define IMXDPUV1_FRAMEGEN1_INT1_CMD 29U + +/* Programmable interrupt 2 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT2_IRQ 30U +#define IMXDPUV1_FRAMEGEN1_INT2_CMD 30U + +/* Programmable interrupt 3 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT3_IRQ 31U +#define IMXDPUV1_FRAMEGEN1_INT3_CMD 31U + +/* Shadow load (Display Controller Display Stream 1 Sig #1 unit) */ +#define IMXDPUV1_SIG1_SHDLOAD_IRQ 32U +#define IMXDPUV1_SIG1_SHDLOAD_CMD 32U + +/* Measurement valid (Display Controller Display Stream 1 Sig #1 unit) */ +#define IMXDPUV1_SIG1_VALID_IRQ 33U +#define IMXDPUV1_SIG1_VALID_CMD 33U + +/* Error condition (Display Controller Display Stream 1 Sig #1 unit) */ +#define IMXDPUV1_SIG1_ERROR_IRQ 34U +#define IMXDPUV1_SIG1_ERROR_CMD 34U + +/* Reserved Do not use */ +#define IMXDPUV1_RESERVED35_IRQ 35U +#define IMXDPUV1_RESERVED35_CMD 35U + +/* Error condition (Command Sequencer) */ +#define IMXDPUV1_CMDSEQ_ERROR_IRQ 36U +#define IMXDPUV1_CMDSEQ_ERROR_CMD 36U + +/* Software interrupt 0 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW0_IRQ 37U +#define IMXDPUV1_COMCTRL_SW0_CMD 37U + +/* Software interrupt 1 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW1_IRQ 38U +#define IMXDPUV1_COMCTRL_SW1_CMD 38U + +/* Software interrupt 2 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW2_IRQ 39U +#define IMXDPUV1_COMCTRL_SW2_CMD 39U + +/* Software interrupt 3 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW3_IRQ 40U +#define IMXDPUV1_COMCTRL_SW3_CMD 40U + +/* Synchronization status activated (Display Controller Safety stream 0) */ +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_ON_IRQ 41U +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_ON_CMD 41U + +/* Synchronization status deactivated (Display Controller Safety stream 0) */ +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_OFF_IRQ 42U +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_OFF_CMD 42U + +/* Synchronization status activated (Display Controller Content stream 0) */ +#define IMXDPUV1_FRAMEGEN0_SECSYNC_ON_IRQ 43U +#define IMXDPUV1_FRAMEGEN0_SECSYNC_ON_CMD 43U + +/* Synchronization status deactivated (Display Controller Content stream 0) */ +#define IMXDPUV1_FRAMEGEN0_SECSYNC_OFF_IRQ 44U +#define IMXDPUV1_FRAMEGEN0_SECSYNC_OFF_CMD 44U + +/* Synchronization status activated (Display Controller Safety stream 1) */ +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_ON_IRQ 45U +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_ON_CMD 45U + +/* Synchronization status deactivated (Display Controller Safety stream 1) */ +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_OFF_IRQ 46U +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_OFF_CMD 46U + +/* Synchronization status activated (Display Controller Content stream 1) */ +#define IMXDPUV1_FRAMEGEN1_SECSYNC_ON_IRQ 47U +#define IMXDPUV1_FRAMEGEN1_SECSYNC_ON_CMD 47U + +/* Synchronization status deactivated (Display Controller Content stream 1) */ +#define IMXDPUV1_FRAMEGEN1_SECSYNC_OFF_IRQ 48U +#define IMXDPUV1_FRAMEGEN1_SECSYNC_OFF_CMD 48U + +/* Synchronization status (Display Controller Safety stream 0) */ +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_CMD 49U +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_STS 0U + +/* Synchronization status (Display Controller Content stream 0) */ +#define IMXDPUV1_FRAMEGEN0_SECSYNC_CMD 50U +#define IMXDPUV1_FRAMEGEN0_SECSYNC_STS 1U + +/* Synchronization status (Display Controller Safety stream 1) */ +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_CMD 51U +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_STS 2U + +/* Synchronization status (Display Controller Content stream 1) */ +#define IMXDPUV1_FRAMEGEN1_SECSYNC_CMD 52U +#define IMXDPUV1_FRAMEGEN1_SECSYNC_STS 3U + +/* Shadow load request (Display Controller Pixel Engine configuration Store #9 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_STORE9_SHDLDREQ_CMD 53U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #0 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_SHDLDREQ_CMD 54U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #4 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_SHDLDREQ_CMD 55U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #1 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_SHDLDREQ_CMD 56U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #5 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_SHDLDREQ_CMD 57U + +/* Shadow load request (Blit Engine FetchDecode #9 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_SHDLDREQ_CMD 58U + +/* Shadow load request (Blit Engine FetchWarp #9 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_SHDLDREQ_CMD 59U + +/* Shadow load request (Blit Engine FetchEco #9 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_SHDLDREQ_CMD 60U + +/* Shadow load request (Display Controller ConstFrame #0 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_SHDLDREQ_CMD 61U + +/* Shadow load request (Display Controller ConstFrame #4 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_SHDLDREQ_CMD 62U + +/* Shadow load request (Display Controller ConstFrame #1 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_SHDLDREQ_CMD 63U + +/* Shadow load request (Display Controller ConstFrame #5 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_SHDLDREQ_CMD 64U + +/* Shadow load request (Display Controller FetchWarp #2 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_SHDLDREQ_CMD 65U + +/* Shadow load request (Display Controller FetchEco #2 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_SHDLDREQ_CMD 66U + +/* Shadow load request (Display Controller FetchDecode #0 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_SHDLDREQ_CMD 67U + +/* Shadow load request (Display Controller FetchEco #0 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_SHDLDREQ_CMD 68U + +/* Shadow load request (Display Controller FetchDecode #1 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_SHDLDREQ_CMD 69U + +/* Shadow load request (Display Controller FetchEco #1 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_SHDLDREQ_CMD 70U + +/* Shadow load request (Display Controller FetchLayer #0 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_SHDLDREQ_CMD 71U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 0) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ0_CMD 72U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 1) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ1_CMD 73U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 2) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ2_CMD 74U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 3) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ3_CMD 75U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 4) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ4_CMD 76U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 5) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ5_CMD 77U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 6) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ6_CMD 78U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 7) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ7_CMD 79U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 0) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ0_CMD 80U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 1) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ1_CMD 81U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 2) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ2_CMD 82U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 3) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ3_CMD 83U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 4) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ4_CMD 84U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 5) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ5_CMD 85U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 6) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ6_CMD 86U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 7) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ7_CMD 87U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 0) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ0_CMD 88U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 1) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ1_CMD 89U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 2) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ2_CMD 90U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 3) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ3_CMD 91U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 4) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ4_CMD 92U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 5) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ5_CMD 93U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 6) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ6_CMD 94U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 7) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ7_CMD 95U + + +#endif /* IMXDPUV1_EVENTS */ diff --git a/include/imxdpuv1_registers.h b/include/imxdpuv1_registers.h new file mode 100644 index 00000000000..eb9676b0bbf --- /dev/null +++ b/include/imxdpuv1_registers.h @@ -0,0 +1,22682 @@ +/* + * Copyright (c) 2005-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/* Instance: IMXDPU */ + +#ifndef IMXDPUV1_REGISTERS_H +#define IMXDPUV1_REGISTERS_H +/* Register: IMXDPUV1_comctrl_IPIdentifier */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER ((uint32_t)(0)) +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_RESET_VALUE 0x21340400U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNDELIVERYID_MASK 0xF0U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNDELIVERYID_SHIFT 4U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL_MASK 0xF00U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL_SHIFT 8U +/* Field Value: DESIGNMATURITYLEVEL__PREFS, Pre feasibility study. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__PREFS 0x1U +/* Field Value: DESIGNMATURITYLEVEL__FS, Feasibility study. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__FS 0x2U +/* Field Value: DESIGNMATURITYLEVEL__R0, Functionality complete. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__R0 0x3U +/* Field Value: DESIGNMATURITYLEVEL__R1, Verification complete. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__R1 0x4U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPEVOLUTION_MASK 0xF000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPEVOLUTION_SHIFT 12U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET_MASK 0xF0000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET_SHIFT 16U +/* Field Value: IPFEATURESET__E, Minimal functionality (Eco). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__E 0x1U +/* Field Value: IPFEATURESET__L, Reduced functionality (Light). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__L 0x2U +/* Field Value: IPFEATURESET__P, Advanced functionality (Plus). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__P 0x4U +/* Field Value: IPFEATURESET__X, Extensive functionality (eXtensive). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__X 0x5U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION_MASK 0xF00000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION_SHIFT 20U +/* Field Value: IPAPPLICATION__B, Blit Engine only. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__B 0x1U +/* Field Value: IPAPPLICATION__D, Blit Engine and Display Controller. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__D 0x2U +/* Field Value: IPAPPLICATION__V, Display Controller only (with direct capture). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__V 0x3U +/* Field Value: IPAPPLICATION__G, Blit Engine, Display Controller (with direct + * capture), Capture Controller (buffered capture) and Drawing Engine. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__G 0x4U +/* Field Value: IPAPPLICATION__C, Display Controller only. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__C 0x5U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION_MASK 0xF000000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION_SHIFT 24U +/* Field Value: IPCONFIGURATION__M, Graphics core only (Module). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION__M 0x1U +/* Field Value: IPCONFIGURATION__S, Subsystem including a graphics core (System). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION__S 0x2U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY_MASK 0xF0000000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY_SHIFT 28U +/* Field Value: IPFAMILY__IMXDPU2010, IMXDPU building block generation 2010. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2010 0U +/* Field Value: IPFAMILY__IMXDPU2012, IMXDPU building block generation 2012. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2012 0x1U +/* Field Value: IPFAMILY__IMXDPU2013, IMXDPU building block generation 2013. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2013 0x2U + +/* Register: IMXDPUV1_comctrl_LockUnlock */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK ((uint32_t)(0x40)) +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_comctrl_LockStatus */ +#define IMXDPUV1_COMCTRL_LOCKSTATUS ((uint32_t)(0x44)) +#define IMXDPUV1_COMCTRL_LOCKSTATUS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_COMCTRL_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_comctrl_UserInterruptMask0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0 ((uint32_t)(0x48)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptMask1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1 ((uint32_t)(0x4C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptEnable0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0 ((uint32_t)(0x50)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_INTERRUPTENABLE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_INTERRUPTENABLE0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptEnable1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1 ((uint32_t)(0x54)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_INTERRUPTENABLE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_INTERRUPTENABLE1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptPreset0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0 ((uint32_t)(0x58)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_INTERRUPTPRESET0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_INTERRUPTPRESET0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptPreset1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1 ((uint32_t)(0x5C)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_INTERRUPTPRESET1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_INTERRUPTPRESET1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptClear0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0 ((uint32_t)(0x60)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptClear1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1 ((uint32_t)(0x64)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptStatus0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0 ((uint32_t)(0x68)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_INTERRUPTSTATUS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_INTERRUPTSTATUS0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptStatus1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1 ((uint32_t)(0x6C)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_INTERRUPTSTATUS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_INTERRUPTSTATUS1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptEnable0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0 ((uint32_t)(0x80)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_USERINTERRUPTENABLE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_USERINTERRUPTENABLE0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptEnable1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1 ((uint32_t)(0x84)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_USERINTERRUPTENABLE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_USERINTERRUPTENABLE1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptPreset0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0 ((uint32_t)(0x88)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_USERINTERRUPTPRESET0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_USERINTERRUPTPRESET0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptPreset1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1 ((uint32_t)(0x8C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_USERINTERRUPTPRESET1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_USERINTERRUPTPRESET1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptClear0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0 ((uint32_t)(0x90)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptClear1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1 ((uint32_t)(0x94)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptStatus0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0 ((uint32_t)(0x98)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_USERINTERRUPTSTATUS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_USERINTERRUPTSTATUS0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptStatus1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1 ((uint32_t)(0xA8)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_USERINTERRUPTSTATUS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_USERINTERRUPTSTATUS1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_GeneralPurpose */ +#define IMXDPUV1_COMCTRL_GENERALPURPOSE ((uint32_t)(0x100)) +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_GENERALPURPOSE_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_GENERALPURPOSE_SHIFT 0U + +/* Register: IMXDPUV1_cmdseq_HIF */ +#define IMXDPUV1_CMDSEQ_HIF ((uint32_t)(0x400)) +#define IMXDPUV1_CMDSEQ_HIF_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CMDSEQ_HIF_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_HIF_RESET_MASK 0U +#define IMXDPUV1_CMDSEQ_HIF_COMMANDFIFO_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_HIF_COMMANDFIFO_SHIFT 0U + +/* Register: IMXDPUV1_cmdseq_LockUnlockHIF */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF ((uint32_t)(0x500)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_RESET_MASK 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF_SHIFT 0U +/* Field Value: LOCKUNLOCKHIF__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCKHIF__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCKHIF__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCKHIF__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCKHIF__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_cmdseq_LockStatusHIF */ +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF ((uint32_t)(0x504)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_LOCKSTATUSHIF_MASK 0x1U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_LOCKSTATUSHIF_SHIFT 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_PRIVILEGESTATUSHIF_MASK 0x10U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_PRIVILEGESTATUSHIF_SHIFT 4U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_FREEZESTATUSHIF_MASK 0x100U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_FREEZESTATUSHIF_SHIFT 8U + +/* Register: IMXDPUV1_cmdseq_LockUnlock */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK ((uint32_t)(0x580)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_cmdseq_LockStatus */ +#define IMXDPUV1_CMDSEQ_LOCKSTATUS ((uint32_t)(0x584)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_cmdseq_BufferAddress */ +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS ((uint32_t)(0x588)) +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_LOCAL_MASK 0x1U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_LOCAL_SHIFT 0U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_ADDR_MASK 0xFFFFFFE0U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_ADDR_SHIFT 5U + +/* Register: IMXDPUV1_cmdseq_BufferSize */ +#define IMXDPUV1_CMDSEQ_BUFFERSIZE ((uint32_t)(0x58C)) +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_RESET_VALUE 0x80U +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_RESET_MASK 0xFFF8U +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_SIZE_MASK 0xFFF8U +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_SIZE_SHIFT 3U + +/* Register: IMXDPUV1_cmdseq_WatermarkControl */ +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL ((uint32_t)(0x590)) +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_OFFSET ((uint32_t)(0x190)) +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_RESET_VALUE 0x600020U +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_LOWWM_MASK 0xFFFFU +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_LOWWM_SHIFT 0U +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_HIGHWM_MASK 0xFFFF0000U +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_HIGHWM_SHIFT 16U + +/* Register: IMXDPUV1_cmdseq_Control */ +#define IMXDPUV1_CMDSEQ_CONTROL ((uint32_t)(0x594)) +#define IMXDPUV1_CMDSEQ_CONTROL_OFFSET ((uint32_t)(0x194)) +#define IMXDPUV1_CMDSEQ_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_CONTROL_CLRAXIW_MASK 0x1U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRAXIW_SHIFT 0U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRRBUF_MASK 0x4U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRRBUF_SHIFT 2U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRCMDBUF_MASK 0x8U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRCMDBUF_SHIFT 3U +#define IMXDPUV1_CMDSEQ_CONTROL_CLEAR_MASK 0x80000000U +#define IMXDPUV1_CMDSEQ_CONTROL_CLEAR_SHIFT 31U + +/* Register: IMXDPUV1_cmdseq_Status */ +#define IMXDPUV1_CMDSEQ_STATUS ((uint32_t)(0x598)) +#define IMXDPUV1_CMDSEQ_STATUS_OFFSET ((uint32_t)(0x198)) +#define IMXDPUV1_CMDSEQ_STATUS_RESET_VALUE 0x41000080U +#define IMXDPUV1_CMDSEQ_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_STATUS_FIFOSPACE_MASK 0x1FFFFU +#define IMXDPUV1_CMDSEQ_STATUS_FIFOSPACE_SHIFT 0U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOEMPTY_MASK 0x1000000U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOEMPTY_SHIFT 24U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOFULL_MASK 0x2000000U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOFULL_SHIFT 25U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOWMSTATE_MASK 0x4000000U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOWMSTATE_SHIFT 26U +#define IMXDPUV1_CMDSEQ_STATUS_WATCHDOG_MASK 0x8000000U +#define IMXDPUV1_CMDSEQ_STATUS_WATCHDOG_SHIFT 27U +#define IMXDPUV1_CMDSEQ_STATUS_READBUSY_MASK 0x10000000U +#define IMXDPUV1_CMDSEQ_STATUS_READBUSY_SHIFT 28U +#define IMXDPUV1_CMDSEQ_STATUS_WRITEBUSY_MASK 0x20000000U +#define IMXDPUV1_CMDSEQ_STATUS_WRITEBUSY_SHIFT 29U +#define IMXDPUV1_CMDSEQ_STATUS_IDLE_MASK 0x40000000U +#define IMXDPUV1_CMDSEQ_STATUS_IDLE_SHIFT 30U +#define IMXDPUV1_CMDSEQ_STATUS_ERRORHALT_MASK 0x80000000U +#define IMXDPUV1_CMDSEQ_STATUS_ERRORHALT_SHIFT 31U + +/* Register: IMXDPUV1_cmdseq_PrefetchWindowStart */ +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART ((uint32_t)(0x59C)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_OFFSET ((uint32_t)(0x19C)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_PWSTART_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_PWSTART_SHIFT 2U + +/* Register: IMXDPUV1_cmdseq_PrefetchWindowEnd */ +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND ((uint32_t)(0x5A0)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_OFFSET ((uint32_t)(0x1A0)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_RESET_VALUE 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_PWEND_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_PWEND_SHIFT 2U + +/* Register: IMXDPUV1_pixengcfg_SafetyLockUnlock */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK ((uint32_t)(0x800)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK_SHIFT 0U +/* Field Value: SAFETYLOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: SAFETYLOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: SAFETYLOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: SAFETYLOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: SAFETYLOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_SafetyLockStatus */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS ((uint32_t)(0x804)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYLOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYLOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYPRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYPRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYFREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYFREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_store9_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK ((uint32_t)(0x808)) +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_STORE9_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_STORE9_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst0_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK ((uint32_t)(0x80C)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_EXTDST0_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_EXTDST0_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst4_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK ((uint32_t)(0x810)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_EXTDST4_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_EXTDST4_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst1_SafetyMask_0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0 ((uint32_t)(0x814)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_EXTDST1_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_EXTDST1_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst5_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK ((uint32_t)(0x818)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_EXTDST5_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_EXTDST5_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK ((uint32_t)(0x820)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHDECODE9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHDECODE9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHDECODE9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege + * protection. Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHDECODE9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHDECODE9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS ((uint32_t)(0x824)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC ((uint32_t)(0x828)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL_SHIFT 0U +/* Field Value: FETCHDECODE9_SRC_SEL__DISABLE, Unit fetchdecode9 input port + * src is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__DISABLE 0U +/* Field Value: FETCHDECODE9_SRC_SEL__FETCHECO9, Unit fetchdecode9 input port + * src is connected to output of unit fetcheco9 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__FETCHECO9 0x3U +/* Field Value: FETCHDECODE9_SRC_SEL__FETCHPERSP9, Unit fetchdecode9 input + * port src is connected to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__FETCHPERSP9 0x2U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS ((uint32_t)(0x82C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL_SHIFT 16U +/* Field Value: FETCHDECODE9_SEL__STORE9, fetchdecode9 module is used from + * store9 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE9 0x1U +/* Field Value: FETCHDECODE9_SEL__EXTDST0, fetchdecode9 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST0 0x2U +/* Field Value: FETCHDECODE9_SEL__EXTDST4, fetchdecode9 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST4 0x3U +/* Field Value: FETCHDECODE9_SEL__EXTDST1, fetchdecode9 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST1 0x4U +/* Field Value: FETCHDECODE9_SEL__EXTDST5, fetchdecode9 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST5 0x5U +/* Field Value: FETCHDECODE9_SEL__STORE4, fetchdecode9 module is used from + * store4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE4 0x6U +/* Field Value: FETCHDECODE9_SEL__STORE5, fetchdecode9 module is used from + * store5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE5 0x7U +/* Field Value: FETCHDECODE9_SEL__DISABLE, fetchdecode9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK ((uint32_t)(0x840)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHWARP9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHWARP9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHWARP9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHWARP9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHWARP9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS ((uint32_t)(0x844)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC ((uint32_t)(0x848)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL_SHIFT 0U +/* Field Value: FETCHWARP9_SRC_SEL__DISABLE, Unit fetchpersp9 input port src + * is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL__DISABLE 0U +/* Field Value: FETCHWARP9_SRC_SEL__FETCHECO9, Unit fetchpersp9 input port + * src is connected to output of unit fetcheco9 */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL__FETCHECO9 0x3U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS ((uint32_t)(0x84C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL_SHIFT 16U +/* Field Value: FETCHWARP9_SEL__STORE9, fetchpersp9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE9 0x1U +/* Field Value: FETCHWARP9_SEL__EXTDST0, fetchpersp9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST0 0x2U +/* Field Value: FETCHWARP9_SEL__EXTDST4, fetchpersp9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST4 0x3U +/* Field Value: FETCHWARP9_SEL__EXTDST1, fetchpersp9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST1 0x4U +/* Field Value: FETCHWARP9_SEL__EXTDST5, fetchpersp9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST5 0x5U +/* Field Value: FETCHWARP9_SEL__STORE4, fetchpersp9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE4 0x6U +/* Field Value: FETCHWARP9_SEL__STORE5, fetchpersp9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE5 0x7U +/* Field Value: FETCHWARP9_SEL__DISABLE, fetchpersp9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK ((uint32_t)(0x850)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS ((uint32_t)(0x854)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco9_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS ((uint32_t)(0x858)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL_SHIFT 16U +/* Field Value: FETCHECO9_SEL__STORE9, fetcheco9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE9 0x1U +/* Field Value: FETCHECO9_SEL__EXTDST0, fetcheco9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO9_SEL__EXTDST4, fetcheco9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO9_SEL__EXTDST1, fetcheco9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO9_SEL__EXTDST5, fetcheco9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO9_SEL__STORE4, fetcheco9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE4 0x6U +/* Field Value: FETCHECO9_SEL__STORE5, fetcheco9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE5 0x7U +/* Field Value: FETCHECO9_SEL__DISABLE, fetcheco9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_rop9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK ((uint32_t)(0x860)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK_SHIFT 0U +/* Field Value: ROP9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: ROP9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: ROP9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: ROP9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: ROP9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_rop9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS ((uint32_t)(0x864)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_rop9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC ((uint32_t)(0x868)) +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL_SHIFT 0U +/* Field Value: ROP9_PRIM_SEL__DISABLE, Unit rop9 input port prim is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__DISABLE 0U +/* Field Value: ROP9_PRIM_SEL__FETCHDECODE9, Unit rop9 input port prim is + * connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__FETCHDECODE9 0x1U +/* Field Value: ROP9_PRIM_SEL__FETCHPERSP9, Unit rop9 input port prim is connected + * to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__FETCHPERSP9 0x2U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL_SHIFT 8U +/* Field Value: ROP9_SEC_SEL__DISABLE, Unit rop9 input port sec is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL__DISABLE 0U +/* Field Value: ROP9_SEC_SEL__FETCHECO9, Unit rop9 input port sec is connected + * to output of unit fetcheco9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL__FETCHECO9 0x3U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL_MASK 0x3F0000U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL_SHIFT 16U +/* Field Value: ROP9_TERT_SEL__DISABLE, Unit rop9 input port tert is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__DISABLE 0U +/* Field Value: ROP9_TERT_SEL__FETCHDECODE9, Unit rop9 input port tert is + * connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__FETCHDECODE9 0x1U +/* Field Value: ROP9_TERT_SEL__FETCHPERSP9, Unit rop9 input port tert is connected + * to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__FETCHPERSP9 0x2U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN_SHIFT 24U +/* Field Value: ROP9_CLKEN__DISABLE, Clock for rop9 is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__DISABLE 0U +/* Field Value: ROP9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, frequency + * is defined by the register setting for this pipeline (see [endpoint_name]_Static + * register) */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__AUTOMATIC 0x1U +/* Field Value: ROP9_CLKEN__FULL, Clock for rop9 is without gating */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_rop9_Status */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS ((uint32_t)(0x86C)) +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL_SHIFT 16U +/* Field Value: ROP9_SEL__STORE9, rop9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE9 0x1U +/* Field Value: ROP9_SEL__EXTDST0, rop9 module is used from extdst0 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST0 0x2U +/* Field Value: ROP9_SEL__EXTDST4, rop9 module is used from extdst4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST4 0x3U +/* Field Value: ROP9_SEL__EXTDST1, rop9 module is used from extdst1 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST1 0x4U +/* Field Value: ROP9_SEL__EXTDST5, rop9 module is used from extdst5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST5 0x5U +/* Field Value: ROP9_SEL__STORE4, rop9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE4 0x6U +/* Field Value: ROP9_SEL__STORE5, rop9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE5 0x7U +/* Field Value: ROP9_SEL__DISABLE, rop9 module is not used */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_clut9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK ((uint32_t)(0x880)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK_SHIFT 0U +/* Field Value: CLUT9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CLUT9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CLUT9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CLUT9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CLUT9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_clut9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS ((uint32_t)(0x884)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_clut9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC ((uint32_t)(0x888)) +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL_SHIFT 0U +/* Field Value: CLUT9_SRC_SEL__DISABLE, Unit clut9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__DISABLE 0U +/* Field Value: CLUT9_SRC_SEL__BLITBLEND9, Unit clut9 input port src is connected + * to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: CLUT9_SRC_SEL__ROP9, Unit clut9 input port src is connected + * to output of unit rop9 */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__ROP9 0x4U + +/* Register: IMXDPUV1_pixengcfg_clut9_Status */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS ((uint32_t)(0x88C)) +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL_SHIFT 16U +/* Field Value: CLUT9_SEL__STORE9, clut9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE9 0x1U +/* Field Value: CLUT9_SEL__EXTDST0, clut9 module is used from extdst0 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST0 0x2U +/* Field Value: CLUT9_SEL__EXTDST4, clut9 module is used from extdst4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST4 0x3U +/* Field Value: CLUT9_SEL__EXTDST1, clut9 module is used from extdst1 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST1 0x4U +/* Field Value: CLUT9_SEL__EXTDST5, clut9 module is used from extdst5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST5 0x5U +/* Field Value: CLUT9_SEL__STORE4, clut9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE4 0x6U +/* Field Value: CLUT9_SEL__STORE5, clut9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE5 0x7U +/* Field Value: CLUT9_SEL__DISABLE, clut9 module is not used */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_matrix9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK ((uint32_t)(0x8A0)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK_SHIFT 0U +/* Field Value: MATRIX9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: MATRIX9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: MATRIX9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: MATRIX9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: MATRIX9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_matrix9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS ((uint32_t)(0x8A4)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_matrix9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC ((uint32_t)(0x8A8)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL_SHIFT 0U +/* Field Value: MATRIX9_SRC_SEL__DISABLE, Unit matrix9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__DISABLE 0U +/* Field Value: MATRIX9_SRC_SEL__CLUT9, Unit matrix9 input port src is connected + * to output of unit clut9 */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__CLUT9 0x5U +/* Field Value: MATRIX9_SRC_SEL__BLITBLEND9, Unit matrix9 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: MATRIX9_SRC_SEL__ROP9, Unit matrix9 input port src is connected + * to output of unit rop9 */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__ROP9 0x4U +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN_SHIFT 24U +/* Field Value: MATRIX9_CLKEN__DISABLE, Clock for matrix9 is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__DISABLE 0U +/* Field Value: MATRIX9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__AUTOMATIC 0x1U +/* Field Value: MATRIX9_CLKEN__FULL, Clock for matrix9 is without gating */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_matrix9_Status */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS ((uint32_t)(0x8AC)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL_SHIFT 16U +/* Field Value: MATRIX9_SEL__STORE9, matrix9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE9 0x1U +/* Field Value: MATRIX9_SEL__EXTDST0, matrix9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST0 0x2U +/* Field Value: MATRIX9_SEL__EXTDST4, matrix9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST4 0x3U +/* Field Value: MATRIX9_SEL__EXTDST1, matrix9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST1 0x4U +/* Field Value: MATRIX9_SEL__EXTDST5, matrix9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST5 0x5U +/* Field Value: MATRIX9_SEL__STORE4, matrix9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE4 0x6U +/* Field Value: MATRIX9_SEL__STORE5, matrix9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE5 0x7U +/* Field Value: MATRIX9_SEL__DISABLE, matrix9 module is not used */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK ((uint32_t)(0x8C0)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK_SHIFT 0U +/* Field Value: HSCALER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: HSCALER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: HSCALER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: HSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: HSCALER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS ((uint32_t)(0x8C4)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC ((uint32_t)(0x8C8)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL_SHIFT 0U +/* Field Value: HSCALER9_SRC_SEL__DISABLE, Unit hscaler9 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__DISABLE 0U +/* Field Value: HSCALER9_SRC_SEL__VSCALER9, Unit hscaler9 input port src is + * connected to output of unit vscaler9 */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__VSCALER9 0x8U +/* Field Value: HSCALER9_SRC_SEL__FILTER9, Unit hscaler9 input port src is + * connected to output of unit filter9 */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__FILTER9 0x9U +/* Field Value: HSCALER9_SRC_SEL__MATRIX9, Unit hscaler9 input port src is + * connected to output of unit matrix9 */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__MATRIX9 0x6U +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN_SHIFT 24U +/* Field Value: HSCALER9_CLKEN__DISABLE, Clock for hscaler9 is disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__DISABLE 0U +/* Field Value: HSCALER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__AUTOMATIC 0x1U +/* Field Value: HSCALER9_CLKEN__FULL, Clock for hscaler9 is without gating */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_Status */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS ((uint32_t)(0x8CC)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL_SHIFT 16U +/* Field Value: HSCALER9_SEL__STORE9, hscaler9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE9 0x1U +/* Field Value: HSCALER9_SEL__EXTDST0, hscaler9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST0 0x2U +/* Field Value: HSCALER9_SEL__EXTDST4, hscaler9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST4 0x3U +/* Field Value: HSCALER9_SEL__EXTDST1, hscaler9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST1 0x4U +/* Field Value: HSCALER9_SEL__EXTDST5, hscaler9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST5 0x5U +/* Field Value: HSCALER9_SEL__STORE4, hscaler9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE4 0x6U +/* Field Value: HSCALER9_SEL__STORE5, hscaler9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE5 0x7U +/* Field Value: HSCALER9_SEL__DISABLE, hscaler9 module is not used */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK ((uint32_t)(0x8E0)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK_SHIFT 0U +/* Field Value: VSCALER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: VSCALER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: VSCALER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: VSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: VSCALER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS ((uint32_t)(0x8E4)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC ((uint32_t)(0x8E8)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL_SHIFT 0U +/* Field Value: VSCALER9_SRC_SEL__DISABLE, Unit vscaler9 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__DISABLE 0U +/* Field Value: VSCALER9_SRC_SEL__HSCALER9, Unit vscaler9 input port src is + * connected to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__HSCALER9 0x7U +/* Field Value: VSCALER9_SRC_SEL__MATRIX9, Unit vscaler9 input port src is + * connected to output of unit matrix9 */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__MATRIX9 0x6U +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN_SHIFT 24U +/* Field Value: VSCALER9_CLKEN__DISABLE, Clock for vscaler9 is disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__DISABLE 0U +/* Field Value: VSCALER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__AUTOMATIC 0x1U +/* Field Value: VSCALER9_CLKEN__FULL, Clock for vscaler9 is without gating */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_Status */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS ((uint32_t)(0x8EC)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL_SHIFT 16U +/* Field Value: VSCALER9_SEL__STORE9, vscaler9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE9 0x1U +/* Field Value: VSCALER9_SEL__EXTDST0, vscaler9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST0 0x2U +/* Field Value: VSCALER9_SEL__EXTDST4, vscaler9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST4 0x3U +/* Field Value: VSCALER9_SEL__EXTDST1, vscaler9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST1 0x4U +/* Field Value: VSCALER9_SEL__EXTDST5, vscaler9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST5 0x5U +/* Field Value: VSCALER9_SEL__STORE4, vscaler9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE4 0x6U +/* Field Value: VSCALER9_SEL__STORE5, vscaler9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE5 0x7U +/* Field Value: VSCALER9_SEL__DISABLE, vscaler9 module is not used */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_filter9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK ((uint32_t)(0x900)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FILTER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FILTER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FILTER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FILTER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FILTER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_filter9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS ((uint32_t)(0x904)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_filter9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC ((uint32_t)(0x908)) +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL_SHIFT 0U +/* Field Value: FILTER9_SRC_SEL__DISABLE, Unit filter9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__DISABLE 0U +/* Field Value: FILTER9_SRC_SEL__HSCALER9, Unit filter9 input port src is + * connected to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__HSCALER9 0x7U +/* Field Value: FILTER9_SRC_SEL__MATRIX9, Unit filter9 input port src is connected + * to output of unit matrix9 */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__MATRIX9 0x6U +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN_SHIFT 24U +/* Field Value: FILTER9_CLKEN__DISABLE, Clock for filter9 is disabled */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__DISABLE 0U +/* Field Value: FILTER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__AUTOMATIC 0x1U +/* Field Value: FILTER9_CLKEN__FULL, Clock for filter9 is without gating */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_filter9_Status */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS ((uint32_t)(0x90C)) +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL_SHIFT 16U +/* Field Value: FILTER9_SEL__STORE9, filter9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE9 0x1U +/* Field Value: FILTER9_SEL__EXTDST0, filter9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST0 0x2U +/* Field Value: FILTER9_SEL__EXTDST4, filter9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST4 0x3U +/* Field Value: FILTER9_SEL__EXTDST1, filter9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST1 0x4U +/* Field Value: FILTER9_SEL__EXTDST5, filter9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST5 0x5U +/* Field Value: FILTER9_SEL__STORE4, filter9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE4 0x6U +/* Field Value: FILTER9_SEL__STORE5, filter9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE5 0x7U +/* Field Value: FILTER9_SEL__DISABLE, filter9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK ((uint32_t)(0x920)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK_SHIFT 0U +/* Field Value: BLITBLEND9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: BLITBLEND9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: BLITBLEND9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: BLITBLEND9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: BLITBLEND9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS ((uint32_t)(0x924)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC ((uint32_t)(0x928)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL_SHIFT 0U +/* Field Value: BLITBLEND9_PRIM_SEL__DISABLE, Unit blitblend9 input port prim + * is disabled */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__DISABLE 0U +/* Field Value: BLITBLEND9_PRIM_SEL__HSCALER9, Unit blitblend9 input port + * prim is connected to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__HSCALER9 0x7U +/* Field Value: BLITBLEND9_PRIM_SEL__VSCALER9, Unit blitblend9 input port + * prim is connected to output of unit vscaler9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__VSCALER9 0x8U +/* Field Value: BLITBLEND9_PRIM_SEL__FILTER9, Unit blitblend9 input port prim + * is connected to output of unit filter9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__FILTER9 0x9U +/* Field Value: BLITBLEND9_PRIM_SEL__ROP9, Unit blitblend9 input port prim + * is connected to output of unit rop9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__ROP9 0x4U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL_SHIFT 8U +/* Field Value: BLITBLEND9_SEC_SEL__DISABLE, Unit blitblend9 input port sec + * is disabled */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__DISABLE 0U +/* Field Value: BLITBLEND9_SEC_SEL__FETCHDECODE9, Unit blitblend9 input port + * sec is connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__FETCHDECODE9 0x1U +/* Field Value: BLITBLEND9_SEC_SEL__FETCHPERSP9, Unit blitblend9 input port + * sec is connected to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__FETCHPERSP9 0x2U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN_SHIFT 24U +/* Field Value: BLITBLEND9_CLKEN__DISABLE, Clock for blitblend9 is disabled */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__DISABLE 0U +/* Field Value: BLITBLEND9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__AUTOMATIC 0x1U +/* Field Value: BLITBLEND9_CLKEN__FULL, Clock for blitblend9 is without gating */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_Status */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS ((uint32_t)(0x92C)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL_SHIFT 16U +/* Field Value: BLITBLEND9_SEL__STORE9, blitblend9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE9 0x1U +/* Field Value: BLITBLEND9_SEL__EXTDST0, blitblend9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST0 0x2U +/* Field Value: BLITBLEND9_SEL__EXTDST4, blitblend9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST4 0x3U +/* Field Value: BLITBLEND9_SEL__EXTDST1, blitblend9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST1 0x4U +/* Field Value: BLITBLEND9_SEL__EXTDST5, blitblend9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST5 0x5U +/* Field Value: BLITBLEND9_SEL__STORE4, blitblend9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE4 0x6U +/* Field Value: BLITBLEND9_SEL__STORE5, blitblend9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE5 0x7U +/* Field Value: BLITBLEND9_SEL__DISABLE, blitblend9 module is not used */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_store9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK ((uint32_t)(0x940)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK_SHIFT 0U +/* Field Value: STORE9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: STORE9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: STORE9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: STORE9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: STORE9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_store9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS ((uint32_t)(0x944)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_store9_Static */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC ((uint32_t)(0x948)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_SHIFT 8U +/* Field Value: STORE9_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__SINGLE 0U +/* Field Value: STORE9_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_SHIFT 11U +/* Field Value: STORE9_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__OPERATION 0U +/* Field Value: STORE9_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_store9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC ((uint32_t)(0x94C)) +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_RESET_VALUE 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL_SHIFT 0U +/* Field Value: STORE9_SRC_SEL__DISABLE, Unit store9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__DISABLE 0U +/* Field Value: STORE9_SRC_SEL__HSCALER9, Unit store9 input port src is connected + * to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__HSCALER9 0x7U +/* Field Value: STORE9_SRC_SEL__VSCALER9, Unit store9 input port src is connected + * to output of unit vscaler9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__VSCALER9 0x8U +/* Field Value: STORE9_SRC_SEL__FILTER9, Unit store9 input port src is connected + * to output of unit filter9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FILTER9 0x9U +/* Field Value: STORE9_SRC_SEL__BLITBLEND9, Unit store9 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: STORE9_SRC_SEL__FETCHDECODE9, Unit store9 input port src is + * connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FETCHDECODE9 0x1U +/* Field Value: STORE9_SRC_SEL__FETCHPERSP9, Unit store9 input port src is + * connected to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FETCHPERSP9 0x2U + +/* Register: IMXDPUV1_pixengcfg_store9_Request */ +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST ((uint32_t)(0x950)) +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_store9_Trigger */ +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER ((uint32_t)(0x954)) +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_store9_Status */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS ((uint32_t)(0x958)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS_SHIFT 0U +/* Field Value: STORE9_PIPELINE_STATUS__EMPTY, Pipeline with endpoint store9 + * is empty */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__EMPTY 0U +/* Field Value: STORE9_PIPELINE_STATUS__RUNNING, Pipeline with endpoint store9 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: STORE9_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint store9 is currently processing one operation with a second one + * already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: STORE9_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY_SHIFT 8U +/* Field Value: STORE9_SYNC_BUSY__IDLE, store9 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY__IDLE 0U +/* Field Value: STORE9_SYNC_BUSY__BUSY, store9 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK ((uint32_t)(0x960)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS ((uint32_t)(0x964)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe0_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS ((uint32_t)(0x968)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL_SHIFT 16U +/* Field Value: CONSTFRAME0_SEL__STORE9, constframe0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME0_SEL__EXTDST0, constframe0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME0_SEL__EXTDST4, constframe0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME0_SEL__EXTDST1, constframe0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME0_SEL__EXTDST5, constframe0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME0_SEL__STORE4, constframe0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME0_SEL__STORE5, constframe0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME0_SEL__DISABLE, constframe0 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK ((uint32_t)(0x980)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS ((uint32_t)(0x984)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC ((uint32_t)(0x988)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST0_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST0_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET_SHIFT 11U +/* Field Value: EXTDST0_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__OPERATION 0U +/* Field Value: EXTDST0_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC ((uint32_t)(0x98C)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_RESET_VALUE 0x2CU +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST0_SRC_SEL__DISABLE, Unit extdst0 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST0_SRC_SEL__BLITBLEND9, Unit extdst0 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME0, Unit extdst0 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME1, Unit extdst0 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME4, Unit extdst0 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME5, Unit extdst0 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST0_SRC_SEL__MATRIX4, Unit extdst0 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST0_SRC_SEL__HSCALER4, Unit extdst0 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST0_SRC_SEL__VSCALER4, Unit extdst0 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST0_SRC_SEL__EXTSRC4, Unit extdst0 input port src is connected + * to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC4 0x14U +/* Field Value: EXTDST0_SRC_SEL__MATRIX5, Unit extdst0 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST0_SRC_SEL__HSCALER5, Unit extdst0 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST0_SRC_SEL__VSCALER5, Unit extdst0 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST0_SRC_SEL__EXTSRC5, Unit extdst0 input port src is connected + * to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC5 0x16U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND6, Unit extdst0 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND5, Unit extdst0 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND4, Unit extdst0 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND3, Unit extdst0 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND2, Unit extdst0 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND1, Unit extdst0 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND0, Unit extdst0 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst0_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST ((uint32_t)(0x990)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_OFFSET ((uint32_t)(0x190)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER ((uint32_t)(0x994)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_OFFSET ((uint32_t)(0x194)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS ((uint32_t)(0x998)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_OFFSET ((uint32_t)(0x198)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST0_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst0 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST0_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst0 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST0_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst0 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST0_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST0_SYNC_BUSY__IDLE, extdst0 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST0_SYNC_BUSY__BUSY, extdst0 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK ((uint32_t)(0x9A0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_OFFSET ((uint32_t)(0x1A0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS ((uint32_t)(0x9A4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_OFFSET ((uint32_t)(0x1A4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe4_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS ((uint32_t)(0x9A8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_OFFSET ((uint32_t)(0x1A8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL_SHIFT 16U +/* Field Value: CONSTFRAME4_SEL__STORE9, constframe4 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME4_SEL__EXTDST0, constframe4 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME4_SEL__EXTDST4, constframe4 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME4_SEL__EXTDST1, constframe4 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME4_SEL__EXTDST5, constframe4 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME4_SEL__STORE4, constframe4 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME4_SEL__STORE5, constframe4 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME4_SEL__DISABLE, constframe4 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK ((uint32_t)(0x9C0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_OFFSET ((uint32_t)(0x1C0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS ((uint32_t)(0x9C4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_OFFSET ((uint32_t)(0x1C4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC ((uint32_t)(0x9C8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_OFFSET ((uint32_t)(0x1C8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST4_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST4_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET_SHIFT 11U +/* Field Value: EXTDST4_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET__OPERATION 0U +/* Field Value: EXTDST4_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC ((uint32_t)(0x9CC)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_OFFSET ((uint32_t)(0x1CC)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_RESET_VALUE 0x30U +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST4_SRC_SEL__DISABLE, Unit extdst4 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST4_SRC_SEL__BLITBLEND9, Unit extdst4 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME0, Unit extdst4 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME1, Unit extdst4 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME4, Unit extdst4 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME5, Unit extdst4 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST4_SRC_SEL__MATRIX4, Unit extdst4 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST4_SRC_SEL__HSCALER4, Unit extdst4 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST4_SRC_SEL__VSCALER4, Unit extdst4 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST4_SRC_SEL__MATRIX5, Unit extdst4 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST4_SRC_SEL__HSCALER5, Unit extdst4 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST4_SRC_SEL__VSCALER5, Unit extdst4 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND6, Unit extdst4 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND5, Unit extdst4 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND4, Unit extdst4 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND3, Unit extdst4 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND2, Unit extdst4 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND1, Unit extdst4 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND0, Unit extdst4 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst4_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST ((uint32_t)(0x9D0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_OFFSET ((uint32_t)(0x1D0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER ((uint32_t)(0x9D4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_OFFSET ((uint32_t)(0x1D4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS ((uint32_t)(0x9D8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_OFFSET ((uint32_t)(0x1D8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST4_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst4 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST4_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst4 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST4_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst4 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST4_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST4_SYNC_BUSY__IDLE, extdst4 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST4_SYNC_BUSY__BUSY, extdst4 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK ((uint32_t)(0x9E0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_OFFSET ((uint32_t)(0x1E0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS ((uint32_t)(0x9E4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_OFFSET ((uint32_t)(0x1E4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe1_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS ((uint32_t)(0x9E8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_OFFSET ((uint32_t)(0x1E8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL_SHIFT 16U +/* Field Value: CONSTFRAME1_SEL__STORE9, constframe1 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME1_SEL__EXTDST0, constframe1 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME1_SEL__EXTDST4, constframe1 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME1_SEL__EXTDST1, constframe1 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME1_SEL__EXTDST5, constframe1 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME1_SEL__STORE4, constframe1 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME1_SEL__STORE5, constframe1 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME1_SEL__DISABLE, constframe1 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK ((uint32_t)(0xA00)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_OFFSET ((uint32_t)(0x200)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS ((uint32_t)(0xA04)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_OFFSET ((uint32_t)(0x204)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC ((uint32_t)(0xA08)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_OFFSET ((uint32_t)(0x208)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST1_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST1_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET_SHIFT 11U +/* Field Value: EXTDST1_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__OPERATION 0U +/* Field Value: EXTDST1_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC ((uint32_t)(0xA0C)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_OFFSET ((uint32_t)(0x20C)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_RESET_VALUE 0x2DU +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST1_SRC_SEL__DISABLE, Unit extdst1 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST1_SRC_SEL__BLITBLEND9, Unit extdst1 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME0, Unit extdst1 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME1, Unit extdst1 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME4, Unit extdst1 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME5, Unit extdst1 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST1_SRC_SEL__MATRIX4, Unit extdst1 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST1_SRC_SEL__HSCALER4, Unit extdst1 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST1_SRC_SEL__VSCALER4, Unit extdst1 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST1_SRC_SEL__EXTSRC4, Unit extdst1 input port src is connected + * to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC4 0x14U +/* Field Value: EXTDST1_SRC_SEL__MATRIX5, Unit extdst1 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST1_SRC_SEL__HSCALER5, Unit extdst1 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST1_SRC_SEL__VSCALER5, Unit extdst1 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST1_SRC_SEL__EXTSRC5, Unit extdst1 input port src is connected + * to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC5 0x16U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND6, Unit extdst1 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND5, Unit extdst1 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND4, Unit extdst1 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND3, Unit extdst1 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND2, Unit extdst1 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND1, Unit extdst1 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND0, Unit extdst1 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst1_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST ((uint32_t)(0xA10)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_OFFSET ((uint32_t)(0x210)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER ((uint32_t)(0xA14)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_OFFSET ((uint32_t)(0x214)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS ((uint32_t)(0xA18)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_OFFSET ((uint32_t)(0x218)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST1_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst1 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST1_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst1 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST1_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst1 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST1_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST1_SYNC_BUSY__IDLE, extdst1 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST1_SYNC_BUSY__BUSY, extdst1 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK ((uint32_t)(0xA20)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_OFFSET ((uint32_t)(0x220)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS ((uint32_t)(0xA24)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_OFFSET ((uint32_t)(0x224)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe5_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS ((uint32_t)(0xA28)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_OFFSET ((uint32_t)(0x228)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL_SHIFT 16U +/* Field Value: CONSTFRAME5_SEL__STORE9, constframe5 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME5_SEL__EXTDST0, constframe5 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME5_SEL__EXTDST4, constframe5 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME5_SEL__EXTDST1, constframe5 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME5_SEL__EXTDST5, constframe5 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME5_SEL__STORE4, constframe5 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME5_SEL__STORE5, constframe5 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME5_SEL__DISABLE, constframe5 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK ((uint32_t)(0xA40)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_OFFSET ((uint32_t)(0x240)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS ((uint32_t)(0xA44)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_OFFSET ((uint32_t)(0x244)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC ((uint32_t)(0xA48)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_OFFSET ((uint32_t)(0x248)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST5_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST5_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET_SHIFT 11U +/* Field Value: EXTDST5_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET__OPERATION 0U +/* Field Value: EXTDST5_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC ((uint32_t)(0xA4C)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_OFFSET ((uint32_t)(0x24C)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_RESET_VALUE 0x31U +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST5_SRC_SEL__DISABLE, Unit extdst5 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST5_SRC_SEL__BLITBLEND9, Unit extdst5 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME0, Unit extdst5 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME1, Unit extdst5 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME4, Unit extdst5 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME5, Unit extdst5 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST5_SRC_SEL__MATRIX4, Unit extdst5 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST5_SRC_SEL__HSCALER4, Unit extdst5 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST5_SRC_SEL__VSCALER4, Unit extdst5 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST5_SRC_SEL__MATRIX5, Unit extdst5 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST5_SRC_SEL__HSCALER5, Unit extdst5 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST5_SRC_SEL__VSCALER5, Unit extdst5 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND6, Unit extdst5 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND5, Unit extdst5 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND4, Unit extdst5 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND3, Unit extdst5 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND2, Unit extdst5 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND1, Unit extdst5 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND0, Unit extdst5 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst5_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST ((uint32_t)(0xA50)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_OFFSET ((uint32_t)(0x250)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER ((uint32_t)(0xA54)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_OFFSET ((uint32_t)(0x254)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS ((uint32_t)(0xA58)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_OFFSET ((uint32_t)(0x258)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST5_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst5 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST5_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst5 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST5_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst5 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST5_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST5_SYNC_BUSY__IDLE, extdst5 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST5_SYNC_BUSY__BUSY, extdst5 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK ((uint32_t)(0xA60)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_OFFSET ((uint32_t)(0x260)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHWARP2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHWARP2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHWARP2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHWARP2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHWARP2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS ((uint32_t)(0xA64)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_OFFSET ((uint32_t)(0x264)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC ((uint32_t)(0xA68)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_OFFSET ((uint32_t)(0x268)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL_SHIFT 0U +/* Field Value: FETCHWARP2_SRC_SEL__DISABLE, Unit fetchwarp2 input port src + * is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL__DISABLE 0U +/* Field Value: FETCHWARP2_SRC_SEL__FETCHECO2, Unit fetchwarp2 input port + * src is connected to output of unit fetcheco2 */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL__FETCHECO2 0x1BU + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS ((uint32_t)(0xA6C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_OFFSET ((uint32_t)(0x26C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL_SHIFT 16U +/* Field Value: FETCHWARP2_SEL__STORE9, fetchwarp2 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE9 0x1U +/* Field Value: FETCHWARP2_SEL__EXTDST0, fetchwarp2 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST0 0x2U +/* Field Value: FETCHWARP2_SEL__EXTDST4, fetchwarp2 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST4 0x3U +/* Field Value: FETCHWARP2_SEL__EXTDST1, fetchwarp2 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST1 0x4U +/* Field Value: FETCHWARP2_SEL__EXTDST5, fetchwarp2 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST5 0x5U +/* Field Value: FETCHWARP2_SEL__STORE4, fetchwarp2 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE4 0x6U +/* Field Value: FETCHWARP2_SEL__STORE5, fetchwarp2 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE5 0x7U +/* Field Value: FETCHWARP2_SEL__DISABLE, fetchwarp2 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco2_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK ((uint32_t)(0xA70)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_OFFSET ((uint32_t)(0x270)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco2_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS ((uint32_t)(0xA74)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_OFFSET ((uint32_t)(0x274)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco2_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS ((uint32_t)(0xA78)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_OFFSET ((uint32_t)(0x278)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL_SHIFT 16U +/* Field Value: FETCHECO2_SEL__STORE9, fetcheco2 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE9 0x1U +/* Field Value: FETCHECO2_SEL__EXTDST0, fetcheco2 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO2_SEL__EXTDST4, fetcheco2 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO2_SEL__EXTDST1, fetcheco2 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO2_SEL__EXTDST5, fetcheco2 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO2_SEL__STORE4, fetcheco2 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE4 0x6U +/* Field Value: FETCHECO2_SEL__STORE5, fetcheco2 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE5 0x7U +/* Field Value: FETCHECO2_SEL__DISABLE, fetcheco2 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK ((uint32_t)(0xA80)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_OFFSET ((uint32_t)(0x280)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHDECODE0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHDECODE0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHDECODE0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege + * protection. Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHDECODE0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHDECODE0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS ((uint32_t)(0xA84)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_OFFSET ((uint32_t)(0x284)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC ((uint32_t)(0xA88)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_OFFSET ((uint32_t)(0x288)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL_SHIFT 0U +/* Field Value: FETCHDECODE0_SRC_SEL__DISABLE, Unit fetchdecode0 input port + * src is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__DISABLE 0U +/* Field Value: FETCHDECODE0_SRC_SEL__FETCHECO0, Unit fetchdecode0 input port + * src is connected to output of unit fetcheco0 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHECO0 0x1DU +/* Field Value: FETCHDECODE0_SRC_SEL__FETCHDECODE2, Unit fetchdecode0 input + * port src is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHDECODE2 0x18U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS ((uint32_t)(0xA8C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_OFFSET ((uint32_t)(0x28C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL_SHIFT 16U +/* Field Value: FETCHDECODE0_SEL__STORE9, fetchdecode0 module is used from + * store9 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE9 0x1U +/* Field Value: FETCHDECODE0_SEL__EXTDST0, fetchdecode0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST0 0x2U +/* Field Value: FETCHDECODE0_SEL__EXTDST4, fetchdecode0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST4 0x3U +/* Field Value: FETCHDECODE0_SEL__EXTDST1, fetchdecode0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST1 0x4U +/* Field Value: FETCHDECODE0_SEL__EXTDST5, fetchdecode0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST5 0x5U +/* Field Value: FETCHDECODE0_SEL__STORE4, fetchdecode0 module is used from + * store4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE4 0x6U +/* Field Value: FETCHDECODE0_SEL__STORE5, fetchdecode0 module is used from + * store5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE5 0x7U +/* Field Value: FETCHDECODE0_SEL__DISABLE, fetchdecode0 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK ((uint32_t)(0xA90)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_OFFSET ((uint32_t)(0x290)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS ((uint32_t)(0xA94)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_OFFSET ((uint32_t)(0x294)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco0_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS ((uint32_t)(0xA98)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_OFFSET ((uint32_t)(0x298)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL_SHIFT 16U +/* Field Value: FETCHECO0_SEL__STORE9, fetcheco0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE9 0x1U +/* Field Value: FETCHECO0_SEL__EXTDST0, fetcheco0 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO0_SEL__EXTDST4, fetcheco0 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO0_SEL__EXTDST1, fetcheco0 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO0_SEL__EXTDST5, fetcheco0 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO0_SEL__STORE4, fetcheco0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE4 0x6U +/* Field Value: FETCHECO0_SEL__STORE5, fetcheco0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE5 0x7U +/* Field Value: FETCHECO0_SEL__DISABLE, fetcheco0 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK ((uint32_t)(0xAA0)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_OFFSET ((uint32_t)(0x2A0)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHDECODE1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHDECODE1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHDECODE1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege + * protection. Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHDECODE1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHDECODE1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS ((uint32_t)(0xAA4)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_OFFSET ((uint32_t)(0x2A4)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC ((uint32_t)(0xAA8)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_OFFSET ((uint32_t)(0x2A8)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL_SHIFT 0U +/* Field Value: FETCHDECODE1_SRC_SEL__DISABLE, Unit fetchdecode1 input port + * src is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__DISABLE 0U +/* Field Value: FETCHDECODE1_SRC_SEL__FETCHECO1, Unit fetchdecode1 input port + * src is connected to output of unit fetcheco1 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHECO1 0x1FU +/* Field Value: FETCHDECODE1_SRC_SEL__FETCHDECODE3, Unit fetchdecode1 input + * port src is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHDECODE3 0x19U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS ((uint32_t)(0xAAC)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_OFFSET ((uint32_t)(0x2AC)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL_SHIFT 16U +/* Field Value: FETCHDECODE1_SEL__STORE9, fetchdecode1 module is used from + * store9 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE9 0x1U +/* Field Value: FETCHDECODE1_SEL__EXTDST0, fetchdecode1 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST0 0x2U +/* Field Value: FETCHDECODE1_SEL__EXTDST4, fetchdecode1 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST4 0x3U +/* Field Value: FETCHDECODE1_SEL__EXTDST1, fetchdecode1 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST1 0x4U +/* Field Value: FETCHDECODE1_SEL__EXTDST5, fetchdecode1 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST5 0x5U +/* Field Value: FETCHDECODE1_SEL__STORE4, fetchdecode1 module is used from + * store4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE4 0x6U +/* Field Value: FETCHDECODE1_SEL__STORE5, fetchdecode1 module is used from + * store5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE5 0x7U +/* Field Value: FETCHDECODE1_SEL__DISABLE, fetchdecode1 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK ((uint32_t)(0xAB0)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_OFFSET ((uint32_t)(0x2B0)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS ((uint32_t)(0xAB4)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_OFFSET ((uint32_t)(0x2B4)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco1_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS ((uint32_t)(0xAB8)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_OFFSET ((uint32_t)(0x2B8)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL_SHIFT 16U +/* Field Value: FETCHECO1_SEL__STORE9, fetcheco1 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE9 0x1U +/* Field Value: FETCHECO1_SEL__EXTDST0, fetcheco1 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO1_SEL__EXTDST4, fetcheco1 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO1_SEL__EXTDST1, fetcheco1 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO1_SEL__EXTDST5, fetcheco1 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO1_SEL__STORE4, fetcheco1 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE4 0x6U +/* Field Value: FETCHECO1_SEL__STORE5, fetcheco1 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE5 0x7U +/* Field Value: FETCHECO1_SEL__DISABLE, fetcheco1 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchlayer0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK ((uint32_t)(0xAC0)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_OFFSET ((uint32_t)(0x2C0)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHLAYER0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHLAYER0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHLAYER0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHLAYER0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHLAYER0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchlayer0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS ((uint32_t)(0xAC4)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_OFFSET ((uint32_t)(0x2C4)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchlayer0_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS ((uint32_t)(0xAC8)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_OFFSET ((uint32_t)(0x2C8)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL_SHIFT 16U +/* Field Value: FETCHLAYER0_SEL__STORE9, fetchlayer0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE9 0x1U +/* Field Value: FETCHLAYER0_SEL__EXTDST0, fetchlayer0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST0 0x2U +/* Field Value: FETCHLAYER0_SEL__EXTDST4, fetchlayer0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST4 0x3U +/* Field Value: FETCHLAYER0_SEL__EXTDST1, fetchlayer0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST1 0x4U +/* Field Value: FETCHLAYER0_SEL__EXTDST5, fetchlayer0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST5 0x5U +/* Field Value: FETCHLAYER0_SEL__STORE4, fetchlayer0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE4 0x6U +/* Field Value: FETCHLAYER0_SEL__STORE5, fetchlayer0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE5 0x7U +/* Field Value: FETCHLAYER0_SEL__DISABLE, fetchlayer0 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_matrix4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK ((uint32_t)(0xAE0)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_OFFSET ((uint32_t)(0x2E0)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK_SHIFT 0U +/* Field Value: MATRIX4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: MATRIX4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: MATRIX4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: MATRIX4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: MATRIX4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_matrix4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS ((uint32_t)(0xAE4)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_OFFSET ((uint32_t)(0x2E4)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_matrix4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC ((uint32_t)(0xAE8)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_OFFSET ((uint32_t)(0x2E8)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL_SHIFT 0U +/* Field Value: MATRIX4_SRC_SEL__DISABLE, Unit matrix4 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL__DISABLE 0U +/* Field Value: MATRIX4_SRC_SEL__GAMMACOR4, Unit matrix4 input port src is + * connected to output of unit gammacor4 */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL__GAMMACOR4 0x22U +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN_SHIFT 24U +/* Field Value: MATRIX4_CLKEN__DISABLE, Clock for matrix4 is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__DISABLE 0U +/* Field Value: MATRIX4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__AUTOMATIC 0x1U +/* Field Value: MATRIX4_CLKEN__FULL, Clock for matrix4 is without gating */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_matrix4_Status */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS ((uint32_t)(0xAEC)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_OFFSET ((uint32_t)(0x2EC)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL_SHIFT 16U +/* Field Value: MATRIX4_SEL__STORE9, matrix4 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE9 0x1U +/* Field Value: MATRIX4_SEL__EXTDST0, matrix4 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST0 0x2U +/* Field Value: MATRIX4_SEL__EXTDST4, matrix4 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST4 0x3U +/* Field Value: MATRIX4_SEL__EXTDST1, matrix4 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST1 0x4U +/* Field Value: MATRIX4_SEL__EXTDST5, matrix4 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST5 0x5U +/* Field Value: MATRIX4_SEL__STORE4, matrix4 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE4 0x6U +/* Field Value: MATRIX4_SEL__STORE5, matrix4 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE5 0x7U +/* Field Value: MATRIX4_SEL__DISABLE, matrix4 module is not used */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK ((uint32_t)(0xB00)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0x300)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK_SHIFT 0U +/* Field Value: HSCALER4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: HSCALER4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: HSCALER4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: HSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: HSCALER4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS ((uint32_t)(0xB04)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x304)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC ((uint32_t)(0xB08)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_OFFSET ((uint32_t)(0x308)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL_SHIFT 0U +/* Field Value: HSCALER4_SRC_SEL__DISABLE, Unit hscaler4 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__DISABLE 0U +/* Field Value: HSCALER4_SRC_SEL__EXTSRC4, Unit hscaler4 input port src is + * connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__EXTSRC4 0x14U +/* Field Value: HSCALER4_SRC_SEL__FETCHDECODE0, Unit hscaler4 input port src + * is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__FETCHDECODE0 0x1CU +/* Field Value: HSCALER4_SRC_SEL__FETCHDECODE2, Unit hscaler4 input port src + * is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__FETCHDECODE2 0x18U +/* Field Value: HSCALER4_SRC_SEL__MATRIX4, Unit hscaler4 input port src is + * connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__MATRIX4 0x23U +/* Field Value: HSCALER4_SRC_SEL__VSCALER4, Unit hscaler4 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__VSCALER4 0x25U +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN_SHIFT 24U +/* Field Value: HSCALER4_CLKEN__DISABLE, Clock for hscaler4 is disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__DISABLE 0U +/* Field Value: HSCALER4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__AUTOMATIC 0x1U +/* Field Value: HSCALER4_CLKEN__FULL, Clock for hscaler4 is without gating */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_Status */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS ((uint32_t)(0xB0C)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_OFFSET ((uint32_t)(0x30C)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL_SHIFT 16U +/* Field Value: HSCALER4_SEL__STORE9, hscaler4 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE9 0x1U +/* Field Value: HSCALER4_SEL__EXTDST0, hscaler4 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST0 0x2U +/* Field Value: HSCALER4_SEL__EXTDST4, hscaler4 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST4 0x3U +/* Field Value: HSCALER4_SEL__EXTDST1, hscaler4 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST1 0x4U +/* Field Value: HSCALER4_SEL__EXTDST5, hscaler4 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST5 0x5U +/* Field Value: HSCALER4_SEL__STORE4, hscaler4 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE4 0x6U +/* Field Value: HSCALER4_SEL__STORE5, hscaler4 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE5 0x7U +/* Field Value: HSCALER4_SEL__DISABLE, hscaler4 module is not used */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK ((uint32_t)(0xB20)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0x320)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK_SHIFT 0U +/* Field Value: VSCALER4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: VSCALER4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: VSCALER4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: VSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: VSCALER4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS ((uint32_t)(0xB24)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x324)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC ((uint32_t)(0xB28)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_OFFSET ((uint32_t)(0x328)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL_SHIFT 0U +/* Field Value: VSCALER4_SRC_SEL__DISABLE, Unit vscaler4 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__DISABLE 0U +/* Field Value: VSCALER4_SRC_SEL__EXTSRC4, Unit vscaler4 input port src is + * connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__EXTSRC4 0x14U +/* Field Value: VSCALER4_SRC_SEL__FETCHDECODE0, Unit vscaler4 input port src + * is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__FETCHDECODE0 0x1CU +/* Field Value: VSCALER4_SRC_SEL__FETCHDECODE2, Unit vscaler4 input port src + * is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__FETCHDECODE2 0x18U +/* Field Value: VSCALER4_SRC_SEL__HSCALER4, Unit vscaler4 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__HSCALER4 0x24U +/* Field Value: VSCALER4_SRC_SEL__MATRIX4, Unit vscaler4 input port src is + * connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__MATRIX4 0x23U +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN_SHIFT 24U +/* Field Value: VSCALER4_CLKEN__DISABLE, Clock for vscaler4 is disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__DISABLE 0U +/* Field Value: VSCALER4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__AUTOMATIC 0x1U +/* Field Value: VSCALER4_CLKEN__FULL, Clock for vscaler4 is without gating */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_Status */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS ((uint32_t)(0xB2C)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_OFFSET ((uint32_t)(0x32C)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL_SHIFT 16U +/* Field Value: VSCALER4_SEL__STORE9, vscaler4 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE9 0x1U +/* Field Value: VSCALER4_SEL__EXTDST0, vscaler4 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST0 0x2U +/* Field Value: VSCALER4_SEL__EXTDST4, vscaler4 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST4 0x3U +/* Field Value: VSCALER4_SEL__EXTDST1, vscaler4 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST1 0x4U +/* Field Value: VSCALER4_SEL__EXTDST5, vscaler4 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST5 0x5U +/* Field Value: VSCALER4_SEL__STORE4, vscaler4 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE4 0x6U +/* Field Value: VSCALER4_SEL__STORE5, vscaler4 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE5 0x7U +/* Field Value: VSCALER4_SEL__DISABLE, vscaler4 module is not used */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_matrix5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK ((uint32_t)(0xB40)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_OFFSET ((uint32_t)(0x340)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK_SHIFT 0U +/* Field Value: MATRIX5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: MATRIX5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: MATRIX5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: MATRIX5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: MATRIX5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_matrix5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS ((uint32_t)(0xB44)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_OFFSET ((uint32_t)(0x344)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_matrix5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC ((uint32_t)(0xB48)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_OFFSET ((uint32_t)(0x348)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL_SHIFT 0U +/* Field Value: MATRIX5_SRC_SEL__DISABLE, Unit matrix5 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL__DISABLE 0U +/* Field Value: MATRIX5_SRC_SEL__GAMMACOR5, Unit matrix5 input port src is + * connected to output of unit gammacor5 */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL__GAMMACOR5 0x27U +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN_SHIFT 24U +/* Field Value: MATRIX5_CLKEN__DISABLE, Clock for matrix5 is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__DISABLE 0U +/* Field Value: MATRIX5_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__AUTOMATIC 0x1U +/* Field Value: MATRIX5_CLKEN__FULL, Clock for matrix5 is without gating */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_matrix5_Status */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS ((uint32_t)(0xB4C)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_OFFSET ((uint32_t)(0x34C)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL_SHIFT 16U +/* Field Value: MATRIX5_SEL__STORE9, matrix5 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE9 0x1U +/* Field Value: MATRIX5_SEL__EXTDST0, matrix5 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST0 0x2U +/* Field Value: MATRIX5_SEL__EXTDST4, matrix5 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST4 0x3U +/* Field Value: MATRIX5_SEL__EXTDST1, matrix5 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST1 0x4U +/* Field Value: MATRIX5_SEL__EXTDST5, matrix5 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST5 0x5U +/* Field Value: MATRIX5_SEL__STORE4, matrix5 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE4 0x6U +/* Field Value: MATRIX5_SEL__STORE5, matrix5 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE5 0x7U +/* Field Value: MATRIX5_SEL__DISABLE, matrix5 module is not used */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK ((uint32_t)(0xB60)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0x360)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK_SHIFT 0U +/* Field Value: HSCALER5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: HSCALER5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: HSCALER5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: HSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: HSCALER5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS ((uint32_t)(0xB64)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x364)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC ((uint32_t)(0xB68)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_OFFSET ((uint32_t)(0x368)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL_SHIFT 0U +/* Field Value: HSCALER5_SRC_SEL__DISABLE, Unit hscaler5 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__DISABLE 0U +/* Field Value: HSCALER5_SRC_SEL__EXTSRC5, Unit hscaler5 input port src is + * connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__EXTSRC5 0x16U +/* Field Value: HSCALER5_SRC_SEL__FETCHDECODE1, Unit hscaler5 input port src + * is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__FETCHDECODE1 0x1EU +/* Field Value: HSCALER5_SRC_SEL__FETCHDECODE3, Unit hscaler5 input port src + * is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__FETCHDECODE3 0x19U +/* Field Value: HSCALER5_SRC_SEL__MATRIX5, Unit hscaler5 input port src is + * connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__MATRIX5 0x28U +/* Field Value: HSCALER5_SRC_SEL__VSCALER5, Unit hscaler5 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__VSCALER5 0x2AU +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN_SHIFT 24U +/* Field Value: HSCALER5_CLKEN__DISABLE, Clock for hscaler5 is disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__DISABLE 0U +/* Field Value: HSCALER5_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__AUTOMATIC 0x1U +/* Field Value: HSCALER5_CLKEN__FULL, Clock for hscaler5 is without gating */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_Status */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS ((uint32_t)(0xB6C)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_OFFSET ((uint32_t)(0x36C)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL_SHIFT 16U +/* Field Value: HSCALER5_SEL__STORE9, hscaler5 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE9 0x1U +/* Field Value: HSCALER5_SEL__EXTDST0, hscaler5 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST0 0x2U +/* Field Value: HSCALER5_SEL__EXTDST4, hscaler5 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST4 0x3U +/* Field Value: HSCALER5_SEL__EXTDST1, hscaler5 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST1 0x4U +/* Field Value: HSCALER5_SEL__EXTDST5, hscaler5 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST5 0x5U +/* Field Value: HSCALER5_SEL__STORE4, hscaler5 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE4 0x6U +/* Field Value: HSCALER5_SEL__STORE5, hscaler5 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE5 0x7U +/* Field Value: HSCALER5_SEL__DISABLE, hscaler5 module is not used */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK ((uint32_t)(0xB80)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0x380)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK_SHIFT 0U +/* Field Value: VSCALER5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: VSCALER5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: VSCALER5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: VSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: VSCALER5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS ((uint32_t)(0xB84)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x384)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC ((uint32_t)(0xB88)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_OFFSET ((uint32_t)(0x388)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL_SHIFT 0U +/* Field Value: VSCALER5_SRC_SEL__DISABLE, Unit vscaler5 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__DISABLE 0U +/* Field Value: VSCALER5_SRC_SEL__EXTSRC5, Unit vscaler5 input port src is + * connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__EXTSRC5 0x16U +/* Field Value: VSCALER5_SRC_SEL__FETCHDECODE1, Unit vscaler5 input port src + * is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__FETCHDECODE1 0x1EU +/* Field Value: VSCALER5_SRC_SEL__FETCHDECODE3, Unit vscaler5 input port src + * is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__FETCHDECODE3 0x19U +/* Field Value: VSCALER5_SRC_SEL__HSCALER5, Unit vscaler5 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__HSCALER5 0x29U +/* Field Value: VSCALER5_SRC_SEL__MATRIX5, Unit vscaler5 input port src is + * connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__MATRIX5 0x28U +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN_SHIFT 24U +/* Field Value: VSCALER5_CLKEN__DISABLE, Clock for vscaler5 is disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__DISABLE 0U +/* Field Value: VSCALER5_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__AUTOMATIC 0x1U +/* Field Value: VSCALER5_CLKEN__FULL, Clock for vscaler5 is without gating */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_Status */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS ((uint32_t)(0xB8C)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_OFFSET ((uint32_t)(0x38C)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL_SHIFT 16U +/* Field Value: VSCALER5_SEL__STORE9, vscaler5 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE9 0x1U +/* Field Value: VSCALER5_SEL__EXTDST0, vscaler5 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST0 0x2U +/* Field Value: VSCALER5_SEL__EXTDST4, vscaler5 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST4 0x3U +/* Field Value: VSCALER5_SEL__EXTDST1, vscaler5 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST1 0x4U +/* Field Value: VSCALER5_SEL__EXTDST5, vscaler5 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST5 0x5U +/* Field Value: VSCALER5_SEL__STORE4, vscaler5 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE4 0x6U +/* Field Value: VSCALER5_SEL__STORE5, vscaler5 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE5 0x7U +/* Field Value: VSCALER5_SEL__DISABLE, vscaler5 module is not used */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK ((uint32_t)(0xBA0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_OFFSET ((uint32_t)(0x3A0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS ((uint32_t)(0xBA4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_OFFSET ((uint32_t)(0x3A4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC ((uint32_t)(0xBA8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_OFFSET ((uint32_t)(0x3A8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_RESET_VALUE 0x1001C0CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND0_PRIM_SEL__DISABLE, Unit layerblend0 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND0_PRIM_SEL__BLITBLEND9, Unit layerblend0 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME0, Unit layerblend0 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME1, Unit layerblend0 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME4, Unit layerblend0 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME5, Unit layerblend0 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND0_PRIM_SEL__MATRIX4, Unit layerblend0 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND0_PRIM_SEL__HSCALER4, Unit layerblend0 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND0_PRIM_SEL__VSCALER4, Unit layerblend0 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND0_PRIM_SEL__EXTSRC4, Unit layerblend0 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND0_PRIM_SEL__MATRIX5, Unit layerblend0 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND0_PRIM_SEL__HSCALER5, Unit layerblend0 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND0_PRIM_SEL__VSCALER5, Unit layerblend0 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND0_PRIM_SEL__EXTSRC5, Unit layerblend0 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__EXTSRC5 0x16U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND0_SEC_SEL__DISABLE, Unit layerblend0 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE2, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE3, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHWARP2, Unit layerblend0 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE0, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE1, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND0_SEC_SEL__MATRIX4, Unit layerblend0 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND0_SEC_SEL__HSCALER4, Unit layerblend0 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND0_SEC_SEL__VSCALER4, Unit layerblend0 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND0_SEC_SEL__MATRIX5, Unit layerblend0 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND0_SEC_SEL__HSCALER5, Unit layerblend0 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND0_SEC_SEL__VSCALER5, Unit layerblend0 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHLAYER0, Unit layerblend0 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHLAYER1, Unit layerblend0 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND0_CLKEN__DISABLE, Clock for layerblend0 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND0_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND0_CLKEN__FULL, Clock for layerblend0 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS ((uint32_t)(0xBAC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_OFFSET ((uint32_t)(0x3AC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL_SHIFT 16U +/* Field Value: LAYERBLEND0_SEL__STORE9, layerblend0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND0_SEL__EXTDST0, layerblend0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND0_SEL__EXTDST4, layerblend0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND0_SEL__EXTDST1, layerblend0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND0_SEL__EXTDST5, layerblend0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND0_SEL__STORE4, layerblend0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND0_SEL__STORE5, layerblend0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND0_SEL__DISABLE, layerblend0 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK ((uint32_t)(0xBC0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_OFFSET ((uint32_t)(0x3C0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS ((uint32_t)(0xBC4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_OFFSET ((uint32_t)(0x3C4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC ((uint32_t)(0xBC8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_OFFSET ((uint32_t)(0x3C8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_RESET_VALUE 0x1001E10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND1_PRIM_SEL__DISABLE, Unit layerblend1 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND1_PRIM_SEL__BLITBLEND9, Unit layerblend1 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME0, Unit layerblend1 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME1, Unit layerblend1 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME4, Unit layerblend1 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME5, Unit layerblend1 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND1_PRIM_SEL__MATRIX4, Unit layerblend1 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND1_PRIM_SEL__HSCALER4, Unit layerblend1 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND1_PRIM_SEL__VSCALER4, Unit layerblend1 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND1_PRIM_SEL__EXTSRC4, Unit layerblend1 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND1_PRIM_SEL__MATRIX5, Unit layerblend1 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND1_PRIM_SEL__HSCALER5, Unit layerblend1 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND1_PRIM_SEL__VSCALER5, Unit layerblend1 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND1_PRIM_SEL__EXTSRC5, Unit layerblend1 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__EXTSRC5 0x16U +/* Field Value: LAYERBLEND1_PRIM_SEL__LAYERBLEND0, Unit layerblend1 input + * port prim is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__LAYERBLEND0 0x2CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND1_SEC_SEL__DISABLE, Unit layerblend1 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE2, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE3, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHWARP2, Unit layerblend1 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE0, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE1, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND1_SEC_SEL__MATRIX4, Unit layerblend1 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND1_SEC_SEL__HSCALER4, Unit layerblend1 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND1_SEC_SEL__VSCALER4, Unit layerblend1 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND1_SEC_SEL__MATRIX5, Unit layerblend1 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND1_SEC_SEL__HSCALER5, Unit layerblend1 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND1_SEC_SEL__VSCALER5, Unit layerblend1 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHLAYER0, Unit layerblend1 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHLAYER1, Unit layerblend1 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND1_CLKEN__DISABLE, Clock for layerblend1 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND1_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND1_CLKEN__FULL, Clock for layerblend1 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS ((uint32_t)(0xBCC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_OFFSET ((uint32_t)(0x3CC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL_SHIFT 16U +/* Field Value: LAYERBLEND1_SEL__STORE9, layerblend1 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND1_SEL__EXTDST0, layerblend1 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND1_SEL__EXTDST4, layerblend1 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND1_SEL__EXTDST1, layerblend1 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND1_SEL__EXTDST5, layerblend1 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND1_SEL__STORE4, layerblend1 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND1_SEL__STORE5, layerblend1 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND1_SEL__DISABLE, layerblend1 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK ((uint32_t)(0xBE0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_OFFSET ((uint32_t)(0x3E0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS ((uint32_t)(0xBE4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_OFFSET ((uint32_t)(0x3E4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC ((uint32_t)(0xBE8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_OFFSET ((uint32_t)(0x3E8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND2_PRIM_SEL__DISABLE, Unit layerblend2 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND2_PRIM_SEL__BLITBLEND9, Unit layerblend2 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME0, Unit layerblend2 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME1, Unit layerblend2 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME4, Unit layerblend2 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME5, Unit layerblend2 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND2_PRIM_SEL__MATRIX4, Unit layerblend2 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND2_PRIM_SEL__HSCALER4, Unit layerblend2 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND2_PRIM_SEL__VSCALER4, Unit layerblend2 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND2_PRIM_SEL__EXTSRC4, Unit layerblend2 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND2_PRIM_SEL__MATRIX5, Unit layerblend2 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND2_PRIM_SEL__HSCALER5, Unit layerblend2 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND2_PRIM_SEL__VSCALER5, Unit layerblend2 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND2_PRIM_SEL__EXTSRC5, Unit layerblend2 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__EXTSRC5 0x16U +/* Field Value: LAYERBLEND2_PRIM_SEL__LAYERBLEND1, Unit layerblend2 input + * port prim is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__LAYERBLEND1 0x2DU +/* Field Value: LAYERBLEND2_PRIM_SEL__LAYERBLEND0, Unit layerblend2 input + * port prim is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__LAYERBLEND0 0x2CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND2_SEC_SEL__DISABLE, Unit layerblend2 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE2, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE3, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHWARP2, Unit layerblend2 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE0, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE1, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND2_SEC_SEL__MATRIX4, Unit layerblend2 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND2_SEC_SEL__HSCALER4, Unit layerblend2 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND2_SEC_SEL__VSCALER4, Unit layerblend2 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND2_SEC_SEL__MATRIX5, Unit layerblend2 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND2_SEC_SEL__HSCALER5, Unit layerblend2 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND2_SEC_SEL__VSCALER5, Unit layerblend2 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHLAYER0, Unit layerblend2 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHLAYER1, Unit layerblend2 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND2_CLKEN__DISABLE, Clock for layerblend2 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND2_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND2_CLKEN__FULL, Clock for layerblend2 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS ((uint32_t)(0xBEC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_OFFSET ((uint32_t)(0x3EC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL_SHIFT 16U +/* Field Value: LAYERBLEND2_SEL__STORE9, layerblend2 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND2_SEL__EXTDST0, layerblend2 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND2_SEL__EXTDST4, layerblend2 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND2_SEL__EXTDST1, layerblend2 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND2_SEL__EXTDST5, layerblend2 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND2_SEL__STORE4, layerblend2 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND2_SEL__STORE5, layerblend2 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND2_SEL__DISABLE, layerblend2 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK ((uint32_t)(0xC00)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND3_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND3_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND3_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND3_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND3_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS ((uint32_t)(0xC04)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC ((uint32_t)(0xC08)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND3_PRIM_SEL__DISABLE, Unit layerblend3 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND3_PRIM_SEL__BLITBLEND9, Unit layerblend3 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME0, Unit layerblend3 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME1, Unit layerblend3 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME4, Unit layerblend3 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME5, Unit layerblend3 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND3_PRIM_SEL__MATRIX4, Unit layerblend3 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND3_PRIM_SEL__HSCALER4, Unit layerblend3 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND3_PRIM_SEL__VSCALER4, Unit layerblend3 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND3_PRIM_SEL__EXTSRC4, Unit layerblend3 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND3_PRIM_SEL__MATRIX5, Unit layerblend3 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND3_PRIM_SEL__HSCALER5, Unit layerblend3 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND3_PRIM_SEL__VSCALER5, Unit layerblend3 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND3_PRIM_SEL__EXTSRC5, Unit layerblend3 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__EXTSRC5 0x16U +/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND2, Unit layerblend3 input + * port prim is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND2 0x2EU +/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND1, Unit layerblend3 input + * port prim is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND1 0x2DU +/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND0, Unit layerblend3 input + * port prim is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND0 0x2CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND3_SEC_SEL__DISABLE, Unit layerblend3 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE2, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE3, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHWARP2, Unit layerblend3 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE0, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE1, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND3_SEC_SEL__MATRIX4, Unit layerblend3 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND3_SEC_SEL__HSCALER4, Unit layerblend3 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND3_SEC_SEL__VSCALER4, Unit layerblend3 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND3_SEC_SEL__MATRIX5, Unit layerblend3 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND3_SEC_SEL__HSCALER5, Unit layerblend3 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND3_SEC_SEL__VSCALER5, Unit layerblend3 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHLAYER0, Unit layerblend3 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHLAYER1, Unit layerblend3 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND3_CLKEN__DISABLE, Clock for layerblend3 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND3_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND3_CLKEN__FULL, Clock for layerblend3 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS ((uint32_t)(0xC0C)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL_SHIFT 16U +/* Field Value: LAYERBLEND3_SEL__STORE9, layerblend3 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND3_SEL__EXTDST0, layerblend3 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND3_SEL__EXTDST4, layerblend3 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND3_SEL__EXTDST1, layerblend3 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND3_SEL__EXTDST5, layerblend3 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND3_SEL__STORE4, layerblend3 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND3_SEL__STORE5, layerblend3 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND3_SEL__DISABLE, layerblend3 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__DISABLE 0U + +/* Register: IMXDPUV1_FetchDecode9_LockUnlock */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK ((uint32_t)(0x1000)) +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_FetchDecode9_LockStatus */ +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS ((uint32_t)(0x1004)) +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode9_StaticControl */ +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL ((uint32_t)(0x1008)) +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_BurstBufferManagement */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x100C)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_FetchDecode9_RingBufStartAddr0 */ +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0 ((uint32_t)(0x1010)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_RingBufWrapAddr0 */ +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0 ((uint32_t)(0x1014)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_FrameProperties0 */ +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0 ((uint32_t)(0x1018)) +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_BaseAddress0 */ +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0 ((uint32_t)(0x101C)) +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1020)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1024)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ColorComponentBits0 */ +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0 ((uint32_t)(0x1028)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode9_ColorComponentShift0 */ +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x102C)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode9_LayerOffset0 */ +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0 ((uint32_t)(0x1030)) +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1034)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x1038)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ConstantColor0 */ +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0 ((uint32_t)(0x103C)) +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode9_LayerProperty0 */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0 ((uint32_t)(0x1040)) +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode9_FrameDimensions */ +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS ((uint32_t)(0x1044)) +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode9_FrameResampling */ +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING ((uint32_t)(0x1048)) +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode9_DecodeControl */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL ((uint32_t)(0x104C)) +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression). */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U +/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length. */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RL 0x3U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS_SHIFT 15U +/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U +/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_FetchDecode9_SourceBufferLength */ +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH ((uint32_t)(0x1050)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_Control */ +#define IMXDPUV1_FETCHDECODE9_CONTROL ((uint32_t)(0x1054)) +#define IMXDPUV1_FETCHDECODE9_CONTROL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHDECODE9_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U +/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed + * samples (UV samples between Y samples). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U +/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned + * samples (UV samples at Y sample positions). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHDECODE9_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHDECODE9_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_FetchDecode9_ControlTrigger */ +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER ((uint32_t)(0x1058)) +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_Start */ +#define IMXDPUV1_FETCHDECODE9_START ((uint32_t)(0x105C)) +#define IMXDPUV1_FETCHDECODE9_START_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHDECODE9_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE9_START_START_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_FetchType */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE ((uint32_t)(0x1060)) +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_FetchDecode9_DecoderStatus */ +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS ((uint32_t)(0x1064)) +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U + +/* Register: IMXDPUV1_FetchDecode9_ReadAddress0 */ +#define IMXDPUV1_FETCHDECODE9_READADDRESS0 ((uint32_t)(0x1068)) +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_READADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_BurstBufferProperties */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES ((uint32_t)(0x106C)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode9_Status */ +#define IMXDPUV1_FETCHDECODE9_STATUS ((uint32_t)(0x1070)) +#define IMXDPUV1_FETCHDECODE9_STATUS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHDECODE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHDECODE9_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_FetchDecode9_HiddenStatus */ +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS ((uint32_t)(0x1074)) +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode9_ColorPalette */ +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE ((uint32_t)(0x1400)) +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_LockUnlock */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK ((uint32_t)(0x1800)) +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetchwarp9_LockStatus */ +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS ((uint32_t)(0x1804)) +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp9_StaticControl */ +#define IMXDPUV1_FETCHWARP9_STATICCONTROL ((uint32_t)(0x1808)) +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_VALUE 0xFF000000U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_BurstBufferManagement */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x180C)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress0 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0 ((uint32_t)(0x1810)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1814)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1818)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits0 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0 ((uint32_t)(0x181C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift0 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x1820)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset0 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0 ((uint32_t)(0x1824)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1828)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x182C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor0 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0 ((uint32_t)(0x1830)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty0 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0 ((uint32_t)(0x1834)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress1 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1 ((uint32_t)(0x1838)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_BASEADDRESS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_BASEADDRESS1_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes1 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1 ((uint32_t)(0x183C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension1 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1 ((uint32_t)(0x1840)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits1 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1 ((uint32_t)(0x1844)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift1 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1 ((uint32_t)(0x1848)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset1 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1 ((uint32_t)(0x184C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset1 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1 ((uint32_t)(0x1850)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions1 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1 ((uint32_t)(0x1854)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor1 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1 ((uint32_t)(0x1858)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty1 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1 ((uint32_t)(0x185C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1_SHIFT 4U +/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U +/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHAMASKENABLE1_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHAMASKENABLE1_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHAMASKENABLE1_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHAMASKENABLE1_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U +/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress2 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2 ((uint32_t)(0x1860)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_BASEADDRESS2_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_BASEADDRESS2_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes2 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2 ((uint32_t)(0x1864)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension2 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2 ((uint32_t)(0x1868)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits2 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2 ((uint32_t)(0x186C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift2 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2 ((uint32_t)(0x1870)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset2 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2 ((uint32_t)(0x1874)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset2 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2 ((uint32_t)(0x1878)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions2 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2 ((uint32_t)(0x187C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor2 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2 ((uint32_t)(0x1880)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty2 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2 ((uint32_t)(0x1884)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2_SHIFT 4U +/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U +/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHAMASKENABLE2_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHAMASKENABLE2_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHAMASKENABLE2_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHAMASKENABLE2_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U +/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress3 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3 ((uint32_t)(0x1888)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_BASEADDRESS3_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_BASEADDRESS3_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes3 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3 ((uint32_t)(0x188C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension3 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3 ((uint32_t)(0x1890)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits3 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3 ((uint32_t)(0x1894)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift3 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3 ((uint32_t)(0x1898)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset3 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3 ((uint32_t)(0x189C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset3 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3 ((uint32_t)(0x18A0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions3 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3 ((uint32_t)(0x18A4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor3 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3 ((uint32_t)(0x18A8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty3 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3 ((uint32_t)(0x18AC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3_SHIFT 4U +/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U +/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHAMASKENABLE3_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHAMASKENABLE3_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHAMASKENABLE3_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHAMASKENABLE3_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U +/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress4 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4 ((uint32_t)(0x18B0)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_BASEADDRESS4_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_BASEADDRESS4_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes4 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4 ((uint32_t)(0x18B4)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension4 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4 ((uint32_t)(0x18B8)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits4 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4 ((uint32_t)(0x18BC)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift4 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4 ((uint32_t)(0x18C0)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset4 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4 ((uint32_t)(0x18C4)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset4 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4 ((uint32_t)(0x18C8)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions4 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4 ((uint32_t)(0x18CC)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor4 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4 ((uint32_t)(0x18D0)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty4 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4 ((uint32_t)(0x18D4)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4_SHIFT 4U +/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U +/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHAMASKENABLE4_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHAMASKENABLE4_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHAMASKENABLE4_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHAMASKENABLE4_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U +/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress5 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5 ((uint32_t)(0x18D8)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_BASEADDRESS5_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_BASEADDRESS5_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes5 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5 ((uint32_t)(0x18DC)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension5 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5 ((uint32_t)(0x18E0)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits5 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5 ((uint32_t)(0x18E4)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift5 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5 ((uint32_t)(0x18E8)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset5 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5 ((uint32_t)(0x18EC)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset5 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5 ((uint32_t)(0x18F0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions5 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5 ((uint32_t)(0x18F4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor5 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5 ((uint32_t)(0x18F8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty5 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5 ((uint32_t)(0x18FC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5_SHIFT 4U +/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U +/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHAMASKENABLE5_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHAMASKENABLE5_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHAMASKENABLE5_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHAMASKENABLE5_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U +/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress6 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6 ((uint32_t)(0x1900)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_BASEADDRESS6_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_BASEADDRESS6_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes6 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6 ((uint32_t)(0x1904)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension6 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6 ((uint32_t)(0x1908)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits6 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6 ((uint32_t)(0x190C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift6 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6 ((uint32_t)(0x1910)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset6 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6 ((uint32_t)(0x1914)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset6 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6 ((uint32_t)(0x1918)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions6 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6 ((uint32_t)(0x191C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor6 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6 ((uint32_t)(0x1920)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty6 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6 ((uint32_t)(0x1924)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6_SHIFT 4U +/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U +/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHAMASKENABLE6_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHAMASKENABLE6_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHAMASKENABLE6_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHAMASKENABLE6_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U +/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress7 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7 ((uint32_t)(0x1928)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_BASEADDRESS7_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_BASEADDRESS7_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes7 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7 ((uint32_t)(0x192C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension7 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7 ((uint32_t)(0x1930)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits7 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7 ((uint32_t)(0x1934)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift7 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7 ((uint32_t)(0x1938)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset7 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7 ((uint32_t)(0x193C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset7 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7 ((uint32_t)(0x1940)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions7 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7 ((uint32_t)(0x1944)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor7 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7 ((uint32_t)(0x1948)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty7 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7 ((uint32_t)(0x194C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7_SHIFT 4U +/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U +/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHAMASKENABLE7_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHAMASKENABLE7_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHAMASKENABLE7_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHAMASKENABLE7_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U +/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_FrameDimensions */ +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS ((uint32_t)(0x1950)) +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_FrameResampling */ +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING ((uint32_t)(0x1954)) +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_WarpControl */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL ((uint32_t)(0x1958)) +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPBITSPERPIXEL_MASK 0x3FU +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPBITSPERPIXEL_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE_MASK 0x300U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE_SHIFT 8U +/* Field Value: WARPCOORDINATEMODE__PNT, x and y (sample points). */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__PNT 0U +/* Field Value: WARPCOORDINATEMODE__D_PNT, dx and dy (vectors between adjacent + * sample points). */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__D_PNT 0x1U +/* Field Value: WARPCOORDINATEMODE__DD_PNT, ddx and ddy (deltas between adjacent + * vectors). */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__DD_PNT 0x2U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPSYMMETRICOFFSET_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPSYMMETRICOFFSET_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp9_ArbStartX */ +#define IMXDPUV1_FETCHWARP9_ARBSTARTX ((uint32_t)(0x195C)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_ARBSTARTX_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_ARBSTARTX_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_ArbStartY */ +#define IMXDPUV1_FETCHWARP9_ARBSTARTY ((uint32_t)(0x1960)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_ARBSTARTY_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_ARBSTARTY_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_ArbDelta */ +#define IMXDPUV1_FETCHWARP9_ARBDELTA ((uint32_t)(0x1964)) +#define IMXDPUV1_FETCHWARP9_ARBDELTA_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_FETCHWARP9_ARBDELTA_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXX_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXX_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXY_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXY_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYX_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYX_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_FIRPositions */ +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS ((uint32_t)(0x1968)) +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_RESET_VALUE 0xA965U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR0POSITION_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR0POSITION_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR1POSITION_MASK 0xF0U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR1POSITION_SHIFT 4U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR2POSITION_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR2POSITION_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR3POSITION_MASK 0xF000U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR3POSITION_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp9_FIRCoefficients */ +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS ((uint32_t)(0x196C)) +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR0COEFFICIENT_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR0COEFFICIENT_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR1COEFFICIENT_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR1COEFFICIENT_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR2COEFFICIENT_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR2COEFFICIENT_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR3COEFFICIENT_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR3COEFFICIENT_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_Control */ +#define IMXDPUV1_FETCHWARP9_CONTROL ((uint32_t)(0x1970)) +#define IMXDPUV1_FETCHWARP9_CONTROL_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_FETCHWARP9_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHWARP9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHWARP9_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHWARP9_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR__LAYER 0x1U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPLAYER_MASK 0xE0000U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPLAYER_SHIFT 17U +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE_MASK 0x700000U +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE_SHIFT 20U +/* Field Value: FILTERMODE__NEAREST, Chooses pixel closest to sample point */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__NEAREST 0U +/* Field Value: FILTERMODE__BILINEAR, Calculates result from 4 pixels closest + * to sample point */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__BILINEAR 0x1U +/* Field Value: FILTERMODE__FIR2, FIR mode with 2 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__FIR2 0x2U +/* Field Value: FILTERMODE__FIR4, FIR mode with 4 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__FIR4 0x3U +/* Field Value: FILTERMODE__HOR_LINEAR, Calculates result from 2 pixels closest + * to the sample point and on the same line */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__HOR_LINEAR 0x4U + +/* Register: IMXDPUV1_fetchwarp9_TriggerEnable */ +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE ((uint32_t)(0x1974)) +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_ControlTrigger */ +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER ((uint32_t)(0x1978)) +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_Start */ +#define IMXDPUV1_FETCHWARP9_START ((uint32_t)(0x197C)) +#define IMXDPUV1_FETCHWARP9_START_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_FETCHWARP9_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP9_START_START_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_FetchType */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE ((uint32_t)(0x1980)) +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetchwarp9_BurstBufferProperties */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES ((uint32_t)(0x1984)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp9_Status */ +#define IMXDPUV1_FETCHWARP9_STATUS ((uint32_t)(0x1988)) +#define IMXDPUV1_FETCHWARP9_STATUS_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_FETCHWARP9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHWARP9_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_fetchwarp9_HiddenStatus */ +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS ((uint32_t)(0x198C)) +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco9_LockUnlock */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK ((uint32_t)(0x1C00)) +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco9_LockStatus */ +#define IMXDPUV1_FETCHECO9_LOCKSTATUS ((uint32_t)(0x1C04)) +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco9_StaticControl */ +#define IMXDPUV1_FETCHECO9_STATICCONTROL ((uint32_t)(0x1C08)) +#define IMXDPUV1_FETCHECO9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x1C0C)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco9_BaseAddress0 */ +#define IMXDPUV1_FETCHECO9_BASEADDRESS0 ((uint32_t)(0x1C10)) +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco9_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1C14)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1C18)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0 ((uint32_t)(0x1C1C)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco9_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x1C20)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco9_LayerOffset0 */ +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0 ((uint32_t)(0x1C24)) +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1C28)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x1C2C)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ConstantColor0 */ +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0 ((uint32_t)(0x1C30)) +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco9_LayerProperty0 */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0 ((uint32_t)(0x1C34)) +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco9_FrameDimensions */ +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS ((uint32_t)(0x1C38)) +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco9_FrameResampling */ +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING ((uint32_t)(0x1C3C)) +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco9_Control */ +#define IMXDPUV1_FETCHECO9_CONTROL ((uint32_t)(0x1C40)) +#define IMXDPUV1_FETCHECO9_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO9_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO9_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco9_ControlTrigger */ +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER ((uint32_t)(0x1C44)) +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco9_Start */ +#define IMXDPUV1_FETCHECO9_START ((uint32_t)(0x1C48)) +#define IMXDPUV1_FETCHECO9_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO9_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO9_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco9_FetchType */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE ((uint32_t)(0x1C4C)) +#define IMXDPUV1_FETCHECO9_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO9_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco9_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES ((uint32_t)(0x1C50)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco9_HiddenStatus */ +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS ((uint32_t)(0x1C54)) +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_rop9_LockUnlock */ +#define IMXDPUV1_ROP9_LOCKUNLOCK ((uint32_t)(0x2000)) +#define IMXDPUV1_ROP9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_ROP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_ROP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_rop9_LockStatus */ +#define IMXDPUV1_ROP9_LOCKSTATUS ((uint32_t)(0x2004)) +#define IMXDPUV1_ROP9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_ROP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_ROP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_ROP9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_ROP9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_ROP9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_ROP9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_ROP9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_rop9_StaticControl */ +#define IMXDPUV1_ROP9_STATICCONTROL ((uint32_t)(0x2008)) +#define IMXDPUV1_ROP9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_ROP9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_ROP9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_ROP9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_rop9_Control */ +#define IMXDPUV1_ROP9_CONTROL ((uint32_t)(0x200C)) +#define IMXDPUV1_ROP9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_ROP9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_ROP9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_ROP9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode */ +#define IMXDPUV1_ROP9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__OPERATION, Normal Operation */ +#define IMXDPUV1_ROP9_CONTROL_MODE__OPERATION 0x1U +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE_MASK 0x10U +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE_SHIFT 4U +/* Field Value: ALPHAMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE__ROP 0U +/* Field Value: ALPHAMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE_MASK 0x20U +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE_SHIFT 5U +/* Field Value: BLUEMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE__ROP 0U +/* Field Value: BLUEMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_GREENMODE_MASK 0x40U +#define IMXDPUV1_ROP9_CONTROL_GREENMODE_SHIFT 6U +/* Field Value: GREENMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_GREENMODE__ROP 0U +/* Field Value: GREENMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_GREENMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_REDMODE_MASK 0x80U +#define IMXDPUV1_ROP9_CONTROL_REDMODE_SHIFT 7U +/* Field Value: REDMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_REDMODE__ROP 0U +/* Field Value: REDMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_REDMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2_MASK 0x100U +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2_SHIFT 8U +/* Field Value: PRIMDIV2__BYPASS, No change to input */ +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2__BYPASS 0U +/* Field Value: PRIMDIV2__DIVIDEBY2, Input is divided by two/shift to the + * right by one */ +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2__DIVIDEBY2 0x1U +#define IMXDPUV1_ROP9_CONTROL_SECDIV2_MASK 0x200U +#define IMXDPUV1_ROP9_CONTROL_SECDIV2_SHIFT 9U +/* Field Value: SECDIV2__BYPASS, No change to input */ +#define IMXDPUV1_ROP9_CONTROL_SECDIV2__BYPASS 0U +/* Field Value: SECDIV2__DIVIDEBY2, Input is divided by two/shift to the right + * by one */ +#define IMXDPUV1_ROP9_CONTROL_SECDIV2__DIVIDEBY2 0x1U +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2_MASK 0x400U +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2_SHIFT 10U +/* Field Value: TERTDIV2__BYPASS, No change to input */ +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2__BYPASS 0U +/* Field Value: TERTDIV2__DIVIDEBY2, Input is divided by two/shift to the + * right by one */ +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2__DIVIDEBY2 0x1U + +/* Register: IMXDPUV1_rop9_RasterOperationIndices */ +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES ((uint32_t)(0x2010)) +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_RESET_VALUE 0U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXALPHA_MASK 0xFFU +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXALPHA_SHIFT 0U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXBLUE_MASK 0xFF00U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXBLUE_SHIFT 8U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXGREEN_MASK 0xFF0000U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXGREEN_SHIFT 16U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXRED_MASK 0xFF000000U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXRED_SHIFT 24U + +/* Register: IMXDPUV1_rop9_PrimControlWord */ +#define IMXDPUV1_ROP9_PRIMCONTROLWORD ((uint32_t)(0x2014)) +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_rop9_SecControlWord */ +#define IMXDPUV1_ROP9_SECCONTROLWORD ((uint32_t)(0x2018)) +#define IMXDPUV1_ROP9_SECCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_ROP9_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_ROP9_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_ROP9_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_rop9_TertControlWord */ +#define IMXDPUV1_ROP9_TERTCONTROLWORD ((uint32_t)(0x201C)) +#define IMXDPUV1_ROP9_TERTCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_ROP9_TERTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_ROP9_TERTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_ROP9_TERTCONTROLWORD_T_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_TERTCONTROLWORD_T_VAL_SHIFT 0U + +/* Register: IMXDPUV1_clut9_LockUnlock */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK ((uint32_t)(0x2400)) +#define IMXDPUV1_CLUT9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CLUT9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_clut9_LockStatus */ +#define IMXDPUV1_CLUT9_LOCKSTATUS ((uint32_t)(0x2404)) +#define IMXDPUV1_CLUT9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CLUT9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CLUT9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CLUT9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CLUT9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CLUT9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CLUT9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_clut9_StaticControl */ +#define IMXDPUV1_CLUT9_STATICCONTROL ((uint32_t)(0x2408)) +#define IMXDPUV1_CLUT9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CLUT9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CLUT9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_clut9_UnshadowedControl */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL ((uint32_t)(0x240C)) +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN_MASK 0x1U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN_SHIFT 0U +/* Field Value: B_EN__DISABLE, disable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__DISABLE 0U +/* Field Value: B_EN__ENABLE, enable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__ENABLE 0x1U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN_MASK 0x2U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN_SHIFT 1U +/* Field Value: G_EN__DISABLE, disable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__DISABLE 0U +/* Field Value: G_EN__ENABLE, enable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__ENABLE 0x1U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN_MASK 0x4U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN_SHIFT 2U +/* Field Value: R_EN__DISABLE, disable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__DISABLE 0U +/* Field Value: R_EN__ENABLE, enable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__ENABLE 0x1U + +/* Register: IMXDPUV1_clut9_Control */ +#define IMXDPUV1_CLUT9_CONTROL ((uint32_t)(0x2410)) +#define IMXDPUV1_CLUT9_CONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CLUT9_CONTROL_RESET_VALUE 0x800U +#define IMXDPUV1_CLUT9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_CLUT9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, module in neutral mode, input data is bypassed + * to the output */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__LUT, module in color lookup mode (LUT holds a 10bit + * color value for CLut derivate and 8bit color value for CLutL derivate + * for each input color) */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__LUT 0x1U +/* Field Value: MODE__INDEX_10BIT, module in 10bit color index table mode + * (LUT holds a 3x10bit color value for derivate CLut and 3x8bit color value + * for CLUTL derivate, indexed with the red input color) */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__INDEX_10BIT 0x2U +/* Field Value: MODE__INDEX_RGBA, module in RGBA color index table mode (LUT + * holds a 3x8bit color value and a 6bit alpha value for CLut derivate + * and 3x6bit color value and 6bit alpha value for CLutL derivate, indexed + * with the red input color) */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__INDEX_RGBA 0x3U +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT_MASK 0x10U +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT_SHIFT 4U +/* Field Value: COL_8BIT__DISABLE, color is 10bit output */ +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT__DISABLE 0U +/* Field Value: COL_8BIT__ENABLE, color is 8bit output (dithering of internal + * 10bit value) */ +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT__ENABLE 0x1U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK_MASK 0x20U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK_SHIFT 5U +/* Field Value: ALPHAMASK__DISABLE, Alpha mask mode disabled */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK__DISABLE 0U +/* Field Value: ALPHAMASK__ENABLE, Alpha mask mode enabled */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK__ENABLE 0x1U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT_MASK 0x40U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT_SHIFT 6U +/* Field Value: ALPHAINVERT__NORMAL, Disable computation for alpha smaller + * than 128 */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT__NORMAL 0U +/* Field Value: ALPHAINVERT__INVERT, Disable computation for alpha greater + * than or equal to 128 */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT__INVERT 0x1U +#define IMXDPUV1_CLUT9_CONTROL_IDX_BITS_MASK 0xF00U +#define IMXDPUV1_CLUT9_CONTROL_IDX_BITS_SHIFT 8U + +/* Register: IMXDPUV1_clut9_Status */ +#define IMXDPUV1_CLUT9_STATUS ((uint32_t)(0x2414)) +#define IMXDPUV1_CLUT9_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CLUT9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_STATUS_WRITE_TIMEOUT_MASK 0x1U +#define IMXDPUV1_CLUT9_STATUS_WRITE_TIMEOUT_SHIFT 0U +#define IMXDPUV1_CLUT9_STATUS_READ_TIMEOUT_MASK 0x10U +#define IMXDPUV1_CLUT9_STATUS_READ_TIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_clut9_LastControlWord */ +#define IMXDPUV1_CLUT9_LASTCONTROLWORD ((uint32_t)(0x2418)) +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_clut9_LUT */ +#define IMXDPUV1_CLUT9_LUT ((uint32_t)(0x2800)) +#define IMXDPUV1_CLUT9_LUT_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CLUT9_LUT_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LUT_RESET_MASK 0xC0000000U +#define IMXDPUV1_CLUT9_LUT_BLUE_MASK 0x3FFU +#define IMXDPUV1_CLUT9_LUT_BLUE_SHIFT 0U +#define IMXDPUV1_CLUT9_LUT_GREEN_MASK 0xFFC00U +#define IMXDPUV1_CLUT9_LUT_GREEN_SHIFT 10U +#define IMXDPUV1_CLUT9_LUT_RED_MASK 0x3FF00000U +#define IMXDPUV1_CLUT9_LUT_RED_SHIFT 20U + +/* Register: IMXDPUV1_matrix9_LockUnlock */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK ((uint32_t)(0x2C00)) +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix9_LockStatus */ +#define IMXDPUV1_MATRIX9_LOCKSTATUS ((uint32_t)(0x2C04)) +#define IMXDPUV1_MATRIX9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix9_StaticControl */ +#define IMXDPUV1_MATRIX9_STATICCONTROL ((uint32_t)(0x2C08)) +#define IMXDPUV1_MATRIX9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix9_Control */ +#define IMXDPUV1_MATRIX9_CONTROL ((uint32_t)(0x2C0C)) +#define IMXDPUV1_MATRIX9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix9_Red0 */ +#define IMXDPUV1_MATRIX9_RED0 ((uint32_t)(0x2C10)) +#define IMXDPUV1_MATRIX9_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX9_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX9_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX9_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Red1 */ +#define IMXDPUV1_MATRIX9_RED1 ((uint32_t)(0x2C14)) +#define IMXDPUV1_MATRIX9_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX9_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX9_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Green0 */ +#define IMXDPUV1_MATRIX9_GREEN0 ((uint32_t)(0x2C18)) +#define IMXDPUV1_MATRIX9_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX9_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX9_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX9_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Green1 */ +#define IMXDPUV1_MATRIX9_GREEN1 ((uint32_t)(0x2C1C)) +#define IMXDPUV1_MATRIX9_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX9_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX9_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Blue0 */ +#define IMXDPUV1_MATRIX9_BLUE0 ((uint32_t)(0x2C20)) +#define IMXDPUV1_MATRIX9_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX9_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX9_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Blue1 */ +#define IMXDPUV1_MATRIX9_BLUE1 ((uint32_t)(0x2C24)) +#define IMXDPUV1_MATRIX9_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX9_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX9_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX9_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Alpha0 */ +#define IMXDPUV1_MATRIX9_ALPHA0 ((uint32_t)(0x2C28)) +#define IMXDPUV1_MATRIX9_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX9_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX9_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Alpha1 */ +#define IMXDPUV1_MATRIX9_ALPHA1 ((uint32_t)(0x2C2C)) +#define IMXDPUV1_MATRIX9_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX9_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX9_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX9_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_OffsetVector0 */ +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0 ((uint32_t)(0x2C30)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_OffsetVector1 */ +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1 ((uint32_t)(0x2C34)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_LastControlWord */ +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD ((uint32_t)(0x2C38)) +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_LockUnlock */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK ((uint32_t)(0x3000)) +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_hscaler9_LockStatus */ +#define IMXDPUV1_HSCALER9_LOCKSTATUS ((uint32_t)(0x3004)) +#define IMXDPUV1_HSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_HSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_hscaler9_StaticControl */ +#define IMXDPUV1_HSCALER9_STATICCONTROL ((uint32_t)(0x3008)) +#define IMXDPUV1_HSCALER9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_HSCALER9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_Setup1 */ +#define IMXDPUV1_HSCALER9_SETUP1 ((uint32_t)(0x300C)) +#define IMXDPUV1_HSCALER9_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_HSCALER9_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_HSCALER9_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_HSCALER9_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_Setup2 */ +#define IMXDPUV1_HSCALER9_SETUP2 ((uint32_t)(0x3010)) +#define IMXDPUV1_HSCALER9_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_HSCALER9_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_HSCALER9_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_Control */ +#define IMXDPUV1_HSCALER9_CONTROL ((uint32_t)(0x3014)) +#define IMXDPUV1_HSCALER9_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_HSCALER9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_HSCALER9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_HSCALER9_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size) */ +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_HSCALER9_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_vscaler9_LockUnlock */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK ((uint32_t)(0x3400)) +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_vscaler9_LockStatus */ +#define IMXDPUV1_VSCALER9_LOCKSTATUS ((uint32_t)(0x3404)) +#define IMXDPUV1_VSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_VSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_vscaler9_StaticControl */ +#define IMXDPUV1_VSCALER9_STATICCONTROL ((uint32_t)(0x3408)) +#define IMXDPUV1_VSCALER9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_VSCALER9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup1 */ +#define IMXDPUV1_VSCALER9_SETUP1 ((uint32_t)(0x340C)) +#define IMXDPUV1_VSCALER9_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_VSCALER9_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_VSCALER9_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_VSCALER9_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup2 */ +#define IMXDPUV1_VSCALER9_SETUP2 ((uint32_t)(0x3410)) +#define IMXDPUV1_VSCALER9_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_VSCALER9_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup3 */ +#define IMXDPUV1_VSCALER9_SETUP3 ((uint32_t)(0x3414)) +#define IMXDPUV1_VSCALER9_SETUP3_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_VSCALER9_SETUP3_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP3_PHASE_OFFSET1_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP3_PHASE_OFFSET1_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup4 */ +#define IMXDPUV1_VSCALER9_SETUP4 ((uint32_t)(0x3418)) +#define IMXDPUV1_VSCALER9_SETUP4_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_VSCALER9_SETUP4_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP4_PHASE_OFFSET2_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP4_PHASE_OFFSET2_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup5 */ +#define IMXDPUV1_VSCALER9_SETUP5 ((uint32_t)(0x341C)) +#define IMXDPUV1_VSCALER9_SETUP5_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_VSCALER9_SETUP5_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP5_PHASE_OFFSET3_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP5_PHASE_OFFSET3_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Control */ +#define IMXDPUV1_VSCALER9_CONTROL ((uint32_t)(0x3420)) +#define IMXDPUV1_VSCALER9_CONTROL_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_VSCALER9_CONTROL_RESET_VALUE 0x2000U +#define IMXDPUV1_VSCALER9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_VSCALER9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_VSCALER9_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size). */ +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE_MASK 0x3000U +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE_SHIFT 12U +/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__ALWAYS0 0U +/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__ALWAYS1 0x1U +/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input + * field polarity. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__INPUT 0x2U +/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting + * with 0 after reset. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__TOGGLE 0x3U +#define IMXDPUV1_VSCALER9_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_VSCALER9_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_filter9_LockUnlock */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK ((uint32_t)(0x3800)) +#define IMXDPUV1_FILTER9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FILTER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_filter9_LockStatus */ +#define IMXDPUV1_FILTER9_LOCKSTATUS ((uint32_t)(0x3804)) +#define IMXDPUV1_FILTER9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FILTER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FILTER9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FILTER9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FILTER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FILTER9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FILTER9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_filter9_StaticControl */ +#define IMXDPUV1_FILTER9_STATICCONTROL ((uint32_t)(0x3808)) +#define IMXDPUV1_FILTER9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FILTER9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FILTER9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_filter9_Control */ +#define IMXDPUV1_FILTER9_CONTROL ((uint32_t)(0x380C)) +#define IMXDPUV1_FILTER9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FILTER9_CONTROL_RESET_VALUE 0x5500U +#define IMXDPUV1_FILTER9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_FILTER9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the filter, all + * other settings are ignored. */ +#define IMXDPUV1_FILTER9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Filter is active. */ +#define IMXDPUV1_FILTER9_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE_MASK 0x30U +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE_SHIFT 4U +/* Field Value: TILE_MODE__PAD, Samples outside the frame are padded with + * the last valid border pixels. */ +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__PAD 0U +/* Field Value: TILE_MODE__ZERO, Samples outside the frame are treated as + * zero pixel value. */ +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__ZERO 0x1U +/* Field Value: TILE_MODE__PAD_ZERO, Applies tile mode PAD to RGB channels + * and tile mode ZERO to alpha channel. */ +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__PAD_ZERO 0x2U +#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE_MASK 0xFFFF00U +#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__FIR_5X5, FIR filter 5x5 window. */ +#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE__FIR_5X5 0x55U +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT_MASK 0x30000000U +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT_SHIFT 28U +/* Field Value: BUFFER_FORMAT__RGB888, RGB888 format. Alpha is not filtered + * but set to constant value 255. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGB888 0U +/* Field Value: BUFFER_FORMAT__RGBA5658, RGBA5658 format. Alpha is filtered. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA5658 0x1U +/* Field Value: BUFFER_FORMAT__RGBA8888, RGBA8888 format. Alpha is filtered. + * The filter window is limited to 5x4. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA8888 0x2U +/* Field Value: BUFFER_FORMAT__RGBA1010108, RGBA10.10.10.8 format. Alpha is + * filtered. The filter window is limited to 5x3. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA1010108 0x3U + +/* Register: IMXDPUV1_filter9_FIR_control */ +#define IMXDPUV1_FILTER9_FIR_CONTROL ((uint32_t)(0x3810)) +#define IMXDPUV1_FILTER9_FIR_CONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FILTER9_FIR_CONTROL_RESET_VALUE 0xEU +#define IMXDPUV1_FILTER9_FIR_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_COMPONENT_SELECT_MASK 0xFU +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_COMPONENT_SELECT_SHIFT 0U +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_EXPONENT_MASK 0xF00U +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_EXPONENT_SHIFT 8U + +/* Register: IMXDPUV1_filter9_Coefficients0 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS0 ((uint32_t)(0x3814)) +#define IMXDPUV1_FILTER9_COEFFICIENTS0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FILTER9_COEFFICIENTS0_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF0_0_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF0_0_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF1_0_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF1_0_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF2_0_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF2_0_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF3_0_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF3_0_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients1 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS1 ((uint32_t)(0x3818)) +#define IMXDPUV1_FILTER9_COEFFICIENTS1_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FILTER9_COEFFICIENTS1_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF4_0_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF4_0_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF0_1_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF0_1_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF1_1_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF1_1_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF2_1_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF2_1_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients2 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS2 ((uint32_t)(0x381C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS2_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS2_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF3_1_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF3_1_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF4_1_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF4_1_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF0_2_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF0_2_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF1_2_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF1_2_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients3 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS3 ((uint32_t)(0x3820)) +#define IMXDPUV1_FILTER9_COEFFICIENTS3_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FILTER9_COEFFICIENTS3_RESET_VALUE 0x1U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF2_2_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF2_2_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF3_2_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF3_2_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF4_2_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF4_2_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF0_3_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF0_3_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients4 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS4 ((uint32_t)(0x3824)) +#define IMXDPUV1_FILTER9_COEFFICIENTS4_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FILTER9_COEFFICIENTS4_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF1_3_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF1_3_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF2_3_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF2_3_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF3_3_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF3_3_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF4_3_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF4_3_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients5 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS5 ((uint32_t)(0x3828)) +#define IMXDPUV1_FILTER9_COEFFICIENTS5_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FILTER9_COEFFICIENTS5_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF0_4_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF0_4_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF1_4_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF1_4_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF2_4_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF2_4_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF3_4_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF3_4_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients6 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS6 ((uint32_t)(0x382C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS6_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS6_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS6_COEFF4_4_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS6_COEFF4_4_SHIFT 0U + +/* Register: IMXDPUV1_blitblend9_LockUnlock */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK ((uint32_t)(0x3C00)) +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_blitblend9_LockStatus */ +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS ((uint32_t)(0x3C04)) +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_blitblend9_StaticControl */ +#define IMXDPUV1_BLITBLEND9_STATICCONTROL ((uint32_t)(0x3C08)) +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_blitblend9_Control */ +#define IMXDPUV1_BLITBLEND9_CONTROL ((uint32_t)(0x3C0C)) +#define IMXDPUV1_BLITBLEND9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_BLITBLEND9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode, only route pixels and commands + * from primary input to output */ +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__OPERATION, Normal Operation */ +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE__OPERATION 0x1U + +/* Register: IMXDPUV1_blitblend9_NeutralBorder */ +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER ((uint32_t)(0x3C10)) +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE_SHIFT 0U +/* Field Value: NEUTRALBORDERMODE__PRIMARY, Bypasses primary pixel */ +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE__PRIMARY 0U +/* Field Value: NEUTRALBORDERMODE__SECONDARY, Bypasses secondary pixel */ +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE__SECONDARY 0x1U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERLEFT_MASK 0x700U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERLEFT_SHIFT 8U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERRIGHT_MASK 0x7000U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERRIGHT_SHIFT 12U + +/* Register: IMXDPUV1_blitblend9_ConstantColor */ +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR ((uint32_t)(0x3C14)) +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_blitblend9_ColorRedBlendFunction */ +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION ((uint32_t)(0x3C18)) +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_ColorGreenBlendFunction */ +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION ((uint32_t)(0x3C1C)) +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_ColorBlueBlendFunction */ +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION ((uint32_t)(0x3C20)) +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_AlphaBlendFunction */ +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION ((uint32_t)(0x3C24)) +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_BlendMode1 */ +#define IMXDPUV1_BLITBLEND9_BLENDMODE1 ((uint32_t)(0x3C28)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_RESET_VALUE 0x80068006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_ADDITIVE 0x2009U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_ADDITIVE 0x2009U + +/* Register: IMXDPUV1_blitblend9_BlendMode2 */ +#define IMXDPUV1_BLITBLEND9_BLENDMODE2 ((uint32_t)(0x3C2C)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_RESET_VALUE 0x80068006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_ADDITIVE 0x2009U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_ADDITIVE 0x2009U + +/* Register: IMXDPUV1_blitblend9_DirectSetup */ +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP ((uint32_t)(0x3C30)) +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_COLORDEBUG_MASK 0x3FFU +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_COLORDEBUG_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_ALPHADEBUG_MASK 0x3FF0000U +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_ALPHADEBUG_SHIFT 16U + +/* Register: IMXDPUV1_blitblend9_PrimControlWord */ +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD ((uint32_t)(0x3C34)) +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_blitblend9_SecControlWord */ +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD ((uint32_t)(0x3C38)) +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_store9_LockUnlock */ +#define IMXDPUV1_STORE9_LOCKUNLOCK ((uint32_t)(0x4000)) +#define IMXDPUV1_STORE9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_STORE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_STORE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_store9_LockStatus */ +#define IMXDPUV1_STORE9_LOCKSTATUS ((uint32_t)(0x4004)) +#define IMXDPUV1_STORE9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_STORE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_STORE9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_STORE9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_STORE9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_STORE9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_STORE9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_store9_StaticControl */ +#define IMXDPUV1_STORE9_STATICCONTROL ((uint32_t)(0x4008)) +#define IMXDPUV1_STORE9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_STORE9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_STORE9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_STORE9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0x100U +#define IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 8U + +/* Register: IMXDPUV1_store9_BurstBufferManagement */ +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x400C)) +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x400U +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U + +/* Register: IMXDPUV1_store9_RingBufStartAddr */ +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR ((uint32_t)(0x4010)) +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RESET_VALUE 0U +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RINGBUFSTARTADDR_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RINGBUFSTARTADDR_SHIFT 0U + +/* Register: IMXDPUV1_store9_RingBufWrapAddr */ +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR ((uint32_t)(0x4014)) +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RESET_VALUE 0U +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RINGBUFWRAPADDR_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RINGBUFWRAPADDR_SHIFT 0U + +/* Register: IMXDPUV1_store9_BaseAddress */ +#define IMXDPUV1_STORE9_BASEADDRESS ((uint32_t)(0x4018)) +#define IMXDPUV1_STORE9_BASEADDRESS_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_STORE9_BASEADDRESS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_BASEADDRESS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_BASEADDRESS_BASEADDRESS_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_BASEADDRESS_BASEADDRESS_SHIFT 0U + +/* Register: IMXDPUV1_store9_DestinationBufferAttributes */ +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES ((uint32_t)(0x401C)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_RESET_VALUE 0x200004FFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE_MASK 0x1FFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE_SHIFT 0U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL_MASK 0x7F000000U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL_SHIFT 24U + +/* Register: IMXDPUV1_store9_DestinationBufferDimension */ +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION ((uint32_t)(0x4020)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH_SHIFT 0U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT_MASK 0x3FFF0000U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT_SHIFT 16U + +/* Register: IMXDPUV1_store9_FrameOffset */ +#define IMXDPUV1_STORE9_FRAMEOFFSET ((uint32_t)(0x4024)) +#define IMXDPUV1_STORE9_FRAMEOFFSET_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_STORE9_FRAMEOFFSET_RESET_VALUE 0U +#define IMXDPUV1_STORE9_FRAMEOFFSET_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET_MASK 0x7FFFU +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET_SHIFT 0U +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET_MASK 0x7FFF0000U +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET_SHIFT 16U + +/* Register: IMXDPUV1_store9_ColorComponentBits */ +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS ((uint32_t)(0x4028)) +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_RESET_VALUE 0x8080808U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSALPHA_MASK 0xFU +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSALPHA_SHIFT 0U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSBLUE_MASK 0xF00U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSBLUE_SHIFT 8U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSGREEN_MASK 0xF0000U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSGREEN_SHIFT 16U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSRED_MASK 0xF000000U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSRED_SHIFT 24U + +/* Register: IMXDPUV1_store9_ColorComponentShift */ +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT ((uint32_t)(0x402C)) +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_RESET_VALUE 0x18100800U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTALPHA_MASK 0x1FU +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTALPHA_SHIFT 0U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE_MASK 0x1F00U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE_SHIFT 8U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN_MASK 0x1F0000U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN_SHIFT 16U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED_MASK 0x1F000000U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED_SHIFT 24U + +/* Register: IMXDPUV1_store9_Control */ +#define IMXDPUV1_STORE9_CONTROL ((uint32_t)(0x4030)) +#define IMXDPUV1_STORE9_CONTROL_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_STORE9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_STORE9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_CONTROL_COLORDITHERENABLE_MASK 0x1U +#define IMXDPUV1_STORE9_CONTROL_COLORDITHERENABLE_SHIFT 0U +#define IMXDPUV1_STORE9_CONTROL_ALPHADITHERENABLE_MASK 0x2U +#define IMXDPUV1_STORE9_CONTROL_ALPHADITHERENABLE_SHIFT 1U +#define IMXDPUV1_STORE9_CONTROL_DITHEROFFSET_MASK 0xF0U +#define IMXDPUV1_STORE9_CONTROL_DITHEROFFSET_SHIFT 4U +#define IMXDPUV1_STORE9_CONTROL_GAMMAAPPLYENABLE_MASK 0x1000U +#define IMXDPUV1_STORE9_CONTROL_GAMMAAPPLYENABLE_SHIFT 12U +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE_MASK 0x30000U +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE_SHIFT 16U +/* Field Value: YUVCONVERSIONMODE__OFF, No conversion. Input data must be + * RGB. */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__OFF 0U +/* Field Value: YUVCONVERSIONMODE__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU709 0x3U +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE_MASK 0xC0000U +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE_SHIFT 18U +/* Field Value: RASTERMODE__NORMAL, RGBA or YUV 4:4:4 pixel buffer. */ +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__YUV422, [Store derivate only] Packed YUV 4:2:2 + * pixel buffer. Effect is that U samples are written for pixels with even + * and V samples for odd column index only. So BitsPerPixel must be set + * to the size that a pair of YU or YV has in memory (most typically 16 + * bits). All correlated widths and horizontal offsets must be even. */ +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__YUV422 0x1U +/* Field Value: RASTERMODE__ENCODE, [Store derivate only] RLAD compressed + * bit stream. */ +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__ENCODE 0x2U +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE_MASK 0x300000U +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE_SHIFT 20U +/* Field Value: YUV422DOWNSAMPLINGMODE__NEAREST, Nearest mode. Discards all + * odd samples, outputs even samples. */ +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__NEAREST 0U +/* Field Value: YUV422DOWNSAMPLINGMODE__COALIGNED, Linear coaligned mode. + * 3 nearest UV samples are combined in linear filter to get one output sample. */ +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__COALIGNED 0x1U +/* Field Value: YUV422DOWNSAMPLINGMODE__INTERSPERSED, Linear interspersed + * mode. 2 nearest UV samples are combined in linear filter to get one output + * sample. */ +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__INTERSPERSED 0x2U + +/* Register: IMXDPUV1_store9_EncodeControl */ +#define IMXDPUV1_STORE9_ENCODECONTROL ((uint32_t)(0x4034)) +#define IMXDPUV1_STORE9_ENCODECONTROL_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_STORE9_ENCODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_STORE9_ENCODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE_MASK 0x1U +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_store9_DestinationBufferLength */ +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH ((uint32_t)(0x4038)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RLEWORDSMAX_MASK 0x1FFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RLEWORDSMAX_SHIFT 0U + +/* Register: IMXDPUV1_store9_Start */ +#define IMXDPUV1_STORE9_START ((uint32_t)(0x403C)) +#define IMXDPUV1_STORE9_START_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_STORE9_START_RESET_VALUE 0U +#define IMXDPUV1_STORE9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_STORE9_START_START_MASK 0x1U +#define IMXDPUV1_STORE9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_store9_EncoderStatus */ +#define IMXDPUV1_STORE9_ENCODERSTATUS ((uint32_t)(0x4040)) +#define IMXDPUV1_STORE9_ENCODERSTATUS_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_STORE9_ENCODERSTATUS_RESET_VALUE 0x1FFFFFFFU +#define IMXDPUV1_STORE9_ENCODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_ENCODERSTATUS_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_STORE9_ENCODERSTATUS_RLEWORDS_SHIFT 0U +#define IMXDPUV1_STORE9_ENCODERSTATUS_BUFFERTOOSMALL_MASK 0x80000000U +#define IMXDPUV1_STORE9_ENCODERSTATUS_BUFFERTOOSMALL_SHIFT 31U + +/* Register: IMXDPUV1_store9_WriteAddress */ +#define IMXDPUV1_STORE9_WRITEADDRESS ((uint32_t)(0x4044)) +#define IMXDPUV1_STORE9_WRITEADDRESS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_STORE9_WRITEADDRESS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_WRITEADDRESS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_WRITEADDRESS_WRITEADDRESS_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_WRITEADDRESS_WRITEADDRESS_SHIFT 0U + +/* Register: IMXDPUV1_store9_FrameProperties */ +#define IMXDPUV1_STORE9_FRAMEPROPERTIES ((uint32_t)(0x4048)) +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_FIELDID_MASK 0x1U +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_FIELDID_SHIFT 0U + +/* Register: IMXDPUV1_store9_BurstBufferProperties */ +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES ((uint32_t)(0x404C)) +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE0FFU +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_MAXBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_MAXBURSTLENGTH_SHIFT 8U + +/* Register: IMXDPUV1_store9_LastControlWord */ +#define IMXDPUV1_STORE9_LASTCONTROLWORD ((uint32_t)(0x4050)) +#define IMXDPUV1_STORE9_LASTCONTROLWORD_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_STORE9_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_STORE9_LASTCONTROLWORD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_store9_PerfCounter */ +#define IMXDPUV1_STORE9_PERFCOUNTER ((uint32_t)(0x4054)) +#define IMXDPUV1_STORE9_PERFCOUNTER_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_STORE9_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_STORE9_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_store9_Status */ +#define IMXDPUV1_STORE9_STATUS ((uint32_t)(0x4058)) +#define IMXDPUV1_STORE9_STATUS_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_STORE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_STATUS_RESET_MASK 0xFFFFFF8EU +#define IMXDPUV1_STORE9_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_STORE9_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_STORE9_STATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_STORE9_STATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_STORE9_STATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_STORE9_STATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_STORE9_STATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_STORE9_STATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_STORE9_STATUS_PIXELBUSERROR_MASK 0x100U +#define IMXDPUV1_STORE9_STATUS_PIXELBUSERROR_SHIFT 8U +#define IMXDPUV1_STORE9_STATUS_ENCODEROVERFLOW_MASK 0x10000U +#define IMXDPUV1_STORE9_STATUS_ENCODEROVERFLOW_SHIFT 16U +#define IMXDPUV1_STORE9_STATUS_ENCODERSTALLPIXEL_MASK 0x20000U +#define IMXDPUV1_STORE9_STATUS_ENCODERSTALLPIXEL_SHIFT 17U + +/* Register: IMXDPUV1_constframe0_LockUnlock */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK ((uint32_t)(0x4400)) +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe0_LockStatus */ +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS ((uint32_t)(0x4404)) +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe0_StaticControl */ +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL ((uint32_t)(0x4408)) +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe0_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS ((uint32_t)(0x440C)) +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe0_ConstantColor */ +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR ((uint32_t)(0x4410)) +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe0_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER ((uint32_t)(0x4414)) +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe0_Start */ +#define IMXDPUV1_CONSTFRAME0_START ((uint32_t)(0x4418)) +#define IMXDPUV1_CONSTFRAME0_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME0_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME0_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe0_Status */ +#define IMXDPUV1_CONSTFRAME0_STATUS ((uint32_t)(0x441C)) +#define IMXDPUV1_CONSTFRAME0_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME0_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME0_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst0_LockUnlock */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK ((uint32_t)(0x4800)) +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst0_LockStatus */ +#define IMXDPUV1_EXTDST0_LOCKSTATUS ((uint32_t)(0x4804)) +#define IMXDPUV1_EXTDST0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst0_StaticControl */ +#define IMXDPUV1_EXTDST0_STATICCONTROL ((uint32_t)(0x4808)) +#define IMXDPUV1_EXTDST0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST0_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst0_Control */ +#define IMXDPUV1_EXTDST0_CONTROL ((uint32_t)(0x480C)) +#define IMXDPUV1_EXTDST0_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST0_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_SoftwareKick */ +#define IMXDPUV1_EXTDST0_SOFTWAREKICK ((uint32_t)(0x4810)) +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_Status */ +#define IMXDPUV1_EXTDST0_STATUS ((uint32_t)(0x4814)) +#define IMXDPUV1_EXTDST0_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST0_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_ControlWord */ +#define IMXDPUV1_EXTDST0_CONTROLWORD ((uint32_t)(0x4818)) +#define IMXDPUV1_EXTDST0_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST0_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_CurPixelCnt */ +#define IMXDPUV1_EXTDST0_CURPIXELCNT ((uint32_t)(0x481C)) +#define IMXDPUV1_EXTDST0_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST0_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst0_LastPixelCnt */ +#define IMXDPUV1_EXTDST0_LASTPIXELCNT ((uint32_t)(0x4820)) +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst0_PerfCounter */ +#define IMXDPUV1_EXTDST0_PERFCOUNTER ((uint32_t)(0x4824)) +#define IMXDPUV1_EXTDST0_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST0_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_LockUnlock */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK ((uint32_t)(0x4C00)) +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe4_LockStatus */ +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS ((uint32_t)(0x4C04)) +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe4_StaticControl */ +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL ((uint32_t)(0x4C08)) +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS ((uint32_t)(0x4C0C)) +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe4_ConstantColor */ +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR ((uint32_t)(0x4C10)) +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe4_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER ((uint32_t)(0x4C14)) +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_Start */ +#define IMXDPUV1_CONSTFRAME4_START ((uint32_t)(0x4C18)) +#define IMXDPUV1_CONSTFRAME4_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME4_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME4_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_Status */ +#define IMXDPUV1_CONSTFRAME4_STATUS ((uint32_t)(0x4C1C)) +#define IMXDPUV1_CONSTFRAME4_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME4_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME4_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst4_LockUnlock */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK ((uint32_t)(0x5000)) +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst4_LockStatus */ +#define IMXDPUV1_EXTDST4_LOCKSTATUS ((uint32_t)(0x5004)) +#define IMXDPUV1_EXTDST4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst4_StaticControl */ +#define IMXDPUV1_EXTDST4_STATICCONTROL ((uint32_t)(0x5008)) +#define IMXDPUV1_EXTDST4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST4_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST4_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST4_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST4_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst4_Control */ +#define IMXDPUV1_EXTDST4_CONTROL ((uint32_t)(0x500C)) +#define IMXDPUV1_EXTDST4_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST4_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST4_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_SoftwareKick */ +#define IMXDPUV1_EXTDST4_SOFTWAREKICK ((uint32_t)(0x5010)) +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_Status */ +#define IMXDPUV1_EXTDST4_STATUS ((uint32_t)(0x5014)) +#define IMXDPUV1_EXTDST4_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST4_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_ControlWord */ +#define IMXDPUV1_EXTDST4_CONTROLWORD ((uint32_t)(0x5018)) +#define IMXDPUV1_EXTDST4_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST4_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_CurPixelCnt */ +#define IMXDPUV1_EXTDST4_CURPIXELCNT ((uint32_t)(0x501C)) +#define IMXDPUV1_EXTDST4_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST4_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst4_LastPixelCnt */ +#define IMXDPUV1_EXTDST4_LASTPIXELCNT ((uint32_t)(0x5020)) +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst4_PerfCounter */ +#define IMXDPUV1_EXTDST4_PERFCOUNTER ((uint32_t)(0x5024)) +#define IMXDPUV1_EXTDST4_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST4_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_LockUnlock */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK ((uint32_t)(0x5400)) +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe1_LockStatus */ +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS ((uint32_t)(0x5404)) +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe1_StaticControl */ +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL ((uint32_t)(0x5408)) +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS ((uint32_t)(0x540C)) +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe1_ConstantColor */ +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR ((uint32_t)(0x5410)) +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe1_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER ((uint32_t)(0x5414)) +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_Start */ +#define IMXDPUV1_CONSTFRAME1_START ((uint32_t)(0x5418)) +#define IMXDPUV1_CONSTFRAME1_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME1_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME1_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_Status */ +#define IMXDPUV1_CONSTFRAME1_STATUS ((uint32_t)(0x541C)) +#define IMXDPUV1_CONSTFRAME1_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME1_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME1_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst1_LockUnlock */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK ((uint32_t)(0x5800)) +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst1_LockStatus */ +#define IMXDPUV1_EXTDST1_LOCKSTATUS ((uint32_t)(0x5804)) +#define IMXDPUV1_EXTDST1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst1_StaticControl */ +#define IMXDPUV1_EXTDST1_STATICCONTROL ((uint32_t)(0x5808)) +#define IMXDPUV1_EXTDST1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST1_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst1_Control */ +#define IMXDPUV1_EXTDST1_CONTROL ((uint32_t)(0x580C)) +#define IMXDPUV1_EXTDST1_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST1_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_SoftwareKick */ +#define IMXDPUV1_EXTDST1_SOFTWAREKICK ((uint32_t)(0x5810)) +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_Status */ +#define IMXDPUV1_EXTDST1_STATUS ((uint32_t)(0x5814)) +#define IMXDPUV1_EXTDST1_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST1_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_ControlWord */ +#define IMXDPUV1_EXTDST1_CONTROLWORD ((uint32_t)(0x5818)) +#define IMXDPUV1_EXTDST1_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST1_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_CurPixelCnt */ +#define IMXDPUV1_EXTDST1_CURPIXELCNT ((uint32_t)(0x581C)) +#define IMXDPUV1_EXTDST1_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST1_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst1_LastPixelCnt */ +#define IMXDPUV1_EXTDST1_LASTPIXELCNT ((uint32_t)(0x5820)) +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst1_PerfCounter */ +#define IMXDPUV1_EXTDST1_PERFCOUNTER ((uint32_t)(0x5824)) +#define IMXDPUV1_EXTDST1_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST1_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_LockUnlock */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK ((uint32_t)(0x5C00)) +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe5_LockStatus */ +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS ((uint32_t)(0x5C04)) +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe5_StaticControl */ +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL ((uint32_t)(0x5C08)) +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS ((uint32_t)(0x5C0C)) +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe5_ConstantColor */ +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR ((uint32_t)(0x5C10)) +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe5_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER ((uint32_t)(0x5C14)) +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_Start */ +#define IMXDPUV1_CONSTFRAME5_START ((uint32_t)(0x5C18)) +#define IMXDPUV1_CONSTFRAME5_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME5_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME5_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_Status */ +#define IMXDPUV1_CONSTFRAME5_STATUS ((uint32_t)(0x5C1C)) +#define IMXDPUV1_CONSTFRAME5_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME5_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME5_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst5_LockUnlock */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK ((uint32_t)(0x6000)) +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst5_LockStatus */ +#define IMXDPUV1_EXTDST5_LOCKSTATUS ((uint32_t)(0x6004)) +#define IMXDPUV1_EXTDST5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst5_StaticControl */ +#define IMXDPUV1_EXTDST5_STATICCONTROL ((uint32_t)(0x6008)) +#define IMXDPUV1_EXTDST5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST5_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST5_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST5_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST5_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst5_Control */ +#define IMXDPUV1_EXTDST5_CONTROL ((uint32_t)(0x600C)) +#define IMXDPUV1_EXTDST5_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST5_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST5_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_SoftwareKick */ +#define IMXDPUV1_EXTDST5_SOFTWAREKICK ((uint32_t)(0x6010)) +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_Status */ +#define IMXDPUV1_EXTDST5_STATUS ((uint32_t)(0x6014)) +#define IMXDPUV1_EXTDST5_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST5_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_ControlWord */ +#define IMXDPUV1_EXTDST5_CONTROLWORD ((uint32_t)(0x6018)) +#define IMXDPUV1_EXTDST5_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST5_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_CurPixelCnt */ +#define IMXDPUV1_EXTDST5_CURPIXELCNT ((uint32_t)(0x601C)) +#define IMXDPUV1_EXTDST5_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST5_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst5_LastPixelCnt */ +#define IMXDPUV1_EXTDST5_LASTPIXELCNT ((uint32_t)(0x6020)) +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst5_PerfCounter */ +#define IMXDPUV1_EXTDST5_PERFCOUNTER ((uint32_t)(0x6024)) +#define IMXDPUV1_EXTDST5_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST5_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_LockUnlock */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK ((uint32_t)(0x6400)) +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetchwarp2_LockStatus */ +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS ((uint32_t)(0x6404)) +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp2_StaticControl */ +#define IMXDPUV1_FETCHWARP2_STATICCONTROL ((uint32_t)(0x6408)) +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_VALUE 0xFF000000U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_BurstBufferManagement */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT ((uint32_t)(0x640C)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress0 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0 ((uint32_t)(0x6410)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x6414)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x6418)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits0 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0 ((uint32_t)(0x641C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift0 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0 ((uint32_t)(0x6420)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset0 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0 ((uint32_t)(0x6424)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0 ((uint32_t)(0x6428)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x642C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor0 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0 ((uint32_t)(0x6430)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty0 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0 ((uint32_t)(0x6434)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress1 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1 ((uint32_t)(0x6438)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_BASEADDRESS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_BASEADDRESS1_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes1 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1 ((uint32_t)(0x643C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension1 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1 ((uint32_t)(0x6440)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits1 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1 ((uint32_t)(0x6444)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift1 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1 ((uint32_t)(0x6448)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset1 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1 ((uint32_t)(0x644C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset1 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1 ((uint32_t)(0x6450)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions1 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1 ((uint32_t)(0x6454)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor1 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1 ((uint32_t)(0x6458)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty1 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1 ((uint32_t)(0x645C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1_SHIFT 4U +/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U +/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHAMASKENABLE1_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHAMASKENABLE1_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHAMASKENABLE1_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHAMASKENABLE1_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U +/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress2 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2 ((uint32_t)(0x6460)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_BASEADDRESS2_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_BASEADDRESS2_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes2 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2 ((uint32_t)(0x6464)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension2 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2 ((uint32_t)(0x6468)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits2 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2 ((uint32_t)(0x646C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift2 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2 ((uint32_t)(0x6470)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset2 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2 ((uint32_t)(0x6474)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset2 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2 ((uint32_t)(0x6478)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions2 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2 ((uint32_t)(0x647C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor2 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2 ((uint32_t)(0x6480)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty2 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2 ((uint32_t)(0x6484)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2_SHIFT 4U +/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U +/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHAMASKENABLE2_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHAMASKENABLE2_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHAMASKENABLE2_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHAMASKENABLE2_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U +/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress3 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3 ((uint32_t)(0x6488)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_BASEADDRESS3_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_BASEADDRESS3_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes3 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3 ((uint32_t)(0x648C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension3 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3 ((uint32_t)(0x6490)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits3 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3 ((uint32_t)(0x6494)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift3 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3 ((uint32_t)(0x6498)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset3 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3 ((uint32_t)(0x649C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset3 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3 ((uint32_t)(0x64A0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions3 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3 ((uint32_t)(0x64A4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor3 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3 ((uint32_t)(0x64A8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty3 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3 ((uint32_t)(0x64AC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3_SHIFT 4U +/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U +/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHAMASKENABLE3_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHAMASKENABLE3_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHAMASKENABLE3_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHAMASKENABLE3_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U +/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress4 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4 ((uint32_t)(0x64B0)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_BASEADDRESS4_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_BASEADDRESS4_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes4 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4 ((uint32_t)(0x64B4)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension4 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4 ((uint32_t)(0x64B8)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits4 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4 ((uint32_t)(0x64BC)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift4 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4 ((uint32_t)(0x64C0)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset4 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4 ((uint32_t)(0x64C4)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset4 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4 ((uint32_t)(0x64C8)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions4 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4 ((uint32_t)(0x64CC)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor4 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4 ((uint32_t)(0x64D0)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty4 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4 ((uint32_t)(0x64D4)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4_SHIFT 4U +/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U +/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHAMASKENABLE4_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHAMASKENABLE4_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHAMASKENABLE4_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHAMASKENABLE4_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U +/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress5 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5 ((uint32_t)(0x64D8)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_BASEADDRESS5_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_BASEADDRESS5_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes5 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5 ((uint32_t)(0x64DC)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension5 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5 ((uint32_t)(0x64E0)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits5 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5 ((uint32_t)(0x64E4)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift5 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5 ((uint32_t)(0x64E8)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset5 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5 ((uint32_t)(0x64EC)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset5 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5 ((uint32_t)(0x64F0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions5 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5 ((uint32_t)(0x64F4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor5 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5 ((uint32_t)(0x64F8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty5 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5 ((uint32_t)(0x64FC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5_SHIFT 4U +/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U +/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHAMASKENABLE5_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHAMASKENABLE5_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHAMASKENABLE5_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHAMASKENABLE5_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U +/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress6 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6 ((uint32_t)(0x6500)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_BASEADDRESS6_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_BASEADDRESS6_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes6 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6 ((uint32_t)(0x6504)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension6 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6 ((uint32_t)(0x6508)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits6 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6 ((uint32_t)(0x650C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift6 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6 ((uint32_t)(0x6510)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset6 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6 ((uint32_t)(0x6514)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset6 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6 ((uint32_t)(0x6518)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions6 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6 ((uint32_t)(0x651C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor6 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6 ((uint32_t)(0x6520)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty6 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6 ((uint32_t)(0x6524)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6_SHIFT 4U +/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U +/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHAMASKENABLE6_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHAMASKENABLE6_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHAMASKENABLE6_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHAMASKENABLE6_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U +/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress7 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7 ((uint32_t)(0x6528)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_BASEADDRESS7_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_BASEADDRESS7_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes7 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7 ((uint32_t)(0x652C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension7 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7 ((uint32_t)(0x6530)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits7 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7 ((uint32_t)(0x6534)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift7 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7 ((uint32_t)(0x6538)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset7 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7 ((uint32_t)(0x653C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset7 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7 ((uint32_t)(0x6540)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions7 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7 ((uint32_t)(0x6544)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor7 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7 ((uint32_t)(0x6548)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty7 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7 ((uint32_t)(0x654C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7_SHIFT 4U +/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U +/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHAMASKENABLE7_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHAMASKENABLE7_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHAMASKENABLE7_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHAMASKENABLE7_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U +/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_FrameDimensions */ +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS ((uint32_t)(0x6550)) +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_FrameResampling */ +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING ((uint32_t)(0x6554)) +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_WarpControl */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL ((uint32_t)(0x6558)) +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPBITSPERPIXEL_MASK 0x3FU +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPBITSPERPIXEL_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE_MASK 0x300U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE_SHIFT 8U +/* Field Value: WARPCOORDINATEMODE__PNT, x and y (sample points). */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__PNT 0U +/* Field Value: WARPCOORDINATEMODE__D_PNT, dx and dy (vectors between adjacent + * sample points). */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__D_PNT 0x1U +/* Field Value: WARPCOORDINATEMODE__DD_PNT, ddx and ddy (deltas between adjacent + * vectors). */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__DD_PNT 0x2U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPSYMMETRICOFFSET_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPSYMMETRICOFFSET_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp2_ArbStartX */ +#define IMXDPUV1_FETCHWARP2_ARBSTARTX ((uint32_t)(0x655C)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_ARBSTARTX_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_ARBSTARTX_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_ArbStartY */ +#define IMXDPUV1_FETCHWARP2_ARBSTARTY ((uint32_t)(0x6560)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_ARBSTARTY_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_ARBSTARTY_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_ArbDelta */ +#define IMXDPUV1_FETCHWARP2_ARBDELTA ((uint32_t)(0x6564)) +#define IMXDPUV1_FETCHWARP2_ARBDELTA_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_FETCHWARP2_ARBDELTA_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXX_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXX_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXY_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXY_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYX_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYX_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_FIRPositions */ +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS ((uint32_t)(0x6568)) +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_RESET_VALUE 0xA965U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR0POSITION_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR0POSITION_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR1POSITION_MASK 0xF0U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR1POSITION_SHIFT 4U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR2POSITION_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR2POSITION_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR3POSITION_MASK 0xF000U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR3POSITION_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp2_FIRCoefficients */ +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS ((uint32_t)(0x656C)) +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR0COEFFICIENT_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR0COEFFICIENT_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR1COEFFICIENT_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR1COEFFICIENT_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR2COEFFICIENT_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR2COEFFICIENT_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR3COEFFICIENT_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR3COEFFICIENT_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_Control */ +#define IMXDPUV1_FETCHWARP2_CONTROL ((uint32_t)(0x6570)) +#define IMXDPUV1_FETCHWARP2_CONTROL_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_FETCHWARP2_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHWARP2_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHWARP2_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHWARP2_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR__LAYER 0x1U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPLAYER_MASK 0xE0000U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPLAYER_SHIFT 17U +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE_MASK 0x700000U +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE_SHIFT 20U +/* Field Value: FILTERMODE__NEAREST, Chooses pixel closest to sample point */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__NEAREST 0U +/* Field Value: FILTERMODE__BILINEAR, Calculates result from 4 pixels closest + * to sample point */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__BILINEAR 0x1U +/* Field Value: FILTERMODE__FIR2, FIR mode with 2 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__FIR2 0x2U +/* Field Value: FILTERMODE__FIR4, FIR mode with 4 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__FIR4 0x3U +/* Field Value: FILTERMODE__HOR_LINEAR, Calculates result from 2 pixels closest + * to the sample point and on the same line */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__HOR_LINEAR 0x4U + +/* Register: IMXDPUV1_fetchwarp2_TriggerEnable */ +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE ((uint32_t)(0x6574)) +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_ControlTrigger */ +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER ((uint32_t)(0x6578)) +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_Start */ +#define IMXDPUV1_FETCHWARP2_START ((uint32_t)(0x657C)) +#define IMXDPUV1_FETCHWARP2_START_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_FETCHWARP2_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP2_START_START_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_FetchType */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE ((uint32_t)(0x6580)) +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetchwarp2_BurstBufferProperties */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES ((uint32_t)(0x6584)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp2_Status */ +#define IMXDPUV1_FETCHWARP2_STATUS ((uint32_t)(0x6588)) +#define IMXDPUV1_FETCHWARP2_STATUS_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_FETCHWARP2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHWARP2_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_fetchwarp2_HiddenStatus */ +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS ((uint32_t)(0x658C)) +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco2_LockUnlock */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK ((uint32_t)(0x6800)) +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco2_LockStatus */ +#define IMXDPUV1_FETCHECO2_LOCKSTATUS ((uint32_t)(0x6804)) +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco2_StaticControl */ +#define IMXDPUV1_FETCHECO2_STATICCONTROL ((uint32_t)(0x6808)) +#define IMXDPUV1_FETCHECO2_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO2_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT ((uint32_t)(0x680C)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco2_BaseAddress0 */ +#define IMXDPUV1_FETCHECO2_BASEADDRESS0 ((uint32_t)(0x6810)) +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco2_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x6814)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x6818)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0 ((uint32_t)(0x681C)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco2_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0 ((uint32_t)(0x6820)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco2_LayerOffset0 */ +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0 ((uint32_t)(0x6824)) +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0 ((uint32_t)(0x6828)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x682C)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ConstantColor0 */ +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0 ((uint32_t)(0x6830)) +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco2_LayerProperty0 */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0 ((uint32_t)(0x6834)) +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco2_FrameDimensions */ +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS ((uint32_t)(0x6838)) +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco2_FrameResampling */ +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING ((uint32_t)(0x683C)) +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco2_Control */ +#define IMXDPUV1_FETCHECO2_CONTROL ((uint32_t)(0x6840)) +#define IMXDPUV1_FETCHECO2_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO2_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO2_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO2_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco2_ControlTrigger */ +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER ((uint32_t)(0x6844)) +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco2_Start */ +#define IMXDPUV1_FETCHECO2_START ((uint32_t)(0x6848)) +#define IMXDPUV1_FETCHECO2_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO2_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO2_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO2_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco2_FetchType */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE ((uint32_t)(0x684C)) +#define IMXDPUV1_FETCHECO2_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO2_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco2_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES ((uint32_t)(0x6850)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco2_HiddenStatus */ +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS ((uint32_t)(0x6854)) +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_LockUnlock */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK ((uint32_t)(0x6C00)) +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_FetchDecode0_LockStatus */ +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS ((uint32_t)(0x6C04)) +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_StaticControl */ +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL ((uint32_t)(0x6C08)) +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_BurstBufferManagement */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT ((uint32_t)(0x6C0C)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_FetchDecode0_RingBufStartAddr0 */ +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0 ((uint32_t)(0x6C10)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_RingBufWrapAddr0 */ +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0 ((uint32_t)(0x6C14)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_FrameProperties0 */ +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0 ((uint32_t)(0x6C18)) +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_BaseAddress0 */ +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0 ((uint32_t)(0x6C1C)) +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x6C20)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x6C24)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ColorComponentBits0 */ +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0 ((uint32_t)(0x6C28)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode0_ColorComponentShift0 */ +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0 ((uint32_t)(0x6C2C)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode0_LayerOffset0 */ +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0 ((uint32_t)(0x6C30)) +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0 ((uint32_t)(0x6C34)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x6C38)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ConstantColor0 */ +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0 ((uint32_t)(0x6C3C)) +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode0_LayerProperty0 */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0 ((uint32_t)(0x6C40)) +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode0_FrameDimensions */ +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS ((uint32_t)(0x6C44)) +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode0_FrameResampling */ +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING ((uint32_t)(0x6C48)) +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode0_DecodeControl */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL ((uint32_t)(0x6C4C)) +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression). */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U +/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length. */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RL 0x3U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS_SHIFT 15U +/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U +/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_FetchDecode0_SourceBufferLength */ +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH ((uint32_t)(0x6C50)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_Control */ +#define IMXDPUV1_FETCHDECODE0_CONTROL ((uint32_t)(0x6C54)) +#define IMXDPUV1_FETCHDECODE0_CONTROL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHDECODE0_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U +/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed + * samples (UV samples between Y samples). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U +/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned + * samples (UV samples at Y sample positions). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_FetchDecode0_ControlTrigger */ +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER ((uint32_t)(0x6C58)) +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_Start */ +#define IMXDPUV1_FETCHDECODE0_START ((uint32_t)(0x6C5C)) +#define IMXDPUV1_FETCHDECODE0_START_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHDECODE0_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE0_START_START_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_FetchType */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE ((uint32_t)(0x6C60)) +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_FetchDecode0_DecoderStatus */ +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS ((uint32_t)(0x6C64)) +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U + +/* Register: IMXDPUV1_FetchDecode0_ReadAddress0 */ +#define IMXDPUV1_FETCHDECODE0_READADDRESS0 ((uint32_t)(0x6C68)) +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_READADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_BurstBufferProperties */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES ((uint32_t)(0x6C6C)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_Status */ +#define IMXDPUV1_FETCHDECODE0_STATUS ((uint32_t)(0x6C70)) +#define IMXDPUV1_FETCHDECODE0_STATUS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHDECODE0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHDECODE0_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_FetchDecode0_HiddenStatus */ +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS ((uint32_t)(0x6C74)) +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_ColorPalette */ +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE ((uint32_t)(0x7000)) +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_LockUnlock */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK ((uint32_t)(0x7400)) +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco0_LockStatus */ +#define IMXDPUV1_FETCHECO0_LOCKSTATUS ((uint32_t)(0x7404)) +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco0_StaticControl */ +#define IMXDPUV1_FETCHECO0_STATICCONTROL ((uint32_t)(0x7408)) +#define IMXDPUV1_FETCHECO0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT ((uint32_t)(0x740C)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco0_BaseAddress0 */ +#define IMXDPUV1_FETCHECO0_BASEADDRESS0 ((uint32_t)(0x7410)) +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x7414)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x7418)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0 ((uint32_t)(0x741C)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco0_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0 ((uint32_t)(0x7420)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco0_LayerOffset0 */ +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0 ((uint32_t)(0x7424)) +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0 ((uint32_t)(0x7428)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x742C)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ConstantColor0 */ +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0 ((uint32_t)(0x7430)) +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco0_LayerProperty0 */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0 ((uint32_t)(0x7434)) +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco0_FrameDimensions */ +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS ((uint32_t)(0x7438)) +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco0_FrameResampling */ +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING ((uint32_t)(0x743C)) +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco0_Control */ +#define IMXDPUV1_FETCHECO0_CONTROL ((uint32_t)(0x7440)) +#define IMXDPUV1_FETCHECO0_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO0_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO0_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco0_ControlTrigger */ +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER ((uint32_t)(0x7444)) +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_Start */ +#define IMXDPUV1_FETCHECO0_START ((uint32_t)(0x7448)) +#define IMXDPUV1_FETCHECO0_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO0_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO0_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_FetchType */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE ((uint32_t)(0x744C)) +#define IMXDPUV1_FETCHECO0_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO0_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco0_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES ((uint32_t)(0x7450)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco0_HiddenStatus */ +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS ((uint32_t)(0x7454)) +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_LockUnlock */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK ((uint32_t)(0x7800)) +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_FetchDecode1_LockStatus */ +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS ((uint32_t)(0x7804)) +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_StaticControl */ +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL ((uint32_t)(0x7808)) +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_BurstBufferManagement */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT ((uint32_t)(0x780C)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_FetchDecode1_RingBufStartAddr0 */ +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0 ((uint32_t)(0x7810)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_RingBufWrapAddr0 */ +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0 ((uint32_t)(0x7814)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_FrameProperties0 */ +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0 ((uint32_t)(0x7818)) +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_BaseAddress0 */ +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0 ((uint32_t)(0x781C)) +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x7820)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x7824)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ColorComponentBits0 */ +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0 ((uint32_t)(0x7828)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode1_ColorComponentShift0 */ +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0 ((uint32_t)(0x782C)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode1_LayerOffset0 */ +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0 ((uint32_t)(0x7830)) +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0 ((uint32_t)(0x7834)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x7838)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ConstantColor0 */ +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0 ((uint32_t)(0x783C)) +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode1_LayerProperty0 */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0 ((uint32_t)(0x7840)) +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode1_FrameDimensions */ +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS ((uint32_t)(0x7844)) +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode1_FrameResampling */ +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING ((uint32_t)(0x7848)) +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode1_DecodeControl */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL ((uint32_t)(0x784C)) +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression). */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U +/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length. */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RL 0x3U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS_SHIFT 15U +/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U +/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_FetchDecode1_SourceBufferLength */ +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH ((uint32_t)(0x7850)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_Control */ +#define IMXDPUV1_FETCHDECODE1_CONTROL ((uint32_t)(0x7854)) +#define IMXDPUV1_FETCHDECODE1_CONTROL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHDECODE1_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U +/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed + * samples (UV samples between Y samples). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U +/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned + * samples (UV samples at Y sample positions). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHDECODE1_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHDECODE1_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_FetchDecode1_ControlTrigger */ +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER ((uint32_t)(0x7858)) +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_Start */ +#define IMXDPUV1_FETCHDECODE1_START ((uint32_t)(0x785C)) +#define IMXDPUV1_FETCHDECODE1_START_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHDECODE1_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE1_START_START_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_START_START_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_FetchType */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE ((uint32_t)(0x7860)) +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_FetchDecode1_DecoderStatus */ +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS ((uint32_t)(0x7864)) +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U + +/* Register: IMXDPUV1_FetchDecode1_ReadAddress0 */ +#define IMXDPUV1_FETCHDECODE1_READADDRESS0 ((uint32_t)(0x7868)) +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_READADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_BurstBufferProperties */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES ((uint32_t)(0x786C)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_Status */ +#define IMXDPUV1_FETCHDECODE1_STATUS ((uint32_t)(0x7870)) +#define IMXDPUV1_FETCHDECODE1_STATUS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHDECODE1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHDECODE1_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_FetchDecode1_HiddenStatus */ +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS ((uint32_t)(0x7874)) +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_ColorPalette */ +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE ((uint32_t)(0x7C00)) +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_LockUnlock */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK ((uint32_t)(0x8000)) +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco1_LockStatus */ +#define IMXDPUV1_FETCHECO1_LOCKSTATUS ((uint32_t)(0x8004)) +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco1_StaticControl */ +#define IMXDPUV1_FETCHECO1_STATICCONTROL ((uint32_t)(0x8008)) +#define IMXDPUV1_FETCHECO1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT ((uint32_t)(0x800C)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco1_BaseAddress0 */ +#define IMXDPUV1_FETCHECO1_BASEADDRESS0 ((uint32_t)(0x8010)) +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x8014)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x8018)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0 ((uint32_t)(0x801C)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco1_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0 ((uint32_t)(0x8020)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco1_LayerOffset0 */ +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0 ((uint32_t)(0x8024)) +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0 ((uint32_t)(0x8028)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x802C)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ConstantColor0 */ +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0 ((uint32_t)(0x8030)) +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco1_LayerProperty0 */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0 ((uint32_t)(0x8034)) +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco1_FrameDimensions */ +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS ((uint32_t)(0x8038)) +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco1_FrameResampling */ +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING ((uint32_t)(0x803C)) +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco1_Control */ +#define IMXDPUV1_FETCHECO1_CONTROL ((uint32_t)(0x8040)) +#define IMXDPUV1_FETCHECO1_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO1_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO1_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco1_ControlTrigger */ +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER ((uint32_t)(0x8044)) +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_Start */ +#define IMXDPUV1_FETCHECO1_START ((uint32_t)(0x8048)) +#define IMXDPUV1_FETCHECO1_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO1_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO1_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO1_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_FetchType */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE ((uint32_t)(0x804C)) +#define IMXDPUV1_FETCHECO1_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO1_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco1_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES ((uint32_t)(0x8050)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco1_HiddenStatus */ +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS ((uint32_t)(0x8054)) +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_LockUnlock */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK ((uint32_t)(0x8400)) +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetchlayer0_LockStatus */ +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS ((uint32_t)(0x8404)) +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_StaticControl */ +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL ((uint32_t)(0x8408)) +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_RESET_VALUE 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_BurstBufferManagement */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT ((uint32_t)(0x840C)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress0 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0 ((uint32_t)(0x8410)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x8414)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x8418)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits0 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0 ((uint32_t)(0x841C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift0 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0 ((uint32_t)(0x8420)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset0 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0 ((uint32_t)(0x8424)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0 ((uint32_t)(0x8428)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x842C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor0 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0 ((uint32_t)(0x8430)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty0 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0 ((uint32_t)(0x8434)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress1 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1 ((uint32_t)(0x8438)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_BASEADDRESS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_BASEADDRESS1_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes1 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1 ((uint32_t)(0x843C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension1 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1 ((uint32_t)(0x8440)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits1 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1 ((uint32_t)(0x8444)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift1 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1 ((uint32_t)(0x8448)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset1 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1 ((uint32_t)(0x844C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset1 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1 ((uint32_t)(0x8450)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions1 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1 ((uint32_t)(0x8454)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor1 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1 ((uint32_t)(0x8458)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty1 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1 ((uint32_t)(0x845C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PALETTEENABLE1_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PALETTEENABLE1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1_SHIFT 4U +/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U +/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U +/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress2 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2 ((uint32_t)(0x8460)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_BASEADDRESS2_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_BASEADDRESS2_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes2 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2 ((uint32_t)(0x8464)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension2 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2 ((uint32_t)(0x8468)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits2 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2 ((uint32_t)(0x846C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift2 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2 ((uint32_t)(0x8470)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset2 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2 ((uint32_t)(0x8474)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset2 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2 ((uint32_t)(0x8478)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions2 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2 ((uint32_t)(0x847C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor2 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2 ((uint32_t)(0x8480)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty2 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2 ((uint32_t)(0x8484)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PALETTEENABLE2_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PALETTEENABLE2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2_SHIFT 4U +/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U +/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U +/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress3 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3 ((uint32_t)(0x8488)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_BASEADDRESS3_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_BASEADDRESS3_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes3 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3 ((uint32_t)(0x848C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension3 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3 ((uint32_t)(0x8490)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits3 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3 ((uint32_t)(0x8494)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift3 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3 ((uint32_t)(0x8498)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset3 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3 ((uint32_t)(0x849C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset3 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3 ((uint32_t)(0x84A0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions3 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3 ((uint32_t)(0x84A4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor3 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3 ((uint32_t)(0x84A8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty3 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3 ((uint32_t)(0x84AC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PALETTEENABLE3_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PALETTEENABLE3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3_SHIFT 4U +/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U +/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U +/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress4 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4 ((uint32_t)(0x84B0)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_BASEADDRESS4_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_BASEADDRESS4_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes4 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4 ((uint32_t)(0x84B4)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension4 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4 ((uint32_t)(0x84B8)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits4 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4 ((uint32_t)(0x84BC)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift4 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4 ((uint32_t)(0x84C0)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset4 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4 ((uint32_t)(0x84C4)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset4 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4 ((uint32_t)(0x84C8)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions4 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4 ((uint32_t)(0x84CC)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor4 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4 ((uint32_t)(0x84D0)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty4 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4 ((uint32_t)(0x84D4)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PALETTEENABLE4_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PALETTEENABLE4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4_SHIFT 4U +/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U +/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U +/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress5 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5 ((uint32_t)(0x84D8)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_BASEADDRESS5_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_BASEADDRESS5_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes5 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5 ((uint32_t)(0x84DC)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension5 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5 ((uint32_t)(0x84E0)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits5 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5 ((uint32_t)(0x84E4)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift5 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5 ((uint32_t)(0x84E8)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset5 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5 ((uint32_t)(0x84EC)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset5 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5 ((uint32_t)(0x84F0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions5 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5 ((uint32_t)(0x84F4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor5 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5 ((uint32_t)(0x84F8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty5 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5 ((uint32_t)(0x84FC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PALETTEENABLE5_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PALETTEENABLE5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5_SHIFT 4U +/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U +/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U +/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress6 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6 ((uint32_t)(0x8500)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_BASEADDRESS6_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_BASEADDRESS6_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes6 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6 ((uint32_t)(0x8504)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension6 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6 ((uint32_t)(0x8508)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits6 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6 ((uint32_t)(0x850C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift6 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6 ((uint32_t)(0x8510)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset6 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6 ((uint32_t)(0x8514)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset6 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6 ((uint32_t)(0x8518)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions6 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6 ((uint32_t)(0x851C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor6 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6 ((uint32_t)(0x8520)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty6 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6 ((uint32_t)(0x8524)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PALETTEENABLE6_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PALETTEENABLE6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6_SHIFT 4U +/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U +/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U +/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress7 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7 ((uint32_t)(0x8528)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_BASEADDRESS7_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_BASEADDRESS7_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes7 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7 ((uint32_t)(0x852C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension7 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7 ((uint32_t)(0x8530)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits7 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7 ((uint32_t)(0x8534)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift7 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7 ((uint32_t)(0x8538)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset7 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7 ((uint32_t)(0x853C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset7 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7 ((uint32_t)(0x8540)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions7 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7 ((uint32_t)(0x8544)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor7 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7 ((uint32_t)(0x8548)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty7 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7 ((uint32_t)(0x854C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PALETTEENABLE7_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PALETTEENABLE7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7_SHIFT 4U +/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U +/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U +/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_FrameDimensions */ +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS ((uint32_t)(0x8550)) +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_FrameResampling */ +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING ((uint32_t)(0x8554)) +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_Control */ +#define IMXDPUV1_FETCHLAYER0_CONTROL ((uint32_t)(0x8558)) +#define IMXDPUV1_FETCHLAYER0_CONTROL_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_FETCHLAYER0_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHLAYER0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHLAYER0_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHLAYER0_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHLAYER0_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR__LAYER 0x1U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPLAYER_MASK 0xE0000U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPLAYER_SHIFT 17U + +/* Register: IMXDPUV1_fetchlayer0_TriggerEnable */ +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE ((uint32_t)(0x855C)) +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_ControlTrigger */ +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER ((uint32_t)(0x8560)) +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_Start */ +#define IMXDPUV1_FETCHLAYER0_START ((uint32_t)(0x8564)) +#define IMXDPUV1_FETCHLAYER0_START_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_FETCHLAYER0_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHLAYER0_START_START_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_FetchType */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE ((uint32_t)(0x8568)) +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetchlayer0_BurstBufferProperties */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES ((uint32_t)(0x856C)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_Status */ +#define IMXDPUV1_FETCHLAYER0_STATUS ((uint32_t)(0x8570)) +#define IMXDPUV1_FETCHLAYER0_STATUS_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_FETCHLAYER0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHLAYER0_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_fetchlayer0_HiddenStatus */ +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS ((uint32_t)(0x8574)) +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_ColorPalette */ +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE ((uint32_t)(0x8800)) +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_matrix4_LockUnlock */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK ((uint32_t)(0x8C00)) +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix4_LockStatus */ +#define IMXDPUV1_MATRIX4_LOCKSTATUS ((uint32_t)(0x8C04)) +#define IMXDPUV1_MATRIX4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix4_StaticControl */ +#define IMXDPUV1_MATRIX4_STATICCONTROL ((uint32_t)(0x8C08)) +#define IMXDPUV1_MATRIX4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix4_Control */ +#define IMXDPUV1_MATRIX4_CONTROL ((uint32_t)(0x8C0C)) +#define IMXDPUV1_MATRIX4_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX4_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX4_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix4_Red0 */ +#define IMXDPUV1_MATRIX4_RED0 ((uint32_t)(0x8C10)) +#define IMXDPUV1_MATRIX4_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX4_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX4_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX4_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Red1 */ +#define IMXDPUV1_MATRIX4_RED1 ((uint32_t)(0x8C14)) +#define IMXDPUV1_MATRIX4_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX4_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX4_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Green0 */ +#define IMXDPUV1_MATRIX4_GREEN0 ((uint32_t)(0x8C18)) +#define IMXDPUV1_MATRIX4_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX4_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX4_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX4_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Green1 */ +#define IMXDPUV1_MATRIX4_GREEN1 ((uint32_t)(0x8C1C)) +#define IMXDPUV1_MATRIX4_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX4_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX4_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Blue0 */ +#define IMXDPUV1_MATRIX4_BLUE0 ((uint32_t)(0x8C20)) +#define IMXDPUV1_MATRIX4_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX4_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX4_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Blue1 */ +#define IMXDPUV1_MATRIX4_BLUE1 ((uint32_t)(0x8C24)) +#define IMXDPUV1_MATRIX4_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX4_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX4_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX4_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Alpha0 */ +#define IMXDPUV1_MATRIX4_ALPHA0 ((uint32_t)(0x8C28)) +#define IMXDPUV1_MATRIX4_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX4_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX4_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Alpha1 */ +#define IMXDPUV1_MATRIX4_ALPHA1 ((uint32_t)(0x8C2C)) +#define IMXDPUV1_MATRIX4_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX4_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX4_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX4_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_OffsetVector0 */ +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0 ((uint32_t)(0x8C30)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_OffsetVector1 */ +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1 ((uint32_t)(0x8C34)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_LastControlWord */ +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD ((uint32_t)(0x8C38)) +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_LockUnlock */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK ((uint32_t)(0x9000)) +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_hscaler4_LockStatus */ +#define IMXDPUV1_HSCALER4_LOCKSTATUS ((uint32_t)(0x9004)) +#define IMXDPUV1_HSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_HSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_hscaler4_StaticControl */ +#define IMXDPUV1_HSCALER4_STATICCONTROL ((uint32_t)(0x9008)) +#define IMXDPUV1_HSCALER4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_HSCALER4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_HSCALER4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_Setup1 */ +#define IMXDPUV1_HSCALER4_SETUP1 ((uint32_t)(0x900C)) +#define IMXDPUV1_HSCALER4_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_HSCALER4_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_HSCALER4_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_HSCALER4_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_Setup2 */ +#define IMXDPUV1_HSCALER4_SETUP2 ((uint32_t)(0x9010)) +#define IMXDPUV1_HSCALER4_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_HSCALER4_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_HSCALER4_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_Control */ +#define IMXDPUV1_HSCALER4_CONTROL ((uint32_t)(0x9014)) +#define IMXDPUV1_HSCALER4_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_HSCALER4_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_HSCALER4_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_HSCALER4_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size) */ +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_HSCALER4_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_vscaler4_LockUnlock */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK ((uint32_t)(0x9400)) +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_vscaler4_LockStatus */ +#define IMXDPUV1_VSCALER4_LOCKSTATUS ((uint32_t)(0x9404)) +#define IMXDPUV1_VSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_VSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_vscaler4_StaticControl */ +#define IMXDPUV1_VSCALER4_STATICCONTROL ((uint32_t)(0x9408)) +#define IMXDPUV1_VSCALER4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_VSCALER4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_VSCALER4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup1 */ +#define IMXDPUV1_VSCALER4_SETUP1 ((uint32_t)(0x940C)) +#define IMXDPUV1_VSCALER4_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_VSCALER4_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_VSCALER4_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_VSCALER4_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup2 */ +#define IMXDPUV1_VSCALER4_SETUP2 ((uint32_t)(0x9410)) +#define IMXDPUV1_VSCALER4_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_VSCALER4_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup3 */ +#define IMXDPUV1_VSCALER4_SETUP3 ((uint32_t)(0x9414)) +#define IMXDPUV1_VSCALER4_SETUP3_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_VSCALER4_SETUP3_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP3_PHASE_OFFSET1_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP3_PHASE_OFFSET1_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup4 */ +#define IMXDPUV1_VSCALER4_SETUP4 ((uint32_t)(0x9418)) +#define IMXDPUV1_VSCALER4_SETUP4_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_VSCALER4_SETUP4_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP4_PHASE_OFFSET2_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP4_PHASE_OFFSET2_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup5 */ +#define IMXDPUV1_VSCALER4_SETUP5 ((uint32_t)(0x941C)) +#define IMXDPUV1_VSCALER4_SETUP5_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_VSCALER4_SETUP5_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP5_PHASE_OFFSET3_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP5_PHASE_OFFSET3_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Control */ +#define IMXDPUV1_VSCALER4_CONTROL ((uint32_t)(0x9420)) +#define IMXDPUV1_VSCALER4_CONTROL_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_VSCALER4_CONTROL_RESET_VALUE 0x2000U +#define IMXDPUV1_VSCALER4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_VSCALER4_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_VSCALER4_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size). */ +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE_MASK 0x3000U +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE_SHIFT 12U +/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__ALWAYS0 0U +/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__ALWAYS1 0x1U +/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input + * field polarity. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__INPUT 0x2U +/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting + * with 0 after reset. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__TOGGLE 0x3U +#define IMXDPUV1_VSCALER4_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_VSCALER4_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_LockUnlock */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK ((uint32_t)(0x9800)) +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix5_LockStatus */ +#define IMXDPUV1_MATRIX5_LOCKSTATUS ((uint32_t)(0x9804)) +#define IMXDPUV1_MATRIX5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix5_StaticControl */ +#define IMXDPUV1_MATRIX5_STATICCONTROL ((uint32_t)(0x9808)) +#define IMXDPUV1_MATRIX5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix5_Control */ +#define IMXDPUV1_MATRIX5_CONTROL ((uint32_t)(0x980C)) +#define IMXDPUV1_MATRIX5_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX5_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX5_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix5_Red0 */ +#define IMXDPUV1_MATRIX5_RED0 ((uint32_t)(0x9810)) +#define IMXDPUV1_MATRIX5_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX5_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX5_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX5_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Red1 */ +#define IMXDPUV1_MATRIX5_RED1 ((uint32_t)(0x9814)) +#define IMXDPUV1_MATRIX5_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX5_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX5_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Green0 */ +#define IMXDPUV1_MATRIX5_GREEN0 ((uint32_t)(0x9818)) +#define IMXDPUV1_MATRIX5_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX5_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX5_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX5_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Green1 */ +#define IMXDPUV1_MATRIX5_GREEN1 ((uint32_t)(0x981C)) +#define IMXDPUV1_MATRIX5_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX5_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX5_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Blue0 */ +#define IMXDPUV1_MATRIX5_BLUE0 ((uint32_t)(0x9820)) +#define IMXDPUV1_MATRIX5_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX5_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX5_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Blue1 */ +#define IMXDPUV1_MATRIX5_BLUE1 ((uint32_t)(0x9824)) +#define IMXDPUV1_MATRIX5_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX5_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX5_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX5_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Alpha0 */ +#define IMXDPUV1_MATRIX5_ALPHA0 ((uint32_t)(0x9828)) +#define IMXDPUV1_MATRIX5_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX5_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX5_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Alpha1 */ +#define IMXDPUV1_MATRIX5_ALPHA1 ((uint32_t)(0x982C)) +#define IMXDPUV1_MATRIX5_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX5_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX5_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX5_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_OffsetVector0 */ +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0 ((uint32_t)(0x9830)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_OffsetVector1 */ +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1 ((uint32_t)(0x9834)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_LastControlWord */ +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD ((uint32_t)(0x9838)) +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_LockUnlock */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK ((uint32_t)(0x9C00)) +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_hscaler5_LockStatus */ +#define IMXDPUV1_HSCALER5_LOCKSTATUS ((uint32_t)(0x9C04)) +#define IMXDPUV1_HSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_HSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_hscaler5_StaticControl */ +#define IMXDPUV1_HSCALER5_STATICCONTROL ((uint32_t)(0x9C08)) +#define IMXDPUV1_HSCALER5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_HSCALER5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_HSCALER5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_Setup1 */ +#define IMXDPUV1_HSCALER5_SETUP1 ((uint32_t)(0x9C0C)) +#define IMXDPUV1_HSCALER5_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_HSCALER5_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_HSCALER5_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_HSCALER5_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_Setup2 */ +#define IMXDPUV1_HSCALER5_SETUP2 ((uint32_t)(0x9C10)) +#define IMXDPUV1_HSCALER5_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_HSCALER5_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_HSCALER5_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_Control */ +#define IMXDPUV1_HSCALER5_CONTROL ((uint32_t)(0x9C14)) +#define IMXDPUV1_HSCALER5_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_HSCALER5_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_HSCALER5_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_HSCALER5_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size) */ +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_HSCALER5_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_vscaler5_LockUnlock */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK ((uint32_t)(0xA000)) +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_vscaler5_LockStatus */ +#define IMXDPUV1_VSCALER5_LOCKSTATUS ((uint32_t)(0xA004)) +#define IMXDPUV1_VSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_VSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_vscaler5_StaticControl */ +#define IMXDPUV1_VSCALER5_STATICCONTROL ((uint32_t)(0xA008)) +#define IMXDPUV1_VSCALER5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_VSCALER5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_VSCALER5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup1 */ +#define IMXDPUV1_VSCALER5_SETUP1 ((uint32_t)(0xA00C)) +#define IMXDPUV1_VSCALER5_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_VSCALER5_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_VSCALER5_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_VSCALER5_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup2 */ +#define IMXDPUV1_VSCALER5_SETUP2 ((uint32_t)(0xA010)) +#define IMXDPUV1_VSCALER5_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_VSCALER5_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup3 */ +#define IMXDPUV1_VSCALER5_SETUP3 ((uint32_t)(0xA014)) +#define IMXDPUV1_VSCALER5_SETUP3_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_VSCALER5_SETUP3_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP3_PHASE_OFFSET1_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP3_PHASE_OFFSET1_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup4 */ +#define IMXDPUV1_VSCALER5_SETUP4 ((uint32_t)(0xA018)) +#define IMXDPUV1_VSCALER5_SETUP4_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_VSCALER5_SETUP4_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP4_PHASE_OFFSET2_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP4_PHASE_OFFSET2_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup5 */ +#define IMXDPUV1_VSCALER5_SETUP5 ((uint32_t)(0xA01C)) +#define IMXDPUV1_VSCALER5_SETUP5_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_VSCALER5_SETUP5_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP5_PHASE_OFFSET3_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP5_PHASE_OFFSET3_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Control */ +#define IMXDPUV1_VSCALER5_CONTROL ((uint32_t)(0xA020)) +#define IMXDPUV1_VSCALER5_CONTROL_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_VSCALER5_CONTROL_RESET_VALUE 0x2000U +#define IMXDPUV1_VSCALER5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_VSCALER5_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_VSCALER5_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size). */ +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE_MASK 0x3000U +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE_SHIFT 12U +/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__ALWAYS0 0U +/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__ALWAYS1 0x1U +/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input + * field polarity. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__INPUT 0x2U +/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting + * with 0 after reset. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__TOGGLE 0x3U +#define IMXDPUV1_VSCALER5_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_VSCALER5_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_layerblend0_LockUnlock */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK ((uint32_t)(0xA400)) +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend0_LockStatus */ +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS ((uint32_t)(0xA404)) +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend0_StaticControl */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL ((uint32_t)(0xA408)) +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend0_Control */ +#define IMXDPUV1_LAYERBLEND0_CONTROL ((uint32_t)(0xA40C)) +#define IMXDPUV1_LAYERBLEND0_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND0_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend0_BlendControl */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL ((uint32_t)(0xA410)) +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend0_Position */ +#define IMXDPUV1_LAYERBLEND0_POSITION ((uint32_t)(0xA414)) +#define IMXDPUV1_LAYERBLEND0_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND0_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND0_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND0_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND0_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend0_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD ((uint32_t)(0xA418)) +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend0_SecControlWord */ +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD ((uint32_t)(0xA41C)) +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend1_LockUnlock */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK ((uint32_t)(0xA800)) +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend1_LockStatus */ +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS ((uint32_t)(0xA804)) +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend1_StaticControl */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL ((uint32_t)(0xA808)) +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend1_Control */ +#define IMXDPUV1_LAYERBLEND1_CONTROL ((uint32_t)(0xA80C)) +#define IMXDPUV1_LAYERBLEND1_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND1_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend1_BlendControl */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL ((uint32_t)(0xA810)) +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend1_Position */ +#define IMXDPUV1_LAYERBLEND1_POSITION ((uint32_t)(0xA814)) +#define IMXDPUV1_LAYERBLEND1_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND1_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND1_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND1_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND1_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend1_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD ((uint32_t)(0xA818)) +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend1_SecControlWord */ +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD ((uint32_t)(0xA81C)) +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend2_LockUnlock */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK ((uint32_t)(0xAC00)) +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend2_LockStatus */ +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS ((uint32_t)(0xAC04)) +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend2_StaticControl */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL ((uint32_t)(0xAC08)) +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend2_Control */ +#define IMXDPUV1_LAYERBLEND2_CONTROL ((uint32_t)(0xAC0C)) +#define IMXDPUV1_LAYERBLEND2_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND2_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend2_BlendControl */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL ((uint32_t)(0xAC10)) +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend2_Position */ +#define IMXDPUV1_LAYERBLEND2_POSITION ((uint32_t)(0xAC14)) +#define IMXDPUV1_LAYERBLEND2_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND2_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND2_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND2_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND2_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend2_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD ((uint32_t)(0xAC18)) +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend2_SecControlWord */ +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD ((uint32_t)(0xAC1C)) +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend3_LockUnlock */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK ((uint32_t)(0xB000)) +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend3_LockStatus */ +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS ((uint32_t)(0xB004)) +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend3_StaticControl */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL ((uint32_t)(0xB008)) +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend3_Control */ +#define IMXDPUV1_LAYERBLEND3_CONTROL ((uint32_t)(0xB00C)) +#define IMXDPUV1_LAYERBLEND3_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND3_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend3_BlendControl */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL ((uint32_t)(0xB010)) +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend3_Position */ +#define IMXDPUV1_LAYERBLEND3_POSITION ((uint32_t)(0xB014)) +#define IMXDPUV1_LAYERBLEND3_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND3_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND3_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND3_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND3_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend3_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD ((uint32_t)(0xB018)) +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend3_SecControlWord */ +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD ((uint32_t)(0xB01C)) +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_disengcfg_LockUnlock0 */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0 ((uint32_t)(0xB400)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_RESET_MASK 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0_SHIFT 0U +/* Field Value: LOCKUNLOCK0__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK0__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK0__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK0__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK0__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_disengcfg_LockStatus0 */ +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0 ((uint32_t)(0xB404)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_LOCKSTATUS0_MASK 0x1U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_LOCKSTATUS0_SHIFT 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_PRIVILEGESTATUS0_MASK 0x10U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_PRIVILEGESTATUS0_SHIFT 4U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_FREEZESTATUS0_MASK 0x100U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_FREEZESTATUS0_SHIFT 8U + +/* Register: IMXDPUV1_disengcfg_ClockCtrl0 */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0 ((uint32_t)(0xB408)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_RESET_VALUE 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0_MASK 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0_SHIFT 0U +/* Field Value: DSPCLKDIVIDE0__DIV1, External display clock signal has pixel + * clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0__DIV1 0U +/* Field Value: DSPCLKDIVIDE0__DIV2, External display clock signal has twice + * the pixel clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0__DIV2 0x1U + +/* Register: IMXDPUV1_disengcfg_PolarityCtrl0 */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0 ((uint32_t)(0xB40C)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_RESET_VALUE 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0_MASK 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0_SHIFT 0U +/* Field Value: POLHS0__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__LOW 0U +/* Field Value: POLHS0__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0_MASK 0x2U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0_SHIFT 1U +/* Field Value: POLVS0__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__LOW 0U +/* Field Value: POLVS0__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0_MASK 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0_SHIFT 2U +/* Field Value: POLEN0__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__LOW 0U +/* Field Value: POLEN0__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0_MASK 0x8U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0_SHIFT 3U +/* Field Value: PIXINV0__NONINV, No inversion of pixel data */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0__NONINV 0U +/* Field Value: PIXINV0__INV, Pixel data inverted (1. complement) */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0__INV 0x1U + +/* Register: IMXDPUV1_disengcfg_SrcSelect0 */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0 ((uint32_t)(0xB410)) +#define IMXDPUV1_DISENGCFG_SRCSELECT0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DISENGCFG_SRCSELECT0_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0_MASK 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0_SHIFT 0U +/* Field Value: SIG_SELECT0__FRAMEGEN, Source is FrameGen#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__FRAMEGEN 0U +/* Field Value: SIG_SELECT0__GAMMACOR, Source is GammaCor#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__GAMMACOR 0x1U +/* Field Value: SIG_SELECT0__MATRIX, Source is Matrix#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__MATRIX 0x2U +/* Field Value: SIG_SELECT0__DITHER, Source is Dither#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0_MASK 0x10U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0_SHIFT 4U +/* Field Value: PATH_SELECT0__GAMMA_FIRST, Framegen - Gamma - Matrix - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0__GAMMA_FIRST 0U +/* Field Value: PATH_SELECT0__MATRIX_FIRST, Framegen - Matrix - Gamma - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0__MATRIX_FIRST 0x1U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0_MASK 0x300U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0_SHIFT 8U +/* Field Value: DUMP0_SELECT0__FRAMEGEN, Source is FrameGen#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__FRAMEGEN 0U +/* Field Value: DUMP0_SELECT0__GAMMACOR, Source is GammaCor#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__GAMMACOR 0x1U +/* Field Value: DUMP0_SELECT0__MATRIX, Source is Matrix#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__MATRIX 0x2U +/* Field Value: DUMP0_SELECT0__DITHER, Source is Dither#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0_MASK 0xC00U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0_SHIFT 10U +/* Field Value: DUMP1_SELECT0__FRAMEGEN, Source is FrameGen#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__FRAMEGEN 0U +/* Field Value: DUMP1_SELECT0__GAMMACOR, Source is GammaCor#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__GAMMACOR 0x1U +/* Field Value: DUMP1_SELECT0__MATRIX, Source is Matrix#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__MATRIX 0x2U +/* Field Value: DUMP1_SELECT0__DITHER, Source is Dither#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__DITHER 0x3U + +/* Register: IMXDPUV1_disengcfg_LockUnlock1 */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1 ((uint32_t)(0xB420)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_RESET_MASK 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1_SHIFT 0U +/* Field Value: LOCKUNLOCK1__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK1__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK1__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK1__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK1__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_disengcfg_LockStatus1 */ +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1 ((uint32_t)(0xB424)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_LOCKSTATUS1_MASK 0x1U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_LOCKSTATUS1_SHIFT 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_PRIVILEGESTATUS1_MASK 0x10U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_PRIVILEGESTATUS1_SHIFT 4U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_FREEZESTATUS1_MASK 0x100U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_FREEZESTATUS1_SHIFT 8U + +/* Register: IMXDPUV1_disengcfg_ClockCtrl1 */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1 ((uint32_t)(0xB428)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_RESET_VALUE 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1_MASK 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1_SHIFT 0U +/* Field Value: DSPCLKDIVIDE1__DIV1, External display clock signal has pixel + * clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1__DIV1 0U +/* Field Value: DSPCLKDIVIDE1__DIV2, External display clock signal has twice + * the pixel clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1__DIV2 0x1U + +/* Register: IMXDPUV1_disengcfg_PolarityCtrl1 */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1 ((uint32_t)(0xB42C)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_RESET_VALUE 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1_MASK 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1_SHIFT 0U +/* Field Value: POLHS1__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__LOW 0U +/* Field Value: POLHS1__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1_MASK 0x2U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1_SHIFT 1U +/* Field Value: POLVS1__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__LOW 0U +/* Field Value: POLVS1__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1_MASK 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1_SHIFT 2U +/* Field Value: POLEN1__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__LOW 0U +/* Field Value: POLEN1__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1_MASK 0x8U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1_SHIFT 3U +/* Field Value: PIXINV1__NONINV, No inversion of pixel data */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1__NONINV 0U +/* Field Value: PIXINV1__INV, Pixel data inverted (1. complement) */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1__INV 0x1U + +/* Register: IMXDPUV1_disengcfg_SrcSelect1 */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1 ((uint32_t)(0xB430)) +#define IMXDPUV1_DISENGCFG_SRCSELECT1_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_DISENGCFG_SRCSELECT1_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1_MASK 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1_SHIFT 0U +/* Field Value: SIG_SELECT1__FRAMEGEN, Source is FrameGen#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__FRAMEGEN 0U +/* Field Value: SIG_SELECT1__GAMMACOR, Source is GammaCor#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__GAMMACOR 0x1U +/* Field Value: SIG_SELECT1__MATRIX, Source is Matrix#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__MATRIX 0x2U +/* Field Value: SIG_SELECT1__DITHER, Source is Dither#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1_MASK 0x10U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1_SHIFT 4U +/* Field Value: PATH_SELECT1__GAMMA_FIRST, Framegen - Gamma - Matrix - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1__GAMMA_FIRST 0U +/* Field Value: PATH_SELECT1__MATRIX_FIRST, Framegen - Matrix - Gamma - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1__MATRIX_FIRST 0x1U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1_MASK 0x300U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1_SHIFT 8U +/* Field Value: DUMP0_SELECT1__FRAMEGEN, Source is FrameGen#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__FRAMEGEN 0U +/* Field Value: DUMP0_SELECT1__GAMMACOR, Source is GammaCor#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__GAMMACOR 0x1U +/* Field Value: DUMP0_SELECT1__MATRIX, Source is Matrix#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__MATRIX 0x2U +/* Field Value: DUMP0_SELECT1__DITHER, Source is Dither#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1_MASK 0xC00U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1_SHIFT 10U +/* Field Value: DUMP1_SELECT1__FRAMEGEN, Source is FrameGen#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__FRAMEGEN 0U +/* Field Value: DUMP1_SELECT1__GAMMACOR, Source is GammaCor#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__GAMMACOR 0x1U +/* Field Value: DUMP1_SELECT1__MATRIX, Source is Matrix#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__MATRIX 0x2U +/* Field Value: DUMP1_SELECT1__DITHER, Source is Dither#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__DITHER 0x3U + +/* Register: IMXDPUV1_framegen0_LockUnlock */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK ((uint32_t)(0xB800)) +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_framegen0_LockStatus */ +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS ((uint32_t)(0xB804)) +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_framegen0_FgStCtrl */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL ((uint32_t)(0xB808)) +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_SHDEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_SHDEN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE_SHIFT 1U +/* Field Value: FGSYNCMODE__OFF, No side-by-side synchronization. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__OFF 0U +/* Field Value: FGSYNCMODE__MASTER, Framegen is master. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__MASTER 0x1U +/* Field Value: FGSYNCMODE__SLAVE_CYC, Framegen is slave. Runs in cyclic synchronization + * mode. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__SLAVE_CYC 0x2U +/* Field Value: FGSYNCMODE__SLAVE_ONCE, Framegen is slave. Runs in one time + * synchronization mode. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__SLAVE_ONCE 0x3U + +/* Register: IMXDPUV1_framegen0_HtCfg1 */ +#define IMXDPUV1_FRAMEGEN0_HTCFG1 ((uint32_t)(0xB80C)) +#define IMXDPUV1_FRAMEGEN0_HTCFG1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FRAMEGEN0_HTCFG1_RESET_VALUE 0x18F0140U +#define IMXDPUV1_FRAMEGEN0_HTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_HtCfg2 */ +#define IMXDPUV1_FRAMEGEN0_HTCFG2 ((uint32_t)(0xB810)) +#define IMXDPUV1_FRAMEGEN0_HTCFG2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FRAMEGEN0_HTCFG2_RESET_VALUE 0x8047001FU +#define IMXDPUV1_FRAMEGEN0_HTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_VtCfg1 */ +#define IMXDPUV1_FRAMEGEN0_VTCFG1 ((uint32_t)(0xB814)) +#define IMXDPUV1_FRAMEGEN0_VTCFG1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FRAMEGEN0_VTCFG1_RESET_VALUE 0xFC00F0U +#define IMXDPUV1_FRAMEGEN0_VTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_VtCfg2 */ +#define IMXDPUV1_FRAMEGEN0_VTCFG2 ((uint32_t)(0xB818)) +#define IMXDPUV1_FRAMEGEN0_VTCFG2_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FRAMEGEN0_VTCFG2_RESET_VALUE 0x80090003U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int0Config */ +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG ((uint32_t)(0xB81C)) +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int1Config */ +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG ((uint32_t)(0xB820)) +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int2Config */ +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG ((uint32_t)(0xB824)) +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int3Config */ +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG ((uint32_t)(0xB828)) +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_PKickConfig */ +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG ((uint32_t)(0xB82C)) +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKINT0EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKINT0EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_SKickConfig */ +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG ((uint32_t)(0xB830)) +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG_SHIFT 30U +/* Field Value: SKICKTRIG__INTERNAL, Use internal skick signal, trigger point + * defined by SKickRow and SKickCol. */ +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG__INTERNAL 0U +/* Field Value: SKICKTRIG__EXTERNAL, Use external skick input as trigger. */ +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG__EXTERNAL 0x1U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_SecStatConfig */ +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG ((uint32_t)(0xB834)) +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_RESET_VALUE 0x112U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVGOODFRAMES_MASK 0xFU +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVGOODFRAMES_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVBADFRAMES_MASK 0xF0U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVBADFRAMES_SHIFT 4U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVSKEWINRANGE_MASK 0xF00U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVSKEWINRANGE_SHIFT 8U + +/* Register: IMXDPUV1_framegen0_FgSRCR1 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1 ((uint32_t)(0xB838)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE_SHIFT 1U +/* Field Value: SRMODE__OFF, Skew Regulation is off. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__OFF 0U +/* Field Value: SRMODE__HREG, Horizontal regulation enabled. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__HREG 0x1U +/* Field Value: SRMODE__VREG, Vertical regulation enabled. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__VREG 0x2U +/* Field Value: SRMODE__BOTH, Both regulation modes are enabled. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__BOTH 0x3U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRADJ_MASK 0x8U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRADJ_SHIFT 3U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREVEN_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREVEN_SHIFT 4U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRFASTSYNC_MASK 0x20U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRFASTSYNC_SHIFT 5U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQALIGN_MASK 0x40U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQALIGN_SHIFT 6U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL_MASK 0x180U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL_SHIFT 7U +/* Field Value: SRQVAL__ZERO, Fixed two LSB values of HTOTAL are 0b00. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__ZERO 0U +/* Field Value: SRQVAL__ONE, Fixed two LSB values of HTOTAL are 0b01. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__ONE 0x1U +/* Field Value: SRQVAL__TWO, Fixed two LSB values of HTOTAL are 0b10. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__TWO 0x2U +/* Field Value: SRQVAL__THREE, Fixed two LSB values of HTOTAL are 0b11. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__THREE 0x3U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRDBGDISP_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRDBGDISP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREPOFF_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREPOFF_SHIFT 17U + +/* Register: IMXDPUV1_framegen0_FgSRCR2 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR2 ((uint32_t)(0xB83C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_RESET_VALUE 0x1B70188U +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgSRCR3 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR3 ((uint32_t)(0xB840)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_RESET_VALUE 0x11500FBU +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgSRCR4 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR4 ((uint32_t)(0xB844)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_RESET_VALUE 0xC8U +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_TARGETSKEW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_TARGETSKEW_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSRCR5 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR5 ((uint32_t)(0xB848)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_SYNCRANGELOW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_SYNCRANGELOW_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSRCR6 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR6 ((uint32_t)(0xB84C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_RESET_VALUE 0x190U +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_SYNCRANGEHIGH_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_SYNCRANGEHIGH_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgKSDR */ +#define IMXDPUV1_FRAMEGEN0_FGKSDR ((uint32_t)(0xB850)) +#define IMXDPUV1_FRAMEGEN0_FGKSDR_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FRAMEGEN0_FGKSDR_RESET_VALUE 0x20002U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGKSDR_PCNTCPLMAX_MASK 0x7U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_PCNTCPLMAX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_SCNTCPLMAX_MASK 0x70000U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_SCNTCPLMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_PaCfg */ +#define IMXDPUV1_FRAMEGEN0_PACFG ((uint32_t)(0xB854)) +#define IMXDPUV1_FRAMEGEN0_PACFG_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FRAMEGEN0_PACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN0_PACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_SaCfg */ +#define IMXDPUV1_FRAMEGEN0_SACFG ((uint32_t)(0xB858)) +#define IMXDPUV1_FRAMEGEN0_SACFG_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FRAMEGEN0_SACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN0_SACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgInCtrl */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL ((uint32_t)(0xB85C)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_RESET_VALUE 0x6U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM_MASK 0x7U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM_SHIFT 0U +/* Field Value: FGDM__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__BLACK 0U +/* Field Value: FGDM__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__CONSTCOL 0x1U +/* Field Value: FGDM__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__PRIM 0x2U +/* Field Value: FGDM__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC 0x3U +/* Field Value: FGDM__PRIM_ON_TOP, Both inputs overlaid with primary on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__PRIM_ON_TOP 0x4U +/* Field Value: FGDM__SEC_ON_TOP, Both inputs overlaid with secondary on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC_ON_TOP 0x5U +/* Field Value: FGDM__TEST, White color background with test pattern is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__TEST 0x6U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA_MASK 0x8U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA_SHIFT 3U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA_SHIFT 4U + +/* Register: IMXDPUV1_framegen0_FgInCtrlPanic */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC ((uint32_t)(0xB860)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC_MASK 0x7U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC_SHIFT 0U +/* Field Value: FGDMPANIC__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__BLACK 0U +/* Field Value: FGDMPANIC__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__CONSTCOL 0x1U +/* Field Value: FGDMPANIC__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__PRIM 0x2U +/* Field Value: FGDMPANIC__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__SEC 0x3U +/* Field Value: FGDMPANIC__PRIM_ON_TOP, Both inputs overlaid with primary + * on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__PRIM_ON_TOP 0x4U +/* Field Value: FGDMPANIC__SEC_ON_TOP, Both inputs overlaid with secondary + * on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__SEC_ON_TOP 0x5U +/* Field Value: FGDMPANIC__TEST, White color background with test pattern + * is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__TEST 0x6U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC_MASK 0x8U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC_SHIFT 3U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC_SHIFT 4U + +/* Register: IMXDPUV1_framegen0_FgCCR */ +#define IMXDPUV1_FRAMEGEN0_FGCCR ((uint32_t)(0xB864)) +#define IMXDPUV1_FRAMEGEN0_FGCCR_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FRAMEGEN0_FGCCR_RESET_VALUE 0x7FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCCR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE_MASK 0x3FFU +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN_MASK 0xFFC00U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN_SHIFT 10U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCRED_MASK 0x3FF00000U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCRED_SHIFT 20U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA_SHIFT 30U + +/* Register: IMXDPUV1_framegen0_FgEnable */ +#define IMXDPUV1_FRAMEGEN0_FGENABLE ((uint32_t)(0xB868)) +#define IMXDPUV1_FRAMEGEN0_FGENABLE_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FRAMEGEN0_FGENABLE_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSlr */ +#define IMXDPUV1_FRAMEGEN0_FGSLR ((uint32_t)(0xB86C)) +#define IMXDPUV1_FRAMEGEN0_FGSLR_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FRAMEGEN0_FGSLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSLR_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSLR_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgEnSts */ +#define IMXDPUV1_FRAMEGEN0_FGENSTS ((uint32_t)(0xB870)) +#define IMXDPUV1_FRAMEGEN0_FGENSTS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FRAMEGEN0_FGENSTS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGENSTS_ENSTS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_ENSTS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_PANICSTAT_MASK 0x2U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_PANICSTAT_SHIFT 1U + +/* Register: IMXDPUV1_framegen0_FgTimeStamp */ +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP ((uint32_t)(0xB874)) +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX_MASK 0xFFFFC000U +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX_SHIFT 14U + +/* Register: IMXDPUV1_framegen0_FgChStat */ +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT ((uint32_t)(0xB878)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT_MASK 0x100U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT_SHIFT 8U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR_SHIFT 17U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT_MASK 0x1000000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT_SHIFT 24U + +/* Register: IMXDPUV1_framegen0_FgChStatClr */ +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR ((uint32_t)(0xB87C)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgSkewMon */ +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON ((uint32_t)(0xB880)) +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_SKEWMON_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_SKEWMON_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSFifoMin */ +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN ((uint32_t)(0xB884)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_SFIFOMIN_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_SFIFOMIN_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSFifoMax */ +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX ((uint32_t)(0xB888)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_SFIFOMAX_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_SFIFOMAX_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSFifoFillClr */ +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR ((uint32_t)(0xB88C)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_SFIFOFILLCLR_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_SFIFOFILLCLR_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSrEpD */ +#define IMXDPUV1_FRAMEGEN0_FGSREPD ((uint32_t)(0xB890)) +#define IMXDPUV1_FRAMEGEN0_FGSREPD_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FRAMEGEN0_FGSREPD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSREPD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSREPD_EPVAL_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSREPD_EPVAL_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSrFtD */ +#define IMXDPUV1_FRAMEGEN0_FGSRFTD ((uint32_t)(0xB894)) +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_FRTOT_MASK 0xFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_FRTOT_SHIFT 0U + +/* Register: IMXDPUV1_matrix0_LockUnlock */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK ((uint32_t)(0xBC00)) +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix0_LockStatus */ +#define IMXDPUV1_MATRIX0_LOCKSTATUS ((uint32_t)(0xBC04)) +#define IMXDPUV1_MATRIX0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix0_StaticControl */ +#define IMXDPUV1_MATRIX0_STATICCONTROL ((uint32_t)(0xBC08)) +#define IMXDPUV1_MATRIX0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX0_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix0_Control */ +#define IMXDPUV1_MATRIX0_CONTROL ((uint32_t)(0xBC0C)) +#define IMXDPUV1_MATRIX0_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix0_Red0 */ +#define IMXDPUV1_MATRIX0_RED0 ((uint32_t)(0xBC10)) +#define IMXDPUV1_MATRIX0_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX0_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX0_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX0_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Red1 */ +#define IMXDPUV1_MATRIX0_RED1 ((uint32_t)(0xBC14)) +#define IMXDPUV1_MATRIX0_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX0_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX0_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Green0 */ +#define IMXDPUV1_MATRIX0_GREEN0 ((uint32_t)(0xBC18)) +#define IMXDPUV1_MATRIX0_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX0_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX0_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX0_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Green1 */ +#define IMXDPUV1_MATRIX0_GREEN1 ((uint32_t)(0xBC1C)) +#define IMXDPUV1_MATRIX0_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX0_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX0_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Blue0 */ +#define IMXDPUV1_MATRIX0_BLUE0 ((uint32_t)(0xBC20)) +#define IMXDPUV1_MATRIX0_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX0_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX0_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Blue1 */ +#define IMXDPUV1_MATRIX0_BLUE1 ((uint32_t)(0xBC24)) +#define IMXDPUV1_MATRIX0_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX0_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX0_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX0_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Alpha0 */ +#define IMXDPUV1_MATRIX0_ALPHA0 ((uint32_t)(0xBC28)) +#define IMXDPUV1_MATRIX0_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX0_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX0_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Alpha1 */ +#define IMXDPUV1_MATRIX0_ALPHA1 ((uint32_t)(0xBC2C)) +#define IMXDPUV1_MATRIX0_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX0_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX0_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX0_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_OffsetVector0 */ +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0 ((uint32_t)(0xBC30)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_OffsetVector1 */ +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1 ((uint32_t)(0xBC34)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_LastControlWord */ +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD ((uint32_t)(0xBC38)) +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_gammacor0_LockUnlock */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK ((uint32_t)(0xC000)) +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_gammacor0_LockStatus */ +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS ((uint32_t)(0xC004)) +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_gammacor0_StaticControl */ +#define IMXDPUV1_GAMMACOR0_STATICCONTROL ((uint32_t)(0xC008)) +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_RESET_VALUE 0xEU +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_BLUEWRITEENABLE_MASK 0x2U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_BLUEWRITEENABLE_SHIFT 1U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_GREENWRITEENABLE_MASK 0x4U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_GREENWRITEENABLE_SHIFT 2U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_REDWRITEENABLE_MASK 0x8U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_REDWRITEENABLE_SHIFT 3U + +/* Register: IMXDPUV1_gammacor0_LutStart */ +#define IMXDPUV1_GAMMACOR0_LUTSTART ((uint32_t)(0xC00C)) +#define IMXDPUV1_GAMMACOR0_LUTSTART_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_GAMMACOR0_LUTSTART_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LUTSTART_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTBLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTBLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTRED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTRED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor0_LutDeltas */ +#define IMXDPUV1_GAMMACOR0_LUTDELTAS ((uint32_t)(0xC010)) +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_RESET_MASK 0xC0000000U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTABLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTABLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTAGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTAGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTARED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTARED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor0_Control */ +#define IMXDPUV1_GAMMACOR0_CONTROL ((uint32_t)(0xC014)) +#define IMXDPUV1_GAMMACOR0_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_GAMMACOR0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed + * to the output. */ +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__GAMMACOR, Module in gamma correction mode. */ +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE__GAMMACOR 0x1U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_gammacor0_Status */ +#define IMXDPUV1_GAMMACOR0_STATUS ((uint32_t)(0xC018)) +#define IMXDPUV1_GAMMACOR0_STATUS_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_GAMMACOR0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_STATUS_WRITETIMEOUT_SHIFT 0U + +/* Register: IMXDPUV1_gammacor0_LastControlWord */ +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD ((uint32_t)(0xC01C)) +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_dither0_LockUnlock */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK ((uint32_t)(0xC400)) +#define IMXDPUV1_DITHER0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DITHER0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_dither0_LockStatus */ +#define IMXDPUV1_DITHER0_LOCKSTATUS ((uint32_t)(0xC404)) +#define IMXDPUV1_DITHER0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DITHER0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_DITHER0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_DITHER0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_DITHER0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_DITHER0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_DITHER0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_dither0_Control */ +#define IMXDPUV1_DITHER0_CONTROL ((uint32_t)(0xC408)) +#define IMXDPUV1_DITHER0_CONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DITHER0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_DITHER0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the Dither Unit, + * all other settings are ignored. */ +#define IMXDPUV1_DITHER0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Dither Unit is active. */ +#define IMXDPUV1_DITHER0_CONTROL_MODE__ACTIVE 0x1U + +/* Register: IMXDPUV1_dither0_DitherControl */ +#define IMXDPUV1_DITHER0_DITHERCONTROL ((uint32_t)(0xC40C)) +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DITHER0_DITHERCONTROL_RESET_VALUE 0x300222U +#define IMXDPUV1_DITHER0_DITHERCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT_MASK 0x7U +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT_SHIFT 0U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO8, Reduces blue component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO8 0x2U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO7, Reduces blue component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO7 0x3U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO6, Reduces blue component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO6 0x4U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO5, Reduces blue component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO5 0x5U +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT_MASK 0x70U +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT_SHIFT 4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO8, Reduces green component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO8 0x2U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO7, Reduces green component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO7 0x3U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO6, Reduces green component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO6 0x4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO5, Reduces green component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO5 0x5U +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT_MASK 0x700U +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT_SHIFT 8U +/* Field Value: RED_RANGE_SELECT__RED_10TO8, Reduces red component width from + * 10 bit to 8bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO8 0x2U +/* Field Value: RED_RANGE_SELECT__RED_10TO7, Reduces red component width from + * 10 bit to 7bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO7 0x3U +/* Field Value: RED_RANGE_SELECT__RED_10TO6, Reduces red component width from + * 10 bit to 6bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO6 0x4U +/* Field Value: RED_RANGE_SELECT__RED_10TO5, Reduces red component width from + * 10 bit to 5bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO5 0x5U +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT_MASK 0x10000U +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT_SHIFT 16U +/* Field Value: OFFSET_SELECT__OFFS_SPATIAL, Offset is a bayer matrix value, + * which is selected according to pixel frame position. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT__OFFS_SPATIAL 0U +/* Field Value: OFFSET_SELECT__OFFS_TEMPORAL, Offset is the sum from a bayer + * matrix value, which is selected according to pixel frame position, + * and a value from a regular sequence, which changes each frame. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT__OFFS_TEMPORAL 0x1U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT_MASK 0x300000U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT_SHIFT 20U +/* Field Value: ALGO_SELECT__NO_CORRECTION, Best possible resolution for most + * dark colors. Adds a diminutive offset to overall image brightness. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__NO_CORRECTION 0x1U +/* Field Value: ALGO_SELECT__BRIGHTNESS_CORRECTION, Preserves overall image + * brightness. Cannot resolve most dark and most bright colors. All codes + * in-between are distributed perfectly smooth. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__BRIGHTNESS_CORRECTION 0x2U +/* Field Value: ALGO_SELECT__CONTRAST_CORRECTION, Preserves overall image + * brightness. Best possible distribution of color codes over complete range. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__CONTRAST_CORRECTION 0x3U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE_MASK 0x3000000U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE_SHIFT 24U +/* Field Value: ALPHA_MODE__DISABLE, The alpha bit is not considered. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__DISABLE 0U +/* Field Value: ALPHA_MODE__ENABLE_BY1, Red, green and blue components are + * only dithered, if the alpha bit is 1. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__ENABLE_BY1 0x1U +/* Field Value: ALPHA_MODE__ENABLE_BY0, Red, green and blue components are + * only dithered, if the alpha bit is 0. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__ENABLE_BY0 0x2U + +/* Register: IMXDPUV1_dither0_Release */ +#define IMXDPUV1_DITHER0_RELEASE ((uint32_t)(0xC410)) +#define IMXDPUV1_DITHER0_RELEASE_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DITHER0_RELEASE_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_RELEASE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_RELEASE_SUBVERSION_MASK 0xFFU +#define IMXDPUV1_DITHER0_RELEASE_SUBVERSION_SHIFT 0U +#define IMXDPUV1_DITHER0_RELEASE_VERSION_MASK 0xFF00U +#define IMXDPUV1_DITHER0_RELEASE_VERSION_SHIFT 8U + +/* Register: IMXDPUV1_tcon0_SSqCnts */ +#define IMXDPUV1_TCON0_SSQCNTS ((uint32_t)(0xC800)) +#define IMXDPUV1_TCON0_SSQCNTS_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON0_SSQCNTS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SSQCNTS_RESET_MASK 0U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQY_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQY_SHIFT 0U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_FIELD_MASK 0x8000U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_FIELD_SHIFT 15U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQX_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQX_SHIFT 16U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_OUT_MASK 0x80000000U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_OUT_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_LockUnlock */ +#define IMXDPUV1_TCON0_LOCKUNLOCK ((uint32_t)(0xCC00)) +#define IMXDPUV1_TCON0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_TCON0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_tcon0_LockStatus */ +#define IMXDPUV1_TCON0_LOCKSTATUS ((uint32_t)(0xCC04)) +#define IMXDPUV1_TCON0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_TCON0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_TCON0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_TCON0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_TCON0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_TCON0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_TCON0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_tcon0_SSqCycle */ +#define IMXDPUV1_TCON0_SSQCYCLE ((uint32_t)(0xCC08)) +#define IMXDPUV1_TCON0_SSQCYCLE_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_TCON0_SSQCYCLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SSQCYCLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SSQCYCLE_SSQCYCLE_MASK 0x3FU +#define IMXDPUV1_TCON0_SSQCYCLE_SSQCYCLE_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SWreset */ +#define IMXDPUV1_TCON0_SWRESET ((uint32_t)(0xCC0C)) +#define IMXDPUV1_TCON0_SWRESET_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_TCON0_SWRESET_RESET_VALUE 0x3FC00410U +#define IMXDPUV1_TCON0_SWRESET_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SWRESET_SWRESET_MASK 0x1U +#define IMXDPUV1_TCON0_SWRESET_SWRESET_SHIFT 0U +/* Field Value: SWRESET__OPERATION, operation mode */ +#define IMXDPUV1_TCON0_SWRESET_SWRESET__OPERATION 0U +/* Field Value: SWRESET__SWRESET, So long SWReset = 0x1 tcon is in 'SW reset + * state' and it is released by internal logic (SWReset is released and + * end of frame arrived), read: 0b: reset not active 1b: reset active (that + * means NO pixel of video frame is excepted until 'SW reset state' + * is released) */ +#define IMXDPUV1_TCON0_SWRESET_SWRESET__SWRESET 0x1U +#define IMXDPUV1_TCON0_SWRESET_ENRESETWORD_MASK 0xFFF0U +#define IMXDPUV1_TCON0_SWRESET_ENRESETWORD_SHIFT 4U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDEND_MASK 0xFF0000U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDEND_SHIFT 16U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDSTART_MASK 0xFF000000U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDSTART_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_TCON_CTRL */ +#define IMXDPUV1_TCON0_TCON_CTRL ((uint32_t)(0xCC10)) +#define IMXDPUV1_TCON0_TCON_CTRL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_TCON0_TCON_CTRL_RESET_VALUE 0x1401408U +#define IMXDPUV1_TCON0_TCON_CTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE_MASK 0x3U +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE_SHIFT 0U +/* Field Value: CHANNELMODE__SINGLE, Single pixel mode. Both channels channel + * are active at full pixel clock. If bitmap of both panels are the same, + * both panels are identical */ +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__SINGLE 0U +/* Field Value: CHANNELMODE__DUAL_INTERLEAVED, Dual pixel mode. Both channels + * are active at half the pixel clock. 1st channel drives display columns + * with even and 2nd one with odd index. */ +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__DUAL_INTERLEAVED 0x1U +/* Field Value: CHANNELMODE__DUAL_SPLIT, Dual pixel mode. Both channels are + * active at half the pixel clock. 1st channel drives the left and 2nd + * one the righ half of the display. Note : data_en is needed in this mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__DUAL_SPLIT 0x2U +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC_MASK 0x4U +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC_SHIFT 2U +/* Field Value: TCON_SYNC__H_VLAST, tcon timing generator synchronized to + * hlast, vlast */ +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC__H_VLAST 0U +/* Field Value: TCON_SYNC__H_VSYNC, tcon timing generator synchronized to + * hsync, vsync where horizontal synchronization is synchronized at the falling + * edge of hsync */ +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC__H_VSYNC 0x1U +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS_MASK 0x8U +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS_SHIFT 3U +/* Field Value: BYPASS__TCON_MODE, tcon operation mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS__TCON_MODE 0U +/* Field Value: BYPASS__BYPASS_MODE, tcon in Bypass mode. input pixel and + * its sync-signals are bypassed to tcon-output */ +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS__BYPASS_MODE 0x1U +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL_MASK 0xF0U +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL_SHIFT 4U +/* Field Value: INV_CTRL__DISABLE, Disable inversion control */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__DISABLE 0U +/* Field Value: INV_CTRL__RGB_2_BITS, Enable inversion control for number + * of RGB-Bits = 2 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_2_BITS 0x1U +/* Field Value: INV_CTRL__RGB_4_BITS, Enable inversion control for number + * of RGB-Bits = 4 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_4_BITS 0x2U +/* Field Value: INV_CTRL__RGB_6_BITS, Enable inversion control for number + * of RGB-Bits = 6 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_6_BITS 0x3U +/* Field Value: INV_CTRL__RGB_8_BITS, Enable inversion control for number + * of RGB-Bits = 8 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_8_BITS 0x4U +/* Field Value: INV_CTRL__RGB_10_BITS, Enable inversion control for number + * of RGB-Bits = 10 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_10_BITS 0x5U +/* Field Value: INV_CTRL__RGB_12_BITS, Enable inversion control for number + * of RGB-Bits = 12 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_12_BITS 0x6U +/* Field Value: INV_CTRL__RGB_14_BITS, Enable inversion control for number + * of RGB-Bits = 14 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_14_BITS 0x7U +/* Field Value: INV_CTRL__RGB_16_BITS, Enable inversion control for number + * of RGB-Bits = 16 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_16_BITS 0x8U +/* Field Value: INV_CTRL__RGB_18_BITS, Enable inversion control for number + * of RGB-Bits = 18 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_18_BITS 0x9U +/* Field Value: INV_CTRL__RGB_20_BITS, Enable inversion control for number + * of RGB-Bits = 20 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_20_BITS 0xAU +/* Field Value: INV_CTRL__RGB_22_BITS, Enable inversion control for number + * of RGB-Bits = 22 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_22_BITS 0xBU +/* Field Value: INV_CTRL__RGB_24_BITS, Enable inversion control for number + * of RGB-Bits = 24 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_24_BITS 0xCU +/* Field Value: INV_CTRL__RGB_26_BITS, Enable inversion control for number + * of RGB-Bits = 26 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_26_BITS 0xDU +/* Field Value: INV_CTRL__RGB_28_BITS, Enable inversion control for number + * of RGB-Bits = 28 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_28_BITS 0xEU +/* Field Value: INV_CTRL__RGB_30_BITS, Enable inversion control for number + * of RGB-Bits = 30 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_30_BITS 0xFU +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS_MASK 0x100U +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS_SHIFT 8U +/* Field Value: ENLVDS__ENABLE_LVDS, Enable LVDS , TTL and RSDS are disable + * */ +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS__ENABLE_LVDS 0x1U +/* Field Value: ENLVDS__DISABLE_LVDS, Disable LVDS, Enable TTL and RSDS */ +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS__DISABLE_LVDS 0U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE_MASK 0x200U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE_SHIFT 9U +/* Field Value: LVDSMODE__MINI_LVDS, MiniLVDS */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE__MINI_LVDS 0x1U +/* Field Value: LVDSMODE__LVDS, LVDS Mode, refered to OpenLDI */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE__LVDS 0U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE_MASK 0x400U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE_SHIFT 10U +/* Field Value: LVDS_BALANCE__BALANCED, LVDS operates in 24 bits Balanced + * Mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__BALANCED 0x1U +/* Field Value: LVDS_BALANCE__UNBALANCED, LVDS operates in 24 bits Unbalanced + * Mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__UNBALANCED 0U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV_MASK 0x800U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV_SHIFT 11U +/* Field Value: LVDS_CLOCK_INV__INV, Invert LVDS Clock */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV__INV 0x1U +/* Field Value: LVDS_CLOCK_INV__NON_INV, NON-Invert LVDS Clock */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV__NON_INV 0U +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE_MASK 0x7000U +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE_SHIFT 12U +/* Field Value: MINILVDS_OPCODE__MODE_3PAIRS, MiniLVDS operates in 6 and 8 + * bit data, three pairs */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_3PAIRS 0U +/* Field Value: MINILVDS_OPCODE__MODE_4PAIRS, Not Implemented */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS 0x1U +/* Field Value: MINILVDS_OPCODE__MODE_5PAIRS, Not Implemented */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_5PAIRS 0x2U +/* Field Value: MINILVDS_OPCODE__MODE_6PAIRS, MiniLVDS operates in 6 and 8 + * bit data, six pairs */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_6PAIRS 0x3U +/* Field Value: MINILVDS_OPCODE__RESERVED1, RESERVED1 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED1 0x4U +/* Field Value: MINILVDS_OPCODE__RESERVED2, RESERVED2 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED2 0x5U +/* Field Value: MINILVDS_OPCODE__RESERVED3, RESERVED3 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED3 0x6U +/* Field Value: MINILVDS_OPCODE__RESERVED4, RESERVED4 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED4 0x7U +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP_MASK 0x8000U +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP_SHIFT 15U +/* Field Value: DUAL_SWAP__SWAP, swapping pixels between lower-channel and + * upper-channel */ +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP__SWAP 0x1U +/* Field Value: DUAL_SWAP__NON_SWAP, NON-swapping pixels between lower-channel + * and upper-channel */ +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP__NON_SWAP 0U +#define IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION_MASK 0x3FFF0000U +#define IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_RSDSInvCtrl */ +#define IMXDPUV1_TCON0_RSDSINVCTRL ((uint32_t)(0xCC14)) +#define IMXDPUV1_TCON0_RSDSINVCTRL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_TCON0_RSDSINVCTRL_RESET_VALUE 0U +#define IMXDPUV1_TCON0_RSDSINVCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_MASK 0x7FFFU +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_SHIFT 0U +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_DUAL_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_MapBit3_0 */ +#define IMXDPUV1_TCON0_MAPBIT3_0 ((uint32_t)(0xCC18)) +#define IMXDPUV1_TCON0_MAPBIT3_0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_TCON0_MAPBIT3_0_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON0_MAPBIT3_0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT0_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT0_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT1_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT1_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT2_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT2_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT3_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT3_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit7_4 */ +#define IMXDPUV1_TCON0_MAPBIT7_4 ((uint32_t)(0xCC1C)) +#define IMXDPUV1_TCON0_MAPBIT7_4_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_TCON0_MAPBIT7_4_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON0_MAPBIT7_4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT4_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT4_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT5_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT5_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT6_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT6_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT7_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT7_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit11_8 */ +#define IMXDPUV1_TCON0_MAPBIT11_8 ((uint32_t)(0xCC20)) +#define IMXDPUV1_TCON0_MAPBIT11_8_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_TCON0_MAPBIT11_8_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON0_MAPBIT11_8_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT8_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT8_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT9_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT9_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT10_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT10_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT11_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT11_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit15_12 */ +#define IMXDPUV1_TCON0_MAPBIT15_12 ((uint32_t)(0xCC24)) +#define IMXDPUV1_TCON0_MAPBIT15_12_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_TCON0_MAPBIT15_12_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON0_MAPBIT15_12_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT12_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT12_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT13_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT13_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT14_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT14_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT15_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT15_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit19_16 */ +#define IMXDPUV1_TCON0_MAPBIT19_16 ((uint32_t)(0xCC28)) +#define IMXDPUV1_TCON0_MAPBIT19_16_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_TCON0_MAPBIT19_16_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON0_MAPBIT19_16_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT16_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT16_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT17_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT17_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT18_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT18_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT19_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT19_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit23_20 */ +#define IMXDPUV1_TCON0_MAPBIT23_20 ((uint32_t)(0xCC2C)) +#define IMXDPUV1_TCON0_MAPBIT23_20_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_TCON0_MAPBIT23_20_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON0_MAPBIT23_20_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT20_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT20_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT21_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT21_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT22_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT22_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT23_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT23_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit27_24 */ +#define IMXDPUV1_TCON0_MAPBIT27_24 ((uint32_t)(0xCC30)) +#define IMXDPUV1_TCON0_MAPBIT27_24_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_TCON0_MAPBIT27_24_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON0_MAPBIT27_24_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT24_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT24_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT25_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT25_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT26_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT26_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT27_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT27_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit31_28 */ +#define IMXDPUV1_TCON0_MAPBIT31_28 ((uint32_t)(0xCC34)) +#define IMXDPUV1_TCON0_MAPBIT31_28_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_TCON0_MAPBIT31_28_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON0_MAPBIT31_28_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT28_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT28_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT29_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT29_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT30_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT30_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT31_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT31_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit34_32 */ +#define IMXDPUV1_TCON0_MAPBIT34_32 ((uint32_t)(0xCC38)) +#define IMXDPUV1_TCON0_MAPBIT34_32_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_TCON0_MAPBIT34_32_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON0_MAPBIT34_32_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT32_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT32_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT33_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT33_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT34_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT34_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_MapBit3_0_Dual */ +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL ((uint32_t)(0xCC3C)) +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT0_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT0_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT1_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT1_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT2_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT2_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT3_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT3_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit7_4_Dual */ +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL ((uint32_t)(0xCC40)) +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT4_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT4_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT5_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT5_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT6_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT6_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT7_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT7_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit11_8_Dual */ +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL ((uint32_t)(0xCC44)) +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT8_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT8_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT9_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT9_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT10_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT10_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT11_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT11_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit15_12_Dual */ +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL ((uint32_t)(0xCC48)) +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT12_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT12_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT13_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT13_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT14_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT14_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT15_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT15_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit19_16_Dual */ +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL ((uint32_t)(0xCC4C)) +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT16_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT16_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT17_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT17_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT18_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT18_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT19_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT19_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit23_20_Dual */ +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL ((uint32_t)(0xCC50)) +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT20_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT20_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT21_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT21_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT22_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT22_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT23_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT23_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit27_24_Dual */ +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL ((uint32_t)(0xCC54)) +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT24_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT24_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT25_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT25_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT26_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT26_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT27_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT27_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit31_28_Dual */ +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL ((uint32_t)(0xCC58)) +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT28_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT28_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT29_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT29_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT30_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT30_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT31_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT31_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit34_32_Dual */ +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL ((uint32_t)(0xCC5C)) +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT32_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT32_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT33_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT33_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT34_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT34_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_SPG0PosOn */ +#define IMXDPUV1_TCON0_SPG0POSON ((uint32_t)(0xCC60)) +#define IMXDPUV1_TCON0_SPG0POSON_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_TCON0_SPG0POSON_RESET_VALUE 0x1480000U +#define IMXDPUV1_TCON0_SPG0POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_Y0_SHIFT 0U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0_SHIFT 16U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG0MaskOn */ +#define IMXDPUV1_TCON0_SPG0MASKON ((uint32_t)(0xCC64)) +#define IMXDPUV1_TCON0_SPG0MASKON_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_TCON0_SPG0MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG0MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKON_SPGMKON0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKON_SPGMKON0_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG0PosOff */ +#define IMXDPUV1_TCON0_SPG0POSOFF ((uint32_t)(0xCC68)) +#define IMXDPUV1_TCON0_SPG0POSOFF_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_TCON0_SPG0POSOFF_RESET_VALUE 0x1680000U +#define IMXDPUV1_TCON0_SPG0POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_Y0_SHIFT 0U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0_SHIFT 16U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG0MaskOff */ +#define IMXDPUV1_TCON0_SPG0MASKOFF ((uint32_t)(0xCC6C)) +#define IMXDPUV1_TCON0_SPG0MASKOFF_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_TCON0_SPG0MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG0MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKOFF_SPGMKOFF0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKOFF_SPGMKOFF0_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG1PosOn */ +#define IMXDPUV1_TCON0_SPG1POSON ((uint32_t)(0xCC70)) +#define IMXDPUV1_TCON0_SPG1POSON_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_TCON0_SPG1POSON_RESET_VALUE 0xF3U +#define IMXDPUV1_TCON0_SPG1POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1_SHIFT 0U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1_SHIFT 16U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG1MaskOn */ +#define IMXDPUV1_TCON0_SPG1MASKON ((uint32_t)(0xCC74)) +#define IMXDPUV1_TCON0_SPG1MASKON_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_TCON0_SPG1MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKON_SPGMKON1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKON_SPGMKON1_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG1PosOff */ +#define IMXDPUV1_TCON0_SPG1POSOFF ((uint32_t)(0xCC78)) +#define IMXDPUV1_TCON0_SPG1POSOFF_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_TCON0_SPG1POSOFF_RESET_VALUE 0xF7U +#define IMXDPUV1_TCON0_SPG1POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1_SHIFT 0U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1_SHIFT 16U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG1MaskOff */ +#define IMXDPUV1_TCON0_SPG1MASKOFF ((uint32_t)(0xCC7C)) +#define IMXDPUV1_TCON0_SPG1MASKOFF_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_TCON0_SPG1MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKOFF_SPGMKOFF1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKOFF_SPGMKOFF1_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG2PosOn */ +#define IMXDPUV1_TCON0_SPG2POSON ((uint32_t)(0xCC80)) +#define IMXDPUV1_TCON0_SPG2POSON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_TCON0_SPG2POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG2POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_Y2_SHIFT 0U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_X2_SHIFT 16U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG2MaskOn */ +#define IMXDPUV1_TCON0_SPG2MASKON ((uint32_t)(0xCC84)) +#define IMXDPUV1_TCON0_SPG2MASKON_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_TCON0_SPG2MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG2MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKON_SPGMKON2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKON_SPGMKON2_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG2PosOff */ +#define IMXDPUV1_TCON0_SPG2POSOFF ((uint32_t)(0xCC88)) +#define IMXDPUV1_TCON0_SPG2POSOFF_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_TCON0_SPG2POSOFF_RESET_VALUE 0x1400000U +#define IMXDPUV1_TCON0_SPG2POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_Y2_SHIFT 0U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2_SHIFT 16U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG2MaskOff */ +#define IMXDPUV1_TCON0_SPG2MASKOFF ((uint32_t)(0xCC8C)) +#define IMXDPUV1_TCON0_SPG2MASKOFF_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_TCON0_SPG2MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG2MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKOFF_SPGMKOFF2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKOFF_SPGMKOFF2_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG3PosOn */ +#define IMXDPUV1_TCON0_SPG3POSON ((uint32_t)(0xCC90)) +#define IMXDPUV1_TCON0_SPG3POSON_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_TCON0_SPG3POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG3POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_Y3_SHIFT 0U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_X3_SHIFT 16U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG3MaskOn */ +#define IMXDPUV1_TCON0_SPG3MASKON ((uint32_t)(0xCC94)) +#define IMXDPUV1_TCON0_SPG3MASKON_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_TCON0_SPG3MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKON_SPGMKON3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKON_SPGMKON3_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG3PosOff */ +#define IMXDPUV1_TCON0_SPG3POSOFF ((uint32_t)(0xCC98)) +#define IMXDPUV1_TCON0_SPG3POSOFF_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_TCON0_SPG3POSOFF_RESET_VALUE 0xF0U +#define IMXDPUV1_TCON0_SPG3POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3_SHIFT 0U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3_SHIFT 16U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG3MaskOff */ +#define IMXDPUV1_TCON0_SPG3MASKOFF ((uint32_t)(0xCC9C)) +#define IMXDPUV1_TCON0_SPG3MASKOFF_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_TCON0_SPG3MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKOFF_SPGMKOFF3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKOFF_SPGMKOFF3_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG4PosOn */ +#define IMXDPUV1_TCON0_SPG4POSON ((uint32_t)(0xCCA0)) +#define IMXDPUV1_TCON0_SPG4POSON_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_TCON0_SPG4POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4_SHIFT 0U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4_SHIFT 16U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG4MaskOn */ +#define IMXDPUV1_TCON0_SPG4MASKON ((uint32_t)(0xCCA4)) +#define IMXDPUV1_TCON0_SPG4MASKON_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_TCON0_SPG4MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKON_SPGMKON4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKON_SPGMKON4_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG4PosOff */ +#define IMXDPUV1_TCON0_SPG4POSOFF ((uint32_t)(0xCCA8)) +#define IMXDPUV1_TCON0_SPG4POSOFF_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_TCON0_SPG4POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4_SHIFT 0U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4_SHIFT 16U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG4MaskOff */ +#define IMXDPUV1_TCON0_SPG4MASKOFF ((uint32_t)(0xCCAC)) +#define IMXDPUV1_TCON0_SPG4MASKOFF_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_TCON0_SPG4MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKOFF_SPGMKOFF4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKOFF_SPGMKOFF4_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG5PosOn */ +#define IMXDPUV1_TCON0_SPG5POSON ((uint32_t)(0xCCB0)) +#define IMXDPUV1_TCON0_SPG5POSON_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_TCON0_SPG5POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_Y5_SHIFT 0U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_X5_SHIFT 16U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG5MaskOn */ +#define IMXDPUV1_TCON0_SPG5MASKON ((uint32_t)(0xCCB4)) +#define IMXDPUV1_TCON0_SPG5MASKON_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_TCON0_SPG5MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKON_SPGMKON5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKON_SPGMKON5_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG5PosOff */ +#define IMXDPUV1_TCON0_SPG5POSOFF ((uint32_t)(0xCCB8)) +#define IMXDPUV1_TCON0_SPG5POSOFF_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_TCON0_SPG5POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_Y5_SHIFT 0U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_X5_SHIFT 16U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG5MaskOff */ +#define IMXDPUV1_TCON0_SPG5MASKOFF ((uint32_t)(0xCCBC)) +#define IMXDPUV1_TCON0_SPG5MASKOFF_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_TCON0_SPG5MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKOFF_SPGMKOFF5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKOFF_SPGMKOFF5_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG6PosOn */ +#define IMXDPUV1_TCON0_SPG6POSON ((uint32_t)(0xCCC0)) +#define IMXDPUV1_TCON0_SPG6POSON_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_TCON0_SPG6POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_Y6_SHIFT 0U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_X6_SHIFT 16U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG6MaskOn */ +#define IMXDPUV1_TCON0_SPG6MASKON ((uint32_t)(0xCCC4)) +#define IMXDPUV1_TCON0_SPG6MASKON_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_TCON0_SPG6MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKON_SPGMKON6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKON_SPGMKON6_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG6PosOff */ +#define IMXDPUV1_TCON0_SPG6POSOFF ((uint32_t)(0xCCC8)) +#define IMXDPUV1_TCON0_SPG6POSOFF_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_TCON0_SPG6POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_Y6_SHIFT 0U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_X6_SHIFT 16U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG6MaskOff */ +#define IMXDPUV1_TCON0_SPG6MASKOFF ((uint32_t)(0xCCCC)) +#define IMXDPUV1_TCON0_SPG6MASKOFF_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_TCON0_SPG6MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKOFF_SPGMKOFF6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKOFF_SPGMKOFF6_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG7PosOn */ +#define IMXDPUV1_TCON0_SPG7POSON ((uint32_t)(0xCCD0)) +#define IMXDPUV1_TCON0_SPG7POSON_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_TCON0_SPG7POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_Y7_SHIFT 0U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_X7_SHIFT 16U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG7MaskOn */ +#define IMXDPUV1_TCON0_SPG7MASKON ((uint32_t)(0xCCD4)) +#define IMXDPUV1_TCON0_SPG7MASKON_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_TCON0_SPG7MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKON_SPGMKON7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKON_SPGMKON7_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG7PosOff */ +#define IMXDPUV1_TCON0_SPG7POSOFF ((uint32_t)(0xCCD8)) +#define IMXDPUV1_TCON0_SPG7POSOFF_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_TCON0_SPG7POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_Y7_SHIFT 0U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_X7_SHIFT 16U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG7MaskOff */ +#define IMXDPUV1_TCON0_SPG7MASKOFF ((uint32_t)(0xCCDC)) +#define IMXDPUV1_TCON0_SPG7MASKOFF_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_TCON0_SPG7MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKOFF_SPGMKOFF7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKOFF_SPGMKOFF7_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG8PosOn */ +#define IMXDPUV1_TCON0_SPG8POSON ((uint32_t)(0xCCE0)) +#define IMXDPUV1_TCON0_SPG8POSON_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_TCON0_SPG8POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_Y8_SHIFT 0U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_X8_SHIFT 16U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG8MaskOn */ +#define IMXDPUV1_TCON0_SPG8MASKON ((uint32_t)(0xCCE4)) +#define IMXDPUV1_TCON0_SPG8MASKON_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_TCON0_SPG8MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKON_SPGMKON8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKON_SPGMKON8_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG8PosOff */ +#define IMXDPUV1_TCON0_SPG8POSOFF ((uint32_t)(0xCCE8)) +#define IMXDPUV1_TCON0_SPG8POSOFF_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_TCON0_SPG8POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_Y8_SHIFT 0U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_X8_SHIFT 16U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG8MaskOff */ +#define IMXDPUV1_TCON0_SPG8MASKOFF ((uint32_t)(0xCCEC)) +#define IMXDPUV1_TCON0_SPG8MASKOFF_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_TCON0_SPG8MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKOFF_SPGMKOFF8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKOFF_SPGMKOFF8_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG9PosOn */ +#define IMXDPUV1_TCON0_SPG9POSON ((uint32_t)(0xCCF0)) +#define IMXDPUV1_TCON0_SPG9POSON_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_TCON0_SPG9POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_Y9_SHIFT 0U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_X9_SHIFT 16U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG9MaskOn */ +#define IMXDPUV1_TCON0_SPG9MASKON ((uint32_t)(0xCCF4)) +#define IMXDPUV1_TCON0_SPG9MASKON_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_TCON0_SPG9MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKON_SPGMKON9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKON_SPGMKON9_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG9PosOff */ +#define IMXDPUV1_TCON0_SPG9POSOFF ((uint32_t)(0xCCF8)) +#define IMXDPUV1_TCON0_SPG9POSOFF_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_TCON0_SPG9POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_Y9_SHIFT 0U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_X9_SHIFT 16U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG9MaskOff */ +#define IMXDPUV1_TCON0_SPG9MASKOFF ((uint32_t)(0xCCFC)) +#define IMXDPUV1_TCON0_SPG9MASKOFF_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_TCON0_SPG9MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKOFF_SPGMKOFF9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKOFF_SPGMKOFF9_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG10PosOn */ +#define IMXDPUV1_TCON0_SPG10POSON ((uint32_t)(0xCD00)) +#define IMXDPUV1_TCON0_SPG10POSON_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_TCON0_SPG10POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_Y10_SHIFT 0U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_X10_SHIFT 16U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG10MaskOn */ +#define IMXDPUV1_TCON0_SPG10MASKON ((uint32_t)(0xCD04)) +#define IMXDPUV1_TCON0_SPG10MASKON_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_TCON0_SPG10MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKON_SPGMKON10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKON_SPGMKON10_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG10PosOff */ +#define IMXDPUV1_TCON0_SPG10POSOFF ((uint32_t)(0xCD08)) +#define IMXDPUV1_TCON0_SPG10POSOFF_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_TCON0_SPG10POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_Y10_SHIFT 0U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_X10_SHIFT 16U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG10MaskOff */ +#define IMXDPUV1_TCON0_SPG10MASKOFF ((uint32_t)(0xCD0C)) +#define IMXDPUV1_TCON0_SPG10MASKOFF_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_TCON0_SPG10MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKOFF_SPGMKOFF10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKOFF_SPGMKOFF10_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG11PosOn */ +#define IMXDPUV1_TCON0_SPG11POSON ((uint32_t)(0xCD10)) +#define IMXDPUV1_TCON0_SPG11POSON_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_TCON0_SPG11POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_Y11_SHIFT 0U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_X11_SHIFT 16U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG11MaskOn */ +#define IMXDPUV1_TCON0_SPG11MASKON ((uint32_t)(0xCD14)) +#define IMXDPUV1_TCON0_SPG11MASKON_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_TCON0_SPG11MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKON_SPGMKON11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKON_SPGMKON11_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG11PosOff */ +#define IMXDPUV1_TCON0_SPG11POSOFF ((uint32_t)(0xCD18)) +#define IMXDPUV1_TCON0_SPG11POSOFF_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_TCON0_SPG11POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_Y11_SHIFT 0U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_X11_SHIFT 16U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG11MaskOff */ +#define IMXDPUV1_TCON0_SPG11MASKOFF ((uint32_t)(0xCD1C)) +#define IMXDPUV1_TCON0_SPG11MASKOFF_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_TCON0_SPG11MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKOFF_SPGMKOFF11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKOFF_SPGMKOFF11_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx0Sigs */ +#define IMXDPUV1_TCON0_SMX0SIGS ((uint32_t)(0xCD20)) +#define IMXDPUV1_TCON0_SMX0SIGS_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_TCON0_SMX0SIGS_RESET_VALUE 0x2U +#define IMXDPUV1_TCON0_SMX0SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx0FctTable */ +#define IMXDPUV1_TCON0_SMX0FCTTABLE ((uint32_t)(0xCD24)) +#define IMXDPUV1_TCON0_SMX0FCTTABLE_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_TCON0_SMX0FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON0_SMX0FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX0FCTTABLE_SMXFCT0_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX0FCTTABLE_SMXFCT0_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx1Sigs */ +#define IMXDPUV1_TCON0_SMX1SIGS ((uint32_t)(0xCD28)) +#define IMXDPUV1_TCON0_SMX1SIGS_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_TCON0_SMX1SIGS_RESET_VALUE 0x3U +#define IMXDPUV1_TCON0_SMX1SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx1FctTable */ +#define IMXDPUV1_TCON0_SMX1FCTTABLE ((uint32_t)(0xCD2C)) +#define IMXDPUV1_TCON0_SMX1FCTTABLE_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_TCON0_SMX1FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON0_SMX1FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX1FCTTABLE_SMXFCT1_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX1FCTTABLE_SMXFCT1_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx2Sigs */ +#define IMXDPUV1_TCON0_SMX2SIGS ((uint32_t)(0xCD30)) +#define IMXDPUV1_TCON0_SMX2SIGS_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_TCON0_SMX2SIGS_RESET_VALUE 0x2CU +#define IMXDPUV1_TCON0_SMX2SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx2FctTable */ +#define IMXDPUV1_TCON0_SMX2FCTTABLE ((uint32_t)(0xCD34)) +#define IMXDPUV1_TCON0_SMX2FCTTABLE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_TCON0_SMX2FCTTABLE_RESET_VALUE 0x8U +#define IMXDPUV1_TCON0_SMX2FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX2FCTTABLE_SMXFCT2_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX2FCTTABLE_SMXFCT2_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx3Sigs */ +#define IMXDPUV1_TCON0_SMX3SIGS ((uint32_t)(0xCD38)) +#define IMXDPUV1_TCON0_SMX3SIGS_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_TCON0_SMX3SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX3SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx3FctTable */ +#define IMXDPUV1_TCON0_SMX3FCTTABLE ((uint32_t)(0xCD3C)) +#define IMXDPUV1_TCON0_SMX3FCTTABLE_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_TCON0_SMX3FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX3FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX3FCTTABLE_SMXFCT3_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX3FCTTABLE_SMXFCT3_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx4Sigs */ +#define IMXDPUV1_TCON0_SMX4SIGS ((uint32_t)(0xCD40)) +#define IMXDPUV1_TCON0_SMX4SIGS_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_TCON0_SMX4SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX4SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx4FctTable */ +#define IMXDPUV1_TCON0_SMX4FCTTABLE ((uint32_t)(0xCD44)) +#define IMXDPUV1_TCON0_SMX4FCTTABLE_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_TCON0_SMX4FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX4FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX4FCTTABLE_SMXFCT4_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX4FCTTABLE_SMXFCT4_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx5Sigs */ +#define IMXDPUV1_TCON0_SMX5SIGS ((uint32_t)(0xCD48)) +#define IMXDPUV1_TCON0_SMX5SIGS_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_TCON0_SMX5SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX5SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx5FctTable */ +#define IMXDPUV1_TCON0_SMX5FCTTABLE ((uint32_t)(0xCD4C)) +#define IMXDPUV1_TCON0_SMX5FCTTABLE_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_TCON0_SMX5FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX5FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX5FCTTABLE_SMXFCT5_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX5FCTTABLE_SMXFCT5_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx6Sigs */ +#define IMXDPUV1_TCON0_SMX6SIGS ((uint32_t)(0xCD50)) +#define IMXDPUV1_TCON0_SMX6SIGS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_TCON0_SMX6SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX6SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx6FctTable */ +#define IMXDPUV1_TCON0_SMX6FCTTABLE ((uint32_t)(0xCD54)) +#define IMXDPUV1_TCON0_SMX6FCTTABLE_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_TCON0_SMX6FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX6FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX6FCTTABLE_SMXFCT6_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX6FCTTABLE_SMXFCT6_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx7Sigs */ +#define IMXDPUV1_TCON0_SMX7SIGS ((uint32_t)(0xCD58)) +#define IMXDPUV1_TCON0_SMX7SIGS_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_TCON0_SMX7SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX7SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx7FctTable */ +#define IMXDPUV1_TCON0_SMX7FCTTABLE ((uint32_t)(0xCD5C)) +#define IMXDPUV1_TCON0_SMX7FCTTABLE_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_TCON0_SMX7FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX7FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX7FCTTABLE_SMXFCT7_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX7FCTTABLE_SMXFCT7_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx8Sigs */ +#define IMXDPUV1_TCON0_SMX8SIGS ((uint32_t)(0xCD60)) +#define IMXDPUV1_TCON0_SMX8SIGS_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_TCON0_SMX8SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX8SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx8FctTable */ +#define IMXDPUV1_TCON0_SMX8FCTTABLE ((uint32_t)(0xCD64)) +#define IMXDPUV1_TCON0_SMX8FCTTABLE_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_TCON0_SMX8FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX8FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX8FCTTABLE_SMXFCT8_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX8FCTTABLE_SMXFCT8_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx9Sigs */ +#define IMXDPUV1_TCON0_SMX9SIGS ((uint32_t)(0xCD68)) +#define IMXDPUV1_TCON0_SMX9SIGS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_TCON0_SMX9SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX9SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx9FctTable */ +#define IMXDPUV1_TCON0_SMX9FCTTABLE ((uint32_t)(0xCD6C)) +#define IMXDPUV1_TCON0_SMX9FCTTABLE_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_TCON0_SMX9FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX9FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX9FCTTABLE_SMXFCT9_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX9FCTTABLE_SMXFCT9_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx10Sigs */ +#define IMXDPUV1_TCON0_SMX10SIGS ((uint32_t)(0xCD70)) +#define IMXDPUV1_TCON0_SMX10SIGS_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_TCON0_SMX10SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX10SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx10FctTable */ +#define IMXDPUV1_TCON0_SMX10FCTTABLE ((uint32_t)(0xCD74)) +#define IMXDPUV1_TCON0_SMX10FCTTABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_TCON0_SMX10FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX10FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX10FCTTABLE_SMXFCT10_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX10FCTTABLE_SMXFCT10_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx11Sigs */ +#define IMXDPUV1_TCON0_SMX11SIGS ((uint32_t)(0xCD78)) +#define IMXDPUV1_TCON0_SMX11SIGS_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_TCON0_SMX11SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX11SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx11FctTable */ +#define IMXDPUV1_TCON0_SMX11FCTTABLE ((uint32_t)(0xCD7C)) +#define IMXDPUV1_TCON0_SMX11FCTTABLE_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_TCON0_SMX11FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX11FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX11FCTTABLE_SMXFCT11_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX11FCTTABLE_SMXFCT11_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_Reset_Over_Unferflow */ +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW ((uint32_t)(0xCD80)) +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_VALUE 0U +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_STATUS_MASK 0x1U +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_STATUS_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_Dual_Debug */ +#define IMXDPUV1_TCON0_DUAL_DEBUG ((uint32_t)(0xCD84)) +#define IMXDPUV1_TCON0_DUAL_DEBUG_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_TCON0_DUAL_DEBUG_RESET_VALUE 0U +#define IMXDPUV1_TCON0_DUAL_DEBUG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_MASK 0x1U +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_SHIFT 0U +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_MASK 0x2U +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_SHIFT 1U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_MASK 0x10U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_SHIFT 4U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_MASK 0x20U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_SHIFT 5U + +/* Register: IMXDPUV1_sig0_LockUnlock */ +#define IMXDPUV1_SIG0_LOCKUNLOCK ((uint32_t)(0xD000)) +#define IMXDPUV1_SIG0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_SIG0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_SIG0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_sig0_LockStatus */ +#define IMXDPUV1_SIG0_LOCKSTATUS ((uint32_t)(0xD004)) +#define IMXDPUV1_SIG0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_SIG0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_SIG0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_SIG0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_SIG0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_SIG0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_SIG0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_SIG0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_sig0_StaticControl */ +#define IMXDPUV1_SIG0_STATICCONTROL ((uint32_t)(0xD008)) +#define IMXDPUV1_SIG0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_SIG0_STATICCONTROL_RESET_VALUE 0x8000000U +#define IMXDPUV1_SIG0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_SIG0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL_MASK 0x10U +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL_SHIFT 4U +/* Field Value: SHDLDSEL__LOCAL, Shadows are loaded at start of frame for + * each evaluation window for which ShdLdReq has been set. */ +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL__LOCAL 0U +/* Field Value: SHDLDSEL__GLOBAL, Shadows of all evaluation windows are loaded + * synchronous to the display stream (shadow load token received on + * frame input port). */ +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL__GLOBAL 0x1U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRES_MASK 0xFF0000U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRES_SHIFT 16U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRESRESET_MASK 0xFF000000U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRESRESET_SHIFT 24U + +/* Register: IMXDPUV1_sig0_PanicColor */ +#define IMXDPUV1_SIG0_PANICCOLOR ((uint32_t)(0xD00C)) +#define IMXDPUV1_SIG0_PANICCOLOR_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_SIG0_PANICCOLOR_RESET_VALUE 0U +#define IMXDPUV1_SIG0_PANICCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_PANICCOLOR_PANICALPHA_MASK 0x80U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICALPHA_SHIFT 7U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICBLUE_MASK 0xFF00U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICBLUE_SHIFT 8U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICGREEN_MASK 0xFF0000U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICGREEN_SHIFT 16U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICRED_MASK 0xFF000000U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICRED_SHIFT 24U + +/* Register: IMXDPUV1_sig0_EvalControl0 */ +#define IMXDPUV1_SIG0_EVALCONTROL0 ((uint32_t)(0xD010)) +#define IMXDPUV1_SIG0_EVALCONTROL0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_SIG0_EVALCONTROL0_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL0_ENEVALWIN0_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENEVALWIN0_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENCRC0_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENCRC0_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAMASK0_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAMASK0_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAINV0_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAINV0_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENLOCALPANIC0_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENLOCALPANIC0_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENGLOBALPANIC0_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENGLOBALPANIC0_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft0 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT0 ((uint32_t)(0xD014)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_XEVALUPPERLEFT0_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_XEVALUPPERLEFT0_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_YEVALUPPERLEFT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_YEVALUPPERLEFT0_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight0 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0 ((uint32_t)(0xD018)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef0 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF0 ((uint32_t)(0xD01C)) +#define IMXDPUV1_SIG0_SIGCRCREDREF0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_SIG0_SIGCRCREDREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF0_SIGCRCREDREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF0_SIGCRCREDREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef0 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF0 ((uint32_t)(0xD020)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_SIGCRCGREENREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_SIGCRCGREENREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef0 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0 ((uint32_t)(0xD024)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_SIGCRCBLUEREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_SIGCRCBLUEREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed0 */ +#define IMXDPUV1_SIG0_SIGCRCRED0 ((uint32_t)(0xD028)) +#define IMXDPUV1_SIG0_SIGCRCRED0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_SIG0_SIGCRCRED0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED0_SIGCRCRED0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED0_SIGCRCRED0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen0 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN0 ((uint32_t)(0xD02C)) +#define IMXDPUV1_SIG0_SIGCRCGREEN0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_SIG0_SIGCRCGREEN0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN0_SIGCRCGREEN0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN0_SIGCRCGREEN0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue0 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE0 ((uint32_t)(0xD030)) +#define IMXDPUV1_SIG0_SIGCRCBLUE0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_SIG0_SIGCRCBLUE0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE0_SIGCRCBLUE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE0_SIGCRCBLUE0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl1 */ +#define IMXDPUV1_SIG0_EVALCONTROL1 ((uint32_t)(0xD034)) +#define IMXDPUV1_SIG0_EVALCONTROL1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_SIG0_EVALCONTROL1_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL1_ENEVALWIN1_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENEVALWIN1_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENCRC1_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENCRC1_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAMASK1_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAMASK1_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAINV1_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAINV1_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENLOCALPANIC1_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENLOCALPANIC1_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENGLOBALPANIC1_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENGLOBALPANIC1_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft1 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT1 ((uint32_t)(0xD038)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_XEVALUPPERLEFT1_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_XEVALUPPERLEFT1_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_YEVALUPPERLEFT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_YEVALUPPERLEFT1_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight1 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1 ((uint32_t)(0xD03C)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef1 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF1 ((uint32_t)(0xD040)) +#define IMXDPUV1_SIG0_SIGCRCREDREF1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_SIG0_SIGCRCREDREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF1_SIGCRCREDREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF1_SIGCRCREDREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef1 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF1 ((uint32_t)(0xD044)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_SIGCRCGREENREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_SIGCRCGREENREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef1 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1 ((uint32_t)(0xD048)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_SIGCRCBLUEREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_SIGCRCBLUEREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed1 */ +#define IMXDPUV1_SIG0_SIGCRCRED1 ((uint32_t)(0xD04C)) +#define IMXDPUV1_SIG0_SIGCRCRED1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_SIG0_SIGCRCRED1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED1_SIGCRCRED1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED1_SIGCRCRED1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen1 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN1 ((uint32_t)(0xD050)) +#define IMXDPUV1_SIG0_SIGCRCGREEN1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_SIG0_SIGCRCGREEN1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN1_SIGCRCGREEN1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN1_SIGCRCGREEN1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue1 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE1 ((uint32_t)(0xD054)) +#define IMXDPUV1_SIG0_SIGCRCBLUE1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_SIG0_SIGCRCBLUE1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE1_SIGCRCBLUE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE1_SIGCRCBLUE1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl2 */ +#define IMXDPUV1_SIG0_EVALCONTROL2 ((uint32_t)(0xD058)) +#define IMXDPUV1_SIG0_EVALCONTROL2_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_SIG0_EVALCONTROL2_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL2_ENEVALWIN2_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENEVALWIN2_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENCRC2_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENCRC2_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAMASK2_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAMASK2_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAINV2_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAINV2_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENLOCALPANIC2_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENLOCALPANIC2_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENGLOBALPANIC2_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENGLOBALPANIC2_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft2 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT2 ((uint32_t)(0xD05C)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_XEVALUPPERLEFT2_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_XEVALUPPERLEFT2_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_YEVALUPPERLEFT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_YEVALUPPERLEFT2_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight2 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2 ((uint32_t)(0xD060)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef2 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF2 ((uint32_t)(0xD064)) +#define IMXDPUV1_SIG0_SIGCRCREDREF2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_SIG0_SIGCRCREDREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF2_SIGCRCREDREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF2_SIGCRCREDREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef2 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF2 ((uint32_t)(0xD068)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_SIGCRCGREENREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_SIGCRCGREENREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef2 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2 ((uint32_t)(0xD06C)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_SIGCRCBLUEREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_SIGCRCBLUEREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed2 */ +#define IMXDPUV1_SIG0_SIGCRCRED2 ((uint32_t)(0xD070)) +#define IMXDPUV1_SIG0_SIGCRCRED2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_SIG0_SIGCRCRED2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED2_SIGCRCRED2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED2_SIGCRCRED2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen2 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN2 ((uint32_t)(0xD074)) +#define IMXDPUV1_SIG0_SIGCRCGREEN2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_SIG0_SIGCRCGREEN2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN2_SIGCRCGREEN2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN2_SIGCRCGREEN2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue2 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE2 ((uint32_t)(0xD078)) +#define IMXDPUV1_SIG0_SIGCRCBLUE2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_SIG0_SIGCRCBLUE2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE2_SIGCRCBLUE2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE2_SIGCRCBLUE2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl3 */ +#define IMXDPUV1_SIG0_EVALCONTROL3 ((uint32_t)(0xD07C)) +#define IMXDPUV1_SIG0_EVALCONTROL3_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_SIG0_EVALCONTROL3_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL3_ENEVALWIN3_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENEVALWIN3_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENCRC3_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENCRC3_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAMASK3_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAMASK3_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAINV3_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAINV3_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENLOCALPANIC3_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENLOCALPANIC3_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENGLOBALPANIC3_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENGLOBALPANIC3_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft3 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT3 ((uint32_t)(0xD080)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_XEVALUPPERLEFT3_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_XEVALUPPERLEFT3_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_YEVALUPPERLEFT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_YEVALUPPERLEFT3_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight3 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3 ((uint32_t)(0xD084)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef3 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF3 ((uint32_t)(0xD088)) +#define IMXDPUV1_SIG0_SIGCRCREDREF3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_SIG0_SIGCRCREDREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF3_SIGCRCREDREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF3_SIGCRCREDREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef3 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF3 ((uint32_t)(0xD08C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_SIGCRCGREENREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_SIGCRCGREENREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef3 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3 ((uint32_t)(0xD090)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_SIGCRCBLUEREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_SIGCRCBLUEREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed3 */ +#define IMXDPUV1_SIG0_SIGCRCRED3 ((uint32_t)(0xD094)) +#define IMXDPUV1_SIG0_SIGCRCRED3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_SIG0_SIGCRCRED3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED3_SIGCRCRED3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED3_SIGCRCRED3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen3 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN3 ((uint32_t)(0xD098)) +#define IMXDPUV1_SIG0_SIGCRCGREEN3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_SIG0_SIGCRCGREEN3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN3_SIGCRCGREEN3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN3_SIGCRCGREEN3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue3 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE3 ((uint32_t)(0xD09C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE3_SIGCRCBLUE3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE3_SIGCRCBLUE3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl4 */ +#define IMXDPUV1_SIG0_EVALCONTROL4 ((uint32_t)(0xD0A0)) +#define IMXDPUV1_SIG0_EVALCONTROL4_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_SIG0_EVALCONTROL4_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL4_ENEVALWIN4_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENEVALWIN4_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENCRC4_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENCRC4_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAMASK4_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAMASK4_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAINV4_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAINV4_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENLOCALPANIC4_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENLOCALPANIC4_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENGLOBALPANIC4_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENGLOBALPANIC4_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft4 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT4 ((uint32_t)(0xD0A4)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_XEVALUPPERLEFT4_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_XEVALUPPERLEFT4_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_YEVALUPPERLEFT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_YEVALUPPERLEFT4_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight4 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4 ((uint32_t)(0xD0A8)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef4 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF4 ((uint32_t)(0xD0AC)) +#define IMXDPUV1_SIG0_SIGCRCREDREF4_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_SIG0_SIGCRCREDREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF4_SIGCRCREDREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF4_SIGCRCREDREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef4 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF4 ((uint32_t)(0xD0B0)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_SIGCRCGREENREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_SIGCRCGREENREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef4 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4 ((uint32_t)(0xD0B4)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_SIGCRCBLUEREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_SIGCRCBLUEREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed4 */ +#define IMXDPUV1_SIG0_SIGCRCRED4 ((uint32_t)(0xD0B8)) +#define IMXDPUV1_SIG0_SIGCRCRED4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_SIG0_SIGCRCRED4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED4_SIGCRCRED4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED4_SIGCRCRED4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen4 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN4 ((uint32_t)(0xD0BC)) +#define IMXDPUV1_SIG0_SIGCRCGREEN4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_SIG0_SIGCRCGREEN4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN4_SIGCRCGREEN4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN4_SIGCRCGREEN4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue4 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE4 ((uint32_t)(0xD0C0)) +#define IMXDPUV1_SIG0_SIGCRCBLUE4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_SIG0_SIGCRCBLUE4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE4_SIGCRCBLUE4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE4_SIGCRCBLUE4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl5 */ +#define IMXDPUV1_SIG0_EVALCONTROL5 ((uint32_t)(0xD0C4)) +#define IMXDPUV1_SIG0_EVALCONTROL5_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_SIG0_EVALCONTROL5_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL5_ENEVALWIN5_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENEVALWIN5_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENCRC5_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENCRC5_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAMASK5_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAMASK5_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAINV5_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAINV5_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENLOCALPANIC5_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENLOCALPANIC5_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENGLOBALPANIC5_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENGLOBALPANIC5_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft5 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT5 ((uint32_t)(0xD0C8)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_XEVALUPPERLEFT5_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_XEVALUPPERLEFT5_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_YEVALUPPERLEFT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_YEVALUPPERLEFT5_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight5 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5 ((uint32_t)(0xD0CC)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef5 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF5 ((uint32_t)(0xD0D0)) +#define IMXDPUV1_SIG0_SIGCRCREDREF5_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_SIG0_SIGCRCREDREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF5_SIGCRCREDREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF5_SIGCRCREDREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef5 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF5 ((uint32_t)(0xD0D4)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_SIGCRCGREENREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_SIGCRCGREENREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef5 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5 ((uint32_t)(0xD0D8)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_SIGCRCBLUEREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_SIGCRCBLUEREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed5 */ +#define IMXDPUV1_SIG0_SIGCRCRED5 ((uint32_t)(0xD0DC)) +#define IMXDPUV1_SIG0_SIGCRCRED5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_SIG0_SIGCRCRED5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED5_SIGCRCRED5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED5_SIGCRCRED5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen5 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN5 ((uint32_t)(0xD0E0)) +#define IMXDPUV1_SIG0_SIGCRCGREEN5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_SIG0_SIGCRCGREEN5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN5_SIGCRCGREEN5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN5_SIGCRCGREEN5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue5 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE5 ((uint32_t)(0xD0E4)) +#define IMXDPUV1_SIG0_SIGCRCBLUE5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_SIG0_SIGCRCBLUE5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE5_SIGCRCBLUE5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE5_SIGCRCBLUE5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl6 */ +#define IMXDPUV1_SIG0_EVALCONTROL6 ((uint32_t)(0xD0E8)) +#define IMXDPUV1_SIG0_EVALCONTROL6_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_SIG0_EVALCONTROL6_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL6_ENEVALWIN6_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENEVALWIN6_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENCRC6_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENCRC6_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAMASK6_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAMASK6_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAINV6_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAINV6_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENLOCALPANIC6_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENLOCALPANIC6_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENGLOBALPANIC6_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENGLOBALPANIC6_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft6 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT6 ((uint32_t)(0xD0EC)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_XEVALUPPERLEFT6_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_XEVALUPPERLEFT6_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_YEVALUPPERLEFT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_YEVALUPPERLEFT6_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight6 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6 ((uint32_t)(0xD0F0)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef6 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF6 ((uint32_t)(0xD0F4)) +#define IMXDPUV1_SIG0_SIGCRCREDREF6_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_SIG0_SIGCRCREDREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF6_SIGCRCREDREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF6_SIGCRCREDREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef6 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF6 ((uint32_t)(0xD0F8)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_SIGCRCGREENREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_SIGCRCGREENREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef6 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6 ((uint32_t)(0xD0FC)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_SIGCRCBLUEREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_SIGCRCBLUEREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed6 */ +#define IMXDPUV1_SIG0_SIGCRCRED6 ((uint32_t)(0xD100)) +#define IMXDPUV1_SIG0_SIGCRCRED6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_SIG0_SIGCRCRED6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED6_SIGCRCRED6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED6_SIGCRCRED6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen6 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN6 ((uint32_t)(0xD104)) +#define IMXDPUV1_SIG0_SIGCRCGREEN6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_SIG0_SIGCRCGREEN6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN6_SIGCRCGREEN6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN6_SIGCRCGREEN6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue6 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE6 ((uint32_t)(0xD108)) +#define IMXDPUV1_SIG0_SIGCRCBLUE6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_SIG0_SIGCRCBLUE6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE6_SIGCRCBLUE6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE6_SIGCRCBLUE6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl7 */ +#define IMXDPUV1_SIG0_EVALCONTROL7 ((uint32_t)(0xD10C)) +#define IMXDPUV1_SIG0_EVALCONTROL7_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_SIG0_EVALCONTROL7_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL7_ENEVALWIN7_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENEVALWIN7_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENCRC7_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENCRC7_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAMASK7_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAMASK7_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAINV7_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAINV7_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENLOCALPANIC7_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENLOCALPANIC7_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENGLOBALPANIC7_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENGLOBALPANIC7_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft7 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT7 ((uint32_t)(0xD110)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_XEVALUPPERLEFT7_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_XEVALUPPERLEFT7_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_YEVALUPPERLEFT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_YEVALUPPERLEFT7_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight7 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7 ((uint32_t)(0xD114)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef7 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF7 ((uint32_t)(0xD118)) +#define IMXDPUV1_SIG0_SIGCRCREDREF7_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_SIG0_SIGCRCREDREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF7_SIGCRCREDREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF7_SIGCRCREDREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef7 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF7 ((uint32_t)(0xD11C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_SIGCRCGREENREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_SIGCRCGREENREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef7 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7 ((uint32_t)(0xD120)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_SIGCRCBLUEREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_SIGCRCBLUEREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed7 */ +#define IMXDPUV1_SIG0_SIGCRCRED7 ((uint32_t)(0xD124)) +#define IMXDPUV1_SIG0_SIGCRCRED7_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_SIG0_SIGCRCRED7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED7_SIGCRCRED7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED7_SIGCRCRED7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen7 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN7 ((uint32_t)(0xD128)) +#define IMXDPUV1_SIG0_SIGCRCGREEN7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_SIG0_SIGCRCGREEN7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN7_SIGCRCGREEN7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN7_SIGCRCGREEN7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue7 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE7 ((uint32_t)(0xD12C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE7_SIGCRCBLUE7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE7_SIGCRCBLUE7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_ShadowLoad */ +#define IMXDPUV1_SIG0_SHADOWLOAD ((uint32_t)(0xD130)) +#define IMXDPUV1_SIG0_SHADOWLOAD_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_SIG0_SHADOWLOAD_RESET_VALUE 0U +#define IMXDPUV1_SIG0_SHADOWLOAD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SHADOWLOAD_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_SIG0_SHADOWLOAD_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_sig0_ContinuousMode */ +#define IMXDPUV1_SIG0_CONTINUOUSMODE ((uint32_t)(0xD134)) +#define IMXDPUV1_SIG0_CONTINUOUSMODE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_SIG0_CONTINUOUSMODE_RESET_VALUE 0U +#define IMXDPUV1_SIG0_CONTINUOUSMODE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_CONTINUOUSMODE_ENCONT_MASK 0x1U +#define IMXDPUV1_SIG0_CONTINUOUSMODE_ENCONT_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SoftwareKick */ +#define IMXDPUV1_SIG0_SOFTWAREKICK ((uint32_t)(0xD138)) +#define IMXDPUV1_SIG0_SOFTWAREKICK_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_SIG0_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_SIG0_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_SIG0_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_sig0_Status */ +#define IMXDPUV1_SIG0_STATUS ((uint32_t)(0xD13C)) +#define IMXDPUV1_SIG0_STATUS_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_SIG0_STATUS_RESET_VALUE 0x100000U +#define IMXDPUV1_SIG0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_STATUS_STSSIGERROR_MASK 0xFFU +#define IMXDPUV1_SIG0_STATUS_STSSIGERROR_SHIFT 0U +#define IMXDPUV1_SIG0_STATUS_STSSIGVALID_MASK 0x10000U +#define IMXDPUV1_SIG0_STATUS_STSSIGVALID_SHIFT 16U +#define IMXDPUV1_SIG0_STATUS_STSSIGIDLE_MASK 0x100000U +#define IMXDPUV1_SIG0_STATUS_STSSIGIDLE_SHIFT 20U + +/* Register: IMXDPUV1_framegen1_LockUnlock */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK ((uint32_t)(0xD400)) +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_framegen1_LockStatus */ +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS ((uint32_t)(0xD404)) +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_framegen1_FgStCtrl */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL ((uint32_t)(0xD408)) +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_SHDEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_SHDEN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE_SHIFT 1U +/* Field Value: FGSYNCMODE__OFF, No side-by-side synchronization. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__OFF 0U +/* Field Value: FGSYNCMODE__MASTER, Framegen is master. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__MASTER 0x1U +/* Field Value: FGSYNCMODE__SLAVE_CYC, Framegen is slave. Runs in cyclic synchronization + * mode. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_CYC 0x2U +/* Field Value: FGSYNCMODE__SLAVE_ONCE, Framegen is slave. Runs in one time + * synchronization mode. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_ONCE 0x3U + +/* Register: IMXDPUV1_framegen1_HtCfg1 */ +#define IMXDPUV1_FRAMEGEN1_HTCFG1 ((uint32_t)(0xD40C)) +#define IMXDPUV1_FRAMEGEN1_HTCFG1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FRAMEGEN1_HTCFG1_RESET_VALUE 0x18F0140U +#define IMXDPUV1_FRAMEGEN1_HTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_HtCfg2 */ +#define IMXDPUV1_FRAMEGEN1_HTCFG2 ((uint32_t)(0xD410)) +#define IMXDPUV1_FRAMEGEN1_HTCFG2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FRAMEGEN1_HTCFG2_RESET_VALUE 0x8047001FU +#define IMXDPUV1_FRAMEGEN1_HTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_VtCfg1 */ +#define IMXDPUV1_FRAMEGEN1_VTCFG1 ((uint32_t)(0xD414)) +#define IMXDPUV1_FRAMEGEN1_VTCFG1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FRAMEGEN1_VTCFG1_RESET_VALUE 0xFC00F0U +#define IMXDPUV1_FRAMEGEN1_VTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_VtCfg2 */ +#define IMXDPUV1_FRAMEGEN1_VTCFG2 ((uint32_t)(0xD418)) +#define IMXDPUV1_FRAMEGEN1_VTCFG2_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FRAMEGEN1_VTCFG2_RESET_VALUE 0x80090003U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int0Config */ +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG ((uint32_t)(0xD41C)) +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int1Config */ +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG ((uint32_t)(0xD420)) +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int2Config */ +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG ((uint32_t)(0xD424)) +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int3Config */ +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG ((uint32_t)(0xD428)) +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_PKickConfig */ +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG ((uint32_t)(0xD42C)) +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKINT0EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKINT0EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_SKickConfig */ +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG ((uint32_t)(0xD430)) +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKINT1EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKINT1EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG_SHIFT 30U +/* Field Value: SKICKTRIG__INTERNAL, Use internal skick signal, trigger point + * defined by SKickRow and SKickCol. */ +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG__INTERNAL 0U +/* Field Value: SKICKTRIG__EXTERNAL, Use external skick input as trigger. */ +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG__EXTERNAL 0x1U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_SecStatConfig */ +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG ((uint32_t)(0xD434)) +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_RESET_VALUE 0x112U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVGOODFRAMES_MASK 0xFU +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVGOODFRAMES_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVBADFRAMES_MASK 0xF0U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVBADFRAMES_SHIFT 4U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVSKEWINRANGE_MASK 0xF00U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVSKEWINRANGE_SHIFT 8U + +/* Register: IMXDPUV1_framegen1_FgSRCR1 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1 ((uint32_t)(0xD438)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE_SHIFT 1U +/* Field Value: SRMODE__OFF, Skew Regulation is off. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__OFF 0U +/* Field Value: SRMODE__HREG, Horizontal regulation enabled. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__HREG 0x1U +/* Field Value: SRMODE__VREG, Vertical regulation enabled. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__VREG 0x2U +/* Field Value: SRMODE__BOTH, Both regulation modes are enabled. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__BOTH 0x3U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRADJ_MASK 0x8U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRADJ_SHIFT 3U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREVEN_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREVEN_SHIFT 4U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRFASTSYNC_MASK 0x20U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRFASTSYNC_SHIFT 5U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQALIGN_MASK 0x40U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQALIGN_SHIFT 6U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL_MASK 0x180U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL_SHIFT 7U +/* Field Value: SRQVAL__ZERO, Fixed two LSB values of HTOTAL are 0b00. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__ZERO 0U +/* Field Value: SRQVAL__ONE, Fixed two LSB values of HTOTAL are 0b01. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__ONE 0x1U +/* Field Value: SRQVAL__TWO, Fixed two LSB values of HTOTAL are 0b10. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__TWO 0x2U +/* Field Value: SRQVAL__THREE, Fixed two LSB values of HTOTAL are 0b11. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__THREE 0x3U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRDBGDISP_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRDBGDISP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREPOFF_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREPOFF_SHIFT 17U + +/* Register: IMXDPUV1_framegen1_FgSRCR2 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR2 ((uint32_t)(0xD43C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_RESET_VALUE 0x1B70188U +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgSRCR3 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR3 ((uint32_t)(0xD440)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_RESET_VALUE 0x11500FBU +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgSRCR4 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR4 ((uint32_t)(0xD444)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_RESET_VALUE 0xC8U +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_TARGETSKEW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_TARGETSKEW_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSRCR5 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR5 ((uint32_t)(0xD448)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_SYNCRANGELOW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_SYNCRANGELOW_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSRCR6 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR6 ((uint32_t)(0xD44C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_RESET_VALUE 0x190U +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_SYNCRANGEHIGH_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_SYNCRANGEHIGH_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgKSDR */ +#define IMXDPUV1_FRAMEGEN1_FGKSDR ((uint32_t)(0xD450)) +#define IMXDPUV1_FRAMEGEN1_FGKSDR_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FRAMEGEN1_FGKSDR_RESET_VALUE 0x20002U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGKSDR_PCNTCPLMAX_MASK 0x7U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_PCNTCPLMAX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_SCNTCPLMAX_MASK 0x70000U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_SCNTCPLMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_PaCfg */ +#define IMXDPUV1_FRAMEGEN1_PACFG ((uint32_t)(0xD454)) +#define IMXDPUV1_FRAMEGEN1_PACFG_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FRAMEGEN1_PACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN1_PACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_SaCfg */ +#define IMXDPUV1_FRAMEGEN1_SACFG ((uint32_t)(0xD458)) +#define IMXDPUV1_FRAMEGEN1_SACFG_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FRAMEGEN1_SACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN1_SACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgInCtrl */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL ((uint32_t)(0xD45C)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_RESET_VALUE 0x6U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM_MASK 0x7U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM_SHIFT 0U +/* Field Value: FGDM__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__BLACK 0U +/* Field Value: FGDM__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__CONSTCOL 0x1U +/* Field Value: FGDM__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__PRIM 0x2U +/* Field Value: FGDM__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__SEC 0x3U +/* Field Value: FGDM__PRIM_ON_TOP, Both inputs overlaid with primary on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__PRIM_ON_TOP 0x4U +/* Field Value: FGDM__SEC_ON_TOP, Both inputs overlaid with secondary on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__SEC_ON_TOP 0x5U +/* Field Value: FGDM__TEST, White color background with test pattern is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__TEST 0x6U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENPRIMALPHA_MASK 0x8U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENPRIMALPHA_SHIFT 3U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENSECALPHA_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENSECALPHA_SHIFT 4U + +/* Register: IMXDPUV1_framegen1_FgInCtrlPanic */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC ((uint32_t)(0xD460)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC_MASK 0x7U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC_SHIFT 0U +/* Field Value: FGDMPANIC__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__BLACK 0U +/* Field Value: FGDMPANIC__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__CONSTCOL 0x1U +/* Field Value: FGDMPANIC__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__PRIM 0x2U +/* Field Value: FGDMPANIC__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__SEC 0x3U +/* Field Value: FGDMPANIC__PRIM_ON_TOP, Both inputs overlaid with primary + * on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__PRIM_ON_TOP 0x4U +/* Field Value: FGDMPANIC__SEC_ON_TOP, Both inputs overlaid with secondary + * on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__SEC_ON_TOP 0x5U +/* Field Value: FGDMPANIC__TEST, White color background with test pattern + * is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__TEST 0x6U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENPRIMALPHAPANIC_MASK 0x8U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENPRIMALPHAPANIC_SHIFT 3U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENSECALPHAPANIC_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENSECALPHAPANIC_SHIFT 4U + +/* Register: IMXDPUV1_framegen1_FgCCR */ +#define IMXDPUV1_FRAMEGEN1_FGCCR ((uint32_t)(0xD464)) +#define IMXDPUV1_FRAMEGEN1_FGCCR_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FRAMEGEN1_FGCCR_RESET_VALUE 0x7FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCCR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCBLUE_MASK 0x3FFU +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCBLUE_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCGREEN_MASK 0xFFC00U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCGREEN_SHIFT 10U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCRED_MASK 0x3FF00000U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCRED_SHIFT 20U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCALPHA_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCALPHA_SHIFT 30U + +/* Register: IMXDPUV1_framegen1_FgEnable */ +#define IMXDPUV1_FRAMEGEN1_FGENABLE ((uint32_t)(0xD468)) +#define IMXDPUV1_FRAMEGEN1_FGENABLE_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FRAMEGEN1_FGENABLE_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGENABLE_FGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGENABLE_FGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSlr */ +#define IMXDPUV1_FRAMEGEN1_FGSLR ((uint32_t)(0xD46C)) +#define IMXDPUV1_FRAMEGEN1_FGSLR_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FRAMEGEN1_FGSLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSLR_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSLR_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgEnSts */ +#define IMXDPUV1_FRAMEGEN1_FGENSTS ((uint32_t)(0xD470)) +#define IMXDPUV1_FRAMEGEN1_FGENSTS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FRAMEGEN1_FGENSTS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGENSTS_ENSTS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_ENSTS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_PANICSTAT_MASK 0x2U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_PANICSTAT_SHIFT 1U + +/* Register: IMXDPUV1_framegen1_FgTimeStamp */ +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP ((uint32_t)(0xD474)) +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_LINEINDEX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_LINEINDEX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_FRAMEINDEX_MASK 0xFFFFC000U +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_FRAMEINDEX_SHIFT 14U + +/* Register: IMXDPUV1_framegen1_FgChStat */ +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT ((uint32_t)(0xD478)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PFIFOEMPTY_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PFIFOEMPTY_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PRIMSYNCSTAT_MASK 0x100U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PRIMSYNCSTAT_SHIFT 8U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SFIFOEMPTY_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SFIFOEMPTY_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SKEWRANGEERR_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SKEWRANGEERR_SHIFT 17U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SECSYNCSTAT_MASK 0x1000000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SECSYNCSTAT_SHIFT 24U + +/* Register: IMXDPUV1_framegen1_FgChStatClr */ +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR ((uint32_t)(0xD47C)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRPRIMSTAT_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRPRIMSTAT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRSECSTAT_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRSECSTAT_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgSkewMon */ +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON ((uint32_t)(0xD480)) +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_SKEWMON_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_SKEWMON_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSFifoMin */ +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN ((uint32_t)(0xD484)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_SFIFOMIN_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_SFIFOMIN_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSFifoMax */ +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX ((uint32_t)(0xD488)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_SFIFOMAX_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_SFIFOMAX_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSFifoFillClr */ +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR ((uint32_t)(0xD48C)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_SFIFOFILLCLR_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_SFIFOFILLCLR_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSrEpD */ +#define IMXDPUV1_FRAMEGEN1_FGSREPD ((uint32_t)(0xD490)) +#define IMXDPUV1_FRAMEGEN1_FGSREPD_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FRAMEGEN1_FGSREPD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSREPD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSREPD_EPVAL_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSREPD_EPVAL_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSrFtD */ +#define IMXDPUV1_FRAMEGEN1_FGSRFTD ((uint32_t)(0xD494)) +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_FRTOT_MASK 0xFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_FRTOT_SHIFT 0U + +/* Register: IMXDPUV1_matrix1_LockUnlock */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK ((uint32_t)(0xD800)) +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix1_LockStatus */ +#define IMXDPUV1_MATRIX1_LOCKSTATUS ((uint32_t)(0xD804)) +#define IMXDPUV1_MATRIX1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix1_StaticControl */ +#define IMXDPUV1_MATRIX1_STATICCONTROL ((uint32_t)(0xD808)) +#define IMXDPUV1_MATRIX1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX1_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix1_Control */ +#define IMXDPUV1_MATRIX1_CONTROL ((uint32_t)(0xD80C)) +#define IMXDPUV1_MATRIX1_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix1_Red0 */ +#define IMXDPUV1_MATRIX1_RED0 ((uint32_t)(0xD810)) +#define IMXDPUV1_MATRIX1_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX1_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX1_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX1_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Red1 */ +#define IMXDPUV1_MATRIX1_RED1 ((uint32_t)(0xD814)) +#define IMXDPUV1_MATRIX1_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX1_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX1_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Green0 */ +#define IMXDPUV1_MATRIX1_GREEN0 ((uint32_t)(0xD818)) +#define IMXDPUV1_MATRIX1_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX1_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX1_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX1_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Green1 */ +#define IMXDPUV1_MATRIX1_GREEN1 ((uint32_t)(0xD81C)) +#define IMXDPUV1_MATRIX1_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX1_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX1_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Blue0 */ +#define IMXDPUV1_MATRIX1_BLUE0 ((uint32_t)(0xD820)) +#define IMXDPUV1_MATRIX1_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX1_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX1_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Blue1 */ +#define IMXDPUV1_MATRIX1_BLUE1 ((uint32_t)(0xD824)) +#define IMXDPUV1_MATRIX1_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX1_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX1_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX1_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Alpha0 */ +#define IMXDPUV1_MATRIX1_ALPHA0 ((uint32_t)(0xD828)) +#define IMXDPUV1_MATRIX1_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX1_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX1_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Alpha1 */ +#define IMXDPUV1_MATRIX1_ALPHA1 ((uint32_t)(0xD82C)) +#define IMXDPUV1_MATRIX1_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX1_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX1_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX1_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_OffsetVector0 */ +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0 ((uint32_t)(0xD830)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_OffsetVector1 */ +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1 ((uint32_t)(0xD834)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_LastControlWord */ +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD ((uint32_t)(0xD838)) +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_gammacor1_LockUnlock */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK ((uint32_t)(0xDC00)) +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_gammacor1_LockStatus */ +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS ((uint32_t)(0xDC04)) +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_gammacor1_StaticControl */ +#define IMXDPUV1_GAMMACOR1_STATICCONTROL ((uint32_t)(0xDC08)) +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_RESET_VALUE 0xEU +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE_MASK 0x2U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE_SHIFT 1U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE_MASK 0x4U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE_SHIFT 2U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE_MASK 0x8U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE_SHIFT 3U + +/* Register: IMXDPUV1_gammacor1_LutStart */ +#define IMXDPUV1_GAMMACOR1_LUTSTART ((uint32_t)(0xDC0C)) +#define IMXDPUV1_GAMMACOR1_LUTSTART_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_GAMMACOR1_LUTSTART_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LUTSTART_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTBLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTBLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTRED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTRED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor1_LutDeltas */ +#define IMXDPUV1_GAMMACOR1_LUTDELTAS ((uint32_t)(0xDC10)) +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_RESET_MASK 0xC0000000U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTABLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTABLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTAGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTAGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTARED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTARED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor1_Control */ +#define IMXDPUV1_GAMMACOR1_CONTROL ((uint32_t)(0xDC14)) +#define IMXDPUV1_GAMMACOR1_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_GAMMACOR1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed + * to the output. */ +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__GAMMACOR, Module in gamma correction mode. */ +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE__GAMMACOR 0x1U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_gammacor1_Status */ +#define IMXDPUV1_GAMMACOR1_STATUS ((uint32_t)(0xDC18)) +#define IMXDPUV1_GAMMACOR1_STATUS_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_GAMMACOR1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_STATUS_WRITETIMEOUT_SHIFT 0U + +/* Register: IMXDPUV1_gammacor1_LastControlWord */ +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD ((uint32_t)(0xDC1C)) +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_dither1_LockUnlock */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK ((uint32_t)(0xE000)) +#define IMXDPUV1_DITHER1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DITHER1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_dither1_LockStatus */ +#define IMXDPUV1_DITHER1_LOCKSTATUS ((uint32_t)(0xE004)) +#define IMXDPUV1_DITHER1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DITHER1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_DITHER1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_DITHER1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_DITHER1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_DITHER1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_DITHER1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_dither1_Control */ +#define IMXDPUV1_DITHER1_CONTROL ((uint32_t)(0xE008)) +#define IMXDPUV1_DITHER1_CONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DITHER1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_DITHER1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the Dither Unit, + * all other settings are ignored. */ +#define IMXDPUV1_DITHER1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Dither Unit is active. */ +#define IMXDPUV1_DITHER1_CONTROL_MODE__ACTIVE 0x1U + +/* Register: IMXDPUV1_dither1_DitherControl */ +#define IMXDPUV1_DITHER1_DITHERCONTROL ((uint32_t)(0xE00C)) +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DITHER1_DITHERCONTROL_RESET_VALUE 0x300222U +#define IMXDPUV1_DITHER1_DITHERCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT_MASK 0x7U +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT_SHIFT 0U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO8, Reduces blue component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO8 0x2U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO7, Reduces blue component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO7 0x3U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO6, Reduces blue component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO6 0x4U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO5, Reduces blue component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO5 0x5U +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT_MASK 0x70U +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT_SHIFT 4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO8, Reduces green component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO8 0x2U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO7, Reduces green component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO7 0x3U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO6, Reduces green component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO6 0x4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO5, Reduces green component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO5 0x5U +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT_MASK 0x700U +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT_SHIFT 8U +/* Field Value: RED_RANGE_SELECT__RED_10TO8, Reduces red component width from + * 10 bit to 8bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO8 0x2U +/* Field Value: RED_RANGE_SELECT__RED_10TO7, Reduces red component width from + * 10 bit to 7bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO7 0x3U +/* Field Value: RED_RANGE_SELECT__RED_10TO6, Reduces red component width from + * 10 bit to 6bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO6 0x4U +/* Field Value: RED_RANGE_SELECT__RED_10TO5, Reduces red component width from + * 10 bit to 5bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO5 0x5U +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT_MASK 0x10000U +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT_SHIFT 16U +/* Field Value: OFFSET_SELECT__OFFS_SPATIAL, Offset is a bayer matrix value, + * which is selected according to pixel frame position. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT__OFFS_SPATIAL 0U +/* Field Value: OFFSET_SELECT__OFFS_TEMPORAL, Offset is the sum from a bayer + * matrix value, which is selected according to pixel frame position, + * and a value from a regular sequence, which changes each frame. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT__OFFS_TEMPORAL 0x1U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT_MASK 0x300000U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT_SHIFT 20U +/* Field Value: ALGO_SELECT__NO_CORRECTION, Best possible resolution for most + * dark colors. Adds a diminutive offset to overall image brightness. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__NO_CORRECTION 0x1U +/* Field Value: ALGO_SELECT__BRIGHTNESS_CORRECTION, Preserves overall image + * brightness. Cannot resolve most dark and most bright colors. All codes + * in-between are distributed perfectly smooth. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__BRIGHTNESS_CORRECTION 0x2U +/* Field Value: ALGO_SELECT__CONTRAST_CORRECTION, Preserves overall image + * brightness. Best possible distribution of color codes over complete range. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__CONTRAST_CORRECTION 0x3U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE_MASK 0x3000000U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE_SHIFT 24U +/* Field Value: ALPHA_MODE__DISABLE, The alpha bit is not considered. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__DISABLE 0U +/* Field Value: ALPHA_MODE__ENABLE_BY1, Red, green and blue components are + * only dithered, if the alpha bit is 1. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__ENABLE_BY1 0x1U +/* Field Value: ALPHA_MODE__ENABLE_BY0, Red, green and blue components are + * only dithered, if the alpha bit is 0. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__ENABLE_BY0 0x2U + +/* Register: IMXDPUV1_dither1_Release */ +#define IMXDPUV1_DITHER1_RELEASE ((uint32_t)(0xE010)) +#define IMXDPUV1_DITHER1_RELEASE_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DITHER1_RELEASE_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_RELEASE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_RELEASE_SUBVERSION_MASK 0xFFU +#define IMXDPUV1_DITHER1_RELEASE_SUBVERSION_SHIFT 0U +#define IMXDPUV1_DITHER1_RELEASE_VERSION_MASK 0xFF00U +#define IMXDPUV1_DITHER1_RELEASE_VERSION_SHIFT 8U + +/* Register: IMXDPUV1_tcon1_SSqCnts */ +#define IMXDPUV1_TCON1_SSQCNTS ((uint32_t)(0xE400)) +#define IMXDPUV1_TCON1_SSQCNTS_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON1_SSQCNTS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SSQCNTS_RESET_MASK 0U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQY_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQY_SHIFT 0U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_FIELD_MASK 0x8000U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_FIELD_SHIFT 15U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQX_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQX_SHIFT 16U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_OUT_MASK 0x80000000U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_OUT_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_LockUnlock */ +#define IMXDPUV1_TCON1_LOCKUNLOCK ((uint32_t)(0xE800)) +#define IMXDPUV1_TCON1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_TCON1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_tcon1_LockStatus */ +#define IMXDPUV1_TCON1_LOCKSTATUS ((uint32_t)(0xE804)) +#define IMXDPUV1_TCON1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_TCON1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_TCON1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_TCON1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_TCON1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_TCON1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_TCON1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_tcon1_SSqCycle */ +#define IMXDPUV1_TCON1_SSQCYCLE ((uint32_t)(0xE808)) +#define IMXDPUV1_TCON1_SSQCYCLE_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_TCON1_SSQCYCLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SSQCYCLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SSQCYCLE_SSQCYCLE_MASK 0x3FU +#define IMXDPUV1_TCON1_SSQCYCLE_SSQCYCLE_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SWreset */ +#define IMXDPUV1_TCON1_SWRESET ((uint32_t)(0xE80C)) +#define IMXDPUV1_TCON1_SWRESET_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_TCON1_SWRESET_RESET_VALUE 0x3FC00410U +#define IMXDPUV1_TCON1_SWRESET_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SWRESET_SWRESET_MASK 0x1U +#define IMXDPUV1_TCON1_SWRESET_SWRESET_SHIFT 0U +/* Field Value: SWRESET__OPERATION, operation mode */ +#define IMXDPUV1_TCON1_SWRESET_SWRESET__OPERATION 0U +/* Field Value: SWRESET__SWRESET, So long SWReset = 0x1 tcon is in 'SW reset + * state' and it is released by internal logic (SWReset is released and + * end of frame arrived), read: 0b: reset not active 1b: reset active (that + * means NO pixel of video frame is excepted until 'SW reset state' + * is released) */ +#define IMXDPUV1_TCON1_SWRESET_SWRESET__SWRESET 0x1U +#define IMXDPUV1_TCON1_SWRESET_ENRESETWORD_MASK 0xFFF0U +#define IMXDPUV1_TCON1_SWRESET_ENRESETWORD_SHIFT 4U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDEND_MASK 0xFF0000U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDEND_SHIFT 16U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDSTART_MASK 0xFF000000U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDSTART_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_TCON_CTRL */ +#define IMXDPUV1_TCON1_TCON_CTRL ((uint32_t)(0xE810)) +#define IMXDPUV1_TCON1_TCON_CTRL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_TCON1_TCON_CTRL_RESET_VALUE 0x1401408U +#define IMXDPUV1_TCON1_TCON_CTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE_MASK 0x3U +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE_SHIFT 0U +/* Field Value: CHANNELMODE__SINGLE, Single pixel mode. Both channels channel + * are active at full pixel clock. If bitmap of both panels are the same, + * both panels are identical */ +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__SINGLE 0U +/* Field Value: CHANNELMODE__DUAL_INTERLEAVED, Dual pixel mode. Both channels + * are active at half the pixel clock. 1st channel drives display columns + * with even and 2nd one with odd index. */ +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__DUAL_INTERLEAVED 0x1U +/* Field Value: CHANNELMODE__DUAL_SPLIT, Dual pixel mode. Both channels are + * active at half the pixel clock. 1st channel drives the left and 2nd + * one the righ half of the display. Note : data_en is needed in this mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__DUAL_SPLIT 0x2U +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC_MASK 0x4U +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC_SHIFT 2U +/* Field Value: TCON_SYNC__H_VLAST, tcon timing generator synchronized to + * hlast, vlast */ +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC__H_VLAST 0U +/* Field Value: TCON_SYNC__H_VSYNC, tcon timing generator synchronized to + * hsync, vsync where horizontal synchronization is synchronized at the falling + * edge of hsync */ +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC__H_VSYNC 0x1U +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS_MASK 0x8U +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS_SHIFT 3U +/* Field Value: BYPASS__TCON_MODE, tcon operation mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS__TCON_MODE 0U +/* Field Value: BYPASS__BYPASS_MODE, tcon in Bypass mode. input pixel and + * its sync-signals are bypassed to tcon-output */ +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS__BYPASS_MODE 0x1U +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL_MASK 0xF0U +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL_SHIFT 4U +/* Field Value: INV_CTRL__DISABLE, Disable inversion control */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__DISABLE 0U +/* Field Value: INV_CTRL__RGB_2_BITS, Enable inversion control for number + * of RGB-Bits = 2 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_2_BITS 0x1U +/* Field Value: INV_CTRL__RGB_4_BITS, Enable inversion control for number + * of RGB-Bits = 4 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_4_BITS 0x2U +/* Field Value: INV_CTRL__RGB_6_BITS, Enable inversion control for number + * of RGB-Bits = 6 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_6_BITS 0x3U +/* Field Value: INV_CTRL__RGB_8_BITS, Enable inversion control for number + * of RGB-Bits = 8 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_8_BITS 0x4U +/* Field Value: INV_CTRL__RGB_10_BITS, Enable inversion control for number + * of RGB-Bits = 10 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_10_BITS 0x5U +/* Field Value: INV_CTRL__RGB_12_BITS, Enable inversion control for number + * of RGB-Bits = 12 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_12_BITS 0x6U +/* Field Value: INV_CTRL__RGB_14_BITS, Enable inversion control for number + * of RGB-Bits = 14 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_14_BITS 0x7U +/* Field Value: INV_CTRL__RGB_16_BITS, Enable inversion control for number + * of RGB-Bits = 16 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_16_BITS 0x8U +/* Field Value: INV_CTRL__RGB_18_BITS, Enable inversion control for number + * of RGB-Bits = 18 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_18_BITS 0x9U +/* Field Value: INV_CTRL__RGB_20_BITS, Enable inversion control for number + * of RGB-Bits = 20 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_20_BITS 0xAU +/* Field Value: INV_CTRL__RGB_22_BITS, Enable inversion control for number + * of RGB-Bits = 22 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_22_BITS 0xBU +/* Field Value: INV_CTRL__RGB_24_BITS, Enable inversion control for number + * of RGB-Bits = 24 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_24_BITS 0xCU +/* Field Value: INV_CTRL__RGB_26_BITS, Enable inversion control for number + * of RGB-Bits = 26 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_26_BITS 0xDU +/* Field Value: INV_CTRL__RGB_28_BITS, Enable inversion control for number + * of RGB-Bits = 28 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_28_BITS 0xEU +/* Field Value: INV_CTRL__RGB_30_BITS, Enable inversion control for number + * of RGB-Bits = 30 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_30_BITS 0xFU +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS_MASK 0x100U +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS_SHIFT 8U +/* Field Value: ENLVDS__ENABLE_LVDS, Enable LVDS , TTL and RSDS are disable + * */ +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS__ENABLE_LVDS 0x1U +/* Field Value: ENLVDS__DISABLE_LVDS, Disable LVDS, Enable TTL and RSDS */ +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS__DISABLE_LVDS 0U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE_MASK 0x200U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE_SHIFT 9U +/* Field Value: LVDSMODE__MINI_LVDS, MiniLVDS */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE__MINI_LVDS 0x1U +/* Field Value: LVDSMODE__LVDS, LVDS Mode, refered to OpenLDI */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE__LVDS 0U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE_MASK 0x400U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE_SHIFT 10U +/* Field Value: LVDS_BALANCE__BALANCED, LVDS operates in 24 bits Balanced + * Mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE__BALANCED 0x1U +/* Field Value: LVDS_BALANCE__UNBALANCED, LVDS operates in 24 bits Unbalanced + * Mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE__UNBALANCED 0U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV_MASK 0x800U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV_SHIFT 11U +/* Field Value: LVDS_CLOCK_INV__INV, Invert LVDS Clock */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV__INV 0x1U +/* Field Value: LVDS_CLOCK_INV__NON_INV, NON-Invert LVDS Clock */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV__NON_INV 0U +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE_MASK 0x7000U +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE_SHIFT 12U +/* Field Value: MINILVDS_OPCODE__MODE_3PAIRS, MiniLVDS operates in 6 and 8 + * bit data, three pairs */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_3PAIRS 0U +/* Field Value: MINILVDS_OPCODE__MODE_4PAIRS, Not Implemented */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS 0x1U +/* Field Value: MINILVDS_OPCODE__MODE_5PAIRS, Not Implemented */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_5PAIRS 0x2U +/* Field Value: MINILVDS_OPCODE__MODE_6PAIRS, MiniLVDS operates in 6 and 8 + * bit data, six pairs */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_6PAIRS 0x3U +/* Field Value: MINILVDS_OPCODE__RESERVED1, RESERVED1 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED1 0x4U +/* Field Value: MINILVDS_OPCODE__RESERVED2, RESERVED2 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED2 0x5U +/* Field Value: MINILVDS_OPCODE__RESERVED3, RESERVED3 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED3 0x6U +/* Field Value: MINILVDS_OPCODE__RESERVED4, RESERVED4 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED4 0x7U +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP_MASK 0x8000U +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP_SHIFT 15U +/* Field Value: DUAL_SWAP__SWAP, swapping pixels between lower-channel and + * upper-channel */ +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP__SWAP 0x1U +/* Field Value: DUAL_SWAP__NON_SWAP, NON-swapping pixels between lower-channel + * and upper-channel */ +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP__NON_SWAP 0U +#define IMXDPUV1_TCON1_TCON_CTRL_SPLITPOSITION_MASK 0x3FFF0000U +#define IMXDPUV1_TCON1_TCON_CTRL_SPLITPOSITION_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_RSDSInvCtrl */ +#define IMXDPUV1_TCON1_RSDSINVCTRL ((uint32_t)(0xE814)) +#define IMXDPUV1_TCON1_RSDSINVCTRL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_TCON1_RSDSINVCTRL_RESET_VALUE 0U +#define IMXDPUV1_TCON1_RSDSINVCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_MASK 0x7FFFU +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_SHIFT 0U +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_DUAL_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_MapBit3_0 */ +#define IMXDPUV1_TCON1_MAPBIT3_0 ((uint32_t)(0xE818)) +#define IMXDPUV1_TCON1_MAPBIT3_0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_TCON1_MAPBIT3_0_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON1_MAPBIT3_0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT0_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT0_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT1_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT1_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT2_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT2_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT3_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT3_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit7_4 */ +#define IMXDPUV1_TCON1_MAPBIT7_4 ((uint32_t)(0xE81C)) +#define IMXDPUV1_TCON1_MAPBIT7_4_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_TCON1_MAPBIT7_4_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON1_MAPBIT7_4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT4_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT4_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT5_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT5_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT6_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT6_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT7_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT7_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit11_8 */ +#define IMXDPUV1_TCON1_MAPBIT11_8 ((uint32_t)(0xE820)) +#define IMXDPUV1_TCON1_MAPBIT11_8_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_TCON1_MAPBIT11_8_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON1_MAPBIT11_8_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT8_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT8_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT9_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT9_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT10_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT10_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT11_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT11_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit15_12 */ +#define IMXDPUV1_TCON1_MAPBIT15_12 ((uint32_t)(0xE824)) +#define IMXDPUV1_TCON1_MAPBIT15_12_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_TCON1_MAPBIT15_12_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON1_MAPBIT15_12_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT12_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT12_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT13_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT13_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT14_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT14_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT15_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT15_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit19_16 */ +#define IMXDPUV1_TCON1_MAPBIT19_16 ((uint32_t)(0xE828)) +#define IMXDPUV1_TCON1_MAPBIT19_16_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_TCON1_MAPBIT19_16_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON1_MAPBIT19_16_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT16_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT16_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT17_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT17_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT18_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT18_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT19_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT19_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit23_20 */ +#define IMXDPUV1_TCON1_MAPBIT23_20 ((uint32_t)(0xE82C)) +#define IMXDPUV1_TCON1_MAPBIT23_20_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_TCON1_MAPBIT23_20_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON1_MAPBIT23_20_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT20_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT20_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT21_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT21_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT22_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT22_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT23_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT23_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit27_24 */ +#define IMXDPUV1_TCON1_MAPBIT27_24 ((uint32_t)(0xE830)) +#define IMXDPUV1_TCON1_MAPBIT27_24_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_TCON1_MAPBIT27_24_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON1_MAPBIT27_24_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT24_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT24_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT25_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT25_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT26_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT26_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT27_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT27_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit31_28 */ +#define IMXDPUV1_TCON1_MAPBIT31_28 ((uint32_t)(0xE834)) +#define IMXDPUV1_TCON1_MAPBIT31_28_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_TCON1_MAPBIT31_28_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON1_MAPBIT31_28_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT28_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT28_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT29_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT29_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT30_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT30_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT31_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT31_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit34_32 */ +#define IMXDPUV1_TCON1_MAPBIT34_32 ((uint32_t)(0xE838)) +#define IMXDPUV1_TCON1_MAPBIT34_32_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_TCON1_MAPBIT34_32_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON1_MAPBIT34_32_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT32_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT32_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT33_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT33_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT34_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT34_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_MapBit3_0_Dual */ +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL ((uint32_t)(0xE83C)) +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT0_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT0_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT1_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT1_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT2_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT2_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT3_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT3_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit7_4_Dual */ +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL ((uint32_t)(0xE840)) +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT4_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT4_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT5_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT5_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT6_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT6_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT7_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT7_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit11_8_Dual */ +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL ((uint32_t)(0xE844)) +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT8_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT8_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT9_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT9_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT10_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT10_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT11_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT11_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit15_12_Dual */ +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL ((uint32_t)(0xE848)) +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT12_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT12_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT13_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT13_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT14_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT14_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT15_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT15_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit19_16_Dual */ +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL ((uint32_t)(0xE84C)) +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT16_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT16_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT17_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT17_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT18_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT18_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT19_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT19_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit23_20_Dual */ +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL ((uint32_t)(0xE850)) +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT20_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT20_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT21_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT21_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT22_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT22_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT23_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT23_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit27_24_Dual */ +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL ((uint32_t)(0xE854)) +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT24_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT24_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT25_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT25_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT26_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT26_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT27_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT27_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit31_28_Dual */ +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL ((uint32_t)(0xE858)) +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT28_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT28_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT29_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT29_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT30_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT30_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT31_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT31_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit34_32_Dual */ +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL ((uint32_t)(0xE85C)) +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT32_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT32_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT33_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT33_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT34_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT34_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_SPG0PosOn */ +#define IMXDPUV1_TCON1_SPG0POSON ((uint32_t)(0xE860)) +#define IMXDPUV1_TCON1_SPG0POSON_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_TCON1_SPG0POSON_RESET_VALUE 0x1480000U +#define IMXDPUV1_TCON1_SPG0POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_Y0_SHIFT 0U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_X0_SHIFT 16U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG0MaskOn */ +#define IMXDPUV1_TCON1_SPG0MASKON ((uint32_t)(0xE864)) +#define IMXDPUV1_TCON1_SPG0MASKON_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_TCON1_SPG0MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG0MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKON_SPGMKON0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKON_SPGMKON0_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG0PosOff */ +#define IMXDPUV1_TCON1_SPG0POSOFF ((uint32_t)(0xE868)) +#define IMXDPUV1_TCON1_SPG0POSOFF_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_TCON1_SPG0POSOFF_RESET_VALUE 0x1680000U +#define IMXDPUV1_TCON1_SPG0POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_Y0_SHIFT 0U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_X0_SHIFT 16U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG0MaskOff */ +#define IMXDPUV1_TCON1_SPG0MASKOFF ((uint32_t)(0xE86C)) +#define IMXDPUV1_TCON1_SPG0MASKOFF_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_TCON1_SPG0MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG0MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKOFF_SPGMKOFF0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKOFF_SPGMKOFF0_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG1PosOn */ +#define IMXDPUV1_TCON1_SPG1POSON ((uint32_t)(0xE870)) +#define IMXDPUV1_TCON1_SPG1POSON_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_TCON1_SPG1POSON_RESET_VALUE 0xF3U +#define IMXDPUV1_TCON1_SPG1POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_Y1_SHIFT 0U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_X1_SHIFT 16U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG1MaskOn */ +#define IMXDPUV1_TCON1_SPG1MASKON ((uint32_t)(0xE874)) +#define IMXDPUV1_TCON1_SPG1MASKON_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_TCON1_SPG1MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKON_SPGMKON1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKON_SPGMKON1_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG1PosOff */ +#define IMXDPUV1_TCON1_SPG1POSOFF ((uint32_t)(0xE878)) +#define IMXDPUV1_TCON1_SPG1POSOFF_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_TCON1_SPG1POSOFF_RESET_VALUE 0xF7U +#define IMXDPUV1_TCON1_SPG1POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_Y1_SHIFT 0U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_X1_SHIFT 16U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG1MaskOff */ +#define IMXDPUV1_TCON1_SPG1MASKOFF ((uint32_t)(0xE87C)) +#define IMXDPUV1_TCON1_SPG1MASKOFF_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_TCON1_SPG1MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKOFF_SPGMKOFF1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKOFF_SPGMKOFF1_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG2PosOn */ +#define IMXDPUV1_TCON1_SPG2POSON ((uint32_t)(0xE880)) +#define IMXDPUV1_TCON1_SPG2POSON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_TCON1_SPG2POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG2POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_Y2_SHIFT 0U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_X2_SHIFT 16U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG2MaskOn */ +#define IMXDPUV1_TCON1_SPG2MASKON ((uint32_t)(0xE884)) +#define IMXDPUV1_TCON1_SPG2MASKON_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_TCON1_SPG2MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG2MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKON_SPGMKON2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKON_SPGMKON2_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG2PosOff */ +#define IMXDPUV1_TCON1_SPG2POSOFF ((uint32_t)(0xE888)) +#define IMXDPUV1_TCON1_SPG2POSOFF_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_TCON1_SPG2POSOFF_RESET_VALUE 0x1400000U +#define IMXDPUV1_TCON1_SPG2POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_Y2_SHIFT 0U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_X2_SHIFT 16U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG2MaskOff */ +#define IMXDPUV1_TCON1_SPG2MASKOFF ((uint32_t)(0xE88C)) +#define IMXDPUV1_TCON1_SPG2MASKOFF_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_TCON1_SPG2MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG2MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKOFF_SPGMKOFF2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKOFF_SPGMKOFF2_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG3PosOn */ +#define IMXDPUV1_TCON1_SPG3POSON ((uint32_t)(0xE890)) +#define IMXDPUV1_TCON1_SPG3POSON_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_TCON1_SPG3POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG3POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_Y3_SHIFT 0U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_X3_SHIFT 16U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG3MaskOn */ +#define IMXDPUV1_TCON1_SPG3MASKON ((uint32_t)(0xE894)) +#define IMXDPUV1_TCON1_SPG3MASKON_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_TCON1_SPG3MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKON_SPGMKON3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKON_SPGMKON3_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG3PosOff */ +#define IMXDPUV1_TCON1_SPG3POSOFF ((uint32_t)(0xE898)) +#define IMXDPUV1_TCON1_SPG3POSOFF_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_TCON1_SPG3POSOFF_RESET_VALUE 0xF0U +#define IMXDPUV1_TCON1_SPG3POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_Y3_SHIFT 0U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_X3_SHIFT 16U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG3MaskOff */ +#define IMXDPUV1_TCON1_SPG3MASKOFF ((uint32_t)(0xE89C)) +#define IMXDPUV1_TCON1_SPG3MASKOFF_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_TCON1_SPG3MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKOFF_SPGMKOFF3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKOFF_SPGMKOFF3_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG4PosOn */ +#define IMXDPUV1_TCON1_SPG4POSON ((uint32_t)(0xE8A0)) +#define IMXDPUV1_TCON1_SPG4POSON_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_TCON1_SPG4POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_Y4_SHIFT 0U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_X4_SHIFT 16U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG4MaskOn */ +#define IMXDPUV1_TCON1_SPG4MASKON ((uint32_t)(0xE8A4)) +#define IMXDPUV1_TCON1_SPG4MASKON_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_TCON1_SPG4MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKON_SPGMKON4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKON_SPGMKON4_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG4PosOff */ +#define IMXDPUV1_TCON1_SPG4POSOFF ((uint32_t)(0xE8A8)) +#define IMXDPUV1_TCON1_SPG4POSOFF_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_TCON1_SPG4POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_Y4_SHIFT 0U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_X4_SHIFT 16U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG4MaskOff */ +#define IMXDPUV1_TCON1_SPG4MASKOFF ((uint32_t)(0xE8AC)) +#define IMXDPUV1_TCON1_SPG4MASKOFF_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_TCON1_SPG4MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKOFF_SPGMKOFF4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKOFF_SPGMKOFF4_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG5PosOn */ +#define IMXDPUV1_TCON1_SPG5POSON ((uint32_t)(0xE8B0)) +#define IMXDPUV1_TCON1_SPG5POSON_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_TCON1_SPG5POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_Y5_SHIFT 0U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_X5_SHIFT 16U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG5MaskOn */ +#define IMXDPUV1_TCON1_SPG5MASKON ((uint32_t)(0xE8B4)) +#define IMXDPUV1_TCON1_SPG5MASKON_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_TCON1_SPG5MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKON_SPGMKON5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKON_SPGMKON5_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG5PosOff */ +#define IMXDPUV1_TCON1_SPG5POSOFF ((uint32_t)(0xE8B8)) +#define IMXDPUV1_TCON1_SPG5POSOFF_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_TCON1_SPG5POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_Y5_SHIFT 0U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_X5_SHIFT 16U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG5MaskOff */ +#define IMXDPUV1_TCON1_SPG5MASKOFF ((uint32_t)(0xE8BC)) +#define IMXDPUV1_TCON1_SPG5MASKOFF_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_TCON1_SPG5MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKOFF_SPGMKOFF5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKOFF_SPGMKOFF5_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG6PosOn */ +#define IMXDPUV1_TCON1_SPG6POSON ((uint32_t)(0xE8C0)) +#define IMXDPUV1_TCON1_SPG6POSON_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_TCON1_SPG6POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_Y6_SHIFT 0U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_X6_SHIFT 16U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG6MaskOn */ +#define IMXDPUV1_TCON1_SPG6MASKON ((uint32_t)(0xE8C4)) +#define IMXDPUV1_TCON1_SPG6MASKON_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_TCON1_SPG6MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKON_SPGMKON6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKON_SPGMKON6_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG6PosOff */ +#define IMXDPUV1_TCON1_SPG6POSOFF ((uint32_t)(0xE8C8)) +#define IMXDPUV1_TCON1_SPG6POSOFF_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_TCON1_SPG6POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_Y6_SHIFT 0U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_X6_SHIFT 16U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG6MaskOff */ +#define IMXDPUV1_TCON1_SPG6MASKOFF ((uint32_t)(0xE8CC)) +#define IMXDPUV1_TCON1_SPG6MASKOFF_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_TCON1_SPG6MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKOFF_SPGMKOFF6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKOFF_SPGMKOFF6_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG7PosOn */ +#define IMXDPUV1_TCON1_SPG7POSON ((uint32_t)(0xE8D0)) +#define IMXDPUV1_TCON1_SPG7POSON_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_TCON1_SPG7POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_Y7_SHIFT 0U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_X7_SHIFT 16U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG7MaskOn */ +#define IMXDPUV1_TCON1_SPG7MASKON ((uint32_t)(0xE8D4)) +#define IMXDPUV1_TCON1_SPG7MASKON_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_TCON1_SPG7MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKON_SPGMKON7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKON_SPGMKON7_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG7PosOff */ +#define IMXDPUV1_TCON1_SPG7POSOFF ((uint32_t)(0xE8D8)) +#define IMXDPUV1_TCON1_SPG7POSOFF_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_TCON1_SPG7POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_Y7_SHIFT 0U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_X7_SHIFT 16U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG7MaskOff */ +#define IMXDPUV1_TCON1_SPG7MASKOFF ((uint32_t)(0xE8DC)) +#define IMXDPUV1_TCON1_SPG7MASKOFF_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_TCON1_SPG7MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKOFF_SPGMKOFF7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKOFF_SPGMKOFF7_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG8PosOn */ +#define IMXDPUV1_TCON1_SPG8POSON ((uint32_t)(0xE8E0)) +#define IMXDPUV1_TCON1_SPG8POSON_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_TCON1_SPG8POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_Y8_SHIFT 0U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_X8_SHIFT 16U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG8MaskOn */ +#define IMXDPUV1_TCON1_SPG8MASKON ((uint32_t)(0xE8E4)) +#define IMXDPUV1_TCON1_SPG8MASKON_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_TCON1_SPG8MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKON_SPGMKON8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKON_SPGMKON8_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG8PosOff */ +#define IMXDPUV1_TCON1_SPG8POSOFF ((uint32_t)(0xE8E8)) +#define IMXDPUV1_TCON1_SPG8POSOFF_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_TCON1_SPG8POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_Y8_SHIFT 0U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_X8_SHIFT 16U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG8MaskOff */ +#define IMXDPUV1_TCON1_SPG8MASKOFF ((uint32_t)(0xE8EC)) +#define IMXDPUV1_TCON1_SPG8MASKOFF_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_TCON1_SPG8MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKOFF_SPGMKOFF8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKOFF_SPGMKOFF8_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG9PosOn */ +#define IMXDPUV1_TCON1_SPG9POSON ((uint32_t)(0xE8F0)) +#define IMXDPUV1_TCON1_SPG9POSON_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_TCON1_SPG9POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_Y9_SHIFT 0U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_X9_SHIFT 16U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG9MaskOn */ +#define IMXDPUV1_TCON1_SPG9MASKON ((uint32_t)(0xE8F4)) +#define IMXDPUV1_TCON1_SPG9MASKON_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_TCON1_SPG9MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKON_SPGMKON9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKON_SPGMKON9_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG9PosOff */ +#define IMXDPUV1_TCON1_SPG9POSOFF ((uint32_t)(0xE8F8)) +#define IMXDPUV1_TCON1_SPG9POSOFF_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_TCON1_SPG9POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_Y9_SHIFT 0U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_X9_SHIFT 16U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG9MaskOff */ +#define IMXDPUV1_TCON1_SPG9MASKOFF ((uint32_t)(0xE8FC)) +#define IMXDPUV1_TCON1_SPG9MASKOFF_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_TCON1_SPG9MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKOFF_SPGMKOFF9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKOFF_SPGMKOFF9_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG10PosOn */ +#define IMXDPUV1_TCON1_SPG10POSON ((uint32_t)(0xE900)) +#define IMXDPUV1_TCON1_SPG10POSON_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_TCON1_SPG10POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_Y10_SHIFT 0U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_X10_SHIFT 16U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG10MaskOn */ +#define IMXDPUV1_TCON1_SPG10MASKON ((uint32_t)(0xE904)) +#define IMXDPUV1_TCON1_SPG10MASKON_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_TCON1_SPG10MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKON_SPGMKON10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKON_SPGMKON10_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG10PosOff */ +#define IMXDPUV1_TCON1_SPG10POSOFF ((uint32_t)(0xE908)) +#define IMXDPUV1_TCON1_SPG10POSOFF_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_TCON1_SPG10POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_Y10_SHIFT 0U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_X10_SHIFT 16U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG10MaskOff */ +#define IMXDPUV1_TCON1_SPG10MASKOFF ((uint32_t)(0xE90C)) +#define IMXDPUV1_TCON1_SPG10MASKOFF_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_TCON1_SPG10MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKOFF_SPGMKOFF10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKOFF_SPGMKOFF10_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG11PosOn */ +#define IMXDPUV1_TCON1_SPG11POSON ((uint32_t)(0xE910)) +#define IMXDPUV1_TCON1_SPG11POSON_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_TCON1_SPG11POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_Y11_SHIFT 0U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_X11_SHIFT 16U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG11MaskOn */ +#define IMXDPUV1_TCON1_SPG11MASKON ((uint32_t)(0xE914)) +#define IMXDPUV1_TCON1_SPG11MASKON_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_TCON1_SPG11MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKON_SPGMKON11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKON_SPGMKON11_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG11PosOff */ +#define IMXDPUV1_TCON1_SPG11POSOFF ((uint32_t)(0xE918)) +#define IMXDPUV1_TCON1_SPG11POSOFF_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_TCON1_SPG11POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_Y11_SHIFT 0U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_X11_SHIFT 16U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG11MaskOff */ +#define IMXDPUV1_TCON1_SPG11MASKOFF ((uint32_t)(0xE91C)) +#define IMXDPUV1_TCON1_SPG11MASKOFF_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_TCON1_SPG11MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKOFF_SPGMKOFF11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKOFF_SPGMKOFF11_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx0Sigs */ +#define IMXDPUV1_TCON1_SMX0SIGS ((uint32_t)(0xE920)) +#define IMXDPUV1_TCON1_SMX0SIGS_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_TCON1_SMX0SIGS_RESET_VALUE 0x2U +#define IMXDPUV1_TCON1_SMX0SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx0FctTable */ +#define IMXDPUV1_TCON1_SMX0FCTTABLE ((uint32_t)(0xE924)) +#define IMXDPUV1_TCON1_SMX0FCTTABLE_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_TCON1_SMX0FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON1_SMX0FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX0FCTTABLE_SMXFCT0_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX0FCTTABLE_SMXFCT0_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx1Sigs */ +#define IMXDPUV1_TCON1_SMX1SIGS ((uint32_t)(0xE928)) +#define IMXDPUV1_TCON1_SMX1SIGS_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_TCON1_SMX1SIGS_RESET_VALUE 0x3U +#define IMXDPUV1_TCON1_SMX1SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx1FctTable */ +#define IMXDPUV1_TCON1_SMX1FCTTABLE ((uint32_t)(0xE92C)) +#define IMXDPUV1_TCON1_SMX1FCTTABLE_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_TCON1_SMX1FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON1_SMX1FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX1FCTTABLE_SMXFCT1_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX1FCTTABLE_SMXFCT1_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx2Sigs */ +#define IMXDPUV1_TCON1_SMX2SIGS ((uint32_t)(0xE930)) +#define IMXDPUV1_TCON1_SMX2SIGS_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_TCON1_SMX2SIGS_RESET_VALUE 0x2CU +#define IMXDPUV1_TCON1_SMX2SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx2FctTable */ +#define IMXDPUV1_TCON1_SMX2FCTTABLE ((uint32_t)(0xE934)) +#define IMXDPUV1_TCON1_SMX2FCTTABLE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_TCON1_SMX2FCTTABLE_RESET_VALUE 0x8U +#define IMXDPUV1_TCON1_SMX2FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX2FCTTABLE_SMXFCT2_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX2FCTTABLE_SMXFCT2_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx3Sigs */ +#define IMXDPUV1_TCON1_SMX3SIGS ((uint32_t)(0xE938)) +#define IMXDPUV1_TCON1_SMX3SIGS_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_TCON1_SMX3SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX3SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx3FctTable */ +#define IMXDPUV1_TCON1_SMX3FCTTABLE ((uint32_t)(0xE93C)) +#define IMXDPUV1_TCON1_SMX3FCTTABLE_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_TCON1_SMX3FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX3FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX3FCTTABLE_SMXFCT3_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX3FCTTABLE_SMXFCT3_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx4Sigs */ +#define IMXDPUV1_TCON1_SMX4SIGS ((uint32_t)(0xE940)) +#define IMXDPUV1_TCON1_SMX4SIGS_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_TCON1_SMX4SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX4SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx4FctTable */ +#define IMXDPUV1_TCON1_SMX4FCTTABLE ((uint32_t)(0xE944)) +#define IMXDPUV1_TCON1_SMX4FCTTABLE_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_TCON1_SMX4FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX4FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX4FCTTABLE_SMXFCT4_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX4FCTTABLE_SMXFCT4_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx5Sigs */ +#define IMXDPUV1_TCON1_SMX5SIGS ((uint32_t)(0xE948)) +#define IMXDPUV1_TCON1_SMX5SIGS_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_TCON1_SMX5SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX5SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx5FctTable */ +#define IMXDPUV1_TCON1_SMX5FCTTABLE ((uint32_t)(0xE94C)) +#define IMXDPUV1_TCON1_SMX5FCTTABLE_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_TCON1_SMX5FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX5FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX5FCTTABLE_SMXFCT5_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX5FCTTABLE_SMXFCT5_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx6Sigs */ +#define IMXDPUV1_TCON1_SMX6SIGS ((uint32_t)(0xE950)) +#define IMXDPUV1_TCON1_SMX6SIGS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_TCON1_SMX6SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX6SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx6FctTable */ +#define IMXDPUV1_TCON1_SMX6FCTTABLE ((uint32_t)(0xE954)) +#define IMXDPUV1_TCON1_SMX6FCTTABLE_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_TCON1_SMX6FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX6FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX6FCTTABLE_SMXFCT6_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX6FCTTABLE_SMXFCT6_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx7Sigs */ +#define IMXDPUV1_TCON1_SMX7SIGS ((uint32_t)(0xE958)) +#define IMXDPUV1_TCON1_SMX7SIGS_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_TCON1_SMX7SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX7SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx7FctTable */ +#define IMXDPUV1_TCON1_SMX7FCTTABLE ((uint32_t)(0xE95C)) +#define IMXDPUV1_TCON1_SMX7FCTTABLE_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_TCON1_SMX7FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX7FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX7FCTTABLE_SMXFCT7_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX7FCTTABLE_SMXFCT7_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx8Sigs */ +#define IMXDPUV1_TCON1_SMX8SIGS ((uint32_t)(0xE960)) +#define IMXDPUV1_TCON1_SMX8SIGS_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_TCON1_SMX8SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX8SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx8FctTable */ +#define IMXDPUV1_TCON1_SMX8FCTTABLE ((uint32_t)(0xE964)) +#define IMXDPUV1_TCON1_SMX8FCTTABLE_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_TCON1_SMX8FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX8FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX8FCTTABLE_SMXFCT8_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX8FCTTABLE_SMXFCT8_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx9Sigs */ +#define IMXDPUV1_TCON1_SMX9SIGS ((uint32_t)(0xE968)) +#define IMXDPUV1_TCON1_SMX9SIGS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_TCON1_SMX9SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX9SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx9FctTable */ +#define IMXDPUV1_TCON1_SMX9FCTTABLE ((uint32_t)(0xE96C)) +#define IMXDPUV1_TCON1_SMX9FCTTABLE_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_TCON1_SMX9FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX9FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX9FCTTABLE_SMXFCT9_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX9FCTTABLE_SMXFCT9_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx10Sigs */ +#define IMXDPUV1_TCON1_SMX10SIGS ((uint32_t)(0xE970)) +#define IMXDPUV1_TCON1_SMX10SIGS_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_TCON1_SMX10SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX10SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx10FctTable */ +#define IMXDPUV1_TCON1_SMX10FCTTABLE ((uint32_t)(0xE974)) +#define IMXDPUV1_TCON1_SMX10FCTTABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_TCON1_SMX10FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX10FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX10FCTTABLE_SMXFCT10_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX10FCTTABLE_SMXFCT10_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx11Sigs */ +#define IMXDPUV1_TCON1_SMX11SIGS ((uint32_t)(0xE978)) +#define IMXDPUV1_TCON1_SMX11SIGS_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_TCON1_SMX11SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX11SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx11FctTable */ +#define IMXDPUV1_TCON1_SMX11FCTTABLE ((uint32_t)(0xE97C)) +#define IMXDPUV1_TCON1_SMX11FCTTABLE_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_TCON1_SMX11FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX11FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX11FCTTABLE_SMXFCT11_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX11FCTTABLE_SMXFCT11_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_Reset_Over_Unferflow */ +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW ((uint32_t)(0xE980)) +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_VALUE 0U +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_STATUS_MASK 0x1U +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_STATUS_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_Dual_Debug */ +#define IMXDPUV1_TCON1_DUAL_DEBUG ((uint32_t)(0xE984)) +#define IMXDPUV1_TCON1_DUAL_DEBUG_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_TCON1_DUAL_DEBUG_RESET_VALUE 0U +#define IMXDPUV1_TCON1_DUAL_DEBUG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_MASK 0x1U +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_SHIFT 0U +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_MASK 0x2U +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_SHIFT 1U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_MASK 0x10U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_SHIFT 4U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_MASK 0x20U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_SHIFT 5U + +/* Register: IMXDPUV1_sig1_LockUnlock */ +#define IMXDPUV1_SIG1_LOCKUNLOCK ((uint32_t)(0xEC00)) +#define IMXDPUV1_SIG1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_SIG1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_SIG1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_sig1_LockStatus */ +#define IMXDPUV1_SIG1_LOCKSTATUS ((uint32_t)(0xEC04)) +#define IMXDPUV1_SIG1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_SIG1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_SIG1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_SIG1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_SIG1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_SIG1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_SIG1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_SIG1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_sig1_StaticControl */ +#define IMXDPUV1_SIG1_STATICCONTROL ((uint32_t)(0xEC08)) +#define IMXDPUV1_SIG1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_SIG1_STATICCONTROL_RESET_VALUE 0x8000000U +#define IMXDPUV1_SIG1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_SIG1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL_MASK 0x10U +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL_SHIFT 4U +/* Field Value: SHDLDSEL__LOCAL, Shadows are loaded at start of frame for + * each evaluation window for which ShdLdReq has been set. */ +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL__LOCAL 0U +/* Field Value: SHDLDSEL__GLOBAL, Shadows of all evaluation windows are loaded + * synchronous to the display stream (shadow load token received on + * frame input port). */ +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL__GLOBAL 0x1U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRES_MASK 0xFF0000U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRES_SHIFT 16U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRESRESET_MASK 0xFF000000U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRESRESET_SHIFT 24U + +/* Register: IMXDPUV1_sig1_PanicColor */ +#define IMXDPUV1_SIG1_PANICCOLOR ((uint32_t)(0xEC0C)) +#define IMXDPUV1_SIG1_PANICCOLOR_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_SIG1_PANICCOLOR_RESET_VALUE 0U +#define IMXDPUV1_SIG1_PANICCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_PANICCOLOR_PANICALPHA_MASK 0x80U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICALPHA_SHIFT 7U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICBLUE_MASK 0xFF00U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICBLUE_SHIFT 8U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICGREEN_MASK 0xFF0000U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICGREEN_SHIFT 16U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICRED_MASK 0xFF000000U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICRED_SHIFT 24U + +/* Register: IMXDPUV1_sig1_EvalControl0 */ +#define IMXDPUV1_SIG1_EVALCONTROL0 ((uint32_t)(0xEC10)) +#define IMXDPUV1_SIG1_EVALCONTROL0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_SIG1_EVALCONTROL0_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL0_ENEVALWIN0_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENEVALWIN0_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENCRC0_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENCRC0_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAMASK0_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAMASK0_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAINV0_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAINV0_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENLOCALPANIC0_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENLOCALPANIC0_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENGLOBALPANIC0_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENGLOBALPANIC0_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft0 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT0 ((uint32_t)(0xEC14)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_XEVALUPPERLEFT0_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_XEVALUPPERLEFT0_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_YEVALUPPERLEFT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_YEVALUPPERLEFT0_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight0 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0 ((uint32_t)(0xEC18)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef0 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF0 ((uint32_t)(0xEC1C)) +#define IMXDPUV1_SIG1_SIGCRCREDREF0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_SIG1_SIGCRCREDREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF0_SIGCRCREDREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF0_SIGCRCREDREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef0 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF0 ((uint32_t)(0xEC20)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_SIGCRCGREENREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_SIGCRCGREENREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef0 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0 ((uint32_t)(0xEC24)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_SIGCRCBLUEREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_SIGCRCBLUEREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed0 */ +#define IMXDPUV1_SIG1_SIGCRCRED0 ((uint32_t)(0xEC28)) +#define IMXDPUV1_SIG1_SIGCRCRED0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_SIG1_SIGCRCRED0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED0_SIGCRCRED0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED0_SIGCRCRED0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen0 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN0 ((uint32_t)(0xEC2C)) +#define IMXDPUV1_SIG1_SIGCRCGREEN0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_SIG1_SIGCRCGREEN0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN0_SIGCRCGREEN0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN0_SIGCRCGREEN0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue0 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE0 ((uint32_t)(0xEC30)) +#define IMXDPUV1_SIG1_SIGCRCBLUE0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_SIG1_SIGCRCBLUE0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE0_SIGCRCBLUE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE0_SIGCRCBLUE0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl1 */ +#define IMXDPUV1_SIG1_EVALCONTROL1 ((uint32_t)(0xEC34)) +#define IMXDPUV1_SIG1_EVALCONTROL1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_SIG1_EVALCONTROL1_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL1_ENEVALWIN1_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENEVALWIN1_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENCRC1_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENCRC1_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAMASK1_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAMASK1_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAINV1_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAINV1_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENLOCALPANIC1_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENLOCALPANIC1_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENGLOBALPANIC1_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENGLOBALPANIC1_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft1 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT1 ((uint32_t)(0xEC38)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_XEVALUPPERLEFT1_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_XEVALUPPERLEFT1_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_YEVALUPPERLEFT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_YEVALUPPERLEFT1_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight1 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1 ((uint32_t)(0xEC3C)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef1 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF1 ((uint32_t)(0xEC40)) +#define IMXDPUV1_SIG1_SIGCRCREDREF1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_SIG1_SIGCRCREDREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF1_SIGCRCREDREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF1_SIGCRCREDREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef1 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF1 ((uint32_t)(0xEC44)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_SIGCRCGREENREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_SIGCRCGREENREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef1 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1 ((uint32_t)(0xEC48)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_SIGCRCBLUEREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_SIGCRCBLUEREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed1 */ +#define IMXDPUV1_SIG1_SIGCRCRED1 ((uint32_t)(0xEC4C)) +#define IMXDPUV1_SIG1_SIGCRCRED1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_SIG1_SIGCRCRED1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED1_SIGCRCRED1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED1_SIGCRCRED1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen1 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN1 ((uint32_t)(0xEC50)) +#define IMXDPUV1_SIG1_SIGCRCGREEN1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_SIG1_SIGCRCGREEN1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN1_SIGCRCGREEN1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN1_SIGCRCGREEN1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue1 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE1 ((uint32_t)(0xEC54)) +#define IMXDPUV1_SIG1_SIGCRCBLUE1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_SIG1_SIGCRCBLUE1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE1_SIGCRCBLUE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE1_SIGCRCBLUE1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl2 */ +#define IMXDPUV1_SIG1_EVALCONTROL2 ((uint32_t)(0xEC58)) +#define IMXDPUV1_SIG1_EVALCONTROL2_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_SIG1_EVALCONTROL2_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL2_ENEVALWIN2_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENEVALWIN2_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENCRC2_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENCRC2_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAMASK2_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAMASK2_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAINV2_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAINV2_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENLOCALPANIC2_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENLOCALPANIC2_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENGLOBALPANIC2_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENGLOBALPANIC2_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft2 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT2 ((uint32_t)(0xEC5C)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_XEVALUPPERLEFT2_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_XEVALUPPERLEFT2_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_YEVALUPPERLEFT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_YEVALUPPERLEFT2_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight2 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2 ((uint32_t)(0xEC60)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef2 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF2 ((uint32_t)(0xEC64)) +#define IMXDPUV1_SIG1_SIGCRCREDREF2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_SIG1_SIGCRCREDREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF2_SIGCRCREDREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF2_SIGCRCREDREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef2 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF2 ((uint32_t)(0xEC68)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_SIGCRCGREENREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_SIGCRCGREENREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef2 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2 ((uint32_t)(0xEC6C)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_SIGCRCBLUEREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_SIGCRCBLUEREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed2 */ +#define IMXDPUV1_SIG1_SIGCRCRED2 ((uint32_t)(0xEC70)) +#define IMXDPUV1_SIG1_SIGCRCRED2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_SIG1_SIGCRCRED2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED2_SIGCRCRED2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED2_SIGCRCRED2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen2 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN2 ((uint32_t)(0xEC74)) +#define IMXDPUV1_SIG1_SIGCRCGREEN2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_SIG1_SIGCRCGREEN2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN2_SIGCRCGREEN2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN2_SIGCRCGREEN2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue2 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE2 ((uint32_t)(0xEC78)) +#define IMXDPUV1_SIG1_SIGCRCBLUE2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_SIG1_SIGCRCBLUE2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE2_SIGCRCBLUE2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE2_SIGCRCBLUE2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl3 */ +#define IMXDPUV1_SIG1_EVALCONTROL3 ((uint32_t)(0xEC7C)) +#define IMXDPUV1_SIG1_EVALCONTROL3_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_SIG1_EVALCONTROL3_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL3_ENEVALWIN3_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENEVALWIN3_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENCRC3_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENCRC3_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAMASK3_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAMASK3_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAINV3_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAINV3_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENLOCALPANIC3_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENLOCALPANIC3_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENGLOBALPANIC3_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENGLOBALPANIC3_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft3 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT3 ((uint32_t)(0xEC80)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_XEVALUPPERLEFT3_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_XEVALUPPERLEFT3_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_YEVALUPPERLEFT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_YEVALUPPERLEFT3_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight3 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3 ((uint32_t)(0xEC84)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef3 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF3 ((uint32_t)(0xEC88)) +#define IMXDPUV1_SIG1_SIGCRCREDREF3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_SIG1_SIGCRCREDREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF3_SIGCRCREDREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF3_SIGCRCREDREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef3 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF3 ((uint32_t)(0xEC8C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_SIGCRCGREENREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_SIGCRCGREENREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef3 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3 ((uint32_t)(0xEC90)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_SIGCRCBLUEREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_SIGCRCBLUEREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed3 */ +#define IMXDPUV1_SIG1_SIGCRCRED3 ((uint32_t)(0xEC94)) +#define IMXDPUV1_SIG1_SIGCRCRED3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_SIG1_SIGCRCRED3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED3_SIGCRCRED3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED3_SIGCRCRED3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen3 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN3 ((uint32_t)(0xEC98)) +#define IMXDPUV1_SIG1_SIGCRCGREEN3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_SIG1_SIGCRCGREEN3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN3_SIGCRCGREEN3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN3_SIGCRCGREEN3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue3 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE3 ((uint32_t)(0xEC9C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE3_SIGCRCBLUE3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE3_SIGCRCBLUE3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl4 */ +#define IMXDPUV1_SIG1_EVALCONTROL4 ((uint32_t)(0xECA0)) +#define IMXDPUV1_SIG1_EVALCONTROL4_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_SIG1_EVALCONTROL4_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL4_ENEVALWIN4_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENEVALWIN4_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENCRC4_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENCRC4_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAMASK4_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAMASK4_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAINV4_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAINV4_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENLOCALPANIC4_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENLOCALPANIC4_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENGLOBALPANIC4_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENGLOBALPANIC4_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft4 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT4 ((uint32_t)(0xECA4)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_XEVALUPPERLEFT4_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_XEVALUPPERLEFT4_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_YEVALUPPERLEFT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_YEVALUPPERLEFT4_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight4 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4 ((uint32_t)(0xECA8)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef4 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF4 ((uint32_t)(0xECAC)) +#define IMXDPUV1_SIG1_SIGCRCREDREF4_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_SIG1_SIGCRCREDREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF4_SIGCRCREDREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF4_SIGCRCREDREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef4 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF4 ((uint32_t)(0xECB0)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_SIGCRCGREENREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_SIGCRCGREENREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef4 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4 ((uint32_t)(0xECB4)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_SIGCRCBLUEREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_SIGCRCBLUEREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed4 */ +#define IMXDPUV1_SIG1_SIGCRCRED4 ((uint32_t)(0xECB8)) +#define IMXDPUV1_SIG1_SIGCRCRED4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_SIG1_SIGCRCRED4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED4_SIGCRCRED4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED4_SIGCRCRED4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen4 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN4 ((uint32_t)(0xECBC)) +#define IMXDPUV1_SIG1_SIGCRCGREEN4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_SIG1_SIGCRCGREEN4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN4_SIGCRCGREEN4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN4_SIGCRCGREEN4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue4 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE4 ((uint32_t)(0xECC0)) +#define IMXDPUV1_SIG1_SIGCRCBLUE4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_SIG1_SIGCRCBLUE4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE4_SIGCRCBLUE4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE4_SIGCRCBLUE4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl5 */ +#define IMXDPUV1_SIG1_EVALCONTROL5 ((uint32_t)(0xECC4)) +#define IMXDPUV1_SIG1_EVALCONTROL5_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_SIG1_EVALCONTROL5_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL5_ENEVALWIN5_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENEVALWIN5_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENCRC5_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENCRC5_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAMASK5_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAMASK5_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAINV5_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAINV5_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENLOCALPANIC5_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENLOCALPANIC5_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENGLOBALPANIC5_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENGLOBALPANIC5_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft5 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT5 ((uint32_t)(0xECC8)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_XEVALUPPERLEFT5_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_XEVALUPPERLEFT5_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_YEVALUPPERLEFT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_YEVALUPPERLEFT5_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight5 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5 ((uint32_t)(0xECCC)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef5 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF5 ((uint32_t)(0xECD0)) +#define IMXDPUV1_SIG1_SIGCRCREDREF5_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_SIG1_SIGCRCREDREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF5_SIGCRCREDREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF5_SIGCRCREDREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef5 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF5 ((uint32_t)(0xECD4)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_SIGCRCGREENREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_SIGCRCGREENREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef5 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5 ((uint32_t)(0xECD8)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_SIGCRCBLUEREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_SIGCRCBLUEREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed5 */ +#define IMXDPUV1_SIG1_SIGCRCRED5 ((uint32_t)(0xECDC)) +#define IMXDPUV1_SIG1_SIGCRCRED5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_SIG1_SIGCRCRED5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED5_SIGCRCRED5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED5_SIGCRCRED5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen5 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN5 ((uint32_t)(0xECE0)) +#define IMXDPUV1_SIG1_SIGCRCGREEN5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_SIG1_SIGCRCGREEN5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN5_SIGCRCGREEN5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN5_SIGCRCGREEN5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue5 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE5 ((uint32_t)(0xECE4)) +#define IMXDPUV1_SIG1_SIGCRCBLUE5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_SIG1_SIGCRCBLUE5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE5_SIGCRCBLUE5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE5_SIGCRCBLUE5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl6 */ +#define IMXDPUV1_SIG1_EVALCONTROL6 ((uint32_t)(0xECE8)) +#define IMXDPUV1_SIG1_EVALCONTROL6_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_SIG1_EVALCONTROL6_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL6_ENEVALWIN6_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENEVALWIN6_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENCRC6_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENCRC6_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAMASK6_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAMASK6_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAINV6_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAINV6_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENLOCALPANIC6_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENLOCALPANIC6_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENGLOBALPANIC6_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENGLOBALPANIC6_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft6 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT6 ((uint32_t)(0xECEC)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_XEVALUPPERLEFT6_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_XEVALUPPERLEFT6_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_YEVALUPPERLEFT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_YEVALUPPERLEFT6_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight6 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6 ((uint32_t)(0xECF0)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef6 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF6 ((uint32_t)(0xECF4)) +#define IMXDPUV1_SIG1_SIGCRCREDREF6_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_SIG1_SIGCRCREDREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF6_SIGCRCREDREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF6_SIGCRCREDREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef6 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF6 ((uint32_t)(0xECF8)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_SIGCRCGREENREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_SIGCRCGREENREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef6 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6 ((uint32_t)(0xECFC)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_SIGCRCBLUEREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_SIGCRCBLUEREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed6 */ +#define IMXDPUV1_SIG1_SIGCRCRED6 ((uint32_t)(0xED00)) +#define IMXDPUV1_SIG1_SIGCRCRED6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_SIG1_SIGCRCRED6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED6_SIGCRCRED6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED6_SIGCRCRED6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen6 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN6 ((uint32_t)(0xED04)) +#define IMXDPUV1_SIG1_SIGCRCGREEN6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_SIG1_SIGCRCGREEN6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN6_SIGCRCGREEN6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN6_SIGCRCGREEN6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue6 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE6 ((uint32_t)(0xED08)) +#define IMXDPUV1_SIG1_SIGCRCBLUE6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_SIG1_SIGCRCBLUE6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE6_SIGCRCBLUE6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE6_SIGCRCBLUE6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl7 */ +#define IMXDPUV1_SIG1_EVALCONTROL7 ((uint32_t)(0xED0C)) +#define IMXDPUV1_SIG1_EVALCONTROL7_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_SIG1_EVALCONTROL7_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL7_ENEVALWIN7_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENEVALWIN7_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENCRC7_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENCRC7_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAMASK7_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAMASK7_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAINV7_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAINV7_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENLOCALPANIC7_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENLOCALPANIC7_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENGLOBALPANIC7_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENGLOBALPANIC7_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft7 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT7 ((uint32_t)(0xED10)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_XEVALUPPERLEFT7_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_XEVALUPPERLEFT7_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_YEVALUPPERLEFT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_YEVALUPPERLEFT7_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight7 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7 ((uint32_t)(0xED14)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef7 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF7 ((uint32_t)(0xED18)) +#define IMXDPUV1_SIG1_SIGCRCREDREF7_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_SIG1_SIGCRCREDREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF7_SIGCRCREDREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF7_SIGCRCREDREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef7 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF7 ((uint32_t)(0xED1C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_SIGCRCGREENREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_SIGCRCGREENREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef7 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7 ((uint32_t)(0xED20)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_SIGCRCBLUEREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_SIGCRCBLUEREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed7 */ +#define IMXDPUV1_SIG1_SIGCRCRED7 ((uint32_t)(0xED24)) +#define IMXDPUV1_SIG1_SIGCRCRED7_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_SIG1_SIGCRCRED7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED7_SIGCRCRED7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED7_SIGCRCRED7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen7 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN7 ((uint32_t)(0xED28)) +#define IMXDPUV1_SIG1_SIGCRCGREEN7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_SIG1_SIGCRCGREEN7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN7_SIGCRCGREEN7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN7_SIGCRCGREEN7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue7 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE7 ((uint32_t)(0xED2C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE7_SIGCRCBLUE7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE7_SIGCRCBLUE7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_ShadowLoad */ +#define IMXDPUV1_SIG1_SHADOWLOAD ((uint32_t)(0xED30)) +#define IMXDPUV1_SIG1_SHADOWLOAD_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_SIG1_SHADOWLOAD_RESET_VALUE 0U +#define IMXDPUV1_SIG1_SHADOWLOAD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SHADOWLOAD_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_SIG1_SHADOWLOAD_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_sig1_ContinuousMode */ +#define IMXDPUV1_SIG1_CONTINUOUSMODE ((uint32_t)(0xED34)) +#define IMXDPUV1_SIG1_CONTINUOUSMODE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_SIG1_CONTINUOUSMODE_RESET_VALUE 0U +#define IMXDPUV1_SIG1_CONTINUOUSMODE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_CONTINUOUSMODE_ENCONT_MASK 0x1U +#define IMXDPUV1_SIG1_CONTINUOUSMODE_ENCONT_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SoftwareKick */ +#define IMXDPUV1_SIG1_SOFTWAREKICK ((uint32_t)(0xED38)) +#define IMXDPUV1_SIG1_SOFTWAREKICK_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_SIG1_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_SIG1_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_SIG1_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_sig1_Status */ +#define IMXDPUV1_SIG1_STATUS ((uint32_t)(0xED3C)) +#define IMXDPUV1_SIG1_STATUS_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_SIG1_STATUS_RESET_VALUE 0x100000U +#define IMXDPUV1_SIG1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_STATUS_STSSIGERROR_MASK 0xFFU +#define IMXDPUV1_SIG1_STATUS_STSSIGERROR_SHIFT 0U +#define IMXDPUV1_SIG1_STATUS_STSSIGVALID_MASK 0x10000U +#define IMXDPUV1_SIG1_STATUS_STSSIGVALID_SHIFT 16U +#define IMXDPUV1_SIG1_STATUS_STSSIGIDLE_MASK 0x100000U +#define IMXDPUV1_SIG1_STATUS_STSSIGIDLE_SHIFT 20U + +/* Register: IMXDPUV1_DPUXPC_Control */ +#define IMXDPUV1_DPUXPC_CONTROL ((uint32_t)(0xF000)) +#define IMXDPUV1_DPUXPC_CONTROL_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DPUXPC_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_CONTROL_ENABLE_MASK 0x1U +#define IMXDPUV1_DPUXPC_CONTROL_ENABLE_SHIFT 0U +#define IMXDPUV1_DPUXPC_CONTROL_MODE_MASK 0x6U +#define IMXDPUV1_DPUXPC_CONTROL_MODE_SHIFT 1U +/* Field Value: MODE__XPC_MODE_MANUAL, Manual measurement end */ +#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_MANUAL 0U +/* Field Value: MODE__XPC_MODE_TIMER, Timer controlled measurement end */ +#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_TIMER 0x1U +/* Field Value: MODE__XPC_MODE_CONTINUOUS, Continuous measurement; retriggered + * by reading SW_Tag register */ +#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_CONTINUOUS 0x2U +#define IMXDPUV1_DPUXPC_CONTROL_INCREMENTMODE_MASK 0x40000000U +#define IMXDPUV1_DPUXPC_CONTROL_INCREMENTMODE_SHIFT 30U +#define IMXDPUV1_DPUXPC_CONTROL_OTCDISABLE_MASK 0x80000000U +#define IMXDPUV1_DPUXPC_CONTROL_OTCDISABLE_SHIFT 31U + +/* Register: IMXDPUV1_DPUXPC_Timer */ +#define IMXDPUV1_DPUXPC_TIMER ((uint32_t)(0xF004)) +#define IMXDPUV1_DPUXPC_TIMER_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DPUXPC_TIMER_RESET_VALUE 0xFFFFFFFU +#define IMXDPUV1_DPUXPC_TIMER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_TIMER_LOAD_MASK 0xFFFFFFFU +#define IMXDPUV1_DPUXPC_TIMER_LOAD_SHIFT 0U +#define IMXDPUV1_DPUXPC_TIMER_DIVIDER_MASK 0xF0000000U +#define IMXDPUV1_DPUXPC_TIMER_DIVIDER_SHIFT 28U + +/* Register: IMXDPUV1_DPUXPC_MeasurementTimeControl */ +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL ((uint32_t)(0xF008)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTDIVIDER_MASK 0xFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTDIVIDER_SHIFT 0U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTENABLE_MASK 0x80000000U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTENABLE_SHIFT 31U + +/* Register: IMXDPUV1_DPUXPC_SW_Tag */ +#define IMXDPUV1_DPUXPC_SW_TAG ((uint32_t)(0xF00C)) +#define IMXDPUV1_DPUXPC_SW_TAG_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DPUXPC_SW_TAG_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_SW_TAG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_SW_TAG_TAG_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_SW_TAG_TAG_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MeasurementTime */ +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME ((uint32_t)(0xF010)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_TIME_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_TIME_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_Global_Counter */ +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER ((uint32_t)(0xF014)) +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_GLOBAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_GLOBAL_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Switch */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH ((uint32_t)(0xF018)) +#define IMXDPUV1_DPUXPC_MU00_SWITCH_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_DPUXPC_MU00_SWITCH_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT_SHIFT 0U +/* Field Value: MU00_SELECT__MU00_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC00 0U +/* Field Value: MU00_SELECT__MU00_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC01 0x1U +/* Field Value: MU00_SELECT__MU00_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC02 0x2U +/* Field Value: MU00_SELECT__MU00_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC03 0x3U +/* Field Value: MU00_SELECT__MU00_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC04 0x4U +/* Field Value: MU00_SELECT__MU00_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC05 0x5U +/* Field Value: MU00_SELECT__MU00_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC06 0x6U +/* Field Value: MU00_SELECT__MU00_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC07 0x7U +/* Field Value: MU00_SELECT__MU00_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC08 0x8U +/* Field Value: MU00_SELECT__MU00_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC09 0x9U +/* Field Value: MU00_SELECT__MU00_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC10 0xAU +/* Field Value: MU00_SELECT__MU00_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC11 0xBU +/* Field Value: MU00_SELECT__MU00_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC12 0xCU +/* Field Value: MU00_SELECT__MU00_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC13 0xDU +/* Field Value: MU00_SELECT__MU00_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC14 0xEU +/* Field Value: MU00_SELECT__MU00_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC15 0xFU +/* Field Value: MU00_SELECT__MU00_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC16 0x10U +/* Field Value: MU00_SELECT__MU00_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU00_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER ((uint32_t)(0xF01C)) +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_MU00_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_MU00_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER ((uint32_t)(0xF020)) +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_MU00_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_MU00_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER ((uint32_t)(0xF024)) +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_MU00_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_MU00_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER ((uint32_t)(0xF028)) +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER ((uint32_t)(0xF02C)) +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_MU00_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_MU00_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Switch */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH ((uint32_t)(0xF030)) +#define IMXDPUV1_DPUXPC_MU01_SWITCH_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_DPUXPC_MU01_SWITCH_RESET_VALUE 0x1U +#define IMXDPUV1_DPUXPC_MU01_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT_SHIFT 0U +/* Field Value: MU01_SELECT__MU01_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC00 0U +/* Field Value: MU01_SELECT__MU01_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC01 0x1U +/* Field Value: MU01_SELECT__MU01_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC02 0x2U +/* Field Value: MU01_SELECT__MU01_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC03 0x3U +/* Field Value: MU01_SELECT__MU01_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC04 0x4U +/* Field Value: MU01_SELECT__MU01_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC05 0x5U +/* Field Value: MU01_SELECT__MU01_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC06 0x6U +/* Field Value: MU01_SELECT__MU01_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC07 0x7U +/* Field Value: MU01_SELECT__MU01_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC08 0x8U +/* Field Value: MU01_SELECT__MU01_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC09 0x9U +/* Field Value: MU01_SELECT__MU01_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC10 0xAU +/* Field Value: MU01_SELECT__MU01_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC11 0xBU +/* Field Value: MU01_SELECT__MU01_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC12 0xCU +/* Field Value: MU01_SELECT__MU01_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC13 0xDU +/* Field Value: MU01_SELECT__MU01_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC14 0xEU +/* Field Value: MU01_SELECT__MU01_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC15 0xFU +/* Field Value: MU01_SELECT__MU01_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC16 0x10U +/* Field Value: MU01_SELECT__MU01_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU01_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER ((uint32_t)(0xF034)) +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_MU01_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_MU01_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER ((uint32_t)(0xF038)) +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_MU01_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_MU01_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER ((uint32_t)(0xF03C)) +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_MU01_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_MU01_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER ((uint32_t)(0xF040)) +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER ((uint32_t)(0xF044)) +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_MU01_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_MU01_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Switch */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH ((uint32_t)(0xF048)) +#define IMXDPUV1_DPUXPC_MU02_SWITCH_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_DPUXPC_MU02_SWITCH_RESET_VALUE 0x2U +#define IMXDPUV1_DPUXPC_MU02_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT_SHIFT 0U +/* Field Value: MU02_SELECT__MU02_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC00 0U +/* Field Value: MU02_SELECT__MU02_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC01 0x1U +/* Field Value: MU02_SELECT__MU02_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC02 0x2U +/* Field Value: MU02_SELECT__MU02_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC03 0x3U +/* Field Value: MU02_SELECT__MU02_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC04 0x4U +/* Field Value: MU02_SELECT__MU02_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC05 0x5U +/* Field Value: MU02_SELECT__MU02_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC06 0x6U +/* Field Value: MU02_SELECT__MU02_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC07 0x7U +/* Field Value: MU02_SELECT__MU02_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC08 0x8U +/* Field Value: MU02_SELECT__MU02_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC09 0x9U +/* Field Value: MU02_SELECT__MU02_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC10 0xAU +/* Field Value: MU02_SELECT__MU02_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC11 0xBU +/* Field Value: MU02_SELECT__MU02_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC12 0xCU +/* Field Value: MU02_SELECT__MU02_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC13 0xDU +/* Field Value: MU02_SELECT__MU02_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC14 0xEU +/* Field Value: MU02_SELECT__MU02_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC15 0xFU +/* Field Value: MU02_SELECT__MU02_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC16 0x10U +/* Field Value: MU02_SELECT__MU02_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU02_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER ((uint32_t)(0xF04C)) +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_MU02_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_MU02_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER ((uint32_t)(0xF050)) +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_MU02_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_MU02_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER ((uint32_t)(0xF054)) +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_MU02_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_MU02_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER ((uint32_t)(0xF058)) +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER ((uint32_t)(0xF05C)) +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_MU02_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_MU02_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Switch */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH ((uint32_t)(0xF060)) +#define IMXDPUV1_DPUXPC_MU03_SWITCH_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_DPUXPC_MU03_SWITCH_RESET_VALUE 0x3U +#define IMXDPUV1_DPUXPC_MU03_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT_SHIFT 0U +/* Field Value: MU03_SELECT__MU03_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC00 0U +/* Field Value: MU03_SELECT__MU03_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC01 0x1U +/* Field Value: MU03_SELECT__MU03_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC02 0x2U +/* Field Value: MU03_SELECT__MU03_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC03 0x3U +/* Field Value: MU03_SELECT__MU03_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC04 0x4U +/* Field Value: MU03_SELECT__MU03_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC05 0x5U +/* Field Value: MU03_SELECT__MU03_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC06 0x6U +/* Field Value: MU03_SELECT__MU03_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC07 0x7U +/* Field Value: MU03_SELECT__MU03_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC08 0x8U +/* Field Value: MU03_SELECT__MU03_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC09 0x9U +/* Field Value: MU03_SELECT__MU03_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC10 0xAU +/* Field Value: MU03_SELECT__MU03_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC11 0xBU +/* Field Value: MU03_SELECT__MU03_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC12 0xCU +/* Field Value: MU03_SELECT__MU03_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC13 0xDU +/* Field Value: MU03_SELECT__MU03_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC14 0xEU +/* Field Value: MU03_SELECT__MU03_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC15 0xFU +/* Field Value: MU03_SELECT__MU03_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC16 0x10U +/* Field Value: MU03_SELECT__MU03_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU03_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER ((uint32_t)(0xF064)) +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_MU03_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_MU03_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER ((uint32_t)(0xF068)) +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_MU03_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_MU03_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER ((uint32_t)(0xF06C)) +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_MU03_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_MU03_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER ((uint32_t)(0xF070)) +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER ((uint32_t)(0xF074)) +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_MU03_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_MU03_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Switch */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH ((uint32_t)(0xF078)) +#define IMXDPUV1_DPUXPC_MU04_SWITCH_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_DPUXPC_MU04_SWITCH_RESET_VALUE 0x4U +#define IMXDPUV1_DPUXPC_MU04_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT_SHIFT 0U +/* Field Value: MU04_SELECT__MU04_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC00 0U +/* Field Value: MU04_SELECT__MU04_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC01 0x1U +/* Field Value: MU04_SELECT__MU04_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC02 0x2U +/* Field Value: MU04_SELECT__MU04_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC03 0x3U +/* Field Value: MU04_SELECT__MU04_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC04 0x4U +/* Field Value: MU04_SELECT__MU04_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC05 0x5U +/* Field Value: MU04_SELECT__MU04_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC06 0x6U +/* Field Value: MU04_SELECT__MU04_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC07 0x7U +/* Field Value: MU04_SELECT__MU04_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC08 0x8U +/* Field Value: MU04_SELECT__MU04_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC09 0x9U +/* Field Value: MU04_SELECT__MU04_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC10 0xAU +/* Field Value: MU04_SELECT__MU04_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC11 0xBU +/* Field Value: MU04_SELECT__MU04_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC12 0xCU +/* Field Value: MU04_SELECT__MU04_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC13 0xDU +/* Field Value: MU04_SELECT__MU04_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC14 0xEU +/* Field Value: MU04_SELECT__MU04_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC15 0xFU +/* Field Value: MU04_SELECT__MU04_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC16 0x10U +/* Field Value: MU04_SELECT__MU04_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU04_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER ((uint32_t)(0xF07C)) +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_MU04_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_MU04_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER ((uint32_t)(0xF080)) +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_MU04_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_MU04_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER ((uint32_t)(0xF084)) +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_MU04_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_MU04_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER ((uint32_t)(0xF088)) +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER ((uint32_t)(0xF08C)) +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_MU04_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_MU04_LATENCY_SHIFT 0U + +#endif /* IMXDPUV1_REGISTERS_H */ diff --git a/include/interface/avb/avb.h b/include/interface/avb/avb.h new file mode 100644 index 00000000000..608f6afc400 --- /dev/null +++ b/include/interface/avb/avb.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_INTERFACE_AVB_H_ +#define TRUSTY_INTERFACE_AVB_H_ + +#include + +#define AVB_PORT "com.android.trusty.avb" +#define AVB_MAX_BUFFER_LENGTH 2048 + +enum avb_command { + AVB_REQ_SHIFT = 1, + AVB_RESP_BIT = 1, + + READ_ROLLBACK_INDEX = (0 << AVB_REQ_SHIFT), + WRITE_ROLLBACK_INDEX = (1 << AVB_REQ_SHIFT), + AVB_GET_VERSION = (2 << AVB_REQ_SHIFT), + READ_PERMANENT_ATTRIBUTES = (3 << AVB_REQ_SHIFT), + WRITE_PERMANENT_ATTRIBUTES = (4 << AVB_REQ_SHIFT), + READ_LOCK_STATE = (5 << AVB_REQ_SHIFT), + WRITE_LOCK_STATE = (6 << AVB_REQ_SHIFT), + LOCK_BOOT_STATE = (7 << AVB_REQ_SHIFT), + READ_VBMETA_PUBLIC_KEY = (8 << AVB_REQ_SHIFT), + WRITE_VBMETA_PUBLIC_KEY = (9 << AVB_REQ_SHIFT), +}; + +/** + * enum avb_error - error codes for AVB protocol + * @AVB_ERROR_NONE: All OK + * @AVB_ERROR_INVALID: Invalid input + * @AVB_ERROR_INTERNAL: Error occurred during an operation in Trusty + */ +enum avb_error { + AVB_ERROR_NONE = 0, + AVB_ERROR_INVALID = 1, + AVB_ERROR_INTERNAL = 2, +}; + +/** + * avb_message - Serial header for communicating with AVB server + * @cmd: the command. Payload must be a serialized buffer of the + * corresponding request object. + * @result: resulting error code for message, one of avb_error. + * @payload: start of the serialized command specific payload + */ +struct avb_message { + uint32_t cmd; + uint32_t result; + uint8_t payload[0]; +}; + +/** + * avb_rollback_req - request format for [READ|WRITE]_ROLLBACK_INDEX + * @value: value to write to rollback index. Ignored for read. + * @slot: slot number of rollback index to write + */ +struct avb_rollback_req { + uint64_t value; + uint32_t slot; +} TRUSTY_ATTR_PACKED; + +/** + * avb_rollback_resp - response format for [READ|WRITE]_ROLLBACK_INDEX. + * @value: value of the requested rollback index. + */ +struct avb_rollback_resp { + uint64_t value; +}; + +/** + * avb_get_version_resp - response format for AVB_GET_VERSION. + * @version: version of AVB message format + */ +struct avb_get_version_resp { + uint32_t version; +}; + +#endif /* TRUSTY_INTERFACE_AVB_H_ */ diff --git a/include/interface/hwcrypto/hwcrypto.h b/include/interface/hwcrypto/hwcrypto.h new file mode 100644 index 00000000000..270c57910a2 --- /dev/null +++ b/include/interface/hwcrypto/hwcrypto.h @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * Copyright NXP 2018 + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + */ + +#ifndef TRUSTY_INTERFACE_HWCRYPTO_H_ +#define TRUSTY_INTERFACE_HWCRYPTO_H_ + +#include + +#define HWCRYPTO_PORT "com.android.trusty.hwcrypto" +#define HWCRYPTO_MAX_BUFFER_LENGTH 2048 + +enum hwcrypto_command { + HWCRYPTO_REQ_SHIFT = 1, + HWCRYPTO_RESP_BIT = 1, + + HWCRYPTO_HASH = (1 << HWCRYPTO_REQ_SHIFT), + HWCRYPTO_ENCAP_BLOB = (2 << HWCRYPTO_REQ_SHIFT), + HWCRYPTO_GEN_RNG = (3 << HWCRYPTO_REQ_SHIFT), +}; + +/** + * enum hwcrypto_error - error codes for HWCRYPTO protocol + * @HWCRYPTO_ERROR_NONE: All OK + * @HWCRYPTO_ERROR_INVALID: Invalid input + * @HWCRYPTO_ERROR_INTERNAL: Error occurred during an operation in Trusty + */ +enum hwcrypto_error { + HWCRYPTO_ERROR_NONE = 0, + HWCRYPTO_ERROR_INVALID = 1, + HWCRYPTO_ERROR_INTERNAL = 2, +}; + +enum hwcrypto_hash_algo { + SHA1 = 0, + SHA256 +}; +/** + * hwcrypto_message - Serial header for communicating with hwcrypto server + * @cmd: the command. Payload must be a serialized buffer of the + * corresponding request object. + * @result: resulting error code for message, one of hwcrypto_error. + * @payload: start of the serialized command specific payload + */ +struct hwcrypto_message { + uint32_t cmd; + uint32_t result; + uint8_t payload[0]; +}; + +/** + * hwcrypto_hash_msg - Serial header for communicating with hwcrypto server + * @in_addr: start address of the input buf. + * @in_len: size of the input buf. + * @out_addr: start addrss of the output buf. + * @out_len: size of the output buf. + * @algo: hash algorithm expect to use. + */ +typedef struct hwcrypto_hash_msg { + uint32_t in_addr; + uint32_t in_len; + uint32_t out_addr; + uint32_t out_len; + enum hwcrypto_hash_algo algo; +} hwcrypto_hash_msg; + +/** + * @plain_pa: physical start address of the plain blob buf. + * @plain_size: size of the plain blob. + * @blob: physical start addrss of the output buf. + */ +typedef struct hwcrypto_blob_msg { + uint32_t plain_pa; + uint32_t plain_size; + uint32_t blob_pa; +}hwcrypto_blob_msg; + +/** + * @buf: physical start address of the output rng buf. + * @len: size of required rng. + */ +typedef struct hwcrypto_rng_msg { + uint32_t buf; + uint32_t len; +}hwcrypto_rng_msg; +#endif /* TRUSTY_INTERFACE_HWCRYPTO_H_ */ diff --git a/include/interface/keymaster/keymaster.h b/include/interface/keymaster/keymaster.h new file mode 100644 index 00000000000..a5e3e8b4c7b --- /dev/null +++ b/include/interface/keymaster/keymaster.h @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_INTERFACE_KEYMASTER_H_ +#define TRUSTY_INTERFACE_KEYMASTER_H_ + +#include + +#define KEYMASTER_PORT "com.android.trusty.keymaster" +#define KEYMASTER_MAX_BUFFER_LENGTH 4096 + +enum keymaster_command { + KEYMASTER_RESP_BIT = 1, + KEYMASTER_STOP_BIT = 2, + KEYMASTER_REQ_SHIFT = 2, + + KM_GENERATE_KEY = (0 << KEYMASTER_REQ_SHIFT), + KM_BEGIN_OPERATION = (1 << KEYMASTER_REQ_SHIFT), + KM_UPDATE_OPERATION = (2 << KEYMASTER_REQ_SHIFT), + KM_FINISH_OPERATION = (3 << KEYMASTER_REQ_SHIFT), + KM_ABORT_OPERATION = (4 << KEYMASTER_REQ_SHIFT), + KM_IMPORT_KEY = (5 << KEYMASTER_REQ_SHIFT), + + KM_EXPORT_KEY = (6 << KEYMASTER_REQ_SHIFT), + KM_GET_VERSION = (7 << KEYMASTER_REQ_SHIFT), + KM_ADD_RNG_ENTROPY = (8 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_ALGORITHMS = (9 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_BLOCK_MODES = (10 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_PADDING_MODES = (11 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_DIGESTS = (12 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_IMPORT_FORMATS = (13 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_EXPORT_FORMATS = (14 << KEYMASTER_REQ_SHIFT), + KM_GET_KEY_CHARACTERISTICS = (15 << KEYMASTER_REQ_SHIFT), + + // Bootloader calls. + KM_SET_BOOT_PARAMS = (0x1000 << KEYMASTER_REQ_SHIFT), + KM_SET_ATTESTATION_KEY = (0x2000 << KEYMASTER_REQ_SHIFT), + KM_APPEND_ATTESTATION_CERT_CHAIN = (0x3000 << KEYMASTER_REQ_SHIFT), + KM_ATAP_GET_CA_REQUEST = (0x4000 << KEYMASTER_REQ_SHIFT), + KM_ATAP_SET_CA_RESPONSE_BEGIN = (0x5000 << KEYMASTER_REQ_SHIFT), + KM_ATAP_SET_CA_RESPONSE_UPDATE = (0x6000 << KEYMASTER_REQ_SHIFT), + KM_ATAP_SET_CA_RESPONSE_FINISH = (0x7000 << KEYMASTER_REQ_SHIFT), + KM_ATAP_READ_UUID = (0x8000 << KEYMASTER_REQ_SHIFT), + KM_SET_PRODUCT_ID = (0x9000 << KEYMASTER_REQ_SHIFT) +}; + +typedef enum { + KM_VERIFIED_BOOT_VERIFIED = 0, /* Full chain of trust extending from the bootloader to + * verified partitions, including the bootloader, boot + * partition, and all verified partitions*/ + KM_VERIFIED_BOOT_SELF_SIGNED = 1, /* The boot partition has been verified using the embedded + * certificate, and the signature is valid. The bootloader + * displays a warning and the fingerprint of the public + * key before allowing the boot process to continue.*/ + KM_VERIFIED_BOOT_UNVERIFIED = 2, /* The device may be freely modified. Device integrity is left + * to the user to verify out-of-band. The bootloader + * displays a warning to the user before allowing the boot + * process to continue */ + KM_VERIFIED_BOOT_FAILED = 3, /* The device failed verification. The bootloader displays a + * warning and stops the boot process, so no keymaster + * implementation should ever actually return this value, + * since it should not run. Included here only for + * completeness. */ +} keymaster_verified_boot_t; + +/** + * Algorithms that may be provided by keymaster implementations. + */ +typedef enum { + /* Asymmetric algorithms. */ + KM_ALGORITHM_RSA = 1, + // KM_ALGORITHM_DSA = 2, -- Removed, do not re-use value 2. + KM_ALGORITHM_EC = 3, + + /* Block ciphers algorithms */ + KM_ALGORITHM_AES = 32, + + /* MAC algorithms */ + KM_ALGORITHM_HMAC = 128, +} keymaster_algorithm_t; + +typedef enum { + KM_ERROR_OK = 0, + KM_ERROR_ROOT_OF_TRUST_ALREADY_SET = -1, + KM_ERROR_UNSUPPORTED_PURPOSE = -2, + KM_ERROR_INCOMPATIBLE_PURPOSE = -3, + KM_ERROR_UNSUPPORTED_ALGORITHM = -4, + KM_ERROR_INCOMPATIBLE_ALGORITHM = -5, + KM_ERROR_UNSUPPORTED_KEY_SIZE = -6, + KM_ERROR_UNSUPPORTED_BLOCK_MODE = -7, + KM_ERROR_INCOMPATIBLE_BLOCK_MODE = -8, + KM_ERROR_UNSUPPORTED_MAC_LENGTH = -9, + KM_ERROR_UNSUPPORTED_PADDING_MODE = -10, + KM_ERROR_INCOMPATIBLE_PADDING_MODE = -11, + KM_ERROR_UNSUPPORTED_DIGEST = -12, + KM_ERROR_INCOMPATIBLE_DIGEST = -13, + KM_ERROR_INVALID_EXPIRATION_TIME = -14, + KM_ERROR_INVALID_USER_ID = -15, + KM_ERROR_INVALID_AUTHORIZATION_TIMEOUT = -16, + KM_ERROR_UNSUPPORTED_KEY_FORMAT = -17, + KM_ERROR_INCOMPATIBLE_KEY_FORMAT = -18, + KM_ERROR_UNSUPPORTED_KEY_ENCRYPTION_ALGORITHM = -19, /* For PKCS8 & PKCS12 */ + KM_ERROR_UNSUPPORTED_KEY_VERIFICATION_ALGORITHM = -20, /* For PKCS8 & PKCS12 */ + KM_ERROR_INVALID_INPUT_LENGTH = -21, + KM_ERROR_KEY_EXPORT_OPTIONS_INVALID = -22, + KM_ERROR_DELEGATION_NOT_ALLOWED = -23, + KM_ERROR_KEY_NOT_YET_VALID = -24, + KM_ERROR_KEY_EXPIRED = -25, + KM_ERROR_KEY_USER_NOT_AUTHENTICATED = -26, + KM_ERROR_OUTPUT_PARAMETER_NULL = -27, + KM_ERROR_INVALID_OPERATION_HANDLE = -28, + KM_ERROR_INSUFFICIENT_BUFFER_SPACE = -29, + KM_ERROR_VERIFICATION_FAILED = -30, + KM_ERROR_TOO_MANY_OPERATIONS = -31, + KM_ERROR_UNEXPECTED_NULL_POINTER = -32, + KM_ERROR_INVALID_KEY_BLOB = -33, + KM_ERROR_IMPORTED_KEY_NOT_ENCRYPTED = -34, + KM_ERROR_IMPORTED_KEY_DECRYPTION_FAILED = -35, + KM_ERROR_IMPORTED_KEY_NOT_SIGNED = -36, + KM_ERROR_IMPORTED_KEY_VERIFICATION_FAILED = -37, + KM_ERROR_INVALID_ARGUMENT = -38, + KM_ERROR_UNSUPPORTED_TAG = -39, + KM_ERROR_INVALID_TAG = -40, + KM_ERROR_MEMORY_ALLOCATION_FAILED = -41, + KM_ERROR_IMPORT_PARAMETER_MISMATCH = -44, + KM_ERROR_SECURE_HW_ACCESS_DENIED = -45, + KM_ERROR_OPERATION_CANCELLED = -46, + KM_ERROR_CONCURRENT_ACCESS_CONFLICT = -47, + KM_ERROR_SECURE_HW_BUSY = -48, + KM_ERROR_SECURE_HW_COMMUNICATION_FAILED = -49, + KM_ERROR_UNSUPPORTED_EC_FIELD = -50, + KM_ERROR_MISSING_NONCE = -51, + KM_ERROR_INVALID_NONCE = -52, + KM_ERROR_MISSING_MAC_LENGTH = -53, + KM_ERROR_KEY_RATE_LIMIT_EXCEEDED = -54, + KM_ERROR_CALLER_NONCE_PROHIBITED = -55, + KM_ERROR_KEY_MAX_OPS_EXCEEDED = -56, + KM_ERROR_INVALID_MAC_LENGTH = -57, + KM_ERROR_MISSING_MIN_MAC_LENGTH = -58, + KM_ERROR_UNSUPPORTED_MIN_MAC_LENGTH = -59, + KM_ERROR_UNSUPPORTED_KDF = -60, + KM_ERROR_UNSUPPORTED_EC_CURVE = -61, + KM_ERROR_KEY_REQUIRES_UPGRADE = -62, + KM_ERROR_ATTESTATION_CHALLENGE_MISSING = -63, + KM_ERROR_KEYMASTER_NOT_CONFIGURED = -64, + + KM_ERROR_UNIMPLEMENTED = -100, + KM_ERROR_VERSION_MISMATCH = -101, + + KM_ERROR_UNKNOWN_ERROR = -1000, +} keymaster_error_t; + +/** + * keymaster_message - Serial header for communicating with KM server + * + * @cmd: the command, one of keymaster_command. + * @payload: start of the serialized command specific payload + */ +struct keymaster_message { + uint32_t cmd; + uint8_t payload[0]; +}; + +/** + * km_no_response - Generic keymaster response for commands with no special + * response data + * + * @error: error code from command + */ +struct km_no_response { + int32_t error; +}; + +/** + * km_get_version_resp - response format for KM_GET_VERSION. + */ +struct km_get_version_resp { + int32_t error; + uint8_t major_ver; + uint8_t minor_ver; + uint8_t subminor_ver; +} TRUSTY_ATTR_PACKED; + +/** + * km_raw_buffer_resp - response format for a raw buffer + */ +struct km_raw_buffer_resp { + int32_t error; + uint32_t data_size; + int8_t data[0]; +} TRUSTY_ATTR_PACKED; + +/** + * km_set_ca_response_begin_req - starts the process to set the ATAP CA Response + * + * @ca_response_size: total size of the CA Response message + */ +struct km_set_ca_response_begin_req { + uint32_t ca_response_size; +} TRUSTY_ATTR_PACKED; + +/** + * km_boot_params - Parameters sent from the bootloader to the Keymaster TA + * + * Since verified_boot_key_hash and verified_boot_hash have variable sizes, this + * structure must be serialized before sending to the secure side + * using km_boot_params_serialize(). + * + * @os_version: OS version from Android image header + * @os_patchlevel: OS patch level from Android image header + * @device_locked: nonzero if device is locked + * @verified_boot_state: one of keymaster_verified_boot_t + * @verified_boot_key_hash_size: size of verified_boot_key_hash + * @verified_boot_key_hash: hash of key used to verify Android image + * @verified_boot_hash_size: size of verified_boot_hash + * @verified_boot_hash: cumulative hash of all images verified thus far + */ +struct km_boot_params { + uint32_t os_version; + uint32_t os_patchlevel; + uint32_t device_locked; + uint32_t verified_boot_state; + uint32_t verified_boot_key_hash_size; + const uint8_t *verified_boot_key_hash; + uint32_t verified_boot_hash_size; + const uint8_t *verified_boot_hash; +} TRUSTY_ATTR_PACKED; + +/** + * km_attestation_data - represents a DER encoded key or certificate + * + * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC + * @data_size: size of |data| + * @data: DER encoded key or certificate (depending on operation) + */ +struct km_attestation_data { + uint32_t algorithm; + uint32_t data_size; + const uint8_t *data; +} TRUSTY_ATTR_PACKED; + +/** + * km_raw_buffer - represents a single raw buffer + * + * @data_size: size of |data| + * @data: pointer to the buffer + */ +struct km_raw_buffer { + uint32_t data_size; + const uint8_t *data; +} TRUSTY_ATTR_PACKED; + +#endif /* TRUSTY_INTERFACE_KEYMASTER_H_ */ diff --git a/include/interface/storage/storage.h b/include/interface/storage/storage.h new file mode 100644 index 00000000000..e4f7f836567 --- /dev/null +++ b/include/interface/storage/storage.h @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_INTERFACE_STORAGE_H_ +#define TRUSTY_INTERFACE_STORAGE_H_ + +/* + * The contents of this file are copied from + * trusty/lib/interface/storage/include/interface/storage/storage.h. + * It is required to stay in sync for struct formats and enum values. + */ + +#include + +/* + * @STORAGE_DISK_PROXY_PORT: Port used by non-secure proxy server + */ +#define STORAGE_DISK_PROXY_PORT "com.android.trusty.storage.proxy" + +enum storage_cmd { + STORAGE_REQ_SHIFT = 1, + STORAGE_RESP_BIT = 1, + + STORAGE_RESP_MSG_ERR = STORAGE_RESP_BIT, + + STORAGE_FILE_DELETE = 1 << STORAGE_REQ_SHIFT, + STORAGE_FILE_OPEN = 2 << STORAGE_REQ_SHIFT, + STORAGE_FILE_CLOSE = 3 << STORAGE_REQ_SHIFT, + STORAGE_FILE_READ = 4 << STORAGE_REQ_SHIFT, + STORAGE_FILE_WRITE = 5 << STORAGE_REQ_SHIFT, + STORAGE_FILE_GET_SIZE = 6 << STORAGE_REQ_SHIFT, + STORAGE_FILE_SET_SIZE = 7 << STORAGE_REQ_SHIFT, + + STORAGE_RPMB_SEND = 8 << STORAGE_REQ_SHIFT, + + /* transaction support */ + STORAGE_END_TRANSACTION = 9 << STORAGE_REQ_SHIFT, +}; + +/** + * enum storage_err - error codes for storage protocol + * @STORAGE_NO_ERROR: all OK + * @STORAGE_ERR_GENERIC: unknown error. Can occur when there's an internal server + * error, e.g. the server runs out of memory or is in a bad state. + * @STORAGE_ERR_NOT_VALID: input not valid. May occur if the arguments passed + * into the command are not valid, for example if the file handle + * passed in is not a valid one. + * @STORAGE_ERR_UNIMPLEMENTED: the command passed in is not recognized + * @STORAGE_ERR_ACCESS: the file is not accessible in the requested mode + * @STORAGE_ERR_NOT_FOUND: the file was not found + * @STORAGE_ERR_EXIST the file exists when it shouldn't as in with OPEN_CREATE | OPEN_EXCLUSIVE. + * @STORAGE_ERR_TRANSACT returned by various operations to indicate that current transaction + * is in error state. Such state could be only cleared by sending + * STORAGE_END_TRANSACTION message. + */ +enum storage_err { + STORAGE_NO_ERROR = 0, + STORAGE_ERR_GENERIC = 1, + STORAGE_ERR_NOT_VALID = 2, + STORAGE_ERR_UNIMPLEMENTED = 3, + STORAGE_ERR_ACCESS = 4, + STORAGE_ERR_NOT_FOUND = 5, + STORAGE_ERR_EXIST = 6, + STORAGE_ERR_TRANSACT = 7, +}; + +/** + * enum storage_msg_flag - protocol-level flags in struct storage_msg + * @STORAGE_MSG_FLAG_BATCH: if set, command belongs to a batch transaction. + * No response will be sent by the server until + * it receives a command with this flag unset, at + * which point a cummulative result for all messages + * sent with STORAGE_MSG_FLAG_BATCH will be sent. + * This is only supported by the non-secure disk proxy + * server. + * @STORAGE_MSG_FLAG_PRE_COMMIT: if set, indicates that server need to commit + * pending changes before processing this message. + * @STORAGE_MSG_FLAG_POST_COMMIT: if set, indicates that server need to commit + * pending changes after processing this message. + * @STORAGE_MSG_FLAG_TRANSACT_COMPLETE: if set, indicates that server need to commit + * current transaction after processing this message. + * It is an alias for STORAGE_MSG_FLAG_POST_COMMIT. + */ +enum storage_msg_flag { + STORAGE_MSG_FLAG_BATCH = 0x1, + STORAGE_MSG_FLAG_PRE_COMMIT = 0x2, + STORAGE_MSG_FLAG_POST_COMMIT = 0x4, + STORAGE_MSG_FLAG_TRANSACT_COMPLETE = STORAGE_MSG_FLAG_POST_COMMIT, +}; + +/* + * The following declarations are the message-specific contents of + * the 'payload' element inside struct storage_msg. + */ + +/** + * struct storage_rpmb_send_req - request format for STORAGE_RPMB_SEND + * @reliable_write_size: size in bytes of reliable write region + * @write_size: size in bytes of write region + * @read_size: number of bytes to read for a read request + * @__reserved: unused, must be set to 0 + * @payload: start of reliable write region, followed by + * write region. + * + * Only used in proxy<->server interface. + */ +struct storage_rpmb_send_req { + uint32_t reliable_write_size; + uint32_t write_size; + uint32_t read_size; + uint32_t __reserved; + uint8_t payload[0]; +}; + +/** + * struct storage_rpmb_send_resp: response type for STORAGE_RPMB_SEND + * @data: the data frames frames retrieved from the MMC. + */ +struct storage_rpmb_send_resp { + uint8_t data[0]; +}; + +/** + * struct storage_msg - generic req/resp format for all storage commands + * @cmd: one of enum storage_cmd + * @op_id: client chosen operation identifier for an instance + * of a command or atomic grouping of commands (transaction). + * @flags: one or many of enum storage_msg_flag or'ed together. + * @size: total size of the message including this header + * @result: one of enum storage_err + * @__reserved: unused, must be set to 0. + * @payload: beginning of command specific message format + */ +struct storage_msg { + uint32_t cmd; + uint32_t op_id; + uint32_t flags; + uint32_t size; + int32_t result; + uint32_t __reserved; + uint8_t payload[0]; +}; + +#endif /* TRUSTY_INTERFACE_STORAGE_H_ */ diff --git a/include/lcd.h b/include/lcd.h index 797d0b0de12..dd04b87a150 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -31,6 +31,7 @@ extern struct vidinfo panel_info; void lcd_ctrl_init(void *lcdbase); void lcd_enable(void); void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); +void lcd_initcolregs (void); /** * Set whether we need to flush the dcache when changing the LCD image. This @@ -47,6 +48,64 @@ void lcd_set_flush_dcache(int flush); #include #elif defined(CONFIG_EXYNOS_FB) #include +#elif defined(CONFIG_MXC_EPDC) + +struct waveform_modes { + int mode_init; + int mode_du; + int mode_gc4; + int mode_gc8; + int mode_gc16; + int mode_gc32; +}; + +struct epdc_timing_params { + int vscan_holdoff; + int sdoed_width; + int sdoed_delay; + int sdoez_width; + int sdoez_delay; + int gdclk_hp_offs; + int gdsp_offs; + int gdoe_offs; + int gdclk_offs; + int num_ce; +}; + +struct epdc_data_struct { + /* EPDC buffer pointers */ + u_long working_buf_addr; + u_long waveform_buf_addr; + + /* Waveform mode definitions */ + struct waveform_modes wv_modes; + struct epdc_timing_params epdc_timings; +}; + +typedef struct vidinfo { + u_long vl_refresh; /* Refresh Rate Hz */ + u_long vl_row; /* resolution in x */ + u_long vl_col; /* resolution in y */ + u_long vl_rot; + u_long vl_pixclock; /* pixel clock in picoseconds */ + u_long vl_left_margin; /* Horizontal back porch */ + u_long vl_right_margin; /* Horizontal front porch */ + u_long vl_upper_margin; /* Vertical back porch */ + u_long vl_lower_margin; /* Vertical front porch */ + u_long vl_hsync; /* Horizontal sync pulse length */ + u_long vl_vsync; /* Vertical sync pulse length */ + u_long vl_sync; /* Polarity on data enable */ + u_long vl_mode; /* Video Mode */ + u_long vl_flag; + u_char vl_bpix; + ushort *cmap; + struct epdc_data_struct epdc_data; +} vidinfo_t; + +static __maybe_unused ushort *configuration_get_cmap(void) +{ + return panel_info.cmap; +} #else typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 160) */ @@ -163,6 +222,16 @@ void lcd_sync(void); #define LCD_BPP LCD_COLOR8 #endif +#if LCD_BPP == LCD_MONOCHROME +# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ + (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) +#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || \ + (LCD_BPP == LCD_COLOR32) +# define COLOR_MASK(c) (c) +#else +#error Unsupported LCD BPP. +#endif + #ifndef LCD_DF #define LCD_DF 1 #endif @@ -171,7 +240,14 @@ void lcd_sync(void); #define NBITS(bit_code) (1 << (bit_code)) #define NCOLORS(bit_code) (1 << NBITS(bit_code)) -#if LCD_BPP == LCD_COLOR8 +#if LCD_BPP == LCD_MONOCHROME +/* + * Simple black/white definitions + */ +# define CONSOLE_COLOR_BLACK 0 +# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */ + +#elif LCD_BPP == LCD_COLOR8 # define CONSOLE_COLOR_BLACK 0 # define CONSOLE_COLOR_RED 1 # define CONSOLE_COLOR_GREEN 2 diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 6c3e838d809..ad67e03b598 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -47,7 +47,7 @@ void nand_wait_ready(struct mtd_info *mtd); * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. */ -#define NAND_MAX_OOBSIZE 1664 +#define NAND_MAX_OOBSIZE 1872 #define NAND_MAX_PAGESIZE 16384 /* diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h index 86e1ceac3cb..4f1ee707f7e 100644 --- a/include/linux/usb/composite.h +++ b/include/linux/usb/composite.h @@ -38,6 +38,53 @@ struct usb_configuration; +/** + * struct usb_os_desc_ext_prop - describes one "Extended Property" + * @entry: used to keep a list of extended properties + * @type: Extended Property type + * @name_len: Extended Property unicode name length, including terminating '\0' + * @name: Extended Property name + * @data_len: Length of Extended Property blob (for unicode store double len) + * @data: Extended Property blob + */ +struct usb_os_desc_ext_prop { + struct list_head entry; + u8 type; + int name_len; + char *name; + int data_len; + char *data; +}; + +/** + * struct usb_os_desc - describes OS descriptors associated with one interface + * @ext_compat_id: 16 bytes of "Compatible ID" and "Subcompatible ID" + * @ext_prop: Extended Properties list + * @ext_prop_len: Total length of Extended Properties blobs + * @ext_prop_count: Number of Extended Properties + */ +struct usb_os_desc { + char *ext_compat_id; + struct list_head ext_prop; + int ext_prop_len; + int ext_prop_count; +}; + +/** + * struct usb_os_desc_table - describes OS descriptors associated with one + * interface of a usb_function + * @if_id: Interface id + * @os_desc: "Extended Compatibility ID" and "Extended Properties" of the + * interface + * + * Each interface can have at most one "Extended Compatibility ID" and a + * number of "Extended Properties". + */ +struct usb_os_desc_table { + int if_id; + struct usb_os_desc *os_desc; +}; + /** * struct usb_function - describes one function of a configuration * @name: For diagnostics, identifies the function. @@ -51,6 +98,10 @@ struct usb_configuration; * the function will not be available at high speed. * @config: assigned when @usb_add_function() is called; this is the * configuration with which this function is associated. + * @os_desc_table: Table of (interface id, os descriptors) pairs. The function + * can expose more than one interface. If an interface is a member of + * an IAD, only the first interface of IAD has its entry in the table. + * @os_desc_n: Number of entries in os_desc_table * @bind: Before the gadget can register, all of its functions bind() to the * available resources including string and interface identifiers used * in interface or class descriptors; endpoints; I/O buffers; and so on. @@ -96,9 +147,13 @@ struct usb_function { struct usb_gadget_strings **strings; struct usb_descriptor_header **descriptors; struct usb_descriptor_header **hs_descriptors; + struct usb_descriptor_header **ss_descriptors; struct usb_configuration *config; + struct usb_os_desc_table *os_desc_table; + unsigned os_desc_n; + /* REVISIT: bind() functions can be marked __init, which * makes trouble for section mismatch analysis. See if * we can't restructure things to avoid mismatching. @@ -226,6 +281,7 @@ struct usb_configuration { u8 next_interface_id; unsigned highspeed:1; unsigned fullspeed:1; + unsigned superspeed:1; struct usb_function *interface[MAX_CONFIG_INTERFACES]; }; @@ -239,6 +295,7 @@ int usb_add_config(struct usb_composite_dev *, * identifiers. * @strings: tables of strings, keyed by identifiers assigned during bind() * and language IDs provided in control requests + * @max_speed: Highest speed the driver supports. * @bind: (REQUIRED) Used to allocate resources that are shared across the * whole device, such as string IDs, and add its configurations using * @usb_add_config(). This may fail by returning a negative errno @@ -266,6 +323,7 @@ struct usb_composite_driver { const char *name; const struct usb_device_descriptor *dev; struct usb_gadget_strings **strings; + enum usb_device_speed max_speed; /* REVISIT: bind() functions can be marked __init, which * makes trouble for section mismatch analysis. See if @@ -285,13 +343,20 @@ struct usb_composite_driver { extern int usb_composite_register(struct usb_composite_driver *); extern void usb_composite_unregister(struct usb_composite_driver *); +#define OS_STRING_QW_SIGN_LEN 14 +#define OS_STRING_IDX 0xEE /** * struct usb_composite_device - represents one composite usb gadget * @gadget: read-only, abstracts the gadget's usb peripheral controller * @req: used for control responses; buffer is pre-allocated * @bufsiz: size of buffer pre-allocated in @req + * @os_desc_req: used for OS descriptors responses; buffer is pre-allocated * @config: the currently active configuration + * @qw_sign: qwSignature part of the OS string + * @b_vendor_code: bMS_VendorCode part of the OS string + * @use_os_string: false by default, interested gadgets set it + * @os_desc_config: the configuration to be used with OS descriptors * * One of these devices is allocated and initialized before the * associated device driver's bind() is called. @@ -325,6 +390,12 @@ struct usb_composite_dev { struct usb_configuration *config; + /* OS String is a custom (yet popular) extension to the USB standard. */ + u8 qw_sign[OS_STRING_QW_SIGN_LEN]; + u8 b_vendor_code; + struct usb_configuration *os_desc_config; + unsigned int use_os_string:1; + /* private: */ /* internals */ unsigned int suspended:1; diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h index c1b23b2f1bd..14ff81c4503 100644 --- a/include/linux/usb/dwc3.h +++ b/include/linux/usb/dwc3.h @@ -155,6 +155,7 @@ struct dwc3 { /* offset: 0xC100 */ /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) +#define DWC3_GCTL_PWRDNSCALE_MASK DWC3_GCTL_PWRDNSCALE(0x1fff) #define DWC3_GCTL_U2RSTECN (1 << 16) #define DWC3_GCTL_RAMCLKSEL(x) \ (((x) & DWC3_GCTL_CLK_MASK) << 6) diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index b824f13477b..51baff42811 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -428,6 +428,13 @@ static inline void usb_ep_fifo_flush(struct usb_ep *ep) /*-------------------------------------------------------------------------*/ +struct usb_dcd_config_params { + __u8 bU1devExitLat; /* U1 Device exit Latency */ +#define USB_DEFAULT_U1_DEV_EXIT_LAT 0x01 /* Less then 1 microsec */ + __le16 bU2DevExitLat; /* U2 Device exit Latency */ +#define USB_DEFAULT_U2_DEV_EXIT_LAT 0x1F4 /* Less then 500 microsec */ +}; + struct usb_gadget; struct usb_gadget_driver; @@ -443,9 +450,13 @@ struct usb_gadget_ops { int (*pullup) (struct usb_gadget *, int is_on); int (*ioctl)(struct usb_gadget *, unsigned code, unsigned long param); + void (*get_config_params)(struct usb_dcd_config_params *); int (*udc_start)(struct usb_gadget *, struct usb_gadget_driver *); int (*udc_stop)(struct usb_gadget *); + int (*match_ep)(struct usb_gadget *, + struct usb_ep *, + struct usb_endpoint_descriptor *); }; /** @@ -549,6 +560,15 @@ static inline int gadget_is_dualspeed(struct usb_gadget *g) #endif } +/** + * gadget_is_superspeed() - return true if the hardware handles superspeed + * @g: controller that might support superspeed + */ +static inline int gadget_is_superspeed(struct usb_gadget *g) +{ + return g->max_speed >= USB_SPEED_SUPER; +} + /** * gadget_is_otg - return true iff the hardware is OTG-ready * @g: controller that might have a Mini-AB connector diff --git a/include/linux/utf.h b/include/linux/utf.h new file mode 100644 index 00000000000..e1f7d3bd1d6 --- /dev/null +++ b/include/linux/utf.h @@ -0,0 +1,75 @@ +#ifndef _LINUX_UTF_H +#define _LINUX_UTF_H + +#include + +static inline int utf8_to_utf16le(const char *s, __le16 *cp, unsigned len) +{ + int count = 0; + u8 c; + u16 uchar; + + /* + * this insists on correct encodings, though not minimal ones. + * BUT it currently rejects legit 4-byte UTF-8 code points, + * which need surrogate pairs. (Unicode 3.1 can use them.) + */ + while (len != 0 && (c = (u8) *s++) != 0) { + if ((c & 0x80)) { + /* + * 2-byte sequence: + * 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx + */ + if ((c & 0xe0) == 0xc0) { + uchar = (c & 0x1f) << 6; + + c = (u8) *s++; + if ((c & 0xc0) != 0x80) + goto fail; + c &= 0x3f; + uchar |= c; + + /* + * 3-byte sequence (most CJKV characters): + * zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx + */ + } else if ((c & 0xf0) == 0xe0) { + uchar = (c & 0x0f) << 12; + + c = (u8) *s++; + if ((c & 0xc0) != 0x80) + goto fail; + c &= 0x3f; + uchar |= c << 6; + + c = (u8) *s++; + if ((c & 0xc0) != 0x80) + goto fail; + c &= 0x3f; + uchar |= c; + + /* no bogus surrogates */ + if (0xd800 <= uchar && uchar <= 0xdfff) + goto fail; + + /* + * 4-byte sequence (surrogate pairs, currently rare): + * 11101110wwwwzzzzyy + 110111yyyyxxxxxx + * = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx + * (uuuuu = wwww + 1) + * FIXME accept the surrogate code points (only) + */ + } else + goto fail; + } else + uchar = c; + put_unaligned_le16(uchar, cp++); + count++; + len--; + } + return count; +fail: + return -1; +} + +#endif /* _LINUX_UTF_H */ diff --git a/include/mailbox.h b/include/mailbox.h index a92a1a590df..8d89f3f99ee 100644 --- a/include/mailbox.h +++ b/include/mailbox.h @@ -124,7 +124,7 @@ int mbox_free(struct mbox_chan *chan); * will ignore this parameter. * @return 0 if OK, or a negative error code. */ -int mbox_send(struct mbox_chan *chan, const void *data); +int mbox_send(struct mbox_chan *chan, const void *data, ulong timeout_us); /** * mbox_recv - Receive any available message from a mailbox channel diff --git a/include/mipi_display.h b/include/mipi_display.h index ddcc8ca7316..1554ef70c71 100644 --- a/include/mipi_display.h +++ b/include/mipi_display.h @@ -115,6 +115,7 @@ enum { MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, MIPI_DCS_SET_TEAR_SCANLINE = 0x44, MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */ MIPI_DCS_READ_DDB_START = 0xA1, MIPI_DCS_READ_DDB_CONTINUE = 0xA8, }; diff --git a/include/mipi_dsi_northwest.h b/include/mipi_dsi_northwest.h new file mode 100644 index 00000000000..9be24984c74 --- /dev/null +++ b/include/mipi_dsi_northwest.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __MIPI_DSI_NORTHWEST_H +#define __MIPI_DSI_NORTHWEST_H + +#include + +/* Setup mipi dsi host driver instance, with base address and SIM address provided */ +int mipi_dsi_northwest_setup(u32 base_addr, u32 sim_addr); + +#endif diff --git a/include/mipi_dsi_panel.h b/include/mipi_dsi_panel.h new file mode 100644 index 00000000000..dc28e7721f9 --- /dev/null +++ b/include/mipi_dsi_panel.h @@ -0,0 +1,15 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __MIPI_DSI_PANEL_H +#define __MIPI_DSI_PANEL_H + +void hx8363_init(void); +void rm67191_init(void); +void rm68200_init(void); + +#endif diff --git a/include/mmc.h b/include/mmc.h index 86f885b504e..40ed3bc01ae 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -65,6 +65,8 @@ #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52) #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52) #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200) +#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400) +#define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES) #define MMC_MODE_8BIT BIT(30) #define MMC_MODE_4BIT BIT(29) @@ -215,10 +217,12 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define EXT_CSD_WR_REL_PARAM 166 /* R */ #define EXT_CSD_WR_REL_SET 167 /* R/W */ #define EXT_CSD_RPMB_MULT 168 /* RO */ +#define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */ #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ #define EXT_CSD_BOOT_BUS_WIDTH 177 #define EXT_CSD_PART_CONF 179 /* R/W */ #define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_STROBE_SUPPORT 184 /* R/W */ #define EXT_CSD_HS_TIMING 185 /* R/W */ #define EXT_CSD_REV 192 /* RO */ #define EXT_CSD_CARD_TYPE 196 /* RO */ @@ -250,16 +254,24 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ EXT_CSD_CARD_TYPE_HS200_1_2V) +#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6) +#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7) +#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ + EXT_CSD_CARD_TYPE_HS400_1_2V) + #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */ +#define EXT_CSD_BUS_WIDTH_STROBE (1 << 7) /* Enhanced strobe mode */ #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */ #define EXT_CSD_TIMING_HS 1 /* HS */ #define EXT_CSD_TIMING_HS200 2 /* HS200 */ +#define EXT_CSD_TIMING_HS400 3 /* HS400 */ +#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */ #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) @@ -317,6 +329,8 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define MMC_QUIRK_RETRY_SEND_CID BIT(0) #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1) +#define BOOT1_PWR_WP (0x83) + enum mmc_voltage { MMC_SIGNAL_VOLTAGE_000 = 0, MMC_SIGNAL_VOLTAGE_120 = 1, @@ -328,6 +342,7 @@ enum mmc_voltage { MMC_SIGNAL_VOLTAGE_180 |\ MMC_SIGNAL_VOLTAGE_330) + /* Maximum block size for MMC */ #define MMC_MAX_BLOCK_LEN 512 @@ -456,6 +471,11 @@ struct dm_mmc_ops { */ int (*wait_dat0)(struct udevice *dev, int state, int timeout); #endif + +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) + /* set_enhanced_strobe() - set HS400 enhanced strobe */ + void (*set_enhanced_strobe)(struct udevice *dev); +#endif }; #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops) @@ -476,6 +496,7 @@ int mmc_getcd(struct mmc *mmc); int mmc_getwp(struct mmc *mmc); int mmc_execute_tuning(struct mmc *mmc, uint opcode); int mmc_wait_dat0(struct mmc *mmc, int state, int timeout); +void mmc_set_enhanced_strobe(struct mmc *mmc); #else struct mmc_ops { @@ -520,6 +541,8 @@ enum bus_mode { UHS_DDR50, UHS_SDR104, MMC_HS_200, + MMC_HS_400, + MMC_HS_400_ES, MMC_MODES_END }; @@ -533,6 +556,14 @@ static inline bool mmc_is_mode_ddr(enum bus_mode mode) #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) else if (mode == UHS_DDR50) return true; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + else if (mode == MMC_HS_400) + return true; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) + else if (mode == MMC_HS_400_ES) + return true; #endif else return false; @@ -740,12 +771,34 @@ int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); /* Functions to read / write the RPMB partition */ +/* Sizes of RPMB data frame */ +#define RPMB_SZ_STUFF 196 +#define RPMB_SZ_MAC 32 +#define RPMB_SZ_DATA 256 +#define RPMB_SZ_NONCE 16 + +/* Structure of RPMB data frame. */ +struct s_rpmb { + unsigned char stuff[RPMB_SZ_STUFF]; + unsigned char mac[RPMB_SZ_MAC]; + unsigned char data[RPMB_SZ_DATA]; + unsigned char nonce[RPMB_SZ_NONCE]; + unsigned int write_counter; + unsigned short address; + unsigned short block_count; + unsigned short result; + unsigned short request; +}; int mmc_rpmb_set_key(struct mmc *mmc, void *key); int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, unsigned short cnt, unsigned char *key); int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, unsigned short cnt, unsigned char *key); +int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, + unsigned int count, bool is_rel_write); +int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, + unsigned int count, unsigned short expected); #ifdef CONFIG_CMD_BKOPS_ENABLE int mmc_set_bkops_enable(struct mmc *mmc); #endif @@ -787,6 +840,7 @@ int board_mmc_init(bd_t *bis); int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); int mmc_get_env_dev(void); +int mmc_map_to_kernel_blk(int dev_no); /* Set block count limit because of 16 bit register limit on some hardware*/ #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT diff --git a/include/mxc_epdc_fb.h b/include/mxc_epdc_fb.h new file mode 100644 index 00000000000..a32ebac0dbf --- /dev/null +++ b/include/mxc_epdc_fb.h @@ -0,0 +1,565 @@ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __EPDC_REGS_INCLUDED__ +#define __EPDC_REGS_INCLUDED__ + +#include +#include +#include + +/************************************* + * Register addresses + *************************************/ +#define EPDC_BASE (EPDC_BASE_ADDR) + +#define EPDC_CTRL 0x000 +#define EPDC_CTRL_SET 0x004 +#define EPDC_CTRL_CLR 0x008 +#define EPDC_CTRL_TOG 0x00C +#define EPDC_WVADDR 0x020 +#define EPDC_WB_ADDR 0x030 +#define EPDC_RES 0x040 +#define EPDC_FORMAT 0x050 +#define EPDC_FORMAT_SET 0x054 +#define EPDC_FORMAT_CLR 0x058 +#define EPDC_FORMAT_TOG 0x05C +#define EPDC_WB_FIELD0 0x060 +#define EPDC_WB_FIELD0_SET 0x064 +#define EPDC_WB_FIELD0_CLR 0x068 +#define EPDC_WB_FIELD0_TOG 0x06C +#define EPDC_WB_FIELD1 0x070 +#define EPDC_WB_FIELD1_SET 0x074 +#define EPDC_WB_FIELD1_CLR 0x078 +#define EPDC_WB_FIELD1_TOG 0x07C +#define EPDC_WB_FIELD2 0x080 +#define EPDC_WB_FIELD2_SET 0x084 +#define EPDC_WB_FIELD2_CLR 0x088 +#define EPDC_WB_FIELD2_TOG 0x08C +#define EPDC_WB_FIELD3 0x090 +#define EPDC_WB_FIELD3_SET 0x094 +#define EPDC_WB_FIELD3_CLR 0x098 +#define EPDC_WB_FIELD3_TOG 0x09C +#define EPDC_FIFOCTRL 0x0A0 +#define EPDC_FIFOCTRL_SET 0x0A4 +#define EPDC_FIFOCTRL_CLR 0x0A8 +#define EPDC_FIFOCTRL_TOG 0x0AC +#define EPDC_UPD_ADDR 0x100 +#define EPDC_UPD_STRIDE 0x110 +#define EPDC_UPD_CORD 0x120 +#define EPDC_UPD_SIZE 0x140 +#define EPDC_UPD_CTRL 0x160 +#define EPDC_UPD_FIXED 0x180 +#define EPDC_TEMP 0x1A0 +#define EPDC_AUTOWV_LUT 0x1C0 +#define EPDC_LUT_STANDBY1 0x1E0 +#define EPDC_LUT_STANDBY1_SET 0x1E4 +#define EPDC_LUT_STANDBY1_CLR 0x1E8 +#define EPDC_LUT_STANDBY1_TOG 0x1EC +#define EPDC_LUT_STANDBY2 0x1F0 +#define EPDC_LUT_STANDBY2_SET 0x1F4 +#define EPDC_LUT_STANDBY2_CLR 0x1F8 +#define EPDC_LUT_STANDBY2_TOG 0x1FC +#define EPDC_TCE_CTRL 0x200 +#define EPDC_TCE_SDCFG 0x220 +#define EPDC_TCE_GDCFG 0x240 +#define EPDC_TCE_HSCAN1 0x260 +#define EPDC_TCE_HSCAN2 0x280 +#define EPDC_TCE_VSCAN 0x2A0 +#define EPDC_TCE_OE 0x2C0 +#define EPDC_TCE_POLARITY 0x2E0 +#define EPDC_TCE_TIMING1 0x300 +#define EPDC_TCE_TIMING2 0x310 +#define EPDC_TCE_TIMING3 0x320 +#define EPDC_PIGEON_CTRL0 0x380 +#define EPDC_PIGEON_CTRL1 0x390 +#define EPDC_IRQ_MASK1 0x3C0 +#define EPDC_IRQ_MASK1_SET 0x3C4 +#define EPDC_IRQ_MASK1_CLR 0x3C8 +#define EPDC_IRQ_MASK1_TOG 0x3CC +#define EPDC_IRQ_MASK2 0x3D0 +#define EPDC_IRQ_MASK2_SET 0x3D4 +#define EPDC_IRQ_MASK2_CLR 0x3D8 +#define EPDC_IRQ_MASK2_TOG 0x3DC +#define EPDC_IRQ1 0x3E0 +#define EPDC_IRQ1_SET 0x3E4 +#define EPDC_IRQ1_CLR 0x3E8 +#define EPDC_IRQ1_TOG 0x3EC +#define EPDC_IRQ2 0x3F0 +#define EPDC_IRQ2_SET 0x3F4 +#define EPDC_IRQ2_CLR 0x3F8 +#define EPDC_IRQ2_TOG 0x3FC +#define EPDC_IRQ_MASK 0x400 +#define EPDC_IRQ_MASK_SET 0x404 +#define EPDC_IRQ_MASK_CLR 0x408 +#define EPDC_IRQ_MASK_TOG 0x40C +#define EPDC_IRQ 0x420 +#define EPDC_IRQ_SET 0x424 +#define EPDC_IRQ_CLR 0x428 +#define EPDC_IRQ_TOG 0x42C +#define EPDC_STATUS_LUTS 0x440 +#define EPDC_STATUS_LUTS_SET 0x444 +#define EPDC_STATUS_LUTS_CLR 0x448 +#define EPDC_STATUS_LUTS_TOG 0x44C +#define EPDC_STATUS_LUTS2 0x450 +#define EPDC_STATUS_LUTS2_SET 0x454 +#define EPDC_STATUS_LUTS2_CLR 0x458 +#define EPDC_STATUS_LUTS2_TOG 0x45C +#define EPDC_STATUS_NEXTLUT 0x460 +#define EPDC_STATUS_COL 0x480 +#define EPDC_STATUS_COL2 0x490 +#define EPDC_STATUS 0x4A0 +#define EPDC_STATUS_SET 0x4A4 +#define EPDC_STATUS_CLR 0x4A8 +#define EPDC_STATUS_TOG 0x4AC +#define EPDC_UPD_COL_CORD 0x4C0 +#define EPDC_UPD_COL_SIZE 0x4E0 +#define EPDC_DEBUG 0x500 +#define EPDC_DEBUG_LUT 0x530 +#define EPDC_HIST1_PARAM 0x600 +#define EPDC_HIST2_PARAM 0x610 +#define EPDC_HIST4_PARAM 0x620 +#define EPDC_HIST8_PARAM0 0x630 +#define EPDC_HIST8_PARAM1 0x640 +#define EPDC_HIST16_PARAM0 0x650 +#define EPDC_HIST16_PARAM1 0x660 +#define EPDC_HIST16_PARAM2 0x670 +#define EPDC_HIST16_PARAM3 0x680 +#define EPDC_GPIO 0x700 +#define EPDC_VERSION 0x7F0 +#define EPDC_PIGEON_0_0 0x800 +#define EPDC_PIGEON_0_1 0x810 +#define EPDC_PIGEON_0_2 0x820 +#define EPDC_PIGEON_1_0 0x840 +#define EPDC_PIGEON_1_1 0x850 +#define EPDC_PIGEON_1_2 0x860 +#define EPDC_PIGEON_2_0 0x880 +#define EPDC_PIGEON_2_1 0x890 +#define EPDC_PIGEON_2_2 0x8A0 +#define EPDC_PIGEON_3_0 0x8C0 +#define EPDC_PIGEON_3_1 0x8D0 +#define EPDC_PIGEON_3_2 0x8E0 +#define EPDC_PIGEON_4_0 0x900 +#define EPDC_PIGEON_4_1 0x910 +#define EPDC_PIGEON_4_2 0x920 +#define EPDC_PIGEON_5_0 0x940 +#define EPDC_PIGEON_5_1 0x950 +#define EPDC_PIGEON_5_2 0x960 +#define EPDC_PIGEON_6_0 0x980 +#define EPDC_PIGEON_6_1 0x990 +#define EPDC_PIGEON_6_2 0x9A0 +#define EPDC_PIGEON_7_0 0x9C0 +#define EPDC_PIGEON_7_1 0x9D0 +#define EPDC_PIGEON_7_2 0x9E0 +#define EPDC_PIGEON_8_0 0xA00 +#define EPDC_PIGEON_8_1 0xA10 +#define EPDC_PIGEON_8_2 0xA20 +#define EPDC_PIGEON_9_0 0xA40 +#define EPDC_PIGEON_9_1 0xA50 +#define EPDC_PIGEON_9_2 0xA60 +#define EPDC_PIGEON_10_0 0xA80 +#define EPDC_PIGEON_10_1 0xA90 +#define EPDC_PIGEON_10_2 0xAA0 +#define EPDC_PIGEON_11_0 0xAC0 +#define EPDC_PIGEON_11_1 0xAD0 +#define EPDC_PIGEON_11_2 0xAE0 +#define EPDC_PIGEON_12_0 0xB00 +#define EPDC_PIGEON_12_1 0xB10 +#define EPDC_PIGEON_12_2 0xB20 +#define EPDC_PIGEON_13_0 0xB40 +#define EPDC_PIGEON_13_1 0xB50 +#define EPDC_PIGEON_13_2 0xB60 +#define EPDC_PIGEON_14_0 0xB80 +#define EPDC_PIGEON_14_1 0xB90 +#define EPDC_PIGEON_14_2 0xBA0 +#define EPDC_PIGEON_15_0 0xBC0 +#define EPDC_PIGEON_15_1 0xBD0 +#define EPDC_PIGEON_15_2 0xBE0 +#define EPDC_PIGEON_16_0 0xC00 +#define EPDC_PIGEON_16_1 0xC10 +#define EPDC_PIGEON_16_2 0xC20 +#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) +#define EPDC_WB_ADDR_TCE 0x010 +#else +#define EPDC_WB_ADDR_TCE 0xC10 +#endif + +#define REG_RD(base, reg) \ + (*(volatile unsigned int *)((base) + (reg))) +#define REG_WR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg))) = (value)) +#define REG_SET(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _SET))) = (value)) +#define REG_CLR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _CLR))) = (value)) +#define REG_TOG(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _TOG))) = (value)) +/* + * Register field definitions + */ + +enum { +/* EPDC_CTRL field values */ + EPDC_CTRL_SFTRST = 0x80000000, + EPDC_CTRL_CLKGATE = 0x40000000, + EPDC_CTRL_SRAM_POWERDOWN = 0x100, + EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xC0, + EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0, + EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40, + EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80, + EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xC0, + EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30, + EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0, + EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10, + EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20, + EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30, + EPDC_CTRL_BURST_LEN_8_8 = 0x1, + EPDC_CTRL_BURST_LEN_8_16 = 0, + +/* EPDC_RES field values */ + EPDC_RES_VERTICAL_MASK = 0x1FFF0000, + EPDC_RES_VERTICAL_OFFSET = 16, + EPDC_RES_HORIZONTAL_MASK = 0x1FFF, + EPDC_RES_HORIZONTAL_OFFSET = 0, + +/* EPDC_FORMAT field values */ + EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000, + EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xFF0000, + EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16, + EPDC_FORMAT_WB_ADDR_NO_COPY = 0x4000, + EPDC_FORMAT_WB_TYPE_MASK = 0x3000, + EPDC_FORMAT_WB_TYPE_OFFSET = 12, + EPDC_FORMAT_WB_TYPE_WB_INTERNAL = 0x0, + EPDC_FORMAT_WB_TYPE_WB_WAVEFORM = 0x1000, + EPDC_FORMAT_WB_TYPE_WB_EXTERNAL16 = 0x2000, + EPDC_FORMAT_WB_TYPE_WB_EXTERNAL32 = 0x3000, + EPDC_FORMAT_WB_COMPRESS = 0x800, + EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK = 0x700, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500, + EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0, + EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1, + EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2, + EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3, + +/* EPDC_WB_FIELD field values */ + EPDC_WB_FIELD_FIXED_MASK = 0xFF000000, + EPDC_WB_FIELD_FIXED_OFFSET = 24, + EPDC_WB_FIELD_USE_FIXED_MASK = 0x30000, + EPDC_WB_FIELD_USE_FIXED_OFFSET = 16, + EPDC_WB_FIELD_USE_FIXED_NO_FIXED = 0x0, + EPDC_WB_FIELD_USE_FIXED_USE_FIXED = 0x1, + EPDC_WB_FIELD_USE_FIXED_NE_FIXED = 0x2, + EPDC_WB_FIELD_USE_FIXED_EQ_FIXED = 0x3, + EPDC_WB_FIELD_USAGE_MASK = 0xE000, + EPDC_WB_FIELD_USAGE_OFFSET = 13, + EPDC_WB_FIELD_USAGE_NOT_USED = 0x0, + EPDC_WB_FIELD_USAGE_PARTIAL = 0x3, + EPDC_WB_FIELD_USAGE_LUT = 0x4, + EPDC_WB_FIELD_USAGE_CP = 0x5, + EPDC_WB_FIELD_USAGE_NP = 0x6, + EPDC_WB_FIELD_USAGE_PTS = 0x7, + EPDC_WB_FIELD_FROM_MASK = 0x1F00, + EPDC_WB_FIELD_FROM_OFFSET = 8, + EPDC_WB_FIELD_TO_MASK = 0xF0, + EPDC_WB_FIELD_TO_OFFSET = 4, + EPDC_WB_FIELD_LEN_MASK = 0xF, + EPDC_WB_FIELD_LEN_OFFSET = 0, + +/* EPDC_FIFOCTRL field values */ + EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000, + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xFF0000, + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16, + EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xFF00, + EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8, + EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xFF, + EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0, + +/* EPDC_UPD_CORD field values */ + EPDC_UPD_CORD_YCORD_MASK = 0x1FFF0000, + EPDC_UPD_CORD_YCORD_OFFSET = 16, + EPDC_UPD_CORD_XCORD_MASK = 0x1FFF, + EPDC_UPD_CORD_XCORD_OFFSET = 0, + +/* EPDC_UPD_SIZE field values */ + EPDC_UPD_SIZE_HEIGHT_MASK = 0x1FFF0000, + EPDC_UPD_SIZE_HEIGHT_OFFSET = 16, + EPDC_UPD_SIZE_WIDTH_MASK = 0x1FFF, + EPDC_UPD_SIZE_WIDTH_OFFSET = 0, + +/* EPDC_UPD_CTRL field values */ + EPDC_UPD_CTRL_USE_FIXED = 0x80000000, +#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) + EPDC_UPD_CTRL_LUT_SEL_MASK = 0x3F0000, +#else + EPDC_UPD_CTRL_LUT_SEL_MASK = 0xF0000, +#endif + EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16, + EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xFF00, + EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8, + EPDC_UPD_CTRL_NO_LUT_CANCEL = 0x10, + EPDC_UPD_CTRL_AUTOWV_PAUSE = 0x8, + EPDC_UPD_CTRL_AUTOWV = 0x4, + EPDC_UPD_CTRL_DRY_RUN = 0x2, + EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1, + +/* EPDC_UPD_FIXED field values */ + EPDC_UPD_FIXED_FIXNP_EN = 0x80000000, + EPDC_UPD_FIXED_FIXCP_EN = 0x40000000, + EPDC_UPD_FIXED_FIXNP_MASK = 0xFF00, + EPDC_UPD_FIXED_FIXNP_OFFSET = 8, + EPDC_UPD_FIXED_FIXCP_MASK = 0xFF, + EPDC_UPD_FIXED_FIXCP_OFFSET = 0, + +/* EPDC_AUTOWV_LUT field values */ + EPDC_AUTOWV_LUT_DATA_MASK = 0xFF0000, + EPDC_AUTOWV_LUT_DATA_OFFSET = 16, +#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) + EPDC_AUTOWV_LUT_ADDR_MASK = 0x7, +#else + EPDC_AUTOWV_LUT_ADDR_MASK = 0xFF, +#endif + EPDC_AUTOWV_LUT_ADDR_OFFSET = 0, + +/* EPDC_TCE_CTRL field values */ + EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1FF0000, + EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16, + EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xC00, + EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10, + EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200, + EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000, + EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100, + EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80, + EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40, + EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20, + EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10, + EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8, + EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3, + +/* EPDC_TCE_SDCFG field values */ + EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000, + EPDC_TCE_SDCFG_SDSHR = 0x100000, + EPDC_TCE_SDCFG_NUM_CE_MASK = 0xF0000, + EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16, + EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0, + EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000, + EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000, + EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1FFF, + EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0, + +/* EPDC_TCE_GDCFG field values */ + EPDC_TCE_SDCFG_GDRL = 0x10, + EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2, + EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1, + EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0, + +/* EPDC_TCE_HSCAN1 field values */ + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xFFF0000, + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16, + EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xFFF, + EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0, + +/* EPDC_TCE_HSCAN2 field values */ + EPDC_TCE_HSCAN2_LINE_END_MASK = 0xFFF0000, + EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16, + EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xFFF, + EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0, + +/* EPDC_TCE_VSCAN field values */ + EPDC_TCE_VSCAN_FRAME_END_MASK = 0xFF0000, + EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16, + EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xFF00, + EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8, + EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xFF, + EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0, + +/* EPDC_TCE_OE field values */ + EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xFF000000, + EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24, + EPDC_TCE_OE_SDOED_DLY_MASK = 0xFF0000, + EPDC_TCE_OE_SDOED_DLY_OFFSET = 16, + EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xFF00, + EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8, + EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xFF, + EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0, + +/* EPDC_TCE_POLARITY field values */ + EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10, + EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8, + EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4, + EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2, + EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1, + +/* EPDC_TCE_TIMING1 field values */ + EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00, + EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10, + EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20, + EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30, + EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8, + EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0, + EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1, + EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2, + EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3, + +/* EPDC_TCE_TIMING2 field values */ + EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xFFFF0000, + EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16, + EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xFFFF, + EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0, + +/* EPDC_TCE_TIMING3 field values */ + EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xFFFF0000, + EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16, + EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xFFFF, + EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0, + +/* EPDC EPDC_PIGEON_CTRL0 field values */ + EPDC_PIGEON_CTRL0_LD_PERIOD_MASK = 0xFFF0000, + EPDC_PIGEON_CTRL0_LD_PERIOD_OFFSET = 16, + EPDC_PIGEON_CTRL0_FD_PERIOD_MASK = 0xFFF, + EPDC_PIGEON_CTRL0_FD_PERIOD_OFFSET = 0, + +/* EPDC EPDC_PIGEON_CTRL1 field values */ + EPDC_PIGEON_CTRL1_LD_PERIOD_MASK = 0xFFF0000, + EPDC_PIGEON_CTRL1_LD_PERIOD_OFFSET = 16, + EPDC_PIGEON_CTRL1_FD_PERIOD_MASK = 0xFFF, + EPDC_PIGEON_CTRL1_FD_PERIOD_OFFSET = 0, + +/* EPDC_IRQ_MASK/EPDC_IRQ field values */ + EPDC_IRQ_WB_CMPLT_IRQ = 0x10000, + EPDC_IRQ_LUT_COL_IRQ = 0x20000, + EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000, + EPDC_IRQ_FRAME_END_IRQ = 0x80000, + EPDC_IRQ_BUS_ERROR_IRQ = 0x100000, + EPDC_IRQ_TCE_IDLE_IRQ = 0x200000, + EPDC_IRQ_UPD_DONE_IRQ = 0x400000, + EPDC_IRQ_PWR_IRQ = 0x800000, + +/* EPDC_STATUS_NEXTLUT field values */ + EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100, + EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0x3F, + EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0, + +/* EPDC_STATUS field values */ + EPDC_STATUS_HISTOGRAM_CP_MASK = 0x1F0000, + EPDC_STATUS_HISTOGRAM_CP_OFFSET = 16, + EPDC_STATUS_HISTOGRAM_NP_MASK = 0x1F00, + EPDC_STATUS_HISTOGRAM_NP_OFFSET = 8, + EPDC_STATUS_UPD_VOID = 0x8, + EPDC_STATUS_LUTS_UNDERRUN = 0x4, + EPDC_STATUS_LUTS_BUSY = 0x2, + EPDC_STATUS_WB_BUSY = 0x1, + +/* EPDC_UPD_COL_CORD field values */ + EPDC_UPD_COL_CORD_YCORD_MASK = 0x1FFF0000, + EPDC_UPD_COL_CORD_YCORD_OFFSET = 16, + EPDC_UPD_COL_CORD_XCORD_MASK = 0x1FFF, + EPDC_UPD_COL_CORD_XCORD_OFFSET = 0, + +/* EPDC_UPD_COL_SIZE field values */ + EPDC_UPD_COL_SIZE_HEIGHT_MASK = 0x1FFF0000, + EPDC_UPD_COL_SIZE_HEIGHT_OFFSET = 16, + EPDC_UPD_COL_SIZE_WIDTH_MASK = 0x1FFF, + EPDC_UPD_COL_SIZE_WIDTH_OFFSET = 0, + +/* EPDC_DEBUG field values */ + EPDC_DEBUG_DEBUG_LUT_SEL_MASK = 0x3F00000, + EPDC_DEBUG_DEBUG_LUT_SEL_OFFSET = 24, + EPDC_DEBUG_UBW_BURST_LEN_MASK = 0xF000, + EPDC_DEBUG_UBW_BURST_LEN_OFFSET = 12, + EPDC_DEBUG_UBR_BURST_LEN_MASK = 0xF00, + EPDC_DEBUG_UBR_BURST_LEN = 8, + EPDC_DEBUG_UPD_BURST_LEN_MASK = 0xF0, + EPDC_DEBUG_UPD_BURST_LEN_OFFSET = 4, + EPDC_DEBUG_UPDATE_SAME = 0x4, + EPDC_DEBUG_UNDERRUN_RECOVER = 0x2, + EPDC_DEBUG_COLLISION_OFF = 0x1, + +/* EPDC_DEBUG_LUT field values */ + EPDC_DEBUG_LUT_LUTADDR_MASK = 0x3FF0000, + EPDC_DEBUG_LUT_LUTADDR_OFFSET = 16, + EPDC_DEBUG_LUT_FRAME_MASK = 0x7FE0, + EPDC_DEBUG_LUT_FRAME_OFFSET = 5, + EPDC_DEBUG_LUT_STATEMACHINE_MASK = 0x1F, + EPDC_DEBUG_LUT_STATEMACHINE_OFFSET = 0, + +/* EPDC_HISTx_PARAM field values */ + EPDC_HIST_PARAM_VALUE0_MASK = 0x1F, + EPDC_HIST_PARAM_VALUE0_OFFSET = 0, + EPDC_HIST_PARAM_VALUE1_MASK = 0x1F00, + EPDC_HIST_PARAM_VALUE1_OFFSET = 8, + EPDC_HIST_PARAM_VALUE2_MASK = 0x1F0000, + EPDC_HIST_PARAM_VALUE2_OFFSET = 16, + EPDC_HIST_PARAM_VALUE3_MASK = 0x1F000000, + EPDC_HIST_PARAM_VALUE3_OFFSET = 24, + EPDC_HIST_PARAM_VALUE4_MASK = 0x1F, + EPDC_HIST_PARAM_VALUE4_OFFSET = 0, + EPDC_HIST_PARAM_VALUE5_MASK = 0x1F00, + EPDC_HIST_PARAM_VALUE5_OFFSET = 8, + EPDC_HIST_PARAM_VALUE6_MASK = 0x1F0000, + EPDC_HIST_PARAM_VALUE6_OFFSET = 16, + EPDC_HIST_PARAM_VALUE7_MASK = 0x1F000000, + EPDC_HIST_PARAM_VALUE7_OFFSET = 24, + EPDC_HIST_PARAM_VALUE8_MASK = 0x1F, + EPDC_HIST_PARAM_VALUE8_OFFSET = 0, + EPDC_HIST_PARAM_VALUE9_MASK = 0x1F00, + EPDC_HIST_PARAM_VALUE9_OFFSET = 8, + EPDC_HIST_PARAM_VALUE10_MASK = 0x1F0000, + EPDC_HIST_PARAM_VALUE10_OFFSET = 16, + EPDC_HIST_PARAM_VALUE11_MASK = 0x1F000000, + EPDC_HIST_PARAM_VALUE11_OFFSET = 24, + EPDC_HIST_PARAM_VALUE12_MASK = 0x1F, + EPDC_HIST_PARAM_VALUE12_OFFSET = 0, + EPDC_HIST_PARAM_VALUE13_MASK = 0x1F00, + EPDC_HIST_PARAM_VALUE13_OFFSET = 8, + EPDC_HIST_PARAM_VALUE14_MASK = 0x1F0000, + EPDC_HIST_PARAM_VALUE14_OFFSET = 16, + EPDC_HIST_PARAM_VALUE15_MASK = 0x1F000000, + EPDC_HIST_PARAM_VALUE15_OFFSET = 24, + +/* EPDC_GPIO field values */ + EPDC_GPIO_PWRSTAT = 0x100, + EPDC_GPIO_PWRWAKE = 0x80, + EPDC_GPIO_PWRCOM = 0x40, + EPDC_GPIO_PWRCTRL_MASK = 0x3C, + EPDC_GPIO_PWRCTRL_OFFSET = 2, + EPDC_GPIO_BDR_MASK = 0x3, + EPDC_GPIO_BDR_OFFSET = 0, + +/* EPDC_VERSION field values */ + EPDC_VERSION_MAJOR_MASK = 0xFF000000, + EPDC_VERSION_MAJOR_OFFSET = 24, + EPDC_VERSION_MINOR_MASK = 0xFF0000, + EPDC_VERSION_MINOR_OFFSET = 16, + EPDC_VERSION_STEP_MASK = 0xFFFF, + EPDC_VERSION_STEP_OFFSET = 0, +}; + +int board_setup_waveform_file(ulong waveform_buf); +int board_setup_logo_file(void *display_buf); +void epdc_power_on(void); +void epdc_power_off(void); + +extern void *lcd_base; + +#endif /* __EPDC_REGS_INCLUDED__ */ diff --git a/include/mxc_keyb.h b/include/mxc_keyb.h new file mode 100644 index 00000000000..eba8b770c86 --- /dev/null +++ b/include/mxc_keyb.h @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * @defgroup keypad Keypad Driver + */ + +/*! + * @file mxc_keyb.h + * + * @brief MXC keypad header file. + * + * @ingroup keypad + */ +#ifndef __MXC_KEYB_H__ +#define __MXC_KEYB_H__ + +/*! + * Keypad Module Name + */ +#define MOD_NAME "mxckpd" + +/*! + * Keypad irq number + */ +#define KPP_IRQ MXC_INT_KPP + +/*! + * XLATE mode selection + */ +#define KEYPAD_XLATE 0 + +/*! + * RAW mode selection + */ +#define KEYPAD_RAW 1 + +/*! + * Maximum number of keys. + */ +#define MAXROW 8 +#define MAXCOL 8 +#define MXC_MAXKEY (MAXROW * MAXCOL) + +/*! + * This define indicates break scancode for every key release. A constant + * of 128 is added to the key press scancode. + */ +#define MXC_KEYRELEASE 128 + +/* + * _reg_KPP_KPCR _reg_KPP_KPSR _reg_KPP_KDDR _reg_KPP_KPDR + * Keypad Control Register Address + */ +#define KPCR (KPP_BASE_ADDR + 0x00) + +/* + * Keypad Status Register Address + */ +#define KPSR (KPP_BASE_ADDR + 0x02) + +/* + * Keypad Data Direction Address + */ +#define KDDR (KPP_BASE_ADDR + 0x04) + +/* + * Keypad Data Register + */ +#define KPDR (KPP_BASE_ADDR + 0x06) + +/* + * Key Press Interrupt Status bit + */ +#define KBD_STAT_KPKD 0x01 + +/* + * Key Release Interrupt Status bit + */ +#define KBD_STAT_KPKR 0x02 + +/* + * Key Depress Synchronizer Chain Status bit + */ +#define KBD_STAT_KDSC 0x04 + +/* + * Key Release Synchronizer Status bit + */ +#define KBD_STAT_KRSS 0x08 + +/* + * Key Depress Interrupt Enable Status bit + */ +#define KBD_STAT_KDIE 0x100 + +/* + * Key Release Interrupt Enable + */ +#define KBD_STAT_KRIE 0x200 + +/* + * Keypad Clock Enable + */ +#define KBD_STAT_KPPEN 0x400 + +/*! + * Buffer size of keypad queue. Should be a power of 2. + */ +#define KPP_BUF_SIZE 128 + +/*! + * Test whether bit is set for integer c + */ +#define TEST_BIT(c, n) ((c) & (0x1 << (n))) + +/*! + * Set nth bit in the integer c + */ +#define BITSET(c, n) ((c) | (1 << (n))) + +/*! + * Reset nth bit in the integer c + */ +#define BITRESET(c, n) ((c) & ~(1 << (n))) + +enum KeyEvent { + KDepress, + KRelease +}; + +/*! + * This enum represents the keypad state machine to maintain debounce logic + * for key press/release. + */ +enum KeyState { + + /*! + * Key press state. + */ + KStateUp, + + /*! + * Key press debounce state. + */ + KStateFirstDown, + + /*! + * Key release state. + */ + KStateDown, + + /*! + * Key release debounce state. + */ + KStateFirstUp +}; + +/*! + * Keypad Private Data Structure + */ +struct keypad_priv { + + /*! + * Keypad state machine. + */ + enum KeyState iKeyState; + + /*! + * Number of rows configured in the keypad matrix + */ + unsigned long kpp_rows; + + /*! + * Number of Columns configured in the keypad matrix + */ + unsigned long kpp_cols; +}; + +/*! + * Keypad Data Structure + * */ +struct kpp_key_info { + enum KeyEvent evt; + unsigned short val; +}; + +int mxc_kpp_init(void); +int mxc_kpp_getc(struct kpp_key_info **); + +/*! + * These functions are used to configure and the GPIO pins for keypad to + * activate and deactivate it. + */ +void setup_mxc_kpd(void); + + +#endif /* __MXC_KEYB_H__ */ diff --git a/include/mxsfb.h b/include/mxsfb.h new file mode 100644 index 00000000000..85f24aa2865 --- /dev/null +++ b/include/mxsfb.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MXSFB_H__ +#define __MXSFB_H__ + +#include + +#ifdef CONFIG_VIDEO_MXS +struct display_panel { + unsigned int reg_base; + unsigned int width; + unsigned int height; + unsigned int gdfindex; + unsigned int gdfbytespp; +}; + +void mxs_lcd_get_panel(struct display_panel *panel); +void lcdif_power_down(void); +int mxs_lcd_panel_setup(struct fb_videomode mode, int bpp, + uint32_t base_addr); +#endif + +#endif /* __MXSFB_H__ */ diff --git a/include/netdev.h b/include/netdev.h index 3958a4cd32d..c96f851be03 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -119,11 +119,7 @@ static inline int pci_eth_init(bd_t *bis) return num; } -#ifdef CONFIG_DM_ETH -struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id); -#else -struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id); -#endif +struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id); #ifdef CONFIG_PHYLIB struct phy_device; diff --git a/include/part.h b/include/part.h index 0caceafc5f7..b39800b1f3e 100644 --- a/include/part.h +++ b/include/part.h @@ -94,6 +94,7 @@ struct disk_part { struct blk_desc *blk_get_dev(const char *ifname, int dev); struct blk_desc *mg_disk_get_dev(int dev); +struct blk_desc *sata_get_dev(int dev); int host_get_dev_err(int dev, struct blk_desc **blk_devp); /* disk/part.c */ @@ -221,6 +222,7 @@ extern const struct block_drvr block_drvr[]; static inline struct blk_desc *blk_get_dev(const char *ifname, int dev) { return NULL; } static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; } +static inline struct blk_desc *sata_get_dev(int dev) { return NULL; } static inline int part_get_info(struct blk_desc *dev_desc, int part, disk_partition_t *info) { return -1; } @@ -248,7 +250,8 @@ static inline int blk_get_device_part_str(const char *ifname, #ifdef CONFIG_SPL_BUILD # define part_print_ptr(x) NULL # if defined(CONFIG_SPL_EXT_SUPPORT) || defined(CONFIG_SPL_FAT_SUPPORT) || \ - defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION) + defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION) || \ + defined(CONFIG_DUAL_BOOTLOADER) # define part_get_info_ptr(x) x # else # define part_get_info_ptr(x) NULL @@ -372,6 +375,14 @@ int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf); */ int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf); +/** + * write_backup_gpt_partitions - write MBR, backup gpt table. + * @param dev_desc - block device descriptor + * @param buf - buffer which contains the MBR and Primary GPT info + * + * @return - '0' on success, otherwise error + */ +int write_backup_gpt_partitions(struct blk_desc *dev_desc, void *buf); /** * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header * and partition table entries (PTE) diff --git a/include/power-domain.h b/include/power-domain.h index 10999790b56..7fa85640f98 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2016, NVIDIA CORPORATION. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0 */ @@ -75,6 +76,19 @@ struct power_domain { unsigned long id; }; +/** + * power_domain_lookup_name - Lookup the power domain device by name and request it. + * + * This looks up and requests a provider power domain by using its device name. This + * skip the associated client device, but directly get the power domain device. + * + * @name: The power domain device's name. + * @power_domain A pointer to a power domain struct to initialize. + * @return 0 if OK, or a negative error code. + */ + +int power_domain_lookup_name(const char *name, struct power_domain *power_domain); + /** * power_domain_get - Get/request the power domain for a device. * diff --git a/include/power/bd71837.h b/include/power/bd71837.h new file mode 100644 index 00000000000..189c3df5f3d --- /dev/null +++ b/include/power/bd71837.h @@ -0,0 +1,62 @@ + +#ifndef BD71837_H_ +#define BD71837_H_ + +#define BD71837_REGULATOR_DRIVER "bd71837_regulator" + +enum { + BD71837_REV = 0x00, + BD71837_SWRESET = 0x01, + BD71837_I2C_DEV = 0x02, + BD71837_PWRCTRL0 = 0x03, + BD71837_PWRCTRL1 = 0x04, + BD71837_BUCK1_CTRL = 0x05, + BD71837_BUCK2_CTRL = 0x06, + BD71837_BUCK3_CTRL = 0x07, + BD71837_BUCK4_CTRL = 0x08, + BD71837_BUCK5_CTRL = 0x09, + BD71837_BUCK6_CTRL = 0x0A, + BD71837_BUCK7_CTRL = 0x0B, + BD71837_BUCK8_CTRL = 0x0C, + BD71837_BUCK1_VOLT_RUN = 0x0D, + BD71837_BUCK1_VOLT_IDLE = 0x0E, + BD71837_BUCK1_VOLT_SUSP = 0x0F, + BD71837_BUCK2_VOLT_RUN = 0x10, + BD71837_BUCK2_VOLT_IDLE = 0x11, + BD71837_BUCK3_VOLT_RUN = 0x12, + BD71837_BUCK4_VOLT_RUN = 0x13, + BD71837_BUCK5_VOLT = 0x14, + BD71837_BUCK6_VOLT = 0x15, + BD71837_BUCK7_VOLT = 0x16, + BD71837_BUCK8_VOLT = 0x17, + BD71837_LDO1_VOLT = 0x18, + BD71837_LDO2_VOLT = 0x19, + BD71837_LDO3_VOLT = 0x1A, + BD71837_LDO4_VOLT = 0x1B, + BD71837_LDO5_VOLT = 0x1C, + BD71837_LDO6_VOLT = 0x1D, + BD71837_LDO7_VOLT = 0x1E, + BD71837_TRANS_COND0 = 0x1F, + BD71837_TRANS_COND1 = 0x20, + BD71837_VRFAULTEN = 0x21, + BD71837_MVRFLTMASK0 = 0x22, + BD71837_MVRFLTMASK1 = 0x23, + BD71837_MVRFLTMASK2 = 0x24, + BD71837_RCVCFG = 0x25, + BD71837_RCVNUM = 0x26, + BD71837_PWRONCONFIG0 = 0x27, + BD71837_PWRONCONFIG1 = 0x28, + BD71837_RESETSRC = 0x29, + BD71837_MIRQ = 0x2A, + BD71837_IRQ = 0x2B, + BD71837_IN_MON = 0x2C, + BD71837_POW_STATE = 0x2D, + BD71837_OUT32K = 0x2E, + BD71837_REGLOCK = 0x2F, + BD71837_MUXSW_EN = 0x30, + BD71837_REG_NUM, +}; + +int power_bd71837_init(unsigned char bus); + +#endif diff --git a/include/recovery.h b/include/recovery.h new file mode 100644 index 00000000000..4519cffcb7a --- /dev/null +++ b/include/recovery.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __RECOVERY_H_ +#define __RECOVERY_H_ + +struct reco_envs { + char *cmd; + char *args; +}; + +void board_recovery_setup(void); + +#endif diff --git a/include/sec_mipi_dsim.h b/include/sec_mipi_dsim.h new file mode 100644 index 00000000000..7bce9707f27 --- /dev/null +++ b/include/sec_mipi_dsim.h @@ -0,0 +1,20 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SEC_MIPI_DSIM_H__ +#define __SEC_MIPI_DSIM_H__ + +struct sec_mipi_dsim_plat_data { + uint32_t version; + uint32_t max_data_lanes; + uint64_t max_data_rate; + ulong reg_base; + ulong gpr_base; +}; + +int sec_mipi_dsim_setup(const struct sec_mipi_dsim_plat_data *plat_data); + +#endif diff --git a/include/serial.h b/include/serial.h index d87f01082a0..2f3315e3a73 100644 --- a/include/serial.h +++ b/include/serial.h @@ -97,6 +97,14 @@ struct dm_serial_ops { * @return character (0..255), -ve on error */ int (*getc)(struct udevice *dev); + /** + * puts() - puts a string + * + * @dev: Device pointer + * @str: string to write + * @return 0 if OK, -ve on error + */ + int (*puts)(struct udevice *dev, const char *str); /** * putc() - Write a character * diff --git a/include/spl.h b/include/spl.h index c14448b8fc9..199ce33e7f8 100644 --- a/include/spl.h +++ b/include/spl.h @@ -33,6 +33,9 @@ struct spl_image_info { u32 size; u32 flags; void *arg; +#ifdef CONFIG_DUAL_BOOTLOADER + uint64_t rbindex; +#endif }; /* @@ -77,6 +80,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, struct spl_load_info *info, ulong sector, void *fdt); #define SPL_COPY_PAYLOAD_ONLY 1 +#define SPL_FIT_FOUND 2 /* SPL common functions */ void preloader_console_init(void); @@ -95,6 +99,19 @@ void spl_set_bd(void); */ void spl_set_header_raw_uboot(struct spl_image_info *spl_image); + + +/** + * spl_set_header_raw_atf() - Set up a standard SPL image structure for ATF + * + * This sets up the given spl_image which the standard values obtained from + * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START, + * CONFIG_SYS_TEXT_BASE. + * + * @spl_image: Image description to set up + */ +void spl_set_header_raw_atf(struct spl_image_info *spl_image); + /** * spl_parse_image_header() - parse the image header and set up info * diff --git a/include/trusty/avb.h b/include/trusty/avb.h new file mode 100644 index 00000000000..daaac2cae54 --- /dev/null +++ b/include/trusty/avb.h @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_AVB_H_ +#define TRUSTY_AVB_H_ + +#include +#include +#include + +/* + * Initialize AVB TIPC client. Returns one of trusty_err. + * + * @dev: initialized with trusty_ipc_dev_create + */ +int avb_tipc_init(struct trusty_ipc_dev *dev); +/* + * Shutdown AVB TIPC client. + * + * @dev: initialized with trusty_ipc_dev_create + */ +void avb_tipc_shutdown(struct trusty_ipc_dev *dev); +/* + * Send request to secure side to read rollback index. + * Returns one of trusty_err. + * + * @slot: rollback index slot + * @value: rollback index value stored here + */ +int trusty_read_rollback_index(uint32_t slot, uint64_t *value); +/* + * Send request to secure side to write rollback index + * Returns one of trusty_err. + * + * @slot: rollback index slot + * @value: rollback index value to write + */ +int trusty_write_rollback_index(uint32_t slot, uint64_t value); +/* + * Send request to secure side to read permanent attributes. When permanent + * attributes are stored in RPMB, a hash of the permanent attributes which is + * given to AVB during verification MUST still be backed by write-once hardware. + * + * Copies attributes received by secure side to |attributes|. If |size| does not + * match the size returned by the secure side, an error is returned. Returns one + * of trusty_err. + * + * @attributes: caller allocated buffer + * @size: size of |attributes| + */ +int trusty_read_permanent_attributes(uint8_t *attributes, uint32_t size); +/* + * Send request to secure side to write permanent attributes. Permanent + * attributes can only be written to storage once. + * + * Returns one of trusty_err. + */ +int trusty_write_permanent_attributes(uint8_t *attributes, uint32_t size); +/* + * Send request to secure side to read vbmeta public key. + * + * Copies public key received by secure side to |publickey|. If |size| does not + * match the size returned by the secure side, an error is returned. Returns one + * of trusty_err. + * + * @publickey: caller allocated buffer + * @size: size of |publickey| + */ +int trusty_read_vbmeta_public_key(uint8_t *publickey, uint32_t size); +/* + * Send request to secure side to write vbmeta public key. Public key + * can only be written to storage once. + * + * Returns one of trusty_err. + */ +int trusty_write_vbmeta_public_key(uint8_t *publickey, uint32_t size); +/* + * Send request to secure side to read device lock state from RPMB. + * + * Returns one of trusty_err. + */ +int trusty_read_lock_state(uint8_t *lock_state); +/* + * Send request to secure side to write device lock state to RPMB. If the lock + * state is changed, all rollback index data will be cleared. + * + * Returns one of trusty_err. + */ +int trusty_write_lock_state(uint8_t lock_state); +/* + * Send request to secure side to lock the boot state. After this is invoked, + * the non-secure side will not be able to write to data managed by the AVB + * service until next boot. + * + * Returns one of trusty_err. + */ +int trusty_lock_boot_state(void); + +#endif /* TRUSTY_AVB_H_ */ diff --git a/include/trusty/hwcrypto.h b/include/trusty/hwcrypto.h new file mode 100644 index 00000000000..9a510a889d7 --- /dev/null +++ b/include/trusty/hwcrypto.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * Copyright NXP 2018 + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + */ + +#ifndef TRUSTY_HWCRYPTO_H_ +#define TRUSTY_HWCRYPTO_H_ + +#include +#include +#include + +/* + * Initialize HWCRYPTO TIPC client. Returns one of trusty_err. + * + * @dev: initialized with trusty_ipc_dev_create + */ +int hwcrypto_tipc_init(struct trusty_ipc_dev *dev); +/* + * Shutdown HWCRYPTO TIPC client. + * + * @dev: initialized with trusty_ipc_dev_create + */ +void hwcrypto_tipc_shutdown(struct trusty_ipc_dev *dev); +/* + * Send request to secure side to calculate sha256 hash with caam. + * Returns one of trusty_err. + * + * @in_addr: start address of the input buf + * @in_len: size of the input buf + * @out_addr: start address of the output buf + * @out_len: size of the output buf + * @algo: hash algorithm type expect to use + */ +int hwcrypto_hash(uint32_t in_addr, uint32_t in_len, uint32_t out_addr, + uint32_t out_len, enum hwcrypto_hash_algo algo); + +/* + * Send request to secure side to generate blob with caam. + * Returns one of trusty_err. + * + * @plain_pa: physical start address of the plain blob buffer. + * @plain_size: size of the plain blob buffer. + * @blob_pa: physical start address of the generated blob buffer. + */ +int hwcrypto_gen_blob(uint32_t plain_pa, + uint32_t plain_size, uint32_t blob_pa); + +/* Send request to secure side to generate rng with caam. + * Returns one of trusty_err. + * + * @buf: physical start address of the output rng buf. + * @len: size of required rng. + * */ +int hwcrypto_gen_rng(uint32_t buf, uint32_t len); +#endif /* TRUSTY_HWCRYPTO_H_ */ diff --git a/include/trusty/keymaster.h b/include/trusty/keymaster.h new file mode 100644 index 00000000000..eadb0d13196 --- /dev/null +++ b/include/trusty/keymaster.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_KEYMASTER_H_ +#define TRUSTY_KEYMASTER_H_ + +#include +#include +#include + +/* + * Initialize Keymaster TIPC client. Returns one of trusty_err. + * + * @dev: initialized with trusty_ipc_dev_create + */ +int km_tipc_init(struct trusty_ipc_dev *dev); + +/* + * Shutdown Keymaster TIPC client. + * + * @dev: initialized with trusty_ipc_dev_create + */ +void km_tipc_shutdown(struct trusty_ipc_dev *dev); + +/* + * Set Keymaster boot parameters. Returns one of trusty_err. + * + * @os_version: OS version from Android image header + * @os_patchlevel: OS patch level from Android image header + * @verified_boot_state: one of keymaster_verified_boot_t + * @device_locked: nonzero if device is locked + * @verified_boot_key_hash: hash of key used to verify Android image + * @verified_boot_key_hash_size: size of verified_boot_key_hash + * @verified_boot_hash: cumulative hash of all images verified thus far. + * May be NULL if not computed. + * @verified_boot_hash_size: size of verified_boot_hash + */ +int trusty_set_boot_params(uint32_t os_version, uint32_t os_patchlevel, + keymaster_verified_boot_t verified_boot_state, + bool device_locked, + const uint8_t *verified_boot_key_hash, + uint32_t verified_boot_key_hash_size, + const uint8_t *verified_boot_hash, + uint32_t verified_boot_hash_size); + +/* + * Set Keymaster attestation key. Returns one of trusty_err. + * + * @key: buffer containing key + * @key_size: size of key in bytes + * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC + */ +int trusty_set_attestation_key(const uint8_t *key, uint32_t key_size, + keymaster_algorithm_t algorithm); + +/* + * Append certificate to Keymaster attestation certificate chain. Returns + * one of trusty_err. + * + * @cert: buffer containing certificate + * @cert_size: size of certificate in bytes + * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC + */ +int trusty_append_attestation_cert_chain(const uint8_t *cert, + uint32_t cert_size, + keymaster_algorithm_t algorithm); +/* + * Reads a CA Request from Keymaster. On success allocates a new CA Request + * message at |*ca_request_p|, and the caller takes ownership. Returns one + * of trusty_err. + * + * @operation_start: Operation Start message + * @operation_start_size: size of operation_start + * @ca_request_p: location of newly allocated CA Request message + * @ca_request_size_p: location of size of the CA Request message + */ +int trusty_atap_get_ca_request(const uint8_t *operation_start, + uint32_t operation_start_size, + uint8_t** ca_request_p, + uint32_t* ca_request_size_p); +/* + * Sends the CA Response to Keymaster. Returns one of trusty_err. + * + * @ca_response: CA Response message + * @ca_response_size: size of ca_response + */ +int trusty_atap_set_ca_response(const uint8_t *ca_response, + uint32_t ca_response_size); + +/* +* Reads the UUID from the certificate of the last provisioned attestation +* credentials as a c-string into |*uuid_p|. Caller takes ownership of +* |*uuid_p|. Returns one of trusty_err. +* +* @uuid_p: location of newly allocated UUID c-string +*/ +int trusty_atap_read_uuid_str(char **uuid_p); + +/* + * SetProductId is only called once to set the secure product id. Caller should + * read the product id from permanent attributes structure and set the product + * id while fusing the permanent attributes. + * + * @product_id: The product id to be set. + * @size: The size of the product id. + */ +int trusty_set_product_id(const uint8_t *product_id, uint32_t size); + +#endif /* TRUSTY_KEYMASTER_H_ */ diff --git a/include/trusty/keymaster_serializable.h b/include/trusty/keymaster_serializable.h new file mode 100644 index 00000000000..196e606fe84 --- /dev/null +++ b/include/trusty/keymaster_serializable.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_KEYMASTER_SERIALIZABLE_H_ +#define TRUSTY_KEYMASTER_SERIALIZABLE_H_ + +#include + +/** + * Simple serialization routines for dynamically sized keymaster messages. + */ + +/** + * Appends |data_len| bytes at |data| to |buf|. Performs no bounds checking, + * assumes sufficient memory allocated at |buf|. Returns |buf| + |data_len|. + */ +uint8_t *append_to_buf(uint8_t *buf, const void *data, size_t data_len); + +/** + * Appends |val| to |buf|. Performs no bounds checking. Returns |buf| + + * sizeof(uint32_t). + */ +uint8_t *append_uint32_to_buf(uint8_t *buf, uint32_t val); + +/** + * Appends a sized buffer to |buf|. First appends |data_len| to |buf|, then + * appends |data_len| bytes at |data| to |buf|. Performs no bounds checking. + * Returns |buf| + sizeof(uint32_t) + |data_len|. + */ +uint8_t *append_sized_buf_to_buf(uint8_t *buf, const uint8_t *data, + uint32_t data_len); + +/** + * Serializes a km_boot_params structure. On success, allocates |*out_size| + * bytes to |*out| and writes the serialized |params| to |*out|. Caller takes + * ownership of |*out|. Returns one of trusty_err. + */ +int km_boot_params_serialize(const struct km_boot_params *params, uint8_t **out, + uint32_t *out_size); + +/** + * Serializes a km_attestation_data structure. On success, allocates |*out_size| + * bytes to |*out| and writes the serialized |data| to |*out|. Caller takes + * ownership of |*out|. Returns one of trusty_err. + */ +int km_attestation_data_serialize(const struct km_attestation_data *data, + uint8_t **out, uint32_t *out_size); + +/** + * Serializes a km_raw_buffer structure. On success, allocates |*out_size| + * bytes to |*out| and writes the serialized |data| to |*out|. Caller takes + * ownership of |*out|. Returns one of trusty_err. + */ +int km_raw_buffer_serialize(const struct km_raw_buffer *buf, uint8_t** out, + uint32_t *out_size); + +#endif /* TRUSTY_KEYMASTER_SERIALIZABLE_H_ */ diff --git a/include/trusty/libtipc.h b/include/trusty/libtipc.h new file mode 100644 index 00000000000..69e480104c2 --- /dev/null +++ b/include/trusty/libtipc.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef TRUSTY_LIBTIPC_H_ +#define TRUSTY_LIBTIPC_H_ + +#include +#include +#include + +/* + * Initialize TIPC library + */ +int trusty_ipc_init(void); +/* + * Shutdown TIPC library + */ +void trusty_ipc_shutdown(void); + +#endif /* TRUSTY_LIBTIPC_H_ */ diff --git a/include/trusty/rpmb.h b/include/trusty/rpmb.h new file mode 100644 index 00000000000..e29a608a4b3 --- /dev/null +++ b/include/trusty/rpmb.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_RPMB_H_ +#define TRUSTY_RPMB_H_ + +#include +#include + +#define MMC_BLOCK_SIZE 512 + +/* + * Initialize RPMB storage proxy. Returns one of trusty_err. + * + * @dev: initialized with trusty_ipc_dev_create + * @rpmb_dev: Context of RPMB device, initialized with rpmb_storage_get_ctx + */ +int rpmb_storage_proxy_init(struct trusty_ipc_dev *dev, void *rpmb_dev); +/* + * Shutdown RPMB storage proxy + * + * @dev: initialized with trusty_ipc_dev_create + */ +void rpmb_storage_proxy_shutdown(struct trusty_ipc_dev *dev); +/* + * Execute RPMB command. Implementation is platform specific. + * Returns one of trusty_err. + * + * @rpmb_dev: Context of RPMB device, initialized with + * rpmb_storage_get_ctx + * @reliable_write_data: Buffer containing RPMB structs for reliable write + * @reliable_write_size: Size of reliable_write_data + * @write_data: Buffer containing RPMB structs for write + * @write_size: Size of write_data + * @read_data: Buffer to be filled with RPMB structs read from RPMB + * partition + * @read_size: Size of read_data + */ +int rpmb_storage_send(void *rpmb_dev, + const void *reliable_write_data, + size_t reliable_write_size, + const void *write_data, size_t write_size, + void *read_buf, size_t read_size); +/* + * Return context for RPMB device. This is called when the RPMB storage proxy is + * initialized, and subsequently used when issuing RPMB storage requests. + * Implementation is platform specific. + */ +void *rpmb_storage_get_ctx(void); + +/* + * Put back RPMB device. This is called when the RPMB storage proxy is + * shutdown + */ +void rpmb_storage_put_ctx(void *dev); + +#endif /* TRUSTY_RPMB_H_ */ diff --git a/include/trusty/sysdeps.h b/include/trusty/sysdeps.h new file mode 100644 index 00000000000..1f26bbd4c3d --- /dev/null +++ b/include/trusty/sysdeps.h @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_SYSDEPS_H_ +#define TRUSTY_SYSDEPS_H_ +/* + * Change these includes to match your platform to bring in the equivalent + * types available in a normal C runtime. At least things like uint64_t, + * uintptr_t, and bool (with |false|, |true| keywords) must be present. + */ +#include +#include + +/* + * These attribute macros may need to be adjusted if not using gcc or clang. + */ +#define TRUSTY_ATTR_PACKED __attribute__((packed)) +#define TRUSTY_ATTR_NO_RETURN __attribute__((noreturn)) +#define TRUSTY_ATTR_SENTINEL __attribute__((__sentinel__)) +#define TRUSTY_ATTR_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) + +#define PAGE_SIZE 4096 +/* + * Struct containing attributes for memory to be shared with secure size. + */ +struct ns_mem_page_info { + uint64_t attr; +}; + +struct trusty_dev; + +/* + * Lock/unlock mutex associated with @dev. These can be safely empty in a single + * threaded environment. + * + * @dev: Trusty device initialized with trusty_dev_init + */ +void trusty_lock(struct trusty_dev *dev); +void trusty_unlock(struct trusty_dev *dev); +/* + * Disable/enable IRQ interrupts and save/restore @state + */ +void trusty_local_irq_disable(unsigned long *state); +void trusty_local_irq_restore(unsigned long *state); +/* + * Put in standby state waiting for interrupt. + * + * @dev: Trusty device initialized with trusty_dev_init + */ +void trusty_idle(struct trusty_dev *dev); +/* + * Aborts the program or reboots the device. + */ +void trusty_abort(void) TRUSTY_ATTR_NO_RETURN; +/* + * Print a formatted string. @format must point to a NULL-terminated string, and + * is followed by arguments to be printed. + */ +void trusty_printf(const char *format, ...); +/* + * Copy @n bytes from @src to @dest. + */ +void *trusty_memcpy(void *dest, const void *src, size_t n); +/* + * Set @n bytes starting at @dest to @c. Returns @dest. + */ +void *trusty_memset(void *dest, const int c, size_t n); +/* + * Copy string from @src to @dest, including the terminating NULL byte. + * + * The size of the array at @dest should be long enough to contain the string + * at @src, and should not overlap in memory with @src. + */ +char *trusty_strcpy(char *dest, const char *src); +/* + * Returns the length of @str, excluding the terminating NULL byte. + */ +size_t trusty_strlen(const char *str); +/* + * Allocate @n elements of size @size. Initializes memory to 0, returns pointer + * to it. + */ +void *trusty_calloc(size_t n, size_t size) TRUSTY_ATTR_WARN_UNUSED_RESULT; +/* + * Free memory at @addr allocated with trusty_calloc. + */ +void trusty_free(void *addr); +/* + * Allocate @count contiguous pages to be shared with secure side. + * + * Returns: vaddr of allocated memory + */ +void *trusty_alloc_pages(unsigned count) TRUSTY_ATTR_WARN_UNUSED_RESULT; +/* + * Free @count pages at @vaddr allocated by trusty_alloc_pages + */ +void trusty_free_pages(void *vaddr, unsigned count); + +#endif /* TRUSTY_SYSDEPS_H_ */ diff --git a/include/trusty/trusty_dev.h b/include/trusty/trusty_dev.h new file mode 100644 index 00000000000..27ae8cca83e --- /dev/null +++ b/include/trusty/trusty_dev.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_TRUSTY_DEV_H_ +#define TRUSTY_TRUSTY_DEV_H_ + +#include + +/* + * Architecture specific Trusty device struct. + * + * @priv_data: system dependent data, may be unused + * @api_version: TIPC version + */ +struct trusty_dev { + void *priv_data; + uint32_t api_version; +}; + +/* + * Initializes @dev with @priv, and gets the API version by calling + * into Trusty. Returns negative on error. + */ +int trusty_dev_init(struct trusty_dev *dev, void *priv); + +/* + * Cleans up anything related to @dev. Returns negative on error. + */ +int trusty_dev_shutdown(struct trusty_dev *dev); + +/* + * Invokes creation of queueless Trusty IPC device on the secure side. + * @buf will be mapped into Trusty's address space. + * + * @dev: trusty device, initialized with trusty_dev_init + * @buf: physical address info of buffer to share with Trusty + * @buf_size: size of @buf + */ +int trusty_dev_init_ipc(struct trusty_dev *dev, struct ns_mem_page_info *buf, + uint32_t buf_size); +/* + * Invokes execution of command on the secure side. + * + * @dev: trusty device, initialized with trusty_dev_init + * @buf: physical address info of shared buffer containing command + * @buf_size: size of command data + */ +int trusty_dev_exec_ipc(struct trusty_dev *dev, struct ns_mem_page_info *buf, + uint32_t buf_size); +/* + * Invokes deletion of queueless Trusty IPC device on the secure side. + * @buf is unmapped, and all open channels are closed. + * + * @dev: trusty device, initialized with trusty_dev_init + * @buf: physical address info of shared buffer + * @buf_size: size of @buf + */ +int trusty_dev_shutdown_ipc(struct trusty_dev *dev, + struct ns_mem_page_info *buf, uint32_t buf_size); + +#endif /* TRUSTY_TRUSTY_DEV_H_ */ diff --git a/include/trusty/trusty_ipc.h b/include/trusty/trusty_ipc.h new file mode 100644 index 00000000000..ce7cbd126aa --- /dev/null +++ b/include/trusty/trusty_ipc.h @@ -0,0 +1,258 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_TRUSTY_IPC_H_ +#define TRUSTY_TRUSTY_IPC_H_ + +#include + +/* + * handle_t is an opaque 32 bit value that is used to reference an + * Trusty IPC channel + */ +typedef uint32_t handle_t; + +#define INVALID_IPC_HANDLE 0 + +/* + * Error codes returned by Trusty IPC device function calls + */ +enum trusty_err { + TRUSTY_ERR_NONE = 0, + TRUSTY_ERR_GENERIC = -1, + TRUSTY_ERR_NOT_SUPPORTED = -2, + TRUSTY_ERR_NO_MEMORY = -3, + TRUSTY_ERR_INVALID_ARGS = -4, + TRUSTY_ERR_SECOS_ERR = -5, + TRUSTY_ERR_MSG_TOO_BIG = -6, + TRUSTY_ERR_NO_MSG = -7, + TRUSTY_ERR_CHANNEL_CLOSED = -8, + TRUSTY_ERR_SEND_BLOCKED = -9, +}; +/* + * Return codes for successful Trusty IPC events (failures return trusty_err) + */ +enum trusty_event_result { + TRUSTY_EVENT_HANDLED = 1, + TRUSTY_EVENT_NONE = 2 +}; + +/* + * Combination of these values are used for the event field + * of trusty_ipc_event structure. + */ +enum trusty_ipc_event_type { + IPC_HANDLE_POLL_NONE = 0x0, + IPC_HANDLE_POLL_READY = 0x1, + IPC_HANDLE_POLL_ERROR = 0x2, + IPC_HANDLE_POLL_HUP = 0x4, + IPC_HANDLE_POLL_MSG = 0x8, + IPC_HANDLE_POLL_SEND_UNBLOCKED = 0x10, +}; + +struct trusty_dev; +struct trusty_ipc_chan; + +/* + * Trusty IPC event + * + * @event: event type + * @handle: handle this event is related to + * @cookie: cookie associated with handle + */ +struct trusty_ipc_event { + uint32_t event; + uint32_t handle; + uint64_t cookie; +}; + +struct trusty_ipc_iovec { + void *base; + size_t len; +}; + +/* + * Trusty IPC device + * + * @buf_vaddr: virtual address of shared buffer associated with device + * @buf_size: size of shared buffer + * @buf_ns: physical address info of shared buffer + * @tdev: trusty device + */ +struct trusty_ipc_dev { + void *buf_vaddr; + size_t buf_size; + struct ns_mem_page_info buf_ns; + struct trusty_dev *tdev; +}; + +/* + * Trusty IPC event handlers. + */ +struct trusty_ipc_ops { + int (*on_raw_event)(struct trusty_ipc_chan *chan, + struct trusty_ipc_event *evt); + int (*on_connect_complete)(struct trusty_ipc_chan *chan); + int (*on_send_unblocked)(struct trusty_ipc_chan *chan); + int (*on_message)(struct trusty_ipc_chan *chan); + int (*on_disconnect)(struct trusty_ipc_chan *chan); +}; + +/* + * Trusty IPC channel. + * + * @ops_ctx: refers to additional data that may be used by trusty_ipc_ops + * @handle: identifier for channel + * @complete: completion status of last event on channel + * @dev: Trusty IPC device used by channel, initialized with + trusty_ipc_dev_create + * @ops: callbacks for Trusty events + */ +struct trusty_ipc_chan { + void *ops_ctx; + handle_t handle; + volatile int complete; + struct trusty_ipc_dev *dev; + struct trusty_ipc_ops *ops; +}; + +/* + * Creates new Trusty IPC device on @tdev. Allocates shared buffer, and calls + * trusty_dev_init_ipc to register with secure side. Returns a trusty_err. + * + * @ipc_dev: new Trusty IPC device to be initialized + * @tdev: associated Trusty device + * @shared_buf_size: size of shared buffer to be allocated + */ +int trusty_ipc_dev_create(struct trusty_ipc_dev **ipc_dev, + struct trusty_dev *tdev, + size_t shared_buf_size); +/* + * Shutdown @dev. Frees shared buffer, and calls trusty_dev_shutdown_ipc + * to shutdown on the secure side. + */ +void trusty_ipc_dev_shutdown(struct trusty_ipc_dev *dev); + +/* + * Calls into secure OS to initiate a new connection to a Trusty IPC service. + * Returns handle for the new channel, a trusty_err on error. + * + * @dev: Trusty IPC device initialized with trusty_ipc_dev_create + * @port: name of port to connect to on secure side + * @cookie: cookie associated with new channel. + */ +int trusty_ipc_dev_connect(struct trusty_ipc_dev *dev, const char *port, + uint64_t cookie); +/* + * Calls into secure OS to close connection to Trusty IPC service. + * Returns a trusty_err. + * + * @dev: Trusty IPC device + * @chan: handle for connection, opened with trusty_ipc_dev_connect + */ +int trusty_ipc_dev_close(struct trusty_ipc_dev *dev, handle_t chan); + +/* + * Calls into secure OS to receive pending event. Returns a trusty_err. + * + * @dev: Trusty IPC device + * @chan: handle for connection + * @event: pointer to output event struct + */ +int trusty_ipc_dev_get_event(struct trusty_ipc_dev *dev, handle_t chan, + struct trusty_ipc_event *event); +/* + * Calls into secure OS to send message to channel. Returns a trusty_err. + * + * @dev: Trusty IPC device + * @chan: handle for connection + * @iovs: contains messages to be sent + * @iovs_cnt: number of iovecs to be sent + */ +int trusty_ipc_dev_send(struct trusty_ipc_dev *dev, handle_t chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt); +/* + * Calls into secure OS to receive message on channel. Returns number of bytes + * received on success, trusty_err on failure. + * + * @dev: Trusty IPC device + * @chan: handle for connection + * @iovs: contains received messages + * @iovs_cnt: number of iovecs received + */ +int trusty_ipc_dev_recv(struct trusty_ipc_dev *dev, handle_t chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt); + +void trusty_ipc_dev_idle(struct trusty_ipc_dev *dev); + +/* + * Initializes @chan with default values and @dev. + */ +void trusty_ipc_chan_init(struct trusty_ipc_chan *chan, + struct trusty_ipc_dev *dev); +/* + * Calls trusty_ipc_dev_connect to get a handle for channel. + * Returns a trusty_err. + * + * @chan: channel to initialize with new handle + * @port: name of port to connect to on secure side + * @wait: flag to wait for connect to complete by polling for + * IPC_HANDLE_POLL_READY event + */ +int trusty_ipc_connect(struct trusty_ipc_chan *chan, const char *port, + bool wait); +/* + * Calls trusty_ipc_dev_close and invalidates @chan. Returns a trusty_err. + */ +int trusty_ipc_close(struct trusty_ipc_chan *chan); +/* + * Calls trusty_ipc_dev_get_event to poll @dev for events. Handles + * events by calling appropriate callbacks. Returns nonnegative on success. + */ +int trusty_ipc_poll_for_event(struct trusty_ipc_dev *dev); +/* + * Calls trusty_ipc_dev_send to send a message. Returns a trusty_err. + * + * @chan: handle for connection + * @iovs: contains messages to be sent + * @iovs_cnt: number of iovecs to be sent + * @wait: flag to wait for send to complete + */ +int trusty_ipc_send(struct trusty_ipc_chan *chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt, + bool wait); +/* + * Calls trusty_ipc_dev_recv to receive a message. Return number of bytes + * received on success, trusty_err on failure. + * + * @chan: handle for connection + * @iovs: contains received messages + * @iovs_cnt: number of iovecs received + * @wait: flag to wait for a message to receive + */ +int trusty_ipc_recv(struct trusty_ipc_chan *chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt, + bool wait); + +#endif /* TRUSTY_TRUSTY_IPC_H_ */ diff --git a/include/trusty/trusty_mem.h b/include/trusty/trusty_mem.h new file mode 100644 index 00000000000..c796baa03f4 --- /dev/null +++ b/include/trusty/trusty_mem.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2018 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_TRUSTY_MEM_H_ +#define TRUSTY_TRUSTY_MEM_H_ + +#include + +/* + * Encodes the memory attributes of @va into @inf + * + * @inf: ns_mem_page_info allocated by the caller + * @va: virtual addresses to retrieve attributes for + * + * Returns 0 on success and -1 on failure + */ + +int trusty_encode_page_info(struct ns_mem_page_info *inf, void *va); + +#endif /* TRUSTY_TRUSTY_MEM_H_ */ diff --git a/include/trusty/util.h b/include/trusty/util.h new file mode 100644 index 00000000000..72b960eacbc --- /dev/null +++ b/include/trusty/util.h @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_UTIL_H_ +#define TRUSTY_UTIL_H_ + +#include + +/* Returns the basename of |str|. This is defined as the last path + * component, assuming the normal POSIX separator '/'. If there are no + * separators, returns |str|. + */ +const char* trusty_basename(const char* str); + +#define TRUSTY_STRINGIFY(x) #x +#define TRUSTY_TO_STRING(x) TRUSTY_STRINGIFY(x) + +/* + * Aborts the program if @expr is false. + * + * This has no effect unless TIPC_ENABLE_DEBUG is defined. + */ +#ifdef TIPC_ENABLE_DEBUG +#define trusty_assert(expr) \ + do { \ + if (!(expr)) { \ + trusty_fatal("assert fail: " #expr "\n"); \ + } \ + } while(0) +#else +#define trusty_assert(expr) +#endif + +/* + * Prints debug message. + * + * This has no effect unless TIPC_ENABLE_DEBUG and LOCAL_LOG is defined. + */ +#ifdef TIPC_ENABLE_DEBUG +#define trusty_debug(message, ...) \ + do { \ + if (LOCAL_LOG) { \ + trusty_printf(trusty_basename(__FILE__)); \ + trusty_printf(":" TRUSTY_TO_STRING(__LINE__) ": DEBUG "); \ + trusty_printf(message, ##__VA_ARGS__); \ + } \ + } while(0) +#else +#define trusty_debug(message, ...) +#endif + +/* + * Prints info message. + */ +#define trusty_info(message, ...) \ + do { \ + trusty_printf(trusty_basename(__FILE__)); \ + trusty_printf(": INFO "); \ + trusty_printf(message, ##__VA_ARGS__); \ + } while(0) + +/* + * Prints error message. + */ +#define trusty_error(message, ...) \ + do { \ + trusty_printf(trusty_basename(__FILE__)); \ + trusty_printf(":" TRUSTY_TO_STRING(__LINE__) ": ERROR "); \ + trusty_printf(message, ##__VA_ARGS__); \ + } while(0) + +/* + * Prints message and calls trusty_abort. + */ +#define trusty_fatal(message, ...) \ + do { \ + trusty_printf(trusty_basename(__FILE__)); \ + trusty_printf(":" TRUSTY_TO_STRING(__LINE__) ": FATAL "); \ + trusty_printf(message, ##__VA_ARGS__); \ + trusty_abort(); \ + } while(0) + +#endif /* TRUSTY_UTIL_H_ */ diff --git a/include/usb.h b/include/usb.h index 57a7d8d0ea3..279bf5555e3 100644 --- a/include/usb.h +++ b/include/usb.h @@ -905,6 +905,15 @@ struct ehci_ctrl; */ int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp); +/** + * usb_remove_ehci_gadget() - Remove a gadget USB device + * + * TODO(sjg@chromium.org): Tidy this up when USB gadgets can use driver model + * + * This provides a way to tell a controller to remove a USB device + */ +int usb_remove_ehci_gadget(struct ehci_ctrl **ctlrp); + /** * usb_stor_reset() - Prepare to scan USB storage devices * diff --git a/include/usb/imx8_usb3_reg_def.h b/include/usb/imx8_usb3_reg_def.h new file mode 100644 index 00000000000..5d81cdc9034 --- /dev/null +++ b/include/usb/imx8_usb3_reg_def.h @@ -0,0 +1,457 @@ +/* + * Copyright 2017 NXP + * + * NXP i.MX8 USB HOST xHCI Controller (Cadence IP) Register Definition + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMX8_USB3_H_ +#define _IMX8_USB3_H_ + +#define REG32(m) (m) + +#define USB3_REGS_BASE 0x5B110000 +#define USB3_CTRL_BASE (USB3_REGS_BASE + 0x00000) +#define USB3_CORE_BASE (USB3_REGS_BASE + 0x10000) +#define USB3_PHY_BASE (USB3_REGS_BASE + 0x50000) +/* PHY registers */ +#define PHY_PMA_CMN_CTRL1 (USB3_PHY_BASE + 0xC800 * 4) +#define TB_ADDR_CMN_DIAG_HSCLK_SEL (USB3_PHY_BASE + 0x01e0 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR (USB3_PHY_BASE + 0x0084 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR (USB3_PHY_BASE + 0x0085 * 4) +#define TB_ADDR_CMN_PLL0_INTDIV (USB3_PHY_BASE + 0x0094 * 4) +#define TB_ADDR_CMN_PLL0_FRACDIV (USB3_PHY_BASE + 0x0095 * 4) +#define TB_ADDR_CMN_PLL0_HIGH_THR (USB3_PHY_BASE + 0x0096 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL1 (USB3_PHY_BASE + 0x0098 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL2 (USB3_PHY_BASE + 0x0099 * 4) +#define TB_ADDR_CMN_PLL0_DSM_DIAG (USB3_PHY_BASE + 0x0097 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_OVRD (USB3_PHY_BASE + 0x01c2 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD (USB3_PHY_BASE + 0x01c0 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD (USB3_PHY_BASE + 0x01c1 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE (USB3_PHY_BASE + 0x01C5 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE (USB3_PHY_BASE + 0x01C6 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG (USB3_PHY_BASE + 0x01C7 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE (USB3_PHY_BASE + 0x01c4 * 4) +#define TB_ADDR_CMN_PSM_CLK_CTRL (USB3_PHY_BASE + 0x0061 * 4) +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR (USB3_PHY_BASE + 0x40ea * 4) +#define TB_ADDR_XCVR_PSM_RCTRL (USB3_PHY_BASE + 0x4001 * 4) +#define TB_ADDR_TX_PSC_A0 (USB3_PHY_BASE + 0x4100 * 4) +#define TB_ADDR_TX_PSC_A1 (USB3_PHY_BASE + 0x4101 * 4) +#define TB_ADDR_TX_PSC_A2 (USB3_PHY_BASE + 0x4102 * 4) +#define TB_ADDR_TX_PSC_A3 (USB3_PHY_BASE + 0x4103 * 4) +#define TB_ADDR_TX_DIAG_ECTRL_OVRD (USB3_PHY_BASE + 0x41f5 * 4) +#define TB_ADDR_TX_PSC_CAL (USB3_PHY_BASE + 0x4106 * 4) +#define TB_ADDR_TX_PSC_RDY (USB3_PHY_BASE + 0x4107 * 4) +#define TB_ADDR_RX_PSC_A0 (USB3_PHY_BASE + 0x8000 * 4) +#define TB_ADDR_RX_PSC_A1 (USB3_PHY_BASE + 0x8001 * 4) +#define TB_ADDR_RX_PSC_A2 (USB3_PHY_BASE + 0x8002 * 4) +#define TB_ADDR_RX_PSC_A3 (USB3_PHY_BASE + 0x8003 * 4) +#define TB_ADDR_RX_PSC_CAL (USB3_PHY_BASE + 0x8006 * 4) +#define TB_ADDR_RX_PSC_RDY (USB3_PHY_BASE + 0x8007 * 4) +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 (USB3_PHY_BASE + 0x4058 * 4) +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY (USB3_PHY_BASE + 0x41e7 * 4) +#define TB_ADDR_RX_SLC_CU_ITER_TMR (USB3_PHY_BASE + 0x80e3 * 4) +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR (USB3_PHY_BASE + 0x8090 * 4) +#define TB_ADDR_RX_SAMP_DAC_CTRL (USB3_PHY_BASE + 0x8058 * 4) +#define TB_ADDR_RX_DIAG_SIGDET_TUNE (USB3_PHY_BASE + 0x81dc * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 (USB3_PHY_BASE + 0x81df * 4) +#define TB_ADDR_RX_DIAG_BS_TM (USB3_PHY_BASE + 0x81f5 * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL1 (USB3_PHY_BASE + 0x81d3 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 (USB3_PHY_BASE + 0x81c7 * 4) +#define TB_ADDR_RX_DIAG_ILL_E_TRIM0 (USB3_PHY_BASE + 0x81c2 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 (USB3_PHY_BASE + 0x81c1 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 (USB3_PHY_BASE + 0x81c9 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM3 (USB3_PHY_BASE + 0x81f8 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM4 (USB3_PHY_BASE + 0x81f9 * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE (USB3_PHY_BASE + 0x81dd * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL3 (USB3_PHY_BASE + 0x81d5 * 4) +#define TB_ADDR_RX_DIAG_SC2C_DELAY (USB3_PHY_BASE + 0x81e1 * 4) +#define TB_ADDR_RX_REE_VGA_GAIN_NODFE (USB3_PHY_BASE + 0x81bf * 4) +#define TB_ADDR_XCVR_PSM_CAL_TMR (USB3_PHY_BASE + 0x4002 * 4) +#define TB_ADDR_XCVR_PSM_A0BYP_TMR (USB3_PHY_BASE + 0x4004 * 4) +#define TB_ADDR_XCVR_PSM_A0IN_TMR (USB3_PHY_BASE + 0x4003 * 4) +#define TB_ADDR_XCVR_PSM_A1IN_TMR (USB3_PHY_BASE + 0x4005 * 4) +#define TB_ADDR_XCVR_PSM_A2IN_TMR (USB3_PHY_BASE + 0x4006 * 4) +#define TB_ADDR_XCVR_PSM_A3IN_TMR (USB3_PHY_BASE + 0x4007 * 4) +#define TB_ADDR_XCVR_PSM_A4IN_TMR (USB3_PHY_BASE + 0x4008 * 4) +#define TB_ADDR_XCVR_PSM_A5IN_TMR (USB3_PHY_BASE + 0x4009 * 4) +#define TB_ADDR_XCVR_PSM_A0OUT_TMR (USB3_PHY_BASE + 0x400a * 4) +#define TB_ADDR_XCVR_PSM_A1OUT_TMR (USB3_PHY_BASE + 0x400b * 4) +#define TB_ADDR_XCVR_PSM_A2OUT_TMR (USB3_PHY_BASE + 0x400c * 4) +#define TB_ADDR_XCVR_PSM_A3OUT_TMR (USB3_PHY_BASE + 0x400d * 4) +#define TB_ADDR_XCVR_PSM_A4OUT_TMR (USB3_PHY_BASE + 0x400e * 4) +#define TB_ADDR_XCVR_PSM_A5OUT_TMR (USB3_PHY_BASE + 0x400f * 4) +#define TB_ADDR_TX_RCVDET_EN_TMR (USB3_PHY_BASE + 0x4122 * 4) +#define TB_ADDR_TX_RCVDET_ST_TMR (USB3_PHY_BASE + 0x4123 * 4) +#define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR (USB3_PHY_BASE + 0x40f2 * 4) + + +/* Host registers */ +#define HCIVERSION_CAPLENGTH (USB3_CORE_BASE + 0x10000) +#define HCSPARAMS1 (USB3_CORE_BASE + 0x10004) +#define HCSPARAMS2 (USB3_CORE_BASE + 0x10008) +#define HCSPARAMS3 (USB3_CORE_BASE + 0x1000c) +#define HCCPARAMS (USB3_CORE_BASE + 0x10010) +#define DBOFF (USB3_CORE_BASE + 0x10014) +#define RTSOFF (USB3_CORE_BASE + 0x10018) +#define USBCMD (USB3_CORE_BASE + 0x10080) +#define USBSTS (USB3_CORE_BASE + 0x10084) +#define PAGESIZE (USB3_CORE_BASE + 0x10088) +#define DNCTRL (USB3_CORE_BASE + 0x10094) +#define CRCR_LO (USB3_CORE_BASE + 0x10098) +#define CRCR_HI (USB3_CORE_BASE + 0x1009c) +#define DCBAAP_LO (USB3_CORE_BASE + 0x100b0) +#define DCBAAP_HI (USB3_CORE_BASE + 0x100b4) +#define CONFIG (USB3_CORE_BASE + 0x100b8) +#define PORTSC1USB2 (USB3_CORE_BASE + 0x10480) +#define PORTPMSC1USB2 (USB3_CORE_BASE + 0x10484) +#define PORT1HLPMC (USB3_CORE_BASE + 0x1048c) +#define PORTSC1USB3 (USB3_CORE_BASE + 0x10490) +#define PORTPMSC1USB3 (USB3_CORE_BASE + 0x10494) +#define PORTLI1 (USB3_CORE_BASE + 0x10498) +#define MFINDEX (USB3_CORE_BASE + 0x12000) +#define IMAN0 (USB3_CORE_BASE + 0x12020) +#define IMOD0 (USB3_CORE_BASE + 0x12024) +#define ERSTSZ0 (USB3_CORE_BASE + 0x12028) +#define XHCI_RESERVED0 (USB3_CORE_BASE + 0x1202c) +#define ERSTBA0_LO (USB3_CORE_BASE + 0x12030) +#define ERSTBA0_HI (USB3_CORE_BASE + 0x12034) +#define ERDP0_LO (USB3_CORE_BASE + 0x12038) +#define ERDP0_HI (USB3_CORE_BASE + 0x1203c) +#define IMAN1 (USB3_CORE_BASE + 0x12040) +#define IMOD1 (USB3_CORE_BASE + 0x12044) +#define ERSTSZ1 (USB3_CORE_BASE + 0x12048) +#define XHCI_RESERVED1 (USB3_CORE_BASE + 0x1204c) +#define ERSTBA1_LO (USB3_CORE_BASE + 0x12050) +#define ERSTBA1_HI (USB3_CORE_BASE + 0x12054) +#define ERDP1_LO (USB3_CORE_BASE + 0x12058) +#define ERDP1_HI (USB3_CORE_BASE + 0x1205c) +#define IMAN2 (USB3_CORE_BASE + 0x12060) +#define IMOD2 (USB3_CORE_BASE + 0x12064) +#define ERSTSZ2 (USB3_CORE_BASE + 0x12068) +#define XHCI_RESERVED2 (USB3_CORE_BASE + 0x1206c) +#define ERSTBA2_LO (USB3_CORE_BASE + 0x12070) +#define ERSTBA2_HI (USB3_CORE_BASE + 0x12074) +#define ERDP2_LO (USB3_CORE_BASE + 0x12078) +#define ERDP2_HI (USB3_CORE_BASE + 0x1207c) +#define IMAN3 (USB3_CORE_BASE + 0x12080) +#define IMOD3 (USB3_CORE_BASE + 0x12084) +#define ERSTSZ3 (USB3_CORE_BASE + 0x12088) +#define XHCI_RESERVED3 (USB3_CORE_BASE + 0x1208c) +#define ERSTBA3_LO (USB3_CORE_BASE + 0x12090) +#define ERSTBA3_HI (USB3_CORE_BASE + 0x12094) +#define ERDP3_LO (USB3_CORE_BASE + 0x12098) +#define ERDP3_HI (USB3_CORE_BASE + 0x1209c) +#define IMAN4 (USB3_CORE_BASE + 0x120a0) +#define IMOD4 (USB3_CORE_BASE + 0x120a4) +#define ERSTSZ4 (USB3_CORE_BASE + 0x120a8) +#define XHCI_RESERVED4 (USB3_CORE_BASE + 0x120ac) +#define ERSTBA4_LO (USB3_CORE_BASE + 0x120b0) +#define ERSTBA4_HI (USB3_CORE_BASE + 0x120b4) +#define ERDP4_LO (USB3_CORE_BASE + 0x120b8) +#define ERDP4_HI (USB3_CORE_BASE + 0x120bc) +#define IMAN5 (USB3_CORE_BASE + 0x120c0) +#define IMOD5 (USB3_CORE_BASE + 0x120c4) +#define ERSTSZ5 (USB3_CORE_BASE + 0x120c8) +#define XHCI_RESERVED5 (USB3_CORE_BASE + 0x120cc) +#define ERSTBA5_LO (USB3_CORE_BASE + 0x120d0) +#define ERSTBA5_HI (USB3_CORE_BASE + 0x120d4) +#define ERDP5_LO (USB3_CORE_BASE + 0x120d8) +#define ERDP5_HI (USB3_CORE_BASE + 0x120dc) +#define IMAN6 (USB3_CORE_BASE + 0x120e0) +#define IMOD6 (USB3_CORE_BASE + 0x120e4) +#define ERSTSZ6 (USB3_CORE_BASE + 0x120e8) +#define XHCI_RESERVED6 (USB3_CORE_BASE + 0x120ec) +#define ERSTBA6_LO (USB3_CORE_BASE + 0x120f0) +#define ERSTBA6_HI (USB3_CORE_BASE + 0x120f4) +#define ERDP6_LO (USB3_CORE_BASE + 0x120f8) +#define ERDP6_HI (USB3_CORE_BASE + 0x120fc) +#define IMAN7 (USB3_CORE_BASE + 0x12100) +#define IMOD7 (USB3_CORE_BASE + 0x12104) +#define ERSTSZ7 (USB3_CORE_BASE + 0x12108) +#define XHCI_RESERVED7 (USB3_CORE_BASE + 0x1210c) +#define ERSTBA7_LO (USB3_CORE_BASE + 0x12110) +#define ERSTBA7_HI (USB3_CORE_BASE + 0x12114) +#define ERDP7_LO (USB3_CORE_BASE + 0x12118) +#define ERDP7_HI (USB3_CORE_BASE + 0x1211c) +#define DB0 (USB3_CORE_BASE + 0x13000) +#define DB1 (USB3_CORE_BASE + 0x13004) +#define DB2 (USB3_CORE_BASE + 0x13008) +#define DB3 (USB3_CORE_BASE + 0x1300c) +#define DB4 (USB3_CORE_BASE + 0x13010) +#define DB5 (USB3_CORE_BASE + 0x13014) +#define DB6 (USB3_CORE_BASE + 0x13018) +#define DB7 (USB3_CORE_BASE + 0x1301c) +#define DB8 (USB3_CORE_BASE + 0x13020) +#define DB9 (USB3_CORE_BASE + 0x13024) +#define DB10 (USB3_CORE_BASE + 0x13028) +#define DB11 (USB3_CORE_BASE + 0x1302c) +#define DB12 (USB3_CORE_BASE + 0x13030) +#define DB13 (USB3_CORE_BASE + 0x13034) +#define DB14 (USB3_CORE_BASE + 0x13038) +#define DB15 (USB3_CORE_BASE + 0x1303c) +#define DB16 (USB3_CORE_BASE + 0x13040) +#define DB17 (USB3_CORE_BASE + 0x13044) +#define DB18 (USB3_CORE_BASE + 0x13048) +#define DB19 (USB3_CORE_BASE + 0x1304c) +#define DB20 (USB3_CORE_BASE + 0x13050) +#define DB21 (USB3_CORE_BASE + 0x13054) +#define DB22 (USB3_CORE_BASE + 0x13058) +#define DB23 (USB3_CORE_BASE + 0x1305c) +#define DB24 (USB3_CORE_BASE + 0x13060) +#define DB25 (USB3_CORE_BASE + 0x13064) +#define DB26 (USB3_CORE_BASE + 0x13068) +#define DB27 (USB3_CORE_BASE + 0x1306c) +#define DB28 (USB3_CORE_BASE + 0x13070) +#define DB29 (USB3_CORE_BASE + 0x13074) +#define DB30 (USB3_CORE_BASE + 0x13078) +#define DB31 (USB3_CORE_BASE + 0x1307c) +#define DB32 (USB3_CORE_BASE + 0x13080) +#define XECP_PORT_CAP_REG (USB3_CORE_BASE + 0x18000) +#define XECP_PORT_1_REG (USB3_CORE_BASE + 0x18004) +#define XECP_CDNS_DEBUG_BUS_CAP (USB3_CORE_BASE + 0x18008) +#define XECP_CDNS_DEBUG_BUS_CTRL (USB3_CORE_BASE + 0x1800c) +#define XECP_CDNS_DEBUG_BUS_STATUS (USB3_CORE_BASE + 0x18010) +#define XECP_PM_CAP (USB3_CORE_BASE + 0x18014) +#define XECP_PM_PMCSR (USB3_CORE_BASE + 0x18018) +#define XECP_MSI_CAP (USB3_CORE_BASE + 0x1801c) +#define XECP_MSI_ADDR_L (USB3_CORE_BASE + 0x18020) +#define XECP_MSI_ADDR_H (USB3_CORE_BASE + 0x18024) +#define XECP_MSI_DATA (USB3_CORE_BASE + 0x18028) +#define XECP_AXI_CAP (USB3_CORE_BASE + 0x1802c) +#define XECP_AXI_CFG0 (USB3_CORE_BASE + 0x18030) +#define XECP_AXI_CTRL0 (USB3_CORE_BASE + 0x18034) +#define XECP_AXI_CTRL1 (USB3_CORE_BASE + 0x18038) +#define XECP_AXI_CTRL2 (USB3_CORE_BASE + 0x1803c) +#define XECP_SUPP_USB2_CAP0 (USB3_CORE_BASE + 0x18040) +#define XECP_SUPP_USB2_CAP1 (USB3_CORE_BASE + 0x18044) +#define XECP_SUPP_USB2_CAP2 (USB3_CORE_BASE + 0x18048) +#define XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE (USB3_CORE_BASE + 0x1804c) +#define XECP_PSI_FULL_SPEED (USB3_CORE_BASE + 0x18050) +#define XECP_PSI_LOW_SPEED (USB3_CORE_BASE + 0x18054) +#define XECP_PSI_HIGH_SPEED (USB3_CORE_BASE + 0x18058) +#define XECP_SUPP_USB3_CAP0 (USB3_CORE_BASE + 0x18060) +#define XECP_SUPP_USB3_CAP1 (USB3_CORE_BASE + 0x18064) +#define XECP_SUPP_USB3_CAP2 (USB3_CORE_BASE + 0x18068) +#define XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE (USB3_CORE_BASE + 0x1806c) +#define PSI_SUPER_SPEED (USB3_CORE_BASE + 0x18070) +#define XECP_CMDM_STS0 (USB3_CORE_BASE + 0x18080) +#define XECP_CMDM_RESERVED_1 (USB3_CORE_BASE + 0x18084) +#define XECP_CMDM_RESERVED_2 (USB3_CORE_BASE + 0x18088) +#define XECP_CMDM_RESERVED_3 (USB3_CORE_BASE + 0x1808c) +#define XECP_CMDM_RESERVED_4 (USB3_CORE_BASE + 0x18090) +#define XECP_CMDM_RESERVED_5 (USB3_CORE_BASE + 0x18094) +#define XECP_CMDM_CTRL_REG1 (USB3_CORE_BASE + 0x18098) +#define XECP_CMDM_CTRL_REG2 (USB3_CORE_BASE + 0x1809c) +#define XECP_CMDM_CTRL_REG3 (USB3_CORE_BASE + 0x180a0) +#define XECP_HOST_CTRL_CAP (USB3_CORE_BASE + 0x180b0) +#define XECP_HOST_CTRL_RSVD (USB3_CORE_BASE + 0x180b4) +#define XECP_HOST_CLR_MASK_REG (USB3_CORE_BASE + 0x180b8) +#define XECP_HOST_CLR_IN_EP_VALID_REG (USB3_CORE_BASE + 0x180bc) +#define XECP_HOST_CLR_PMASK_REG (USB3_CORE_BASE + 0x180c0) +#define XECP_HOST_CTRL_OCRD_REG (USB3_CORE_BASE + 0x180c4) +#define XECP_HOST_CTRL_TEST_BUS_LO (USB3_CORE_BASE + 0x180c8) +#define XECP_HOST_CTRL_TEST_BUS_HI (USB3_CORE_BASE + 0x180cc) +#define XECP_HOST_CTRL_TRM_REG1 (USB3_CORE_BASE + 0x180d0) +#define XECP_HOST_CTRL_SCH_REG1 (USB3_CORE_BASE + 0x180d4) +#define XECP_HOST_CTRL_ODMA_REG (USB3_CORE_BASE + 0x180d8) +#define XECP_HOST_CTRL_IDMA_REG (USB3_CORE_BASE + 0x180dc) +#define XECP_HOST_CTRL_PORT_CTRL (USB3_CORE_BASE + 0x180e0) +#define XECP_AUX_CTRL_REG (USB3_CORE_BASE + 0x18100) +#define XECP_HOST_BW_OV_SS_REG (USB3_CORE_BASE + 0x18104) +#define XECP_HOST_BW_OV_HS_REG (USB3_CORE_BASE + 0x18108) +#define XECP_HOST_BW_OV_FS_LS_REG (USB3_CORE_BASE + 0x1810c) +#define XECP_HOST_BW_OV_SYS_REG (USB3_CORE_BASE + 0x18110) +#define XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG (USB3_CORE_BASE + 0x18114) +#define XECP_UPORTS_PON_RST_REG (USB3_CORE_BASE + 0x18118) +#define XECP_HOST_CTRL_TRM_REG3 (USB3_CORE_BASE + 0x1811c) +#define XECP_AUX_CTRL_REG1 (USB3_CORE_BASE + 0x18120) +#define XECP_HOST_CTRL_WATERMARK_REG (USB3_CORE_BASE + 0x18128) +#define XECP_HOST_CTRL_PORT_LINK_REG (USB3_CORE_BASE + 0x1812c) +#define XECP_USB2_LINK_MGR_CTRL_REG1 (USB3_CORE_BASE + 0x18130) +#define XECP_USB2_LINK_MGR_CTRL_REG2 (USB3_CORE_BASE + 0x18134) +#define XECP_USB2_LINK_MGR_CTRL_REG3 (USB3_CORE_BASE + 0x18138) +#define XECP_USB2_LINK_MGR_CTRL_REG4 (USB3_CORE_BASE + 0x1813c) +#define XECP_HOST_CTRL_BW_MAX_REG (USB3_CORE_BASE + 0x18140) +#define XECP_FPGA_REVISION_REG (USB3_CORE_BASE + 0x18144) +#define XECP_HOST_INTF_CTRL_REG (USB3_CORE_BASE + 0x18148) +#define XECP_BW_OV_SS_BURST_REG (USB3_CORE_BASE + 0x1814c) +#define XECP_HOST_CTRL_TRM_REG2 (USB3_CORE_BASE + 0x18150) +#define XECP_HOST_CTRL_BW_MAX1_REG (USB3_CORE_BASE + 0x18168) +#define XECP_HOST_CTRL_BW_MAX2_REG (USB3_CORE_BASE + 0x1816c) +#define XECP_USB2_LINESTATE_REG (USB3_CORE_BASE + 0x18170) +#define XECP_HOST_PROTO_GAP_TIMER1_REG (USB3_CORE_BASE + 0x18174) +#define XECP_HOST_PROTO_GAP_TIMER2_REG (USB3_CORE_BASE + 0x18178) +#define XECP_HOST_PROTO_BTO_TIMER_REG (USB3_CORE_BASE + 0x1817c) +#define XECP_HOST_CTRL_PSCH_REG (USB3_CORE_BASE + 0x18180) +#define XECP_HOST_CTRL_PSCH1_REG (USB3_CORE_BASE + 0x18184) +#define XECP_HOST_CTRL_LTM_REG (USB3_CORE_BASE + 0x18190) +#define XECP_AUX_CTRL_REG2 (USB3_CORE_BASE + 0x18194) +#define XECP_AUX_CTRL_REG3 (USB3_CORE_BASE + 0x18198) +#define XECP_DEBUG_CTRL_REG (USB3_CORE_BASE + 0x1819c) +#define XECP_HOST_CTRL_SCH_REG2 (USB3_CORE_BASE + 0x181a0) +#define XECP_AUX_DEBUG_READ_ONLY (USB3_CORE_BASE + 0x181a4) +#define XECP_AUX_CTRL_PORTNUM_REG (USB3_CORE_BASE + 0x181a8) +#define XECP_AUX_CTRL_DEV_REMOVE_REG (USB3_CORE_BASE + 0x181ac) +#define XECP_HOST_CTRL_DEBUG_PORT_DESC (USB3_CORE_BASE + 0x181b0) +#define XECP_HOST_CTRL_DEBUG_PORT_TRM (USB3_CORE_BASE + 0x181b4) +#define XECP_HOST_CTRL_DEBUG_PORT_IDMA (USB3_CORE_BASE + 0x181b8) +#define XECP_HOST_CTRL_DEBUG_PORT_ODMA (USB3_CORE_BASE + 0x181bc) +#define XECP_HOST_CTRL_DEBUG_PORT_MISC (USB3_CORE_BASE + 0x181c0) +#define XECP_HOST_CTRL_TTE_REG1 (USB3_CORE_BASE + 0x181e0) +#define XECP_HOST_CTRL_LTM_REG1 (USB3_CORE_BASE + 0x181e4) +#define XECP_HOST_CTRL_LTM_REG2 (USB3_CORE_BASE + 0x181e8) +#define XECP_AUX_SCRATCHPAD_0 (USB3_CORE_BASE + 0x18200) +#define XECP_AUX_SCRATCHPAD_1 (USB3_CORE_BASE + 0x18204) +#define XECP_BATTERY_CHARGE_REG (USB3_CORE_BASE + 0x18210) +#define XECP_BATTERY_CHARGE_REG1 (USB3_CORE_BASE + 0x18214) +#define XECP_BATTERY_CHARGE_REG2 (USB3_CORE_BASE + 0x18218) +#define XECP_BATTERY_CHARGE_REG3 (USB3_CORE_BASE + 0x1821c) +#define XECP_HOST_CTRL_PORT_LINK_REG1 (USB3_CORE_BASE + 0x18220) +#define XECP_USBLEGSUP (USB3_CORE_BASE + 0x18370) +#define XECP_USBLEGCTLSTS (USB3_CORE_BASE + 0x18374) +#define XECP_DCID (USB3_CORE_BASE + 0x18380) +#define XECP_DCDB (USB3_CORE_BASE + 0x18384) +#define XECP_DCERSTSZ (USB3_CORE_BASE + 0x18388) +#define XECP_RSVD_0C (USB3_CORE_BASE + 0x1838c) +#define XECP_DCERSTBA_LOW (USB3_CORE_BASE + 0x18390) +#define XECP_DCERSTBA_HIGH (USB3_CORE_BASE + 0x18394) +#define XECP_DCERDP_LOW (USB3_CORE_BASE + 0x18398) +#define XECP_DCERDP_HIGH (USB3_CORE_BASE + 0x1839c) +#define XECP_DCCTRL (USB3_CORE_BASE + 0x183a0) +#define XECP_DCST (USB3_CORE_BASE + 0x183a4) +#define XECP_DCPORTSC (USB3_CORE_BASE + 0x183a8) +#define XECP_RSVD_2C (USB3_CORE_BASE + 0x183ac) +#define XECP_DCCP_LOW (USB3_CORE_BASE + 0x183b0) +#define XECP_DCCP_HIGH (USB3_CORE_BASE + 0x183b4) +#define XECP_DCDDI1 (USB3_CORE_BASE + 0x183b8) +#define XECP_DCDDI2 (USB3_CORE_BASE + 0x183bc) +#define XECP_USB3_TEST_PORT0_REG (USB3_CORE_BASE + 0x18800) + +/* OTG registers */ +#define OTGCMD (USB3_CORE_BASE + 0x0) +#define OTGSTS (USB3_CORE_BASE + 0x4) +#define OTGSTATE (USB3_CORE_BASE + 0x8) +#define OTGREFCLK (USB3_CORE_BASE + 0xc) +#define OTGIEN (USB3_CORE_BASE + 0x10) +#define OTGIVECT (USB3_CORE_BASE + 0x14) +#define OTGVERSION (USB3_CORE_BASE + 0x18) +#define OTGSIMULATE (USB3_CORE_BASE + 0x1c) +#define CLK_FREQ (USB3_CORE_BASE + 0x20) +#define OTGTMR (USB3_CORE_BASE + 0x24) +#define ADPBC_STS (USB3_CORE_BASE + 0xe0) +#define ADP_RAMP_TIME (USB3_CORE_BASE + 0xe4) +#define ADPBC_CTRL1 (USB3_CORE_BASE + 0xe8) +#define ADPBC_CTRL2 (USB3_CORE_BASE + 0xec) +#define SFR0 (USB3_CORE_BASE + 0xf0) +#define SFR1 (USB3_CORE_BASE + 0xf4) +#define SFR2 (USB3_CORE_BASE + 0xf8) +#define SFR3 (USB3_CORE_BASE + 0xfc) + +/* Device registers */ +#define usb_conf (USB3_CORE_BASE + 0x20000) +#define usb_sts (USB3_CORE_BASE + 0x20004) +#define usb_cmd (USB3_CORE_BASE + 0x20008) +#define usb_iptn (USB3_CORE_BASE + 0x2000c) +#define usb_lpm (USB3_CORE_BASE + 0x20010) +#define usb_ien (USB3_CORE_BASE + 0x20014) +#define usb_ists (USB3_CORE_BASE + 0x20018) +#define ep_sel (USB3_CORE_BASE + 0x2001c) +#define ep_traddr (USB3_CORE_BASE + 0x20020) +#define ep_cfg (USB3_CORE_BASE + 0x20024) +#define ep_cmd (USB3_CORE_BASE + 0x20028) +#define ep_sts (USB3_CORE_BASE + 0x2002c) +#define ep_sts_sid (USB3_CORE_BASE + 0x20030) +#define ep_sts_en (USB3_CORE_BASE + 0x20034) +#define drbl (USB3_CORE_BASE + 0x20038) +#define ep_ien (USB3_CORE_BASE + 0x2003c) +#define ep_ists (USB3_CORE_BASE + 0x20040) +#define usb_pwr (USB3_CORE_BASE + 0x20044) +#define usb_conf2 (USB3_CORE_BASE + 0x20048) +#define usb_cap1 (USB3_CORE_BASE + 0x2004c) +#define usb_cap2 (USB3_CORE_BASE + 0x20050) +#define usb_cap3 (USB3_CORE_BASE + 0x20054) +#define usb_cap4 (USB3_CORE_BASE + 0x20058) +#define usb_cap5 (USB3_CORE_BASE + 0x2005c) +#define usb_cpkt1 (USB3_CORE_BASE + 0x20060) +#define usb_cpkt2 (USB3_CORE_BASE + 0x20064) +#define usb_cpkt3 (USB3_CORE_BASE + 0x20068) +#define cfg_reg1 (USB3_CORE_BASE + 0x20100) +#define dbg_link1 (USB3_CORE_BASE + 0x20104) +#define dbg_link2 (USB3_CORE_BASE + 0x20108) +#define cfg_reg4 (USB3_CORE_BASE + 0x2010c) +#define cfg_reg5 (USB3_CORE_BASE + 0x20110) +#define cfg_reg6 (USB3_CORE_BASE + 0x20114) +#define cfg_reg7 (USB3_CORE_BASE + 0x20118) +#define cfg_reg8 (USB3_CORE_BASE + 0x2011c) +#define cfg_reg9 (USB3_CORE_BASE + 0x20120) +#define cfg_reg10 (USB3_CORE_BASE + 0x20124) +#define cfg_reg11 (USB3_CORE_BASE + 0x20128) +#define cfg_reg12 (USB3_CORE_BASE + 0x2012c) +#define cfg_reg13 (USB3_CORE_BASE + 0x20130) +#define cfg_reg14 (USB3_CORE_BASE + 0x20134) +#define cfg_reg15 (USB3_CORE_BASE + 0x20138) +#define cfg_reg16 (USB3_CORE_BASE + 0x2013c) +#define cfg_reg17 (USB3_CORE_BASE + 0x20140) +#define cfg_reg18 (USB3_CORE_BASE + 0x20144) +#define cfg_reg19 (USB3_CORE_BASE + 0x20148) +#define cfg_reg20 (USB3_CORE_BASE + 0x2014c) +#define cfg_reg21 (USB3_CORE_BASE + 0x20150) +#define cfg_reg22 (USB3_CORE_BASE + 0x20154) +#define cfg_reg23 (USB3_CORE_BASE + 0x20158) +#define cfg_reg24 (USB3_CORE_BASE + 0x2015c) +#define cfg_reg25 (USB3_CORE_BASE + 0x20160) +#define cfg_reg26 (USB3_CORE_BASE + 0x20164) +#define cfg_reg27 (USB3_CORE_BASE + 0x20168) +#define cfg_reg28 (USB3_CORE_BASE + 0x2016c) +#define cfg_reg29 (USB3_CORE_BASE + 0x20170) +#define cfg_reg30 (USB3_CORE_BASE + 0x20174) +#define cfg_reg31 (USB3_CORE_BASE + 0x20178) +#define cfg_reg32 (USB3_CORE_BASE + 0x2017c) +#define cfg_reg33 (USB3_CORE_BASE + 0x20180) +#define cfg_reg34 (USB3_CORE_BASE + 0x20184) +#define cfg_reg35 (USB3_CORE_BASE + 0x20188) +#define cfg_reg36 (USB3_CORE_BASE + 0x201ac) +#define cfg_reg37 (USB3_CORE_BASE + 0x201b0) +#define cfg_reg38 (USB3_CORE_BASE + 0x201b4) +#define cfg_reg39 (USB3_CORE_BASE + 0x201b8) +#define cfg_reg40 (USB3_CORE_BASE + 0x201bc) +#define cfg_reg41 (USB3_CORE_BASE + 0x201c0) +#define cfg_reg42 (USB3_CORE_BASE + 0x201c4) +#define cfg_reg43 (USB3_CORE_BASE + 0x201c8) +#define cfg_reg44 (USB3_CORE_BASE + 0x201cc) +#define cfg_reg45 (USB3_CORE_BASE + 0x201d0) +#define cfg_reg46 (USB3_CORE_BASE + 0x201d4) +#define cfg_reg47 (USB3_CORE_BASE + 0x201d8) +#define cfg_reg48 (USB3_CORE_BASE + 0x201dc) +#define cfg_reg49 (USB3_CORE_BASE + 0x201e0) +#define cfg_reg50 (USB3_CORE_BASE + 0x201e4) +#define cfg_reg51 (USB3_CORE_BASE + 0x201e8) +#define cfg_reg52 (USB3_CORE_BASE + 0x201ec) +#define cfg_reg53 (USB3_CORE_BASE + 0x201f0) +#define cfg_reg54 (USB3_CORE_BASE + 0x201f4) +#define cfg_reg55 (USB3_CORE_BASE + 0x201f8) +#define cfg_reg56 (USB3_CORE_BASE + 0x201fc) +#define cfg_reg57 (USB3_CORE_BASE + 0x20200) +#define cfg_reg58 (USB3_CORE_BASE + 0x20204) +#define cfg_reg59 (USB3_CORE_BASE + 0x20208) +#define cfg_reg60 (USB3_CORE_BASE + 0x2020c) +#define cfg_reg61 (USB3_CORE_BASE + 0x20210) +#define cfg_reg62 (USB3_CORE_BASE + 0x20214) + +/* None-core registers */ +#define USB3_CORE_CTRL1 (USB3_CTRL_BASE + 0x00) +#define USB3_CORE_CTRL2 (USB3_CTRL_BASE + 0x04) +#define USB3_INT_REG (USB3_CTRL_BASE + 0x08) +#define USB3_CORE_STATUS (USB3_CTRL_BASE + 0x0c) +#define XHCI_DEBUG_LINK_ST (USB3_CTRL_BASE + 0x10) +#define XHCI_DEBUG_BUS (USB3_CTRL_BASE + 0x14) +#define USB3_SSPHY_CTRL1 (USB3_CTRL_BASE + 0x40) +#define USB3_SSPHY_CTRL2 (USB3_CTRL_BASE + 0x44) +#define USB3_SSPHY_STATUS (USB3_CTRL_BASE + 0x4c) +#define USB2_PHY_CTRL1 (USB3_CTRL_BASE + 0x50) +#define USB2_PHY_CTRL2 (USB3_CTRL_BASE + 0x54) +#define USB2_PHY_STATUS (USB3_CTRL_BASE + 0x5c) + +#endif /* _IMX8_USB3_H_ */ diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h index 8229f62b97f..ffb72da9bb6 100644 --- a/include/usb_mass_storage.h +++ b/include/usb_mass_storage.h @@ -26,7 +26,7 @@ struct ums { struct blk_desc block_dev; }; -int fsg_init(struct ums *ums_devs, int count); +int fsg_init(struct ums *ums_devs, int count, unsigned int controller_idx); void fsg_cleanup(void); int fsg_main_thread(void *); int fsg_add(struct usb_configuration *c); diff --git a/include/xen.h b/include/xen.h new file mode 100644 index 00000000000..b922451364f --- /dev/null +++ b/include/xen.h @@ -0,0 +1,412 @@ +/****************************************************************************** + * xen.h + * + * Guest OS interface to Xen. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Copyright (c) 2004, K A Fraser + */ + +#ifndef __XEN_PUBLIC_XEN_H__ +#define __XEN_PUBLIC_XEN_H__ + +//#include + +/* + * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS). + */ + +/* + * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5. + * EAX = return value + * (argument registers may be clobbered on return) + * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6. + * RAX = return value + * (argument registers not clobbered on return; RCX, R11 are) + */ +#define __HYPERVISOR_set_trap_table 0 +#define __HYPERVISOR_mmu_update 1 +#define __HYPERVISOR_set_gdt 2 +#define __HYPERVISOR_stack_switch 3 +#define __HYPERVISOR_set_callbacks 4 +#define __HYPERVISOR_fpu_taskswitch 5 +#define __HYPERVISOR_sched_op_compat 6 +#define __HYPERVISOR_platform_op 7 +#define __HYPERVISOR_set_debugreg 8 +#define __HYPERVISOR_get_debugreg 9 +#define __HYPERVISOR_update_descriptor 10 +#define __HYPERVISOR_memory_op 12 +#define __HYPERVISOR_multicall 13 +#define __HYPERVISOR_update_va_mapping 14 +#define __HYPERVISOR_set_timer_op 15 +#define __HYPERVISOR_event_channel_op_compat 16 +#define __HYPERVISOR_xen_version 17 +#define __HYPERVISOR_console_io 18 +#define __HYPERVISOR_physdev_op_compat 19 +#define __HYPERVISOR_grant_table_op 20 +#define __HYPERVISOR_vm_assist 21 +#define __HYPERVISOR_update_va_mapping_otherdomain 22 +#define __HYPERVISOR_iret 23 /* x86 only */ +#define __HYPERVISOR_vcpu_op 24 +#define __HYPERVISOR_set_segment_base 25 /* x86/64 only */ +#define __HYPERVISOR_mmuext_op 26 +#define __HYPERVISOR_xsm_op 27 +#define __HYPERVISOR_nmi_op 28 +#define __HYPERVISOR_sched_op 29 +#define __HYPERVISOR_callback_op 30 +#define __HYPERVISOR_xenoprof_op 31 +#define __HYPERVISOR_event_channel_op 32 +#define __HYPERVISOR_physdev_op 33 +#define __HYPERVISOR_hvm_op 34 +#define __HYPERVISOR_sysctl 35 +#define __HYPERVISOR_domctl 36 +#define __HYPERVISOR_kexec_op 37 +#define __HYPERVISOR_tmem_op 38 +#define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */ +#define __HYPERVISOR_xenpmu_op 40 + +/* Architecture-specific hypercall definitions. */ +#define __HYPERVISOR_arch_0 48 +#define __HYPERVISOR_arch_1 49 +#define __HYPERVISOR_arch_2 50 +#define __HYPERVISOR_arch_3 51 +#define __HYPERVISOR_arch_4 52 +#define __HYPERVISOR_arch_5 53 +#define __HYPERVISOR_arch_6 54 +#define __HYPERVISOR_arch_7 55 + +/* + * VIRTUAL INTERRUPTS + * + * Virtual interrupts that a guest OS may receive from Xen. + * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a + * global VIRQ. The former can be bound once per VCPU and cannot be re-bound. + * The latter can be allocated only once per guest: they must initially be + * allocated to VCPU0 but can subsequently be re-bound. + */ +#define VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */ +#define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */ +#define VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */ +#define VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */ +#define VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */ +#define VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */ +#define VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */ +#define VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */ +#define VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */ +#define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occured */ +#define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient */ +#define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */ +#define VIRQ_XENPMU 13 /* PMC interrupt */ + +/* Architecture-specific VIRQ definitions. */ +#define VIRQ_ARCH_0 16 +#define VIRQ_ARCH_1 17 +#define VIRQ_ARCH_2 18 +#define VIRQ_ARCH_3 19 +#define VIRQ_ARCH_4 20 +#define VIRQ_ARCH_5 21 +#define VIRQ_ARCH_6 22 +#define VIRQ_ARCH_7 23 + +#define NR_VIRQS 24 + +/* + * enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[], + * unsigned count, unsigned *done_out, + * unsigned foreigndom) + * @reqs is an array of mmu_update_t structures ((ptr, val) pairs). + * @count is the length of the above array. + * @pdone is an output parameter indicating number of completed operations + * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this + * hypercall invocation. Can be DOMID_SELF. + * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced + * in this hypercall invocation. The value of this field + * (x) encodes the PFD as follows: + * x == 0 => PFD == DOMID_SELF + * x != 0 => PFD == x - 1 + * + * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command. + * ------------- + * ptr[1:0] == MMU_NORMAL_PT_UPDATE: + * Updates an entry in a page table belonging to PFD. If updating an L1 table, + * and the new table entry is valid/present, the mapped frame must belong to + * FD. If attempting to map an I/O page then the caller assumes the privilege + * of the FD. + * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller. + * FD == DOMID_XEN: Map restricted areas of Xen's heap space. + * ptr[:2] -- Machine address of the page-table entry to modify. + * val -- Value to write. + * + * There also certain implicit requirements when using this hypercall. The + * pages that make up a pagetable must be mapped read-only in the guest. + * This prevents uncontrolled guest updates to the pagetable. Xen strictly + * enforces this, and will disallow any pagetable update which will end up + * mapping pagetable page RW, and will disallow using any writable page as a + * pagetable. In practice it means that when constructing a page table for a + * process, thread, etc, we MUST be very dilligient in following these rules: + * 1). Start with top-level page (PGD or in Xen language: L4). Fill out + * the entries. + * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD + * or L2). + * 3). Start filling out the PTE table (L1) with the PTE entries. Once + * done, make sure to set each of those entries to RO (so writeable bit + * is unset). Once that has been completed, set the PMD (L2) for this + * PTE table as RO. + * 4). When completed with all of the PMD (L2) entries, and all of them have + * been set to RO, make sure to set RO the PUD (L3). Do the same + * operation on PGD (L4) pagetable entries that have a PUD (L3) entry. + * 5). Now before you can use those pages (so setting the cr3), you MUST also + * pin them so that the hypervisor can verify the entries. This is done + * via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame + * number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op( + * MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be + * issued. + * For 32-bit guests, the L4 is not used (as there is less pagetables), so + * instead use L3. + * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE + * hypercall. Also if so desired the OS can also try to write to the PTE + * and be trapped by the hypervisor (as the PTE entry is RO). + * + * To deallocate the pages, the operations are the reverse of the steps + * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the + * pagetable MUST not be in use (meaning that the cr3 is not set to it). + * + * ptr[1:0] == MMU_MACHPHYS_UPDATE: + * Updates an entry in the machine->pseudo-physical mapping table. + * ptr[:2] -- Machine address within the frame whose mapping to modify. + * The frame must belong to the FD, if one is specified. + * val -- Value to write into the mapping entry. + * + * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD: + * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed + * with those in @val. + * + * @val is usually the machine frame number along with some attributes. + * The attributes by default follow the architecture defined bits. Meaning that + * if this is a X86_64 machine and four page table layout is used, the layout + * of val is: + * - 63 if set means No execute (NX) + * - 46-13 the machine frame number + * - 12 available for guest + * - 11 available for guest + * - 10 available for guest + * - 9 available for guest + * - 8 global + * - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages) + * - 6 dirty + * - 5 accessed + * - 4 page cached disabled + * - 3 page write through + * - 2 userspace accessible + * - 1 writeable + * - 0 present + * + * The one bits that does not fit with the default layout is the PAGE_PSE + * also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the + * HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB + * (or 2MB) instead of using the PAGE_PSE bit. + * + * The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen + * using it as the Page Attribute Table (PAT) bit - for details on it please + * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of + * pages instead of using MTRRs. + * + * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits): + * PAT4 PAT0 + * +-----+-----+----+----+----+-----+----+----+ + * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux + * +-----+-----+----+----+----+-----+----+----+ + * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) + * +-----+-----+----+----+----+-----+----+----+ + * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen + * +-----+-----+----+----+----+-----+----+----+ + * + * The lookup of this index table translates to looking up + * Bit 7, Bit 4, and Bit 3 of val entry: + * + * PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3). + * + * If all bits are off, then we are using PAT0. If bit 3 turned on, + * then we are using PAT1, if bit 3 and bit 4, then PAT2.. + * + * As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means + * that if a guest that follows Linux's PAT setup and would like to set Write + * Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is + * set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the + * caching as: + * + * WB = none (so PAT0) + * WC = PWT (bit 3 on) + * UC = PWT | PCD (bit 3 and 4 are on). + * + * To make it work with Xen, it needs to translate the WC bit as so: + * + * PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3 + * + * And to translate back it would: + * + * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7. + */ +#define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ +#define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ +#define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */ + +/* + * MMU EXTENDED OPERATIONS + * + * enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[], + * unsigned int count, + * unsigned int *pdone, + * unsigned int foreigndom) + */ +/* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures. + * A foreigndom (FD) can be specified (or DOMID_SELF for none). + * Where the FD has some effect, it is described below. + * + * cmd: MMUEXT_(UN)PIN_*_TABLE + * mfn: Machine frame number to be (un)pinned as a p.t. page. + * The frame must belong to the FD, if one is specified. + * + * cmd: MMUEXT_NEW_BASEPTR + * mfn: Machine frame number of new page-table base to install in MMU. + * + * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only] + * mfn: Machine frame number of new page-table base to install in MMU + * when in user space. + * + * cmd: MMUEXT_TLB_FLUSH_LOCAL + * No additional arguments. Flushes local TLB. + * + * cmd: MMUEXT_INVLPG_LOCAL + * linear_addr: Linear address to be flushed from the local TLB. + * + * cmd: MMUEXT_TLB_FLUSH_MULTI + * vcpumask: Pointer to bitmap of VCPUs to be flushed. + * + * cmd: MMUEXT_INVLPG_MULTI + * linear_addr: Linear address to be flushed. + * vcpumask: Pointer to bitmap of VCPUs to be flushed. + * + * cmd: MMUEXT_TLB_FLUSH_ALL + * No additional arguments. Flushes all VCPUs' TLBs. + * + * cmd: MMUEXT_INVLPG_ALL + * linear_addr: Linear address to be flushed from all VCPUs' TLBs. + * + * cmd: MMUEXT_FLUSH_CACHE + * No additional arguments. Writes back and flushes cache contents. + * + * cmd: MMUEXT_FLUSH_CACHE_GLOBAL + * No additional arguments. Writes back and flushes cache contents + * on all CPUs in the system. + * + * cmd: MMUEXT_SET_LDT + * linear_addr: Linear address of LDT base (NB. must be page-aligned). + * nr_ents: Number of entries in LDT. + * + * cmd: MMUEXT_CLEAR_PAGE + * mfn: Machine frame number to be cleared. + * + * cmd: MMUEXT_COPY_PAGE + * mfn: Machine frame number of the destination page. + * src_mfn: Machine frame number of the source page. + * + * cmd: MMUEXT_[UN]MARK_SUPER + * mfn: Machine frame number of head of superpage to be [un]marked. + */ +#define MMUEXT_PIN_L1_TABLE 0 +#define MMUEXT_PIN_L2_TABLE 1 +#define MMUEXT_PIN_L3_TABLE 2 +#define MMUEXT_PIN_L4_TABLE 3 +#define MMUEXT_UNPIN_TABLE 4 +#define MMUEXT_NEW_BASEPTR 5 +#define MMUEXT_TLB_FLUSH_LOCAL 6 +#define MMUEXT_INVLPG_LOCAL 7 +#define MMUEXT_TLB_FLUSH_MULTI 8 +#define MMUEXT_INVLPG_MULTI 9 +#define MMUEXT_TLB_FLUSH_ALL 10 +#define MMUEXT_INVLPG_ALL 11 +#define MMUEXT_FLUSH_CACHE 12 +#define MMUEXT_SET_LDT 13 +#define MMUEXT_NEW_USER_BASEPTR 15 +#define MMUEXT_CLEAR_PAGE 16 +#define MMUEXT_COPY_PAGE 17 +#define MMUEXT_FLUSH_CACHE_GLOBAL 18 +#define MMUEXT_MARK_SUPER 19 +#define MMUEXT_UNMARK_SUPER 20 + + +/* These are passed as 'flags' to update_va_mapping. They can be ORed. */ +/* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */ +/* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */ +#define UVMF_NONE (0UL<<0) /* No flushing at all. */ +#define UVMF_TLB_FLUSH (1UL<<0) /* Flush entire TLB(s). */ +#define UVMF_INVLPG (2UL<<0) /* Flush only one entry. */ +#define UVMF_FLUSHTYPE_MASK (3UL<<0) +#define UVMF_MULTI (0UL<<2) /* Flush subset of TLBs. */ +#define UVMF_LOCAL (0UL<<2) /* Flush local TLB. */ +#define UVMF_ALL (1UL<<2) /* Flush all TLBs. */ + +/* + * Commands to HYPERVISOR_console_io(). + */ +#define CONSOLEIO_write 0 +#define CONSOLEIO_read 1 + +/* + * Commands to HYPERVISOR_vm_assist(). + */ +#define VMASST_CMD_enable 0 +#define VMASST_CMD_disable 1 + +/* x86/32 guests: simulate full 4GB segment limits. */ +#define VMASST_TYPE_4gb_segments 0 + +/* x86/32 guests: trap (vector 15) whenever above vmassist is used. */ +#define VMASST_TYPE_4gb_segments_notify 1 + +/* + * x86 guests: support writes to bottom-level PTEs. + * NB1. Page-directory entries cannot be written. + * NB2. Guest must continue to remove all writable mappings of PTEs. + */ +#define VMASST_TYPE_writable_pagetables 2 + +/* x86/PAE guests: support PDPTs above 4GB. */ +#define VMASST_TYPE_pae_extended_cr3 3 + +/* + * x86 guests: Sane behaviour for virtual iopl + * - virtual iopl updated from do_iret() hypercalls. + * - virtual iopl reported in bounce frames. + * - guest kernels assumed to be level 0 for the purpose of iopl checks. + */ +#define VMASST_TYPE_architectural_iopl 4 + +/* + * All guests: activate update indicator in vcpu_runstate_info + * Enable setting the XEN_RUNSTATE_UPDATE flag in guest memory mapped + * vcpu_runstate_info during updates of the runstate information. + */ +#define VMASST_TYPE_runstate_update_flag 5 + +#define MAX_VMASST_TYPE 5 + +#endif /* __XEN_PUBLIC_XEN_H__ */ diff --git a/include/xen/event_channel.h b/include/xen/event_channel.h new file mode 100644 index 00000000000..44c549dd6b8 --- /dev/null +++ b/include/xen/event_channel.h @@ -0,0 +1,385 @@ +/****************************************************************************** + * event_channel.h + * + * Event channels between domains. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Copyright (c) 2003-2004, K A Fraser. + */ + +#ifndef __XEN_PUBLIC_EVENT_CHANNEL_H__ +#define __XEN_PUBLIC_EVENT_CHANNEL_H__ + +#include "xen.h" + +/* + * `incontents 150 evtchn Event Channels + * + * Event channels are the basic primitive provided by Xen for event + * notifications. An event is the Xen equivalent of a hardware + * interrupt. They essentially store one bit of information, the event + * of interest is signalled by transitioning this bit from 0 to 1. + * + * Notifications are received by a guest via an upcall from Xen, + * indicating when an event arrives (setting the bit). Further + * notifications are masked until the bit is cleared again (therefore, + * guests must check the value of the bit after re-enabling event + * delivery to ensure no missed notifications). + * + * Event notifications can be masked by setting a flag; this is + * equivalent to disabling interrupts and can be used to ensure + * atomicity of certain operations in the guest kernel. + * + * Event channels are represented by the evtchn_* fields in + * struct shared_info and struct vcpu_info. + */ + +/* + * ` enum neg_errnoval + * ` HYPERVISOR_event_channel_op(enum event_channel_op cmd, void *args) + * ` + * @cmd == EVTCHNOP_* (event-channel operation). + * @args == struct evtchn_* Operation-specific extra arguments (NULL if none). + */ + +/* ` enum event_channel_op { // EVTCHNOP_* => struct evtchn_* */ +#define EVTCHNOP_bind_interdomain 0 +#define EVTCHNOP_bind_virq 1 +#define EVTCHNOP_bind_pirq 2 +#define EVTCHNOP_close 3 +#define EVTCHNOP_send 4 +#define EVTCHNOP_status 5 +#define EVTCHNOP_alloc_unbound 6 +#define EVTCHNOP_bind_ipi 7 +#define EVTCHNOP_bind_vcpu 8 +#define EVTCHNOP_unmask 9 +#define EVTCHNOP_reset 10 +#define EVTCHNOP_init_control 11 +#define EVTCHNOP_expand_array 12 +#define EVTCHNOP_set_priority 13 +/* ` } */ + +typedef uint32_t evtchn_port_t; +DEFINE_XEN_GUEST_HANDLE(evtchn_port_t); + +/* + * EVTCHNOP_alloc_unbound: Allocate a port in domain and mark as + * accepting interdomain bindings from domain . A fresh port + * is allocated in and returned as . + * NOTES: + * 1. If the caller is unprivileged then must be DOMID_SELF. + * 2. may be DOMID_SELF, allowing loopback connections. + */ +struct evtchn_alloc_unbound { + /* IN parameters */ + domid_t dom, remote_dom; + /* OUT parameters */ + evtchn_port_t port; +}; +typedef struct evtchn_alloc_unbound evtchn_alloc_unbound_t; + +/* + * EVTCHNOP_bind_interdomain: Construct an interdomain event channel between + * the calling domain and . must identify + * a port that is unbound and marked as accepting bindings from the calling + * domain. A fresh port is allocated in the calling domain and returned as + * . + * + * In case the peer domain has already tried to set our event channel + * pending, before it was bound, EVTCHNOP_bind_interdomain always sets + * the local event channel pending. + * + * The usual pattern of use, in the guest's upcall (or subsequent + * handler) is as follows: (Re-enable the event channel for subsequent + * signalling and then) check for the existence of whatever condition + * is being waited for by other means, and take whatever action is + * needed (if any). + * + * NOTES: + * 1. may be DOMID_SELF, allowing loopback connections. + */ +struct evtchn_bind_interdomain { + /* IN parameters. */ + domid_t remote_dom; + evtchn_port_t remote_port; + /* OUT parameters. */ + evtchn_port_t local_port; +}; +typedef struct evtchn_bind_interdomain evtchn_bind_interdomain_t; + +/* + * EVTCHNOP_bind_virq: Bind a local event channel to VIRQ on specified + * vcpu. + * NOTES: + * 1. Virtual IRQs are classified as per-vcpu or global. See the VIRQ list + * in xen.h for the classification of each VIRQ. + * 2. Global VIRQs must be allocated on VCPU0 but can subsequently be + * re-bound via EVTCHNOP_bind_vcpu. + * 3. Per-vcpu VIRQs may be bound to at most one event channel per vcpu. + * The allocated event channel is bound to the specified vcpu and the + * binding cannot be changed. + */ +struct evtchn_bind_virq { + /* IN parameters. */ + uint32_t virq; /* enum virq */ + uint32_t vcpu; + /* OUT parameters. */ + evtchn_port_t port; +}; +typedef struct evtchn_bind_virq evtchn_bind_virq_t; + +/* + * EVTCHNOP_bind_pirq: Bind a local event channel to a real IRQ (PIRQ ). + * NOTES: + * 1. A physical IRQ may be bound to at most one event channel per domain. + * 2. Only a sufficiently-privileged domain may bind to a physical IRQ. + */ +struct evtchn_bind_pirq { + /* IN parameters. */ + uint32_t pirq; +#define BIND_PIRQ__WILL_SHARE 1 + uint32_t flags; /* BIND_PIRQ__* */ + /* OUT parameters. */ + evtchn_port_t port; +}; +typedef struct evtchn_bind_pirq evtchn_bind_pirq_t; + +/* + * EVTCHNOP_bind_ipi: Bind a local event channel to receive events. + * NOTES: + * 1. The allocated event channel is bound to the specified vcpu. The binding + * may not be changed. + */ +struct evtchn_bind_ipi { + uint32_t vcpu; + /* OUT parameters. */ + evtchn_port_t port; +}; +typedef struct evtchn_bind_ipi evtchn_bind_ipi_t; + +/* + * EVTCHNOP_close: Close a local event channel . If the channel is + * interdomain then the remote end is placed in the unbound state + * (EVTCHNSTAT_unbound), awaiting a new connection. + */ +struct evtchn_close { + /* IN parameters. */ + evtchn_port_t port; +}; +typedef struct evtchn_close evtchn_close_t; + +/* + * EVTCHNOP_send: Send an event to the remote end of the channel whose local + * endpoint is . + */ +struct evtchn_send { + /* IN parameters. */ + evtchn_port_t port; +}; +typedef struct evtchn_send evtchn_send_t; + +/* + * EVTCHNOP_status: Get the current status of the communication channel which + * has an endpoint at . + * NOTES: + * 1. may be specified as DOMID_SELF. + * 2. Only a sufficiently-privileged domain may obtain the status of an event + * channel for which is not DOMID_SELF. + */ +struct evtchn_status { + /* IN parameters */ + domid_t dom; + evtchn_port_t port; + /* OUT parameters */ +#define EVTCHNSTAT_closed 0 /* Channel is not in use. */ +#define EVTCHNSTAT_unbound 1 /* Channel is waiting interdom connection.*/ +#define EVTCHNSTAT_interdomain 2 /* Channel is connected to remote domain. */ +#define EVTCHNSTAT_pirq 3 /* Channel is bound to a phys IRQ line. */ +#define EVTCHNSTAT_virq 4 /* Channel is bound to a virtual IRQ line */ +#define EVTCHNSTAT_ipi 5 /* Channel is bound to a virtual IPI line */ + uint32_t status; + uint32_t vcpu; /* VCPU to which this channel is bound. */ + union { + struct { + domid_t dom; + } unbound; /* EVTCHNSTAT_unbound */ + struct { + domid_t dom; + evtchn_port_t port; + } interdomain; /* EVTCHNSTAT_interdomain */ + uint32_t pirq; /* EVTCHNSTAT_pirq */ + uint32_t virq; /* EVTCHNSTAT_virq */ + } u; +}; +typedef struct evtchn_status evtchn_status_t; + +/* + * EVTCHNOP_bind_vcpu: Specify which vcpu a channel should notify when an + * event is pending. + * NOTES: + * 1. IPI-bound channels always notify the vcpu specified at bind time. + * This binding cannot be changed. + * 2. Per-VCPU VIRQ channels always notify the vcpu specified at bind time. + * This binding cannot be changed. + * 3. All other channels notify vcpu0 by default. This default is set when + * the channel is allocated (a port that is freed and subsequently reused + * has its binding reset to vcpu0). + */ +struct evtchn_bind_vcpu { + /* IN parameters. */ + evtchn_port_t port; + uint32_t vcpu; +}; +typedef struct evtchn_bind_vcpu evtchn_bind_vcpu_t; + +/* + * EVTCHNOP_unmask: Unmask the specified local event-channel port and deliver + * a notification to the appropriate VCPU if an event is pending. + */ +struct evtchn_unmask { + /* IN parameters. */ + evtchn_port_t port; +}; +typedef struct evtchn_unmask evtchn_unmask_t; + +/* + * EVTCHNOP_reset: Close all event channels associated with specified domain. + * NOTES: + * 1. may be specified as DOMID_SELF. + * 2. Only a sufficiently-privileged domain may specify other than DOMID_SELF. + * 3. Destroys all control blocks and event array, resets event channel + * operations to 2-level ABI if called with == DOMID_SELF and FIFO + * ABI was used. Guests should not bind events during EVTCHNOP_reset call + * as these events are likely to be lost. + */ +struct evtchn_reset { + /* IN parameters. */ + domid_t dom; +}; +typedef struct evtchn_reset evtchn_reset_t; + +/* + * EVTCHNOP_init_control: initialize the control block for the FIFO ABI. + * + * Note: any events that are currently pending will not be resent and + * will be lost. Guests should call this before binding any event to + * avoid losing any events. + */ +struct evtchn_init_control { + /* IN parameters. */ + uint64_t control_gfn; + uint32_t offset; + uint32_t vcpu; + /* OUT parameters. */ + uint8_t link_bits; + uint8_t _pad[7]; +}; +typedef struct evtchn_init_control evtchn_init_control_t; + +/* + * EVTCHNOP_expand_array: add an additional page to the event array. + */ +struct evtchn_expand_array { + /* IN parameters. */ + uint64_t array_gfn; +}; +typedef struct evtchn_expand_array evtchn_expand_array_t; + +/* + * EVTCHNOP_set_priority: set the priority for an event channel. + */ +struct evtchn_set_priority { + /* IN parameters. */ + uint32_t port; + uint32_t priority; +}; +typedef struct evtchn_set_priority evtchn_set_priority_t; + +/* + * ` enum neg_errnoval + * ` HYPERVISOR_event_channel_op_compat(struct evtchn_op *op) + * ` + * Superceded by new event_channel_op() hypercall since 0x00030202. + */ +struct evtchn_op { + uint32_t cmd; /* enum event_channel_op */ + union { + struct evtchn_alloc_unbound alloc_unbound; + struct evtchn_bind_interdomain bind_interdomain; + struct evtchn_bind_virq bind_virq; + struct evtchn_bind_pirq bind_pirq; + struct evtchn_bind_ipi bind_ipi; + struct evtchn_close close; + struct evtchn_send send; + struct evtchn_status status; + struct evtchn_bind_vcpu bind_vcpu; + struct evtchn_unmask unmask; + } u; +}; +typedef struct evtchn_op evtchn_op_t; +DEFINE_XEN_GUEST_HANDLE(evtchn_op_t); + +/* + * 2-level ABI + */ + +#define EVTCHN_2L_NR_CHANNELS (sizeof(xen_ulong_t) * sizeof(xen_ulong_t) * 64) + +/* + * FIFO ABI + */ + +/* Events may have priorities from 0 (highest) to 15 (lowest). */ +#define EVTCHN_FIFO_PRIORITY_MAX 0 +#define EVTCHN_FIFO_PRIORITY_DEFAULT 7 +#define EVTCHN_FIFO_PRIORITY_MIN 15 + +#define EVTCHN_FIFO_MAX_QUEUES (EVTCHN_FIFO_PRIORITY_MIN + 1) + +typedef uint32_t event_word_t; + +#define EVTCHN_FIFO_PENDING 31 +#define EVTCHN_FIFO_MASKED 30 +#define EVTCHN_FIFO_LINKED 29 +#define EVTCHN_FIFO_BUSY 28 + +#define EVTCHN_FIFO_LINK_BITS 17 +#define EVTCHN_FIFO_LINK_MASK ((1 << EVTCHN_FIFO_LINK_BITS) - 1) + +#define EVTCHN_FIFO_NR_CHANNELS (1 << EVTCHN_FIFO_LINK_BITS) + +struct evtchn_fifo_control_block { + uint32_t ready; + uint32_t _rsvd; + uint32_t head[EVTCHN_FIFO_MAX_QUEUES]; +}; +typedef struct evtchn_fifo_control_block evtchn_fifo_control_block_t; + +#endif /* __XEN_PUBLIC_EVENT_CHANNEL_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/include/xen/events.h b/include/xen/events.h new file mode 100644 index 00000000000..c39c080b3b3 --- /dev/null +++ b/include/xen/events.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _XEN_EVENTS_H +#define _XEN_EVENTS_H + +#include +#include +#include + +static inline void notify_remote_via_evtchn(int port) +{ + struct evtchn_send send = { .port = port }; + (void)HYPERVISOR_event_channel_op(EVTCHNOP_send, &send); +} + +#endif /* _XEN_EVENTS_H */ diff --git a/include/xen/hvm.h b/include/xen/hvm.h new file mode 100644 index 00000000000..0b15f8cb17f --- /dev/null +++ b/include/xen/hvm.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Simple wrappers around HVM functions */ +#ifndef XEN_HVM_H__ +#define XEN_HVM_H__ + +#include +#include + +static const char *param_name(int op) +{ +#define PARAM(x) [HVM_PARAM_##x] = #x + static const char *const names[] = { + PARAM(CALLBACK_IRQ), + PARAM(STORE_PFN), + PARAM(STORE_EVTCHN), + PARAM(PAE_ENABLED), + PARAM(IOREQ_PFN), + PARAM(BUFIOREQ_PFN), + PARAM(TIMER_MODE), + PARAM(HPET_ENABLED), + PARAM(IDENT_PT), + PARAM(DM_DOMAIN), + PARAM(ACPI_S_STATE), + PARAM(VM86_TSS), + PARAM(VPT_ALIGN), + PARAM(CONSOLE_PFN), + PARAM(CONSOLE_EVTCHN), + }; +#undef PARAM + + if (op >= ARRAY_SIZE(names)) + return "unknown"; + + if (!names[op]) + return "reserved"; + + return names[op]; +} +static inline int hvm_get_parameter(int idx, uint64_t *value) +{ + struct xen_hvm_param xhv; + int r; + + xhv.domid = DOMID_SELF; + xhv.index = idx; + r = HYPERVISOR_hvm_op(HVMOP_get_param, &xhv); + if (r < 0) { + pr_err("Cannot get hvm parameter %s (%d): %d!\n", + param_name(idx), idx, r); + return r; + } + *value = xhv.value; + return r; +} + +#define HVM_CALLBACK_VIA_TYPE_VECTOR 0x2 +#define HVM_CALLBACK_VIA_TYPE_SHIFT 56 +#define HVM_CALLBACK_VECTOR(x) (((uint64_t)HVM_CALLBACK_VIA_TYPE_VECTOR)<<\ + HVM_CALLBACK_VIA_TYPE_SHIFT | (x)) + +#endif /* XEN_HVM_H__ */ diff --git a/include/xen/interface/event_channel.h b/include/xen/interface/event_channel.h new file mode 100644 index 00000000000..45650c9a06d --- /dev/null +++ b/include/xen/interface/event_channel.h @@ -0,0 +1,279 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * event_channel.h + * + * Event channels between domains. + * + * Copyright (c) 2003-2004, K A Fraser. + */ + +#ifndef __XEN_PUBLIC_EVENT_CHANNEL_H__ +#define __XEN_PUBLIC_EVENT_CHANNEL_H__ + +#include + +typedef uint32_t evtchn_port_t; +DEFINE_GUEST_HANDLE(evtchn_port_t); + +/* + * EVTCHNOP_alloc_unbound: Allocate a port in domain and mark as + * accepting interdomain bindings from domain . A fresh port + * is allocated in and returned as . + * NOTES: + * 1. If the caller is unprivileged then must be DOMID_SELF. + * 2. may be DOMID_SELF, allowing loopback connections. + */ +#define EVTCHNOP_alloc_unbound 6 +struct evtchn_alloc_unbound { + /* IN parameters */ + domid_t dom, remote_dom; + /* OUT parameters */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_bind_interdomain: Construct an interdomain event channel between + * the calling domain and . must identify + * a port that is unbound and marked as accepting bindings from the calling + * domain. A fresh port is allocated in the calling domain and returned as + * . + * NOTES: + * 2. may be DOMID_SELF, allowing loopback connections. + */ +#define EVTCHNOP_bind_interdomain 0 +struct evtchn_bind_interdomain { + /* IN parameters. */ + domid_t remote_dom; + evtchn_port_t remote_port; + /* OUT parameters. */ + evtchn_port_t local_port; +}; + +/* + * EVTCHNOP_bind_virq: Bind a local event channel to VIRQ on specified + * vcpu. + * NOTES: + * 1. A virtual IRQ may be bound to at most one event channel per vcpu. + * 2. The allocated event channel is bound to the specified vcpu. The binding + * may not be changed. + */ +#define EVTCHNOP_bind_virq 1 +struct evtchn_bind_virq { + /* IN parameters. */ + uint32_t virq; + uint32_t vcpu; + /* OUT parameters. */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_bind_pirq: Bind a local event channel to PIRQ . + * NOTES: + * 1. A physical IRQ may be bound to at most one event channel per domain. + * 2. Only a sufficiently-privileged domain may bind to a physical IRQ. + */ +#define EVTCHNOP_bind_pirq 2 +struct evtchn_bind_pirq { + /* IN parameters. */ + uint32_t pirq; +#define BIND_PIRQ__WILL_SHARE 1 + uint32_t flags; /* BIND_PIRQ__* */ + /* OUT parameters. */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_bind_ipi: Bind a local event channel to receive events. + * NOTES: + * 1. The allocated event channel is bound to the specified vcpu. The binding + * may not be changed. + */ +#define EVTCHNOP_bind_ipi 7 +struct evtchn_bind_ipi { + uint32_t vcpu; + /* OUT parameters. */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_close: Close a local event channel . If the channel is + * interdomain then the remote end is placed in the unbound state + * (EVTCHNSTAT_unbound), awaiting a new connection. + */ +#define EVTCHNOP_close 3 +struct evtchn_close { + /* IN parameters. */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_send: Send an event to the remote end of the channel whose local + * endpoint is . + */ +#define EVTCHNOP_send 4 +struct evtchn_send { + /* IN parameters. */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_status: Get the current status of the communication channel which + * has an endpoint at . + * NOTES: + * 1. may be specified as DOMID_SELF. + * 2. Only a sufficiently-privileged domain may obtain the status of an event + * channel for which is not DOMID_SELF. + */ +#define EVTCHNOP_status 5 +struct evtchn_status { + /* IN parameters */ + domid_t dom; + evtchn_port_t port; + /* OUT parameters */ +#define EVTCHNSTAT_closed 0 /* Channel is not in use. */ +#define EVTCHNSTAT_unbound 1 /* Channel is waiting interdom connection.*/ +#define EVTCHNSTAT_interdomain 2 /* Channel is connected to remote domain. */ +#define EVTCHNSTAT_pirq 3 /* Channel is bound to a phys IRQ line. */ +#define EVTCHNSTAT_virq 4 /* Channel is bound to a virtual IRQ line */ +#define EVTCHNSTAT_ipi 5 /* Channel is bound to a virtual IPI line */ + uint32_t status; + uint32_t vcpu; /* VCPU to which this channel is bound. */ + union { + struct { + domid_t dom; + } unbound; /* EVTCHNSTAT_unbound */ + struct { + domid_t dom; + evtchn_port_t port; + } interdomain; /* EVTCHNSTAT_interdomain */ + uint32_t pirq; /* EVTCHNSTAT_pirq */ + uint32_t virq; /* EVTCHNSTAT_virq */ + } u; +}; + +/* + * EVTCHNOP_bind_vcpu: Specify which vcpu a channel should notify when an + * event is pending. + * NOTES: + * 1. IPI- and VIRQ-bound channels always notify the vcpu that initialised + * the binding. This binding cannot be changed. + * 2. All other channels notify vcpu0 by default. This default is set when + * the channel is allocated (a port that is freed and subsequently reused + * has its binding reset to vcpu0). + */ +#define EVTCHNOP_bind_vcpu 8 +struct evtchn_bind_vcpu { + /* IN parameters. */ + evtchn_port_t port; + uint32_t vcpu; +}; + +/* + * EVTCHNOP_unmask: Unmask the specified local event-channel port and deliver + * a notification to the appropriate VCPU if an event is pending. + */ +#define EVTCHNOP_unmask 9 +struct evtchn_unmask { + /* IN parameters. */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_reset: Close all event channels associated with specified domain. + * NOTES: + * 1. may be specified as DOMID_SELF. + * 2. Only a sufficiently-privileged domain may specify other than DOMID_SELF. + */ +#define EVTCHNOP_reset 10 +struct evtchn_reset { + /* IN parameters. */ + domid_t dom; +}; +typedef struct evtchn_reset evtchn_reset_t; + +/* + * EVTCHNOP_init_control: initialize the control block for the FIFO ABI. + */ +#define EVTCHNOP_init_control 11 +struct evtchn_init_control { + /* IN parameters. */ + uint64_t control_gfn; + uint32_t offset; + uint32_t vcpu; + /* OUT parameters. */ + uint8_t link_bits; + uint8_t _pad[7]; +}; + +/* + * EVTCHNOP_expand_array: add an additional page to the event array. + */ +#define EVTCHNOP_expand_array 12 +struct evtchn_expand_array { + /* IN parameters. */ + uint64_t array_gfn; +}; + +/* + * EVTCHNOP_set_priority: set the priority for an event channel. + */ +#define EVTCHNOP_set_priority 13 +struct evtchn_set_priority { + /* IN parameters. */ + uint32_t port; + uint32_t priority; +}; + +struct evtchn_op { + uint32_t cmd; /* EVTCHNOP_* */ + union { + struct evtchn_alloc_unbound alloc_unbound; + struct evtchn_bind_interdomain bind_interdomain; + struct evtchn_bind_virq bind_virq; + struct evtchn_bind_pirq bind_pirq; + struct evtchn_bind_ipi bind_ipi; + struct evtchn_close close; + struct evtchn_send send; + struct evtchn_status status; + struct evtchn_bind_vcpu bind_vcpu; + struct evtchn_unmask unmask; + } u; +}; +DEFINE_GUEST_HANDLE_STRUCT(evtchn_op); + +/* + * 2-level ABI + */ + +#define EVTCHN_2L_NR_CHANNELS (sizeof(xen_ulong_t) * sizeof(xen_ulong_t) * 64) + +/* + * FIFO ABI + */ + +/* Events may have priorities from 0 (highest) to 15 (lowest). */ +#define EVTCHN_FIFO_PRIORITY_MAX 0 +#define EVTCHN_FIFO_PRIORITY_DEFAULT 7 +#define EVTCHN_FIFO_PRIORITY_MIN 15 + +#define EVTCHN_FIFO_MAX_QUEUES (EVTCHN_FIFO_PRIORITY_MIN + 1) + +typedef uint32_t event_word_t; + +#define EVTCHN_FIFO_PENDING 31 +#define EVTCHN_FIFO_MASKED 30 +#define EVTCHN_FIFO_LINKED 29 +#define EVTCHN_FIFO_BUSY 28 + +#define EVTCHN_FIFO_LINK_BITS 17 +#define EVTCHN_FIFO_LINK_MASK ((1 << EVTCHN_FIFO_LINK_BITS) - 1) + +#define EVTCHN_FIFO_NR_CHANNELS (1 << EVTCHN_FIFO_LINK_BITS) + +struct evtchn_fifo_control_block { + uint32_t ready; + uint32_t _rsvd; + event_word_t head[EVTCHN_FIFO_MAX_QUEUES]; +}; + +#endif /* __XEN_PUBLIC_EVENT_CHANNEL_H__ */ diff --git a/include/xen/interface/grant_table.h b/include/xen/interface/grant_table.h new file mode 100644 index 00000000000..7fb7112d667 --- /dev/null +++ b/include/xen/interface/grant_table.h @@ -0,0 +1,568 @@ +/****************************************************************************** + * grant_table.h + * + * Interface for granting foreign access to page frames, and receiving + * page-ownership transfers. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Copyright (c) 2004, K A Fraser + */ + +#ifndef __XEN_PUBLIC_GRANT_TABLE_H__ +#define __XEN_PUBLIC_GRANT_TABLE_H__ + +#include + +/*********************************** + * GRANT TABLE REPRESENTATION + */ + +/* Some rough guidelines on accessing and updating grant-table entries + * in a concurrency-safe manner. For more information, Linux contains a + * reference implementation for guest OSes (arch/xen/kernel/grant_table.c). + * + * NB. WMB is a no-op on current-generation x86 processors. However, a + * compiler barrier will still be required. + * + * Introducing a valid entry into the grant table: + * 1. Write ent->domid. + * 2. Write ent->frame: + * GTF_permit_access: Frame to which access is permitted. + * GTF_accept_transfer: Pseudo-phys frame slot being filled by new + * frame, or zero if none. + * 3. Write memory barrier (WMB). + * 4. Write ent->flags, inc. valid type. + * + * Invalidating an unused GTF_permit_access entry: + * 1. flags = ent->flags. + * 2. Observe that !(flags & (GTF_reading|GTF_writing)). + * 3. Check result of SMP-safe CMPXCHG(&ent->flags, flags, 0). + * NB. No need for WMB as reuse of entry is control-dependent on success of + * step 3, and all architectures guarantee ordering of ctrl-dep writes. + * + * Invalidating an in-use GTF_permit_access entry: + * This cannot be done directly. Request assistance from the domain controller + * which can set a timeout on the use of a grant entry and take necessary + * action. (NB. This is not yet implemented!). + * + * Invalidating an unused GTF_accept_transfer entry: + * 1. flags = ent->flags. + * 2. Observe that !(flags & GTF_transfer_committed). [*] + * 3. Check result of SMP-safe CMPXCHG(&ent->flags, flags, 0). + * NB. No need for WMB as reuse of entry is control-dependent on success of + * step 3, and all architectures guarantee ordering of ctrl-dep writes. + * [*] If GTF_transfer_committed is set then the grant entry is 'committed'. + * The guest must /not/ modify the grant entry until the address of the + * transferred frame is written. It is safe for the guest to spin waiting + * for this to occur (detect by observing GTF_transfer_completed in + * ent->flags). + * + * Invalidating a committed GTF_accept_transfer entry: + * 1. Wait for (ent->flags & GTF_transfer_completed). + * + * Changing a GTF_permit_access from writable to read-only: + * Use SMP-safe CMPXCHG to set GTF_readonly, while checking !GTF_writing. + * + * Changing a GTF_permit_access from read-only to writable: + * Use SMP-safe bit-setting instruction. + */ + +/* + * Reference to a grant entry in a specified domain's grant table. + */ +typedef uint32_t grant_ref_t; + +/* + * A grant table comprises a packed array of grant entries in one or more + * page frames shared between Xen and a guest. + * [XEN]: This field is written by Xen and read by the sharing guest. + * [GST]: This field is written by the guest and read by Xen. + */ + +/* + * Version 1 of the grant table entry structure is maintained purely + * for backwards compatibility. New guests should use version 2. + */ +struct grant_entry_v1 { + /* GTF_xxx: various type and flag information. [XEN,GST] */ + uint16_t flags; + /* The domain being granted foreign privileges. [GST] */ + domid_t domid; + /* + * GTF_permit_access: Frame that @domid is allowed to map and access. [GST] + * GTF_accept_transfer: Frame whose ownership transferred by @domid. [XEN] + */ + uint32_t frame; +}; + +/* + * Type of grant entry. + * GTF_invalid: This grant entry grants no privileges. + * GTF_permit_access: Allow @domid to map/access @frame. + * GTF_accept_transfer: Allow @domid to transfer ownership of one page frame + * to this guest. Xen writes the page number to @frame. + * GTF_transitive: Allow @domid to transitively access a subrange of + * @trans_grant in @trans_domid. No mappings are allowed. + */ +#define GTF_invalid (0U<<0) +#define GTF_permit_access (1U<<0) +#define GTF_accept_transfer (2U<<0) +#define GTF_transitive (3U<<0) +#define GTF_type_mask (3U<<0) + +/* + * Subflags for GTF_permit_access. + * GTF_readonly: Restrict @domid to read-only mappings and accesses. [GST] + * GTF_reading: Grant entry is currently mapped for reading by @domid. [XEN] + * GTF_writing: Grant entry is currently mapped for writing by @domid. [XEN] + * GTF_sub_page: Grant access to only a subrange of the page. @domid + * will only be allowed to copy from the grant, and not + * map it. [GST] + */ +#define _GTF_readonly (2) +#define GTF_readonly (1U<<_GTF_readonly) +#define _GTF_reading (3) +#define GTF_reading (1U<<_GTF_reading) +#define _GTF_writing (4) +#define GTF_writing (1U<<_GTF_writing) +#define _GTF_sub_page (8) +#define GTF_sub_page (1U<<_GTF_sub_page) + +/* + * Subflags for GTF_accept_transfer: + * GTF_transfer_committed: Xen sets this flag to indicate that it is committed + * to transferring ownership of a page frame. When a guest sees this flag + * it must /not/ modify the grant entry until GTF_transfer_completed is + * set by Xen. + * GTF_transfer_completed: It is safe for the guest to spin-wait on this flag + * after reading GTF_transfer_committed. Xen will always write the frame + * address, followed by ORing this flag, in a timely manner. + */ +#define _GTF_transfer_committed (2) +#define GTF_transfer_committed (1U<<_GTF_transfer_committed) +#define _GTF_transfer_completed (3) +#define GTF_transfer_completed (1U<<_GTF_transfer_completed) + +/* + * Version 2 grant table entries. These fulfil the same role as + * version 1 entries, but can represent more complicated operations. + * Any given domain will have either a version 1 or a version 2 table, + * and every entry in the table will be the same version. + * + * The interface by which domains use grant references does not depend + * on the grant table version in use by the other domain. + */ + +/* + * Version 1 and version 2 grant entries share a common prefix. The + * fields of the prefix are documented as part of struct + * grant_entry_v1. + */ +struct grant_entry_header { + uint16_t flags; + domid_t domid; +}; + +/* + * Version 2 of the grant entry structure, here is a union because three + * different types are suppotted: full_page, sub_page and transitive. + */ +union grant_entry_v2 { + struct grant_entry_header hdr; + + /* + * This member is used for V1-style full page grants, where either: + * + * -- hdr.type is GTF_accept_transfer, or + * -- hdr.type is GTF_permit_access and GTF_sub_page is not set. + * + * In that case, the frame field has the same semantics as the + * field of the same name in the V1 entry structure. + */ + struct { + struct grant_entry_header hdr; + uint32_t pad0; + uint64_t frame; + } full_page; + + /* + * If the grant type is GTF_grant_access and GTF_sub_page is set, + * @domid is allowed to access bytes [@page_off,@page_off+@length) + * in frame @frame. + */ + struct { + struct grant_entry_header hdr; + uint16_t page_off; + uint16_t length; + uint64_t frame; + } sub_page; + + /* + * If the grant is GTF_transitive, @domid is allowed to use the + * grant @gref in domain @trans_domid, as if it was the local + * domain. Obviously, the transitive access must be compatible + * with the original grant. + */ + struct { + struct grant_entry_header hdr; + domid_t trans_domid; + uint16_t pad0; + grant_ref_t gref; + } transitive; + + uint32_t __spacer[4]; /* Pad to a power of two */ +}; + +typedef uint16_t grant_status_t; + +/*********************************** + * GRANT TABLE QUERIES AND USES + */ + +/* + * Handle to track a mapping created via a grant reference. + */ +typedef uint32_t grant_handle_t; + +/* + * GNTTABOP_map_grant_ref: Map the grant entry (,) for access + * by devices and/or host CPUs. If successful, is a tracking number + * that must be presented later to destroy the mapping(s). On error, + * is a negative status code. + * NOTES: + * 1. If GNTMAP_device_map is specified then is the address + * via which I/O devices may access the granted frame. + * 2. If GNTMAP_host_map is specified then a mapping will be added at + * either a host virtual address in the current address space, or at + * a PTE at the specified machine address. The type of mapping to + * perform is selected through the GNTMAP_contains_pte flag, and the + * address is specified in . + * 3. Mappings should only be destroyed via GNTTABOP_unmap_grant_ref. If a + * host mapping is destroyed by other means then it is *NOT* guaranteed + * to be accounted to the correct grant reference! + */ +#define GNTTABOP_map_grant_ref 0 +struct gnttab_map_grant_ref { + /* IN parameters. */ + uint64_t host_addr; + uint32_t flags; /* GNTMAP_* */ + grant_ref_t ref; + domid_t dom; + /* OUT parameters. */ + int16_t status; /* GNTST_* */ + grant_handle_t handle; + uint64_t dev_bus_addr; +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_map_grant_ref); + +/* + * GNTTABOP_unmap_grant_ref: Destroy one or more grant-reference mappings + * tracked by . If or is zero, that + * field is ignored. If non-zero, they must refer to a device/host mapping + * that is tracked by + * NOTES: + * 1. The call may fail in an undefined manner if either mapping is not + * tracked by . + * 3. After executing a batch of unmaps, it is guaranteed that no stale + * mappings will remain in the device or host TLBs. + */ +#define GNTTABOP_unmap_grant_ref 1 +struct gnttab_unmap_grant_ref { + /* IN parameters. */ + uint64_t host_addr; + uint64_t dev_bus_addr; + grant_handle_t handle; + /* OUT parameters. */ + int16_t status; /* GNTST_* */ +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_unmap_grant_ref); + +/* + * GNTTABOP_setup_table: Set up a grant table for comprising at least + * pages. The frame addresses are written to the . + * Only addresses are written, even if the table is larger. + * NOTES: + * 1. may be specified as DOMID_SELF. + * 2. Only a sufficiently-privileged domain may specify != DOMID_SELF. + * 3. Xen may not support more than a single grant-table page per domain. + */ +#define GNTTABOP_setup_table 2 +struct gnttab_setup_table { + /* IN parameters. */ + domid_t dom; + uint32_t nr_frames; + /* OUT parameters. */ + int16_t status; /* GNTST_* */ + GUEST_HANDLE(xen_pfn_t) frame_list; +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_setup_table); + +/* + * GNTTABOP_dump_table: Dump the contents of the grant table to the + * xen console. Debugging use only. + */ +#define GNTTABOP_dump_table 3 +struct gnttab_dump_table { + /* IN parameters. */ + domid_t dom; + /* OUT parameters. */ + int16_t status; /* GNTST_* */ +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_dump_table); + +/* + * GNTTABOP_transfer_grant_ref: Transfer to a foreign domain. The + * foreign domain has previously registered its interest in the transfer via + * . + * + * Note that, even if the transfer fails, the specified page no longer belongs + * to the calling domain *unless* the error is GNTST_bad_page. + */ +#define GNTTABOP_transfer 4 +struct gnttab_transfer { + /* IN parameters. */ + xen_pfn_t mfn; + domid_t domid; + grant_ref_t ref; + /* OUT parameters. */ + int16_t status; +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_transfer); + +/* + * GNTTABOP_copy: Hypervisor based copy + * source and destinations can be eithers MFNs or, for foreign domains, + * grant references. the foreign domain has to grant read/write access + * in its grant table. + * + * The flags specify what type source and destinations are (either MFN + * or grant reference). + * + * Note that this can also be used to copy data between two domains + * via a third party if the source and destination domains had previously + * grant appropriate access to their pages to the third party. + * + * source_offset specifies an offset in the source frame, dest_offset + * the offset in the target frame and len specifies the number of + * bytes to be copied. + */ + +#define _GNTCOPY_source_gref (0) +#define GNTCOPY_source_gref (1<<_GNTCOPY_source_gref) +#define _GNTCOPY_dest_gref (1) +#define GNTCOPY_dest_gref (1<<_GNTCOPY_dest_gref) + +#define GNTTABOP_copy 5 +struct gnttab_copy { + /* IN parameters. */ + struct { + union { + grant_ref_t ref; + xen_pfn_t gmfn; + } u; + domid_t domid; + uint16_t offset; + } source, dest; + uint16_t len; + uint16_t flags; /* GNTCOPY_* */ + /* OUT parameters. */ + int16_t status; +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_copy); + +/* + * GNTTABOP_query_size: Query the current and maximum sizes of the shared + * grant table. + * NOTES: + * 1. may be specified as DOMID_SELF. + * 2. Only a sufficiently-privileged domain may specify != DOMID_SELF. + */ +#define GNTTABOP_query_size 6 +struct gnttab_query_size { + /* IN parameters. */ + domid_t dom; + /* OUT parameters. */ + uint32_t nr_frames; + uint32_t max_nr_frames; + int16_t status; /* GNTST_* */ +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_query_size); + +/* + * GNTTABOP_unmap_and_replace: Destroy one or more grant-reference mappings + * tracked by but atomically replace the page table entry with one + * pointing to the machine address under . will be + * redirected to the null entry. + * NOTES: + * 1. The call may fail in an undefined manner if either mapping is not + * tracked by . + * 2. After executing a batch of unmaps, it is guaranteed that no stale + * mappings will remain in the device or host TLBs. + */ +#define GNTTABOP_unmap_and_replace 7 +struct gnttab_unmap_and_replace { + /* IN parameters. */ + uint64_t host_addr; + uint64_t new_addr; + grant_handle_t handle; + /* OUT parameters. */ + int16_t status; /* GNTST_* */ +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_unmap_and_replace); + +/* + * GNTTABOP_set_version: Request a particular version of the grant + * table shared table structure. This operation can only be performed + * once in any given domain. It must be performed before any grants + * are activated; otherwise, the domain will be stuck with version 1. + * The only defined versions are 1 and 2. + */ +#define GNTTABOP_set_version 8 +struct gnttab_set_version { + /* IN parameters */ + uint32_t version; +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_set_version); + +/* + * GNTTABOP_get_status_frames: Get the list of frames used to store grant + * status for . In grant format version 2, the status is separated + * from the other shared grant fields to allow more efficient synchronization + * using barriers instead of atomic cmpexch operations. + * specify the size of vector . + * The frame addresses are returned in the . + * Only addresses are returned, even if the table is larger. + * NOTES: + * 1. may be specified as DOMID_SELF. + * 2. Only a sufficiently-privileged domain may specify != DOMID_SELF. + */ +#define GNTTABOP_get_status_frames 9 +struct gnttab_get_status_frames { + /* IN parameters. */ + uint32_t nr_frames; + domid_t dom; + /* OUT parameters. */ + int16_t status; /* GNTST_* */ + GUEST_HANDLE(uint64_t) frame_list; +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_get_status_frames); + +/* + * GNTTABOP_get_version: Get the grant table version which is in + * effect for domain . + */ +#define GNTTABOP_get_version 10 +struct gnttab_get_version { + /* IN parameters */ + domid_t dom; + uint16_t pad; + /* OUT parameters */ + uint32_t version; +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_get_version); + +/* + * Issue one or more cache maintenance operations on a portion of a + * page granted to the calling domain by a foreign domain. + */ +#define GNTTABOP_cache_flush 12 +struct gnttab_cache_flush { + union { + uint64_t dev_bus_addr; + grant_ref_t ref; + } a; + uint16_t offset; /* offset from start of grant */ + uint16_t length; /* size within the grant */ +#define GNTTAB_CACHE_CLEAN (1<<0) +#define GNTTAB_CACHE_INVAL (1<<1) +#define GNTTAB_CACHE_SOURCE_GREF (1<<31) + uint32_t op; +}; +DEFINE_GUEST_HANDLE_STRUCT(gnttab_cache_flush); + +/* + * Bitfield values for update_pin_status.flags. + */ + /* Map the grant entry for access by I/O devices. */ +#define _GNTMAP_device_map (0) +#define GNTMAP_device_map (1<<_GNTMAP_device_map) + /* Map the grant entry for access by host CPUs. */ +#define _GNTMAP_host_map (1) +#define GNTMAP_host_map (1<<_GNTMAP_host_map) + /* Accesses to the granted frame will be restricted to read-only access. */ +#define _GNTMAP_readonly (2) +#define GNTMAP_readonly (1<<_GNTMAP_readonly) + /* + * GNTMAP_host_map subflag: + * 0 => The host mapping is usable only by the guest OS. + * 1 => The host mapping is usable by guest OS + current application. + */ +#define _GNTMAP_application_map (3) +#define GNTMAP_application_map (1<<_GNTMAP_application_map) + + /* + * GNTMAP_contains_pte subflag: + * 0 => This map request contains a host virtual address. + * 1 => This map request contains the machine addess of the PTE to update. + */ +#define _GNTMAP_contains_pte (4) +#define GNTMAP_contains_pte (1<<_GNTMAP_contains_pte) + +/* + * Bits to be placed in guest kernel available PTE bits (architecture + * dependent; only supported when XENFEAT_gnttab_map_avail_bits is set). + */ +#define _GNTMAP_guest_avail0 (16) +#define GNTMAP_guest_avail_mask ((uint32_t)~0 << _GNTMAP_guest_avail0) + +/* + * Values for error status returns. All errors are -ve. + */ +#define GNTST_okay (0) /* Normal return. */ +#define GNTST_general_error (-1) /* General undefined error. */ +#define GNTST_bad_domain (-2) /* Unrecognsed domain id. */ +#define GNTST_bad_gntref (-3) /* Unrecognised or inappropriate gntref. */ +#define GNTST_bad_handle (-4) /* Unrecognised or inappropriate handle. */ +#define GNTST_bad_virt_addr (-5) /* Inappropriate virtual address to map. */ +#define GNTST_bad_dev_addr (-6) /* Inappropriate device address to unmap.*/ +#define GNTST_no_device_space (-7) /* Out of space in I/O MMU. */ +#define GNTST_permission_denied (-8) /* Not enough privilege for operation. */ +#define GNTST_bad_page (-9) /* Specified page was invalid for op. */ +#define GNTST_bad_copy_arg (-10) /* copy arguments cross page boundary. */ +#define GNTST_address_too_big (-11) /* transfer page address too large. */ +#define GNTST_eagain (-12) /* Operation not done; try again. */ + +#define GNTTABOP_error_msgs { \ + "okay", \ + "undefined error", \ + "unrecognised domain id", \ + "invalid grant reference", \ + "invalid mapping handle", \ + "invalid virtual address", \ + "invalid device address", \ + "no spare translation slot in the I/O MMU", \ + "permission denied", \ + "bad page", \ + "copy arguments cross page boundary", \ + "page address size too large", \ + "operation not done; try again" \ +} + +#endif /* __XEN_PUBLIC_GRANT_TABLE_H__ */ diff --git a/include/xen/interface/hvm/hvm_op.h b/include/xen/interface/hvm/hvm_op.h new file mode 100644 index 00000000000..956a0468286 --- /dev/null +++ b/include/xen/interface/hvm/hvm_op.h @@ -0,0 +1,65 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __XEN_PUBLIC_HVM_HVM_OP_H__ +#define __XEN_PUBLIC_HVM_HVM_OP_H__ + +/* Get/set subcommands: the second argument of the hypercall is a + * pointer to a xen_hvm_param struct. */ +#define HVMOP_set_param 0 +#define HVMOP_get_param 1 +struct xen_hvm_param { + domid_t domid; /* IN */ + uint32_t index; /* IN */ + uint64_t value; /* IN/OUT */ +}; +DEFINE_GUEST_HANDLE_STRUCT(xen_hvm_param); + +/* Hint from PV drivers for pagetable destruction. */ +#define HVMOP_pagetable_dying 9 +struct xen_hvm_pagetable_dying { + /* Domain with a pagetable about to be destroyed. */ + domid_t domid; + /* guest physical address of the toplevel pagetable dying */ + aligned_u64 gpa; +}; +typedef struct xen_hvm_pagetable_dying xen_hvm_pagetable_dying_t; +DEFINE_GUEST_HANDLE_STRUCT(xen_hvm_pagetable_dying_t); + +enum hvmmem_type_t { + HVMMEM_ram_rw, /* Normal read/write guest RAM */ + HVMMEM_ram_ro, /* Read-only; writes are discarded */ + HVMMEM_mmio_dm, /* Reads and write go to the device model */ +}; + +#define HVMOP_get_mem_type 15 +/* Return hvmmem_type_t for the specified pfn. */ +struct xen_hvm_get_mem_type { + /* Domain to be queried. */ + domid_t domid; + /* OUT variable. */ + uint16_t mem_type; + uint16_t pad[2]; /* align next field on 8-byte boundary */ + /* IN variable. */ + uint64_t pfn; +}; +DEFINE_GUEST_HANDLE_STRUCT(xen_hvm_get_mem_type); + +#endif /* __XEN_PUBLIC_HVM_HVM_OP_H__ */ diff --git a/include/xen/interface/hvm/params.h b/include/xen/interface/hvm/params.h new file mode 100644 index 00000000000..4d61fc58d99 --- /dev/null +++ b/include/xen/interface/hvm/params.h @@ -0,0 +1,127 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __XEN_PUBLIC_HVM_PARAMS_H__ +#define __XEN_PUBLIC_HVM_PARAMS_H__ + +#include + +/* + * Parameter space for HVMOP_{set,get}_param. + */ + +#define HVM_PARAM_CALLBACK_IRQ 0 +/* + * How should CPU0 event-channel notifications be delivered? + * + * If val == 0 then CPU0 event-channel notifications are not delivered. + * If val != 0, val[63:56] encodes the type, as follows: + */ + +#define HVM_PARAM_CALLBACK_TYPE_GSI 0 +/* + * val[55:0] is a delivery GSI. GSI 0 cannot be used, as it aliases val == 0, + * and disables all notifications. + */ + +#define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1 +/* + * val[55:0] is a delivery PCI INTx line: + * Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0] + */ + +#if defined(__i386__) || defined(__x86_64__) +#define HVM_PARAM_CALLBACK_TYPE_VECTOR 2 +/* + * val[7:0] is a vector number. Check for XENFEAT_hvm_callback_vector to know + * if this delivery method is available. + */ +#elif defined(__arm__) || defined(__aarch64__) +#define HVM_PARAM_CALLBACK_TYPE_PPI 2 +/* + * val[55:16] needs to be zero. + * val[15:8] is interrupt flag of the PPI used by event-channel: + * bit 8: the PPI is edge(1) or level(0) triggered + * bit 9: the PPI is active low(1) or high(0) + * val[7:0] is a PPI number used by event-channel. + * This is only used by ARM/ARM64 and masking/eoi the interrupt associated to + * the notification is handled by the interrupt controller. + */ +#endif + +#define HVM_PARAM_STORE_PFN 1 +#define HVM_PARAM_STORE_EVTCHN 2 + +#define HVM_PARAM_PAE_ENABLED 4 + +#define HVM_PARAM_IOREQ_PFN 5 + +#define HVM_PARAM_BUFIOREQ_PFN 6 + +/* + * Set mode for virtual timers (currently x86 only): + * delay_for_missed_ticks (default): + * Do not advance a vcpu's time beyond the correct delivery time for + * interrupts that have been missed due to preemption. Deliver missed + * interrupts when the vcpu is rescheduled and advance the vcpu's virtual + * time stepwise for each one. + * no_delay_for_missed_ticks: + * As above, missed interrupts are delivered, but guest time always tracks + * wallclock (i.e., real) time while doing so. + * no_missed_ticks_pending: + * No missed interrupts are held pending. Instead, to ensure ticks are + * delivered at some non-zero rate, if we detect missed ticks then the + * internal tick alarm is not disabled if the VCPU is preempted during the + * next tick period. + * one_missed_tick_pending: + * Missed interrupts are collapsed together and delivered as one 'late tick'. + * Guest time always tracks wallclock (i.e., real) time. + */ +#define HVM_PARAM_TIMER_MODE 10 +#define HVMPTM_delay_for_missed_ticks 0 +#define HVMPTM_no_delay_for_missed_ticks 1 +#define HVMPTM_no_missed_ticks_pending 2 +#define HVMPTM_one_missed_tick_pending 3 + +/* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */ +#define HVM_PARAM_HPET_ENABLED 11 + +/* Identity-map page directory used by Intel EPT when CR0.PG=0. */ +#define HVM_PARAM_IDENT_PT 12 + +/* Device Model domain, defaults to 0. */ +#define HVM_PARAM_DM_DOMAIN 13 + +/* ACPI S state: currently support S0 and S3 on x86. */ +#define HVM_PARAM_ACPI_S_STATE 14 + +/* TSS used on Intel when CR0.PE=0. */ +#define HVM_PARAM_VM86_TSS 15 + +/* Boolean: Enable aligning all periodic vpts to reduce interrupts */ +#define HVM_PARAM_VPT_ALIGN 16 + +/* Console debug shared memory ring and event channel */ +#define HVM_PARAM_CONSOLE_PFN 17 +#define HVM_PARAM_CONSOLE_EVTCHN 18 + +#define HVM_NR_PARAMS 19 + +#endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */ diff --git a/include/xen/interface/io/console.h b/include/xen/interface/io/console.h new file mode 100644 index 00000000000..85ca8b02695 --- /dev/null +++ b/include/xen/interface/io/console.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * console.h + * + * Console I/O interface for Xen guest OSes. + * + * Copyright (c) 2005, Keir Fraser + */ + +#ifndef __XEN_PUBLIC_IO_CONSOLE_H__ +#define __XEN_PUBLIC_IO_CONSOLE_H__ + +typedef uint32_t XENCONS_RING_IDX; + +#define MASK_XENCONS_IDX(idx, ring) ((idx) & (sizeof(ring)-1)) + +struct xencons_interface { + char in[1024]; + char out[2048]; + XENCONS_RING_IDX in_cons, in_prod; + XENCONS_RING_IDX out_cons, out_prod; +}; + +#endif /* __XEN_PUBLIC_IO_CONSOLE_H__ */ diff --git a/include/xen/interface/io/ring.h b/include/xen/interface/io/ring.h new file mode 100644 index 00000000000..3f40501fc60 --- /dev/null +++ b/include/xen/interface/io/ring.h @@ -0,0 +1,432 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * ring.h + * + * Shared producer-consumer ring macros. + * + * Tim Deegan and Andrew Warfield November 2004. + */ + +#ifndef __XEN_PUBLIC_IO_RING_H__ +#define __XEN_PUBLIC_IO_RING_H__ + +#include + +typedef unsigned int RING_IDX; + +/* Round a 32-bit unsigned constant down to the nearest power of two. */ +#define __RD2(_x) (((_x) & 0x00000002) ? 0x2 : ((_x) & 0x1)) +#define __RD4(_x) (((_x) & 0x0000000c) ? __RD2((_x)>>2)<<2 : __RD2(_x)) +#define __RD8(_x) (((_x) & 0x000000f0) ? __RD4((_x)>>4)<<4 : __RD4(_x)) +#define __RD16(_x) (((_x) & 0x0000ff00) ? __RD8((_x)>>8)<<8 : __RD8(_x)) +#define __RD32(_x) (((_x) & 0xffff0000) ? __RD16((_x)>>16)<<16 : __RD16(_x)) + +/* + * Calculate size of a shared ring, given the total available space for the + * ring and indexes (_sz), and the name tag of the request/response structure. + * A ring contains as many entries as will fit, rounded down to the nearest + * power of two (so we can mask with (size-1) to loop around). + */ +#define __CONST_RING_SIZE(_s, _sz) \ + (__RD32(((_sz) - offsetof(struct _s##_sring, ring)) / \ + sizeof(((struct _s##_sring *)0)->ring[0]))) + +/* + * The same for passing in an actual pointer instead of a name tag. + */ +#define __RING_SIZE(_s, _sz) \ + (__RD32(((_sz) - (long)&(_s)->ring + (long)(_s)) / sizeof((_s)->ring[0]))) + +/* + * Macros to make the correct C datatypes for a new kind of ring. + * + * To make a new ring datatype, you need to have two message structures, + * let's say struct request, and struct response already defined. + * + * In a header where you want the ring datatype declared, you then do: + * + * DEFINE_RING_TYPES(mytag, struct request, struct response); + * + * These expand out to give you a set of types, as you can see below. + * The most important of these are: + * + * struct mytag_sring - The shared ring. + * struct mytag_front_ring - The 'front' half of the ring. + * struct mytag_back_ring - The 'back' half of the ring. + * + * To initialize a ring in your code you need to know the location and size + * of the shared memory area (PAGE_SIZE, for instance). To initialise + * the front half: + * + * struct mytag_front_ring front_ring; + * SHARED_RING_INIT((struct mytag_sring *)shared_page); + * FRONT_RING_INIT(&front_ring, (struct mytag_sring *)shared_page, + * PAGE_SIZE); + * + * Initializing the back follows similarly (note that only the front + * initializes the shared ring): + * + * struct mytag_back_ring back_ring; + * BACK_RING_INIT(&back_ring, (struct mytag_sring *)shared_page, + * PAGE_SIZE); + */ + +#define DEFINE_RING_TYPES(__name, __req_t, __rsp_t) \ + \ +/* Shared ring entry */ \ +union __name##_sring_entry { \ + __req_t req; \ + __rsp_t rsp; \ +}; \ + \ +/* Shared ring page */ \ +struct __name##_sring { \ + RING_IDX req_prod, req_event; \ + RING_IDX rsp_prod, rsp_event; \ + uint8_t pad[48]; \ + union __name##_sring_entry ring[1]; /* variable-length */ \ +}; \ + \ +/* "Front" end's private variables */ \ +struct __name##_front_ring { \ + RING_IDX req_prod_pvt; \ + RING_IDX rsp_cons; \ + unsigned int nr_ents; \ + struct __name##_sring *sring; \ +}; \ + \ +/* "Back" end's private variables */ \ +struct __name##_back_ring { \ + RING_IDX rsp_prod_pvt; \ + RING_IDX req_cons; \ + unsigned int nr_ents; \ + struct __name##_sring *sring; \ +}; + +/* + * Macros for manipulating rings. + * + * FRONT_RING_whatever works on the "front end" of a ring: here + * requests are pushed on to the ring and responses taken off it. + * + * BACK_RING_whatever works on the "back end" of a ring: here + * requests are taken off the ring and responses put on. + * + * N.B. these macros do NO INTERLOCKS OR FLOW CONTROL. + * This is OK in 1-for-1 request-response situations where the + * requestor (front end) never has more than RING_SIZE()-1 + * outstanding requests. + */ + +/* Initialising empty rings */ +#define SHARED_RING_INIT(_s) do { \ + (_s)->req_prod = (_s)->rsp_prod = 0; \ + (_s)->req_event = (_s)->rsp_event = 1; \ + memset((_s)->pad, 0, sizeof((_s)->pad)); \ +} while(0) + +#define FRONT_RING_INIT(_r, _s, __size) do { \ + (_r)->req_prod_pvt = 0; \ + (_r)->rsp_cons = 0; \ + (_r)->nr_ents = __RING_SIZE(_s, __size); \ + (_r)->sring = (_s); \ +} while (0) + +#define BACK_RING_INIT(_r, _s, __size) do { \ + (_r)->rsp_prod_pvt = 0; \ + (_r)->req_cons = 0; \ + (_r)->nr_ents = __RING_SIZE(_s, __size); \ + (_r)->sring = (_s); \ +} while (0) + +/* Initialize to existing shared indexes -- for recovery */ +#define FRONT_RING_ATTACH(_r, _s, __size) do { \ + (_r)->sring = (_s); \ + (_r)->req_prod_pvt = (_s)->req_prod; \ + (_r)->rsp_cons = (_s)->rsp_prod; \ + (_r)->nr_ents = __RING_SIZE(_s, __size); \ +} while (0) + +#define BACK_RING_ATTACH(_r, _s, __size) do { \ + (_r)->sring = (_s); \ + (_r)->rsp_prod_pvt = (_s)->rsp_prod; \ + (_r)->req_cons = (_s)->req_prod; \ + (_r)->nr_ents = __RING_SIZE(_s, __size); \ +} while (0) + +/* How big is this ring? */ +#define RING_SIZE(_r) \ + ((_r)->nr_ents) + +/* Number of free requests (for use on front side only). */ +#define RING_FREE_REQUESTS(_r) \ + (RING_SIZE(_r) - ((_r)->req_prod_pvt - (_r)->rsp_cons)) + +/* Test if there is an empty slot available on the front ring. + * (This is only meaningful from the front. ) + */ +#define RING_FULL(_r) \ + (RING_FREE_REQUESTS(_r) == 0) + +/* Test if there are outstanding messages to be processed on a ring. */ +#define RING_HAS_UNCONSUMED_RESPONSES(_r) \ + ((_r)->sring->rsp_prod - (_r)->rsp_cons) + +#define RING_HAS_UNCONSUMED_REQUESTS(_r) \ + ({ \ + unsigned int req = (_r)->sring->req_prod - (_r)->req_cons; \ + unsigned int rsp = RING_SIZE(_r) - \ + ((_r)->req_cons - (_r)->rsp_prod_pvt); \ + req < rsp ? req : rsp; \ + }) + +/* Direct access to individual ring elements, by index. */ +#define RING_GET_REQUEST(_r, _idx) \ + (&((_r)->sring->ring[((_idx) & (RING_SIZE(_r) - 1))].req)) + +/* + * Get a local copy of a request. + * + * Use this in preference to RING_GET_REQUEST() so all processing is + * done on a local copy that cannot be modified by the other end. + * + * Note that https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145 may cause this + * to be ineffective where _req is a struct which consists of only bitfields. + */ +#define RING_COPY_REQUEST(_r, _idx, _req) do { \ + /* Use volatile to force the copy into _req. */ \ + *(_req) = *(volatile typeof(_req))RING_GET_REQUEST(_r, _idx); \ +} while (0) + +#define RING_GET_RESPONSE(_r, _idx) \ + (&((_r)->sring->ring[((_idx) & (RING_SIZE(_r) - 1))].rsp)) + +/* Loop termination condition: Would the specified index overflow the ring? */ +#define RING_REQUEST_CONS_OVERFLOW(_r, _cons) \ + (((_cons) - (_r)->rsp_prod_pvt) >= RING_SIZE(_r)) + +/* Ill-behaved frontend determination: Can there be this many requests? */ +#define RING_REQUEST_PROD_OVERFLOW(_r, _prod) \ + (((_prod) - (_r)->rsp_prod_pvt) > RING_SIZE(_r)) + + +#define RING_PUSH_REQUESTS(_r) do { \ + virt_wmb(); /* back sees requests /before/ updated producer index */ \ + (_r)->sring->req_prod = (_r)->req_prod_pvt; \ +} while (0) + +#define RING_PUSH_RESPONSES(_r) do { \ + virt_wmb(); /* front sees responses /before/ updated producer index */ \ + (_r)->sring->rsp_prod = (_r)->rsp_prod_pvt; \ +} while (0) + +/* + * Notification hold-off (req_event and rsp_event): + * + * When queueing requests or responses on a shared ring, it may not always be + * necessary to notify the remote end. For example, if requests are in flight + * in a backend, the front may be able to queue further requests without + * notifying the back (if the back checks for new requests when it queues + * responses). + * + * When enqueuing requests or responses: + * + * Use RING_PUSH_{REQUESTS,RESPONSES}_AND_CHECK_NOTIFY(). The second argument + * is a boolean return value. True indicates that the receiver requires an + * asynchronous notification. + * + * After dequeuing requests or responses (before sleeping the connection): + * + * Use RING_FINAL_CHECK_FOR_REQUESTS() or RING_FINAL_CHECK_FOR_RESPONSES(). + * The second argument is a boolean return value. True indicates that there + * are pending messages on the ring (i.e., the connection should not be put + * to sleep). + * + * These macros will set the req_event/rsp_event field to trigger a + * notification on the very next message that is enqueued. If you want to + * create batches of work (i.e., only receive a notification after several + * messages have been enqueued) then you will need to create a customised + * version of the FINAL_CHECK macro in your own code, which sets the event + * field appropriately. + */ + +#define RING_PUSH_REQUESTS_AND_CHECK_NOTIFY(_r, _notify) do { \ + RING_IDX __old = (_r)->sring->req_prod; \ + RING_IDX __new = (_r)->req_prod_pvt; \ + virt_wmb(); /* back sees requests /before/ updated producer index */ \ + (_r)->sring->req_prod = __new; \ + virt_mb(); /* back sees new requests /before/ we check req_event */ \ + (_notify) = ((RING_IDX)(__new - (_r)->sring->req_event) < \ + (RING_IDX)(__new - __old)); \ +} while (0) + +#define RING_PUSH_RESPONSES_AND_CHECK_NOTIFY(_r, _notify) do { \ + RING_IDX __old = (_r)->sring->rsp_prod; \ + RING_IDX __new = (_r)->rsp_prod_pvt; \ + virt_wmb(); /* front sees responses /before/ updated producer index */ \ + (_r)->sring->rsp_prod = __new; \ + virt_mb(); /* front sees new responses /before/ we check rsp_event */ \ + (_notify) = ((RING_IDX)(__new - (_r)->sring->rsp_event) < \ + (RING_IDX)(__new - __old)); \ +} while (0) + +#define RING_FINAL_CHECK_FOR_REQUESTS(_r, _work_to_do) do { \ + (_work_to_do) = RING_HAS_UNCONSUMED_REQUESTS(_r); \ + if (_work_to_do) break; \ + (_r)->sring->req_event = (_r)->req_cons + 1; \ + virt_mb(); \ + (_work_to_do) = RING_HAS_UNCONSUMED_REQUESTS(_r); \ +} while (0) + +#define RING_FINAL_CHECK_FOR_RESPONSES(_r, _work_to_do) do { \ + (_work_to_do) = RING_HAS_UNCONSUMED_RESPONSES(_r); \ + if (_work_to_do) break; \ + (_r)->sring->rsp_event = (_r)->rsp_cons + 1; \ + virt_mb(); \ + (_work_to_do) = RING_HAS_UNCONSUMED_RESPONSES(_r); \ +} while (0) + + +/* + * DEFINE_XEN_FLEX_RING_AND_INTF defines two monodirectional rings and + * functions to check if there is data on the ring, and to read and + * write to them. + * + * DEFINE_XEN_FLEX_RING is similar to DEFINE_XEN_FLEX_RING_AND_INTF, but + * does not define the indexes page. As different protocols can have + * extensions to the basic format, this macro allow them to define their + * own struct. + * + * XEN_FLEX_RING_SIZE + * Convenience macro to calculate the size of one of the two rings + * from the overall order. + * + * $NAME_mask + * Function to apply the size mask to an index, to reduce the index + * within the range [0-size]. + * + * $NAME_read_packet + * Function to read data from the ring. The amount of data to read is + * specified by the "size" argument. + * + * $NAME_write_packet + * Function to write data to the ring. The amount of data to write is + * specified by the "size" argument. + * + * $NAME_get_ring_ptr + * Convenience function that returns a pointer to read/write to the + * ring at the right location. + * + * $NAME_data_intf + * Indexes page, shared between frontend and backend. It also + * contains the array of grant refs. + * + * $NAME_queued + * Function to calculate how many bytes are currently on the ring, + * ready to be read. It can also be used to calculate how much free + * space is currently on the ring (XEN_FLEX_RING_SIZE() - + * $NAME_queued()). + */ + +#ifndef XEN_PAGE_SHIFT +/* The PAGE_SIZE for ring protocols and hypercall interfaces is always + * 4K, regardless of the architecture, and page granularity chosen by + * operating systems. + */ +#define XEN_PAGE_SHIFT 12 +#endif +#define XEN_FLEX_RING_SIZE(order) \ + (1UL << ((order) + XEN_PAGE_SHIFT - 1)) + +#define DEFINE_XEN_FLEX_RING(name) \ +static inline RING_IDX name##_mask(RING_IDX idx, RING_IDX ring_size) \ +{ \ + return idx & (ring_size - 1); \ +} \ + \ +static inline unsigned char *name##_get_ring_ptr(unsigned char *buf, \ + RING_IDX idx, \ + RING_IDX ring_size) \ +{ \ + return buf + name##_mask(idx, ring_size); \ +} \ + \ +static inline void name##_read_packet(void *opaque, \ + const unsigned char *buf, \ + size_t size, \ + RING_IDX masked_prod, \ + RING_IDX *masked_cons, \ + RING_IDX ring_size) \ +{ \ + if (*masked_cons < masked_prod || \ + size <= ring_size - *masked_cons) { \ + memcpy(opaque, buf + *masked_cons, size); \ + } else { \ + memcpy(opaque, buf + *masked_cons, ring_size - *masked_cons); \ + memcpy((unsigned char *)opaque + ring_size - *masked_cons, buf, \ + size - (ring_size - *masked_cons)); \ + } \ + *masked_cons = name##_mask(*masked_cons + size, ring_size); \ +} \ + \ +static inline void name##_write_packet(unsigned char *buf, \ + const void *opaque, \ + size_t size, \ + RING_IDX *masked_prod, \ + RING_IDX masked_cons, \ + RING_IDX ring_size) \ +{ \ + if (*masked_prod < masked_cons || \ + size <= ring_size - *masked_prod) { \ + memcpy(buf + *masked_prod, opaque, size); \ + } else { \ + memcpy(buf + *masked_prod, opaque, ring_size - *masked_prod); \ + memcpy(buf, (unsigned char *)opaque + (ring_size - *masked_prod), \ + size - (ring_size - *masked_prod)); \ + } \ + *masked_prod = name##_mask(*masked_prod + size, ring_size); \ +} \ + \ +static inline RING_IDX name##_queued(RING_IDX prod, \ + RING_IDX cons, \ + RING_IDX ring_size) \ +{ \ + RING_IDX size; \ + \ + if (prod == cons) \ + return 0; \ + \ + prod = name##_mask(prod, ring_size); \ + cons = name##_mask(cons, ring_size); \ + \ + if (prod == cons) \ + return ring_size; \ + \ + if (prod > cons) \ + size = prod - cons; \ + else \ + size = ring_size - (cons - prod); \ + return size; \ +} \ + \ +struct name##_data { \ + unsigned char *in; /* half of the allocation */ \ + unsigned char *out; /* half of the allocation */ \ +} + +#define DEFINE_XEN_FLEX_RING_AND_INTF(name) \ +struct name##_data_intf { \ + RING_IDX in_cons, in_prod; \ + \ + uint8_t pad1[56]; \ + \ + RING_IDX out_cons, out_prod; \ + \ + uint8_t pad2[56]; \ + \ + RING_IDX ring_order; \ + grant_ref_t ref[]; \ +}; \ +DEFINE_XEN_FLEX_RING(name) + +#endif /* __XEN_PUBLIC_IO_RING_H__ */ diff --git a/include/xen/interface/platform.h b/include/xen/interface/platform.h new file mode 100644 index 00000000000..732efb08c3e --- /dev/null +++ b/include/xen/interface/platform.h @@ -0,0 +1,531 @@ +/****************************************************************************** + * platform.h + * + * Hardware platform operations. Intended for use by domain-0 kernel. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Copyright (c) 2002-2006, K Fraser + */ + +#ifndef __XEN_PUBLIC_PLATFORM_H__ +#define __XEN_PUBLIC_PLATFORM_H__ + +#include + +#define XENPF_INTERFACE_VERSION 0x03000001 + +/* + * Set clock such that it would read after 00:00:00 UTC, + * 1 January, 1970 if the current system time was . + */ +#define XENPF_settime32 17 +struct xenpf_settime32 { + /* IN variables. */ + uint32_t secs; + uint32_t nsecs; + uint64_t system_time; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_settime32_t); +#define XENPF_settime64 62 +struct xenpf_settime64 { + /* IN variables. */ + uint64_t secs; + uint32_t nsecs; + uint32_t mbz; + uint64_t system_time; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_settime64_t); + +/* + * Request memory range (@mfn, @mfn+@nr_mfns-1) to have type @type. + * On x86, @type is an architecture-defined MTRR memory type. + * On success, returns the MTRR that was used (@reg) and a handle that can + * be passed to XENPF_DEL_MEMTYPE to accurately tear down the new setting. + * (x86-specific). + */ +#define XENPF_add_memtype 31 +struct xenpf_add_memtype { + /* IN variables. */ + xen_pfn_t mfn; + uint64_t nr_mfns; + uint32_t type; + /* OUT variables. */ + uint32_t handle; + uint32_t reg; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_add_memtype_t); + +/* + * Tear down an existing memory-range type. If @handle is remembered then it + * should be passed in to accurately tear down the correct setting (in case + * of overlapping memory regions with differing types). If it is not known + * then @handle should be set to zero. In all cases @reg must be set. + * (x86-specific). + */ +#define XENPF_del_memtype 32 +struct xenpf_del_memtype { + /* IN variables. */ + uint32_t handle; + uint32_t reg; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_del_memtype_t); + +/* Read current type of an MTRR (x86-specific). */ +#define XENPF_read_memtype 33 +struct xenpf_read_memtype { + /* IN variables. */ + uint32_t reg; + /* OUT variables. */ + xen_pfn_t mfn; + uint64_t nr_mfns; + uint32_t type; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_read_memtype_t); + +#define XENPF_microcode_update 35 +struct xenpf_microcode_update { + /* IN variables. */ + GUEST_HANDLE(void) data; /* Pointer to microcode data */ + uint32_t length; /* Length of microcode data. */ +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_microcode_update_t); + +#define XENPF_platform_quirk 39 +#define QUIRK_NOIRQBALANCING 1 /* Do not restrict IO-APIC RTE targets */ +#define QUIRK_IOAPIC_BAD_REGSEL 2 /* IO-APIC REGSEL forgets its value */ +#define QUIRK_IOAPIC_GOOD_REGSEL 3 /* IO-APIC REGSEL behaves properly */ +struct xenpf_platform_quirk { + /* IN variables. */ + uint32_t quirk_id; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_platform_quirk_t); + +#define XENPF_efi_runtime_call 49 +#define XEN_EFI_get_time 1 +#define XEN_EFI_set_time 2 +#define XEN_EFI_get_wakeup_time 3 +#define XEN_EFI_set_wakeup_time 4 +#define XEN_EFI_get_next_high_monotonic_count 5 +#define XEN_EFI_get_variable 6 +#define XEN_EFI_set_variable 7 +#define XEN_EFI_get_next_variable_name 8 +#define XEN_EFI_query_variable_info 9 +#define XEN_EFI_query_capsule_capabilities 10 +#define XEN_EFI_update_capsule 11 + +struct xenpf_efi_runtime_call { + uint32_t function; + /* + * This field is generally used for per sub-function flags (defined + * below), except for the XEN_EFI_get_next_high_monotonic_count case, + * where it holds the single returned value. + */ + uint32_t misc; + xen_ulong_t status; + union { +#define XEN_EFI_GET_TIME_SET_CLEARS_NS 0x00000001 + struct { + struct xenpf_efi_time { + uint16_t year; + uint8_t month; + uint8_t day; + uint8_t hour; + uint8_t min; + uint8_t sec; + uint32_t ns; + int16_t tz; + uint8_t daylight; + } time; + uint32_t resolution; + uint32_t accuracy; + } get_time; + + struct xenpf_efi_time set_time; + +#define XEN_EFI_GET_WAKEUP_TIME_ENABLED 0x00000001 +#define XEN_EFI_GET_WAKEUP_TIME_PENDING 0x00000002 + struct xenpf_efi_time get_wakeup_time; + +#define XEN_EFI_SET_WAKEUP_TIME_ENABLE 0x00000001 +#define XEN_EFI_SET_WAKEUP_TIME_ENABLE_ONLY 0x00000002 + struct xenpf_efi_time set_wakeup_time; + +#define XEN_EFI_VARIABLE_NON_VOLATILE 0x00000001 +#define XEN_EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 +#define XEN_EFI_VARIABLE_RUNTIME_ACCESS 0x00000004 + struct { + GUEST_HANDLE(void) name; /* UCS-2/UTF-16 string */ + xen_ulong_t size; + GUEST_HANDLE(void) data; + struct xenpf_efi_guid { + uint32_t data1; + uint16_t data2; + uint16_t data3; + uint8_t data4[8]; + } vendor_guid; + } get_variable, set_variable; + + struct { + xen_ulong_t size; + GUEST_HANDLE(void) name; /* UCS-2/UTF-16 string */ + struct xenpf_efi_guid vendor_guid; + } get_next_variable_name; + + struct { + uint32_t attr; + uint64_t max_store_size; + uint64_t remain_store_size; + uint64_t max_size; + } query_variable_info; + + struct { + GUEST_HANDLE(void) capsule_header_array; + xen_ulong_t capsule_count; + uint64_t max_capsule_size; + uint32_t reset_type; + } query_capsule_capabilities; + + struct { + GUEST_HANDLE(void) capsule_header_array; + xen_ulong_t capsule_count; + uint64_t sg_list; /* machine address */ + } update_capsule; + } u; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_efi_runtime_call); + +#define XEN_FW_EFI_VERSION 0 +#define XEN_FW_EFI_CONFIG_TABLE 1 +#define XEN_FW_EFI_VENDOR 2 +#define XEN_FW_EFI_MEM_INFO 3 +#define XEN_FW_EFI_RT_VERSION 4 + +#define XENPF_firmware_info 50 +#define XEN_FW_DISK_INFO 1 /* from int 13 AH=08/41/48 */ +#define XEN_FW_DISK_MBR_SIGNATURE 2 /* from MBR offset 0x1b8 */ +#define XEN_FW_VBEDDC_INFO 3 /* from int 10 AX=4f15 */ +#define XEN_FW_EFI_INFO 4 /* from EFI */ +#define XEN_FW_KBD_SHIFT_FLAGS 5 /* Int16, Fn02: Get keyboard shift flags. */ + +struct xenpf_firmware_info { + /* IN variables. */ + uint32_t type; + uint32_t index; + /* OUT variables. */ + union { + struct { + /* Int13, Fn48: Check Extensions Present. */ + uint8_t device; /* %dl: bios device number */ + uint8_t version; /* %ah: major version */ + uint16_t interface_support; /* %cx: support bitmap */ + /* Int13, Fn08: Legacy Get Device Parameters. */ + uint16_t legacy_max_cylinder; /* %cl[7:6]:%ch: max cyl # */ + uint8_t legacy_max_head; /* %dh: max head # */ + uint8_t legacy_sectors_per_track; /* %cl[5:0]: max sector # */ + /* Int13, Fn41: Get Device Parameters (as filled into %ds:%esi). */ + /* NB. First uint16_t of buffer must be set to buffer size. */ + GUEST_HANDLE(void) edd_params; + } disk_info; /* XEN_FW_DISK_INFO */ + struct { + uint8_t device; /* bios device number */ + uint32_t mbr_signature; /* offset 0x1b8 in mbr */ + } disk_mbr_signature; /* XEN_FW_DISK_MBR_SIGNATURE */ + struct { + /* Int10, AX=4F15: Get EDID info. */ + uint8_t capabilities; + uint8_t edid_transfer_time; + /* must refer to 128-byte buffer */ + GUEST_HANDLE(uchar) edid; + } vbeddc_info; /* XEN_FW_VBEDDC_INFO */ + + union xenpf_efi_info { + uint32_t version; + struct { + uint64_t addr; /* EFI_CONFIGURATION_TABLE */ + uint32_t nent; + } cfg; + struct { + uint32_t revision; + uint32_t bufsz; /* input, in bytes */ + GUEST_HANDLE(void) name; + /* UCS-2/UTF-16 string */ + } vendor; + struct { + uint64_t addr; + uint64_t size; + uint64_t attr; + uint32_t type; + } mem; + } efi_info; /* XEN_FW_EFI_INFO */ + + uint8_t kbd_shift_flags; /* XEN_FW_KBD_SHIFT_FLAGS */ + } u; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_firmware_info_t); + +#define XENPF_enter_acpi_sleep 51 +struct xenpf_enter_acpi_sleep { + /* IN variables */ + uint16_t val_a; /* PM1a control / sleep type A. */ + uint16_t val_b; /* PM1b control / sleep type B. */ + uint32_t sleep_state; /* Which state to enter (Sn). */ +#define XENPF_ACPI_SLEEP_EXTENDED 0x00000001 + uint32_t flags; /* XENPF_ACPI_SLEEP_*. */ +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_enter_acpi_sleep_t); + +#define XENPF_change_freq 52 +struct xenpf_change_freq { + /* IN variables */ + uint32_t flags; /* Must be zero. */ + uint32_t cpu; /* Physical cpu. */ + uint64_t freq; /* New frequency (Hz). */ +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_change_freq_t); + +/* + * Get idle times (nanoseconds since boot) for physical CPUs specified in the + * @cpumap_bitmap with range [0..@cpumap_nr_cpus-1]. The @idletime array is + * indexed by CPU number; only entries with the corresponding @cpumap_bitmap + * bit set are written to. On return, @cpumap_bitmap is modified so that any + * non-existent CPUs are cleared. Such CPUs have their @idletime array entry + * cleared. + */ +#define XENPF_getidletime 53 +struct xenpf_getidletime { + /* IN/OUT variables */ + /* IN: CPUs to interrogate; OUT: subset of IN which are present */ + GUEST_HANDLE(uchar) cpumap_bitmap; + /* IN variables */ + /* Size of cpumap bitmap. */ + uint32_t cpumap_nr_cpus; + /* Must be indexable for every cpu in cpumap_bitmap. */ + GUEST_HANDLE(uint64_t) idletime; + /* OUT variables */ + /* System time when the idletime snapshots were taken. */ + uint64_t now; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_getidletime_t); + +#define XENPF_set_processor_pminfo 54 + +/* ability bits */ +#define XEN_PROCESSOR_PM_CX 1 +#define XEN_PROCESSOR_PM_PX 2 +#define XEN_PROCESSOR_PM_TX 4 + +/* cmd type */ +#define XEN_PM_CX 0 +#define XEN_PM_PX 1 +#define XEN_PM_TX 2 +#define XEN_PM_PDC 3 +/* Px sub info type */ +#define XEN_PX_PCT 1 +#define XEN_PX_PSS 2 +#define XEN_PX_PPC 4 +#define XEN_PX_PSD 8 + +struct xen_power_register { + uint32_t space_id; + uint32_t bit_width; + uint32_t bit_offset; + uint32_t access_size; + uint64_t address; +}; + +struct xen_processor_csd { + uint32_t domain; /* domain number of one dependent group */ + uint32_t coord_type; /* coordination type */ + uint32_t num; /* number of processors in same domain */ +}; +DEFINE_GUEST_HANDLE_STRUCT(xen_processor_csd); + +struct xen_processor_cx { + struct xen_power_register reg; /* GAS for Cx trigger register */ + uint8_t type; /* cstate value, c0: 0, c1: 1, ... */ + uint32_t latency; /* worst latency (ms) to enter/exit this cstate */ + uint32_t power; /* average power consumption(mW) */ + uint32_t dpcnt; /* number of dependency entries */ + GUEST_HANDLE(xen_processor_csd) dp; /* NULL if no dependency */ +}; +DEFINE_GUEST_HANDLE_STRUCT(xen_processor_cx); + +struct xen_processor_flags { + uint32_t bm_control:1; + uint32_t bm_check:1; + uint32_t has_cst:1; + uint32_t power_setup_done:1; + uint32_t bm_rld_set:1; +}; + +struct xen_processor_power { + uint32_t count; /* number of C state entries in array below */ + struct xen_processor_flags flags; /* global flags of this processor */ + GUEST_HANDLE(xen_processor_cx) states; /* supported c states */ +}; + +struct xen_pct_register { + uint8_t descriptor; + uint16_t length; + uint8_t space_id; + uint8_t bit_width; + uint8_t bit_offset; + uint8_t reserved; + uint64_t address; +}; + +struct xen_processor_px { + uint64_t core_frequency; /* megahertz */ + uint64_t power; /* milliWatts */ + uint64_t transition_latency; /* microseconds */ + uint64_t bus_master_latency; /* microseconds */ + uint64_t control; /* control value */ + uint64_t status; /* success indicator */ +}; +DEFINE_GUEST_HANDLE_STRUCT(xen_processor_px); + +struct xen_psd_package { + uint64_t num_entries; + uint64_t revision; + uint64_t domain; + uint64_t coord_type; + uint64_t num_processors; +}; + +struct xen_processor_performance { + uint32_t flags; /* flag for Px sub info type */ + uint32_t platform_limit; /* Platform limitation on freq usage */ + struct xen_pct_register control_register; + struct xen_pct_register status_register; + uint32_t state_count; /* total available performance states */ + GUEST_HANDLE(xen_processor_px) states; + struct xen_psd_package domain_info; + uint32_t shared_type; /* coordination type of this processor */ +}; +DEFINE_GUEST_HANDLE_STRUCT(xen_processor_performance); + +struct xenpf_set_processor_pminfo { + /* IN variables */ + uint32_t id; /* ACPI CPU ID */ + uint32_t type; /* {XEN_PM_CX, XEN_PM_PX} */ + union { + struct xen_processor_power power;/* Cx: _CST/_CSD */ + struct xen_processor_performance perf; /* Px: _PPC/_PCT/_PSS/_PSD */ + GUEST_HANDLE(uint32_t) pdc; + }; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_set_processor_pminfo); + +#define XENPF_get_cpuinfo 55 +struct xenpf_pcpuinfo { + /* IN */ + uint32_t xen_cpuid; + /* OUT */ + /* The maxium cpu_id that is present */ + uint32_t max_present; +#define XEN_PCPU_FLAGS_ONLINE 1 + /* Correponding xen_cpuid is not present*/ +#define XEN_PCPU_FLAGS_INVALID 2 + uint32_t flags; + uint32_t apic_id; + uint32_t acpi_id; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_pcpuinfo); + +#define XENPF_cpu_online 56 +#define XENPF_cpu_offline 57 +struct xenpf_cpu_ol { + uint32_t cpuid; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_cpu_ol); + +#define XENPF_cpu_hotadd 58 +struct xenpf_cpu_hotadd { + uint32_t apic_id; + uint32_t acpi_id; + uint32_t pxm; +}; + +#define XENPF_mem_hotadd 59 +struct xenpf_mem_hotadd { + uint64_t spfn; + uint64_t epfn; + uint32_t pxm; + uint32_t flags; +}; + +#define XENPF_core_parking 60 +struct xenpf_core_parking { + /* IN variables */ +#define XEN_CORE_PARKING_SET 1 +#define XEN_CORE_PARKING_GET 2 + uint32_t type; + /* IN variables: set cpu nums expected to be idled */ + /* OUT variables: get cpu nums actually be idled */ + uint32_t idle_nums; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_core_parking); + +#define XENPF_get_symbol 63 +struct xenpf_symdata { + /* IN/OUT variables */ + uint32_t namelen; /* size of 'name' buffer */ + + /* IN/OUT variables */ + uint32_t symnum; /* IN: Symbol to read */ + /* OUT: Next available symbol. If same as IN */ + /* then we reached the end */ + + /* OUT variables */ + GUEST_HANDLE(char) name; + uint64_t address; + char type; +}; +DEFINE_GUEST_HANDLE_STRUCT(xenpf_symdata); + +struct xen_platform_op { + uint32_t cmd; + uint32_t interface_version; /* XENPF_INTERFACE_VERSION */ + union { + struct xenpf_settime32 settime32; + struct xenpf_settime64 settime64; + struct xenpf_add_memtype add_memtype; + struct xenpf_del_memtype del_memtype; + struct xenpf_read_memtype read_memtype; + struct xenpf_microcode_update microcode; + struct xenpf_platform_quirk platform_quirk; + struct xenpf_efi_runtime_call efi_runtime_call; + struct xenpf_firmware_info firmware_info; + struct xenpf_enter_acpi_sleep enter_acpi_sleep; + struct xenpf_change_freq change_freq; + struct xenpf_getidletime getidletime; + struct xenpf_set_processor_pminfo set_pminfo; + struct xenpf_pcpuinfo pcpu_info; + struct xenpf_cpu_ol cpu_ol; + struct xenpf_cpu_hotadd cpu_add; + struct xenpf_mem_hotadd mem_add; + struct xenpf_core_parking core_parking; + struct xenpf_symdata symdata; + uint8_t pad[128]; + } u; +}; +DEFINE_GUEST_HANDLE_STRUCT(xen_platform_op_t); + +#endif /* __XEN_PUBLIC_PLATFORM_H__ */ diff --git a/include/xen/interface/sched.h b/include/xen/interface/sched.h new file mode 100644 index 00000000000..a4c4d735d78 --- /dev/null +++ b/include/xen/interface/sched.h @@ -0,0 +1,183 @@ +/****************************************************************************** + * sched.h + * + * Scheduler state interactions + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Copyright (c) 2005, Keir Fraser + */ + +#ifndef __XEN_PUBLIC_SCHED_H__ +#define __XEN_PUBLIC_SCHED_H__ + +#include + +/* + * Guest Scheduler Operations + * + * The SCHEDOP interface provides mechanisms for a guest to interact + * with the scheduler, including yield, blocking and shutting itself + * down. + */ + +/* + * The prototype for this hypercall is: + * long HYPERVISOR_sched_op(enum sched_op cmd, void *arg, ...) + * + * @cmd == SCHEDOP_??? (scheduler operation). + * @arg == Operation-specific extra argument(s), as described below. + * ... == Additional Operation-specific extra arguments, described below. + * + * Versions of Xen prior to 3.0.2 provided only the following legacy version + * of this hypercall, supporting only the commands yield, block and shutdown: + * long sched_op(int cmd, unsigned long arg) + * @cmd == SCHEDOP_??? (scheduler operation). + * @arg == 0 (SCHEDOP_yield and SCHEDOP_block) + * == SHUTDOWN_* code (SCHEDOP_shutdown) + * + * This legacy version is available to new guests as: + * long HYPERVISOR_sched_op_compat(enum sched_op cmd, unsigned long arg) + */ + +/* + * Voluntarily yield the CPU. + * @arg == NULL. + */ +#define SCHEDOP_yield 0 + +/* + * Block execution of this VCPU until an event is received for processing. + * If called with event upcalls masked, this operation will atomically + * reenable event delivery and check for pending events before blocking the + * VCPU. This avoids a "wakeup waiting" race. + * @arg == NULL. + */ +#define SCHEDOP_block 1 + +/* + * Halt execution of this domain (all VCPUs) and notify the system controller. + * @arg == pointer to sched_shutdown structure. + * + * If the sched_shutdown_t reason is SHUTDOWN_suspend then + * x86 PV guests must also set RDX (EDX for 32-bit guests) to the MFN + * of the guest's start info page. RDX/EDX is the third hypercall + * argument. + * + * In addition, which reason is SHUTDOWN_suspend this hypercall + * returns 1 if suspend was cancelled or the domain was merely + * checkpointed, and 0 if it is resuming in a new domain. + */ +#define SCHEDOP_shutdown 2 + +/* + * Poll a set of event-channel ports. Return when one or more are pending. An + * optional timeout may be specified. + * @arg == pointer to sched_poll structure. + */ +#define SCHEDOP_poll 3 + +/* + * Declare a shutdown for another domain. The main use of this function is + * in interpreting shutdown requests and reasons for fully-virtualized + * domains. A para-virtualized domain may use SCHEDOP_shutdown directly. + * @arg == pointer to sched_remote_shutdown structure. + */ +#define SCHEDOP_remote_shutdown 4 + +/* + * Latch a shutdown code, so that when the domain later shuts down it + * reports this code to the control tools. + * @arg == sched_shutdown, as for SCHEDOP_shutdown. + */ +#define SCHEDOP_shutdown_code 5 + +/* + * Setup, poke and destroy a domain watchdog timer. + * @arg == pointer to sched_watchdog structure. + * With id == 0, setup a domain watchdog timer to cause domain shutdown + * after timeout, returns watchdog id. + * With id != 0 and timeout == 0, destroy domain watchdog timer. + * With id != 0 and timeout != 0, poke watchdog timer and set new timeout. + */ +#define SCHEDOP_watchdog 6 + +/* + * Override the current vcpu affinity by pinning it to one physical cpu or + * undo this override restoring the previous affinity. + * @arg == pointer to sched_pin_override structure. + * + * A negative pcpu value will undo a previous pin override and restore the + * previous cpu affinity. + * This call is allowed for the hardware domain only and requires the cpu + * to be part of the domain's cpupool. + */ +#define SCHEDOP_pin_override 7 + +struct sched_shutdown { + unsigned int reason; /* SHUTDOWN_* => shutdown reason */ +}; +DEFINE_GUEST_HANDLE_STRUCT(sched_shutdown); + +struct sched_poll { + GUEST_HANDLE(evtchn_port_t) ports; + unsigned int nr_ports; + uint64_t timeout; +}; +DEFINE_GUEST_HANDLE_STRUCT(sched_poll); + +struct sched_remote_shutdown { + domid_t domain_id; /* Remote domain ID */ + unsigned int reason; /* SHUTDOWN_* => shutdown reason */ +}; +DEFINE_GUEST_HANDLE_STRUCT(sched_remote_shutdown); + +struct sched_watchdog { + uint32_t id; /* watchdog ID */ + uint32_t timeout; /* timeout */ +}; +DEFINE_GUEST_HANDLE_STRUCT(sched_watchdog); + +struct sched_pin_override { + int32_t pcpu; +}; +DEFINE_GUEST_HANDLE_STRUCT(sched_pin_override); + +/* + * Reason codes for SCHEDOP_shutdown. These may be interpreted by control + * software to determine the appropriate action. For the most part, Xen does + * not care about the shutdown code. + */ +#define SHUTDOWN_poweroff 0 /* Domain exited normally. Clean up and kill. */ +#define SHUTDOWN_reboot 1 /* Clean up, kill, and then restart. */ +#define SHUTDOWN_suspend 2 /* Clean up, save suspend info, kill. */ +#define SHUTDOWN_crash 3 /* Tell controller we've crashed. */ +#define SHUTDOWN_watchdog 4 /* Restart because watchdog time expired. */ + +/* + * Domain asked to perform 'soft reset' for it. The expected behavior is to + * reset internal Xen state for the domain returning it to the point where it + * was created but leaving the domain's memory contents and vCPU contexts + * intact. This will allow the domain to start over and set up all Xen specific + * interfaces again. + */ +#define SHUTDOWN_soft_reset 5 +#define SHUTDOWN_MAX 5 /* Maximum valid shutdown reason. */ + +#endif /* __XEN_PUBLIC_SCHED_H__ */ diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h new file mode 100644 index 00000000000..8bfb242f433 --- /dev/null +++ b/include/xen/interface/xen.h @@ -0,0 +1,782 @@ +/****************************************************************************** + * xen.h + * + * Guest OS interface to Xen. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Copyright (c) 2004, K A Fraser + */ + +#ifndef __XEN_PUBLIC_XEN_H__ +#define __XEN_PUBLIC_XEN_H__ + +#include + +/* + * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS). + */ + +/* + * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5. + * EAX = return value + * (argument registers may be clobbered on return) + * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6. + * RAX = return value + * (argument registers not clobbered on return; RCX, R11 are) + */ +#define __HYPERVISOR_set_trap_table 0 +#define __HYPERVISOR_mmu_update 1 +#define __HYPERVISOR_set_gdt 2 +#define __HYPERVISOR_stack_switch 3 +#define __HYPERVISOR_set_callbacks 4 +#define __HYPERVISOR_fpu_taskswitch 5 +#define __HYPERVISOR_sched_op_compat 6 +#define __HYPERVISOR_platform_op 7 +#define __HYPERVISOR_set_debugreg 8 +#define __HYPERVISOR_get_debugreg 9 +#define __HYPERVISOR_update_descriptor 10 +#define __HYPERVISOR_memory_op 12 +#define __HYPERVISOR_multicall 13 +#define __HYPERVISOR_update_va_mapping 14 +#define __HYPERVISOR_set_timer_op 15 +#define __HYPERVISOR_event_channel_op_compat 16 +#define __HYPERVISOR_xen_version 17 +#define __HYPERVISOR_console_io 18 +#define __HYPERVISOR_physdev_op_compat 19 +#define __HYPERVISOR_grant_table_op 20 +#define __HYPERVISOR_vm_assist 21 +#define __HYPERVISOR_update_va_mapping_otherdomain 22 +#define __HYPERVISOR_iret 23 /* x86 only */ +#define __HYPERVISOR_vcpu_op 24 +#define __HYPERVISOR_set_segment_base 25 /* x86/64 only */ +#define __HYPERVISOR_mmuext_op 26 +#define __HYPERVISOR_xsm_op 27 +#define __HYPERVISOR_nmi_op 28 +#define __HYPERVISOR_sched_op 29 +#define __HYPERVISOR_callback_op 30 +#define __HYPERVISOR_xenoprof_op 31 +#define __HYPERVISOR_event_channel_op 32 +#define __HYPERVISOR_physdev_op 33 +#define __HYPERVISOR_hvm_op 34 +#define __HYPERVISOR_sysctl 35 +#define __HYPERVISOR_domctl 36 +#define __HYPERVISOR_kexec_op 37 +#define __HYPERVISOR_tmem_op 38 +#define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */ +#define __HYPERVISOR_xenpmu_op 40 +#define __HYPERVISOR_dm_op 41 + +/* Architecture-specific hypercall definitions. */ +#define __HYPERVISOR_arch_0 48 +#define __HYPERVISOR_arch_1 49 +#define __HYPERVISOR_arch_2 50 +#define __HYPERVISOR_arch_3 51 +#define __HYPERVISOR_arch_4 52 +#define __HYPERVISOR_arch_5 53 +#define __HYPERVISOR_arch_6 54 +#define __HYPERVISOR_arch_7 55 + +/* + * VIRTUAL INTERRUPTS + * + * Virtual interrupts that a guest OS may receive from Xen. + * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a + * global VIRQ. The former can be bound once per VCPU and cannot be re-bound. + * The latter can be allocated only once per guest: they must initially be + * allocated to VCPU0 but can subsequently be re-bound. + */ +#define VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */ +#define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */ +#define VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */ +#define VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */ +#define VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */ +#define VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */ +#define VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */ +#define VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */ +#define VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */ +#define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occured */ +#define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient */ +#define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */ +#define VIRQ_XENPMU 13 /* PMC interrupt */ + +/* Architecture-specific VIRQ definitions. */ +#define VIRQ_ARCH_0 16 +#define VIRQ_ARCH_1 17 +#define VIRQ_ARCH_2 18 +#define VIRQ_ARCH_3 19 +#define VIRQ_ARCH_4 20 +#define VIRQ_ARCH_5 21 +#define VIRQ_ARCH_6 22 +#define VIRQ_ARCH_7 23 + +#define NR_VIRQS 24 + +/* + * enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[], + * unsigned count, unsigned *done_out, + * unsigned foreigndom) + * @reqs is an array of mmu_update_t structures ((ptr, val) pairs). + * @count is the length of the above array. + * @pdone is an output parameter indicating number of completed operations + * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this + * hypercall invocation. Can be DOMID_SELF. + * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced + * in this hypercall invocation. The value of this field + * (x) encodes the PFD as follows: + * x == 0 => PFD == DOMID_SELF + * x != 0 => PFD == x - 1 + * + * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command. + * ------------- + * ptr[1:0] == MMU_NORMAL_PT_UPDATE: + * Updates an entry in a page table belonging to PFD. If updating an L1 table, + * and the new table entry is valid/present, the mapped frame must belong to + * FD. If attempting to map an I/O page then the caller assumes the privilege + * of the FD. + * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller. + * FD == DOMID_XEN: Map restricted areas of Xen's heap space. + * ptr[:2] -- Machine address of the page-table entry to modify. + * val -- Value to write. + * + * There also certain implicit requirements when using this hypercall. The + * pages that make up a pagetable must be mapped read-only in the guest. + * This prevents uncontrolled guest updates to the pagetable. Xen strictly + * enforces this, and will disallow any pagetable update which will end up + * mapping pagetable page RW, and will disallow using any writable page as a + * pagetable. In practice it means that when constructing a page table for a + * process, thread, etc, we MUST be very dilligient in following these rules: + * 1). Start with top-level page (PGD or in Xen language: L4). Fill out + * the entries. + * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD + * or L2). + * 3). Start filling out the PTE table (L1) with the PTE entries. Once + * done, make sure to set each of those entries to RO (so writeable bit + * is unset). Once that has been completed, set the PMD (L2) for this + * PTE table as RO. + * 4). When completed with all of the PMD (L2) entries, and all of them have + * been set to RO, make sure to set RO the PUD (L3). Do the same + * operation on PGD (L4) pagetable entries that have a PUD (L3) entry. + * 5). Now before you can use those pages (so setting the cr3), you MUST also + * pin them so that the hypervisor can verify the entries. This is done + * via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame + * number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op( + * MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be + * issued. + * For 32-bit guests, the L4 is not used (as there is less pagetables), so + * instead use L3. + * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE + * hypercall. Also if so desired the OS can also try to write to the PTE + * and be trapped by the hypervisor (as the PTE entry is RO). + * + * To deallocate the pages, the operations are the reverse of the steps + * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the + * pagetable MUST not be in use (meaning that the cr3 is not set to it). + * + * ptr[1:0] == MMU_MACHPHYS_UPDATE: + * Updates an entry in the machine->pseudo-physical mapping table. + * ptr[:2] -- Machine address within the frame whose mapping to modify. + * The frame must belong to the FD, if one is specified. + * val -- Value to write into the mapping entry. + * + * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD: + * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed + * with those in @val. + * + * @val is usually the machine frame number along with some attributes. + * The attributes by default follow the architecture defined bits. Meaning that + * if this is a X86_64 machine and four page table layout is used, the layout + * of val is: + * - 63 if set means No execute (NX) + * - 46-13 the machine frame number + * - 12 available for guest + * - 11 available for guest + * - 10 available for guest + * - 9 available for guest + * - 8 global + * - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages) + * - 6 dirty + * - 5 accessed + * - 4 page cached disabled + * - 3 page write through + * - 2 userspace accessible + * - 1 writeable + * - 0 present + * + * The one bits that does not fit with the default layout is the PAGE_PSE + * also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the + * HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB + * (or 2MB) instead of using the PAGE_PSE bit. + * + * The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen + * using it as the Page Attribute Table (PAT) bit - for details on it please + * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of + * pages instead of using MTRRs. + * + * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits): + * PAT4 PAT0 + * +-----+-----+----+----+----+-----+----+----+ + * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux + * +-----+-----+----+----+----+-----+----+----+ + * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) + * +-----+-----+----+----+----+-----+----+----+ + * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen + * +-----+-----+----+----+----+-----+----+----+ + * + * The lookup of this index table translates to looking up + * Bit 7, Bit 4, and Bit 3 of val entry: + * + * PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3). + * + * If all bits are off, then we are using PAT0. If bit 3 turned on, + * then we are using PAT1, if bit 3 and bit 4, then PAT2.. + * + * As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means + * that if a guest that follows Linux's PAT setup and would like to set Write + * Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is + * set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the + * caching as: + * + * WB = none (so PAT0) + * WC = PWT (bit 3 on) + * UC = PWT | PCD (bit 3 and 4 are on). + * + * To make it work with Xen, it needs to translate the WC bit as so: + * + * PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3 + * + * And to translate back it would: + * + * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7. + */ +#define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ +#define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ +#define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */ +#define MMU_PT_UPDATE_NO_TRANSLATE 3 /* checked '*ptr = val'. ptr is MA. */ + +/* + * MMU EXTENDED OPERATIONS + * + * enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[], + * unsigned int count, + * unsigned int *pdone, + * unsigned int foreigndom) + */ +/* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures. + * A foreigndom (FD) can be specified (or DOMID_SELF for none). + * Where the FD has some effect, it is described below. + * + * cmd: MMUEXT_(UN)PIN_*_TABLE + * mfn: Machine frame number to be (un)pinned as a p.t. page. + * The frame must belong to the FD, if one is specified. + * + * cmd: MMUEXT_NEW_BASEPTR + * mfn: Machine frame number of new page-table base to install in MMU. + * + * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only] + * mfn: Machine frame number of new page-table base to install in MMU + * when in user space. + * + * cmd: MMUEXT_TLB_FLUSH_LOCAL + * No additional arguments. Flushes local TLB. + * + * cmd: MMUEXT_INVLPG_LOCAL + * linear_addr: Linear address to be flushed from the local TLB. + * + * cmd: MMUEXT_TLB_FLUSH_MULTI + * vcpumask: Pointer to bitmap of VCPUs to be flushed. + * + * cmd: MMUEXT_INVLPG_MULTI + * linear_addr: Linear address to be flushed. + * vcpumask: Pointer to bitmap of VCPUs to be flushed. + * + * cmd: MMUEXT_TLB_FLUSH_ALL + * No additional arguments. Flushes all VCPUs' TLBs. + * + * cmd: MMUEXT_INVLPG_ALL + * linear_addr: Linear address to be flushed from all VCPUs' TLBs. + * + * cmd: MMUEXT_FLUSH_CACHE + * No additional arguments. Writes back and flushes cache contents. + * + * cmd: MMUEXT_FLUSH_CACHE_GLOBAL + * No additional arguments. Writes back and flushes cache contents + * on all CPUs in the system. + * + * cmd: MMUEXT_SET_LDT + * linear_addr: Linear address of LDT base (NB. must be page-aligned). + * nr_ents: Number of entries in LDT. + * + * cmd: MMUEXT_CLEAR_PAGE + * mfn: Machine frame number to be cleared. + * + * cmd: MMUEXT_COPY_PAGE + * mfn: Machine frame number of the destination page. + * src_mfn: Machine frame number of the source page. + * + * cmd: MMUEXT_[UN]MARK_SUPER + * mfn: Machine frame number of head of superpage to be [un]marked. + */ +#define MMUEXT_PIN_L1_TABLE 0 +#define MMUEXT_PIN_L2_TABLE 1 +#define MMUEXT_PIN_L3_TABLE 2 +#define MMUEXT_PIN_L4_TABLE 3 +#define MMUEXT_UNPIN_TABLE 4 +#define MMUEXT_NEW_BASEPTR 5 +#define MMUEXT_TLB_FLUSH_LOCAL 6 +#define MMUEXT_INVLPG_LOCAL 7 +#define MMUEXT_TLB_FLUSH_MULTI 8 +#define MMUEXT_INVLPG_MULTI 9 +#define MMUEXT_TLB_FLUSH_ALL 10 +#define MMUEXT_INVLPG_ALL 11 +#define MMUEXT_FLUSH_CACHE 12 +#define MMUEXT_SET_LDT 13 +#define MMUEXT_NEW_USER_BASEPTR 15 +#define MMUEXT_CLEAR_PAGE 16 +#define MMUEXT_COPY_PAGE 17 +#define MMUEXT_FLUSH_CACHE_GLOBAL 18 +#define MMUEXT_MARK_SUPER 19 +#define MMUEXT_UNMARK_SUPER 20 + +#ifndef __ASSEMBLY__ +struct mmuext_op { + unsigned int cmd; + union { + /* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR + * CLEAR_PAGE, COPY_PAGE, [UN]MARK_SUPER */ + xen_pfn_t mfn; + /* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */ + unsigned long linear_addr; + } arg1; + union { + /* SET_LDT */ + unsigned int nr_ents; + /* TLB_FLUSH_MULTI, INVLPG_MULTI */ + void *vcpumask; + /* COPY_PAGE */ + xen_pfn_t src_mfn; + } arg2; +}; +DEFINE_GUEST_HANDLE_STRUCT(mmuext_op); +#endif + +/* These are passed as 'flags' to update_va_mapping. They can be ORed. */ +/* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */ +/* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */ +#define UVMF_NONE (0UL<<0) /* No flushing at all. */ +#define UVMF_TLB_FLUSH (1UL<<0) /* Flush entire TLB(s). */ +#define UVMF_INVLPG (2UL<<0) /* Flush only one entry. */ +#define UVMF_FLUSHTYPE_MASK (3UL<<0) +#define UVMF_MULTI (0UL<<2) /* Flush subset of TLBs. */ +#define UVMF_LOCAL (0UL<<2) /* Flush local TLB. */ +#define UVMF_ALL (1UL<<2) /* Flush all TLBs. */ + +/* + * Commands to HYPERVISOR_console_io(). + */ +#define CONSOLEIO_write 0 +#define CONSOLEIO_read 1 + +/* + * Commands to HYPERVISOR_vm_assist(). + */ +#define VMASST_CMD_enable 0 +#define VMASST_CMD_disable 1 + +/* x86/32 guests: simulate full 4GB segment limits. */ +#define VMASST_TYPE_4gb_segments 0 + +/* x86/32 guests: trap (vector 15) whenever above vmassist is used. */ +#define VMASST_TYPE_4gb_segments_notify 1 + +/* + * x86 guests: support writes to bottom-level PTEs. + * NB1. Page-directory entries cannot be written. + * NB2. Guest must continue to remove all writable mappings of PTEs. + */ +#define VMASST_TYPE_writable_pagetables 2 + +/* x86/PAE guests: support PDPTs above 4GB. */ +#define VMASST_TYPE_pae_extended_cr3 3 + +/* + * x86 guests: Sane behaviour for virtual iopl + * - virtual iopl updated from do_iret() hypercalls. + * - virtual iopl reported in bounce frames. + * - guest kernels assumed to be level 0 for the purpose of iopl checks. + */ +#define VMASST_TYPE_architectural_iopl 4 + +/* + * All guests: activate update indicator in vcpu_runstate_info + * Enable setting the XEN_RUNSTATE_UPDATE flag in guest memory mapped + * vcpu_runstate_info during updates of the runstate information. + */ +#define VMASST_TYPE_runstate_update_flag 5 + +#define MAX_VMASST_TYPE 5 + +#ifndef __ASSEMBLY__ + +typedef uint16_t domid_t; + +/* Domain ids >= DOMID_FIRST_RESERVED cannot be used for ordinary domains. */ +#define DOMID_FIRST_RESERVED (0x7FF0U) + +/* DOMID_SELF is used in certain contexts to refer to oneself. */ +#define DOMID_SELF (0x7FF0U) + +/* + * DOMID_IO is used to restrict page-table updates to mapping I/O memory. + * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO + * is useful to ensure that no mappings to the OS's own heap are accidentally + * installed. (e.g., in Linux this could cause havoc as reference counts + * aren't adjusted on the I/O-mapping code path). + * This only makes sense in MMUEXT_SET_FOREIGNDOM, but in that context can + * be specified by any calling domain. + */ +#define DOMID_IO (0x7FF1U) + +/* + * DOMID_XEN is used to allow privileged domains to map restricted parts of + * Xen's heap space (e.g., the machine_to_phys table). + * This only makes sense in MMUEXT_SET_FOREIGNDOM, and is only permitted if + * the caller is privileged. + */ +#define DOMID_XEN (0x7FF2U) + +/* DOMID_COW is used as the owner of sharable pages */ +#define DOMID_COW (0x7FF3U) + +/* DOMID_INVALID is used to identify pages with unknown owner. */ +#define DOMID_INVALID (0x7FF4U) + +/* Idle domain. */ +#define DOMID_IDLE (0x7FFFU) + +/* + * Send an array of these to HYPERVISOR_mmu_update(). + * NB. The fields are natural pointer/address size for this architecture. + */ +struct mmu_update { + uint64_t ptr; /* Machine address of PTE. */ + uint64_t val; /* New contents of PTE. */ +}; +DEFINE_GUEST_HANDLE_STRUCT(mmu_update); + +/* + * Send an array of these to HYPERVISOR_multicall(). + * NB. The fields are logically the natural register size for this + * architecture. In cases where xen_ulong_t is larger than this then + * any unused bits in the upper portion must be zero. + */ +struct multicall_entry { + xen_ulong_t op; + xen_long_t result; + xen_ulong_t args[6]; +}; +DEFINE_GUEST_HANDLE_STRUCT(multicall_entry); + +struct vcpu_time_info { + /* + * Updates to the following values are preceded and followed + * by an increment of 'version'. The guest can therefore + * detect updates by looking for changes to 'version'. If the + * least-significant bit of the version number is set then an + * update is in progress and the guest must wait to read a + * consistent set of values. The correct way to interact with + * the version number is similar to Linux's seqlock: see the + * implementations of read_seqbegin/read_seqretry. + */ + uint32_t version; + uint32_t pad0; + uint64_t tsc_timestamp; /* TSC at last update of time vals. */ + uint64_t system_time; /* Time, in nanosecs, since boot. */ + /* + * Current system time: + * system_time + ((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul + * CPU frequency (Hz): + * ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift + */ + uint32_t tsc_to_system_mul; + int8_t tsc_shift; + int8_t pad1[3]; +}; /* 32 bytes */ + +struct vcpu_info { + /* + * 'evtchn_upcall_pending' is written non-zero by Xen to indicate + * a pending notification for a particular VCPU. It is then cleared + * by the guest OS /before/ checking for pending work, thus avoiding + * a set-and-check race. Note that the mask is only accessed by Xen + * on the CPU that is currently hosting the VCPU. This means that the + * pending and mask flags can be updated by the guest without special + * synchronisation (i.e., no need for the x86 LOCK prefix). + * This may seem suboptimal because if the pending flag is set by + * a different CPU then an IPI may be scheduled even when the mask + * is set. However, note: + * 1. The task of 'interrupt holdoff' is covered by the per-event- + * channel mask bits. A 'noisy' event that is continually being + * triggered can be masked at source at this very precise + * granularity. + * 2. The main purpose of the per-VCPU mask is therefore to restrict + * reentrant execution: whether for concurrency control, or to + * prevent unbounded stack usage. Whatever the purpose, we expect + * that the mask will be asserted only for short periods at a time, + * and so the likelihood of a 'spurious' IPI is suitably small. + * The mask is read before making an event upcall to the guest: a + * non-zero mask therefore guarantees that the VCPU will not receive + * an upcall activation. The mask is cleared when the VCPU requests + * to block: this avoids wakeup-waiting races. + */ + uint8_t evtchn_upcall_pending; + uint8_t evtchn_upcall_mask; + xen_ulong_t evtchn_pending_sel; + struct arch_vcpu_info arch; + struct pvclock_vcpu_time_info time; +}; /* 64 bytes (x86) */ + +/* + * Xen/kernel shared data -- pointer provided in start_info. + * NB. We expect that this struct is smaller than a page. + */ +struct shared_info { + struct vcpu_info vcpu_info[MAX_VIRT_CPUS]; + + /* + * A domain can create "event channels" on which it can send and receive + * asynchronous event notifications. There are three classes of event that + * are delivered by this mechanism: + * 1. Bi-directional inter- and intra-domain connections. Domains must + * arrange out-of-band to set up a connection (usually by allocating + * an unbound 'listener' port and avertising that via a storage service + * such as xenstore). + * 2. Physical interrupts. A domain with suitable hardware-access + * privileges can bind an event-channel port to a physical interrupt + * source. + * 3. Virtual interrupts ('events'). A domain can bind an event-channel + * port to a virtual interrupt source, such as the virtual-timer + * device or the emergency console. + * + * Event channels are addressed by a "port index". Each channel is + * associated with two bits of information: + * 1. PENDING -- notifies the domain that there is a pending notification + * to be processed. This bit is cleared by the guest. + * 2. MASK -- if this bit is clear then a 0->1 transition of PENDING + * will cause an asynchronous upcall to be scheduled. This bit is only + * updated by the guest. It is read-only within Xen. If a channel + * becomes pending while the channel is masked then the 'edge' is lost + * (i.e., when the channel is unmasked, the guest must manually handle + * pending notifications as no upcall will be scheduled by Xen). + * + * To expedite scanning of pending notifications, any 0->1 pending + * transition on an unmasked channel causes a corresponding bit in a + * per-vcpu selector word to be set. Each bit in the selector covers a + * 'C long' in the PENDING bitfield array. + */ + xen_ulong_t evtchn_pending[sizeof(xen_ulong_t) * 8]; + xen_ulong_t evtchn_mask[sizeof(xen_ulong_t) * 8]; + + /* + * Wallclock time: updated only by control software. Guests should base + * their gettimeofday() syscall on this wallclock-base value. + */ + struct pvclock_wall_clock wc; + + struct arch_shared_info arch; + +}; + +/* + * Start-of-day memory layout + * + * 1. The domain is started within contiguous virtual-memory region. + * 2. The contiguous region begins and ends on an aligned 4MB boundary. + * 3. This the order of bootstrap elements in the initial virtual region: + * a. relocated kernel image + * b. initial ram disk [mod_start, mod_len] + * (may be omitted) + * c. list of allocated page frames [mfn_list, nr_pages] + * (unless relocated due to XEN_ELFNOTE_INIT_P2M) + * d. start_info_t structure [register ESI (x86)] + * in case of dom0 this page contains the console info, too + * e. unless dom0: xenstore ring page + * f. unless dom0: console ring page + * g. bootstrap page tables [pt_base, CR3 (x86)] + * h. bootstrap stack [register ESP (x86)] + * 4. Bootstrap elements are packed together, but each is 4kB-aligned. + * 5. The list of page frames forms a contiguous 'pseudo-physical' memory + * layout for the domain. In particular, the bootstrap virtual-memory + * region is a 1:1 mapping to the first section of the pseudo-physical map. + * 6. All bootstrap elements are mapped read-writable for the guest OS. The + * only exception is the bootstrap page table, which is mapped read-only. + * 7. There is guaranteed to be at least 512kB padding after the final + * bootstrap element. If necessary, the bootstrap virtual region is + * extended by an extra 4MB to ensure this. + */ + +#define MAX_GUEST_CMDLINE 1024 +struct start_info { + /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME. */ + char magic[32]; /* "xen--". */ + unsigned long nr_pages; /* Total pages allocated to this domain. */ + unsigned long shared_info; /* MACHINE address of shared info struct. */ + uint32_t flags; /* SIF_xxx flags. */ + xen_pfn_t store_mfn; /* MACHINE page number of shared page. */ + uint32_t store_evtchn; /* Event channel for store communication. */ + union { + struct { + xen_pfn_t mfn; /* MACHINE page number of console page. */ + uint32_t evtchn; /* Event channel for console page. */ + } domU; + struct { + uint32_t info_off; /* Offset of console_info struct. */ + uint32_t info_size; /* Size of console_info struct from start.*/ + } dom0; + } console; + /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME). */ + unsigned long pt_base; /* VIRTUAL address of page directory. */ + unsigned long nr_pt_frames; /* Number of bootstrap p.t. frames. */ + unsigned long mfn_list; /* VIRTUAL address of page-frame list. */ + unsigned long mod_start; /* VIRTUAL address of pre-loaded module. */ + unsigned long mod_len; /* Size (bytes) of pre-loaded module. */ + int8_t cmd_line[MAX_GUEST_CMDLINE]; + /* The pfn range here covers both page table and p->m table frames. */ + unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table. */ + unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table. */ +}; + +/* These flags are passed in the 'flags' field of start_info_t. */ +#define SIF_PRIVILEGED (1<<0) /* Is the domain privileged? */ +#define SIF_INITDOMAIN (1<<1) /* Is this the initial control domain? */ +#define SIF_MULTIBOOT_MOD (1<<2) /* Is mod_start a multiboot module? */ +#define SIF_MOD_START_PFN (1<<3) /* Is mod_start a PFN? */ +#define SIF_VIRT_P2M_4TOOLS (1<<4) /* Do Xen tools understand a virt. mapped */ + /* P->M making the 3 level tree obsolete? */ +#define SIF_PM_MASK (0xFF<<8) /* reserve 1 byte for xen-pm options */ + +/* + * A multiboot module is a package containing modules very similar to a + * multiboot module array. The only differences are: + * - the array of module descriptors is by convention simply at the beginning + * of the multiboot module, + * - addresses in the module descriptors are based on the beginning of the + * multiboot module, + * - the number of modules is determined by a termination descriptor that has + * mod_start == 0. + * + * This permits to both build it statically and reference it in a configuration + * file, and let the PV guest easily rebase the addresses to virtual addresses + * and at the same time count the number of modules. + */ +struct xen_multiboot_mod_list { + /* Address of first byte of the module */ + uint32_t mod_start; + /* Address of last byte of the module (inclusive) */ + uint32_t mod_end; + /* Address of zero-terminated command line */ + uint32_t cmdline; + /* Unused, must be zero */ + uint32_t pad; +}; +/* + * The console structure in start_info.console.dom0 + * + * This structure includes a variety of information required to + * have a working VGA/VESA console. + */ +struct dom0_vga_console_info { + uint8_t video_type; +#define XEN_VGATYPE_TEXT_MODE_3 0x03 +#define XEN_VGATYPE_VESA_LFB 0x23 +#define XEN_VGATYPE_EFI_LFB 0x70 + + union { + struct { + /* Font height, in pixels. */ + uint16_t font_height; + /* Cursor location (column, row). */ + uint16_t cursor_x, cursor_y; + /* Number of rows and columns (dimensions in characters). */ + uint16_t rows, columns; + } text_mode_3; + + struct { + /* Width and height, in pixels. */ + uint16_t width, height; + /* Bytes per scan line. */ + uint16_t bytes_per_line; + /* Bits per pixel. */ + uint16_t bits_per_pixel; + /* LFB physical address, and size (in units of 64kB). */ + uint32_t lfb_base; + uint32_t lfb_size; + /* RGB mask offsets and sizes, as defined by VBE 1.2+ */ + uint8_t red_pos, red_size; + uint8_t green_pos, green_size; + uint8_t blue_pos, blue_size; + uint8_t rsvd_pos, rsvd_size; + + /* VESA capabilities (offset 0xa, VESA command 0x4f00). */ + uint32_t gbl_caps; + /* Mode attributes (offset 0x0, VESA command 0x4f01). */ + uint16_t mode_attrs; + } vesa_lfb; + } u; +}; + +typedef uint64_t cpumap_t; + +typedef uint8_t xen_domain_handle_t[16]; + +/* Turn a plain number into a C unsigned long constant. */ +#define __mk_unsigned_long(x) x ## UL +#define mk_unsigned_long(x) __mk_unsigned_long(x) + +#define TMEM_SPEC_VERSION 1 + +struct tmem_op { + uint32_t cmd; + int32_t pool_id; + union { + struct { /* for cmd == TMEM_NEW_POOL */ + uint64_t uuid[2]; + uint32_t flags; + } new; + struct { + uint64_t oid[3]; + uint32_t index; + uint32_t tmem_offset; + uint32_t pfn_offset; + uint32_t len; + GUEST_HANDLE(void) gmfn; /* guest machine page frame */ + } gen; + } u; +}; + +DEFINE_GUEST_HANDLE(u64); + +#else /* __ASSEMBLY__ */ + +/* In assembly code we cannot use C numeric constant suffixes. */ +#define mk_unsigned_long(x) x + +#endif /* !__ASSEMBLY__ */ + +#endif /* __XEN_PUBLIC_XEN_H__ */ diff --git a/lib/Kconfig b/lib/Kconfig index 4fd41c4282a..064afeaafbe 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -1,5 +1,15 @@ menu "Library routines" +config AVB_SUPPORT + bool "Enable Android AVB lib support" + +config AVB_ATX + bool "Enable AVB_ATX support" + depends on AVB_SUPPORT + +config APPEND_BOOTARGS + bool "Append bootargs support" + config BCH bool "Enable Software based BCH ECC" help @@ -115,6 +125,14 @@ config RBTREE config BITREVERSE bool "Bit reverse library from Linux" +config DUAL_BOOTLOADER + bool "Enable dual bootloader support" + help + Enable A/B bootloader select in SPL. + +config AT_AUTHENTICATE_UNLOCK + bool "Enable authenticate unlock for Android Things devices" + source lib/dhry/Kconfig menu "Security support" diff --git a/lib/Makefile b/lib/Makefile index 0db41c19f37..3685d757667 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_FIT) += libfdt/ obj-$(CONFIG_OF_LIVE) += of_live.o obj-$(CONFIG_CMD_DHRYSTONE) += dhry/ obj-$(CONFIG_ARCH_AT91) += at91/ - +obj-$(CONFIG_IMX_TRUSTY_OS) += trusty/ql-tipc/ obj-$(CONFIG_AES) += aes.o obj-y += charset.o obj-$(CONFIG_USB_TTY) += circbuf.o @@ -49,6 +49,7 @@ endif obj-$(CONFIG_RSA) += rsa/ obj-$(CONFIG_SHA1) += sha1.o obj-$(CONFIG_SHA256) += sha256.o +obj-$(CONFIG_AVB_SUPPORT) += avb/ obj-$(CONFIG_$(SPL_)ZLIB) += zlib/ obj-$(CONFIG_$(SPL_)GZIP) += gunzip.o diff --git a/lib/avb/Makefile b/lib/avb/Makefile new file mode 100644 index 00000000000..6d9bc7ed4f9 --- /dev/null +++ b/lib/avb/Makefile @@ -0,0 +1,19 @@ +subdir-ccflags-y += -I./lib/avb \ + -D_FILE_OFFSET_BITS=64 \ + -D_POSIX_C_SOURCE=199309L \ + -Wa,--noexecstack \ + -Wall \ + -Wextra \ + -Wformat=2 \ + -Wno-type-limits \ + -Wno-psabi \ + -Wno-unused-parameter \ + -ffunction-sections \ + -std=gnu99 + +ifndef CONFIG_SPL_BUILD +obj-y += libavb_ab/ +obj-$(CONFIG_AVB_ATX) += libavb_atx/ +endif +obj-y += libavb/ +obj-y += fsl/ diff --git a/lib/avb/fsl/Makefile b/lib/avb/fsl/Makefile new file mode 100644 index 00000000000..9c2fb44fc08 --- /dev/null +++ b/lib/avb/fsl/Makefile @@ -0,0 +1,10 @@ +ifndef CONFIG_SPL_BUILD +obj-y += fsl_avb.o +obj-y += fsl_bootctl.o +obj-y += fsl_avb_sysdeps_uboot.o +endif + +obj-y += fsl_avbkey.o +obj-y += utils.o +obj-y += fsl_avb_ab_flow.o +obj-$(CONFIG_AVB_ATX) += fsl_atx_attributes.o diff --git a/lib/avb/fsl/debug.h b/lib/avb/fsl/debug.h new file mode 100644 index 00000000000..c1165ec1ec1 --- /dev/null +++ b/lib/avb/fsl/debug.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AVB_DEBUG_H__ +#define __AVB_DEBUG_H__ + +#ifdef AVB_VVDEBUG +#define AVB_VDEBUG +#define VVDEBUG(format, ...) printf(" %s: "format, __func__, ##__VA_ARGS__) +#else +#define VVDEBUG(format, ...) +#endif + +#ifdef AVB_VDEBUG +#define AVB_DEBUG +#define VDEBUG(format, ...) printf(" %s: "format, __func__, ##__VA_ARGS__) +#else +#define VDEBUG(format, ...) +#endif + +#ifdef AVB_DEBUG +#define DEBUGAVB(format, ...) printf(" %s: "format, __func__, ##__VA_ARGS__) +#else +#define DEBUGAVB(format, ...) +#endif + +#define ERR(format, ...) printf("%s: "format, __func__, ##__VA_ARGS__) + +#define HEXDUMP_COLS 16 +#define HEXDUMP_WIDTH 1 + +#endif diff --git a/lib/avb/fsl/fsl_atx_attributes.c b/lib/avb/fsl/fsl_atx_attributes.c new file mode 100644 index 00000000000..2297140dd17 --- /dev/null +++ b/lib/avb/fsl/fsl_atx_attributes.c @@ -0,0 +1,145 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* This product_id is generated from + * extern/avb/test/data/atx_product_id.bin */ +unsigned char fsl_atx_product_id[16] = { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; +/* This product_root_public_key is generated form + * extern/avb/test/data/testkey_atx_prk.pem */ +unsigned char fsl_product_root_public_key[1032] = { + 0x00,0x00,0x10,0x00,0x9f,0x35,0xef,0x65, + 0xc3,0x29,0x4c,0x23,0x16,0x10,0xac,0x32, + 0xc1,0x3c,0xd5,0xc5,0xab,0xa1,0xd9,0xe7, + 0x13,0x3f,0x7e,0xd1,0xe6,0x61,0x5d,0xa3, + 0xa1,0x60,0xda,0x57,0x4b,0xb2,0xe6,0x0f, + 0xe1,0x50,0xbf,0x47,0xff,0x09,0xaf,0xcd, + 0x49,0x2d,0x82,0x33,0x76,0xa1,0xfe,0x28, + 0x5f,0x89,0x62,0xb3,0xc0,0xf1,0x11,0xaf, + 0x15,0x09,0x27,0xdb,0xeb,0x06,0x01,0xa2, + 0xf8,0xb7,0xd7,0x9c,0xe4,0x88,0x3a,0x86, + 0x05,0x02,0x20,0x69,0xb2,0x36,0x4c,0x3e, + 0x25,0x03,0xed,0xfc,0x0c,0x6b,0x1b,0x0a, + 0x04,0x9c,0xce,0x7f,0x83,0x82,0x60,0xd9, + 0x52,0x7e,0xc4,0x35,0x7b,0x1c,0xe6,0x64, + 0x9c,0x17,0xec,0x81,0xe7,0x9c,0x0c,0x8b, + 0x4b,0x7e,0x48,0xbe,0x00,0x98,0xa8,0x20, + 0x10,0x4c,0x9b,0xd1,0x16,0x5b,0x25,0xe9, + 0x4e,0x61,0xda,0x7c,0x63,0x80,0x8f,0xa4, + 0xac,0x74,0xee,0xa8,0x06,0xac,0x26,0xd5, + 0x71,0x6f,0xaa,0x73,0x20,0x9c,0x7f,0xcd, + 0x73,0xd4,0xa9,0xa0,0x7e,0x5a,0xb5,0x61, + 0xb0,0x88,0xb0,0xdd,0xdb,0x6b,0x79,0xd1, + 0x5a,0x9e,0x54,0x49,0x55,0xc6,0x89,0x76, + 0x7a,0xc6,0x78,0x99,0xdc,0xc9,0x00,0x5d, + 0x20,0xf5,0xfc,0x8f,0x39,0x46,0xf3,0x02, + 0x96,0x0d,0x9b,0xfb,0xbc,0xd5,0xcf,0x5a, + 0x4f,0xc4,0xb8,0x0b,0xd0,0xf3,0x19,0x3c, + 0x74,0x04,0xd5,0x94,0x2c,0x19,0x15,0x64, + 0xbf,0x53,0x67,0x97,0x7b,0x9e,0xc6,0xe0, + 0xfb,0x29,0x5b,0x90,0xad,0x04,0x8a,0xd8, + 0x5b,0xdf,0x69,0x09,0xe4,0xa5,0xe9,0xd9, + 0x0f,0xc4,0xff,0xae,0xb7,0x44,0x12,0xae, + 0xad,0x03,0x97,0xb8,0xda,0xd7,0x60,0x37, + 0x15,0xf2,0xb9,0xdb,0x10,0xf6,0xe2,0x26, + 0x48,0x7e,0x3e,0x3e,0xc3,0x67,0xd3,0xa6, + 0x02,0xf7,0xbc,0x60,0xed,0x45,0xdf,0x37, + 0xef,0xf9,0xea,0x97,0x5f,0x37,0xb4,0xeb, + 0xb4,0x91,0x6c,0x39,0x4d,0xed,0x52,0x15, + 0x39,0x47,0x59,0x62,0xde,0x32,0x55,0xe1, + 0xd4,0x15,0x58,0x7d,0x52,0x41,0x12,0x78, + 0xee,0x9f,0x0d,0xc8,0x5e,0x34,0x91,0xf9, + 0xe7,0x4c,0x1e,0xe7,0x2f,0x90,0x7f,0xbb, + 0xf8,0x99,0x3e,0xc9,0x79,0xab,0x01,0xdb, + 0x24,0x39,0xe3,0xb4,0xc9,0x52,0x73,0xdb, + 0x65,0x42,0xa5,0x2e,0x43,0x56,0xa0,0x33, + 0x8c,0x1a,0xb7,0xa1,0xed,0x5c,0xd0,0x14, + 0x93,0x8d,0x23,0x78,0x93,0xcb,0x3a,0x03, + 0x1f,0xbb,0xc6,0x7b,0xcd,0x51,0x4e,0xaa, + 0x14,0x01,0xe9,0x03,0x27,0x13,0xe2,0xb2, + 0xf8,0x36,0xc6,0xe3,0xc3,0x7f,0xb5,0x74, + 0x20,0x5e,0x17,0xaa,0x25,0x07,0x9b,0x60, + 0xda,0x83,0x98,0xb5,0x55,0xae,0x1b,0x7a, + 0xc1,0x1f,0x49,0x72,0xe2,0xcb,0x6a,0x11, + 0x77,0xdf,0x3f,0xc0,0x9f,0x8f,0x33,0xc7, + 0x10,0x17,0x8c,0xfc,0xd5,0xb7,0x5f,0x5e, + 0xb2,0xe3,0x7b,0x2e,0xdc,0xc7,0x34,0xdb, + 0x31,0xb0,0xdc,0x5d,0x14,0x98,0xb6,0x1a, + 0x2a,0xd4,0xb4,0x04,0x2c,0xf0,0x68,0x1c, + 0x91,0x60,0x28,0xa5,0x3b,0x01,0x98,0xb6, + 0x1e,0x6e,0xaa,0x35,0x89,0xc7,0x94,0xaa, + 0x9e,0xf0,0x11,0x52,0x0f,0x28,0xa1,0x3d, + 0xd3,0x17,0xb5,0x08,0xd8,0x7a,0x41,0xf9, + 0x07,0xe2,0x87,0x36,0xcd,0x86,0x3e,0x79, + 0x99,0x73,0x50,0x21,0x30,0x00,0xd2,0xf3, + 0x88,0x60,0x32,0x59,0x58,0x2f,0x55,0x93, + 0x86,0x56,0x9a,0x96,0xb9,0xf8,0xbf,0x24, + 0xc4,0xba,0xea,0xa4,0x73,0xb0,0x0c,0xa6, + 0xdb,0x09,0x2d,0x0a,0x36,0x3f,0x80,0xe6, + 0x85,0x7a,0xf3,0x01,0x90,0x3a,0xc6,0xee, + 0x2d,0xa8,0xce,0xb4,0x3f,0x3a,0xa6,0xa3, + 0xaf,0xb9,0x21,0xef,0x40,0x6f,0xf4,0x7f, + 0x78,0x25,0x55,0x39,0x53,0x67,0x53,0x56, + 0x8d,0x81,0xaf,0x63,0x97,0x68,0x86,0x75, + 0x66,0x14,0x1e,0xa6,0x63,0x1e,0x02,0xd0, + 0x41,0xd8,0x78,0x75,0x0d,0x76,0x77,0xfa, + 0x9c,0xc5,0xcc,0x54,0x06,0x25,0x53,0x95, + 0xeb,0x4b,0x7c,0xb4,0xc8,0xbb,0x5d,0x6b, + 0x6e,0xf0,0xd7,0x8d,0x3f,0xdf,0x93,0x4c, + 0x30,0x5b,0x02,0xf5,0x0e,0x49,0x87,0x60, + 0x5f,0x19,0x06,0x24,0x3d,0x5d,0x97,0x37, + 0x61,0xef,0x3e,0x0b,0x9e,0x85,0x1c,0x1a, + 0xa6,0x53,0x91,0xd2,0x2c,0x18,0x7c,0x8f, + 0x5b,0x4a,0xd5,0xdd,0xd9,0x8a,0xc3,0x92, + 0x19,0x54,0x39,0xde,0x33,0xa1,0xe1,0x37, + 0x60,0x3c,0x3b,0x3b,0xc5,0xed,0x1b,0xef, + 0x28,0xf5,0xdf,0x44,0x91,0xa3,0x1e,0x69, + 0x6a,0x35,0x85,0x6e,0x26,0x46,0x22,0x4d, + 0x87,0x92,0x44,0x6b,0x96,0xdb,0x75,0xfe, + 0x76,0x03,0x60,0xf7,0xfd,0x90,0x55,0x7d, + 0x6e,0xd7,0xaa,0x44,0x05,0xc7,0x23,0x37, + 0x12,0xa8,0xd4,0xb2,0x2b,0xed,0x41,0x5f, + 0x23,0x38,0x7c,0x16,0xe6,0x16,0xd3,0x10, + 0x19,0x12,0xcc,0x8b,0x6e,0xcd,0xd6,0xa6, + 0x39,0x8a,0x1b,0x24,0x3f,0x4d,0x6f,0xa6, + 0x00,0x7c,0xa0,0xa1,0x4a,0xfd,0xcd,0x68, + 0x50,0x76,0xc8,0x68,0x9d,0xeb,0xdf,0x24, + 0x39,0xaf,0x77,0xb2,0xb6,0xaf,0xb6,0x34, + 0x61,0x37,0x6a,0xfd,0xc7,0x6d,0x02,0x9f, + 0x29,0xd5,0x45,0xf4,0x89,0xd8,0x8c,0x5c, + 0xd3,0x31,0xa0,0x58,0x19,0x54,0x33,0x46, + 0x92,0xbc,0x1e,0x4b,0x14,0xac,0x73,0xa5, + 0x09,0x9f,0xb6,0x2b,0x2b,0x73,0x6b,0x83, + 0x86,0x13,0x6e,0x03,0xf7,0xe0,0x7d,0x81, + 0x47,0x18,0x08,0xea,0x09,0x10,0x24,0x61, + 0x6d,0x09,0x1d,0xb8,0x8e,0xba,0x04,0x4d, + 0xcc,0xe6,0xff,0x28,0x27,0x86,0x38,0x01, + 0x86,0xbe,0xf0,0x5b,0xf8,0x1a,0xd6,0xde, + 0xbe,0xf9,0x3b,0x76,0x3f,0x85,0x82,0x22, + 0x92,0x4b,0xe0,0x76,0x15,0xb2,0x57,0x5a, + 0xb0,0x64,0xde,0xce,0x93,0xb8,0x9f,0x25, + 0x53,0x8c,0x5e,0xdf,0x29,0x4e,0x50,0x69, + 0xfb,0x7e,0x33,0xcb,0x0e,0x28,0x01,0x6c, + 0xab,0xfa,0xd8,0x88,0x02,0xbc,0xf2,0xb1, + 0x0e,0x2f,0x6d,0x1c,0x8d,0xe4,0x11,0x23, + 0xcc,0x67,0x94,0x7b,0xf7,0x8a,0xf3,0x68, + 0x52,0xe4,0x82,0x25,0x86,0xc6,0x72,0x19, + 0x77,0x80,0x28,0xe3,0x86,0xc8,0x8a,0xea, + 0x3d,0x54,0x2f,0x0b,0x64,0x0a,0xc5,0x12, + 0x8c,0xb2,0x07,0x72,0x1b,0x09,0x9f,0x32, + 0xbd,0xa3,0xb0,0x0c,0x95,0xc8,0x4d,0xe5, + 0xd7,0x20,0xdb,0xf8,0x34,0x2a,0x9d,0x91, + 0x58,0x38,0x7a,0x9c,0xe0,0xa3,0x0f,0x40, + 0x9d,0xff,0xeb,0x4b,0xe2,0x16,0x94,0x32, + 0xce,0xe8,0x52,0x75,0x49,0xf4,0x71,0x13, + 0xbc,0x59,0x7d,0x9a,0xe8,0x60,0x29,0x58, + 0x1a,0x14,0x94,0xe6,0x37,0x23,0xad,0xfe, + 0x0b,0xf0,0x63,0x60,0x4f,0x5d,0x10,0x91, + 0xf2,0x50,0x8e,0x0b,0x4a,0x47,0xc9,0x0c, + 0x1f,0xdc,0x94,0x75,0x25,0x52,0x99,0xfc +}; diff --git a/lib/avb/fsl/fsl_atx_attributes.h b/lib/avb/fsl/fsl_atx_attributes.h new file mode 100644 index 00000000000..e6e43835a1e --- /dev/null +++ b/lib/avb/fsl/fsl_atx_attributes.h @@ -0,0 +1,18 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_ATX_ATTRIBUTES_H__ +#define __FSL_ATX_ATTRIBUTES_H__ + +#define fsl_version 1 +/* This product_id is generated from + * extern/avb/test/data/atx_product_id.bin */ +extern unsigned char fsl_atx_product_id[17]; +/* This product_root_public_key is generated form + * extern/avb/test/data/testkey_atx_prk.pem */ +extern unsigned char fsl_product_root_public_key[1032]; + +#endif /* __FSL_ATX_ATTRIBUTES_H__ */ diff --git a/lib/avb/fsl/fsl_avb.c b/lib/avb/fsl/fsl_avb.c new file mode 100644 index 00000000000..ff92654e8b1 --- /dev/null +++ b/lib/avb/fsl/fsl_avb.c @@ -0,0 +1,861 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include +#include "../../../drivers/usb/gadget/fastboot_lock_unlock.h" + +#include +#include "fsl_avbkey.h" +#include "utils.h" +#include "debug.h" +#include "trusty/avb.h" +#if !defined(CONFIG_IMX_TRUSTY_OS) +#include "fsl_public_key.h" +#endif +#include "fsl_atx_attributes.h" + +#define FSL_AVB_DEV "mmc" +#define AVB_MAX_BUFFER_LENGTH 2048 + +static struct blk_desc *fs_dev_desc = NULL; +static struct blk_desc *get_mmc_desc(void) { + extern int mmc_get_env_dev(void); + int dev_no = mmc_get_env_dev(); + return blk_get_dev(FSL_AVB_DEV, dev_no); +} + + /* Reads |num_bytes| from offset |offset| from partition with name + * |partition| (NUL-terminated UTF-8 string). If |offset| is + * negative, its absolute value should be interpreted as the number + * of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * |offset| is outside the partition, and AVB_IO_RESULT_ERROR_IO if + * there was an I/O error from the underlying I/O subsystem. If the + * operation succeeds as requested AVB_IO_RESULT_OK is returned and + * the data is available in |buffer|. + * + * The only time partial I/O may occur is if reading beyond the end + * of the partition. In this case the value returned in + * |out_num_read| may be smaller than |num_bytes|. + */ + AvbIOResult fsl_read_from_partition(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + void* buffer, size_t* out_num_read) +{ + struct fastboot_ptentry *pte; + unsigned char *bdata; + unsigned char *out_buf = (unsigned char *)buffer; + unsigned long blksz; + unsigned long s, cnt; + size_t num_read = 0; + lbaint_t part_start, part_end, bs, be; + margin_pos_t margin; + + AvbIOResult ret; + + DEBUGAVB("[%s]: offset=%ld, num_bytes=%zu\n", partition, (long)offset, num_bytes); + + assert(buffer != NULL && out_num_read != NULL); + + if ((fs_dev_desc = get_mmc_desc()) == NULL) { + ERR("mmc device not found\n"); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + ERR("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + blksz = fs_dev_desc->blksz; + part_start = pte->start; + part_end = pte->start + pte->length - 1; + VDEBUG("blksz: %ld, part_end: %ld, part_start: %ld:\n", + blksz, part_end, part_start); + + if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, true)) + return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION; + + bs = (lbaint_t)margin.blk_start; + be = (lbaint_t)margin.blk_end; + s = margin.start; + + // alloc a blksz mem + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) + return AVB_IO_RESULT_ERROR_OOM; + + // one block a time + while (bs <= be) { + memset(bdata, 0, blksz); + if (blk_dread(fs_dev_desc, bs, 1, bdata) != 1) { + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + cnt = blksz - s; + if (num_read + cnt > num_bytes) + cnt = num_bytes - num_read; + VDEBUG("cur: bs=%ld, start=%ld, cnt=%ld bdata=0x%08x\n", + bs, s, cnt, bdata); + memcpy(out_buf, bdata + s, cnt); + bs++; + num_read += cnt; + out_buf += cnt; + s = 0; + } + *out_num_read = num_read; + ret = AVB_IO_RESULT_OK; +#ifdef AVB_VVDEBUG + printf("\nnum_read=%zu", num_read); + printf("\n----dump---\n"); + print_buffer(0, buffer, HEXDUMP_WIDTH, num_read, 0); + printf("--- end ---\n"); +#endif + +fail: + free(bdata); + return ret; +} + +/* multi block read version of read_from_partition */ + AvbIOResult fsl_read_from_partition_multi(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + void* buffer, size_t* out_num_read) +{ + struct fastboot_ptentry *pte; + unsigned char *bdata; + unsigned char *out_buf = (unsigned char *)buffer; + unsigned char *dst, *dst64 = NULL; + unsigned long blksz; + unsigned long s, cnt; + size_t num_read = 0; + lbaint_t part_start, part_end, bs, be, bm, blk_num; + margin_pos_t margin; + + AvbIOResult ret; + + DEBUGAVB("[%s]: offset=%ld, num_bytes=%zu\n", partition, (long)offset, num_bytes); + + assert(buffer != NULL && out_num_read != NULL); + + if ((fs_dev_desc = get_mmc_desc()) == NULL) { + ERR("mmc device not found\n"); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + ERR("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + blksz = fs_dev_desc->blksz; + part_start = pte->start; + part_end = pte->start + pte->length - 1; + VDEBUG("blksz: %ld, part_end: %ld, part_start: %ld:\n", + blksz, part_end, part_start); + + if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, true)) + return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION; + + bs = (lbaint_t)margin.blk_start; + be = (lbaint_t)margin.blk_end; + s = margin.start; + bm = margin.multi; + + // alloc a blksz mem + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) + return AVB_IO_RESULT_ERROR_OOM; + + // support multi blk read + while (bs <= be) { + if (!s && bm > 1) { + dst = out_buf; + dst64 = PTR_ALIGN(out_buf, 64); //for mmc blk read alignment + VDEBUG("cur: dst=0x%08x, dst64=0x%08x\n", dst, dst64); + if (dst64 != dst) { + dst = dst64; + bm--; + } + blk_num = bm; + cnt = bm * blksz; + bm = 0; //no more multi blk + } else { + blk_num = 1; + cnt = blksz - s; + if (num_read + cnt > num_bytes) + cnt = num_bytes - num_read; + dst = bdata; + } + VDEBUG("cur: bs=%ld, num=%ld, start=%ld, cnt=%ld dst=0x%08x\n", + bs, blk_num, s, cnt, dst); + if (blk_dread(fs_dev_desc, bs, blk_num, dst) != blk_num) { + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + + if (dst == bdata) + memcpy(out_buf, bdata + s, cnt); + else if (dst == dst64) + memcpy(out_buf, dst, cnt); //internal copy + + s = 0; + bs += blk_num; + num_read += cnt; + out_buf += cnt; +#ifdef AVB_VVDEBUG + printf("\nnum_read=%ld", cnt); + printf("\n----dump---\n"); + print_buffer(0, buffer, HEXDUMP_WIDTH, cnt, 0); + printf("--- end ---\n"); +#endif + } + *out_num_read = num_read; + ret = AVB_IO_RESULT_OK; +#ifdef AVB_VVDEBUG + printf("\nnum_read=%zu", num_read); + printf("\n----dump---\n"); + print_buffer(0, buffer, HEXDUMP_WIDTH, num_read, 0); + printf("--- end ---\n"); +#endif + +fail: + free(bdata); + return ret; +} + + /* Writes |num_bytes| from |bffer| at offset |offset| to partition + * with name |partition| (NUL-terminated UTF-8 string). If |offset| + * is negative, its absolute value should be interpreted as the + * number of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * byterange goes outside the partition, and AVB_IO_RESULT_ERROR_IO + * if there was an I/O error from the underlying I/O subsystem. If + * the operation succeeds as requested AVB_IO_RESULT_OK is + * returned. + * + * This function never does any partial I/O, it either transfers all + * of the requested bytes or returns an error. + */ + AvbIOResult fsl_write_to_partition(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + const void* buffer) +{ + struct fastboot_ptentry *pte; + unsigned char *bdata; + unsigned char *in_buf = (unsigned char *)buffer; + unsigned long blksz; + unsigned long s, cnt; + size_t num_write = 0; + lbaint_t part_start, part_end, bs; + margin_pos_t margin; + + AvbIOResult ret; + + DEBUGAVB("[%s]: offset=%ld, num_bytes=%zu\n", partition, (long)offset, num_bytes); + + assert(buffer != NULL); + + if ((fs_dev_desc = get_mmc_desc()) == NULL) { + ERR("mmc device not found\n"); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + ERR("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + blksz = fs_dev_desc->blksz; + part_start = pte->start; + part_end = pte->start + pte->length - 1; + VDEBUG("blksz: %ld, part_end: %ld, part_start: %ld:\n", + blksz, part_end, part_start); + + if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, false)) + return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION; + + bs = (lbaint_t)margin.blk_start; + s = margin.start; + + // alloc a blksz mem + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) + return AVB_IO_RESULT_ERROR_OOM; + + while (num_write < num_bytes) { + memset(bdata, 0, blksz); + cnt = blksz - s; + if (num_write + cnt > num_bytes) + cnt = num_bytes - num_write; + if (!s || cnt != blksz) { //read blk first + if (blk_dread(fs_dev_desc, bs, 1, bdata) != 1) { + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + } + memcpy(bdata + s, in_buf, cnt); //change data + VDEBUG("cur: bs=%ld, start=%ld, cnt=%ld bdata=0x%08x\n", + bs, s, cnt, bdata); + if (blk_dwrite(fs_dev_desc, bs, 1, bdata) != 1) { + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + bs++; + num_write += cnt; + in_buf += cnt; + if (s != 0) + s = 0; + } + ret = AVB_IO_RESULT_OK; + +fail: + free(bdata); + return ret; +} + +/* Reads A/B metadata from persistent storage. Returned data is + * properly byteswapped. Returns AVB_IO_RESULT_OK on success, error + * code otherwise. + * + * If the data read is invalid (e.g. wrong magic or CRC checksum + * failure), the metadata shoule be reset using avb_ab_data_init() + * and then written to persistent storage. + * + * Implementations will typically want to use avb_ab_data_read() + * here to use the 'misc' partition for persistent storage. + */ +AvbIOResult fsl_read_ab_metadata(AvbABOps* ab_ops, struct AvbABData* data) +{ + return avb_ab_data_read(ab_ops, data); +} + +/* Writes A/B metadata to persistent storage. This will byteswap and + * update the CRC as needed. Returns AVB_IO_RESULT_OK on success, + * error code otherwise. + * + * Implementations will typically want to use avb_ab_data_write() + * here to use the 'misc' partition for persistent storage. + */ +AvbIOResult fsl_write_ab_metadata(AvbABOps* ab_ops, const struct AvbABData* data) +{ + return avb_ab_data_write(ab_ops, data); +} + +/* Gets whether the device is unlocked. The value is returned in + * |out_is_unlocked| (true if unlocked, false otherwise). Returns + * AVB_IO_RESULT_OK if the state was retrieved, otherwise an error + * code. + */ +AvbIOResult fsl_read_is_device_unlocked(AvbOps* ops, bool* out_is_unlocked) { + + FbLockState status; + + assert(out_is_unlocked != NULL); + *out_is_unlocked = false; + + status = fastboot_get_lock_stat(); + if (status != FASTBOOT_LOCK_ERROR) { + if (status == FASTBOOT_LOCK) + *out_is_unlocked = false; + else + *out_is_unlocked = true; + } else + return AVB_IO_RESULT_ERROR_IO; + + DEBUGAVB("is_unlocked=%d\n", *out_is_unlocked); + return AVB_IO_RESULT_OK; +} + +/* Gets the unique partition GUID for a partition with name in + * |partition| (NUL-terminated UTF-8 string). The GUID is copied as + * a string into |guid_buf| of size |guid_buf_size| and will be NUL + * terminated. The string must be lower-case and properly + * hyphenated. For example: + * + * 527c1c6d-6361-4593-8842-3c78fcd39219 + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_unique_guid_for_partition(AvbOps* ops, + const char* partition, + char* guid_buf, + size_t guid_buf_size) { + assert(guid_buf != NULL); +#ifdef CONFIG_PARTITION_UUIDS + struct fastboot_ptentry *pte; + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + ERR("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + strncpy(guid_buf, (const char *)pte->uuid, guid_buf_size); + guid_buf[guid_buf_size - 1] = '\0'; + DEBUGAVB("[%s]: GUID=%s\n", partition, guid_buf); + return AVB_IO_RESULT_OK; +#else + return AVB_IO_RESULT_ERROR_IO; +#endif + +} +/* Gets the size of a partition with the name in |partition| + * (NUL-terminated UTF-8 string). Returns the value in + * |out_size_num_bytes|. + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_size_of_partition(AvbOps* ops, + const char* partition, + uint64_t* out_size_num_bytes) +{ + struct fastboot_ptentry *pte; + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + ERR("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + *out_size_num_bytes = (uint64_t)(pte->length * 512); + return AVB_IO_RESULT_OK; +} + +#ifdef CONFIG_AVB_ATX +/* Reads permanent |attributes| data. There are no restrictions on where this + * data is stored. On success, returns AVB_IO_RESULT_OK and populates + * |attributes|. + */ +AvbIOResult fsl_read_permanent_attributes( + AvbAtxOps* atx_ops, AvbAtxPermanentAttributes* attributes) { +#ifdef CONFIG_IMX_TRUSTY_OS + if (!trusty_read_permanent_attributes((uint8_t *)attributes, + sizeof(AvbAtxPermanentAttributes))) { + return AVB_IO_RESULT_OK; + } + ERR("No perm-attr fused. Will use hard code one.\n"); +#endif /* CONFIG_IMX_TRUSTY_OS */ + + /* use hard code permanent attributes due to limited fuse and RPMB */ + attributes->version = fsl_version; + memcpy(attributes->product_root_public_key, fsl_product_root_public_key, + sizeof(fsl_product_root_public_key)); + memcpy(attributes->product_id, fsl_atx_product_id, + sizeof(fsl_atx_product_id)); + + return AVB_IO_RESULT_OK; +} + +/* Reads a |hash| of permanent attributes. This hash MUST be retrieved from a + * permanently read-only location (e.g. fuses) when a device is LOCKED. On + * success, returned AVB_IO_RESULT_OK and populates |hash|. + */ +AvbIOResult fsl_read_permanent_attributes_hash( + AvbAtxOps* atx_ops, uint8_t hash[AVB_SHA256_DIGEST_SIZE]) { +#ifdef CONFIG_ARM64 + /* calculate sha256(permanent attributes) */ + if (permanent_attributes_sha256_hash(hash) != RESULT_OK) { + return AVB_IO_RESULT_ERROR_IO; + } else { + return AVB_IO_RESULT_OK; + } +#else + uint8_t sha256_hash_buf[AVB_SHA256_DIGEST_SIZE]; + uint32_t sha256_hash_fuse[ATX_FUSE_BANK_NUM]; + + /* read first 112 bits of sha256(permanent attributes) from fuse */ + if (fsl_fuse_read(sha256_hash_fuse, ATX_FUSE_BANK_NUM, + PERMANENT_ATTRIBUTE_HASH_OFFSET)) { + printf("ERROR - read permanent attributes hash from " + "fuse error\n"); + return AVB_IO_RESULT_ERROR_IO; + } + /* only take the lower 2 bytes of last bank */ + sha256_hash_fuse[ATX_FUSE_BANK_NUM - 1] &= ATX_FUSE_BANK_MASK; + + /* calculate sha256(permanent attributes) */ + if (permanent_attributes_sha256_hash(sha256_hash_buf) != RESULT_OK) { + return AVB_IO_RESULT_ERROR_IO; + } + /* check if the sha256(permanent attributes) hash match the calculated one, + * if not match, just return all zeros hash. + */ + if (memcmp(sha256_hash_fuse, sha256_hash_buf, ATX_HASH_LENGTH)) { + printf("ERROR - sha256(permanent attributes) does not match\n"); + memset(hash, 0, AVB_SHA256_DIGEST_SIZE); + } else { + memcpy(hash, sha256_hash_buf, AVB_SHA256_DIGEST_SIZE); + } + + return AVB_IO_RESULT_OK; +#endif /* CONFIG_ARM64 */ +} + + /* Generates |num_bytes| random bytes and stores them in |output|, + * which must point to a buffer large enough to store the bytes. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_random(AvbAtxOps* atx_ops, + size_t num_bytes, + uint8_t* output) +{ + uint32_t num = 0; + uint32_t i; + + if (output == NULL) { + ERR("Output buffer is NULL!\n"); + return AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE; + } + + /* set the seed as device boot time. */ + srand((uint32_t)get_timer(0)); + for (i = 0; i < num_bytes; i++) { + num = rand() % 256; + output[i] = (uint8_t)num; + } + + return AVB_IO_RESULT_OK; +} +/* Provides the key version of a key used during verification. This may be + * useful for managing the minimum key version. + */ +void fsl_set_key_version(AvbAtxOps* atx_ops, + size_t rollback_index_location, + uint64_t key_version) { + kblb_hdr_t hdr; + kblb_tag_t *rbk; + uint64_t *plain_idx = NULL; + struct mmc *mmc_dev; + static const uint32_t kTypeMask = 0xF000; + + DEBUGAVB("[rpmb] write to rollback slot: (%zu, %" PRIu64 ")\n", + rollback_index_location, key_version); + + assert(atx_ops != NULL); + + if ((mmc_dev = get_mmc()) == NULL) { + ERR("err get mmc device\n"); + } + /* read the kblb header */ + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { + ERR("read RPMB error\n"); + } + + if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) { + ERR("magic not match\n"); + } + + /* rollback index for Android Things key versions */ + rbk = &hdr.atx_rbk_tags[rollback_index_location & ~kTypeMask]; + + plain_idx = malloc(rbk->len); + if (plain_idx == NULL) + printf("\nError! allocate memory fail!\n"); + memset(plain_idx, 0, rbk->len); + *plain_idx = key_version; + + /* write rollback_index keyblob */ + if (rpmb_write(mmc_dev, (uint8_t *)plain_idx, rbk->len, rbk->offset) != + 0) { + ERR("write rollback index error\n"); + goto fail; + } +fail: + if (plain_idx != NULL) + free(plain_idx); +} +#endif /* CONFIG_AVB_ATX */ + +#ifdef AVB_RPMB +/* Checks if the given public key used to sign the 'vbmeta' + * partition is trusted. Boot loaders typically compare this with + * embedded key material generated with 'avbtool + * extract_public_key'. + * + * If AVB_IO_RESULT_OK is returned then |out_is_trusted| is set - + * true if trusted or false if untrusted. + */ +AvbIOResult fsl_validate_vbmeta_public_key_rpmb(AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted) { + AvbIOResult ret; + assert(ops != NULL && out_is_trusted != NULL); + *out_is_trusted = false; + +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) + uint8_t public_key_buf[AVB_MAX_BUFFER_LENGTH]; + if (trusty_read_vbmeta_public_key(public_key_buf, + public_key_length) != 0) { + ERR("Read public key error\n"); + /* We're not going to return error code here because it will + * abort the following avb verify process even we allow the + * verification error. Return AVB_IO_RESULT_OK and keep the + * 'out_is_trusted' as false, avb will handle the error + * depends on the 'allow_verification_error' flag. + */ + return AVB_IO_RESULT_OK; + } + + if (memcmp(public_key_buf, public_key_data, public_key_length)) { +#else + /* match given public key */ + if (memcmp(fsl_public_key, public_key_data, public_key_length)) { +#endif + ERR("public key not match\n"); + return AVB_IO_RESULT_OK; + } + + *out_is_trusted = true; + ret = AVB_IO_RESULT_OK; + + return ret; +} + +/* Sets the rollback index corresponding to the slot given by + * |rollback_index_slot| to |rollback_index|. Returns + * AVB_IO_RESULT_OK if the rollback index was set, otherwise an + * error code. + * + * A device may have a limited amount of rollback index slots (say, + * one or four) so may error out if |rollback_index_slot| exceeds + * this number. + */ +AvbIOResult fsl_write_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t rollback_index) { + AvbIOResult ret; +#ifdef CONFIG_IMX_TRUSTY_OS + if (trusty_write_rollback_index(rollback_index_slot, rollback_index)) { + ERR("write rollback from Trusty error!\n"); +#ifndef CONFIG_AVB_ATX + /* Read/write rollback index from rpmb will fail if the rpmb + * key hasn't been set, return AVB_IO_RESULT_OK in this case. + */ + if (!rpmbkey_is_set()) + ret = AVB_IO_RESULT_OK; + else +#endif + ret = AVB_IO_RESULT_ERROR_IO; + } else { + ret = AVB_IO_RESULT_OK; + } + return ret; +#else + kblb_hdr_t hdr; + kblb_tag_t *rbk; + uint64_t *plain_idx = NULL; + struct mmc *mmc_dev; +#ifdef CONFIG_AVB_ATX + static const uint32_t kTypeMask = 0xF000; + static const unsigned int kTypeShift = 12; +#endif + + DEBUGAVB("[rpmb] write to rollback slot: (%zu, %" PRIu64 ")\n", + rollback_index_slot, rollback_index); + + assert(ops != NULL); + /* check if the rollback index location exceed the limit */ +#ifdef CONFIG_AVB_ATX + if ((rollback_index_slot & ~kTypeMask) >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) +#else + if (rollback_index_slot >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) +#endif /* CONFIG_AVB_ATX */ + return AVB_IO_RESULT_ERROR_IO; + + if ((mmc_dev = get_mmc()) == NULL) { + ERR("err get mmc device\n"); + return AVB_IO_RESULT_ERROR_IO; + } + /* read the kblb header */ + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { + ERR("read RPMB error\n"); + return AVB_IO_RESULT_ERROR_IO; + } + + if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) { + ERR("magic not match\n"); + return AVB_IO_RESULT_ERROR_IO; + } + /* choose rollback index type */ +#ifdef CONFIG_AVB_ATX + if ((rollback_index_slot & kTypeMask) >> kTypeShift) { + /* rollback index for Android Things key versions */ + rbk = &hdr.atx_rbk_tags[rollback_index_slot & ~kTypeMask]; + } else { + /* rollback index for vbmeta */ + rbk = &hdr.rbk_tags[rollback_index_slot & ~kTypeMask]; + } +#else + rbk = &hdr.rbk_tags[rollback_index_slot]; +#endif /* CONFIG_AVB_ATX */ + plain_idx = malloc(rbk->len); + if (plain_idx == NULL) + return AVB_IO_RESULT_ERROR_OOM; + memset(plain_idx, 0, rbk->len); + *plain_idx = rollback_index; + + /* write rollback_index keyblob */ + if (rpmb_write(mmc_dev, (uint8_t *)plain_idx, rbk->len, rbk->offset) != + 0) { + ERR("write rollback index error\n"); + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + ret = AVB_IO_RESULT_OK; +fail: + if (plain_idx != NULL) + free(plain_idx); + return ret; +#endif /* CONFIG_IMX_TRUSTY_OS */ +} + +/* Gets the rollback index corresponding to the slot given by + * |rollback_index_slot|. The value is returned in + * |out_rollback_index|. Returns AVB_IO_RESULT_OK if the rollback + * index was retrieved, otherwise an error code. + * + * A device may have a limited amount of rollback index slots (say, + * one or four) so may error out if |rollback_index_slot| exceeds + * this number. + */ +AvbIOResult fsl_read_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t* out_rollback_index) { + AvbIOResult ret; +#ifdef CONFIG_IMX_TRUSTY_OS + if (trusty_read_rollback_index(rollback_index_slot, out_rollback_index)) { + ERR("read rollback from Trusty error!\n"); +#ifndef CONFIG_AVB_ATX + if (!rpmbkey_is_set()) { + *out_rollback_index = 0; + ret = AVB_IO_RESULT_OK; + } else +#endif + ret = AVB_IO_RESULT_ERROR_IO; + } else { + ret = AVB_IO_RESULT_OK; + } + return ret; +#else + kblb_hdr_t hdr; + kblb_tag_t *rbk; + uint64_t *extract_idx = NULL; + struct mmc *mmc_dev; +#ifdef CONFIG_AVB_ATX + static const uint32_t kTypeMask = 0xF000; + static const unsigned int kTypeShift = 12; +#endif + + assert(ops != NULL && out_rollback_index != NULL); + *out_rollback_index = ~0; + + DEBUGAVB("[rpmb] read rollback slot: %zu\n", rollback_index_slot); + + /* check if the rollback index location exceed the limit */ +#ifdef CONFIG_AVB_ATX + if ((rollback_index_slot & ~kTypeMask) >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) +#else + if (rollback_index_slot >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) +#endif + return AVB_IO_RESULT_ERROR_IO; + + if ((mmc_dev = get_mmc()) == NULL) { + ERR("err get mmc device\n"); + return AVB_IO_RESULT_ERROR_IO; + } + /* read the kblb header */ + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { + ERR("read RPMB error\n"); + return AVB_IO_RESULT_ERROR_IO; + } + + if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) { + ERR("magic not match\n"); + return AVB_IO_RESULT_ERROR_IO; + } + /* choose rollback index type */ +#ifdef CONFIG_AVB_ATX + if ((rollback_index_slot & kTypeMask) >> kTypeShift) { + /* rollback index for Android Things key versions */ + rbk = &hdr.atx_rbk_tags[rollback_index_slot & ~kTypeMask]; + } else { + /* rollback index for vbmeta */ + rbk = &hdr.rbk_tags[rollback_index_slot & ~kTypeMask]; + } +#else + rbk = &hdr.rbk_tags[rollback_index_slot]; +#endif /* CONFIG_AVB_ATX */ + extract_idx = malloc(rbk->len); + if (extract_idx == NULL) + return AVB_IO_RESULT_ERROR_OOM; + + /* read rollback_index keyblob */ + if (rpmb_read(mmc_dev, (uint8_t *)extract_idx, rbk->len, rbk->offset) != 0) { + ERR("read rollback index error\n"); + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + +#ifdef AVB_VVDEBUG + printf("\n----idx dump: ---\n"); + print_buffer(0, extract_idx, HEXDUMP_WIDTH, rbk->len, 0); + printf("--- end ---\n"); +#endif + *out_rollback_index = *extract_idx; + DEBUGAVB("rollback_index = %" PRIu64 "\n", *out_rollback_index); + ret = AVB_IO_RESULT_OK; +fail: + if (extract_idx != NULL) + free(extract_idx); + return ret; +#endif /* CONFIG_IMX_TRUSTY_OS */ +} +#else /* AVB_RPMB */ +/* + * In no security enhanced ARM64, we cannot protect public key. + * So that we choose to trust the key from vbmeta image + */ +AvbIOResult fsl_validate_vbmeta_public_key_rpmb(AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted) { + *out_is_trusted = true; + return AVB_IO_RESULT_OK; +} + +/* In no security enhanced ARM64, rollback index has no protection so no use it */ +AvbIOResult fsl_write_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t rollback_index) { + return AVB_IO_RESULT_OK; + +} +AvbIOResult fsl_read_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t* out_rollback_index) { + *out_rollback_index = 0; + return AVB_IO_RESULT_OK; +} +#endif /* AVB_RPMB */ diff --git a/lib/avb/fsl/fsl_avb_ab_flow.c b/lib/avb/fsl/fsl_avb_ab_flow.c new file mode 100644 index 00000000000..0dc6850434d --- /dev/null +++ b/lib/avb/fsl/fsl_avb_ab_flow.c @@ -0,0 +1,1105 @@ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include "utils.h" +#include "fsl_caam.h" +#include "fsl_avbkey.h" + +#if defined(CONFIG_DUAL_BOOTLOADER) || !defined(CONFIG_SPL_BUILD) +static const char* slot_suffixes[2] = {"_a", "_b"}; + +/* This is a copy of slot_set_unbootable() form + * external/avb/libavb_ab/avb_ab_flow.c. + */ +void fsl_slot_set_unbootable(AvbABSlotData* slot) { + slot->priority = 0; + slot->tries_remaining = 0; + slot->successful_boot = 0; +} + +/* Ensure all unbootable and/or illegal states are marked as the + * canonical 'unbootable' state, e.g. priority=0, tries_remaining=0, + * and successful_boot=0. This is a copy of slot_normalize from + * external/avb/libavb_ab/avb_ab_flow.c. + */ +void fsl_slot_normalize(AvbABSlotData* slot) { + if (slot->priority > 0) { +#if defined(CONFIG_DUAL_BOOTLOADER) && !defined(CONFIG_SPL_BUILD) + if ((slot->tries_remaining == 0) + && (!slot->successful_boot) && (slot->bootloader_verified != 1)) { + /* We've exhausted all tries -> unbootable. */ + fsl_slot_set_unbootable(slot); + } +#else + if ((slot->tries_remaining == 0) && (!slot->successful_boot)) { + /* We've exhausted all tries -> unbootable. */ + fsl_slot_set_unbootable(slot); + } +#endif + if ((slot->tries_remaining > 0) && (slot->successful_boot)) { + /* Illegal state - avb_ab_mark_slot_successful() will clear + * tries_remaining when setting successful_boot. + */ + fsl_slot_set_unbootable(slot); + } + } else { + fsl_slot_set_unbootable(slot); + } +} + +/* This is a copy of slot_is_bootable() from + * externel/avb/libavb_ab/avb_ab_flow.c. + */ +bool fsl_slot_is_bootable(AvbABSlotData* slot) { + return (slot->priority > 0) && + (slot->successful_boot || (slot->tries_remaining > 0)); +} +#endif /* CONFIG_DUAL_BOOTLOADER || !CONFIG_SPL_BUILD */ + +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_SPL_BUILD) + +#define FSL_AB_METADATA_MISC_PARTITION_OFFSET 2048 +#define PARTITION_NAME_LEN 13 +#define PARTITION_MISC "misc" +#define PARTITION_BOOTLOADER "bootloader" + +extern int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value); +extern int mmc_load_image_parse_container(struct spl_image_info *spl_image, + struct mmc *mmc, unsigned long sector); + +/* Pre-declaration of h_spl_load_read(), see detail implementation in + * common/spl/spl_mmc.c. + */ +ulong h_spl_load_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf); + +void fsl_avb_ab_data_update_crc_and_byteswap(const AvbABData* src, + AvbABData* dest) { + memcpy(dest, src, sizeof(AvbABData)); + dest->crc32 = cpu_to_be32( + avb_crc32((const uint8_t*)dest, + sizeof(AvbABData) - sizeof(uint32_t))); +} + +void fsl_avb_ab_data_init(AvbABData* data) { + memset(data, '\0', sizeof(AvbABData)); + memcpy(data->magic, AVB_AB_MAGIC, AVB_AB_MAGIC_LEN); + data->version_major = AVB_AB_MAJOR_VERSION; + data->version_minor = AVB_AB_MINOR_VERSION; + data->slots[0].priority = AVB_AB_MAX_PRIORITY; + data->slots[0].tries_remaining = AVB_AB_MAX_TRIES_REMAINING; + data->slots[0].successful_boot = 0; + data->slots[0].bootloader_verified = 0; + data->slots[1].priority = AVB_AB_MAX_PRIORITY - 1; + data->slots[1].tries_remaining = AVB_AB_MAX_TRIES_REMAINING; + data->slots[1].successful_boot = 0; + data->slots[1].bootloader_verified = 0; +} + +bool fsl_avb_ab_data_verify_and_byteswap(const AvbABData* src, + AvbABData* dest) { + /* Ensure magic is correct. */ + if (memcmp(src->magic, AVB_AB_MAGIC, AVB_AB_MAGIC_LEN) != 0) { + printf("Magic is incorrect.\n"); + return false; + } + + memcpy(dest, src, sizeof(AvbABData)); + dest->crc32 = be32_to_cpu(dest->crc32); + + /* Ensure we don't attempt to access any fields if the major version + * is not supported. + */ + if (dest->version_major > AVB_AB_MAJOR_VERSION) { + printf("No support for given major version.\n"); + return false; + } + + /* Fail if CRC32 doesn't match. */ + if (dest->crc32 != + avb_crc32((const uint8_t*)dest, sizeof(AvbABData) - sizeof(uint32_t))) { + printf("CRC32 does not match.\n"); + return false; + } + + return true; +} + +/* Writes A/B metadata to disk only if it has changed. + */ +int fsl_save_metadata_if_changed_dual_uboot(struct blk_desc *dev_desc, + AvbABData* ab_data, + AvbABData* ab_data_orig) { + AvbABData serialized; + size_t num_bytes; + disk_partition_t info; + + /* Save metadata if changed. */ + if (memcmp(ab_data, ab_data_orig, sizeof(AvbABData)) != 0) { + /* Get misc partition info */ + if (part_get_info_by_name(dev_desc, PARTITION_MISC, &info) == -1) { + printf("Can't get partition info of partition: misc\n"); + return -1; + } + + /* Writing A/B metadata to disk. */ + fsl_avb_ab_data_update_crc_and_byteswap(ab_data, &serialized); + if (write_to_partition_in_bytes(dev_desc, &info, + FSL_AB_METADATA_MISC_PARTITION_OFFSET, + sizeof(AvbABData), + (void *)&serialized, &num_bytes) || + (num_bytes != sizeof(AvbABData))) { + printf("Error--write metadata fail!\n"); + return -1; + } + } + return 0; +} + +/* Load metadate from misc partition. + */ +int fsl_load_metadata_dual_uboot(struct blk_desc *dev_desc, + AvbABData* ab_data, + AvbABData* ab_data_orig) { + disk_partition_t info; + AvbABData serialized; + size_t num_bytes; + + if (part_get_info_by_name(dev_desc, PARTITION_MISC, &info) == -1) { + printf("Can't get partition info of partition: misc\n"); + return -1; + } else { + read_from_partition_in_bytes(dev_desc, &info, + FSL_AB_METADATA_MISC_PARTITION_OFFSET, + sizeof(AvbABData), + (void *)ab_data, &num_bytes ); + if (num_bytes != sizeof(AvbABData)) { + printf("Error--read metadata fail!\n"); + return -1; + } else { + if (!fsl_avb_ab_data_verify_and_byteswap(ab_data, &serialized)) { + printf("Error validating A/B metadata from disk.\n"); + printf("Resetting and writing new A/B metadata to disk.\n"); + fsl_avb_ab_data_init(ab_data); + fsl_avb_ab_data_update_crc_and_byteswap(ab_data, &serialized); + num_bytes = 0; + if (write_to_partition_in_bytes( + dev_desc, &info, + FSL_AB_METADATA_MISC_PARTITION_OFFSET, + sizeof(AvbABData), + (void *)&serialized, &num_bytes) || + (num_bytes != sizeof(AvbABData))) { + printf("Error--write metadata fail!\n"); + return -1; + } else + return 0; + } else { + memcpy(ab_data_orig, ab_data, sizeof(AvbABData)); + /* Ensure data is normalized, e.g. illegal states will be marked as + * unbootable and all unbootable states are represented with + * (priority=0, tries_remaining=0, successful_boot=0). + */ + fsl_slot_normalize(&ab_data->slots[0]); + fsl_slot_normalize(&ab_data->slots[1]); + return 0; + } + } + } +} + +#ifndef CONFIG_XEN +static int spl_verify_rbidx(struct mmc *mmc, AvbABSlotData *slot, + struct spl_image_info *spl_image) +{ + kblb_hdr_t hdr; + kblb_tag_t *rbk; + uint64_t extract_idx; +#ifdef CONFIG_AVB_ATX + struct bl_rbindex_package *bl_rbindex; +#endif + + /* Make sure rollback index has been initialized before verify */ + if (rpmb_init()) { + printf("RPMB init failed!\n"); + return -1; + } + + /* Read bootloader rollback index header first. */ + if (rpmb_read(mmc, (uint8_t *)&hdr, sizeof(hdr), + BOOTLOADER_RBIDX_OFFSET) != 0) { + printf("Read RPMB error!\n"); + return -1; + } + + /* Read bootloader rollback index. */ + rbk = &(hdr.bootloader_rbk_tags); + if (rpmb_read(mmc, (uint8_t *)&extract_idx, rbk->len, rbk->offset) != 0) { + printf("Read rollback index error!\n"); + return -1; + } + + /* Verify bootloader rollback index. */ + if (spl_image->rbindex >= extract_idx) { + /* Rollback index verify pass, update it only when current slot + * has been marked as successful. + */ + if ((slot->successful_boot != 0) && (spl_image->rbindex != extract_idx) && + rpmb_write(mmc, (uint8_t *)(&(spl_image->rbindex)), + rbk->len, rbk->offset)) { + printf("Update bootloader rollback index failed!\n"); + return -1; + } + +#ifdef CONFIG_AVB_ATX + /* Pass bootloader rbindex to u-boot here. */ + bl_rbindex = (struct bl_rbindex_package *)BL_RBINDEX_LOAD_ADDR; + memcpy(bl_rbindex->magic, BL_RBINDEX_MAGIC, BL_RBINDEX_MAGIC_LEN); + if (slot->successful_boot != 0) + bl_rbindex->rbindex = spl_image->rbindex; + else + bl_rbindex->rbindex = extract_idx; +#endif + + return 0; + } else { + printf("Rollback index verify rejected!\n"); + return -1; + } + +} +#endif /* CONFIG_XEN */ + +#ifdef CONFIG_PARSE_CONTAINER +int mmc_load_image_parse_container_dual_uboot( + struct spl_image_info *spl_image, struct mmc *mmc) +{ + disk_partition_t info; + int ret = 0, n = 0; + char partition_name[PARTITION_NAME_LEN]; + struct blk_desc *dev_desc; + AvbABData ab_data, ab_data_orig; + size_t slot_index_to_boot, target_slot; +#ifndef CONFIG_XEN + struct keyslot_package kp; +#endif + + /* Check if gpt is valid */ + dev_desc = mmc_get_blk_desc(mmc); + if (dev_desc) { + if (part_get_info(dev_desc, 1, &info)) { + printf("GPT is invalid, please flash correct GPT!\n"); + return -1; + } + } else { + printf("Get block desc fail!\n"); + return -1; + } + +#ifndef CONFIG_XEN + /* Read RPMB keyslot package, xen won't check this. */ + read_keyslot_package(&kp); + if (strcmp(kp.magic, KEYPACK_MAGIC)) { + if (rpmbkey_is_set()) { + printf("\nFATAL - RPMB key was destroyed!\n"); + hang(); + } else + printf("keyslot package magic error, do nothing here!\n"); + } else { + /* Set power-on write protection to boot1 partition. */ + if (mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, BOOT1_PWR_WP)) { + printf("Unable to set power-on write protection to boot1!\n"); + return -1; + } + } +#endif + + /* Load AB metadata from misc partition */ + if (fsl_load_metadata_dual_uboot(dev_desc, &ab_data, + &ab_data_orig)) { + return -1; + } + + slot_index_to_boot = 2; // Means not 0 or 1 + target_slot = + (ab_data.slots[1].priority > ab_data.slots[0].priority) ? 1 : 0; + + for (n = 0; n < 2; n++) { + if (!fsl_slot_is_bootable(&ab_data.slots[target_slot])) { + target_slot = (target_slot == 1 ? 0 : 1); + continue; + } + /* Choose slot to load. */ + snprintf(partition_name, PARTITION_NAME_LEN, + PARTITION_BOOTLOADER"%s", + slot_suffixes[target_slot]); + + /* Read part info from gpt */ + if (part_get_info_by_name(dev_desc, partition_name, &info) == -1) { + printf("Can't get partition info of partition bootloader%s\n", + slot_suffixes[target_slot]); + ret = -1; + goto end; + } else { + ret = mmc_load_image_parse_container(spl_image, mmc, info.start); + + /* Don't need to check rollback index for xen. */ +#ifndef CONFIG_XEN + /* Image loaded successfully, go to verify rollback index */ + if (!ret && rpmbkey_is_set()) + ret = spl_verify_rbidx(mmc, &ab_data.slots[target_slot], spl_image); + + /* Copy rpmb keyslot to secure memory. */ + if (!ret) + fill_secure_keyslot_package(&kp); +#endif + } + + /* Set current slot to unbootable if load/verify fail. */ + if (ret != 0) { + printf("Load or verify bootloader%s fail, setting unbootable..\n", + slot_suffixes[target_slot]); + fsl_slot_set_unbootable(&ab_data.slots[target_slot]); + /* Switch to another slot. */ + target_slot = (target_slot == 1 ? 0 : 1); + } else { + slot_index_to_boot = target_slot; + n = 2; + } + } + + if (slot_index_to_boot == 2) { + /* No bootable slots! */ + printf("No bootable slots found.\n"); + ret = -1; + goto end; + } else if (!ab_data.slots[slot_index_to_boot].successful_boot && + (ab_data.slots[slot_index_to_boot].tries_remaining > 0)) { + /* Set the bootloader_verified flag if current slot only has one chance. */ + if (ab_data.slots[slot_index_to_boot].tries_remaining == 1) + ab_data.slots[slot_index_to_boot].bootloader_verified = 1; + ab_data.slots[slot_index_to_boot].tries_remaining -= 1; + } + printf("Booting from bootloader%s...\n", slot_suffixes[slot_index_to_boot]); + +end: + /* Save metadata if changed. */ + if (fsl_save_metadata_if_changed_dual_uboot(dev_desc, &ab_data, &ab_data_orig)) { + ret = -1; + } + + if (ret) + return -1; + else + return 0; +} +#else /* CONFIG_PARSE_CONTAINER */ +int mmc_load_image_raw_sector_dual_uboot( + struct spl_image_info *spl_image, struct mmc *mmc) +{ + unsigned long count; + disk_partition_t info; + int ret = 0, n = 0; + char partition_name[PARTITION_NAME_LEN]; + struct blk_desc *dev_desc; + struct image_header *header; + AvbABData ab_data, ab_data_orig; + size_t slot_index_to_boot, target_slot; + struct keyslot_package kp; + + /* Check if gpt is valid */ + dev_desc = mmc_get_blk_desc(mmc); + if (dev_desc) { + if (part_get_info(dev_desc, 1, &info)) { + printf("GPT is invalid, please flash correct GPT!\n"); + return -1; + } + } else { + printf("Get block desc fail!\n"); + return -1; + } + + /* Init RPMB keyslot package if not initialized before. */ + read_keyslot_package(&kp); + if (strcmp(kp.magic, KEYPACK_MAGIC)) { + printf("keyslot package magic error. Will generate new one\n"); + if (gen_rpmb_key(&kp)) { + printf("Generate keyslot package fail!\n"); + return -1; + } + } + /* Set power-on write protection to boot1 partition. */ + if (mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, BOOT1_PWR_WP)) { + printf("Unable to set power-on write protection to boot1!\n"); + return -1; + } + + /* Load AB metadata from misc partition */ + if (fsl_load_metadata_dual_uboot(dev_desc, &ab_data, + &ab_data_orig)) { + return -1; + } + + slot_index_to_boot = 2; // Means not 0 or 1 + target_slot = + (ab_data.slots[1].priority > ab_data.slots[0].priority) ? 1 : 0; + + for (n = 0; n < 2; n++) { + if (!fsl_slot_is_bootable(&ab_data.slots[target_slot])) { + target_slot = (target_slot == 1 ? 0 : 1); + continue; + } + /* Choose slot to load. */ + snprintf(partition_name, PARTITION_NAME_LEN, + PARTITION_BOOTLOADER"%s", + slot_suffixes[target_slot]); + + /* Read part info from gpt */ + if (part_get_info_by_name(dev_desc, partition_name, &info) == -1) { + printf("Can't get partition info of partition bootloader%s\n", + slot_suffixes[target_slot]); + ret = -1; + goto end; + } else { + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + /* read image header to find the image size & load address */ + count = blk_dread(dev_desc, info.start, 1, header); + if (count == 0) { + ret = -1; + goto end; + } + + /* Load fit and check HAB */ + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && + image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + debug("Found FIT\n"); + load.dev = mmc; + load.priv = NULL; + load.filename = NULL; + load.bl_len = mmc->read_bl_len; + load.read = h_spl_load_read; + ret = spl_load_simple_fit(spl_image, &load, + info.start, header); + } else { + ret = -1; + } + + /* Fit image loaded successfully, go to verify rollback index */ + if (!ret) + ret = spl_verify_rbidx(mmc, &ab_data.slots[target_slot], spl_image); + + /* Copy rpmb keyslot to secure memory. */ + if (!ret) + fill_secure_keyslot_package(&kp); + } + + /* Set current slot to unbootable if load/verify fail. */ + if (ret != 0) { + printf("Load or verify bootloader%s fail, setting unbootable..\n", + slot_suffixes[target_slot]); + fsl_slot_set_unbootable(&ab_data.slots[target_slot]); + /* Switch to another slot. */ + target_slot = (target_slot == 1 ? 0 : 1); + } else { + slot_index_to_boot = target_slot; + n = 2; + } + } + + if (slot_index_to_boot == 2) { + /* No bootable slots! */ + printf("No bootable slots found.\n"); + ret = -1; + goto end; + } else if (!ab_data.slots[slot_index_to_boot].successful_boot && + (ab_data.slots[slot_index_to_boot].tries_remaining > 0)) { + /* Set the bootloader_verified flag as if current slot only has one chance. */ + if (ab_data.slots[slot_index_to_boot].tries_remaining == 1) + ab_data.slots[slot_index_to_boot].bootloader_verified = 1; + ab_data.slots[slot_index_to_boot].tries_remaining -= 1; + } + printf("Booting from bootloader%s...\n", slot_suffixes[slot_index_to_boot]); + +end: + /* Save metadata if changed. */ + if (fsl_save_metadata_if_changed_dual_uboot(dev_desc, &ab_data, &ab_data_orig)) { + ret = -1; + } + + if (ret) + return -1; + else + return 0; +} + +/* + * spl_fit_get_rbindex(): Get rollback index of the bootloader. + * @fit: Pointer to the FDT blob. + * @images: Offset of the /images subnode. + * + * Return: the rollback index value of bootloader or a negative + * error number. + */ +int spl_fit_get_rbindex(const void *fit, int images) +{ + const char *str; + uint64_t index; + int conf_node; + int len; + + conf_node = fit_find_config_node(fit); + if (conf_node < 0) { + return conf_node; + } + + str = fdt_getprop(fit, conf_node, "rbindex", &len); + if (!str) { + debug("cannot find property 'rbindex'\n"); + return -EINVAL; + } + + index = simple_strtoul(str, NULL, 10); + + return index; +} +#endif /* CONFIG_PARSE_CONTAINER */ + +/* For normal build */ +#elif !defined(CONFIG_SPL_BUILD) + +/* Writes A/B metadata to disk only if it has been changed. + */ +static AvbIOResult fsl_save_metadata_if_changed(AvbABOps* ab_ops, + AvbABData* ab_data, + AvbABData* ab_data_orig) { + if (avb_safe_memcmp(ab_data, ab_data_orig, sizeof(AvbABData)) != 0) { + avb_debug("Writing A/B metadata to disk.\n"); + return ab_ops->write_ab_metadata(ab_ops, ab_data); + } + return AVB_IO_RESULT_OK; +} + +/* Helper function to load metadata - returns AVB_IO_RESULT_OK on + * success, error code otherwise. This is a copy of load_metadata() + * from /lib/avb/libavb_ab/avb_ab_flow.c. + */ +static AvbIOResult fsl_load_metadata(AvbABOps* ab_ops, + AvbABData* ab_data, + AvbABData* ab_data_orig) { + AvbIOResult io_ret; + + io_ret = ab_ops->read_ab_metadata(ab_ops, ab_data); + if (io_ret != AVB_IO_RESULT_OK) { + avb_error("I/O error while loading A/B metadata.\n"); + return io_ret; + } + *ab_data_orig = *ab_data; + + /* Ensure data is normalized, e.g. illegal states will be marked as + * unbootable and all unbootable states are represented with + * (priority=0, tries_remaining=0, successful_boot=0). + */ + fsl_slot_normalize(&ab_data->slots[0]); + fsl_slot_normalize(&ab_data->slots[1]); + return AVB_IO_RESULT_OK; +} + +#ifdef CONFIG_DUAL_BOOTLOADER +AvbABFlowResult avb_flow_dual_uboot(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data) { + AvbOps* ops = ab_ops->ops; + AvbSlotVerifyData* slot_data = NULL; + AvbSlotVerifyData* data = NULL; + AvbABFlowResult ret; + AvbABData ab_data, ab_data_orig; + AvbIOResult io_ret; + bool saw_and_allowed_verification_error = false; + AvbSlotVerifyResult verify_result; + bool set_slot_unbootable = false; + int target_slot, n; + uint64_t rollback_index_value = 0; + uint64_t current_rollback_index_value = 0; + + io_ret = fsl_load_metadata(ab_ops, &ab_data, &ab_data_orig); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + + /* Choose the target slot, it should be the same with the one in SPL. */ + target_slot = get_curr_slot(&ab_data); + if (target_slot == -1) { + ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS; + printf("No bootable slot found!\n"); + goto out; + } + /* Clear the bootloader_verified flag. */ + ab_data.slots[target_slot].bootloader_verified = 0; + + printf("Verifying slot %s ...\n", slot_suffixes[target_slot]); + verify_result = avb_slot_verify(ops, + requested_partitions, + slot_suffixes[target_slot], + flags, + hashtree_error_mode, + &slot_data); + + switch (verify_result) { + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + + case AVB_SLOT_VERIFY_RESULT_OK: + ret = AVB_AB_FLOW_RESULT_OK; + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + /* Even with AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR + * these mean game over. + */ + set_slot_unbootable = true; + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + if (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR) { + /* Do nothing since we allow this. */ + avb_debugv("Allowing slot ", + slot_suffixes[target_slot], + " which verified " + "with result ", + avb_slot_verify_result_to_string(verify_result), + " because " + "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR " + "is set.\n", + NULL); + saw_and_allowed_verification_error = + true; + } else { + set_slot_unbootable = true; + } + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + ret = AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT; + goto out; + /* Do not add a 'default:' case here because + * of -Wswitch. + */ + } + + if (set_slot_unbootable) { + avb_errorv("Error verifying slot ", + slot_suffixes[target_slot], + " with result ", + avb_slot_verify_result_to_string(verify_result), + " - setting unbootable.\n", + NULL); + fsl_slot_set_unbootable(&ab_data.slots[target_slot]); + + /* Only the slot chosen by SPL will be verified here so we + * return AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS if the + * slot should be set unbootable. + */ + ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS; + goto out; + } + + /* Update stored rollback index only when the slot has been marked + * as successful. Do this for every rollback index location. + */ + if (ab_data.slots[target_slot].successful_boot != 0) { + for (n = 0; n < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; n++) { + + rollback_index_value = slot_data->rollback_indexes[n]; + + if (rollback_index_value != 0) { + io_ret = ops->read_rollback_index( + ops, n, ¤t_rollback_index_value); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_error("Error getting rollback index for slot.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + if (current_rollback_index_value != rollback_index_value) { + io_ret = ops->write_rollback_index( + ops, n, rollback_index_value); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_error("Error setting stored rollback index.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + } + } + } + } + + /* Finally, select this slot. */ + avb_assert(slot_data != NULL); + data = slot_data; + slot_data = NULL; + if (saw_and_allowed_verification_error) { + avb_assert( + flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR); + ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR; + } else { + ret = AVB_AB_FLOW_RESULT_OK; + } + +out: + io_ret = fsl_save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig); + if (io_ret != AVB_IO_RESULT_OK) { + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + } else { + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + } + if (data != NULL) { + avb_slot_verify_data_free(data); + data = NULL; + } + } + + if (slot_data != NULL) + avb_slot_verify_data_free(slot_data); + + if (out_data != NULL) { + *out_data = data; + } else { + if (data != NULL) { + avb_slot_verify_data_free(data); + } + } + + return ret; +} +#else /* CONFIG_DUAL_BOOTLOADER */ +/* For legacy i.mx6/7, we won't enable A/B due to the limitation of + * storage capacity, but we still want to verify boot/recovery with + * AVB. */ +AvbABFlowResult avb_single_flow(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data) { + AvbOps* ops = ab_ops->ops; + AvbSlotVerifyData* slot_data = NULL; + AvbSlotVerifyData* data = NULL; + AvbABFlowResult ret; + bool saw_and_allowed_verification_error = false; + + /* Validate boot/recovery. */ + AvbSlotVerifyResult verify_result; + + verify_result = avb_slot_verify(ops, + requested_partitions, + "", + flags, + hashtree_error_mode, + &slot_data); + switch (verify_result) { + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + + case AVB_SLOT_VERIFY_RESULT_OK: + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + /* Even with AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR + * these mean game over. + */ + ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS; + goto out; + + /* explicit fallthrough. */ + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + if (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR) { + /* Do nothing since we allow this. */ + avb_debugv("Allowing slot ", + slot_suffixes[n], + " which verified " + "with result ", + avb_slot_verify_result_to_string(verify_result), + " because " + "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR " + "is set.\n", + NULL); + saw_and_allowed_verification_error = true; + } else { + ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS; + goto out; + } + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + ret = AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT; + goto out; + /* Do not add a 'default:' case here because of -Wswitch. */ + } + + avb_assert(slot_data != NULL); + data = slot_data; + slot_data = NULL; + if (saw_and_allowed_verification_error) { + avb_assert(flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR); + ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR; + } else { + ret = AVB_AB_FLOW_RESULT_OK; + } + +out: + if (slot_data != NULL) { + avb_slot_verify_data_free(slot_data); + } + + if (out_data != NULL) { + *out_data = data; + } else { + if (data != NULL) { + avb_slot_verify_data_free(data); + } + } + + return ret; +} + +AvbABFlowResult avb_ab_flow_fast(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data) { + AvbOps* ops = ab_ops->ops; + AvbSlotVerifyData* slot_data[2] = {NULL, NULL}; + AvbSlotVerifyData* data = NULL; + AvbABFlowResult ret; + AvbABData ab_data, ab_data_orig; + size_t slot_index_to_boot, n; + AvbIOResult io_ret; + bool saw_and_allowed_verification_error = false; + size_t target_slot; + AvbSlotVerifyResult verify_result; + bool set_slot_unbootable = false; + uint64_t rollback_index_value = 0; + uint64_t current_rollback_index_value = 0; + + io_ret = fsl_load_metadata(ab_ops, &ab_data, &ab_data_orig); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + + slot_index_to_boot = 2; // Means not 0 or 1 + target_slot = + (ab_data.slots[1].priority > ab_data.slots[0].priority) ? 1 : 0; + + for (n = 0; n < 2; n++) { + if (!fsl_slot_is_bootable(&ab_data.slots[target_slot])) { + target_slot = (target_slot == 1 ? 0 : 1); + continue; + } + verify_result = avb_slot_verify(ops, + requested_partitions, + slot_suffixes[target_slot], + flags, + hashtree_error_mode, + &slot_data[target_slot]); + switch (verify_result) { + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + + case AVB_SLOT_VERIFY_RESULT_OK: + slot_index_to_boot = target_slot; + n = 2; + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + /* Even with AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR + * these mean game over. + */ + set_slot_unbootable = true; + break; + + /* explicit fallthrough. */ + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + if (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR) { + /* Do nothing since we allow this. */ + avb_debugv("Allowing slot ", + slot_suffixes[target_slot], + " which verified " + "with result ", + avb_slot_verify_result_to_string(verify_result), + " because " + "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR " + "is set.\n", + NULL); + saw_and_allowed_verification_error = + true; + slot_index_to_boot = target_slot; + n = 2; + } else { + set_slot_unbootable = true; + } + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + ret = AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT; + goto out; + /* Do not add a 'default:' case here because + * of -Wswitch. + */ + } + + if (set_slot_unbootable) { + avb_errorv("Error verifying slot ", + slot_suffixes[target_slot], + " with result ", + avb_slot_verify_result_to_string(verify_result), + " - setting unbootable.\n", + NULL); + fsl_slot_set_unbootable(&ab_data.slots[target_slot]); + set_slot_unbootable = false; + } + /* switch to another slot */ + target_slot = (target_slot == 1 ? 0 : 1); + } + + if (slot_index_to_boot == 2) { + /* No bootable slots! */ + avb_error("No bootable slots found.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS; + goto out; + } + + /* Update stored rollback index only when the slot has been marked + * as successful. Do this for every rollback index location. + */ + if (ab_data.slots[slot_index_to_boot].successful_boot != 0) { + for (n = 0; n < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; n++) { + + rollback_index_value = slot_data[slot_index_to_boot]->rollback_indexes[n]; + + if (rollback_index_value != 0) { + io_ret = ops->read_rollback_index( + ops, n, ¤t_rollback_index_value); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_error("Error getting rollback index for slot.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + if (current_rollback_index_value != rollback_index_value) { + io_ret = ops->write_rollback_index( + ops, n, rollback_index_value); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_error("Error setting stored rollback index.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + } + } + } + } + + /* Finally, select this slot. */ + avb_assert(slot_data[slot_index_to_boot] != NULL); + data = slot_data[slot_index_to_boot]; + slot_data[slot_index_to_boot] = NULL; + if (saw_and_allowed_verification_error) { + avb_assert( + flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR); + ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR; + } else { + ret = AVB_AB_FLOW_RESULT_OK; + } + + /* ... and decrement tries remaining, if applicable. */ + if (!ab_data.slots[slot_index_to_boot].successful_boot && + (ab_data.slots[slot_index_to_boot].tries_remaining > 0)) { + ab_data.slots[slot_index_to_boot].tries_remaining -= 1; + } + +out: + io_ret = fsl_save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig); + if (io_ret != AVB_IO_RESULT_OK) { + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + } else { + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + } + if (data != NULL) { + avb_slot_verify_data_free(data); + data = NULL; + } + } + + for (n = 0; n < 2; n++) { + if (slot_data[n] != NULL) { + avb_slot_verify_data_free(slot_data[n]); + } + } + + if (out_data != NULL) { + *out_data = data; + } else { + if (data != NULL) { + avb_slot_verify_data_free(data); + } + } + + return ret; +} +#endif /* CONFIG_DUAL_BOOTLOADER */ + +#endif /* CONFIG_DUAL_BOOTLOADER && CONFIG_SPL_BUILD */ diff --git a/lib/avb/fsl/fsl_avb_sysdeps_uboot.c b/lib/avb/fsl/fsl_avb_sysdeps_uboot.c new file mode 100644 index 00000000000..5fcb69f75ea --- /dev/null +++ b/lib/avb/fsl/fsl_avb_sysdeps_uboot.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include + +#include "../libavb/libavb.h" + +int avb_memcmp(const void* src1, const void* src2, size_t n) { + return memcmp(src1, src2, n); +} + +void* avb_memcpy(void* dest, const void* src, size_t n) { + return memcpy(dest, src, n); +} + +void* avb_memset(void* dest, const int c, size_t n) { + return memset(dest, c, n); +} + +int avb_strcmp(const char* s1, const char* s2) { return strcmp(s1, s2); } + +size_t avb_strlen(const char* str) { return strlen(str); } + +void avb_abort(void) { panic("avb_abort!\n"); } + +void avb_print(const char* message) { printf("%s", message); } + +void avb_printv(const char* message, ...) { + va_list ap; + const char* m; + + va_start(ap, message); + for (m = message; m != NULL; m = va_arg(ap, const char*)) { + printf("%s", m); + } + va_end(ap); +} + +void* avb_malloc_(size_t size) { return malloc(size); } + +void avb_free(void* ptr) { free(ptr); } + +uint32_t avb_div_by_10(uint64_t* dividend) { + uint32_t rem = (uint32_t)(*dividend % 10); + *dividend /= 10; + return rem; +} diff --git a/lib/avb/fsl/fsl_avbkey.c b/lib/avb/fsl/fsl_avbkey.c new file mode 100644 index 00000000000..63d51102f3f --- /dev/null +++ b/lib/avb/fsl/fsl_avbkey.c @@ -0,0 +1,1192 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include +#include +#ifdef CONFIG_FSL_CAAM_KB +#include +#endif +#include +#include +#include +#include + +#include +#include "trusty/avb.h" +#ifdef CONFIG_IMX_TRUSTY_OS +#include +#endif +#include "fsl_avbkey.h" +#include "utils.h" +#include "debug.h" +#include +#include "trusty/hwcrypto.h" +#include "fsl_atx_attributes.h" + +#define INITFLAG_FUSE_OFFSET 0 +#define INITFLAG_FUSE_MASK 0x00000001 +#define INITFLAG_FUSE 0x00000001 + +#define RPMB_BLKSZ 256 +#define RPMBKEY_LENGTH 32 +#define RPMBKEY_BLOB_LEN ((RPMBKEY_LENGTH) + (CAAM_PAD)) + +extern int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value); + +#ifdef AVB_RPMB +static int mmc_dev_no = -1; + +struct mmc *get_mmc(void) { + extern int mmc_get_env_devno(void); + struct mmc *mmc; + if (mmc_dev_no < 0 && (mmc_dev_no = mmc_get_env_dev()) < 0) + return NULL; + mmc = find_mmc_device(mmc_dev_no); + if (!mmc || mmc_init(mmc)) + return NULL; + return mmc; +} + +void fill_secure_keyslot_package(struct keyslot_package *kp) { + + memcpy((void*)CAAM_ARB_BASE_ADDR, kp, sizeof(struct keyslot_package)); + + /* invalidate the cache to make sure no critical information left in it */ + memset(kp, 0, sizeof(struct keyslot_package)); + invalidate_dcache_range(((ulong)kp) & 0xffffffc0,(((((ulong)kp) + + sizeof(struct keyslot_package)) & 0xffffff00) + + 0x100)); +} + +int read_keyslot_package(struct keyslot_package* kp) { + char original_part; + int blksz; + unsigned char* fill = NULL; + int ret = 0; + /* load tee from boot1 of eMMC. */ + int mmcc = mmc_get_env_dev(); + struct blk_desc *dev_desc = NULL; + + struct mmc *mmc; +#ifdef CONFIG_IMX8_TRUSTY_XEN + mmcc = 0; +#endif + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("boota: cannot find '%d' mmc device\n", mmcc); + return -1; + } +#ifndef CONFIG_BLK + original_part = mmc->block_dev.hwpart; + dev_desc = blk_get_dev("mmc", mmcc); +#else + dev_desc = mmc_get_blk_desc(mmc); +#endif + if (NULL == dev_desc) { + printf("** Block device MMC %d not supported\n", mmcc); + return -1; + } +#ifdef CONFIG_BLK + original_part = dev_desc->hwpart; +#endif + + blksz = dev_desc->blksz; + fill = (unsigned char *)memalign(ALIGN_BYTES, blksz); + + /* below was i.MX mmc operation code */ + if (mmc_init(mmc)) { + printf("mmc%d init failed\n", mmcc); + ret = -1; + goto fail;; + } + + if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) { + ret = -1; + goto fail; + } +#ifndef CONFIG_BLK + mmc->block_dev.hwpart = KEYSLOT_HWPARTITION_ID; +#else + dev_desc->hwpart = KEYSLOT_HWPARTITION_ID; +#endif + if (blk_dread(dev_desc, KEYSLOT_BLKS, + 1, fill) != 1) { + printf("Failed to read rpmbkeyblob."); + ret = -1; + goto fail; + } else { + memcpy(kp, fill, sizeof(struct keyslot_package)); + } + +fail: + /* Free allocated memory. */ + if (fill != NULL) + free(fill); + /* Return to original partition */ +#ifndef CONFIG_BLK + if (mmc->block_dev.hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + return -1; + mmc->block_dev.hwpart = original_part; + } +#else + if (dev_desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + return -1; + dev_desc->hwpart = original_part; + } +#endif + return ret; +} + +bool rpmbkey_is_set(void) +{ + int mmcc; + bool ret; + uint8_t *buf; + struct mmc *mmc; + char original_part; + struct blk_desc *desc = NULL; + + /* Get current mmc device. */ + mmcc = mmc_get_env_dev(); + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("error - cannot find '%d' mmc device\n", mmcc); + return false; + } + + desc = mmc_get_blk_desc(mmc); + original_part = desc->hwpart; + + /* Switch to the RPMB partition */ + if (desc->hwpart != MMC_PART_RPMB) { + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) { + printf("ERROR - can't switch to rpmb partition \n"); + return false; + } + desc->hwpart = MMC_PART_RPMB; + } + + /* Try to read the first one block, return count '1' means the rpmb + * key has been set, otherwise means the key hasn't been set. + */ + buf = (uint8_t *)memalign(ALIGN_BYTES, desc->blksz); + if (mmc_rpmb_read(mmc, buf, 0, 1, NULL) != 1) + ret = false; + else + ret = true; + + /* return to original partition. */ + if (desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + ret = false; + desc->hwpart = original_part; + } + /* remember to free the buffer */ + if (buf != NULL) + free(buf); + + return ret; +} + +#ifdef CONFIG_FSL_CAAM_KB +int rpmb_read(struct mmc *mmc, uint8_t *buffer, size_t num_bytes, int64_t offset) { + + unsigned char *bdata = NULL; + unsigned char *out_buf = (unsigned char *)buffer; + unsigned long s, cnt; + unsigned long blksz; + size_t num_read = 0; + unsigned short part_start, part_length, part_end, bs, be; + margin_pos_t margin; + char original_part; + uint8_t *blob = NULL; + struct blk_desc *desc = mmc_get_blk_desc(mmc); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, extract_key, RPMBKEY_LENGTH); + + struct keyslot_package kp; + int ret; + + blksz = RPMB_BLKSZ; + part_length = mmc->capacity_rpmb >> 8; + part_start = 0; + part_end = part_start + part_length - 1; + + DEBUGAVB("[rpmb]: offset=%ld, num_bytes=%zu\n", (long)offset, num_bytes); + + if(get_margin_pos(part_start, part_end, blksz, + &margin, offset, num_bytes, false)) + return -1; + + bs = (unsigned short)margin.blk_start; + be = (unsigned short)margin.blk_end; + s = margin.start; + + /* Switch to the RPMB partition */ + original_part = desc->hwpart; + if (desc->hwpart != MMC_PART_RPMB) { + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) + return -1; + desc->hwpart = MMC_PART_RPMB; + } + + /* get rpmb key */ + blob = (uint8_t *)memalign(ARCH_DMA_MINALIGN, RPMBKEY_BLOB_LEN); + if (read_keyslot_package(&kp)) { + ERR("read rpmb key error\n"); + ret = -1; + goto fail; + } + /* copy rpmb key to blob */ + memcpy(blob, kp.rpmb_keyblob, RPMBKEY_BLOB_LEN); + caam_open(); + if (caam_decap_blob((ulong)extract_key, (ulong)blob, + RPMBKEY_LENGTH)) { + ERR("decap rpmb key error\n"); + ret = -1; + goto fail; + } + + /* alloc a blksz mem */ + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) { + ret = -1; + goto fail; + } + /* one block a time */ + while (bs <= be) { + memset(bdata, 0, blksz); + if (mmc_rpmb_read(mmc, bdata, bs, 1, extract_key) != 1) { + ret = -1; + goto fail; + } + cnt = blksz - s; + if (num_read + cnt > num_bytes) + cnt = num_bytes - num_read; + VDEBUG("cur: bs=%d, start=%ld, cnt=%ld bdata=0x%p\n", + bs, s, cnt, bdata); + memcpy(out_buf, bdata + s, cnt); + bs++; + num_read += cnt; + out_buf += cnt; + s = 0; + } + ret = 0; + +fail: + /* Return to original partition */ + if (desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + ret = -1; + else + desc->hwpart = original_part; + } + if (blob != NULL) + free(blob); + if (bdata != NULL) + free(bdata); + return ret; + +} + +int rpmb_write(struct mmc *mmc, uint8_t *buffer, size_t num_bytes, int64_t offset) { + + unsigned char *bdata = NULL; + unsigned char *in_buf = (unsigned char *)buffer; + unsigned long s, cnt; + unsigned long blksz; + size_t num_write = 0; + unsigned short part_start, part_length, part_end, bs; + margin_pos_t margin; + char original_part; + uint8_t *blob = NULL; + struct blk_desc *desc = mmc_get_blk_desc(mmc); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, extract_key, RPMBKEY_LENGTH); + + struct keyslot_package kp; + int ret; + + blksz = RPMB_BLKSZ; + part_length = mmc->capacity_rpmb >> 8; + part_start = 0; + part_end = part_start + part_length - 1; + + DEBUGAVB("[rpmb]: offset=%ld, num_bytes=%zu\n", (long)offset, num_bytes); + + if(get_margin_pos(part_start, part_end, blksz, + &margin, offset, num_bytes, false)) { + ERR("get_margin_pos err\n"); + return -1; + } + + bs = (unsigned short)margin.blk_start; + s = margin.start; + + /* Switch to the RPMB partition */ + original_part = desc->hwpart; + if (desc->hwpart != MMC_PART_RPMB) { + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) + return -1; + desc->hwpart = MMC_PART_RPMB; + } + + /* get rpmb key */ + blob = (uint8_t *)memalign(ARCH_DMA_MINALIGN, RPMBKEY_BLOB_LEN); + if (read_keyslot_package(&kp)) { + ERR("read rpmb key error\n"); + ret = -1; + goto fail; + } + /* copy rpmb key to blob */ + memcpy(blob, kp.rpmb_keyblob, RPMBKEY_BLOB_LEN); + caam_open(); + if (caam_decap_blob((ulong)extract_key, (ulong)blob, + RPMBKEY_LENGTH)) { + ERR("decap rpmb key error\n"); + ret = -1; + goto fail; + } + /* alloc a blksz mem */ + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) { + ret = -1; + goto fail; + } + while (num_write < num_bytes) { + memset(bdata, 0, blksz); + cnt = blksz - s; + if (num_write + cnt > num_bytes) + cnt = num_bytes - num_write; + if (!s || cnt != blksz) { /* read blk first */ + if (mmc_rpmb_read(mmc, bdata, bs, 1, extract_key) != 1) { + ERR("mmc_rpmb_read err, mmc= 0x%08x\n", (uint32_t)(ulong)mmc); + ret = -1; + goto fail; + } + } + memcpy(bdata + s, in_buf, cnt); /* change data */ + VDEBUG("cur: bs=%d, start=%ld, cnt=%ld\n", bs, s, cnt); + if (mmc_rpmb_write(mmc, bdata, bs, 1, extract_key) != 1) { + ret = -1; + goto fail; + } + bs++; + num_write += cnt; + in_buf += cnt; + if (s != 0) + s = 0; + } + ret = 0; + +fail: + /* Return to original partition */ + if (desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + ret = -1; + else + desc->hwpart = original_part; + } + if (blob != NULL) + free(blob); + if (bdata != NULL) + free(bdata); + + return ret; + +} + +int rpmb_init(void) { +#if !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DUAL_BOOTLOADER) + int i; +#endif + kblb_hdr_t hdr; + kblb_tag_t *tag; + struct mmc *mmc_dev; + uint32_t offset; + uint32_t rbidx_len; + uint8_t *rbidx; + + /* check init status first */ + if ((mmc_dev = get_mmc()) == NULL) { + ERR("ERROR - get mmc device\n"); + return -1; + } + /* The bootloader rollback index is stored in the last 8k bytes of + * RPMB which is different from the rollback index for vbmeta and + * ATX key versions. + */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER) + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), + BOOTLOADER_RBIDX_OFFSET) != 0) { +#else + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { +#endif + ERR("read RPMB error\n"); + return -1; + } + if (!memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN)) + return 0; + else + printf("initialize rollback index...\n"); + /* init rollback index */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER) + offset = BOOTLOADER_RBIDX_START; + rbidx_len = BOOTLOADER_RBIDX_LEN; + rbidx = malloc(rbidx_len); + if (rbidx == NULL) { + ERR("failed to allocate memory!\n"); + return -1; + } + memset(rbidx, 0, rbidx_len); + *(uint64_t *)rbidx = BOOTLOADER_RBIDX_INITVAL; + tag = &hdr.bootloader_rbk_tags; + tag->offset = offset; + tag->len = rbidx_len; + if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) { + ERR("write RBKIDX RPMB error\n"); + free(rbidx); + return -1; + } + if (rbidx != NULL) + free(rbidx); +#else /* CONFIG_SPL_BUILD && CONFIG_DUAL_BOOTLOADER */ + offset = AVB_RBIDX_START; + rbidx_len = AVB_RBIDX_LEN; + rbidx = malloc(rbidx_len); + if (rbidx == NULL) + return -1; + memset(rbidx, 0, rbidx_len); + *(uint64_t *)rbidx = AVB_RBIDX_INITVAL; + for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) { + tag = &hdr.rbk_tags[i]; + tag->flag = AVB_RBIDX_FLAG; + tag->offset = offset; + tag->len = rbidx_len; + if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) { + ERR("write RBKIDX RPMB error\n"); + free(rbidx); + return -1; + } + offset += AVB_RBIDX_ALIGN; + } + if (rbidx != NULL) + free(rbidx); +#ifdef CONFIG_AVB_ATX + /* init rollback index for Android Things key versions */ + offset = ATX_RBIDX_START; + rbidx_len = ATX_RBIDX_LEN; + rbidx = malloc(rbidx_len); + if (rbidx == NULL) + return -1; + memset(rbidx, 0, rbidx_len); + *(uint64_t *)rbidx = ATX_RBIDX_INITVAL; + for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) { + tag = &hdr.atx_rbk_tags[i]; + tag->flag = ATX_RBIDX_FLAG; + tag->offset = offset; + tag->len = rbidx_len; + if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) { + ERR("write ATX_RBKIDX RPMB error\n"); + free(rbidx); + return -1; + } + offset += ATX_RBIDX_ALIGN; + } + if (rbidx != NULL) + free(rbidx); +#endif +#endif /* CONFIG_SPL_BUILD && CONFIG_DUAL_BOOTLOADER */ + + /* init hdr */ + memcpy(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN); +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER) + if (rpmb_write(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), + BOOTLOADER_RBIDX_OFFSET) != 0) { +#else + if (rpmb_write(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { +#endif + ERR("write RPMB hdr error\n"); + return -1; + } + + return 0; +} + +int gen_rpmb_key(struct keyslot_package *kp) { + char original_part; + unsigned char* fill = NULL; + int blksz; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, plain_key, RPMBKEY_LENGTH); + + kp->rpmb_keyblob_len = RPMBKEY_LEN; + strcpy(kp->magic, KEYPACK_MAGIC); + + int ret = -1; + /* load tee from boot1 of eMMC. */ + int mmcc = mmc_get_env_dev(); + struct blk_desc *dev_desc = NULL; + + struct mmc *mmc; + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("boota: cannot find '%d' mmc device\n", mmcc); + return -1; + } +#ifndef CONFIG_BLK + original_part = mmc->block_dev.hwpart; + dev_desc = blk_get_dev("mmc", mmcc); +#else + dev_desc = mmc_get_blk_desc(mmc); + original_part = dev_desc->hwpart; +#endif + if (NULL == dev_desc) { + printf("** Block device MMC %d not supported\n", mmcc); + goto fail; + } + + blksz = dev_desc->blksz; + fill = (unsigned char *)memalign(ALIGN_BYTES, blksz); + + /* below was i.MX mmc operation code */ + if (mmc_init(mmc)) { + printf("mmc%d init failed\n", mmcc); + goto fail; + } + + /* Switch to the RPMB partition */ + + /* use caam hwrng to generate */ + caam_open(); + +#ifdef TRUSTY_RPMB_RANDOM_KEY + /* + * Since boot1 is a bit easy to be erase during development + * so that before production stage use full 0 rpmb key + */ + if (caam_hwrng(plain_key, RPMBKEY_LENGTH)) { + ERR("ERROR - caam rng\n"); + goto fail; + } +#else + memset(plain_key, 0, RPMBKEY_LENGTH); +#endif + + /* generate keyblob and program to boot1 partition */ + if (caam_gen_blob((ulong)plain_key, (ulong)(kp->rpmb_keyblob), + RPMBKEY_LENGTH)) { + ERR("gen rpmb key blb error\n"); + goto fail; + } + memcpy(fill, kp, sizeof(struct keyslot_package)); + + if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) { + ret = -1; + goto fail; + } + + if (blk_dwrite(dev_desc, KEYSLOT_BLKS, + 1, (void *)fill) != 1) { + printf("Failed to write rpmbkeyblob."); + goto fail; + } + + /* program key to mmc */ +#ifndef CONFIG_BLK + if (mmc->block_dev.hwpart != MMC_PART_RPMB) { + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) { + ret = -1; + goto fail; + } else + mmc->block_dev.hwpart = MMC_PART_RPMB; + } +#else + if (dev_desc->hwpart != MMC_PART_RPMB) { + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) { + ret = -1; + goto fail; + } else + dev_desc->hwpart = MMC_PART_RPMB; + } +#endif + if (mmc_rpmb_set_key(mmc, plain_key)) { + ERR("Key already programmed ?\n"); + goto fail; + } + + ret = 0; + +fail: + /* Return to original partition */ +#ifndef CONFIG_BLK + if (mmc->block_dev.hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + ret = -1; + else + mmc->block_dev.hwpart = original_part; + } +#else + if (dev_desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + ret = -1; + else + dev_desc->hwpart = original_part; + } +#endif + if (fill != NULL) + free(fill); + + return ret; + +} + +int init_avbkey(void) { + struct keyslot_package kp; + read_keyslot_package(&kp); + if (strcmp(kp.magic, KEYPACK_MAGIC)) { + printf("keyslot package magic error. Will generate new one\n"); + gen_rpmb_key(&kp); + } +#ifndef CONFIG_IMX_TRUSTY_OS + if (rpmb_init()) + return RESULT_ERROR; +#endif +#if defined(CONFIG_AVB_ATX) && !defined(CONFIG_IMX_TRUSTY_OS) + if (init_permanent_attributes_fuse()) + return RESULT_ERROR; +#endif + fill_secure_keyslot_package(&kp); + return RESULT_OK; +} + +#ifndef CONFIG_IMX_TRUSTY_OS +int rbkidx_erase(void) { + int i; + kblb_hdr_t hdr; + kblb_tag_t *tag; + struct mmc *mmc_dev; + + if ((mmc_dev = get_mmc()) == NULL) { + ERR("err get mmc device\n"); + return -1; + } + + /* read the kblb header */ + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { + ERR("read RPMB error\n"); + return -1; + } + if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) { + ERR("magic not match\n"); + return -1; + } + + /* reset rollback index */ + uint32_t offset = AVB_RBIDX_START; + uint32_t rbidx_len = AVB_RBIDX_LEN; + uint8_t *rbidx = malloc(rbidx_len); + if (rbidx == NULL) + return -1; + memset(rbidx, 0, rbidx_len); + *(uint64_t *)rbidx = AVB_RBIDX_INITVAL; + for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) { + tag = &hdr.rbk_tags[i]; + tag->flag = AVB_RBIDX_FLAG; + tag->offset = offset; + tag->len = rbidx_len; + /* write */ + if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) { + ERR("write RBKIDX RPMB error\n"); + free(rbidx); + return -1; + } + offset += AVB_RBIDX_ALIGN; + } + free(rbidx); + /* write back hdr */ + if (rpmb_write(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { + ERR("write RPMB hdr error\n"); + return -1; + } + return 0; +} +#endif /* CONFIG_IMX_TRUSTY_OS */ +#endif /* CONFIG_FSL_CAAM_KB */ +#else /* AVB_RPMB */ +int rbkidx_erase(void) { + return 0; +} +#endif /* AVB_RPMB */ + +#ifdef CONFIG_SPL_BUILD +#if defined (CONFIG_IMX8_TRUSTY_XEN) || \ + (defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX)) +int check_rpmb_blob(struct mmc *mmc) +{ + int ret = 0; + char original_part; + struct keyslot_package kp; + + read_keyslot_package(&kp); + if (strcmp(kp.magic, KEYPACK_MAGIC)) { + if (rpmbkey_is_set()) { + printf("\nFATAL - RPMB key was destroyed!\n"); + hang(); + } else { + printf("keyslot package magic error, do nothing here!\n"); + return 0; + } + } + /* If keyslot package valid, copy it to secure memory */ + fill_secure_keyslot_package(&kp); + + /* switch to boot1 partition. */ + original_part = mmc->block_dev.hwpart; + if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) { + printf("ERROR - can't switch to boot1 partition! \n"); + ret = -1; + goto fail; + } else + mmc->block_dev.hwpart = KEYSLOT_HWPARTITION_ID; + /* write power-on write protection for boot1 partition. */ + if (mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BOOT_WP, BOOT1_PWR_WP)) { + printf("ERROR - unable to set power-on write protection!\n"); + ret = -1; + goto fail; + } +fail: + /* return to original partition. */ + if (mmc->block_dev.hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + return -1; + mmc->block_dev.hwpart = original_part; + } + + return ret; +} +#endif /* CONFIG_IMX_TRUSTY_OS && !defined(CONFIG_AVB_ATX) */ +#else /* CONFIG_SPL_BUILD */ +#ifdef CONFIG_AVB_ATX +static int fsl_fuse_ops(uint32_t *buffer, uint32_t length, uint32_t offset, + const uint8_t read) { + + unsigned short bs, ws, bksz, cnt; + unsigned short num_done = 0; + margin_pos_t margin; + int i; + + /* read from fuse */ + bksz = CONFIG_AVB_FUSE_BANK_SIZEW; + if(get_margin_pos(CONFIG_AVB_FUSE_BANK_START, CONFIG_AVB_FUSE_BANK_END, bksz, + &margin, offset, length, false)) + return -1; + bs = (unsigned short)margin.blk_start; + ws = (unsigned short)margin.start; + + while (num_done < length) { + cnt = bksz - ws; + if (num_done + cnt > length) + cnt = length - num_done; + for (i = 0; i < cnt; i++) { + VDEBUG("cur: bank=%d, word=%d\n",bs, ws); + if (read) { + if (fuse_sense(bs, ws, buffer)) { + ERR("read fuse bank %d, word %d error\n", bs, ws); + return -1; + } + } else { +#ifdef CONFIG_AVB_FUSE + if (fuse_prog(bs, ws, *buffer)) { +#else + if (fuse_override(bs, ws, *buffer)) { +#endif + ERR("write fuse bank %d, word %d error\n", bs, ws); + return -1; + } + } + ws++; + buffer++; + } + bs++; + num_done += cnt; + ws = 0; + } + return 0; +} + +int fsl_fuse_read(uint32_t *buffer, uint32_t length, uint32_t offset) { + + return fsl_fuse_ops( + buffer, + length, + offset, + 1 + ); +} + +int fsl_fuse_write(const uint32_t *buffer, uint32_t length, uint32_t offset) { + + return fsl_fuse_ops( + (uint32_t *)buffer, + length, + offset, + 0 + ); +} + +static int sha256(unsigned char* data, int len, unsigned char* output) { + struct hash_algo *algo; + void *buf; + + if (hash_lookup_algo("sha256", &algo)) { + printf("error in lookup sha256 algo!\n"); + return RESULT_ERROR; + } + buf = map_sysmem((ulong)data, len); + algo->hash_func_ws(buf, len, output, algo->chunk_size); + unmap_sysmem(buf); + + return algo->digest_size; +} + +int permanent_attributes_sha256_hash(unsigned char* output) { + AvbAtxPermanentAttributes attributes; + +#ifdef CONFIG_IMX_TRUSTY_OS + if(!trusty_read_permanent_attributes((uint8_t *)(&attributes), + sizeof(AvbAtxPermanentAttributes))) { + goto calc_sha256; + } else { + ERR("No perm-attr fused. Will use hard code one.\n"); + } +#endif + /* get permanent attributes */ + attributes.version = fsl_version; + memcpy(attributes.product_root_public_key, fsl_product_root_public_key, + sizeof(fsl_product_root_public_key)); + memcpy(attributes.product_id, fsl_atx_product_id, + sizeof(fsl_atx_product_id)); +#ifdef CONFIG_IMX_TRUSTY_OS +calc_sha256: +#endif + /* calculate sha256(permanent attributes) hash */ + if (sha256((unsigned char *)&attributes, sizeof(AvbAtxPermanentAttributes), + output) == RESULT_ERROR) { + printf("ERROR - calculate permanent attributes hash error"); + return RESULT_ERROR; + } + + return RESULT_OK; +} + +static int init_permanent_attributes_fuse(void) { + +#ifdef CONFIG_ARM64 + return RESULT_OK; +#else + uint8_t sha256_hash[AVB_SHA256_DIGEST_SIZE]; + uint32_t buffer[ATX_FUSE_BANK_NUM]; + int num = 0; + + /* read first 112 bits of sha256(permanent attributes) from fuse */ + if (fsl_fuse_read(buffer, ATX_FUSE_BANK_NUM, PERMANENT_ATTRIBUTE_HASH_OFFSET)) { + printf("ERROR - read permanent attributes hash from fuse error\n"); + return RESULT_ERROR; + } + /* only take the lower 2 bytes of the last bank */ + buffer[ATX_FUSE_BANK_NUM - 1] &= ATX_FUSE_BANK_MASK; + + /* return RESULT_OK if fuse has been initialized before */ + for (num = 0; num < ATX_FUSE_BANK_NUM; num++) { + if (buffer[num]) + return RESULT_OK; + } + + /* calculate sha256(permanent attributes) */ + if (permanent_attributes_sha256_hash(sha256_hash) != RESULT_OK) { + printf("ERROR - calculating permanent attributes SHA256 error!\n"); + return RESULT_ERROR; + } + + /* write first 112 bits of sha256(permanent attributes) into fuse */ + memset(buffer, 0, sizeof(buffer)); + memcpy(buffer, sha256_hash, ATX_HASH_LENGTH); + if (fsl_fuse_write(buffer, ATX_FUSE_BANK_NUM, PERMANENT_ATTRIBUTE_HASH_OFFSET)) { + printf("ERROR - write permanent attributes hash to fuse error\n"); + return RESULT_ERROR; + } + + return RESULT_OK; +#endif /* CONFIG_ARM64 */ +} + +int avb_atx_fuse_perm_attr(uint8_t *staged_buffer, uint32_t size) { + + if (staged_buffer == NULL) { + ERR("Error. Get null staged_buffer\n"); + return -1; + } + if (size != sizeof(AvbAtxPermanentAttributes)) { + ERR("Error. expect perm_attr length %u, but get %u.\n", + (uint32_t)sizeof(AvbAtxPermanentAttributes), size); + return -1; + } +#ifdef CONFIG_IMX_TRUSTY_OS + if (trusty_write_permanent_attributes(staged_buffer, size)) { + ERR("Error. Failed to write permanent attributes into secure storage\n"); + return -1; + } + else + return init_permanent_attributes_fuse(); +#else + /* + * TODO: + * Need to handle this when no Trusty OS support. + * But now every Android Things will have Trusty OS support. + */ + ERR("No Trusty OS enabled in bootloader.\n"); + return 0; +#endif +} + +int avb_atx_get_unlock_challenge(struct AvbAtxOps* atx_ops, + uint8_t *upload_buffer, uint32_t *upload_size) +{ + struct AvbAtxUnlockChallenge *buf = NULL; + int ret, size; + + size = sizeof(struct AvbAtxUnlockChallenge); + buf = (struct AvbAtxUnlockChallenge *)malloc(size); + if (buf == NULL) { + ERR("unable to alloc memory!\n"); + return -1; + } + + if (avb_atx_generate_unlock_challenge(atx_ops, buf) != + AVB_IO_RESULT_OK) { + ERR("generate unlock challenge fail!\n"); + ret = -1; + goto fail; + } + /* Current avbtool only accept 16 bytes random numbers as unlock + * challenge, need to return the whole 'AvbAtxUnlockChallenge' + * when avbtool is ready. + */ + memcpy(upload_buffer, buf->challenge, AVB_ATX_UNLOCK_CHALLENGE_SIZE); + *upload_size = AVB_ATX_UNLOCK_CHALLENGE_SIZE; + ret = 0; +fail: + if (buf != NULL) + free(buf); + return ret; +} + +int avb_atx_verify_unlock_credential(struct AvbAtxOps* atx_ops, + uint8_t *staged_buffer) +{ + bool out_is_trusted; + AvbIOResult ret; + const AvbAtxUnlockCredential* buf = NULL; + + buf = (const AvbAtxUnlockCredential*)staged_buffer; + ret = avb_atx_validate_unlock_credential(atx_ops, buf, &out_is_trusted); + if ((ret != AVB_IO_RESULT_OK) || (out_is_trusted != true)) { + ERR("validate unlock credential fail!\n"); + return -1; + } else + return 0; +} + +bool perm_attr_are_fused(void) +{ +#ifdef CONFIG_IMX_TRUSTY_OS + AvbAtxPermanentAttributes attributes; + if(!trusty_read_permanent_attributes((uint8_t *)(&attributes), + sizeof(AvbAtxPermanentAttributes))) { + return true; + } else { + ERR("No perm-attr fused, please fuse your perm-attr first!.\n"); + return false; + } +#else + /* We hard code the perm-attr if trusty is not enabled. */ + return true; +#endif +} + +bool at_unlock_vboot_is_disabled(void) +{ + uint32_t unlock_vboot_status; + + if (fsl_fuse_read(&unlock_vboot_status, 1, + UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD)) { + printf("Read at unlock vboot status error!\n"); + return false; + } + + if (unlock_vboot_status & (1 << UNLOCK_VBOOT_STATUS_OFFSET_IN_BIT)) + return true; + else + return false; +} + +int at_disable_vboot_unlock(void) +{ + uint32_t unlock_vboot_status = 0; + + /* Read the status first */ + if (fsl_fuse_read(&unlock_vboot_status, 1, + UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD)) { + ERR("Read unlock vboot status error!\n"); + return -1; + } + + /* Set the disable unlock vboot bit */ + unlock_vboot_status |= (1 << UNLOCK_VBOOT_STATUS_OFFSET_IN_BIT); + + /* Write disable unlock vboot bit to fuse */ + if (fsl_fuse_write(&unlock_vboot_status, 1, + UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD)) { + ERR("Write unlock vboot status fail!\n"); + return -1; + } + + return 0; +} +#endif /* CONFIG_AVB_ATX */ + +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) +int do_rpmb_key_set(uint8_t *key, uint32_t key_size) +{ + int ret = 0; + int mmcc; + struct mmc *mmc; + char original_part; + struct keyslot_package kp; + struct blk_desc *desc = NULL; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_key, RPMBKEY_LENGTH); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, blob, + RPMBKEY_LENGTH + CAAM_PAD); + + /* copy rpmb key to cache aligned buffer. */ + memset(rpmb_key, 0, RPMBKEY_LENGTH); + memcpy(rpmb_key, key, RPMBKEY_LENGTH); + + /* Get current mmc device. */ + mmcc = mmc_get_env_dev(); + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("error - cannot find '%d' mmc device\n", mmcc); + return -1; + } + desc = mmc_get_blk_desc(mmc); + original_part = desc->hwpart; + + /* Switch to the RPMB partition */ + if (desc->hwpart != MMC_PART_RPMB) { + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) { + printf("ERROR - can't switch to rpmb partition \n"); + return -1; + } + desc->hwpart = MMC_PART_RPMB; + } + + if (mmc_rpmb_set_key(mmc, rpmb_key)) { + printf("ERROR - Key already programmed ?\n"); + ret = -1; + goto fail; + } else + printf("RPMB key programed successfully!\n"); + + /* Generate keyblob with CAAM. */ + kp.rpmb_keyblob_len = RPMBKEY_LENGTH + CAAM_PAD; + strcpy(kp.magic, KEYPACK_MAGIC); + if (hwcrypto_gen_blob((uint32_t)(ulong)rpmb_key, RPMBKEY_LENGTH, + (uint32_t)(ulong)blob) != 0) { + printf("ERROR - generate rpmb key blob error!\n"); + ret = -1; + goto fail; + } else + printf("RPMB key blob generated!\n"); + + memcpy(kp.rpmb_keyblob, blob, kp.rpmb_keyblob_len); + + /* Store the rpmb key blob to last block of boot1 partition. */ + if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) { + printf("ERROR - can't switch to boot1 partition! \n"); + ret = -1; + goto fail; + } else + desc->hwpart = KEYSLOT_HWPARTITION_ID; + if (blk_dwrite(desc, KEYSLOT_BLKS, 1, (void *)&kp) != 1) { + printf("ERROR - failed to write rpmbkeyblob!"); + ret = -1; + goto fail; + } + /* Set power-on write protection to boot1 partition. */ + if (mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BOOT_WP, BOOT1_PWR_WP)) { + printf("ERROR - unable to set power-on write protection!\n"); + ret = -1; + goto fail; + } + + /* Erase the key buffer. */ + memset(rpmb_key, 0, RPMBKEY_LENGTH); + memset(key, 0, RPMBKEY_LENGTH); + +fail: + /* Return to original partition */ + if (desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + return -1; + desc->hwpart = original_part; + } + + return ret; +} + +int fastboot_set_rpmb_key(uint8_t *staged_buf, uint32_t key_size) +{ + + if (memcmp(staged_buf, RPMB_KEY_MAGIC, strlen(RPMB_KEY_MAGIC))) { + printf("ERROR - rpmb magic doesn't match!\n"); + return -1; + } + + return do_rpmb_key_set(staged_buf + strlen(RPMB_KEY_MAGIC), + RPMBKEY_LENGTH); +} + +int fastboot_set_rpmb_random_key(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_key, RPMBKEY_LENGTH); + + if (hwcrypto_gen_rng((ulong)rpmb_key, RPMBKEY_LENGTH)) { + printf("error - can't generate random key!\n"); + return -1; + } + + return do_rpmb_key_set(rpmb_key, RPMBKEY_LENGTH); +} + +int avb_set_public_key(uint8_t *staged_buffer, uint32_t size) { + + if ((staged_buffer == NULL) || (size <= 0)) { + ERR("Error. Get null staged_buffer\n"); + return -1; + } + if (trusty_write_vbmeta_public_key(staged_buffer, size)) { + ERR("Error. Failed to write vbmeta public key into secure storage\n"); + return -1; + } else + printf("Set vbmeta public key successfully!\n"); + + return 0; +} +#endif /* CONFIG_IMX_TRUSTY_OS && !defind(CONFIG_AVB_ATX) */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/lib/avb/fsl/fsl_avbkey.h b/lib/avb/fsl/fsl_avbkey.h new file mode 100644 index 00000000000..8dd8746bf34 --- /dev/null +++ b/lib/avb/fsl/fsl_avbkey.h @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_AVBKEY_H__ +#define __FSL_AVBKEY_H__ + +#include + +#define CAAM_PAD 48 + +#define AVB_PUBKY_FLAG 0xABAB +#define AVB_PUBKY_OFFSET 0x1000 + +#define AVB_RBIDX_FLAG 0xCDCD +#define AVB_RBIDX_START 0x2000 +#define AVB_RBIDX_ALIGN 0x1000 +#define AVB_RBIDX_LEN 0x08 +#define AVB_RBIDX_INITVAL 0 + +#ifdef CONFIG_AVB_ATX +#define ATX_RBIDX_FLAG 0xEFEF +#define ATX_RBIDX_START 0x22000 +#define ATX_RBIDX_ALIGN 0x1000 +#define ATX_RBIDX_LEN 0x08 +#define ATX_RBIDX_INITVAL 0 +#endif + +#define AVB_KBLB_MAGIC "\0KBLB!" +#define AVB_KBLB_MAGIC_LEN 6 + +#if defined(CONFIG_AVB_ATX) && defined(CONFIG_DUAL_BOOTLOADER) +#define BL_RBINDEX_MAGIC "BL_RBINDEX" +#define BL_RBINDEX_MAGIC_LEN 11 +struct bl_rbindex_package { + char magic[BL_RBINDEX_MAGIC_LEN]; + uint32_t rbindex; +}; +#endif + +#ifndef CONFIG_AVB_ATX +#define RPMB_KEY_MAGIC "RPMB" +#endif + +#ifdef CONFIG_AVB_ATX +#define ATX_FUSE_BANK_NUM 4 +#define ATX_FUSE_BANK_MASK 0xFFFF +#define ATX_HASH_LENGTH 14 +#endif + +#define RESULT_ERROR -1 +#define RESULT_OK 0 + +struct kblb_tag { + uint32_t flag; + uint32_t offset; + uint32_t len; +}; +typedef struct kblb_tag kblb_tag_t; + +struct kblb_hdr { + /* avbkey partition magic */ + char magic[AVB_KBLB_MAGIC_LEN]; + /* Rollback index for bootloader is managed by SPL and + * will be stored in RPMB. + */ +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_SPL_BUILD) + kblb_tag_t bootloader_rbk_tags; +#endif + /* public key keyblb tag */ + kblb_tag_t pubk_tag; + /* vbmeta rollback index keyblb tag */ + kblb_tag_t rbk_tags[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS]; +#ifdef CONFIG_AVB_ATX + /* Android Things key versions rollback index keyblb tag */ + kblb_tag_t atx_rbk_tags[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS]; +#endif +}; +typedef struct kblb_hdr kblb_hdr_t; + +#define RPMBKEY_LEN (32 + CAAM_PAD) +#define KEYPACK_MAGIC "!KS" + +struct keyslot_package +{ + char magic[4]; + unsigned int rpmb_keyblob_len; + unsigned char rpmb_keyblob[RPMBKEY_LEN]; +}; + +int gen_rpmb_key(struct keyslot_package *kp); +int read_keyslot_package(struct keyslot_package* kp); +void fill_secure_keyslot_package(struct keyslot_package *kp); +int rpmb_init(void); +int rpmb_read(struct mmc *mmc, uint8_t *buffer, + size_t num_bytes,int64_t offset); +int rpmb_write(struct mmc *mmc, uint8_t *buffer, size_t num_bytes, + int64_t offset); + +int check_rpmb_blob(struct mmc *mmc); +bool rpmbkey_is_set(void); +int fsl_fuse_write(const uint32_t *buffer, uint32_t length, uint32_t offset); +int fsl_fuse_read(uint32_t *buffer, uint32_t length, uint32_t offset); +int permanent_attributes_sha256_hash(unsigned char* output); +struct mmc *get_mmc(void); +#endif diff --git a/lib/avb/fsl/fsl_bootctl.c b/lib/avb/fsl/fsl_bootctl.c new file mode 100755 index 00000000000..8f853bc8073 --- /dev/null +++ b/lib/avb/fsl/fsl_bootctl.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* as libavb's bootctl doesn't have the get_var support + * we add the getvar support on our side ...*/ +#ifndef MAX_PTN +#define MAX_PTN 32 +#endif +#define SLOT_NUM 2 +static char *slot_suffix[SLOT_NUM] = {"_a", "_b"}; + +static int strcmp_l1(const char *s1, const char *s2) { + if (!s1 || !s2) + return -1; + return strncmp(s1, s2, strlen(s1)); +} + +static bool slot_is_bootable(AvbABSlotData* slot) { +#ifdef CONFIG_DUAL_BOOTLOADER + /* The 'bootloader_verified' will be set when the slot has only one chance + * left, which means the slot is bootable even tries_remaining is 0. + */ + return slot->priority > 0 && + (slot->successful_boot || (slot->tries_remaining > 0) + || (slot->bootloader_verified == 1)); +#else + return slot->priority > 0 && + (slot->successful_boot || (slot->tries_remaining > 0)); +#endif +} + +int slotidx_from_suffix(char *suffix) { + int slot = -1; + + if (!strcmp(suffix, "_a") || + !strcmp(suffix, "a")) + slot = 0; + else if (!strcmp(suffix, "_b") || + !strcmp(suffix, "b")) + slot = 1; + + return slot; +} + +bool is_slotvar_avb(char *cmd) { + + assert(cmd != NULL); + if (!strcmp_l1("has-slot:", cmd) || + !strcmp_l1("slot-successful:", cmd) || + !strcmp_l1("slot-count", cmd) || + !strcmp_l1("slot-suffixes", cmd) || + !strcmp_l1("current-slot", cmd) || + !strcmp_l1("slot-unbootable:", cmd) || + !strcmp_l1("slot-retry-count:", cmd)) + return true; + return false; +} + +int get_curr_slot(AvbABData *ab_data) { + if (slot_is_bootable(&ab_data->slots[0]) && + slot_is_bootable(&ab_data->slots[1])) { + if (ab_data->slots[1].priority > ab_data->slots[0].priority) + return 1; + else + return 0; + } else if (slot_is_bootable(&ab_data->slots[0])) + return 0; + else if (slot_is_bootable(&ab_data->slots[1])) + return 1; + else + return -1; +} + +extern struct fastboot_ptentry g_ptable[MAX_PTN]; +extern unsigned int g_pcount; + +static bool has_slot(char *cmd) { + unsigned int n; + char *ptr; + + for (n = 0; n < g_pcount; n++) { + ptr = strstr(g_ptable[n].name, cmd); + if (ptr != NULL) { + ptr += strlen(cmd); + if (!strcmp(ptr, "_a") || !strcmp(ptr, "_b")) + return true; + } + } + return false; +} + +int get_slotvar_avb(AvbABOps *ab_ops, char *cmd, char *buffer, size_t size) { + + AvbABData ab_data; + AvbABSlotData *slot_data; + int slot; + + if ((ab_ops == NULL) || (cmd == NULL) || (buffer == NULL)) + return -1; + + char *str = cmd; + if (!strcmp_l1("has-slot:", cmd)) { + str += strlen("has-slot:"); + if (has_slot(str)) + strlcpy(buffer, "yes", size); + else + strlcpy(buffer, "no", size); + return 0; + + } else if (!strcmp_l1("slot-suffixes", cmd)) { + strlcpy(buffer, "_a,_b", size); + return 0 ; + + } else if (!strcmp_l1("slot-count", cmd)) { + strlcpy(buffer, "2", size); + return 0 ; + } + + /* load ab meta */ + if (ab_ops->read_ab_metadata == NULL || + ab_ops->read_ab_metadata(ab_ops, &ab_data) != AVB_IO_RESULT_OK) { + strlcpy(buffer, "ab data read error", size); + return -1 ; + } + + if (!strcmp_l1("current-slot", cmd)) { + int curr = get_curr_slot(&ab_data); + if (curr >= 0 && curr < SLOT_NUM) + strlcpy(buffer, slot_suffix[curr] + sizeof(unsigned char), size); + else { + strlcpy(buffer, "no bootable slot", size); + return -1; + } + + } else if (!strcmp_l1("slot-successful:", cmd)) { + str += strlen("slot-successful:"); + slot = slotidx_from_suffix(str); + if (slot < 0) { + strlcpy(buffer, "no such slot", size); + return -1; + } else { + slot_data = &ab_data.slots[slot]; + bool succ = (slot_data->successful_boot != 0); + strlcpy(buffer, succ ? "yes" : "no", size); + } + + } else if (!strcmp_l1("slot-unbootable:", cmd)) { + str += strlen("slot-unbootable:"); + slot = slotidx_from_suffix(str); + if (slot < 0) { + strlcpy(buffer, "no such slot", size); + return -1; + } else { + slot_data = &ab_data.slots[slot]; + bool bootable = slot_is_bootable(slot_data); + strlcpy(buffer, bootable ? "no" : "yes", size); + } + + } else if (!strcmp_l1("slot-retry-count:", cmd)) { + str += strlen("slot-retry-count:"); + slot = slotidx_from_suffix(str); + if (slot < 0) { + strlcpy(buffer, "no such slot", size); + return -1; + } + else { + slot_data = &ab_data.slots[slot]; + char var[7]; + sprintf(var, "%d", + slot_data->tries_remaining); + strlcpy(buffer, var, size); + } + + } else { + strlcpy(buffer, "no such slot command", size); + return -1; + } + + return 0; +} + +char *select_slot(AvbABOps *ab_ops) { + AvbABData ab_data; + int curr; + + if (ab_ops == NULL) { + return NULL; + } + + /* load ab meta */ + if (ab_ops->read_ab_metadata == NULL || + ab_ops->read_ab_metadata(ab_ops, &ab_data) != AVB_IO_RESULT_OK) { + return NULL; + } + curr = get_curr_slot(&ab_data); + if (curr >= 0 && curr < SLOT_NUM) + return slot_suffix[curr]; + else + return NULL; +} diff --git a/lib/avb/fsl/fsl_public_key.h b/lib/avb/fsl/fsl_public_key.h new file mode 100644 index 00000000000..f590cdb7115 --- /dev/null +++ b/lib/avb/fsl/fsl_public_key.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_PUBLIC_KEY_H_ +#define __FSL_PUBLIC_KEY_H_ +/*This public key is generated from testkey_rsa4096.pem.*/ +unsigned char fsl_public_key[] = { + 0x00,0x00,0x10,0x00,0x55,0xd9,0x04,0xad, + 0xd8,0x04,0xaf,0xe3,0xd3,0x84,0x6c,0x7e, + 0x0d,0x89,0x3d,0xc2,0x8c,0xd3,0x12,0x55, + 0xe9,0x62,0xc9,0xf1,0x0f,0x5e,0xcc,0x16, + 0x72,0xab,0x44,0x7c,0x2c,0x65,0x4a,0x94, + 0xb5,0x16,0x2b,0x00,0xbb,0x06,0xef,0x13, + 0x07,0x53,0x4c,0xf9,0x64,0xb9,0x28,0x7a, + 0x1b,0x84,0x98,0x88,0xd8,0x67,0xa4,0x23, + 0xf9,0xa7,0x4b,0xdc,0x4a,0x0f,0xf7,0x3a, + 0x18,0xae,0x54,0xa8,0x15,0xfe,0xb0,0xad, + 0xac,0x35,0xda,0x3b,0xad,0x27,0xbc,0xaf, + 0xe8,0xd3,0x2f,0x37,0x34,0xd6,0x51,0x2b, + 0x6c,0x5a,0x27,0xd7,0x96,0x06,0xaf,0x6b, + 0xb8,0x80,0xca,0xfa,0x30,0xb4,0xb1,0x85, + 0xb3,0x4d,0xaa,0xaa,0xc3,0x16,0x34,0x1a, + 0xb8,0xe7,0xc7,0xfa,0xf9,0x09,0x77,0xab, + 0x97,0x93,0xeb,0x44,0xae,0xcf,0x20,0xbc, + 0xf0,0x80,0x11,0xdb,0x23,0x0c,0x47,0x71, + 0xb9,0x6d,0xd6,0x7b,0x60,0x47,0x87,0x16, + 0x56,0x93,0xb7,0xc2,0x2a,0x9a,0xb0,0x4c, + 0x01,0x0c,0x30,0xd8,0x93,0x87,0xf0,0xed, + 0x6e,0x8b,0xbe,0x30,0x5b,0xf6,0xa6,0xaf, + 0xdd,0x80,0x7c,0x45,0x5e,0x8f,0x91,0x93, + 0x5e,0x44,0xfe,0xb8,0x82,0x07,0xee,0x79, + 0xca,0xbf,0x31,0x73,0x62,0x58,0xe3,0xcd, + 0xc4,0xbc,0xc2,0x11,0x1d,0xa1,0x4a,0xbf, + 0xfe,0x27,0x7d,0xa1,0xf6,0x35,0xa3,0x5e, + 0xca,0xdc,0x57,0x2f,0x3e,0xf0,0xc9,0x5d, + 0x86,0x6a,0xf8,0xaf,0x66,0xa7,0xed,0xcd, + 0xb8,0xed,0xa1,0x5f,0xba,0x9b,0x85,0x1a, + 0xd5,0x09,0xae,0x94,0x4e,0x3b,0xcf,0xcb, + 0x5c,0xc9,0x79,0x80,0xf7,0xcc,0xa6,0x4a, + 0xa8,0x6a,0xd8,0xd3,0x31,0x11,0xf9,0xf6, + 0x02,0x63,0x2a,0x1a,0x2d,0xd1,0x1a,0x66, + 0x1b,0x16,0x41,0xbd,0xbd,0xf7,0x4d,0xc0, + 0x4a,0xe5,0x27,0x49,0x5f,0x7f,0x58,0xe3, + 0x27,0x2d,0xe5,0xc9,0x66,0x0e,0x52,0x38, + 0x16,0x38,0xfb,0x16,0xeb,0x53,0x3f,0xe6, + 0xfd,0xe9,0xa2,0x5e,0x25,0x59,0xd8,0x79, + 0x45,0xff,0x03,0x4c,0x26,0xa2,0x00,0x5a, + 0x8e,0xc2,0x51,0xa1,0x15,0xf9,0x7b,0xf4, + 0x5c,0x81,0x9b,0x18,0x47,0x35,0xd8,0x2d, + 0x05,0xe9,0xad,0x0f,0x35,0x74,0x15,0xa3, + 0x8e,0x8b,0xcc,0x27,0xda,0x7c,0x5d,0xe4, + 0xfa,0x04,0xd3,0x05,0x0b,0xba,0x3a,0xb2, + 0x49,0x45,0x2f,0x47,0xc7,0x0d,0x41,0x3f, + 0x97,0x80,0x4d,0x3f,0xc1,0xb5,0xbb,0x70, + 0x5f,0xa7,0x37,0xaf,0x48,0x22,0x12,0x45, + 0x2e,0xf5,0x0f,0x87,0x92,0xe2,0x84,0x01, + 0xf9,0x12,0x0f,0x14,0x15,0x24,0xce,0x89, + 0x99,0xee,0xb9,0xc4,0x17,0x70,0x70,0x15, + 0xea,0xbe,0xc6,0x6c,0x1f,0x62,0xb3,0xf4, + 0x2d,0x16,0x87,0xfb,0x56,0x1e,0x45,0xab, + 0xae,0x32,0xe4,0x5e,0x91,0xed,0x53,0x66, + 0x5e,0xbd,0xed,0xad,0xe6,0x12,0x39,0x0d, + 0x83,0xc9,0xe8,0x6b,0x6c,0x2d,0xa5,0xee, + 0xc4,0x5a,0x66,0xae,0x8c,0x97,0xd7,0x0d, + 0x6c,0x49,0xc7,0xf5,0xc4,0x92,0x31,0x8b, + 0x09,0xee,0x33,0xda,0xa9,0x37,0xb6,0x49, + 0x18,0xf8,0x0e,0x60,0x45,0xc8,0x33,0x91, + 0xef,0x20,0x57,0x10,0xbe,0x78,0x2d,0x83, + 0x26,0xd6,0xca,0x61,0xf9,0x2f,0xe0,0xbf, + 0x05,0x30,0x52,0x5a,0x12,0x1c,0x00,0xa7, + 0x5d,0xcc,0x7c,0x2e,0xc5,0x95,0x8b,0xa3, + 0x3b,0xf0,0x43,0x2e,0x5e,0xdd,0x00,0xdb, + 0x0d,0xb3,0x37,0x99,0xa9,0xcd,0x9c,0xb7, + 0x43,0xf7,0x35,0x44,0x21,0xc2,0x82,0x71, + 0xab,0x8d,0xaa,0xb4,0x41,0x11,0xec,0x1e, + 0x8d,0xfc,0x14,0x82,0x92,0x4e,0x83,0x6a, + 0x0a,0x6b,0x35,0x5e,0x5d,0xe9,0x5c,0xcc, + 0x8c,0xde,0x39,0xd1,0x4a,0x5b,0x5f,0x63, + 0xa9,0x64,0xe0,0x0a,0xcb,0x0b,0xb8,0x5a, + 0x7c,0xc3,0x0b,0xe6,0xbe,0xfe,0x8b,0x0f, + 0x7d,0x34,0x8e,0x02,0x66,0x74,0x01,0x6c, + 0xca,0x76,0xac,0x7c,0x67,0x08,0x2f,0x3f, + 0x1a,0xa6,0x2c,0x60,0xb3,0xff,0xda,0x8d, + 0xb8,0x12,0x0c,0x00,0x7f,0xcc,0x50,0xa1, + 0x5c,0x64,0xa1,0xe2,0x5f,0x32,0x65,0xc9, + 0x9c,0xbe,0xd6,0x0a,0x13,0x87,0x3c,0x2a, + 0x45,0x47,0x0c,0xca,0x42,0x82,0xfa,0x89, + 0x65,0xe7,0x89,0xb4,0x8f,0xf7,0x1e,0xe6, + 0x23,0xa5,0xd0,0x59,0x37,0x79,0x92,0xd7, + 0xce,0x3d,0xfd,0xe3,0xa1,0x0b,0xcf,0x6c, + 0x85,0xa0,0x65,0xf3,0x5c,0xc6,0x4a,0x63, + 0x5f,0x6e,0x3a,0x3a,0x2a,0x8b,0x6a,0xb6, + 0x2f,0xbb,0xf8,0xb2,0x4b,0x62,0xbc,0x1a, + 0x91,0x25,0x66,0xe3,0x69,0xca,0x60,0x49, + 0x0b,0xf6,0x8a,0xbe,0x3e,0x76,0x53,0xc2, + 0x7a,0xa8,0x04,0x17,0x75,0xf1,0xf3,0x03, + 0x62,0x1b,0x85,0xb2,0xb0,0xef,0x80,0x15, + 0xb6,0xd4,0x4e,0xdf,0x71,0xac,0xdb,0x2a, + 0x04,0xd4,0xb4,0x21,0xba,0x65,0x56,0x57, + 0xe8,0xfa,0x84,0xa2,0x7d,0x13,0x0e,0xaf, + 0xd7,0x9a,0x58,0x2a,0xa3,0x81,0x84,0x8d, + 0x09,0xa0,0x6a,0xc1,0xbb,0xd9,0xf5,0x86, + 0xac,0xbd,0x75,0x61,0x09,0xe6,0x8c,0x3d, + 0x77,0xb2,0xed,0x30,0x20,0xe4,0x00,0x1d, + 0x97,0xe8,0xbf,0xc7,0x00,0x1b,0x21,0xb1, + 0x16,0xe7,0x41,0x67,0x2e,0xec,0x38,0xbc, + 0xe5,0x1b,0xb4,0x06,0x23,0x31,0x71,0x1c, + 0x49,0xcd,0x76,0x4a,0x76,0x36,0x8d,0xa3, + 0x89,0x8b,0x4a,0x7a,0xf4,0x87,0xc8,0x15, + 0x0f,0x37,0x39,0xf6,0x6d,0x80,0x19,0xef, + 0x5c,0xa8,0x66,0xce,0x1b,0x16,0x79,0x21, + 0xdf,0xd7,0x31,0x30,0xc4,0x21,0xdd,0x34, + 0x5b,0xd2,0x1a,0x2b,0x3e,0x5d,0xf7,0xea, + 0xca,0x05,0x8e,0xb7,0xcb,0x49,0x2e,0xa0, + 0xe3,0xf4,0xa7,0x48,0x19,0x10,0x9c,0x04, + 0xa7,0xf4,0x28,0x74,0xc8,0x6f,0x63,0x20, + 0x2b,0x46,0x24,0x26,0x19,0x1d,0xd1,0x2c, + 0x31,0x6d,0x5a,0x29,0xa2,0x06,0xa6,0xb2, + 0x41,0xcc,0x0a,0x27,0x96,0x09,0x96,0xac, + 0x47,0x65,0x78,0x68,0x51,0x98,0xd6,0xd8, + 0xa6,0x2d,0xa0,0xcf,0xec,0xe2,0x74,0xf2, + 0x82,0xe3,0x97,0xd9,0x7e,0xd4,0xf8,0x0b, + 0x70,0x43,0x3d,0xb1,0x7b,0x97,0x80,0xd6, + 0xcb,0xd7,0x19,0xbc,0x63,0x0b,0xfd,0x4d, + 0x88,0xfe,0x67,0xac,0xb8,0xcc,0x50,0xb7, + 0x68,0xb3,0x5b,0xd6,0x1e,0x25,0xfc,0x5f, + 0x3c,0x8d,0xb1,0x33,0x7c,0xb3,0x49,0x01, + 0x3f,0x71,0x55,0x0e,0x51,0xba,0x61,0x26, + 0xfa,0xea,0xe5,0xb5,0xe8,0xaa,0xcf,0xcd, + 0x96,0x9f,0xd6,0xc1,0x5f,0x53,0x91,0xad, + 0x05,0xde,0x20,0xe7,0x51,0xda,0x5b,0x95, + 0x67,0xed,0xf4,0xee,0x42,0x65,0x70,0x13, + 0x0b,0x70,0x14,0x1c,0xc9,0xe0,0x19,0xca, + 0x5f,0xf5,0x1d,0x70,0x4b,0x6c,0x06,0x74, + 0xec,0xb5,0x2e,0x77,0xe1,0x74,0xa1,0xa3, + 0x99,0xa0,0x85,0x9e,0xf1,0xac,0xd8,0x7e +}; + + +#endif diff --git a/lib/avb/fsl/utils.c b/lib/avb/fsl/utils.c new file mode 100644 index 00000000000..d3b4254b556 --- /dev/null +++ b/lib/avb/fsl/utils.c @@ -0,0 +1,216 @@ +/* ++ * Copyright (C) 2016 Freescale Semiconductor, Inc. ++ * Copyright 2018 NXP ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ +#include +#include + +#include "debug.h" +#include "utils.h" + +/* + * get margin_pos struct from offset [to the partition start/end] and + * num_bytes to read/write + */ +int get_margin_pos(uint64_t part_start, uint64_t part_end, unsigned long blksz, + margin_pos_t *margin, int64_t offset, size_t num_bytes, + bool allow_partial) { + long off; + if (margin == NULL) + return -1; + + if (blksz == 0 || part_start > part_end) + return -1; + + if (offset < 0) { + margin->blk_start = (offset + 1) / (uint64_t)blksz + part_end; + // offset == -1 means the last byte?, or start need -1 + margin->start = (off = offset % (uint64_t)blksz) == 0 ? + 0 : blksz + off; + if (offset + num_bytes - 1 >= 0) { + if (!allow_partial) + return -1; + margin->blk_end = part_end; + margin->end = blksz - 1; + } else { + // which blk the last byte is in + margin->blk_end = (num_bytes + offset) / + (uint64_t)blksz + part_end; + margin->end = (off = (num_bytes + offset - 1) % + (uint64_t)blksz) == 0 ? + 0 : blksz + off; // last byte + } + } else { + margin->blk_start = offset / (uint64_t)blksz + part_start; + margin->start = offset % (uint64_t)blksz; + margin->blk_end = ((offset + num_bytes - 1) / (uint64_t)blksz) + + part_start ; + margin->end = (offset + num_bytes - 1) % (uint64_t)blksz; + if (margin->blk_end > part_end) { + if (!allow_partial) + return -1; + margin->blk_end = part_end; + margin->end = blksz - 1; + } + } + VDEBUG("bs=%ld, be=%ld, s=%ld, e=%ld\n", + margin->blk_start, margin->blk_end, margin->start, margin->end); + + if (margin->blk_start > part_end || margin->blk_start < part_start) + return -1; + long multi = margin->blk_end - margin->blk_start - 1 + + (margin->start == 0) + (margin->end == blksz -1); + margin->multi = multi > 0 ? multi : 0; + VDEBUG("bm=%ld\n", margin->multi); + return 0; +} + +int read_from_partition_in_bytes(struct blk_desc *fs_dev_desc, + disk_partition_t *info, int64_t offset, + size_t num_bytes, void* buffer, + size_t* out_num_read) +{ + unsigned char *bdata; + unsigned char *out_buf = (unsigned char *)buffer; + unsigned char *dst, *dst64 = NULL; + unsigned long blksz; + unsigned long s, cnt; + size_t num_read = 0; + lbaint_t part_start, part_end, bs, be, bm, blk_num; + margin_pos_t margin; + int ret; + + if(buffer == NULL || out_num_read == NULL) { + printf("NULL pointer error!\n"); + return -1; + } + + blksz = fs_dev_desc->blksz; + part_start = info->start; + part_end = info->start + info->size - 1; + + if (get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, true)) + return -1; + + bs = (lbaint_t)margin.blk_start; + be = (lbaint_t)margin.blk_end; + s = margin.start; + bm = margin.multi; + + /* alloc a blksz mem */ + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) { + printf("Failed to allocate memory!\n"); + return -1; + } + + /* support multi blk read */ + while (bs <= be) { + if (!s && bm > 1) { + dst = out_buf; + /* for mmc blk read alignment */ + dst64 = PTR_ALIGN(out_buf, 64); + if (dst64 != dst) { + dst = dst64; + bm--; + } + blk_num = bm; + cnt = bm * blksz; + bm = 0; /* no more multi blk */ + } else { + blk_num = 1; + cnt = blksz - s; + if (num_read + cnt > num_bytes) + cnt = num_bytes - num_read; + dst = bdata; + } + if (!blk_dread(fs_dev_desc, bs, blk_num, dst)) { + ret = -1; + goto fail; + } + + if (dst == bdata) + memcpy(out_buf, bdata + s, cnt); + else if (dst == dst64) + memcpy(out_buf, dst, cnt); /* internal copy */ + + s = 0; + bs += blk_num; + num_read += cnt; + out_buf += cnt; + } + *out_num_read = num_read; + ret = 0; + +fail: + free(bdata); + return ret; +} + +int write_to_partition_in_bytes(struct blk_desc *fs_dev_desc, + disk_partition_t *info, int64_t offset, + size_t num_bytes, + void* buffer, size_t *out_num_write) +{ + unsigned char *bdata; + unsigned char *in_buf = (unsigned char *)buffer; + unsigned long blksz; + unsigned long s, cnt; + size_t num_write = 0; + lbaint_t part_start, part_end, bs; + margin_pos_t margin; + int ret; + + if(buffer == NULL || out_num_write == NULL) { + printf("NULL pointer error!\n"); + return -1; + } + + blksz = fs_dev_desc->blksz; + part_start = info->start; + part_end = info->start + info->size - 1; + + if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, false)) + return -1; + + bs = (lbaint_t)margin.blk_start; + s = margin.start; + + // alloc a blksz mem + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) + return -1; + + while (num_write < num_bytes) { + memset(bdata, 0, blksz); + cnt = blksz - s; + if (num_write + cnt > num_bytes) + cnt = num_bytes - num_write; + if (!s || cnt != blksz) { //read blk first + if (!blk_dread(fs_dev_desc, bs, 1, + bdata)) { + ret = -1; + goto fail; + } + } + memcpy(bdata + s, in_buf, cnt); //change data + if (!blk_dwrite(fs_dev_desc, bs, 1, bdata)) { + ret = -1; + goto fail; + } + bs++; + num_write += cnt; + in_buf += cnt; + s = 0; + } + *out_num_write = num_write; + ret = 0; + +fail: + free(bdata); + return ret; +} diff --git a/lib/avb/fsl/utils.h b/lib/avb/fsl/utils.h new file mode 100644 index 00000000000..698aec0dc34 --- /dev/null +++ b/lib/avb/fsl/utils.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __UTILS_H__ +#define __UTILS_H__ + +#include + +#define ALIGN_BYTES 64 /*mmc block read/write need 64 bytes aligned */ + +struct margin_pos { + /* which blk the read/write starts */ + uint64_t blk_start; + /* which blk the read/write ends */ + uint64_t blk_end; + /* start position inside the start blk */ + unsigned long start; + /* end position inside the end blk */ + unsigned long end; + /* how many blks can be read/write one time */ + unsigned long multi; +}; +typedef struct margin_pos margin_pos_t; + +int get_margin_pos(uint64_t part_start, uint64_t part_end, unsigned long blksz, + margin_pos_t *margin, int64_t offset, size_t num_bytes, + bool allow_partial); + +int read_from_partition_in_bytes(struct blk_desc *fs_dev_desc, + disk_partition_t *info, + int64_t offset, size_t num_bytes, + void* buffer, size_t* out_num_read); + +int write_to_partition_in_bytes(struct blk_desc *fs_dev_desc, + disk_partition_t *info, int64_t offset, + size_t num_bytes, void* buffer, + size_t *out_num_write); + +#endif diff --git a/lib/avb/libavb/Makefile b/lib/avb/libavb/Makefile new file mode 100644 index 00000000000..7d4ae8e88f1 --- /dev/null +++ b/lib/avb/libavb/Makefile @@ -0,0 +1,21 @@ +ccflags-y += -DAVB_COMPILATION + +ifndef CONFIG_SPL_BUILD +obj-y += avb_descriptor.o \ + avb_kernel_cmdline_descriptor.o \ + avb_sha512.o \ + avb_vbmeta_image.o \ + avb_chain_partition_descriptor.o \ + avb_footer.o \ + avb_property_descriptor.o \ + avb_slot_verify.o \ + avb_hash_descriptor.o \ + avb_rsa.o \ + avb_crypto.o \ + avb_hashtree_descriptor.o \ + avb_sha256.o \ + avb_util.o \ + avb_cmdline.o +endif + +obj-y += avb_crc32.o diff --git a/lib/avb/libavb/avb_chain_partition_descriptor.c b/lib/avb/libavb/avb_chain_partition_descriptor.c new file mode 100644 index 00000000000..3f142325935 --- /dev/null +++ b/lib/avb/libavb/avb_chain_partition_descriptor.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_chain_partition_descriptor.h" +#include "avb_util.h" + +bool avb_chain_partition_descriptor_validate_and_byteswap( + const AvbChainPartitionDescriptor* src, AvbChainPartitionDescriptor* dest) { + uint64_t expected_size; + + avb_memcpy(dest, src, sizeof(AvbChainPartitionDescriptor)); + + if (!avb_descriptor_validate_and_byteswap((const AvbDescriptor*)src, + (AvbDescriptor*)dest)) + return false; + + if (dest->parent_descriptor.tag != AVB_DESCRIPTOR_TAG_CHAIN_PARTITION) { + avb_error("Invalid tag for chain partition descriptor.\n"); + return false; + } + + dest->rollback_index_location = avb_be32toh(dest->rollback_index_location); + dest->partition_name_len = avb_be32toh(dest->partition_name_len); + dest->public_key_len = avb_be32toh(dest->public_key_len); + + if (dest->rollback_index_location < 1) { + avb_error("Invalid rollback index location value.\n"); + return false; + } + + /* Check that partition_name and public_key are fully contained. */ + expected_size = sizeof(AvbChainPartitionDescriptor) - sizeof(AvbDescriptor); + if (!avb_safe_add_to(&expected_size, dest->partition_name_len) || + !avb_safe_add_to(&expected_size, dest->public_key_len)) { + avb_error("Overflow while adding up sizes.\n"); + return false; + } + if (expected_size > dest->parent_descriptor.num_bytes_following) { + avb_error("Descriptor payload size overflow.\n"); + return false; + } + return true; +} diff --git a/lib/avb/libavb/avb_chain_partition_descriptor.h b/lib/avb/libavb/avb_chain_partition_descriptor.h new file mode 100644 index 00000000000..f2c9250156c --- /dev/null +++ b/lib/avb/libavb/avb_chain_partition_descriptor.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_CHAIN_PARTITION_DESCRIPTOR_H_ +#define AVB_CHAIN_PARTITION_DESCRIPTOR_H_ + +#include "avb_descriptor.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* A descriptor containing a pointer to signed integrity data stored + * on another partition. The descriptor contains the partition name in + * question (without the A/B suffix), the public key used to sign the + * integrity data, and rollback index location to use for rollback + * protection. + * + * Following this struct are |partition_name_len| bytes of the + * partition name (UTF-8 encoded) and |public_key_len| bytes of the + * public key. + * + * The |reserved| field is for future expansion and must be set to NUL + * bytes. + */ +typedef struct AvbChainPartitionDescriptor { + AvbDescriptor parent_descriptor; + uint32_t rollback_index_location; + uint32_t partition_name_len; + uint32_t public_key_len; + uint8_t reserved[64]; +} AVB_ATTR_PACKED AvbChainPartitionDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_chain_partition_descriptor_validate_and_byteswap( + const AvbChainPartitionDescriptor* src, + AvbChainPartitionDescriptor* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_CHAIN_PARTITION_DESCRIPTOR_H_ */ diff --git a/lib/avb/libavb/avb_cmdline.c b/lib/avb/libavb/avb_cmdline.c new file mode 100644 index 00000000000..ce331597ae7 --- /dev/null +++ b/lib/avb/libavb/avb_cmdline.c @@ -0,0 +1,440 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_cmdline.h" +#include "avb_sha.h" +#include "avb_util.h" +#include "avb_version.h" + +#define NUM_GUIDS 3 + +/* Substitutes all variables (e.g. $(ANDROID_SYSTEM_PARTUUID)) with + * values. Returns NULL on OOM, otherwise the cmdline with values + * replaced. + */ +char* avb_sub_cmdline(AvbOps* ops, + const char* cmdline, + const char* ab_suffix, + bool using_boot_for_vbmeta, + const AvbCmdlineSubstList* additional_substitutions) { + const char* part_name_str[NUM_GUIDS] = {"system", "boot", "vbmeta"}; + const char* replace_str[NUM_GUIDS] = {"$(ANDROID_SYSTEM_PARTUUID)", + "$(ANDROID_BOOT_PARTUUID)", + "$(ANDROID_VBMETA_PARTUUID)"}; + char* ret = NULL; + AvbIOResult io_ret; + size_t n; + + /* Special-case for when the top-level vbmeta struct is in the boot + * partition. + */ + if (using_boot_for_vbmeta) { + part_name_str[2] = "boot"; + } + + /* Replace unique partition GUIDs */ + for (n = 0; n < NUM_GUIDS; n++) { + char part_name[AVB_PART_NAME_MAX_SIZE]; + char guid_buf[37]; + + if (!avb_str_concat(part_name, + sizeof part_name, + part_name_str[n], + avb_strlen(part_name_str[n]), + ab_suffix, + avb_strlen(ab_suffix))) { + avb_error("Partition name and suffix does not fit.\n"); + goto fail; + } + + io_ret = ops->get_unique_guid_for_partition( + ops, part_name, guid_buf, sizeof guid_buf); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + goto fail; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_error("Error getting unique GUID for partition.\n"); + goto fail; + } + + if (ret == NULL) { + ret = avb_replace(cmdline, replace_str[n], guid_buf); + } else { + char* new_ret = avb_replace(ret, replace_str[n], guid_buf); + avb_free(ret); + ret = new_ret; + } + if (ret == NULL) { + goto fail; + } + } + + avb_assert(ret != NULL); + + /* Replace any additional substitutions. */ + if (additional_substitutions != NULL) { + for (n = 0; n < additional_substitutions->size; ++n) { + char* new_ret = avb_replace(ret, + additional_substitutions->tokens[n], + additional_substitutions->values[n]); + avb_free(ret); + ret = new_ret; + if (ret == NULL) { + goto fail; + } + } + } + + return ret; + +fail: + if (ret != NULL) { + avb_free(ret); + } + return NULL; +} + +static int cmdline_append_option(AvbSlotVerifyData* slot_data, + const char* key, + const char* value) { + size_t offset, key_len, value_len; + char* new_cmdline; + + key_len = avb_strlen(key); + value_len = avb_strlen(value); + + offset = 0; + if (slot_data->cmdline != NULL) { + offset = avb_strlen(slot_data->cmdline); + if (offset > 0) { + offset += 1; + } + } + + new_cmdline = avb_calloc(offset + key_len + value_len + 2); + if (new_cmdline == NULL) { + return 0; + } + if (offset > 0) { + avb_memcpy(new_cmdline, slot_data->cmdline, offset - 1); + new_cmdline[offset - 1] = ' '; + } + avb_memcpy(new_cmdline + offset, key, key_len); + new_cmdline[offset + key_len] = '='; + avb_memcpy(new_cmdline + offset + key_len + 1, value, value_len); + if (slot_data->cmdline != NULL) { + avb_free(slot_data->cmdline); + } + slot_data->cmdline = new_cmdline; + + return 1; +} + +#define AVB_MAX_DIGITS_UINT64 32 + +/* Writes |value| to |digits| in base 10 followed by a NUL byte. + * Returns number of characters written excluding the NUL byte. + */ +static size_t uint64_to_base10(uint64_t value, + char digits[AVB_MAX_DIGITS_UINT64]) { + char rev_digits[AVB_MAX_DIGITS_UINT64]; + size_t n, num_digits; + + for (num_digits = 0; num_digits < AVB_MAX_DIGITS_UINT64 - 1;) { + rev_digits[num_digits++] = avb_div_by_10(&value) + '0'; + if (value == 0) { + break; + } + } + + for (n = 0; n < num_digits; n++) { + digits[n] = rev_digits[num_digits - 1 - n]; + } + digits[n] = '\0'; + return n; +} + +static int cmdline_append_version(AvbSlotVerifyData* slot_data, + const char* key, + uint64_t major_version, + uint64_t minor_version) { + char major_digits[AVB_MAX_DIGITS_UINT64]; + char minor_digits[AVB_MAX_DIGITS_UINT64]; + char combined[AVB_MAX_DIGITS_UINT64 * 2 + 1]; + size_t num_major_digits, num_minor_digits; + + num_major_digits = uint64_to_base10(major_version, major_digits); + num_minor_digits = uint64_to_base10(minor_version, minor_digits); + avb_memcpy(combined, major_digits, num_major_digits); + combined[num_major_digits] = '.'; + avb_memcpy(combined + num_major_digits + 1, minor_digits, num_minor_digits); + combined[num_major_digits + 1 + num_minor_digits] = '\0'; + + return cmdline_append_option(slot_data, key, combined); +} + +static int cmdline_append_uint64_base10(AvbSlotVerifyData* slot_data, + const char* key, + uint64_t value) { + char digits[AVB_MAX_DIGITS_UINT64]; + uint64_to_base10(value, digits); + return cmdline_append_option(slot_data, key, digits); +} + +static int cmdline_append_hex(AvbSlotVerifyData* slot_data, + const char* key, + const uint8_t* data, + size_t data_len) { + int ret; + char* hex_data = avb_bin2hex(data, data_len); + if (hex_data == NULL) { + return 0; + } + ret = cmdline_append_option(slot_data, key, hex_data); + avb_free(hex_data); + return ret; +} + +AvbSlotVerifyResult avb_append_options( + AvbOps* ops, + AvbSlotVerifyData* slot_data, + AvbVBMetaImageHeader* toplevel_vbmeta, + AvbAlgorithmType algorithm_type, + AvbHashtreeErrorMode hashtree_error_mode) { + AvbSlotVerifyResult ret; + const char* verity_mode = NULL; + bool is_device_unlocked; + AvbIOResult io_ret; + + /* Add androidboot.vbmeta.device option. */ + if (!cmdline_append_option(slot_data, + "androidboot.vbmeta.device", + "PARTUUID=$(ANDROID_VBMETA_PARTUUID)")) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + + /* Add androidboot.vbmeta.avb_version option. */ + if (!cmdline_append_version(slot_data, + "androidboot.vbmeta.avb_version", + AVB_VERSION_MAJOR, + AVB_VERSION_MINOR)) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + + /* Set androidboot.avb.device_state to "locked" or "unlocked". */ + io_ret = ops->read_is_device_unlocked(ops, &is_device_unlocked); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_error("Error getting device state.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + if (!cmdline_append_option(slot_data, + "androidboot.vbmeta.device_state", + is_device_unlocked ? "unlocked" : "locked")) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + + /* Set androidboot.vbmeta.{hash_alg, size, digest} - use same hash + * function as is used to sign vbmeta. + */ + switch (algorithm_type) { + /* Explicit fallthrough. */ + case AVB_ALGORITHM_TYPE_NONE: + case AVB_ALGORITHM_TYPE_SHA256_RSA2048: + case AVB_ALGORITHM_TYPE_SHA256_RSA4096: + case AVB_ALGORITHM_TYPE_SHA256_RSA8192: { + size_t n, total_size = 0; + uint8_t vbmeta_digest[AVB_SHA256_DIGEST_SIZE]; + avb_slot_verify_data_calculate_vbmeta_digest( + slot_data, AVB_DIGEST_TYPE_SHA256, vbmeta_digest); + for (n = 0; n < slot_data->num_vbmeta_images; n++) { + total_size += slot_data->vbmeta_images[n].vbmeta_size; + } + if (!cmdline_append_option( + slot_data, "androidboot.vbmeta.hash_alg", "sha256") || + !cmdline_append_uint64_base10( + slot_data, "androidboot.vbmeta.size", total_size) || + !cmdline_append_hex(slot_data, + "androidboot.vbmeta.digest", + vbmeta_digest, + AVB_SHA256_DIGEST_SIZE)) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + } break; + /* Explicit fallthrough. */ + case AVB_ALGORITHM_TYPE_SHA512_RSA2048: + case AVB_ALGORITHM_TYPE_SHA512_RSA4096: + case AVB_ALGORITHM_TYPE_SHA512_RSA8192: { + size_t n, total_size = 0; + uint8_t vbmeta_digest[AVB_SHA512_DIGEST_SIZE]; + avb_slot_verify_data_calculate_vbmeta_digest( + slot_data, AVB_DIGEST_TYPE_SHA512, vbmeta_digest); + for (n = 0; n < slot_data->num_vbmeta_images; n++) { + total_size += slot_data->vbmeta_images[n].vbmeta_size; + } + if (!cmdline_append_option( + slot_data, "androidboot.vbmeta.hash_alg", "sha512") || + !cmdline_append_uint64_base10( + slot_data, "androidboot.vbmeta.size", total_size) || + !cmdline_append_hex(slot_data, + "androidboot.vbmeta.digest", + vbmeta_digest, + AVB_SHA512_DIGEST_SIZE)) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + } break; + case _AVB_ALGORITHM_NUM_TYPES: + avb_assert_not_reached(); + break; + } + + /* Set androidboot.veritymode and androidboot.vbmeta.invalidate_on_error */ + if (toplevel_vbmeta->flags & AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED) { + verity_mode = "disabled"; + } else { + const char* dm_verity_mode = NULL; + char* new_ret; + + switch (hashtree_error_mode) { + case AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE: + if (!cmdline_append_option( + slot_data, "androidboot.vbmeta.invalidate_on_error", "yes")) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + verity_mode = "enforcing"; + dm_verity_mode = "restart_on_corruption"; + break; + case AVB_HASHTREE_ERROR_MODE_RESTART: + verity_mode = "enforcing"; + dm_verity_mode = "restart_on_corruption"; + break; + case AVB_HASHTREE_ERROR_MODE_EIO: + verity_mode = "eio"; + /* For now there's no option to specify the EIO mode. So + * just use 'ignore_zero_blocks' since that's already set + * and dm-verity-target.c supports specifying this multiple + * times. + */ + dm_verity_mode = "ignore_zero_blocks"; + break; + case AVB_HASHTREE_ERROR_MODE_LOGGING: + verity_mode = "logging"; + dm_verity_mode = "ignore_corruption"; + break; + } + new_ret = avb_replace( + slot_data->cmdline, "$(ANDROID_VERITY_MODE)", dm_verity_mode); + avb_free(slot_data->cmdline); + slot_data->cmdline = new_ret; + if (slot_data->cmdline == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + } + if (!cmdline_append_option( + slot_data, "androidboot.veritymode", verity_mode)) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + + ret = AVB_SLOT_VERIFY_RESULT_OK; + +out: + + return ret; +} + +AvbCmdlineSubstList* avb_new_cmdline_subst_list() { + return (AvbCmdlineSubstList*)avb_calloc(sizeof(AvbCmdlineSubstList)); +} + +void avb_free_cmdline_subst_list(AvbCmdlineSubstList* cmdline_subst) { + size_t i; + for (i = 0; i < cmdline_subst->size; ++i) { + avb_free(cmdline_subst->tokens[i]); + avb_free(cmdline_subst->values[i]); + } + cmdline_subst->size = 0; + avb_free(cmdline_subst); +} + +AvbSlotVerifyResult avb_add_root_digest_substitution( + const char* part_name, + const uint8_t* digest, + size_t digest_size, + AvbCmdlineSubstList* out_cmdline_subst) { + const char* kDigestSubPrefix = "$(AVB_"; + const char* kDigestSubSuffix = "_ROOT_DIGEST)"; + size_t part_name_len = avb_strlen(part_name); + size_t list_index = out_cmdline_subst->size; + + avb_assert(part_name_len < AVB_PART_NAME_MAX_SIZE); + avb_assert(digest_size <= AVB_SHA512_DIGEST_SIZE); + if (part_name_len >= AVB_PART_NAME_MAX_SIZE || + digest_size > AVB_SHA512_DIGEST_SIZE) { + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } + + if (out_cmdline_subst->size >= AVB_MAX_NUM_CMDLINE_SUBST) { + /* The list is full. Currently dynamic growth of this list is not supported. + */ + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } + + /* Construct the token to replace in the command line based on the partition + * name. For partition 'foo', this will be '$(AVB_FOO_ROOT_DIGEST)'. + */ + out_cmdline_subst->tokens[list_index] = + avb_strdupv(kDigestSubPrefix, part_name, kDigestSubSuffix, NULL); + if (out_cmdline_subst->tokens[list_index] == NULL) { + goto fail; + } + avb_uppercase(out_cmdline_subst->tokens[list_index]); + + /* The digest value is hex encoded when inserted in the command line. */ + out_cmdline_subst->values[list_index] = avb_bin2hex(digest, digest_size); + if (out_cmdline_subst->values[list_index] == NULL) { + goto fail; + } + + out_cmdline_subst->size++; + return AVB_SLOT_VERIFY_RESULT_OK; + +fail: + if (out_cmdline_subst->tokens[list_index]) { + avb_free(out_cmdline_subst->tokens[list_index]); + } + if (out_cmdline_subst->values[list_index]) { + avb_free(out_cmdline_subst->values[list_index]); + } + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; +} diff --git a/lib/avb/libavb/avb_cmdline.h b/lib/avb/libavb/avb_cmdline.h new file mode 100644 index 00000000000..996535d088c --- /dev/null +++ b/lib/avb/libavb/avb_cmdline.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifdef AVB_INSIDE_LIBAVB_H +#error "You can't include avb_sha.h in the public header libavb.h." +#endif + +#ifndef AVB_COMPILATION +#error "Never include this file, it may only be used from internal avb code." +#endif + +#ifndef AVB_CMDLINE_H_ +#define AVB_CMDLINE_H_ + +#include "avb_ops.h" +#include "avb_slot_verify.h" + +/* Maximum allow length (in bytes) of a partition name, including + * ab_suffix. + */ +#define AVB_PART_NAME_MAX_SIZE 32 + +#define AVB_MAX_NUM_CMDLINE_SUBST 10 + +/* Holds information about command-line substitutions. */ +typedef struct AvbCmdlineSubstList { + size_t size; + char* tokens[AVB_MAX_NUM_CMDLINE_SUBST]; + char* values[AVB_MAX_NUM_CMDLINE_SUBST]; +} AvbCmdlineSubstList; + +/* Substitutes all variables (e.g. $(ANDROID_SYSTEM_PARTUUID)) with + * values. Returns NULL on OOM, otherwise the cmdline with values + * replaced. + */ +char* avb_sub_cmdline(AvbOps* ops, + const char* cmdline, + const char* ab_suffix, + bool using_boot_for_vbmeta, + const AvbCmdlineSubstList* additional_substitutions); + +AvbSlotVerifyResult avb_append_options( + AvbOps* ops, + AvbSlotVerifyData* slot_data, + AvbVBMetaImageHeader* toplevel_vbmeta, + AvbAlgorithmType algorithm_type, + AvbHashtreeErrorMode hashtree_error_mode); + +/* Allocates and initializes a new command line substitution list. Free with + * |avb_free_cmdline_subst_list|. + */ +AvbCmdlineSubstList* avb_new_cmdline_subst_list(void); + +/* Use this instead of |avb_free| to deallocate a AvbCmdlineSubstList. */ +void avb_free_cmdline_subst_list(AvbCmdlineSubstList* cmdline_subst); + +/* Adds a hashtree root digest to be substituted in $(AVB_*_ROOT_DIGEST) + * variables. The partition name differentiates the variable. For example, if + * |part_name| is "foo" then $(AVB_FOO_ROOT_DIGEST) will be substituted with the + * hex encoding of the digest. The substitution will be added to + * |out_cmdline_subst|. Returns AVB_SLOT_VERIFY_RESULT_OK on success. + */ +AvbSlotVerifyResult avb_add_root_digest_substitution( + const char* part_name, + const uint8_t* digest, + size_t digest_size, + AvbCmdlineSubstList* out_cmdline_subst); + +#endif diff --git a/lib/avb/libavb/avb_crc32.c b/lib/avb/libavb/avb_crc32.c new file mode 100644 index 00000000000..7d4cb09035a --- /dev/null +++ b/lib/avb/libavb/avb_crc32.c @@ -0,0 +1,114 @@ +/*- + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or + * code or tables extracted from it, as desired without restriction. + */ + +/* + * First, the polynomial itself and its table of feedback terms. The + * polynomial is + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 + * + * Note that we take it "backwards" and put the highest-order term in + * the lowest-order bit. The X^32 term is "implied"; the LSB is the + * X^31 term, etc. The X^0 term (usually shown as "+1") results in + * the MSB being 1 + * + * Note that the usual hardware shift register implementation, which + * is what we're using (we're merely optimizing it by doing eight-bit + * chunks at a time) shifts bits into the lowest-order term. In our + * implementation, that means shifting towards the right. Why do we + * do it this way? Because the calculated CRC must be transmitted in + * order from highest-order term to lowest-order term. UARTs transmit + * characters in order from LSB to MSB. By storing the CRC this way + * we hand it to the UART in the order low-byte to high-byte; the UART + * sends each low-bit to hight-bit; and the result is transmission bit + * by bit from highest- to lowest-order term without requiring any bit + * shuffling on our part. Reception works similarly + * + * The feedback terms table consists of 256, 32-bit entries. Notes + * + * The table can be generated at runtime if desired; code to do so + * is shown later. It might not be obvious, but the feedback + * terms simply represent the results of eight shift/xor opera + * tions for all combinations of data and CRC register values + * + * The values must be right-shifted by eight bits by the "updcrc + * logic; the shift must be unsigned (bring in zeroes). On some + * hardware you could probably optimize the shift in assembler by + * using byte-swap instructions + * polynomial $edb88320 + * + * + * CRC32 code derived from work by Gary S. Brown. + */ + +#include "avb_sysdeps.h" +#include "avb_util.h" + +/* Code taken from FreeBSD 8 */ + +static uint32_t iavb_crc32_tab[] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d}; + +/* + * A function that calculates the CRC-32 based on the table above is + * given below for documentation purposes. An equivalent implementation + * of this function that's actually used in the kernel can be found + * in sys/libkern.h, where it can be inlined. + */ + +static uint32_t iavb_crc32(uint32_t crc_in, const uint8_t* buf, int size) { + const uint8_t* p = buf; + uint32_t crc; + + crc = crc_in ^ ~0U; + while (size--) + crc = iavb_crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8); + return crc ^ ~0U; +} + +uint32_t avb_crc32(const uint8_t* buf, size_t size) { + return iavb_crc32(0, buf, size); +} diff --git a/lib/avb/libavb/avb_crypto.c b/lib/avb/libavb/avb_crypto.c new file mode 100644 index 00000000000..a99ff80d659 --- /dev/null +++ b/lib/avb/libavb/avb_crypto.c @@ -0,0 +1,372 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_crypto.h" +#include "avb_rsa.h" +#include "avb_sha.h" +#include "avb_util.h" + +/* NOTE: The PKC1-v1.5 padding is a blob of binary DER of ASN.1 and is + * obtained from section 5.2.2 of RFC 4880. + */ + +static const uint8_t + padding_RSA2048_SHA256[AVB_RSA2048_NUM_BYTES - AVB_SHA256_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, + 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20}; + +static const uint8_t + padding_RSA4096_SHA256[AVB_RSA4096_NUM_BYTES - AVB_SHA256_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20}; + +static const uint8_t + padding_RSA8192_SHA256[AVB_RSA8192_NUM_BYTES - AVB_SHA256_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, + 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20}; + +static const uint8_t + padding_RSA2048_SHA512[AVB_RSA2048_NUM_BYTES - AVB_SHA512_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x51, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, 0x05, 0x00, 0x04, 0x40}; + +static const uint8_t + padding_RSA4096_SHA512[AVB_RSA4096_NUM_BYTES - AVB_SHA512_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x51, 0x30, + 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, + 0x05, 0x00, 0x04, 0x40}; + +static const uint8_t + padding_RSA8192_SHA512[AVB_RSA8192_NUM_BYTES - AVB_SHA512_DIGEST_SIZE] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x51, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, 0x05, 0x00, 0x04, 0x40}; + +static AvbAlgorithmData algorithm_data[_AVB_ALGORITHM_NUM_TYPES] = { + /* AVB_ALGORITHM_TYPE_NONE */ + {.padding = NULL, .padding_len = 0, .hash_len = 0}, + /* AVB_ALGORITHM_TYPE_SHA256_RSA2048 */ + {.padding = padding_RSA2048_SHA256, + .padding_len = sizeof(padding_RSA2048_SHA256), + .hash_len = AVB_SHA256_DIGEST_SIZE}, + /* AVB_ALGORITHM_TYPE_SHA256_RSA4096 */ + {.padding = padding_RSA4096_SHA256, + .padding_len = sizeof(padding_RSA4096_SHA256), + .hash_len = AVB_SHA256_DIGEST_SIZE}, + /* AVB_ALGORITHM_TYPE_SHA256_RSA8192 */ + {.padding = padding_RSA8192_SHA256, + .padding_len = sizeof(padding_RSA8192_SHA256), + .hash_len = AVB_SHA256_DIGEST_SIZE}, + /* AVB_ALGORITHM_TYPE_SHA512_RSA2048 */ + {.padding = padding_RSA2048_SHA512, + .padding_len = sizeof(padding_RSA2048_SHA512), + .hash_len = AVB_SHA512_DIGEST_SIZE}, + /* AVB_ALGORITHM_TYPE_SHA512_RSA4096 */ + {.padding = padding_RSA4096_SHA512, + .padding_len = sizeof(padding_RSA4096_SHA512), + .hash_len = AVB_SHA512_DIGEST_SIZE}, + /* AVB_ALGORITHM_TYPE_SHA512_RSA8192 */ + {.padding = padding_RSA8192_SHA512, + .padding_len = sizeof(padding_RSA8192_SHA512), + .hash_len = AVB_SHA512_DIGEST_SIZE}, +}; + +const AvbAlgorithmData* avb_get_algorithm_data(AvbAlgorithmType algorithm) { + if ((size_t)algorithm < _AVB_ALGORITHM_NUM_TYPES) { + return &algorithm_data[algorithm]; + } + return NULL; +} + +bool avb_rsa_public_key_header_validate_and_byteswap( + const AvbRSAPublicKeyHeader* src, AvbRSAPublicKeyHeader* dest) { + avb_memcpy(dest, src, sizeof(AvbRSAPublicKeyHeader)); + + dest->key_num_bits = avb_be32toh(dest->key_num_bits); + dest->n0inv = avb_be32toh(dest->n0inv); + + return true; +} diff --git a/lib/avb/libavb/avb_crypto.h b/lib/avb/libavb/avb_crypto.h new file mode 100644 index 00000000000..30c1e4b9896 --- /dev/null +++ b/lib/avb/libavb/avb_crypto.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_CRYPTO_H_ +#define AVB_CRYPTO_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Size of a RSA-2048 signature. */ +#define AVB_RSA2048_NUM_BYTES 256 + +/* Size of a RSA-4096 signature. */ +#define AVB_RSA4096_NUM_BYTES 512 + +/* Size of a RSA-8192 signature. */ +#define AVB_RSA8192_NUM_BYTES 1024 + +/* Size in bytes of a SHA-1 digest. */ +#define AVB_SHA1_DIGEST_SIZE 20 + +/* Size in bytes of a SHA-256 digest. */ +#define AVB_SHA256_DIGEST_SIZE 32 + +/* Size in bytes of a SHA-512 digest. */ +#define AVB_SHA512_DIGEST_SIZE 64 + +/* Possible digest types supported by libavb routines. */ +typedef enum { + AVB_DIGEST_TYPE_SHA256, + AVB_DIGEST_TYPE_SHA512, +} AvbDigestType; + +/* Algorithms that can be used in the vbmeta image for + * verification. An algorithm consists of a hash type and a signature + * type. + * + * The data used to calculate the hash is the three blocks mentioned + * in the documentation for |AvbVBMetaImageHeader| except for the data + * in the "Authentication data" block. + * + * For signatures with RSA keys, PKCS v1.5 padding is used. The public + * key data is stored in the auxiliary data block, see + * |AvbRSAPublicKeyHeader| for the serialization format. + * + * Each algorithm type is described below: + * + * AVB_ALGORITHM_TYPE_NONE: There is no hash, no signature of the + * data, and no public key. The data cannot be verified. The fields + * |hash_size|, |signature_size|, and |public_key_size| must be zero. + * + * AVB_ALGORITHM_TYPE_SHA256_RSA2048: The hash function used is + * SHA-256, resulting in 32 bytes of hash digest data. This hash is + * signed with a 2048-bit RSA key. The field |hash_size| must be 32, + * |signature_size| must be 256, and the public key data must have + * |key_num_bits| set to 2048. + * + * AVB_ALGORITHM_TYPE_SHA256_RSA4096: Like above, but only with + * a 4096-bit RSA key and |signature_size| set to 512. + * + * AVB_ALGORITHM_TYPE_SHA256_RSA8192: Like above, but only with + * a 8192-bit RSA key and |signature_size| set to 1024. + * + * AVB_ALGORITHM_TYPE_SHA512_RSA2048: The hash function used is + * SHA-512, resulting in 64 bytes of hash digest data. This hash is + * signed with a 2048-bit RSA key. The field |hash_size| must be 64, + * |signature_size| must be 256, and the public key data must have + * |key_num_bits| set to 2048. + * + * AVB_ALGORITHM_TYPE_SHA512_RSA4096: Like above, but only with + * a 4096-bit RSA key and |signature_size| set to 512. + * + * AVB_ALGORITHM_TYPE_SHA512_RSA8192: Like above, but only with + * a 8192-bit RSA key and |signature_size| set to 1024. + */ +typedef enum { + AVB_ALGORITHM_TYPE_NONE, + AVB_ALGORITHM_TYPE_SHA256_RSA2048, + AVB_ALGORITHM_TYPE_SHA256_RSA4096, + AVB_ALGORITHM_TYPE_SHA256_RSA8192, + AVB_ALGORITHM_TYPE_SHA512_RSA2048, + AVB_ALGORITHM_TYPE_SHA512_RSA4096, + AVB_ALGORITHM_TYPE_SHA512_RSA8192, + _AVB_ALGORITHM_NUM_TYPES +} AvbAlgorithmType; + +/* Holds algorithm-specific data. The |padding| is needed by avb_rsa_verify. */ +typedef struct { + const uint8_t* padding; + size_t padding_len; + size_t hash_len; +} AvbAlgorithmData; + +/* Provides algorithm-specific data for a given |algorithm|. Returns NULL if + * |algorithm| is invalid. + */ +const AvbAlgorithmData* avb_get_algorithm_data(AvbAlgorithmType algorithm) + AVB_ATTR_WARN_UNUSED_RESULT; + +/* The header for a serialized RSA public key. + * + * The size of the key is given by |key_num_bits|, for example 2048 + * for a RSA-2048 key. By definition, a RSA public key is the pair (n, + * e) where |n| is the modulus (which can be represented in + * |key_num_bits| bits) and |e| is the public exponent. The exponent + * is not stored since it's assumed to always be 65537. + * + * To optimize verification, the key block includes two precomputed + * values, |n0inv| (fits in 32 bits) and |rr| and can always be + * represented in |key_num_bits|. + + * The value |n0inv| is the value -1/n[0] (mod 2^32). The value |rr| + * is (2^key_num_bits)^2 (mod n). + * + * Following this header is |key_num_bits| bits of |n|, then + * |key_num_bits| bits of |rr|. Both values are stored with most + * significant bit first. Each serialized number takes up + * |key_num_bits|/8 bytes. + * + * All fields in this struct are stored in network byte order when + * serialized. To generate a copy with fields swapped to native byte + * order, use the function avb_rsa_public_key_header_validate_and_byteswap(). + * + * The avb_rsa_verify() function expects a key in this serialized + * format. + * + * The 'avbtool extract_public_key' command can be used to generate a + * serialized RSA public key. + */ +typedef struct AvbRSAPublicKeyHeader { + uint32_t key_num_bits; + uint32_t n0inv; +} AVB_ATTR_PACKED AvbRSAPublicKeyHeader; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + */ +bool avb_rsa_public_key_header_validate_and_byteswap( + const AvbRSAPublicKeyHeader* src, + AvbRSAPublicKeyHeader* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_CRYPTO_H_ */ diff --git a/lib/avb/libavb/avb_descriptor.c b/lib/avb/libavb/avb_descriptor.c new file mode 100644 index 00000000000..4f8e92534e5 --- /dev/null +++ b/lib/avb/libavb/avb_descriptor.c @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_descriptor.h" +#include "avb_util.h" +#include "avb_vbmeta_image.h" + +bool avb_descriptor_validate_and_byteswap(const AvbDescriptor* src, + AvbDescriptor* dest) { + dest->tag = avb_be64toh(src->tag); + dest->num_bytes_following = avb_be64toh(src->num_bytes_following); + + if ((dest->num_bytes_following & 0x07) != 0) { + avb_error("Descriptor size is not divisible by 8.\n"); + return false; + } + return true; +} + +bool avb_descriptor_foreach(const uint8_t* image_data, + size_t image_size, + AvbDescriptorForeachFunc foreach_func, + void* user_data) { + const AvbVBMetaImageHeader* header = NULL; + bool ret = false; + const uint8_t* image_end; + const uint8_t* desc_start; + const uint8_t* desc_end; + const uint8_t* p; + + if (image_data == NULL) { + avb_error("image_data is NULL\n."); + goto out; + } + + if (foreach_func == NULL) { + avb_error("foreach_func is NULL\n."); + goto out; + } + + if (image_size < sizeof(AvbVBMetaImageHeader)) { + avb_error("Length is smaller than header.\n"); + goto out; + } + + /* Ensure magic is correct. */ + if (avb_memcmp(image_data, AVB_MAGIC, AVB_MAGIC_LEN) != 0) { + avb_error("Magic is incorrect.\n"); + goto out; + } + + /* Careful, not byteswapped - also ensure it's aligned properly. */ + avb_assert_aligned(image_data); + header = (const AvbVBMetaImageHeader*)image_data; + image_end = image_data + image_size; + + desc_start = image_data + sizeof(AvbVBMetaImageHeader) + + avb_be64toh(header->authentication_data_block_size) + + avb_be64toh(header->descriptors_offset); + + desc_end = desc_start + avb_be64toh(header->descriptors_size); + + if (desc_start < image_data || desc_start > image_end || + desc_end < image_data || desc_end > image_end || desc_end < desc_start) { + avb_error("Descriptors not inside passed-in data.\n"); + goto out; + } + + for (p = desc_start; p < desc_end;) { + const AvbDescriptor* dh = (const AvbDescriptor*)p; + avb_assert_aligned(dh); + uint64_t nb_following = avb_be64toh(dh->num_bytes_following); + uint64_t nb_total = sizeof(AvbDescriptor) + nb_following; + + if ((nb_total & 7) != 0) { + avb_error("Invalid descriptor length.\n"); + goto out; + } + + if (nb_total + p < desc_start || nb_total + p > desc_end) { + avb_error("Invalid data in descriptors array.\n"); + goto out; + } + + if (foreach_func(dh, user_data) == 0) { + goto out; + } + + p += nb_total; + } + + ret = true; + +out: + return ret; +} + +static bool count_descriptors(const AvbDescriptor* descriptor, + void* user_data) { + size_t* num_descriptors = user_data; + *num_descriptors += 1; + return true; +} + +typedef struct { + size_t descriptor_number; + const AvbDescriptor** descriptors; +} SetDescriptorData; + +static bool set_descriptors(const AvbDescriptor* descriptor, void* user_data) { + SetDescriptorData* data = user_data; + data->descriptors[data->descriptor_number++] = descriptor; + return true; +} + +const AvbDescriptor** avb_descriptor_get_all(const uint8_t* image_data, + size_t image_size, + size_t* out_num_descriptors) { + size_t num_descriptors = 0; + SetDescriptorData data; + + avb_descriptor_foreach( + image_data, image_size, count_descriptors, &num_descriptors); + + data.descriptor_number = 0; + data.descriptors = + avb_calloc(sizeof(const AvbDescriptor*) * (num_descriptors + 1)); + if (data.descriptors == NULL) { + return NULL; + } + avb_descriptor_foreach(image_data, image_size, set_descriptors, &data); + avb_assert(data.descriptor_number == num_descriptors); + + if (out_num_descriptors != NULL) { + *out_num_descriptors = num_descriptors; + } + + return data.descriptors; +} diff --git a/lib/avb/libavb/avb_descriptor.h b/lib/avb/libavb/avb_descriptor.h new file mode 100644 index 00000000000..5d0f0c699fe --- /dev/null +++ b/lib/avb/libavb/avb_descriptor.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_DESCRIPTOR_H_ +#define AVB_DESCRIPTOR_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Well-known descriptor tags. + * + * AVB_DESCRIPTOR_TAG_PROPERTY: see |AvbPropertyDescriptor| struct. + * AVB_DESCRIPTOR_TAG_HASHTREE: see |AvbHashtreeDescriptor| struct. + * AVB_DESCRIPTOR_TAG_HASH: see |AvbHashDescriptor| struct. + * AVB_DESCRIPTOR_TAG_KERNEL_CMDLINE: see |AvbKernelCmdlineDescriptor| struct. + * AVB_DESCRIPTOR_TAG_CHAIN_PARTITION: see |AvbChainPartitionDescriptor| struct. + */ +typedef enum { + AVB_DESCRIPTOR_TAG_PROPERTY, + AVB_DESCRIPTOR_TAG_HASHTREE, + AVB_DESCRIPTOR_TAG_HASH, + AVB_DESCRIPTOR_TAG_KERNEL_CMDLINE, + AVB_DESCRIPTOR_TAG_CHAIN_PARTITION, +} AvbDescriptorTag; + +/* The header for a serialized descriptor. + * + * A descriptor always have two fields, a |tag| (denoting its type, + * see the |AvbDescriptorTag| enumeration) and the size of the bytes + * following, |num_bytes_following|. + * + * For padding, |num_bytes_following| is always a multiple of 8. + */ +typedef struct AvbDescriptor { + uint64_t tag; + uint64_t num_bytes_following; +} AVB_ATTR_PACKED AvbDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_descriptor_validate_and_byteswap( + const AvbDescriptor* src, AvbDescriptor* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Signature for callback function used in avb_descriptor_foreach(). + * The passed in descriptor is given by |descriptor| and the + * |user_data| passed to avb_descriptor_foreach() function is in + * |user_data|. Return true to continue iterating, false to stop + * iterating. + * + * Note that |descriptor| points into the image passed to + * avb_descriptor_foreach() - all fields need to be byteswapped! + */ +typedef bool AvbDescriptorForeachFunc(const AvbDescriptor* descriptor, + void* user_data); + +/* Convenience function to iterate over all descriptors in an vbmeta + * image. + * + * The function given by |foreach_func| will be called for each + * descriptor. The given function should return true to continue + * iterating, false to stop. + * + * The |user_data| parameter will be passed to |foreach_func|. + * + * Returns false if the iteration was short-circuited, that is if + * an invocation of |foreach_func| returned false. + * + * Before using this function, you MUST verify |image_data| with + * avb_vbmeta_image_verify() and reject it unless it's signed by a known + * good public key. Additionally, |image_data| must be word-aligned. + */ +bool avb_descriptor_foreach(const uint8_t* image_data, + size_t image_size, + AvbDescriptorForeachFunc foreach_func, + void* user_data); + +/* Gets all descriptors in a vbmeta image. + * + * The return value is a NULL-pointer terminated array of + * AvbDescriptor pointers. Free with avb_free() when you are done with + * it. If |out_num_descriptors| is non-NULL, the number of descriptors + * will be returned there. + * + * Note that each AvbDescriptor pointer in the array points into + * |image_data| - all fields need to be byteswapped! + * + * Before using this function, you MUST verify |image_data| with + * avb_vbmeta_image_verify() and reject it unless it's signed by a known + * good public key. Additionally, |image_data| must be word-aligned. + */ +const AvbDescriptor** avb_descriptor_get_all(const uint8_t* image_data, + size_t image_size, + size_t* out_num_descriptors) + AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_DESCRIPTOR_H_ */ diff --git a/lib/avb/libavb/avb_footer.c b/lib/avb/libavb/avb_footer.c new file mode 100644 index 00000000000..b8b8211501d --- /dev/null +++ b/lib/avb/libavb/avb_footer.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_footer.h" +#include "avb_util.h" + +bool avb_footer_validate_and_byteswap(const AvbFooter* src, AvbFooter* dest) { + avb_memcpy(dest, src, sizeof(AvbFooter)); + + dest->version_major = avb_be32toh(dest->version_major); + dest->version_minor = avb_be32toh(dest->version_minor); + + dest->original_image_size = avb_be64toh(dest->original_image_size); + dest->vbmeta_offset = avb_be64toh(dest->vbmeta_offset); + dest->vbmeta_size = avb_be64toh(dest->vbmeta_size); + + /* Check that magic is correct. */ + if (avb_safe_memcmp(dest->magic, AVB_FOOTER_MAGIC, AVB_FOOTER_MAGIC_LEN) != + 0) { + avb_error("Footer magic is incorrect.\n"); + return false; + } + + /* Ensure we don't attempt to access any fields if the footer major + * version is not supported. + */ + if (dest->version_major > AVB_FOOTER_VERSION_MAJOR) { + avb_error("No support for footer version.\n"); + return false; + } + + return true; +} diff --git a/lib/avb/libavb/avb_footer.h b/lib/avb/libavb/avb_footer.h new file mode 100644 index 00000000000..e84826fa8f4 --- /dev/null +++ b/lib/avb/libavb/avb_footer.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_FOOTER_H_ +#define AVB_FOOTER_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Magic for the footer. */ +#define AVB_FOOTER_MAGIC "AVBf" +#define AVB_FOOTER_MAGIC_LEN 4 + +/* Size of the footer. */ +#define AVB_FOOTER_SIZE 64 + +/* The current footer version used - keep in sync with avbtool. */ +#define AVB_FOOTER_VERSION_MAJOR 1 +#define AVB_FOOTER_VERSION_MINOR 0 + +/* The struct used as a footer used on partitions, used to find the + * AvbVBMetaImageHeader struct. This struct is always stored at the + * end of a partition. + */ +typedef struct AvbFooter { + /* 0: Four bytes equal to "AVBf" (AVB_FOOTER_MAGIC). */ + uint8_t magic[AVB_FOOTER_MAGIC_LEN]; + /* 4: The major version of the footer struct. */ + uint32_t version_major; + /* 8: The minor version of the footer struct. */ + uint32_t version_minor; + + /* 12: The original size of the image on the partition. */ + uint64_t original_image_size; + + /* 20: The offset of the |AvbVBMetaImageHeader| struct. */ + uint64_t vbmeta_offset; + + /* 28: The size of the vbmeta block (header + auth + aux blocks). */ + uint64_t vbmeta_size; + + /* 36: Padding to ensure struct is size AVB_FOOTER_SIZE bytes. This + * must be set to zeroes. + */ + uint8_t reserved[28]; +} AVB_ATTR_PACKED AvbFooter; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + */ +bool avb_footer_validate_and_byteswap(const AvbFooter* src, AvbFooter* dest) + AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_FOOTER_H_ */ diff --git a/lib/avb/libavb/avb_hash_descriptor.c b/lib/avb/libavb/avb_hash_descriptor.c new file mode 100644 index 00000000000..3a6b8c88091 --- /dev/null +++ b/lib/avb/libavb/avb_hash_descriptor.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_hash_descriptor.h" +#include "avb_util.h" + +bool avb_hash_descriptor_validate_and_byteswap(const AvbHashDescriptor* src, + AvbHashDescriptor* dest) { + uint64_t expected_size; + + avb_memcpy(dest, src, sizeof(AvbHashDescriptor)); + + if (!avb_descriptor_validate_and_byteswap((const AvbDescriptor*)src, + (AvbDescriptor*)dest)) + return false; + + if (dest->parent_descriptor.tag != AVB_DESCRIPTOR_TAG_HASH) { + avb_error("Invalid tag for hash descriptor.\n"); + return false; + } + + dest->image_size = avb_be64toh(dest->image_size); + dest->partition_name_len = avb_be32toh(dest->partition_name_len); + dest->salt_len = avb_be32toh(dest->salt_len); + dest->digest_len = avb_be32toh(dest->digest_len); + dest->flags = avb_be32toh(dest->flags); + + /* Check that partition_name, salt, and digest are fully contained. */ + expected_size = sizeof(AvbHashDescriptor) - sizeof(AvbDescriptor); + if (!avb_safe_add_to(&expected_size, dest->partition_name_len) || + !avb_safe_add_to(&expected_size, dest->salt_len) || + !avb_safe_add_to(&expected_size, dest->digest_len)) { + avb_error("Overflow while adding up sizes.\n"); + return false; + } + if (expected_size > dest->parent_descriptor.num_bytes_following) { + avb_error("Descriptor payload size overflow.\n"); + return false; + } + return true; +} diff --git a/lib/avb/libavb/avb_hash_descriptor.h b/lib/avb/libavb/avb_hash_descriptor.h new file mode 100644 index 00000000000..9ee89971235 --- /dev/null +++ b/lib/avb/libavb/avb_hash_descriptor.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_HASH_DESCRIPTOR_H_ +#define AVB_HASH_DESCRIPTOR_H_ + +#include "avb_descriptor.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Flags for hash descriptors. + * + * AVB_HASH_DESCRIPTOR_FLAGS_DO_NOT_USE_AB: Do not apply the default A/B + * partition logic to this partition. This is intentionally a negative boolean + * because A/B should be both the default and most used in practice. + */ +typedef enum { + AVB_HASH_DESCRIPTOR_FLAGS_DO_NOT_USE_AB = (1 << 0), +} AvbHashDescriptorFlags; + +/* A descriptor containing information about hash for an image. + * + * This descriptor is typically used for boot partitions to verify the + * entire kernel+initramfs image before executing it. + * + * Following this struct are |partition_name_len| bytes of the + * partition name (UTF-8 encoded), |salt_len| bytes of salt, and then + * |digest_len| bytes of the digest. + * + * The |reserved| field is for future expansion and must be set to NUL + * bytes. + * + * Changes in v1.1: + * - flags field is added which supports AVB_HASH_DESCRIPTOR_FLAGS_USE_AB + * - digest_len may be zero, which indicates the use of a persistent digest + */ +typedef struct AvbHashDescriptor { + AvbDescriptor parent_descriptor; + uint64_t image_size; + uint8_t hash_algorithm[32]; + uint32_t partition_name_len; + uint32_t salt_len; + uint32_t digest_len; + uint32_t flags; + uint8_t reserved[60]; +} AVB_ATTR_PACKED AvbHashDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_hash_descriptor_validate_and_byteswap(const AvbHashDescriptor* src, + AvbHashDescriptor* dest) + AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_HASH_DESCRIPTOR_H_ */ diff --git a/lib/avb/libavb/avb_hashtree_descriptor.c b/lib/avb/libavb/avb_hashtree_descriptor.c new file mode 100644 index 00000000000..0822458f84b --- /dev/null +++ b/lib/avb/libavb/avb_hashtree_descriptor.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_hashtree_descriptor.h" +#include "avb_util.h" + +bool avb_hashtree_descriptor_validate_and_byteswap( + const AvbHashtreeDescriptor* src, AvbHashtreeDescriptor* dest) { + uint64_t expected_size; + + avb_memcpy(dest, src, sizeof(AvbHashtreeDescriptor)); + + if (!avb_descriptor_validate_and_byteswap((const AvbDescriptor*)src, + (AvbDescriptor*)dest)) + return false; + + if (dest->parent_descriptor.tag != AVB_DESCRIPTOR_TAG_HASHTREE) { + avb_error("Invalid tag for hashtree descriptor.\n"); + return false; + } + + dest->dm_verity_version = avb_be32toh(dest->dm_verity_version); + dest->image_size = avb_be64toh(dest->image_size); + dest->tree_offset = avb_be64toh(dest->tree_offset); + dest->tree_size = avb_be64toh(dest->tree_size); + dest->data_block_size = avb_be32toh(dest->data_block_size); + dest->hash_block_size = avb_be32toh(dest->hash_block_size); + dest->fec_num_roots = avb_be32toh(dest->fec_num_roots); + dest->fec_offset = avb_be64toh(dest->fec_offset); + dest->fec_size = avb_be64toh(dest->fec_size); + dest->partition_name_len = avb_be32toh(dest->partition_name_len); + dest->salt_len = avb_be32toh(dest->salt_len); + dest->root_digest_len = avb_be32toh(dest->root_digest_len); + dest->flags = avb_be32toh(dest->flags); + + /* Check that partition_name, salt, and root_digest are fully contained. */ + expected_size = sizeof(AvbHashtreeDescriptor) - sizeof(AvbDescriptor); + if (!avb_safe_add_to(&expected_size, dest->partition_name_len) || + !avb_safe_add_to(&expected_size, dest->salt_len) || + !avb_safe_add_to(&expected_size, dest->root_digest_len)) { + avb_error("Overflow while adding up sizes.\n"); + return false; + } + if (expected_size > dest->parent_descriptor.num_bytes_following) { + avb_error("Descriptor payload size overflow.\n"); + return false; + } + return true; +} diff --git a/lib/avb/libavb/avb_hashtree_descriptor.h b/lib/avb/libavb/avb_hashtree_descriptor.h new file mode 100644 index 00000000000..d0f7e2c2885 --- /dev/null +++ b/lib/avb/libavb/avb_hashtree_descriptor.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_HASHTREE_DESCRIPTOR_H_ +#define AVB_HASHTREE_DESCRIPTOR_H_ + +#include "avb_descriptor.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Flags for hashtree descriptors. + * + * AVB_HASHTREE_DESCRIPTOR_FLAGS_DO_NOT_USE_AB: Do not apply the default A/B + * partition logic to this partition. This is intentionally a negative boolean + * because A/B should be both the default and most used in practice. + */ +typedef enum { + AVB_HASHTREE_DESCRIPTOR_FLAGS_DO_NOT_USE_AB = (1 << 0), +} AvbHashtreeDescriptorFlags; + +/* A descriptor containing information about a dm-verity hashtree. + * + * Hash-trees are used to verify large partitions typically containing + * file systems. See + * https://gitlab.com/cryptsetup/cryptsetup/wikis/DMVerity for more + * information about dm-verity. + * + * Following this struct are |partition_name_len| bytes of the + * partition name (UTF-8 encoded), |salt_len| bytes of salt, and then + * |root_digest_len| bytes of the root digest. + * + * The |reserved| field is for future expansion and must be set to NUL + * bytes. + * + * Changes in v1.1: + * - flags field is added which supports AVB_HASHTREE_DESCRIPTOR_FLAGS_USE_AB + * - digest_len may be zero, which indicates the use of a persistent digest + */ +typedef struct AvbHashtreeDescriptor { + AvbDescriptor parent_descriptor; + uint32_t dm_verity_version; + uint64_t image_size; + uint64_t tree_offset; + uint64_t tree_size; + uint32_t data_block_size; + uint32_t hash_block_size; + uint32_t fec_num_roots; + uint64_t fec_offset; + uint64_t fec_size; + uint8_t hash_algorithm[32]; + uint32_t partition_name_len; + uint32_t salt_len; + uint32_t root_digest_len; + uint32_t flags; + uint8_t reserved[60]; +} AVB_ATTR_PACKED AvbHashtreeDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_hashtree_descriptor_validate_and_byteswap( + const AvbHashtreeDescriptor* src, + AvbHashtreeDescriptor* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_HASHTREE_DESCRIPTOR_H_ */ diff --git a/lib/avb/libavb/avb_kernel_cmdline_descriptor.c b/lib/avb/libavb/avb_kernel_cmdline_descriptor.c new file mode 100644 index 00000000000..67521f231ac --- /dev/null +++ b/lib/avb/libavb/avb_kernel_cmdline_descriptor.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_kernel_cmdline_descriptor.h" +#include "avb_util.h" + +bool avb_kernel_cmdline_descriptor_validate_and_byteswap( + const AvbKernelCmdlineDescriptor* src, AvbKernelCmdlineDescriptor* dest) { + uint64_t expected_size; + + avb_memcpy(dest, src, sizeof(AvbKernelCmdlineDescriptor)); + + if (!avb_descriptor_validate_and_byteswap((const AvbDescriptor*)src, + (AvbDescriptor*)dest)) + return false; + + if (dest->parent_descriptor.tag != AVB_DESCRIPTOR_TAG_KERNEL_CMDLINE) { + avb_error("Invalid tag for kernel cmdline descriptor.\n"); + return false; + } + + dest->flags = avb_be32toh(dest->flags); + dest->kernel_cmdline_length = avb_be32toh(dest->kernel_cmdline_length); + + /* Check that kernel_cmdline is fully contained. */ + expected_size = sizeof(AvbKernelCmdlineDescriptor) - sizeof(AvbDescriptor); + if (!avb_safe_add_to(&expected_size, dest->kernel_cmdline_length)) { + avb_error("Overflow while adding up sizes.\n"); + return false; + } + if (expected_size > dest->parent_descriptor.num_bytes_following) { + avb_error("Descriptor payload size overflow.\n"); + return false; + } + + return true; +} diff --git a/lib/avb/libavb/avb_kernel_cmdline_descriptor.h b/lib/avb/libavb/avb_kernel_cmdline_descriptor.h new file mode 100644 index 00000000000..6908b3b19dd --- /dev/null +++ b/lib/avb/libavb/avb_kernel_cmdline_descriptor.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_KERNEL_CMDLINE_DESCRIPTOR_H_ +#define AVB_KERNEL_CMDLINE_DESCRIPTOR_H_ + +#include "avb_descriptor.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Flags for kernel command-line descriptors. + * + * AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_NOT_DISABLED: The + * cmdline will only be applied if hashtree verification is not + * disabled (cf. AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED). + * + * AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_DISABLED: The cmdline + * will only be applied if hashtree verification is disabled + * (cf. AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED). + */ +typedef enum { + AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_NOT_DISABLED = (1 << 0), + AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_DISABLED = (1 << 1) +} AvbKernelCmdlineFlags; + +/* A descriptor containing information to be appended to the kernel + * command-line. + * + * The |flags| field contains flags from the AvbKernelCmdlineFlags + * enumeration. + * + * Following this struct are |kernel_cmdline_len| bytes with the + * kernel command-line (UTF-8 encoded). + */ +typedef struct AvbKernelCmdlineDescriptor { + AvbDescriptor parent_descriptor; + uint32_t flags; + uint32_t kernel_cmdline_length; +} AVB_ATTR_PACKED AvbKernelCmdlineDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_kernel_cmdline_descriptor_validate_and_byteswap( + const AvbKernelCmdlineDescriptor* src, + AvbKernelCmdlineDescriptor* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_KERNEL_CMDLINE_DESCRIPTOR_H_ */ diff --git a/lib/avb/libavb/avb_ops.h b/lib/avb/libavb/avb_ops.h new file mode 100644 index 00000000000..77f7ec3c127 --- /dev/null +++ b/lib/avb/libavb/avb_ops.h @@ -0,0 +1,311 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_OPS_H_ +#define AVB_OPS_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Well-known names of named persistent values. */ +#define AVB_NPV_PERSISTENT_DIGEST_PREFIX "avb.persistent_digest." + +/* Return codes used for I/O operations. + * + * AVB_IO_RESULT_OK is returned if the requested operation was + * successful. + * + * AVB_IO_RESULT_ERROR_IO is returned if the underlying hardware (disk + * or other subsystem) encountered an I/O error. + * + * AVB_IO_RESULT_ERROR_OOM is returned if unable to allocate memory. + * + * AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION is returned if the requested + * partition does not exist. + * + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION is returned if the + * range of bytes requested to be read or written is outside the range + * of the partition. + * + * AVB_IO_RESULT_ERROR_NO_SUCH_VALUE is returned if a named persistent value + * does not exist. + * + * AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE is returned if a named persistent + * value size is not supported or does not match the expected size. + * + * AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE is returned if a buffer is too small + * for the requested operation. + */ +typedef enum { + AVB_IO_RESULT_OK, + AVB_IO_RESULT_ERROR_OOM, + AVB_IO_RESULT_ERROR_IO, + AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION, + AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION, + AVB_IO_RESULT_ERROR_NO_SUCH_VALUE, + AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE, + AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE, +} AvbIOResult; + +struct AvbOps; +typedef struct AvbOps AvbOps; + +/* Forward-declaration of operations in libavb_ab. */ +struct AvbABOps; + +/* Forward-declaration of operations in libavb_atx. */ +struct AvbAtxOps; + +/* High-level operations/functions/methods that are platform + * dependent. + * + * Operations may be added in the future so when implementing it + * always make sure to zero out sizeof(AvbOps) bytes of the struct to + * ensure that unimplemented operations are set to NULL. + */ +struct AvbOps { + /* This pointer can be used by the application/bootloader using + * libavb and is typically used in each operation to get a pointer + * to platform-specific resources. It cannot be used by libraries. + */ + void* user_data; + + /* If libavb_ab is used, this should point to the + * AvbABOps. Otherwise it must be set to NULL. + */ + struct AvbABOps* ab_ops; + + /* If libavb_atx is used, this should point to the + * AvbAtxOps. Otherwise it must be set to NULL. + */ + struct AvbAtxOps* atx_ops; + + /* Reads |num_bytes| from offset |offset| from partition with name + * |partition| (NUL-terminated UTF-8 string). If |offset| is + * negative, its absolute value should be interpreted as the number + * of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * |offset| is outside the partition, and AVB_IO_RESULT_ERROR_IO if + * there was an I/O error from the underlying I/O subsystem. If the + * operation succeeds as requested AVB_IO_RESULT_OK is returned and + * the data is available in |buffer|. + * + * The only time partial I/O may occur is if reading beyond the end + * of the partition. In this case the value returned in + * |out_num_read| may be smaller than |num_bytes|. + */ + AvbIOResult (*read_from_partition)(AvbOps* ops, + const char* partition, + int64_t offset, + size_t num_bytes, + void* buffer, + size_t* out_num_read); + + /* Gets the starting pointer of a partition that is pre-loaded in memory, and + * save it to |out_pointer|. The preloaded partition is expected to be + * |num_bytes|, where the actual preloaded byte count is returned in + * |out_num_bytes_preloaded|. |out_num_bytes_preloaded| must be no larger than + * |num_bytes|. + * + * This provides an alternative way to access a partition that is preloaded + * into memory without a full memory copy. When this function pointer is not + * set (has value NULL), or when the |out_pointer| is set to NULL as a result, + * |read_from_partition| will be used as the fallback. This function is mainly + * used for accessing the entire partition content to calculate its hash. + * + * Preloaded partition data must outlive the lifespan of the + * |AvbSlotVerifyData| structure that |avb_slot_verify| outputs. + */ + AvbIOResult (*get_preloaded_partition)(AvbOps* ops, + const char* partition, + size_t num_bytes, + uint8_t** out_pointer, + size_t* out_num_bytes_preloaded); + + /* Writes |num_bytes| from |bffer| at offset |offset| to partition + * with name |partition| (NUL-terminated UTF-8 string). If |offset| + * is negative, its absolute value should be interpreted as the + * number of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * byterange goes outside the partition, and AVB_IO_RESULT_ERROR_IO + * if there was an I/O error from the underlying I/O subsystem. If + * the operation succeeds as requested AVB_IO_RESULT_OK is + * returned. + * + * This function never does any partial I/O, it either transfers all + * of the requested bytes or returns an error. + */ + AvbIOResult (*write_to_partition)(AvbOps* ops, + const char* partition, + int64_t offset, + size_t num_bytes, + const void* buffer); + + /* Checks if the given public key used to sign the 'vbmeta' + * partition is trusted. Boot loaders typically compare this with + * embedded key material generated with 'avbtool + * extract_public_key'. + * + * The public key is in the array pointed to by |public_key_data| + * and is of |public_key_length| bytes. + * + * If there is no public key metadata (set with the avbtool option + * --public_key_metadata) then |public_key_metadata| will be set to + * NULL. Otherwise this field points to the data which is + * |public_key_metadata_length| bytes long. + * + * If AVB_IO_RESULT_OK is returned then |out_is_trusted| is set - + * true if trusted or false if untrusted. + */ + AvbIOResult (*validate_vbmeta_public_key)(AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted); + + /* Gets the rollback index corresponding to the location given by + * |rollback_index_location|. The value is returned in + * |out_rollback_index|. Returns AVB_IO_RESULT_OK if the rollback + * index was retrieved, otherwise an error code. + * + * A device may have a limited amount of rollback index locations (say, + * one or four) so may error out if |rollback_index_location| exceeds + * this number. + */ + AvbIOResult (*read_rollback_index)(AvbOps* ops, + size_t rollback_index_location, + uint64_t* out_rollback_index); + + /* Sets the rollback index corresponding to the location given by + * |rollback_index_location| to |rollback_index|. Returns + * AVB_IO_RESULT_OK if the rollback index was set, otherwise an + * error code. + * + * A device may have a limited amount of rollback index locations (say, + * one or four) so may error out if |rollback_index_location| exceeds + * this number. + */ + AvbIOResult (*write_rollback_index)(AvbOps* ops, + size_t rollback_index_location, + uint64_t rollback_index); + + /* Gets whether the device is unlocked. The value is returned in + * |out_is_unlocked| (true if unlocked, false otherwise). Returns + * AVB_IO_RESULT_OK if the state was retrieved, otherwise an error + * code. + */ + AvbIOResult (*read_is_device_unlocked)(AvbOps* ops, bool* out_is_unlocked); + + /* Gets the unique partition GUID for a partition with name in + * |partition| (NUL-terminated UTF-8 string). The GUID is copied as + * a string into |guid_buf| of size |guid_buf_size| and will be NUL + * terminated. The string must be lower-case and properly + * hyphenated. For example: + * + * 527c1c6d-6361-4593-8842-3c78fcd39219 + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ + AvbIOResult (*get_unique_guid_for_partition)(AvbOps* ops, + const char* partition, + char* guid_buf, + size_t guid_buf_size); + + /* Gets the size of a partition with the name in |partition| + * (NUL-terminated UTF-8 string). Returns the value in + * |out_size_num_bytes|. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ + AvbIOResult (*get_size_of_partition)(AvbOps* ops, + const char* partition, + uint64_t* out_size_num_bytes); + + /* Reads a persistent value corresponding to the given |name|. The value is + * returned in |out_buffer| which must point to |buffer_size| bytes. On + * success |out_num_bytes_read| contains the number of bytes read into + * |out_buffer|. If AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE is returned, + * |out_num_bytes_read| contains the number of bytes that would have been read + * which can be used to allocate a buffer. + * + * The |buffer_size| may be zero and the |out_buffer| may be NULL, but if + * |out_buffer| is NULL then |buffer_size| *must* be zero. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + * + * If the value does not exist, is not supported, or is not populated, returns + * AVB_IO_RESULT_ERROR_NO_SUCH_VALUE. If |buffer_size| is smaller than the + * size of the stored value, returns AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE. + * + * This operation is currently only used to support persistent digests. If a + * device does not use persistent digests this function pointer can be set to + * NULL. + */ + AvbIOResult (*read_persistent_value)(AvbOps* ops, + const char* name, + size_t buffer_size, + uint8_t* out_buffer, + size_t* out_num_bytes_read); + + /* Writes a persistent value corresponding to the given |name|. The value is + * supplied in |value| which must point to |value_size| bytes. Any existing + * value with the same name is overwritten. If |value_size| is zero, future + * calls to |read_persistent_value| will return + * AVB_IO_RESULT_ERROR_NO_SUCH_VALUE. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + * + * If the value |name| is not supported, returns + * AVB_IO_RESULT_ERROR_NO_SUCH_VALUE. If the |value_size| is not supported, + * returns AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE. + * + * This operation is currently only used to support persistent digests. If a + * device does not use persistent digests this function pointer can be set to + * NULL. + */ + AvbIOResult (*write_persistent_value)(AvbOps* ops, + const char* name, + size_t value_size, + const uint8_t* value); +}; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_OPS_H_ */ diff --git a/lib/avb/libavb/avb_property_descriptor.c b/lib/avb/libavb/avb_property_descriptor.c new file mode 100644 index 00000000000..7eba2c00b07 --- /dev/null +++ b/lib/avb/libavb/avb_property_descriptor.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_property_descriptor.h" +#include "avb_util.h" + +bool avb_property_descriptor_validate_and_byteswap( + const AvbPropertyDescriptor* src, AvbPropertyDescriptor* dest) { + uint64_t expected_size; + + avb_memcpy(dest, src, sizeof(AvbPropertyDescriptor)); + + if (!avb_descriptor_validate_and_byteswap((const AvbDescriptor*)src, + (AvbDescriptor*)dest)) + return false; + + if (dest->parent_descriptor.tag != AVB_DESCRIPTOR_TAG_PROPERTY) { + avb_error("Invalid tag for property descriptor.\n"); + return false; + } + + dest->key_num_bytes = avb_be64toh(dest->key_num_bytes); + dest->value_num_bytes = avb_be64toh(dest->value_num_bytes); + + /* Check that key and value are fully contained. */ + expected_size = sizeof(AvbPropertyDescriptor) - sizeof(AvbDescriptor) + 2; + if (!avb_safe_add_to(&expected_size, dest->key_num_bytes) || + !avb_safe_add_to(&expected_size, dest->value_num_bytes)) { + avb_error("Overflow while adding up sizes.\n"); + return false; + } + if (expected_size > dest->parent_descriptor.num_bytes_following) { + avb_error("Descriptor payload size overflow.\n"); + return false; + } + + return true; +} + +typedef struct { + const char* key; + size_t key_size; + const char* ret_value; + size_t ret_value_size; +} PropertyIteratorData; + +static bool property_lookup_desc_foreach(const AvbDescriptor* header, + void* user_data) { + PropertyIteratorData* data = (PropertyIteratorData*)user_data; + AvbPropertyDescriptor prop_desc; + const uint8_t* p; + bool ret = true; + + if (header->tag != AVB_DESCRIPTOR_TAG_PROPERTY) { + goto out; + } + + if (!avb_property_descriptor_validate_and_byteswap( + (const AvbPropertyDescriptor*)header, &prop_desc)) { + goto out; + } + + p = (const uint8_t*)header; + if (p[sizeof(AvbPropertyDescriptor) + prop_desc.key_num_bytes] != 0) { + avb_error("No terminating NUL byte in key.\n"); + goto out; + } + + if (data->key_size == prop_desc.key_num_bytes) { + if (avb_memcmp(p + sizeof(AvbPropertyDescriptor), + data->key, + data->key_size) == 0) { + data->ret_value = (const char*)(p + sizeof(AvbPropertyDescriptor) + + prop_desc.key_num_bytes + 1); + data->ret_value_size = prop_desc.value_num_bytes; + /* Stop iterating. */ + ret = false; + goto out; + } + } + +out: + return ret; +} + +const char* avb_property_lookup(const uint8_t* image_data, + size_t image_size, + const char* key, + size_t key_size, + size_t* out_value_size) { + PropertyIteratorData data; + + if (key_size == 0) { + key_size = avb_strlen(key); + } + + data.key = key; + data.key_size = key_size; + + if (avb_descriptor_foreach( + image_data, image_size, property_lookup_desc_foreach, &data) == 0) { + if (out_value_size != NULL) { + *out_value_size = data.ret_value_size; + } + return data.ret_value; + } + + if (out_value_size != NULL) { + *out_value_size = 0; + } + return NULL; +} + +bool avb_property_lookup_uint64(const uint8_t* image_data, + size_t image_size, + const char* key, + size_t key_size, + uint64_t* out_value) { + const char* value; + bool ret = false; + uint64_t parsed_val; + int base; + int n; + + value = avb_property_lookup(image_data, image_size, key, key_size, NULL); + if (value == NULL) { + goto out; + } + + base = 10; + if (avb_memcmp(value, "0x", 2) == 0) { + base = 16; + value += 2; + } + + parsed_val = 0; + for (n = 0; value[n] != '\0'; n++) { + int c = value[n]; + int digit; + + parsed_val *= base; + + if (c >= '0' && c <= '9') { + digit = c - '0'; + } else if (base == 16 && c >= 'a' && c <= 'f') { + digit = c - 'a' + 10; + } else if (base == 16 && c >= 'A' && c <= 'F') { + digit = c - 'A' + 10; + } else { + avb_error("Invalid digit.\n"); + goto out; + } + + parsed_val += digit; + } + + ret = true; + if (out_value != NULL) { + *out_value = parsed_val; + } + +out: + return ret; +} diff --git a/lib/avb/libavb/avb_property_descriptor.h b/lib/avb/libavb/avb_property_descriptor.h new file mode 100644 index 00000000000..a2fef696a9a --- /dev/null +++ b/lib/avb/libavb/avb_property_descriptor.h @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_PROPERTY_DESCRIPTOR_H_ +#define AVB_PROPERTY_DESCRIPTOR_H_ + +#include "avb_descriptor.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* A descriptor for properties (free-form key/value pairs). + * + * Following this struct are |key_num_bytes| bytes of key data, + * followed by a NUL byte, then |value_num_bytes| bytes of value data, + * followed by a NUL byte and then enough padding to make the combined + * size a multiple of 8. + */ +typedef struct AvbPropertyDescriptor { + AvbDescriptor parent_descriptor; + uint64_t key_num_bytes; + uint64_t value_num_bytes; +} AVB_ATTR_PACKED AvbPropertyDescriptor; + +/* Copies |src| to |dest| and validates, byte-swapping fields in the + * process if needed. Returns true if valid, false if invalid. + * + * Data following the struct is not validated nor copied. + */ +bool avb_property_descriptor_validate_and_byteswap( + const AvbPropertyDescriptor* src, + AvbPropertyDescriptor* dest) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Convenience function for looking up the value for a property with + * name |key| in a vbmeta image. If |key_size| is 0, |key| must be + * NUL-terminated. + * + * The |image_data| parameter must be a pointer to a vbmeta image of + * size |image_size|. + * + * This function returns a pointer to the value inside the passed-in + * image or NULL if not found. Note that the value is always + * guaranteed to be followed by a NUL byte. + * + * If the value was found and |out_value_size| is not NULL, the size + * of the value is returned there. + * + * This function is O(n) in number of descriptors so if you need to + * look up a lot of values, you may want to build a more efficient + * lookup-table by manually walking all descriptors using + * avb_descriptor_foreach(). + * + * Before using this function, you MUST verify |image_data| with + * avb_vbmeta_image_verify() and reject it unless it's signed by a + * known good public key. + */ +const char* avb_property_lookup(const uint8_t* image_data, + size_t image_size, + const char* key, + size_t key_size, + size_t* out_value_size) + AVB_ATTR_WARN_UNUSED_RESULT; + +/* Like avb_property_lookup() but parses the intial portions of the + * value as an unsigned 64-bit integer. Both decimal and hexadecimal + * representations (e.g. "0x2a") are supported. Returns false on + * failure and true on success. On success, the parsed value is + * returned in |out_value|. + */ +bool avb_property_lookup_uint64(const uint8_t* image_data, + size_t image_size, + const char* key, + size_t key_size, + uint64_t* out_value) + AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_PROPERTY_DESCRIPTOR_H_ */ diff --git a/lib/avb/libavb/avb_rsa.c b/lib/avb/libavb/avb_rsa.c new file mode 100644 index 00000000000..f4cb322b9ea --- /dev/null +++ b/lib/avb/libavb/avb_rsa.c @@ -0,0 +1,299 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Implementation of RSA signature verification which uses a pre-processed + * key for computation. The code extends libmincrypt RSA verification code to + * support multiple RSA key lengths and hash digest algorithms. + */ + +#include "avb_rsa.h" +#include "avb_sha.h" +#include "avb_util.h" +#include "avb_vbmeta_image.h" + +typedef struct IAvbKey { + unsigned int len; /* Length of n[] in number of uint32_t */ + uint32_t n0inv; /* -1 / n[0] mod 2^32 */ + uint32_t* n; /* modulus as array (host-byte order) */ + uint32_t* rr; /* R^2 as array (host-byte order) */ +} IAvbKey; + +static IAvbKey* iavb_parse_key_data(const uint8_t* data, size_t length) { + AvbRSAPublicKeyHeader h; + IAvbKey* key = NULL; + size_t expected_length; + unsigned int i; + const uint8_t* n; + const uint8_t* rr; + + if (!avb_rsa_public_key_header_validate_and_byteswap( + (const AvbRSAPublicKeyHeader*)data, &h)) { + avb_error("Invalid key.\n"); + goto fail; + } + + if (!(h.key_num_bits == 2048 || h.key_num_bits == 4096 || + h.key_num_bits == 8192)) { + avb_error("Unexpected key length.\n"); + goto fail; + } + + expected_length = sizeof(AvbRSAPublicKeyHeader) + 2 * h.key_num_bits / 8; + if (length != expected_length) { + avb_error("Key does not match expected length.\n"); + goto fail; + } + + n = data + sizeof(AvbRSAPublicKeyHeader); + rr = data + sizeof(AvbRSAPublicKeyHeader) + h.key_num_bits / 8; + + /* Store n and rr following the key header so we only have to do one + * allocation. + */ + key = (IAvbKey*)(avb_malloc(sizeof(IAvbKey) + 2 * h.key_num_bits / 8)); + if (key == NULL) { + goto fail; + } + + key->len = h.key_num_bits / 32; + key->n0inv = h.n0inv; + key->n = (uint32_t*)(key + 1); /* Skip ahead sizeof(IAvbKey) bytes. */ + key->rr = key->n + key->len; + + /* Crypto-code below (modpowF4() and friends) expects the key in + * little-endian format (rather than the format we're storing the + * key in), so convert it. + */ + for (i = 0; i < key->len; i++) { + key->n[i] = avb_be32toh(((uint32_t*)n)[key->len - i - 1]); + key->rr[i] = avb_be32toh(((uint32_t*)rr)[key->len - i - 1]); + } + return key; + +fail: + if (key != NULL) { + avb_free(key); + } + return NULL; +} + +static void iavb_free_parsed_key(IAvbKey* key) { + avb_free(key); +} + +/* a[] -= mod */ +static void subM(const IAvbKey* key, uint32_t* a) { + int64_t A = 0; + uint32_t i; + for (i = 0; i < key->len; ++i) { + A += (uint64_t)a[i] - key->n[i]; + a[i] = (uint32_t)A; + A >>= 32; + } +} + +/* return a[] >= mod */ +static int geM(const IAvbKey* key, uint32_t* a) { + uint32_t i; + for (i = key->len; i;) { + --i; + if (a[i] < key->n[i]) { + return 0; + } + if (a[i] > key->n[i]) { + return 1; + } + } + return 1; /* equal */ +} + +/* montgomery c[] += a * b[] / R % mod */ +static void montMulAdd(const IAvbKey* key, + uint32_t* c, + const uint32_t a, + const uint32_t* b) { + uint64_t A = (uint64_t)a * b[0] + c[0]; + uint32_t d0 = (uint32_t)A * key->n0inv; + uint64_t B = (uint64_t)d0 * key->n[0] + (uint32_t)A; + uint32_t i; + + for (i = 1; i < key->len; ++i) { + A = (A >> 32) + (uint64_t)a * b[i] + c[i]; + B = (B >> 32) + (uint64_t)d0 * key->n[i] + (uint32_t)A; + c[i - 1] = (uint32_t)B; + } + + A = (A >> 32) + (B >> 32); + + c[i - 1] = (uint32_t)A; + + if (A >> 32) { + subM(key, c); + } +} + +/* montgomery c[] = a[] * b[] / R % mod */ +static void montMul(const IAvbKey* key, uint32_t* c, uint32_t* a, uint32_t* b) { + uint32_t i; + for (i = 0; i < key->len; ++i) { + c[i] = 0; + } + for (i = 0; i < key->len; ++i) { + montMulAdd(key, c, a[i], b); + } +} + +/* In-place public exponentiation. (65537} + * Input and output big-endian byte array in inout. + */ +static void modpowF4(const IAvbKey* key, uint8_t* inout) { + uint32_t* a = (uint32_t*)avb_malloc(key->len * sizeof(uint32_t)); + uint32_t* aR = (uint32_t*)avb_malloc(key->len * sizeof(uint32_t)); + uint32_t* aaR = (uint32_t*)avb_malloc(key->len * sizeof(uint32_t)); + if (a == NULL || aR == NULL || aaR == NULL) { + goto out; + } + + uint32_t* aaa = aaR; /* Re-use location. */ + int i; + + /* Convert from big endian byte array to little endian word array. */ + for (i = 0; i < (int)key->len; ++i) { + uint32_t tmp = (inout[((key->len - 1 - i) * 4) + 0] << 24) | + (inout[((key->len - 1 - i) * 4) + 1] << 16) | + (inout[((key->len - 1 - i) * 4) + 2] << 8) | + (inout[((key->len - 1 - i) * 4) + 3] << 0); + a[i] = tmp; + } + + montMul(key, aR, a, key->rr); /* aR = a * RR / R mod M */ + for (i = 0; i < 16; i += 2) { + montMul(key, aaR, aR, aR); /* aaR = aR * aR / R mod M */ + montMul(key, aR, aaR, aaR); /* aR = aaR * aaR / R mod M */ + } + montMul(key, aaa, aR, a); /* aaa = aR * a / R mod M */ + + /* Make sure aaa < mod; aaa is at most 1x mod too large. */ + if (geM(key, aaa)) { + subM(key, aaa); + } + + /* Convert to bigendian byte array */ + for (i = (int)key->len - 1; i >= 0; --i) { + uint32_t tmp = aaa[i]; + *inout++ = (uint8_t)(tmp >> 24); + *inout++ = (uint8_t)(tmp >> 16); + *inout++ = (uint8_t)(tmp >> 8); + *inout++ = (uint8_t)(tmp >> 0); + } + +out: + if (a != NULL) { + avb_free(a); + } + if (aR != NULL) { + avb_free(aR); + } + if (aaR != NULL) { + avb_free(aaR); + } +} + +/* Verify a RSA PKCS1.5 signature against an expected hash. + * Returns false on failure, true on success. + */ +bool avb_rsa_verify(const uint8_t* key, + size_t key_num_bytes, + const uint8_t* sig, + size_t sig_num_bytes, + const uint8_t* hash, + size_t hash_num_bytes, + const uint8_t* padding, + size_t padding_num_bytes) { + uint8_t* buf = NULL; + IAvbKey* parsed_key = NULL; + bool success = false; + + if (key == NULL || sig == NULL || hash == NULL || padding == NULL) { + avb_error("Invalid input.\n"); + goto out; + } + + parsed_key = iavb_parse_key_data(key, key_num_bytes); + if (parsed_key == NULL) { + avb_error("Error parsing key.\n"); + goto out; + } + + if (sig_num_bytes != (parsed_key->len * sizeof(uint32_t))) { + avb_error("Signature length does not match key length.\n"); + goto out; + } + + if (padding_num_bytes != sig_num_bytes - hash_num_bytes) { + avb_error("Padding length does not match hash and signature lengths.\n"); + goto out; + } + + buf = (uint8_t*)avb_malloc(sig_num_bytes); + if (buf == NULL) { + avb_error("Error allocating memory.\n"); + goto out; + } + avb_memcpy(buf, sig, sig_num_bytes); + + modpowF4(parsed_key, buf); + + /* Check padding bytes. + * + * Even though there are probably no timing issues here, we use + * avb_safe_memcmp() just to be on the safe side. + */ + if (avb_safe_memcmp(buf, padding, padding_num_bytes)) { + avb_error("Padding check failed.\n"); + goto out; + } + + /* Check hash. */ + if (avb_safe_memcmp(buf + padding_num_bytes, hash, hash_num_bytes)) { + avb_error("Hash check failed.\n"); + goto out; + } + + success = true; + +out: + if (parsed_key != NULL) { + iavb_free_parsed_key(parsed_key); + } + if (buf != NULL) { + avb_free(buf); + } + return success; +} diff --git a/lib/avb/libavb/avb_rsa.h b/lib/avb/libavb/avb_rsa.h new file mode 100644 index 00000000000..c2dcf4715c3 --- /dev/null +++ b/lib/avb/libavb/avb_rsa.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifdef AVB_INSIDE_LIBAVB_H +#error "You can't include avb_rsa.h in the public header libavb.h." +#endif + +#ifndef AVB_COMPILATION +#error "Never include this file, it may only be used from internal avb code." +#endif + +#ifndef AVB_RSA_H_ +#define AVB_RSA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "avb_crypto.h" +#include "avb_sysdeps.h" + +/* Using the key given by |key|, verify a RSA signature |sig| of + * length |sig_num_bytes| against an expected |hash| of length + * |hash_num_bytes|. The padding to expect must be passed in using + * |padding| of length |padding_num_bytes|. + * + * The data in |key| must match the format defined in + * |AvbRSAPublicKeyHeader|, including the two large numbers + * following. The |key_num_bytes| must be the size of the entire + * serialized key. + * + * Returns false if verification fails, true otherwise. + */ +bool avb_rsa_verify(const uint8_t* key, + size_t key_num_bytes, + const uint8_t* sig, + size_t sig_num_bytes, + const uint8_t* hash, + size_t hash_num_bytes, + const uint8_t* padding, + size_t padding_num_bytes) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_RSA_H_ */ diff --git a/lib/avb/libavb/avb_sha.h b/lib/avb/libavb/avb_sha.h new file mode 100644 index 00000000000..c5a6a4c7064 --- /dev/null +++ b/lib/avb/libavb/avb_sha.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifdef AVB_INSIDE_LIBAVB_H +#error "You can't include avb_sha.h in the public header libavb.h." +#endif + +#ifndef AVB_COMPILATION +#error "Never include this file, it may only be used from internal avb code." +#endif + +#ifndef AVB_SHA_H_ +#define AVB_SHA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "avb_crypto.h" +#include "avb_sysdeps.h" + +/* Block size in bytes of a SHA-256 digest. */ +#define AVB_SHA256_BLOCK_SIZE 64 + + +/* Block size in bytes of a SHA-512 digest. */ +#define AVB_SHA512_BLOCK_SIZE 128 + +/* Data structure used for SHA-256. */ +typedef struct { + uint32_t h[8]; + uint32_t tot_len; + uint32_t len; + uint8_t block[2 * AVB_SHA256_BLOCK_SIZE]; + uint8_t buf[AVB_SHA256_DIGEST_SIZE]; /* Used for storing the final digest. */ +} AvbSHA256Ctx; + +/* Data structure used for SHA-512. */ +typedef struct { + uint64_t h[8]; + uint32_t tot_len; + uint32_t len; + uint8_t block[2 * AVB_SHA512_BLOCK_SIZE]; + uint8_t buf[AVB_SHA512_DIGEST_SIZE]; /* Used for storing the final digest. */ +} AvbSHA512Ctx; + +/* Initializes the SHA-256 context. */ +void avb_sha256_init(AvbSHA256Ctx* ctx); + +/* Updates the SHA-256 context with |len| bytes from |data|. */ +void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, uint32_t len); + +/* Returns the SHA-256 digest. */ +uint8_t* avb_sha256_final(AvbSHA256Ctx* ctx) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Initializes the SHA-512 context. */ +void avb_sha512_init(AvbSHA512Ctx* ctx); + +/* Updates the SHA-512 context with |len| bytes from |data|. */ +void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, uint32_t len); + +/* Returns the SHA-512 digest. */ +uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_SHA_H_ */ diff --git a/lib/avb/libavb/avb_sha256.c b/lib/avb/libavb/avb_sha256.c new file mode 100644 index 00000000000..cdd143a93fa --- /dev/null +++ b/lib/avb/libavb/avb_sha256.c @@ -0,0 +1,390 @@ +/* SHA-256 and SHA-512 implementation based on code by Oliver Gay + * under a BSD-style license. See below. + */ + +/* + * FIPS 180-2 SHA-224/256/384/512 implementation + * Last update: 02/02/2007 + * Issue date: 04/30/2005 + * + * Copyright (C) 2005, 2007 Olivier Gay + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the project nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "avb_sha.h" + +#define SHFR(x, n) (x >> n) +#define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n))) +#define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) +#define CH(x, y, z) ((x & y) ^ (~x & z)) +#define MAJ(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) + +#define SHA256_F1(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22)) +#define SHA256_F2(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25)) +#define SHA256_F3(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHFR(x, 3)) +#define SHA256_F4(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHFR(x, 10)) + +#define UNPACK32(x, str) \ + { \ + *((str) + 3) = (uint8_t)((x)); \ + *((str) + 2) = (uint8_t)((x) >> 8); \ + *((str) + 1) = (uint8_t)((x) >> 16); \ + *((str) + 0) = (uint8_t)((x) >> 24); \ + } + +#define PACK32(str, x) \ + { \ + *(x) = ((uint32_t) * ((str) + 3)) | ((uint32_t) * ((str) + 2) << 8) | \ + ((uint32_t) * ((str) + 1) << 16) | \ + ((uint32_t) * ((str) + 0) << 24); \ + } + +/* Macros used for loops unrolling */ + +#define SHA256_SCR(i) \ + { w[i] = SHA256_F4(w[i - 2]) + w[i - 7] + SHA256_F3(w[i - 15]) + w[i - 16]; } + +#define SHA256_EXP(a, b, c, d, e, f, g, h, j) \ + { \ + t1 = wv[h] + SHA256_F2(wv[e]) + CH(wv[e], wv[f], wv[g]) + sha256_k[j] + \ + w[j]; \ + t2 = SHA256_F1(wv[a]) + MAJ(wv[a], wv[b], wv[c]); \ + wv[d] += t1; \ + wv[h] = t1 + t2; \ + } + +static const uint32_t sha256_h0[8] = {0x6a09e667, + 0xbb67ae85, + 0x3c6ef372, + 0xa54ff53a, + 0x510e527f, + 0x9b05688c, + 0x1f83d9ab, + 0x5be0cd19}; + +static const uint32_t sha256_k[64] = { + 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1, + 0x923f82a4, 0xab1c5ed5, 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, + 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, 0xe49b69c1, 0xefbe4786, + 0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, + 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147, + 0x06ca6351, 0x14292967, 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, + 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, 0xa2bfe8a1, 0xa81a664b, + 0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, + 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a, + 0x5b9cca4f, 0x682e6ff3, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, + 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2}; + +/* SHA-256 implementation */ +void avb_sha256_init(AvbSHA256Ctx* ctx) { +#ifndef UNROLL_LOOPS + int i; + for (i = 0; i < 8; i++) { + ctx->h[i] = sha256_h0[i]; + } +#else + ctx->h[0] = sha256_h0[0]; + ctx->h[1] = sha256_h0[1]; + ctx->h[2] = sha256_h0[2]; + ctx->h[3] = sha256_h0[3]; + ctx->h[4] = sha256_h0[4]; + ctx->h[5] = sha256_h0[5]; + ctx->h[6] = sha256_h0[6]; + ctx->h[7] = sha256_h0[7]; +#endif /* !UNROLL_LOOPS */ + + ctx->len = 0; + ctx->tot_len = 0; +} + +static void SHA256_transform(AvbSHA256Ctx* ctx, + const uint8_t* message, + unsigned int block_nb) { + uint32_t w[64]; + uint32_t wv[8]; + uint32_t t1, t2; + const unsigned char* sub_block; + int i; + +#ifndef UNROLL_LOOPS + int j; +#endif + + for (i = 0; i < (int)block_nb; i++) { + sub_block = message + (i << 6); + +#ifndef UNROLL_LOOPS + for (j = 0; j < 16; j++) { + PACK32(&sub_block[j << 2], &w[j]); + } + + for (j = 16; j < 64; j++) { + SHA256_SCR(j); + } + + for (j = 0; j < 8; j++) { + wv[j] = ctx->h[j]; + } + + for (j = 0; j < 64; j++) { + t1 = wv[7] + SHA256_F2(wv[4]) + CH(wv[4], wv[5], wv[6]) + sha256_k[j] + + w[j]; + t2 = SHA256_F1(wv[0]) + MAJ(wv[0], wv[1], wv[2]); + wv[7] = wv[6]; + wv[6] = wv[5]; + wv[5] = wv[4]; + wv[4] = wv[3] + t1; + wv[3] = wv[2]; + wv[2] = wv[1]; + wv[1] = wv[0]; + wv[0] = t1 + t2; + } + + for (j = 0; j < 8; j++) { + ctx->h[j] += wv[j]; + } +#else + PACK32(&sub_block[0], &w[0]); + PACK32(&sub_block[4], &w[1]); + PACK32(&sub_block[8], &w[2]); + PACK32(&sub_block[12], &w[3]); + PACK32(&sub_block[16], &w[4]); + PACK32(&sub_block[20], &w[5]); + PACK32(&sub_block[24], &w[6]); + PACK32(&sub_block[28], &w[7]); + PACK32(&sub_block[32], &w[8]); + PACK32(&sub_block[36], &w[9]); + PACK32(&sub_block[40], &w[10]); + PACK32(&sub_block[44], &w[11]); + PACK32(&sub_block[48], &w[12]); + PACK32(&sub_block[52], &w[13]); + PACK32(&sub_block[56], &w[14]); + PACK32(&sub_block[60], &w[15]); + + SHA256_SCR(16); + SHA256_SCR(17); + SHA256_SCR(18); + SHA256_SCR(19); + SHA256_SCR(20); + SHA256_SCR(21); + SHA256_SCR(22); + SHA256_SCR(23); + SHA256_SCR(24); + SHA256_SCR(25); + SHA256_SCR(26); + SHA256_SCR(27); + SHA256_SCR(28); + SHA256_SCR(29); + SHA256_SCR(30); + SHA256_SCR(31); + SHA256_SCR(32); + SHA256_SCR(33); + SHA256_SCR(34); + SHA256_SCR(35); + SHA256_SCR(36); + SHA256_SCR(37); + SHA256_SCR(38); + SHA256_SCR(39); + SHA256_SCR(40); + SHA256_SCR(41); + SHA256_SCR(42); + SHA256_SCR(43); + SHA256_SCR(44); + SHA256_SCR(45); + SHA256_SCR(46); + SHA256_SCR(47); + SHA256_SCR(48); + SHA256_SCR(49); + SHA256_SCR(50); + SHA256_SCR(51); + SHA256_SCR(52); + SHA256_SCR(53); + SHA256_SCR(54); + SHA256_SCR(55); + SHA256_SCR(56); + SHA256_SCR(57); + SHA256_SCR(58); + SHA256_SCR(59); + SHA256_SCR(60); + SHA256_SCR(61); + SHA256_SCR(62); + SHA256_SCR(63); + + wv[0] = ctx->h[0]; + wv[1] = ctx->h[1]; + wv[2] = ctx->h[2]; + wv[3] = ctx->h[3]; + wv[4] = ctx->h[4]; + wv[5] = ctx->h[5]; + wv[6] = ctx->h[6]; + wv[7] = ctx->h[7]; + + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 0); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 1); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 2); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 3); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 4); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 5); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 6); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 7); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 8); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 9); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 10); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 11); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 12); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 13); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 14); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 15); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 16); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 17); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 18); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 19); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 20); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 21); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 22); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 23); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 24); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 25); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 26); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 27); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 28); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 29); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 30); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 31); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 32); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 33); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 34); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 35); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 36); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 37); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 38); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 39); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 40); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 41); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 42); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 43); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 44); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 45); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 46); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 47); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 48); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 49); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 50); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 51); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 52); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 53); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 54); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 55); + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 56); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, 57); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, 58); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, 59); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, 60); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, 61); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, 62); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, 63); + + ctx->h[0] += wv[0]; + ctx->h[1] += wv[1]; + ctx->h[2] += wv[2]; + ctx->h[3] += wv[3]; + ctx->h[4] += wv[4]; + ctx->h[5] += wv[5]; + ctx->h[6] += wv[6]; + ctx->h[7] += wv[7]; +#endif /* !UNROLL_LOOPS */ + } +} + +void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, uint32_t len) { + unsigned int block_nb; + unsigned int new_len, rem_len, tmp_len; + const uint8_t* shifted_data; + + tmp_len = AVB_SHA256_BLOCK_SIZE - ctx->len; + rem_len = len < tmp_len ? len : tmp_len; + + avb_memcpy(&ctx->block[ctx->len], data, rem_len); + + if (ctx->len + len < AVB_SHA256_BLOCK_SIZE) { + ctx->len += len; + return; + } + + new_len = len - rem_len; + block_nb = new_len / AVB_SHA256_BLOCK_SIZE; + + shifted_data = data + rem_len; + + SHA256_transform(ctx, ctx->block, 1); + SHA256_transform(ctx, shifted_data, block_nb); + + rem_len = new_len % AVB_SHA256_BLOCK_SIZE; + + avb_memcpy(ctx->block, &shifted_data[block_nb << 6], rem_len); + + ctx->len = rem_len; + ctx->tot_len += (block_nb + 1) << 6; +} + +uint8_t* avb_sha256_final(AvbSHA256Ctx* ctx) { + unsigned int block_nb; + unsigned int pm_len; + unsigned int len_b; +#ifndef UNROLL_LOOPS + int i; +#endif + + block_nb = + (1 + ((AVB_SHA256_BLOCK_SIZE - 9) < (ctx->len % AVB_SHA256_BLOCK_SIZE))); + + len_b = (ctx->tot_len + ctx->len) << 3; + pm_len = block_nb << 6; + + avb_memset(ctx->block + ctx->len, 0, pm_len - ctx->len); + ctx->block[ctx->len] = 0x80; + UNPACK32(len_b, ctx->block + pm_len - 4); + + SHA256_transform(ctx, ctx->block, block_nb); + +#ifndef UNROLL_LOOPS + for (i = 0; i < 8; i++) { + UNPACK32(ctx->h[i], &ctx->buf[i << 2]); + } +#else + UNPACK32(ctx->h[0], &ctx->buf[0]); + UNPACK32(ctx->h[1], &ctx->buf[4]); + UNPACK32(ctx->h[2], &ctx->buf[8]); + UNPACK32(ctx->h[3], &ctx->buf[12]); + UNPACK32(ctx->h[4], &ctx->buf[16]); + UNPACK32(ctx->h[5], &ctx->buf[20]); + UNPACK32(ctx->h[6], &ctx->buf[24]); + UNPACK32(ctx->h[7], &ctx->buf[28]); +#endif /* !UNROLL_LOOPS */ + + return ctx->buf; +} diff --git a/lib/avb/libavb/avb_sha512.c b/lib/avb/libavb/avb_sha512.c new file mode 100644 index 00000000000..8df63193c97 --- /dev/null +++ b/lib/avb/libavb/avb_sha512.c @@ -0,0 +1,388 @@ +/* SHA-256 and SHA-512 implementation based on code by Oliver Gay + * under a BSD-style license. See below. + */ + +/* + * FIPS 180-2 SHA-224/256/384/512 implementation + * Last update: 02/02/2007 + * Issue date: 04/30/2005 + * + * Copyright (C) 2005, 2007 Olivier Gay + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the project nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "avb_sha.h" + +#define SHFR(x, n) (x >> n) +#define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n))) +#define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) +#define CH(x, y, z) ((x & y) ^ (~x & z)) +#define MAJ(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) + +#define SHA512_F1(x) (ROTR(x, 28) ^ ROTR(x, 34) ^ ROTR(x, 39)) +#define SHA512_F2(x) (ROTR(x, 14) ^ ROTR(x, 18) ^ ROTR(x, 41)) +#define SHA512_F3(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHFR(x, 7)) +#define SHA512_F4(x) (ROTR(x, 19) ^ ROTR(x, 61) ^ SHFR(x, 6)) + +#define UNPACK32(x, str) \ + { \ + *((str) + 3) = (uint8_t)((x)); \ + *((str) + 2) = (uint8_t)((x) >> 8); \ + *((str) + 1) = (uint8_t)((x) >> 16); \ + *((str) + 0) = (uint8_t)((x) >> 24); \ + } + +#define UNPACK64(x, str) \ + { \ + *((str) + 7) = (uint8_t)x; \ + *((str) + 6) = (uint8_t)((uint64_t)x >> 8); \ + *((str) + 5) = (uint8_t)((uint64_t)x >> 16); \ + *((str) + 4) = (uint8_t)((uint64_t)x >> 24); \ + *((str) + 3) = (uint8_t)((uint64_t)x >> 32); \ + *((str) + 2) = (uint8_t)((uint64_t)x >> 40); \ + *((str) + 1) = (uint8_t)((uint64_t)x >> 48); \ + *((str) + 0) = (uint8_t)((uint64_t)x >> 56); \ + } + +#define PACK64(str, x) \ + { \ + *(x) = \ + ((uint64_t) * ((str) + 7)) | ((uint64_t) * ((str) + 6) << 8) | \ + ((uint64_t) * ((str) + 5) << 16) | ((uint64_t) * ((str) + 4) << 24) | \ + ((uint64_t) * ((str) + 3) << 32) | ((uint64_t) * ((str) + 2) << 40) | \ + ((uint64_t) * ((str) + 1) << 48) | ((uint64_t) * ((str) + 0) << 56); \ + } + +/* Macros used for loops unrolling */ + +#define SHA512_SCR(i) \ + { w[i] = SHA512_F4(w[i - 2]) + w[i - 7] + SHA512_F3(w[i - 15]) + w[i - 16]; } + +#define SHA512_EXP(a, b, c, d, e, f, g, h, j) \ + { \ + t1 = wv[h] + SHA512_F2(wv[e]) + CH(wv[e], wv[f], wv[g]) + sha512_k[j] + \ + w[j]; \ + t2 = SHA512_F1(wv[a]) + MAJ(wv[a], wv[b], wv[c]); \ + wv[d] += t1; \ + wv[h] = t1 + t2; \ + } + +static const uint64_t sha512_h0[8] = {0x6a09e667f3bcc908ULL, + 0xbb67ae8584caa73bULL, + 0x3c6ef372fe94f82bULL, + 0xa54ff53a5f1d36f1ULL, + 0x510e527fade682d1ULL, + 0x9b05688c2b3e6c1fULL, + 0x1f83d9abfb41bd6bULL, + 0x5be0cd19137e2179ULL}; + +static const uint64_t sha512_k[80] = { + 0x428a2f98d728ae22ULL, 0x7137449123ef65cdULL, 0xb5c0fbcfec4d3b2fULL, + 0xe9b5dba58189dbbcULL, 0x3956c25bf348b538ULL, 0x59f111f1b605d019ULL, + 0x923f82a4af194f9bULL, 0xab1c5ed5da6d8118ULL, 0xd807aa98a3030242ULL, + 0x12835b0145706fbeULL, 0x243185be4ee4b28cULL, 0x550c7dc3d5ffb4e2ULL, + 0x72be5d74f27b896fULL, 0x80deb1fe3b1696b1ULL, 0x9bdc06a725c71235ULL, + 0xc19bf174cf692694ULL, 0xe49b69c19ef14ad2ULL, 0xefbe4786384f25e3ULL, + 0x0fc19dc68b8cd5b5ULL, 0x240ca1cc77ac9c65ULL, 0x2de92c6f592b0275ULL, + 0x4a7484aa6ea6e483ULL, 0x5cb0a9dcbd41fbd4ULL, 0x76f988da831153b5ULL, + 0x983e5152ee66dfabULL, 0xa831c66d2db43210ULL, 0xb00327c898fb213fULL, + 0xbf597fc7beef0ee4ULL, 0xc6e00bf33da88fc2ULL, 0xd5a79147930aa725ULL, + 0x06ca6351e003826fULL, 0x142929670a0e6e70ULL, 0x27b70a8546d22ffcULL, + 0x2e1b21385c26c926ULL, 0x4d2c6dfc5ac42aedULL, 0x53380d139d95b3dfULL, + 0x650a73548baf63deULL, 0x766a0abb3c77b2a8ULL, 0x81c2c92e47edaee6ULL, + 0x92722c851482353bULL, 0xa2bfe8a14cf10364ULL, 0xa81a664bbc423001ULL, + 0xc24b8b70d0f89791ULL, 0xc76c51a30654be30ULL, 0xd192e819d6ef5218ULL, + 0xd69906245565a910ULL, 0xf40e35855771202aULL, 0x106aa07032bbd1b8ULL, + 0x19a4c116b8d2d0c8ULL, 0x1e376c085141ab53ULL, 0x2748774cdf8eeb99ULL, + 0x34b0bcb5e19b48a8ULL, 0x391c0cb3c5c95a63ULL, 0x4ed8aa4ae3418acbULL, + 0x5b9cca4f7763e373ULL, 0x682e6ff3d6b2b8a3ULL, 0x748f82ee5defb2fcULL, + 0x78a5636f43172f60ULL, 0x84c87814a1f0ab72ULL, 0x8cc702081a6439ecULL, + 0x90befffa23631e28ULL, 0xa4506cebde82bde9ULL, 0xbef9a3f7b2c67915ULL, + 0xc67178f2e372532bULL, 0xca273eceea26619cULL, 0xd186b8c721c0c207ULL, + 0xeada7dd6cde0eb1eULL, 0xf57d4f7fee6ed178ULL, 0x06f067aa72176fbaULL, + 0x0a637dc5a2c898a6ULL, 0x113f9804bef90daeULL, 0x1b710b35131c471bULL, + 0x28db77f523047d84ULL, 0x32caab7b40c72493ULL, 0x3c9ebe0a15c9bebcULL, + 0x431d67c49c100d4cULL, 0x4cc5d4becb3e42b6ULL, 0x597f299cfc657e2aULL, + 0x5fcb6fab3ad6faecULL, 0x6c44198c4a475817ULL}; + +/* SHA-512 implementation */ + +void avb_sha512_init(AvbSHA512Ctx* ctx) { +#ifdef UNROLL_LOOPS_SHA512 + ctx->h[0] = sha512_h0[0]; + ctx->h[1] = sha512_h0[1]; + ctx->h[2] = sha512_h0[2]; + ctx->h[3] = sha512_h0[3]; + ctx->h[4] = sha512_h0[4]; + ctx->h[5] = sha512_h0[5]; + ctx->h[6] = sha512_h0[6]; + ctx->h[7] = sha512_h0[7]; +#else + int i; + + for (i = 0; i < 8; i++) + ctx->h[i] = sha512_h0[i]; +#endif /* UNROLL_LOOPS_SHA512 */ + + ctx->len = 0; + ctx->tot_len = 0; +} + +static void SHA512_transform(AvbSHA512Ctx* ctx, + const uint8_t* message, + unsigned int block_nb) { + uint64_t w[80]; + uint64_t wv[8]; + uint64_t t1, t2; + const uint8_t* sub_block; + int i, j; + + for (i = 0; i < (int)block_nb; i++) { + sub_block = message + (i << 7); + +#ifdef UNROLL_LOOPS_SHA512 + PACK64(&sub_block[0], &w[0]); + PACK64(&sub_block[8], &w[1]); + PACK64(&sub_block[16], &w[2]); + PACK64(&sub_block[24], &w[3]); + PACK64(&sub_block[32], &w[4]); + PACK64(&sub_block[40], &w[5]); + PACK64(&sub_block[48], &w[6]); + PACK64(&sub_block[56], &w[7]); + PACK64(&sub_block[64], &w[8]); + PACK64(&sub_block[72], &w[9]); + PACK64(&sub_block[80], &w[10]); + PACK64(&sub_block[88], &w[11]); + PACK64(&sub_block[96], &w[12]); + PACK64(&sub_block[104], &w[13]); + PACK64(&sub_block[112], &w[14]); + PACK64(&sub_block[120], &w[15]); + + SHA512_SCR(16); + SHA512_SCR(17); + SHA512_SCR(18); + SHA512_SCR(19); + SHA512_SCR(20); + SHA512_SCR(21); + SHA512_SCR(22); + SHA512_SCR(23); + SHA512_SCR(24); + SHA512_SCR(25); + SHA512_SCR(26); + SHA512_SCR(27); + SHA512_SCR(28); + SHA512_SCR(29); + SHA512_SCR(30); + SHA512_SCR(31); + SHA512_SCR(32); + SHA512_SCR(33); + SHA512_SCR(34); + SHA512_SCR(35); + SHA512_SCR(36); + SHA512_SCR(37); + SHA512_SCR(38); + SHA512_SCR(39); + SHA512_SCR(40); + SHA512_SCR(41); + SHA512_SCR(42); + SHA512_SCR(43); + SHA512_SCR(44); + SHA512_SCR(45); + SHA512_SCR(46); + SHA512_SCR(47); + SHA512_SCR(48); + SHA512_SCR(49); + SHA512_SCR(50); + SHA512_SCR(51); + SHA512_SCR(52); + SHA512_SCR(53); + SHA512_SCR(54); + SHA512_SCR(55); + SHA512_SCR(56); + SHA512_SCR(57); + SHA512_SCR(58); + SHA512_SCR(59); + SHA512_SCR(60); + SHA512_SCR(61); + SHA512_SCR(62); + SHA512_SCR(63); + SHA512_SCR(64); + SHA512_SCR(65); + SHA512_SCR(66); + SHA512_SCR(67); + SHA512_SCR(68); + SHA512_SCR(69); + SHA512_SCR(70); + SHA512_SCR(71); + SHA512_SCR(72); + SHA512_SCR(73); + SHA512_SCR(74); + SHA512_SCR(75); + SHA512_SCR(76); + SHA512_SCR(77); + SHA512_SCR(78); + SHA512_SCR(79); + + wv[0] = ctx->h[0]; + wv[1] = ctx->h[1]; + wv[2] = ctx->h[2]; + wv[3] = ctx->h[3]; + wv[4] = ctx->h[4]; + wv[5] = ctx->h[5]; + wv[6] = ctx->h[6]; + wv[7] = ctx->h[7]; + + j = 0; + + do { + SHA512_EXP(0, 1, 2, 3, 4, 5, 6, 7, j); + j++; + SHA512_EXP(7, 0, 1, 2, 3, 4, 5, 6, j); + j++; + SHA512_EXP(6, 7, 0, 1, 2, 3, 4, 5, j); + j++; + SHA512_EXP(5, 6, 7, 0, 1, 2, 3, 4, j); + j++; + SHA512_EXP(4, 5, 6, 7, 0, 1, 2, 3, j); + j++; + SHA512_EXP(3, 4, 5, 6, 7, 0, 1, 2, j); + j++; + SHA512_EXP(2, 3, 4, 5, 6, 7, 0, 1, j); + j++; + SHA512_EXP(1, 2, 3, 4, 5, 6, 7, 0, j); + j++; + } while (j < 80); + + ctx->h[0] += wv[0]; + ctx->h[1] += wv[1]; + ctx->h[2] += wv[2]; + ctx->h[3] += wv[3]; + ctx->h[4] += wv[4]; + ctx->h[5] += wv[5]; + ctx->h[6] += wv[6]; + ctx->h[7] += wv[7]; +#else + for (j = 0; j < 16; j++) { + PACK64(&sub_block[j << 3], &w[j]); + } + + for (j = 16; j < 80; j++) { + SHA512_SCR(j); + } + + for (j = 0; j < 8; j++) { + wv[j] = ctx->h[j]; + } + + for (j = 0; j < 80; j++) { + t1 = wv[7] + SHA512_F2(wv[4]) + CH(wv[4], wv[5], wv[6]) + sha512_k[j] + + w[j]; + t2 = SHA512_F1(wv[0]) + MAJ(wv[0], wv[1], wv[2]); + wv[7] = wv[6]; + wv[6] = wv[5]; + wv[5] = wv[4]; + wv[4] = wv[3] + t1; + wv[3] = wv[2]; + wv[2] = wv[1]; + wv[1] = wv[0]; + wv[0] = t1 + t2; + } + + for (j = 0; j < 8; j++) + ctx->h[j] += wv[j]; +#endif /* UNROLL_LOOPS_SHA512 */ + } +} + +void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, uint32_t len) { + unsigned int block_nb; + unsigned int new_len, rem_len, tmp_len; + const uint8_t* shifted_data; + + tmp_len = AVB_SHA512_BLOCK_SIZE - ctx->len; + rem_len = len < tmp_len ? len : tmp_len; + + avb_memcpy(&ctx->block[ctx->len], data, rem_len); + + if (ctx->len + len < AVB_SHA512_BLOCK_SIZE) { + ctx->len += len; + return; + } + + new_len = len - rem_len; + block_nb = new_len / AVB_SHA512_BLOCK_SIZE; + + shifted_data = data + rem_len; + + SHA512_transform(ctx, ctx->block, 1); + SHA512_transform(ctx, shifted_data, block_nb); + + rem_len = new_len % AVB_SHA512_BLOCK_SIZE; + + avb_memcpy(ctx->block, &shifted_data[block_nb << 7], rem_len); + + ctx->len = rem_len; + ctx->tot_len += (block_nb + 1) << 7; +} + +uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) { + unsigned int block_nb; + unsigned int pm_len; + unsigned int len_b; + +#ifndef UNROLL_LOOPS_SHA512 + int i; +#endif + + block_nb = + 1 + ((AVB_SHA512_BLOCK_SIZE - 17) < (ctx->len % AVB_SHA512_BLOCK_SIZE)); + + len_b = (ctx->tot_len + ctx->len) << 3; + pm_len = block_nb << 7; + + avb_memset(ctx->block + ctx->len, 0, pm_len - ctx->len); + ctx->block[ctx->len] = 0x80; + UNPACK32(len_b, ctx->block + pm_len - 4); + + SHA512_transform(ctx, ctx->block, block_nb); + +#ifdef UNROLL_LOOPS_SHA512 + UNPACK64(ctx->h[0], &ctx->buf[0]); + UNPACK64(ctx->h[1], &ctx->buf[8]); + UNPACK64(ctx->h[2], &ctx->buf[16]); + UNPACK64(ctx->h[3], &ctx->buf[24]); + UNPACK64(ctx->h[4], &ctx->buf[32]); + UNPACK64(ctx->h[5], &ctx->buf[40]); + UNPACK64(ctx->h[6], &ctx->buf[48]); + UNPACK64(ctx->h[7], &ctx->buf[56]); +#else + for (i = 0; i < 8; i++) + UNPACK64(ctx->h[i], &ctx->buf[i << 3]); +#endif /* UNROLL_LOOPS_SHA512 */ + + return ctx->buf; +} diff --git a/lib/avb/libavb/avb_slot_verify.c b/lib/avb/libavb/avb_slot_verify.c new file mode 100644 index 00000000000..2ca4ff9bd33 --- /dev/null +++ b/lib/avb/libavb/avb_slot_verify.c @@ -0,0 +1,1440 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_slot_verify.h" +#include "avb_chain_partition_descriptor.h" +#include "avb_cmdline.h" +#include "avb_footer.h" +#include "avb_hash_descriptor.h" +#include "avb_hashtree_descriptor.h" +#include "avb_kernel_cmdline_descriptor.h" +#include "avb_sha.h" +#include "avb_util.h" +#include "avb_vbmeta_image.h" +#include "avb_version.h" +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) +#include "trusty/hwcrypto.h" +#include +#endif + +/* Maximum number of partitions that can be loaded with avb_slot_verify(). */ +#define MAX_NUMBER_OF_LOADED_PARTITIONS 32 + +/* Maximum number of vbmeta images that can be loaded with avb_slot_verify(). */ +#define MAX_NUMBER_OF_VBMETA_IMAGES 32 + +/* Maximum size of a vbmeta image - 64 KiB. */ +#define VBMETA_MAX_SIZE (64 * 1024) + +/* Helper function to see if we should continue with verification in + * allow_verification_error=true mode if something goes wrong. See the + * comments for the avb_slot_verify() function for more information. + */ +static inline bool result_should_continue(AvbSlotVerifyResult result) { + switch (result) { + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + return false; + + case AVB_SLOT_VERIFY_RESULT_OK: + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + return true; + } + + return false; +} + +static AvbSlotVerifyResult load_full_partition(AvbOps* ops, + const char* part_name, + uint64_t image_size, + uint8_t** out_image_buf, + bool* out_image_preloaded) { + size_t part_num_read; + AvbIOResult io_ret; + + /* Make sure that we do not overwrite existing data. */ + avb_assert(*out_image_buf == NULL); + avb_assert(!*out_image_preloaded); + + /* We are going to implicitly cast image_size from uint64_t to size_t in the + * following code, so we need to make sure that the cast is safe. */ + if (image_size != (size_t)(image_size)) { + avb_errorv(part_name, ": Partition size too large to load.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } + + /* Try use a preloaded one. */ + if (ops->get_preloaded_partition != NULL) { + io_ret = ops->get_preloaded_partition( + ops, part_name, image_size, out_image_buf, &part_num_read); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(part_name, ": Error loading data from partition.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_IO; + } + + if (*out_image_buf != NULL) { + if (part_num_read != image_size) { + avb_errorv(part_name, ": Read incorrect number of bytes.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_IO; + } + *out_image_preloaded = true; + } + } + + /* Allocate and copy the partition. */ + if (!*out_image_preloaded) { + *out_image_buf = avb_malloc(image_size); + if (*out_image_buf == NULL) { + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + } + + io_ret = ops->read_from_partition(ops, + part_name, + 0 /* offset */, + image_size, + *out_image_buf, + &part_num_read); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(part_name, ": Error loading data from partition.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_IO; + } + if (part_num_read != image_size) { + avb_errorv(part_name, ": Read incorrect number of bytes.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_IO; + } + } + + return AVB_SLOT_VERIFY_RESULT_OK; +} + +static AvbSlotVerifyResult read_persistent_digest(AvbOps* ops, + const char* part_name, + size_t expected_digest_size, + uint8_t* out_digest) { + char* persistent_value_name = NULL; + AvbIOResult io_ret = AVB_IO_RESULT_OK; + size_t stored_digest_size = 0; + + if (ops->read_persistent_value == NULL) { + avb_errorv(part_name, ": Persistent values are not implemented.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } + persistent_value_name = + avb_strdupv(AVB_NPV_PERSISTENT_DIGEST_PREFIX, part_name, NULL); + if (persistent_value_name == NULL) { + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + } + io_ret = ops->read_persistent_value(ops, + persistent_value_name, + expected_digest_size, + out_digest, + &stored_digest_size); + avb_free(persistent_value_name); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + } else if (io_ret == AVB_IO_RESULT_ERROR_NO_SUCH_VALUE) { + avb_errorv(part_name, ": Persistent digest does not exist.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } else if (io_ret == AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE || + io_ret == AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE || + expected_digest_size != stored_digest_size) { + avb_errorv( + part_name, ": Persistent digest is not of expected size.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(part_name, ": Error reading persistent digest.\n", NULL); + return AVB_SLOT_VERIFY_RESULT_ERROR_IO; + } + return AVB_SLOT_VERIFY_RESULT_OK; +} + +static AvbSlotVerifyResult load_and_verify_hash_partition( + AvbOps* ops, + const char* const* requested_partitions, + const char* ab_suffix, + bool allow_verification_error, + const AvbDescriptor* descriptor, + AvbSlotVerifyData* slot_data) { + AvbHashDescriptor hash_desc; + const uint8_t* desc_partition_name = NULL; + const uint8_t* desc_salt; + const uint8_t* desc_digest; + char part_name[AVB_PART_NAME_MAX_SIZE]; + AvbSlotVerifyResult ret; + AvbIOResult io_ret; + uint8_t* image_buf = NULL; + bool image_preloaded = false; + uint8_t* digest; + size_t digest_len; + const char* found; + uint64_t image_size; + size_t expected_digest_len = 0; + uint8_t expected_digest_buf[AVB_SHA512_DIGEST_SIZE]; + const uint8_t* expected_digest = NULL; +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) + uint8_t* hash_out = NULL; + uint8_t* hash_buf = NULL; +#endif + + + if (!avb_hash_descriptor_validate_and_byteswap( + (const AvbHashDescriptor*)descriptor, &hash_desc)) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + desc_partition_name = + ((const uint8_t*)descriptor) + sizeof(AvbHashDescriptor); + desc_salt = desc_partition_name + hash_desc.partition_name_len; + desc_digest = desc_salt + hash_desc.salt_len; + + if (!avb_validate_utf8(desc_partition_name, hash_desc.partition_name_len)) { + avb_error("Partition name is not valid UTF-8.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* Don't bother loading or validating unless the partition was + * requested in the first place. + */ + found = avb_strv_find_str(requested_partitions, + (const char*)desc_partition_name, + hash_desc.partition_name_len); + if (found == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_OK; + goto out; + } + + if ((hash_desc.flags & AVB_HASH_DESCRIPTOR_FLAGS_DO_NOT_USE_AB) != 0) { + /* No ab_suffix, just copy the partition name as is. */ + if (hash_desc.partition_name_len >= AVB_PART_NAME_MAX_SIZE) { + avb_error("Partition name does not fit.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + avb_memcpy(part_name, desc_partition_name, hash_desc.partition_name_len); + part_name[hash_desc.partition_name_len] = '\0'; + } else if (hash_desc.digest_len == 0 && avb_strlen(ab_suffix) != 0) { + /* No ab_suffix allowed for partitions without a digest in the descriptor + * because these partitions hold data unique to this device and are not + * updated using an A/B scheme. + */ + avb_error("Cannot use A/B with a persistent digest.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } else { + /* Add ab_suffix to the partition name. */ + if (!avb_str_concat(part_name, + sizeof part_name, + (const char*)desc_partition_name, + hash_desc.partition_name_len, + ab_suffix, + avb_strlen(ab_suffix))) { + avb_error("Partition name and suffix does not fit.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + } + + /* If we're allowing verification errors then hash_desc.image_size + * may no longer match what's in the partition... so in this case + * just load the entire partition. + * + * For example, this can happen if a developer does 'fastboot flash + * boot /path/to/new/and/bigger/boot.img'. We want this to work + * since it's such a common workflow. + */ + image_size = hash_desc.image_size; + if (allow_verification_error) { + if (ops->get_size_of_partition == NULL) { + avb_errorv(part_name, + ": The get_size_of_partition() operation is " + "not implemented so we may not load the entire partition. " + "Please implement.", + NULL); + } else { + io_ret = ops->get_size_of_partition(ops, part_name, &image_size); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(part_name, ": Error determining partition size.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + avb_debugv(part_name, ": Loading entire partition.\n", NULL); + } + } + + ret = load_full_partition( + ops, part_name, image_size, &image_buf, &image_preloaded); + if (ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto out; + } + + if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha256") == 0) { +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) + /* DMA requires cache aligned input/output buffer */ + hash_out = memalign(ARCH_DMA_MINALIGN, AVB_SHA256_DIGEST_SIZE); + if (hash_out == NULL) { + avb_error("failed to alloc memory!\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + uint32_t round_buf_size = ROUND(hash_desc.salt_len + hash_desc.image_size, + ARCH_DMA_MINALIGN); + hash_buf = memalign(ARCH_DMA_MINALIGN, round_buf_size); + if (hash_buf == NULL) { + avb_error("failed to alloc memory!\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + + avb_memcpy(hash_buf, desc_salt, hash_desc.salt_len); + avb_memcpy(hash_buf + hash_desc.salt_len, + image_buf, hash_desc.image_size); + /* calculate sha256 hash by caam */ + if (hwcrypto_hash((uint32_t)(ulong)hash_buf, + (hash_desc.salt_len + hash_desc.image_size), + (uint32_t)(ulong)hash_out, + AVB_SHA256_DIGEST_SIZE, + SHA256) != 0) { + avb_error("Failed to calculate sha256 hash with caam.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION; + goto out; + } + + digest = hash_out; + free(hash_buf); + hash_buf = NULL; +#else + AvbSHA256Ctx sha256_ctx; + avb_sha256_init(&sha256_ctx); + avb_sha256_update(&sha256_ctx, desc_salt, hash_desc.salt_len); + avb_sha256_update(&sha256_ctx, image_buf, hash_desc.image_size); + digest = avb_sha256_final(&sha256_ctx); +#endif + digest_len = AVB_SHA256_DIGEST_SIZE; + } else if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha512") == 0) { + AvbSHA512Ctx sha512_ctx; + avb_sha512_init(&sha512_ctx); + avb_sha512_update(&sha512_ctx, desc_salt, hash_desc.salt_len); + avb_sha512_update(&sha512_ctx, image_buf, hash_desc.image_size); + digest = avb_sha512_final(&sha512_ctx); + digest_len = AVB_SHA512_DIGEST_SIZE; + } else { + avb_errorv(part_name, ": Unsupported hash algorithm.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + if (hash_desc.digest_len == 0) { + // Expect a match to a persistent digest. + avb_debugv(part_name, ": No digest, using persistent digest.\n", NULL); + expected_digest_len = digest_len; + expected_digest = expected_digest_buf; + avb_assert(expected_digest_len <= sizeof(expected_digest_buf)); + ret = + read_persistent_digest(ops, part_name, digest_len, expected_digest_buf); + if (ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto out; + } + } else { + // Expect a match to the digest in the descriptor. + expected_digest_len = hash_desc.digest_len; + expected_digest = desc_digest; + } + + if (digest_len != expected_digest_len) { + avb_errorv( + part_name, ": Digest in descriptor not of expected size.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + if (avb_safe_memcmp(digest, expected_digest, digest_len) != 0) { + avb_errorv(part_name, + ": Hash of data does not match digest in descriptor.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION; + goto out; + } + + ret = AVB_SLOT_VERIFY_RESULT_OK; + +out: + +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) + if (hash_out != NULL) { + free(hash_out); + hash_out = NULL; + } + if (hash_buf != NULL) { + free(hash_buf); + hash_buf = NULL; + } +#endif + /* If it worked and something was loaded, copy to slot_data. */ + if ((ret == AVB_SLOT_VERIFY_RESULT_OK || result_should_continue(ret)) && + image_buf != NULL) { + AvbPartitionData* loaded_partition; + if (slot_data->num_loaded_partitions == MAX_NUMBER_OF_LOADED_PARTITIONS) { + avb_errorv(part_name, ": Too many loaded partitions.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + loaded_partition = + &slot_data->loaded_partitions[slot_data->num_loaded_partitions++]; + loaded_partition->partition_name = avb_strdup(found); + loaded_partition->data_size = image_size; + loaded_partition->data = image_buf; + loaded_partition->preloaded = image_preloaded; + image_buf = NULL; + } + +fail: + if (image_buf != NULL && !image_preloaded) { + avb_free(image_buf); + } + return ret; +} + +static AvbSlotVerifyResult load_requested_partitions( + AvbOps* ops, + const char* const* requested_partitions, + const char* ab_suffix, + AvbSlotVerifyData* slot_data) { + AvbSlotVerifyResult ret; + uint8_t* image_buf = NULL; + bool image_preloaded = false; + size_t n; + + if (ops->get_size_of_partition == NULL) { + avb_error("get_size_of_partition() not implemented.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT; + goto out; + } + + for (n = 0; requested_partitions[n] != NULL; n++) { + char part_name[AVB_PART_NAME_MAX_SIZE]; + AvbIOResult io_ret; + uint64_t image_size; + AvbPartitionData* loaded_partition; + + if (!avb_str_concat(part_name, + sizeof part_name, + requested_partitions[n], + avb_strlen(requested_partitions[n]), + ab_suffix, + avb_strlen(ab_suffix))) { + avb_error("Partition name and suffix does not fit.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + io_ret = ops->get_size_of_partition(ops, part_name, &image_size); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(part_name, ": Error determining partition size.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + avb_debugv(part_name, ": Loading entire partition.\n", NULL); + + ret = load_full_partition( + ops, part_name, image_size, &image_buf, &image_preloaded); + if (ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto out; + } + + /* Move to slot_data. */ + if (slot_data->num_loaded_partitions == MAX_NUMBER_OF_LOADED_PARTITIONS) { + avb_errorv(part_name, ": Too many loaded partitions.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + loaded_partition = + &slot_data->loaded_partitions[slot_data->num_loaded_partitions++]; + loaded_partition->partition_name = avb_strdup(requested_partitions[n]); + if (loaded_partition->partition_name == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + loaded_partition->data_size = image_size; + loaded_partition->data = image_buf; /* Transferring the owner. */ + loaded_partition->preloaded = image_preloaded; + image_buf = NULL; + image_preloaded = false; + } + + ret = AVB_SLOT_VERIFY_RESULT_OK; + +out: + /* Free the current buffer if any. */ + if (image_buf != NULL && !image_preloaded) { + avb_free(image_buf); + } + /* Buffers that are already saved in slot_data will be handled by the caller + * even on failure. */ + return ret; +} + +static AvbSlotVerifyResult load_and_verify_vbmeta( + AvbOps* ops, + const char* const* requested_partitions, + const char* ab_suffix, + bool allow_verification_error, + AvbVBMetaImageFlags toplevel_vbmeta_flags, + int rollback_index_location, + const char* partition_name, + size_t partition_name_len, + const uint8_t* expected_public_key, + size_t expected_public_key_length, + AvbSlotVerifyData* slot_data, + AvbAlgorithmType* out_algorithm_type, + AvbCmdlineSubstList* out_additional_cmdline_subst) { + char full_partition_name[AVB_PART_NAME_MAX_SIZE]; + AvbSlotVerifyResult ret; + AvbIOResult io_ret; + size_t vbmeta_offset; + size_t vbmeta_size; + uint8_t* vbmeta_buf = NULL; + size_t vbmeta_num_read; + AvbVBMetaVerifyResult vbmeta_ret; + const uint8_t* pk_data; + size_t pk_len; + AvbVBMetaImageHeader vbmeta_header; + uint64_t stored_rollback_index; + const AvbDescriptor** descriptors = NULL; + size_t num_descriptors; + size_t n; + bool is_main_vbmeta; + bool is_vbmeta_partition; + AvbVBMetaData* vbmeta_image_data = NULL; + + ret = AVB_SLOT_VERIFY_RESULT_OK; + + avb_assert(slot_data != NULL); + + /* Since we allow top-level vbmeta in 'boot', use + * rollback_index_location to determine whether we're the main + * vbmeta struct. + */ + is_main_vbmeta = (rollback_index_location == 0); + is_vbmeta_partition = (avb_strcmp(partition_name, "vbmeta") == 0); + + if (!avb_validate_utf8((const uint8_t*)partition_name, partition_name_len)) { + avb_error("Partition name is not valid UTF-8.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* Construct full partition name. */ + if (!avb_str_concat(full_partition_name, + sizeof full_partition_name, + partition_name, + partition_name_len, + ab_suffix, + avb_strlen(ab_suffix))) { + avb_error("Partition name and suffix does not fit.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + avb_debugv("Loading vbmeta struct from partition '", + full_partition_name, + "'.\n", + NULL); + + /* If we're loading from the main vbmeta partition, the vbmeta + * struct is in the beginning. Otherwise we have to locate it via a + * footer. + */ + if (is_vbmeta_partition) { + vbmeta_offset = 0; + vbmeta_size = VBMETA_MAX_SIZE; + } else { + uint8_t footer_buf[AVB_FOOTER_SIZE]; + size_t footer_num_read; + AvbFooter footer; + + io_ret = ops->read_from_partition(ops, + full_partition_name, + -AVB_FOOTER_SIZE, + AVB_FOOTER_SIZE, + footer_buf, + &footer_num_read); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(full_partition_name, ": Error loading footer.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + avb_assert(footer_num_read == AVB_FOOTER_SIZE); + + if (!avb_footer_validate_and_byteswap((const AvbFooter*)footer_buf, + &footer)) { + avb_errorv(full_partition_name, ": Error validating footer.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* Basic footer sanity check since the data is untrusted. */ + if (footer.vbmeta_size > VBMETA_MAX_SIZE) { + avb_errorv( + full_partition_name, ": Invalid vbmeta size in footer.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + vbmeta_offset = footer.vbmeta_offset; + vbmeta_size = footer.vbmeta_size; + } + + vbmeta_buf = avb_malloc(vbmeta_size); + if (vbmeta_buf == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + + io_ret = ops->read_from_partition(ops, + full_partition_name, + vbmeta_offset, + vbmeta_size, + vbmeta_buf, + &vbmeta_num_read); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + /* If we're looking for 'vbmeta' but there is no such partition, + * go try to get it from the boot partition instead. + */ + if (is_main_vbmeta && io_ret == AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION && + is_vbmeta_partition) { + avb_debugv(full_partition_name, + ": No such partition. Trying 'boot' instead.\n", + NULL); + ret = load_and_verify_vbmeta(ops, + requested_partitions, + ab_suffix, + allow_verification_error, + 0 /* toplevel_vbmeta_flags */, + 0 /* rollback_index_location */, + "boot", + avb_strlen("boot"), + NULL /* expected_public_key */, + 0 /* expected_public_key_length */, + slot_data, + out_algorithm_type, + out_additional_cmdline_subst); + goto out; + } else { + avb_errorv(full_partition_name, ": Error loading vbmeta data.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + } + avb_assert(vbmeta_num_read <= vbmeta_size); + + /* Check if the image is properly signed and get the public key used + * to sign the image. + */ + vbmeta_ret = + avb_vbmeta_image_verify(vbmeta_buf, vbmeta_num_read, &pk_data, &pk_len); + switch (vbmeta_ret) { + case AVB_VBMETA_VERIFY_RESULT_OK: + avb_assert(pk_data != NULL && pk_len > 0); + break; + + case AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED: + case AVB_VBMETA_VERIFY_RESULT_HASH_MISMATCH: + case AVB_VBMETA_VERIFY_RESULT_SIGNATURE_MISMATCH: + ret = AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION; + avb_errorv(full_partition_name, + ": Error verifying vbmeta image: ", + avb_vbmeta_verify_result_to_string(vbmeta_ret), + "\n", + NULL); + if (!allow_verification_error) { + goto out; + } + break; + + case AVB_VBMETA_VERIFY_RESULT_INVALID_VBMETA_HEADER: + /* No way to continue this case. */ + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + avb_errorv(full_partition_name, + ": Error verifying vbmeta image: invalid vbmeta header\n", + NULL); + goto out; + + case AVB_VBMETA_VERIFY_RESULT_UNSUPPORTED_VERSION: + /* No way to continue this case. */ + ret = AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION; + avb_errorv(full_partition_name, + ": Error verifying vbmeta image: unsupported AVB version\n", + NULL); + goto out; + } + + /* Byteswap the header. */ + avb_vbmeta_image_header_to_host_byte_order((AvbVBMetaImageHeader*)vbmeta_buf, + &vbmeta_header); + + /* If we're the toplevel, assign flags so they'll be passed down. */ + if (is_main_vbmeta) { + toplevel_vbmeta_flags = (AvbVBMetaImageFlags)vbmeta_header.flags; + } else { + if (vbmeta_header.flags != 0) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + avb_errorv(full_partition_name, + ": chained vbmeta image has non-zero flags\n", + NULL); + goto out; + } + } + + /* Check if key used to make signature matches what is expected. */ + if (pk_data != NULL) { + if (expected_public_key != NULL) { + avb_assert(!is_main_vbmeta); + if (expected_public_key_length != pk_len || + avb_safe_memcmp(expected_public_key, pk_data, pk_len) != 0) { + avb_errorv(full_partition_name, + ": Public key used to sign data does not match key in chain " + "partition descriptor.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED; + if (!allow_verification_error) { + goto out; + } + } + } else { + bool key_is_trusted = false; + const uint8_t* pk_metadata = NULL; + size_t pk_metadata_len = 0; + + if (vbmeta_header.public_key_metadata_size > 0) { + pk_metadata = vbmeta_buf + sizeof(AvbVBMetaImageHeader) + + vbmeta_header.authentication_data_block_size + + vbmeta_header.public_key_metadata_offset; + pk_metadata_len = vbmeta_header.public_key_metadata_size; + } + + avb_assert(is_main_vbmeta); + io_ret = ops->validate_vbmeta_public_key( + ops, pk_data, pk_len, pk_metadata, pk_metadata_len, &key_is_trusted); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(full_partition_name, + ": Error while checking public key used to sign data.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + if (!key_is_trusted) { + avb_errorv(full_partition_name, + ": Public key used to sign data rejected.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED; + if (!allow_verification_error) { + goto out; + } + } + } + } + + /* Check rollback index. */ + io_ret = ops->read_rollback_index( + ops, rollback_index_location, &stored_rollback_index); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_errorv(full_partition_name, + ": Error getting rollback index for location.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO; + goto out; + } + if (vbmeta_header.rollback_index < stored_rollback_index) { + avb_errorv( + full_partition_name, + ": Image rollback index is less than the stored rollback index.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX; + if (!allow_verification_error) { + goto out; + } + } + + /* Copy vbmeta to vbmeta_images before recursing. */ + if (is_main_vbmeta) { + avb_assert(slot_data->num_vbmeta_images == 0); + } else { + avb_assert(slot_data->num_vbmeta_images > 0); + } + if (slot_data->num_vbmeta_images == MAX_NUMBER_OF_VBMETA_IMAGES) { + avb_errorv(full_partition_name, ": Too many vbmeta images.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + vbmeta_image_data = &slot_data->vbmeta_images[slot_data->num_vbmeta_images++]; + vbmeta_image_data->partition_name = avb_strdup(partition_name); + vbmeta_image_data->vbmeta_data = vbmeta_buf; + /* Note that |vbmeta_buf| is actually |vbmeta_num_read| bytes long + * and this includes data past the end of the image. Pass the + * actual size of the vbmeta image. Also, no need to use + * avb_safe_add() since the header has already been verified. + */ + vbmeta_image_data->vbmeta_size = + sizeof(AvbVBMetaImageHeader) + + vbmeta_header.authentication_data_block_size + + vbmeta_header.auxiliary_data_block_size; + vbmeta_image_data->verify_result = vbmeta_ret; + + /* If verification has been disabled by setting a bit in the image, + * we're done... except that we need to load the entirety of the + * requested partitions. + */ + if (vbmeta_header.flags & AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED) { + AvbSlotVerifyResult sub_ret; + avb_debugv( + full_partition_name, ": VERIFICATION_DISABLED bit is set.\n", NULL); + /* If load_requested_partitions() fail it is always a fatal + * failure (e.g. ERROR_INVALID_ARGUMENT, ERROR_OOM, etc.) rather + * than recoverable (e.g. one where result_should_continue() + * returns true) and we want to convey that error. + */ + sub_ret = load_requested_partitions( + ops, requested_partitions, ab_suffix, slot_data); + if (sub_ret != AVB_SLOT_VERIFY_RESULT_OK) { + ret = sub_ret; + } + goto out; + } + + /* Now go through all descriptors and take the appropriate action: + * + * - hash descriptor: Load data from partition, calculate hash, and + * checks that it matches what's in the hash descriptor. + * + * - hashtree descriptor: Do nothing since verification happens + * on-the-fly from within the OS. (Unless the descriptor uses a + * persistent digest, in which case we need to find it). + * + * - chained partition descriptor: Load the footer, load the vbmeta + * image, verify vbmeta image (includes rollback checks, hash + * checks, bail on chained partitions). + */ + descriptors = + avb_descriptor_get_all(vbmeta_buf, vbmeta_num_read, &num_descriptors); + for (n = 0; n < num_descriptors; n++) { + AvbDescriptor desc; + + if (!avb_descriptor_validate_and_byteswap(descriptors[n], &desc)) { + avb_errorv(full_partition_name, ": Descriptor is invalid.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + switch (desc.tag) { + case AVB_DESCRIPTOR_TAG_HASH: { + AvbSlotVerifyResult sub_ret; + sub_ret = load_and_verify_hash_partition(ops, + requested_partitions, + ab_suffix, + allow_verification_error, + descriptors[n], + slot_data); + if (sub_ret != AVB_SLOT_VERIFY_RESULT_OK) { + ret = sub_ret; + if (!allow_verification_error || !result_should_continue(ret)) { + goto out; + } + } + } break; + + case AVB_DESCRIPTOR_TAG_CHAIN_PARTITION: { + AvbSlotVerifyResult sub_ret; + AvbChainPartitionDescriptor chain_desc; + const uint8_t* chain_partition_name; + const uint8_t* chain_public_key; + + /* Only allow CHAIN_PARTITION descriptors in the main vbmeta image. */ + if (!is_main_vbmeta) { + avb_errorv(full_partition_name, + ": Encountered chain descriptor not in main image.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + if (!avb_chain_partition_descriptor_validate_and_byteswap( + (AvbChainPartitionDescriptor*)descriptors[n], &chain_desc)) { + avb_errorv(full_partition_name, + ": Chain partition descriptor is invalid.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + if (chain_desc.rollback_index_location == 0) { + avb_errorv(full_partition_name, + ": Chain partition has invalid " + "rollback_index_location field.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + chain_partition_name = ((const uint8_t*)descriptors[n]) + + sizeof(AvbChainPartitionDescriptor); + chain_public_key = chain_partition_name + chain_desc.partition_name_len; + + sub_ret = + load_and_verify_vbmeta(ops, + requested_partitions, + ab_suffix, + allow_verification_error, + toplevel_vbmeta_flags, + chain_desc.rollback_index_location, + (const char*)chain_partition_name, + chain_desc.partition_name_len, + chain_public_key, + chain_desc.public_key_len, + slot_data, + NULL, /* out_algorithm_type */ + NULL /* out_additional_cmdline_subst */); + if (sub_ret != AVB_SLOT_VERIFY_RESULT_OK) { + ret = sub_ret; + if (!result_should_continue(ret)) { + goto out; + } + } + } break; + + case AVB_DESCRIPTOR_TAG_KERNEL_CMDLINE: { + const uint8_t* kernel_cmdline; + AvbKernelCmdlineDescriptor kernel_cmdline_desc; + bool apply_cmdline; + + if (!avb_kernel_cmdline_descriptor_validate_and_byteswap( + (AvbKernelCmdlineDescriptor*)descriptors[n], + &kernel_cmdline_desc)) { + avb_errorv(full_partition_name, + ": Kernel cmdline descriptor is invalid.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + kernel_cmdline = ((const uint8_t*)descriptors[n]) + + sizeof(AvbKernelCmdlineDescriptor); + + if (!avb_validate_utf8(kernel_cmdline, + kernel_cmdline_desc.kernel_cmdline_length)) { + avb_errorv(full_partition_name, + ": Kernel cmdline is not valid UTF-8.\n", + NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* Compare the flags for top-level VBMeta struct with flags in + * the command-line descriptor so command-line snippets only + * intended for a certain mode (dm-verity enabled/disabled) + * are skipped if applicable. + */ + apply_cmdline = true; + if (toplevel_vbmeta_flags & AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED) { + if (kernel_cmdline_desc.flags & + AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_NOT_DISABLED) { + apply_cmdline = false; + } + } else { + if (kernel_cmdline_desc.flags & + AVB_KERNEL_CMDLINE_FLAGS_USE_ONLY_IF_HASHTREE_DISABLED) { + apply_cmdline = false; + } + } + + if (apply_cmdline) { + if (slot_data->cmdline == NULL) { + slot_data->cmdline = + avb_calloc(kernel_cmdline_desc.kernel_cmdline_length + 1); + if (slot_data->cmdline == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + avb_memcpy(slot_data->cmdline, + kernel_cmdline, + kernel_cmdline_desc.kernel_cmdline_length); + } else { + /* new cmdline is: + ' ' + + '\0' */ + size_t orig_size = avb_strlen(slot_data->cmdline); + size_t new_size = + orig_size + 1 + kernel_cmdline_desc.kernel_cmdline_length + 1; + char* new_cmdline = avb_calloc(new_size); + if (new_cmdline == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + avb_memcpy(new_cmdline, slot_data->cmdline, orig_size); + new_cmdline[orig_size] = ' '; + avb_memcpy(new_cmdline + orig_size + 1, + kernel_cmdline, + kernel_cmdline_desc.kernel_cmdline_length); + avb_free(slot_data->cmdline); + slot_data->cmdline = new_cmdline; + } + } + } break; + + case AVB_DESCRIPTOR_TAG_HASHTREE: { + AvbHashtreeDescriptor hashtree_desc; + + if (!avb_hashtree_descriptor_validate_and_byteswap( + (AvbHashtreeDescriptor*)descriptors[n], &hashtree_desc)) { + avb_errorv( + full_partition_name, ": Hashtree descriptor is invalid.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* We only need to continue when there is no digest in the descriptor. + * This is because the only processing here is to find the digest and + * make it available on the kernel command line. + */ + if (hashtree_desc.root_digest_len == 0) { + char part_name[AVB_PART_NAME_MAX_SIZE]; + size_t digest_len = 0; + uint8_t digest_buf[AVB_SHA512_DIGEST_SIZE]; + const uint8_t* desc_partition_name = + ((const uint8_t*)descriptors[n]) + sizeof(AvbHashtreeDescriptor); + + if (!avb_validate_utf8(desc_partition_name, + hashtree_desc.partition_name_len)) { + avb_error("Partition name is not valid UTF-8.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + /* No ab_suffix for partitions without a digest in the descriptor + * because these partitions hold data unique to this device and are + * not updated using an A/B scheme. + */ + if ((hashtree_desc.flags & + AVB_HASHTREE_DESCRIPTOR_FLAGS_DO_NOT_USE_AB) == 0 && + avb_strlen(ab_suffix) != 0) { + avb_error("Cannot use A/B with a persistent root digest.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + if (hashtree_desc.partition_name_len >= AVB_PART_NAME_MAX_SIZE) { + avb_error("Partition name does not fit.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + avb_memcpy( + part_name, desc_partition_name, hashtree_desc.partition_name_len); + part_name[hashtree_desc.partition_name_len] = '\0'; + + /* Determine the expected digest size from the hash algorithm. */ + if (avb_strcmp((const char*)hashtree_desc.hash_algorithm, "sha1") == + 0) { + digest_len = AVB_SHA1_DIGEST_SIZE; + } else if (avb_strcmp((const char*)hashtree_desc.hash_algorithm, + "sha256") == 0) { + digest_len = AVB_SHA256_DIGEST_SIZE; + } else if (avb_strcmp((const char*)hashtree_desc.hash_algorithm, + "sha512") == 0) { + digest_len = AVB_SHA512_DIGEST_SIZE; + } else { + avb_errorv(part_name, ": Unsupported hash algorithm.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + ret = read_persistent_digest(ops, part_name, digest_len, digest_buf); + if (ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto out; + } + + if (out_additional_cmdline_subst) { + ret = + avb_add_root_digest_substitution(part_name, + digest_buf, + digest_len, + out_additional_cmdline_subst); + if (ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto out; + } + } + } + } break; + + case AVB_DESCRIPTOR_TAG_PROPERTY: + /* Do nothing. */ + break; + } + } + + if (rollback_index_location >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) { + avb_errorv( + full_partition_name, ": Invalid rollback_index_location.\n", NULL); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA; + goto out; + } + + slot_data->rollback_indexes[rollback_index_location] = + vbmeta_header.rollback_index; + + if (out_algorithm_type != NULL) { + *out_algorithm_type = (AvbAlgorithmType)vbmeta_header.algorithm_type; + } + +out: + /* If |vbmeta_image_data| isn't NULL it means that it adopted + * |vbmeta_buf| so in that case don't free it here. + */ + if (vbmeta_image_data == NULL) { + if (vbmeta_buf != NULL) { + avb_free(vbmeta_buf); + } + } + if (descriptors != NULL) { + avb_free(descriptors); + } + return ret; +} + +AvbSlotVerifyResult avb_slot_verify(AvbOps* ops, + const char* const* requested_partitions, + const char* ab_suffix, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data) { + AvbSlotVerifyResult ret; + AvbSlotVerifyData* slot_data = NULL; + AvbAlgorithmType algorithm_type = AVB_ALGORITHM_TYPE_NONE; + bool using_boot_for_vbmeta = false; + AvbVBMetaImageHeader toplevel_vbmeta; + bool allow_verification_error = + (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR); + AvbCmdlineSubstList* additional_cmdline_subst = NULL; + + /* Fail early if we're missing the AvbOps needed for slot verification. + * + * For now, handle get_size_of_partition() not being implemented. In + * a later release we may change that. + */ + avb_assert(ops->read_is_device_unlocked != NULL); + avb_assert(ops->read_from_partition != NULL); + avb_assert(ops->validate_vbmeta_public_key != NULL); + avb_assert(ops->read_rollback_index != NULL); + avb_assert(ops->get_unique_guid_for_partition != NULL); + + if (out_data != NULL) { + *out_data = NULL; + } + + /* Allowing dm-verity errors defeats the purpose of verified boot so + * only allow this if set up to allow verification errors + * (e.g. typically only UNLOCKED mode). + */ + if (hashtree_error_mode == AVB_HASHTREE_ERROR_MODE_LOGGING && + !allow_verification_error) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT; + goto fail; + } + + slot_data = avb_calloc(sizeof(AvbSlotVerifyData)); + if (slot_data == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + slot_data->vbmeta_images = + avb_calloc(sizeof(AvbVBMetaData) * MAX_NUMBER_OF_VBMETA_IMAGES); + if (slot_data->vbmeta_images == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + slot_data->loaded_partitions = + avb_calloc(sizeof(AvbPartitionData) * MAX_NUMBER_OF_LOADED_PARTITIONS); + if (slot_data->loaded_partitions == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + + additional_cmdline_subst = avb_new_cmdline_subst_list(); + if (additional_cmdline_subst == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + + ret = load_and_verify_vbmeta(ops, + requested_partitions, + ab_suffix, + allow_verification_error, + 0 /* toplevel_vbmeta_flags */, + 0 /* rollback_index_location */, + "vbmeta", + avb_strlen("vbmeta"), + NULL /* expected_public_key */, + 0 /* expected_public_key_length */, + slot_data, + &algorithm_type, + additional_cmdline_subst); + if (!allow_verification_error && ret != AVB_SLOT_VERIFY_RESULT_OK) { + goto fail; + } + + /* If things check out, mangle the kernel command-line as needed. */ + if (result_should_continue(ret)) { + if (avb_strcmp(slot_data->vbmeta_images[0].partition_name, "vbmeta") != 0) { + avb_assert( + avb_strcmp(slot_data->vbmeta_images[0].partition_name, "boot") == 0); + using_boot_for_vbmeta = true; + } + + /* Byteswap top-level vbmeta header since we'll need it below. */ + avb_vbmeta_image_header_to_host_byte_order( + (const AvbVBMetaImageHeader*)slot_data->vbmeta_images[0].vbmeta_data, + &toplevel_vbmeta); + + /* Fill in |ab_suffix| field. */ + slot_data->ab_suffix = avb_strdup(ab_suffix); + if (slot_data->ab_suffix == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + + /* If verification is disabled, we are done ... we specifically + * don't want to add any androidboot.* options since verification + * is disabled. + */ + if (toplevel_vbmeta.flags & AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED) { + /* Since verification is disabled we didn't process any + * descriptors and thus there's no cmdline... so set root= such + * that the system partition is mounted. + */ + avb_assert(slot_data->cmdline == NULL); + slot_data->cmdline = + avb_strdup("root=PARTUUID=$(ANDROID_SYSTEM_PARTUUID)"); + if (slot_data->cmdline == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + } else { + /* Add options - any failure in avb_append_options() is either an + * I/O or OOM error. + */ + AvbSlotVerifyResult sub_ret = avb_append_options(ops, + slot_data, + &toplevel_vbmeta, + algorithm_type, + hashtree_error_mode); + if (sub_ret != AVB_SLOT_VERIFY_RESULT_OK) { + ret = sub_ret; + goto fail; + } + } + + /* Substitute $(ANDROID_SYSTEM_PARTUUID) and friends. */ + if (slot_data->cmdline != NULL) { + char* new_cmdline; + new_cmdline = avb_sub_cmdline(ops, + slot_data->cmdline, + ab_suffix, + using_boot_for_vbmeta, + additional_cmdline_subst); + if (new_cmdline != slot_data->cmdline) { + if (new_cmdline == NULL) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto fail; + } + avb_free(slot_data->cmdline); + slot_data->cmdline = new_cmdline; + } + } + + if (out_data != NULL) { + *out_data = slot_data; + } else { + avb_slot_verify_data_free(slot_data); + } + } + + avb_free_cmdline_subst_list(additional_cmdline_subst); + additional_cmdline_subst = NULL; + + if (!allow_verification_error) { + avb_assert(ret == AVB_SLOT_VERIFY_RESULT_OK); + } + + return ret; + +fail: + if (slot_data != NULL) { + avb_slot_verify_data_free(slot_data); + } + if (additional_cmdline_subst != NULL) { + avb_free_cmdline_subst_list(additional_cmdline_subst); + } + return ret; +} + +void avb_slot_verify_data_free(AvbSlotVerifyData* data) { + if (data->ab_suffix != NULL) { + avb_free(data->ab_suffix); + } + if (data->cmdline != NULL) { + avb_free(data->cmdline); + } + if (data->vbmeta_images != NULL) { + size_t n; + for (n = 0; n < data->num_vbmeta_images; n++) { + AvbVBMetaData* vbmeta_image = &data->vbmeta_images[n]; + if (vbmeta_image->partition_name != NULL) { + avb_free(vbmeta_image->partition_name); + } + if (vbmeta_image->vbmeta_data != NULL) { + avb_free(vbmeta_image->vbmeta_data); + } + } + avb_free(data->vbmeta_images); + } + if (data->loaded_partitions != NULL) { + size_t n; + for (n = 0; n < data->num_loaded_partitions; n++) { + AvbPartitionData* loaded_partition = &data->loaded_partitions[n]; + if (loaded_partition->partition_name != NULL) { + avb_free(loaded_partition->partition_name); + } + if (loaded_partition->data != NULL && !loaded_partition->preloaded) { + avb_free(loaded_partition->data); + } + } + avb_free(data->loaded_partitions); + } + avb_free(data); +} + +const char* avb_slot_verify_result_to_string(AvbSlotVerifyResult result) { + const char* ret = NULL; + + switch (result) { + case AVB_SLOT_VERIFY_RESULT_OK: + ret = "OK"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + ret = "ERROR_OOM"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + ret = "ERROR_IO"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + ret = "ERROR_VERIFICATION"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + ret = "ERROR_ROLLBACK_INDEX"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + ret = "ERROR_PUBLIC_KEY_REJECTED"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + ret = "ERROR_INVALID_METADATA"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + ret = "ERROR_UNSUPPORTED_VERSION"; + break; + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + ret = "ERROR_INVALID_ARGUMENT"; + break; + /* Do not add a 'default:' case here because of -Wswitch. */ + } + + if (ret == NULL) { + avb_error("Unknown AvbSlotVerifyResult value.\n"); + ret = "(unknown)"; + } + + return ret; +} + +void avb_slot_verify_data_calculate_vbmeta_digest(AvbSlotVerifyData* data, + AvbDigestType digest_type, + uint8_t* out_digest) { + bool ret = false; + size_t n; + + switch (digest_type) { + case AVB_DIGEST_TYPE_SHA256: { + AvbSHA256Ctx ctx; + avb_sha256_init(&ctx); + for (n = 0; n < data->num_vbmeta_images; n++) { + avb_sha256_update(&ctx, + data->vbmeta_images[n].vbmeta_data, + data->vbmeta_images[n].vbmeta_size); + } + avb_memcpy(out_digest, avb_sha256_final(&ctx), AVB_SHA256_DIGEST_SIZE); + ret = true; + } break; + + case AVB_DIGEST_TYPE_SHA512: { + AvbSHA512Ctx ctx; + avb_sha512_init(&ctx); + for (n = 0; n < data->num_vbmeta_images; n++) { + avb_sha512_update(&ctx, + data->vbmeta_images[n].vbmeta_data, + data->vbmeta_images[n].vbmeta_size); + } + avb_memcpy(out_digest, avb_sha512_final(&ctx), AVB_SHA512_DIGEST_SIZE); + ret = true; + } break; + + /* Do not add a 'default:' case here because of -Wswitch. */ + } + + if (!ret) { + avb_fatal("Unknown digest type"); + } +} diff --git a/lib/avb/libavb/avb_slot_verify.h b/lib/avb/libavb/avb_slot_verify.h new file mode 100644 index 00000000000..375db3da318 --- /dev/null +++ b/lib/avb/libavb/avb_slot_verify.h @@ -0,0 +1,359 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_SLOT_VERIFY_H_ +#define AVB_SLOT_VERIFY_H_ + +#include "avb_ops.h" +#include "avb_vbmeta_image.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Return codes used in avb_slot_verify(), see that function for + * documentation for each field. + * + * Use avb_slot_verify_result_to_string() to get a textual + * representation usable for error/debug output. + */ +typedef enum { + AVB_SLOT_VERIFY_RESULT_OK, + AVB_SLOT_VERIFY_RESULT_ERROR_OOM, + AVB_SLOT_VERIFY_RESULT_ERROR_IO, + AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION, + AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX, + AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED, + AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA, + AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION, + AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT +} AvbSlotVerifyResult; + +/* Various error handling modes for when verification fails using a + * hashtree at runtime inside the HLOS. + * + * AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE means that the OS + * will invalidate the current slot and restart. + * + * AVB_HASHTREE_ERROR_MODE_RESTART means that the OS will restart. + * + * AVB_HASHTREE_ERROR_MODE_EIO means that an EIO error will be + * returned to applications. + * + * AVB_HASHTREE_ERROR_MODE_LOGGING means that errors will be logged + * and corrupt data may be returned to applications. This mode should + * be used ONLY for diagnostics and debugging. It cannot be used + * unless AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR is also + * used. + */ +typedef enum { + AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, + AVB_HASHTREE_ERROR_MODE_RESTART, + AVB_HASHTREE_ERROR_MODE_EIO, + AVB_HASHTREE_ERROR_MODE_LOGGING +} AvbHashtreeErrorMode; + +/* Flags that influence how avb_slot_verify() works. + * + * If AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR is NOT set then + * avb_slot_verify() will bail out as soon as an error is encountered + * and |out_data| is set only if AVB_SLOT_VERIFY_RESULT_OK is + * returned. + * + * Otherwise if AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR is set + * avb_slot_verify() will continue verification efforts and |out_data| + * is also set if AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED, + * AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION, or + * AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX is returned. It is + * undefined which error is returned if more than one distinct error + * is encountered. It is guaranteed that AVB_SLOT_VERIFY_RESULT_OK is + * returned if, and only if, there are no errors. This mode is needed + * to boot valid but unverified slots when the device is unlocked. + * + * Also, if AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR is set the + * contents loaded from |requested_partition| will be the contents of + * the entire partition instead of just the size specified in the hash + * descriptor. + */ +typedef enum { + AVB_SLOT_VERIFY_FLAGS_NONE = 0, + AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR = (1 << 0) +} AvbSlotVerifyFlags; + +/* Get a textual representation of |result|. */ +const char* avb_slot_verify_result_to_string(AvbSlotVerifyResult result); + +/* Maximum number of rollback index locations supported. */ +#define AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS 32 + +/* AvbPartitionData contains data loaded from partitions when using + * avb_slot_verify(). The |partition_name| field contains the name of + * the partition (without A/B suffix), |data| points to the loaded + * data which is |data_size| bytes long. If |preloaded| is set to true, + * this structure dose not own |data|. The caller of |avb_slot_verify| + * needs to make sure that the preloaded data outlives this + * |AvbPartitionData| structure. + * + * Note that this is strictly less than the partition size - it's only + * the image stored there, not the entire partition nor any of the + * metadata. + */ +typedef struct { + char* partition_name; + uint8_t* data; + size_t data_size; + bool preloaded; +} AvbPartitionData; + +/* AvbVBMetaData contains a vbmeta struct loaded from a partition when + * using avb_slot_verify(). The |partition_name| field contains the + * name of the partition (without A/B suffix), |vbmeta_data| points to + * the loaded data which is |vbmeta_size| bytes long. + * + * The |verify_result| field contains the result of + * avb_vbmeta_image_verify() on the data. This is guaranteed to be + * AVB_VBMETA_VERIFY_RESULT_OK for all vbmeta images if + * avb_slot_verify() returns AVB_SLOT_VERIFY_RESULT_OK. + * + * You can use avb_descriptor_get_all(), avb_descriptor_foreach(), and + * avb_vbmeta_image_header_to_host_byte_order() with this data. + */ +typedef struct { + char* partition_name; + uint8_t* vbmeta_data; + size_t vbmeta_size; + AvbVBMetaVerifyResult verify_result; +} AvbVBMetaData; + +/* AvbSlotVerifyData contains data needed to boot a particular slot + * and is returned by avb_slot_verify() if partitions in a slot are + * successfully verified. + * + * All data pointed to by this struct - including data in each item in + * the |partitions| array - will be freed when the + * avb_slot_verify_data_free() function is called. + * + * The |ab_suffix| field is the copy of the of |ab_suffix| field + * passed to avb_slot_verify(). It is the A/B suffix of the slot. This + * value includes the leading underscore - typical values are "" (if + * no slots are in use), "_a" (for the first slot), and "_b" (for the + * second slot). + * + * The VBMeta images that were checked are available in the + * |vbmeta_images| field. The field |num_vbmeta_images| contains the + * number of elements in this array. The first element - + * vbmeta_images[0] - is guaranteed to be from the partition with the + * top-level vbmeta struct. This is usually the "vbmeta" partition in + * the requested slot but if there is no "vbmeta" partition it can + * also be the "boot" partition. + * + * The partitions loaded and verified from from the slot are + * accessible in the |loaded_partitions| array. The field + * |num_loaded_partitions| contains the number of elements in this + * array. The order of partitions in this array may not necessarily be + * the same order as in the passed-in |requested_partitions| array. + * + * Rollback indexes for the verified slot are stored in the + * |rollback_indexes| field. Note that avb_slot_verify() will NEVER + * modify stored_rollback_index[n] locations e.g. it will never use + * the write_rollback_index() AvbOps operation. Instead it is the job + * of the caller of avb_slot_verify() to do this based on e.g. A/B + * policy and other factors. See libavb_ab/avb_ab_flow.c for an + * example of how to do this. + * + * The |cmdline| field is a NUL-terminated string in UTF-8 resulting + * from concatenating all |AvbKernelCmdlineDescriptor| and then + * performing proper substitution of the variables + * $(ANDROID_SYSTEM_PARTUUID), $(ANDROID_BOOT_PARTUUID), and + * $(ANDROID_VBMETA_PARTUUID) using the + * get_unique_guid_for_partition() operation in |AvbOps|. Additionally + * $(ANDROID_VERITY_MODE) will be replaced with the proper dm-verity + * option depending on the value of |hashtree_error_mode|. + * + * Additionally, the |cmdline| field will have the following kernel + * command-line options set (unless verification is disabled, see + * below): + * + * androidboot.veritymode: This is set to 'disabled' if the + * AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED flag is set in top-level + * vbmeta struct. Otherwise it is set to 'enforcing' if the + * passed-in hashtree error mode is AVB_HASHTREE_ERROR_MODE_RESTART + * or AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, 'eio' if it's + * set to AVB_HASHTREE_ERROR_MODE_EIO, and 'logging' if it's set to + * AVB_HASHTREE_ERROR_MODE_LOGGING. + * + * androidboot.vbmeta.invalidate_on_error: This is set to 'yes' only + * if hashtree validation isn't disabled and the passed-in hashtree + * error mode is AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE. + * + * androidboot.vbmeta.device_state: set to "locked" or "unlocked" + * depending on the result of the result of AvbOps's + * read_is_unlocked() function. + * + * androidboot.vbmeta.{hash_alg, size, digest}: Will be set to + * the digest of all images in |vbmeta_images|. + * + * androidboot.vbmeta.device: This is set to the value + * PARTUUID=$(ANDROID_VBMETA_PARTUUID) before substitution so it + * will end up pointing to the vbmeta partition for the verified + * slot. If there is no vbmeta partition it will point to the boot + * partition of the verified slot. + * + * androidboot.vbmeta.avb_version: This is set to the decimal value + * of AVB_VERSION_MAJOR followed by a dot followed by the decimal + * value of AVB_VERSION_MINOR, for example "1.0" or "1.4". This + * version number represents the vbmeta file format version + * supported by libavb copy used in the boot loader. This is not + * necessarily the same version number of the on-disk metadata for + * the slot that was verified. + * + * Note that androidboot.slot_suffix is not set in the |cmdline| field + * in |AvbSlotVerifyData| - you will have to set this yourself. + * + * If the |AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED| flag is set + * in the top-level vbmeta struct then only the top-level vbmeta + * struct is verified and descriptors will not processed. The return + * value will be set accordingly (if this flag is set via 'avbctl + * disable-verification' then the return value will be + * |AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION|) and + * |AvbSlotVerifyData| is returned. Additionally all partitions in the + * |requested_partitions| are loaded and the |cmdline| field is set to + * "root=PARTUUID=$(ANDROID_SYSTEM_PARTUUID)" and the GUID for the + * appropriate system partition is substituted in. Note that none of + * the androidboot.* options mentioned above will be set. + * + * This struct may grow in the future without it being considered an + * ABI break. + */ +typedef struct { + char* ab_suffix; + AvbVBMetaData* vbmeta_images; + size_t num_vbmeta_images; + AvbPartitionData* loaded_partitions; + size_t num_loaded_partitions; + char* cmdline; + uint64_t rollback_indexes[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS]; +} AvbSlotVerifyData; + +/* Calculates a digest of all vbmeta images in |data| using + * the digest indicated by |digest_type|. Stores the result + * in |out_digest| which must be large enough to hold a digest + * of the requested type. + */ +void avb_slot_verify_data_calculate_vbmeta_digest(AvbSlotVerifyData* data, + AvbDigestType digest_type, + uint8_t* out_digest); + +/* Frees a |AvbSlotVerifyData| including all data it points to. */ +void avb_slot_verify_data_free(AvbSlotVerifyData* data); + +/* Performs a full verification of the slot identified by |ab_suffix| + * and load and verify the contents of the partitions whose name is in + * the NULL-terminated string array |requested_partitions| (each + * partition must use hash verification). If not using A/B, pass an + * empty string (e.g. "", not NULL) for |ab_suffix|. This parameter + * must include the leading underscore, for example "_a" should be + * used to refer to the first slot. + * + * Typically the |requested_partitions| array only contains a single + * item for the boot partition, 'boot'. + * + * Verification includes loading and verifying data from the 'vbmeta', + * the requested hash partitions, and possibly other partitions (with + * |ab_suffix| appended), inspecting rollback indexes, and checking if + * the public key used to sign the data is acceptable. The functions + * in |ops| will be used to do this. + * + * If |out_data| is not NULL, it will be set to a newly allocated + * |AvbSlotVerifyData| struct containing all the data needed to + * actually boot the slot. This data structure should be freed with + * avb_slot_verify_data_free() when you are done with it. See below + * for when this is returned. + * + * The |flags| parameter is used to influence the semantics of + * avb_slot_verify() - for example the + * AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR flag can be used to + * ignore verification errors which is something needed in the + * UNLOCKED state. See the AvbSlotVerifyFlags enumeration for details. + * + * The |hashtree_error_mode| parameter should be set to the desired + * error handling mode when hashtree validation fails inside the + * HLOS. This value isn't used by libavb per se - it is forwarded to + * the HLOS through the androidboot.veritymode and + * androidboot.vbmeta.invalidate_on_error cmdline parameters. See the + * AvbHashtreeErrorMode enumeration for details. + * + * Also note that |out_data| is never set if + * AVB_SLOT_VERIFY_RESULT_ERROR_OOM, AVB_SLOT_VERIFY_RESULT_ERROR_IO, + * or AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA is returned. + * + * AVB_SLOT_VERIFY_RESULT_OK is returned if everything is verified + * correctly and all public keys are accepted. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED is returned if + * everything is verified correctly out but one or more public keys + * are not accepted. This includes the case where integrity data is + * not signed. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_OOM is returned if unable to + * allocate memory. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_IO is returned if an I/O error + * occurred while trying to load data or get a rollback index. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION is returned if the data + * did not verify, e.g. the digest didn't match or signature checks + * failed. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX is returned if a + * rollback index was less than its stored value. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA is returned if some + * of the metadata is invalid or inconsistent. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION is returned if + * some of the metadata requires a newer version of libavb than what + * is in use. + * + * AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT is returned if the + * caller passed invalid parameters, for example trying to use + * AVB_HASHTREE_ERROR_MODE_LOGGING without + * AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR. + */ +AvbSlotVerifyResult avb_slot_verify(AvbOps* ops, + const char* const* requested_partitions, + const char* ab_suffix, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data); + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_SLOT_VERIFY_H_ */ diff --git a/lib/avb/libavb/avb_sysdeps.h b/lib/avb/libavb/avb_sysdeps.h new file mode 100644 index 00000000000..cc832970f17 --- /dev/null +++ b/lib/avb/libavb/avb_sysdeps.h @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_SYSDEPS_H_ +#define AVB_SYSDEPS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Change these includes to match your platform to bring in the + * equivalent types available in a normal C runtime. At least things + * like uint8_t, uint64_t, and bool (with |false|, |true| keywords) + * must be present. + */ +#include + +/* If you don't have gcc or clang, these attribute macros may need to + * be adjusted. + */ +#define AVB_ATTR_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) +#define AVB_ATTR_PACKED __attribute__((packed)) +#define AVB_ATTR_NO_RETURN __attribute__((noreturn)) +#define AVB_ATTR_SENTINEL __attribute__((__sentinel__)) + +/* Size in bytes used for alignment. */ +#ifdef __LP64__ +#define AVB_ALIGNMENT_SIZE 8 +#else +#define AVB_ALIGNMENT_SIZE 4 +#endif + +/* Compare |n| bytes in |src1| and |src2|. + * + * Returns an integer less than, equal to, or greater than zero if the + * first |n| bytes of |src1| is found, respectively, to be less than, + * to match, or be greater than the first |n| bytes of |src2|. */ +int avb_memcmp(const void* src1, + const void* src2, + size_t n) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Compare two strings. + * + * Return an integer less than, equal to, or greater than zero if |s1| + * is found, respectively, to be less than, to match, or be greater + * than |s2|. + */ +int avb_strcmp(const char* s1, const char* s2); + +/* Copy |n| bytes from |src| to |dest|. */ +void* avb_memcpy(void* dest, const void* src, size_t n); + +/* Set |n| bytes starting at |s| to |c|. Returns |dest|. */ +void* avb_memset(void* dest, const int c, size_t n); + +/* Prints out a message. The string passed must be a NUL-terminated + * UTF-8 string. + */ +void avb_print(const char* message); + +/* Prints out a vector of strings. Each argument must point to a + * NUL-terminated UTF-8 string and NULL should be the last argument. + */ +void avb_printv(const char* message, ...) AVB_ATTR_SENTINEL; + +/* Aborts the program or reboots the device. */ +void avb_abort(void) AVB_ATTR_NO_RETURN; + +/* Allocates |size| bytes. Returns NULL if no memory is available, + * otherwise a pointer to the allocated memory. + * + * The memory is not initialized. + * + * The pointer returned is guaranteed to be word-aligned. + * + * The memory should be freed with avb_free() when you are done with it. + */ +void* avb_malloc_(size_t size) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Frees memory previously allocated with avb_malloc(). */ +void avb_free(void* ptr); + +/* Returns the lenght of |str|, excluding the terminating NUL-byte. */ +size_t avb_strlen(const char* str) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Divide the |dividend| by 10 and saves back to the pointer. Return the + * remainder. */ +uint32_t avb_div_by_10(uint64_t* dividend); + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_SYSDEPS_H_ */ diff --git a/lib/avb/libavb/avb_sysdeps_posix.c b/lib/avb/libavb/avb_sysdeps_posix.c new file mode 100644 index 00000000000..0cbabee06cf --- /dev/null +++ b/lib/avb/libavb/avb_sysdeps_posix.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "avb_sysdeps.h" + +int avb_memcmp(const void* src1, const void* src2, size_t n) { + return memcmp(src1, src2, n); +} + +void* avb_memcpy(void* dest, const void* src, size_t n) { + return memcpy(dest, src, n); +} + +void* avb_memset(void* dest, const int c, size_t n) { + return memset(dest, c, n); +} + +int avb_strcmp(const char* s1, const char* s2) { + return strcmp(s1, s2); +} + +size_t avb_strlen(const char* str) { + return strlen(str); +} + +void avb_abort(void) { + abort(); +} + +void avb_print(const char* message) { + fprintf(stderr, "%s", message); +} + +void avb_printv(const char* message, ...) { + va_list ap; + const char* m; + + va_start(ap, message); + for (m = message; m != NULL; m = va_arg(ap, const char*)) { + fprintf(stderr, "%s", m); + } + va_end(ap); +} + +void* avb_malloc_(size_t size) { + return malloc(size); +} + +void avb_free(void* ptr) { + free(ptr); +} + +uint32_t avb_div_by_10(uint64_t* dividend) { + uint32_t rem = (uint32_t)(*dividend % 10); + *dividend /= 10; + return rem; +} diff --git a/lib/avb/libavb/avb_util.c b/lib/avb/libavb/avb_util.c new file mode 100644 index 00000000000..c04c79ae71c --- /dev/null +++ b/lib/avb/libavb/avb_util.c @@ -0,0 +1,430 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_util.h" + +#include + +uint32_t avb_be32toh(uint32_t in) { + uint8_t* d = (uint8_t*)∈ + uint32_t ret; + ret = ((uint32_t)d[0]) << 24; + ret |= ((uint32_t)d[1]) << 16; + ret |= ((uint32_t)d[2]) << 8; + ret |= ((uint32_t)d[3]); + return ret; +} + +uint64_t avb_be64toh(uint64_t in) { + uint8_t* d = (uint8_t*)∈ + uint64_t ret; + ret = ((uint64_t)d[0]) << 56; + ret |= ((uint64_t)d[1]) << 48; + ret |= ((uint64_t)d[2]) << 40; + ret |= ((uint64_t)d[3]) << 32; + ret |= ((uint64_t)d[4]) << 24; + ret |= ((uint64_t)d[5]) << 16; + ret |= ((uint64_t)d[6]) << 8; + ret |= ((uint64_t)d[7]); + return ret; +} + +/* Converts a 32-bit unsigned integer from host to big-endian byte order. */ +uint32_t avb_htobe32(uint32_t in) { + union { + uint32_t word; + uint8_t bytes[4]; + } ret; + ret.bytes[0] = (in >> 24) & 0xff; + ret.bytes[1] = (in >> 16) & 0xff; + ret.bytes[2] = (in >> 8) & 0xff; + ret.bytes[3] = in & 0xff; + return ret.word; +} + +/* Converts a 64-bit unsigned integer from host to big-endian byte order. */ +uint64_t avb_htobe64(uint64_t in) { + union { + uint64_t word; + uint8_t bytes[8]; + } ret; + ret.bytes[0] = (in >> 56) & 0xff; + ret.bytes[1] = (in >> 48) & 0xff; + ret.bytes[2] = (in >> 40) & 0xff; + ret.bytes[3] = (in >> 32) & 0xff; + ret.bytes[4] = (in >> 24) & 0xff; + ret.bytes[5] = (in >> 16) & 0xff; + ret.bytes[6] = (in >> 8) & 0xff; + ret.bytes[7] = in & 0xff; + return ret.word; +} + +int avb_safe_memcmp(const void* s1, const void* s2, size_t n) { + const unsigned char* us1 = s1; + const unsigned char* us2 = s2; + int result = 0; + + if (0 == n) { + return 0; + } + + /* + * Code snippet without data-dependent branch due to Nate Lawson + * (nate@root.org) of Root Labs. + */ + while (n--) { + result |= *us1++ ^ *us2++; + } + + return result != 0; +} + +bool avb_safe_add_to(uint64_t* value, uint64_t value_to_add) { + uint64_t original_value; + + avb_assert(value != NULL); + + original_value = *value; + + *value += value_to_add; + if (*value < original_value) { + avb_error("Overflow when adding values.\n"); + return false; + } + + return true; +} + +bool avb_safe_add(uint64_t* out_result, uint64_t a, uint64_t b) { + uint64_t dummy; + if (out_result == NULL) { + out_result = &dummy; + } + *out_result = a; + return avb_safe_add_to(out_result, b); +} + +bool avb_validate_utf8(const uint8_t* data, size_t num_bytes) { + size_t n; + unsigned int num_cc; + + for (n = 0, num_cc = 0; n < num_bytes; n++) { + uint8_t c = data[n]; + + if (num_cc > 0) { + if ((c & (0x80 | 0x40)) == 0x80) { + /* 10xx xxxx */ + } else { + goto fail; + } + num_cc--; + } else { + if (c < 0x80) { + num_cc = 0; + } else if ((c & (0x80 | 0x40 | 0x20)) == (0x80 | 0x40)) { + /* 110x xxxx */ + num_cc = 1; + } else if ((c & (0x80 | 0x40 | 0x20 | 0x10)) == (0x80 | 0x40 | 0x20)) { + /* 1110 xxxx */ + num_cc = 2; + } else if ((c & (0x80 | 0x40 | 0x20 | 0x10 | 0x08)) == + (0x80 | 0x40 | 0x20 | 0x10)) { + /* 1111 0xxx */ + num_cc = 3; + } else { + goto fail; + } + } + } + + if (num_cc != 0) { + goto fail; + } + + return true; + +fail: + return false; +} + +bool avb_str_concat(char* buf, + size_t buf_size, + const char* str1, + size_t str1_len, + const char* str2, + size_t str2_len) { + uint64_t combined_len; + + if (!avb_safe_add(&combined_len, str1_len, str2_len)) { + avb_error("Overflow when adding string sizes.\n"); + return false; + } + + if (combined_len > buf_size - 1) { + avb_error("Insufficient buffer space.\n"); + return false; + } + + avb_memcpy(buf, str1, str1_len); + avb_memcpy(buf + str1_len, str2, str2_len); + buf[combined_len] = '\0'; + + return true; +} + +void* avb_malloc(size_t size) { + void* ret = avb_malloc_(size); + if (ret == NULL) { + avb_error("Failed to allocate memory.\n"); + return NULL; + } + return ret; +} + +void* avb_calloc(size_t size) { + void* ret = avb_malloc(size); + if (ret == NULL) { + return NULL; + } + + avb_memset(ret, '\0', size); + return ret; +} + +char* avb_strdup(const char* str) { + size_t len = avb_strlen(str); + char* ret = avb_malloc(len + 1); + if (ret == NULL) { + return NULL; + } + + avb_memcpy(ret, str, len); + ret[len] = '\0'; + + return ret; +} + +const char* avb_strstr(const char* haystack, const char* needle) { + size_t n, m; + + /* Look through |haystack| and check if the first character of + * |needle| matches. If so, check the rest of |needle|. + */ + for (n = 0; haystack[n] != '\0'; n++) { + if (haystack[n] != needle[0]) { + continue; + } + + for (m = 1;; m++) { + if (needle[m] == '\0') { + return haystack + n; + } + + if (haystack[n + m] != needle[m]) { + break; + } + } + } + + return NULL; +} + +const char* avb_strv_find_str(const char* const* strings, + const char* str, + size_t str_size) { + size_t n; + for (n = 0; strings[n] != NULL; n++) { + if (avb_strlen(strings[n]) == str_size && + avb_memcmp(strings[n], str, str_size) == 0) { + return strings[n]; + } + } + return NULL; +} + +char* avb_replace(const char* str, const char* search, const char* replace) { + char* ret = NULL; + size_t ret_len = 0; + size_t search_len, replace_len; + const char* str_after_last_replace; + + search_len = avb_strlen(search); + replace_len = avb_strlen(replace); + + str_after_last_replace = str; + while (*str != '\0') { + const char* s; + size_t num_before; + size_t num_new; + + s = avb_strstr(str, search); + if (s == NULL) { + break; + } + + num_before = s - str; + + if (ret == NULL) { + num_new = num_before + replace_len + 1; + ret = avb_malloc(num_new); + if (ret == NULL) { + goto out; + } + avb_memcpy(ret, str, num_before); + avb_memcpy(ret + num_before, replace, replace_len); + ret[num_new - 1] = '\0'; + ret_len = num_new - 1; + } else { + char* new_str; + num_new = ret_len + num_before + replace_len + 1; + new_str = avb_malloc(num_new); + if (new_str == NULL) { + goto out; + } + avb_memcpy(new_str, ret, ret_len); + avb_memcpy(new_str + ret_len, str, num_before); + avb_memcpy(new_str + ret_len + num_before, replace, replace_len); + new_str[num_new - 1] = '\0'; + avb_free(ret); + ret = new_str; + ret_len = num_new - 1; + } + + str = s + search_len; + str_after_last_replace = str; + } + + if (ret == NULL) { + ret = avb_strdup(str_after_last_replace); + if (ret == NULL) { + goto out; + } + } else { + size_t num_remaining = avb_strlen(str_after_last_replace); + size_t num_new = ret_len + num_remaining + 1; + char* new_str = avb_malloc(num_new); + if (new_str == NULL) { + goto out; + } + avb_memcpy(new_str, ret, ret_len); + avb_memcpy(new_str + ret_len, str_after_last_replace, num_remaining); + new_str[num_new - 1] = '\0'; + avb_free(ret); + ret = new_str; + ret_len = num_new - 1; + } + +out: + return ret; +} + +/* We only support a limited amount of strings in avb_strdupv(). */ +#define AVB_STRDUPV_MAX_NUM_STRINGS 32 + +char* avb_strdupv(const char* str, ...) { + va_list ap; + const char* strings[AVB_STRDUPV_MAX_NUM_STRINGS]; + size_t lengths[AVB_STRDUPV_MAX_NUM_STRINGS]; + size_t num_strings, n; + uint64_t total_length; + char *ret = NULL, *dest; + + num_strings = 0; + total_length = 0; + va_start(ap, str); + do { + size_t str_len = avb_strlen(str); + strings[num_strings] = str; + lengths[num_strings] = str_len; + if (!avb_safe_add_to(&total_length, str_len)) { + avb_fatal("Overflow while determining total length.\n"); + break; + } + num_strings++; + if (num_strings == AVB_STRDUPV_MAX_NUM_STRINGS) { + avb_fatal("Too many strings passed.\n"); + break; + } + str = va_arg(ap, const char*); + } while (str != NULL); + va_end(ap); + + ret = avb_malloc(total_length + 1); + if (ret == NULL) { + goto out; + } + + dest = ret; + for (n = 0; n < num_strings; n++) { + avb_memcpy(dest, strings[n], lengths[n]); + dest += lengths[n]; + } + *dest = '\0'; + avb_assert(dest == ret + total_length); + +out: + return ret; +} + +const char* avb_basename(const char* str) { + int64_t n; + size_t len; + + len = avb_strlen(str); + if (len >= 2) { + for (n = len - 2; n >= 0; n--) { + if (str[n] == '/') { + return str + n + 1; + } + } + } + return str; +} + +void avb_uppercase(char* str) { + size_t i; + for (i = 0; str[i] != '\0'; ++i) { + if (str[i] <= 0x7A && str[i] >= 0x61) { + str[i] -= 0x20; + } + } +} + +char* avb_bin2hex(const uint8_t* data, size_t data_len) { + const char hex_digits[17] = "0123456789abcdef"; + char* hex_data; + size_t n; + + hex_data = avb_malloc(data_len * 2 + 1); + if (hex_data == NULL) { + return NULL; + } + + for (n = 0; n < data_len; n++) { + hex_data[n * 2] = hex_digits[data[n] >> 4]; + hex_data[n * 2 + 1] = hex_digits[data[n] & 0x0f]; + } + hex_data[n * 2] = '\0'; + return hex_data; +} diff --git a/lib/avb/libavb/avb_util.h b/lib/avb/libavb/avb_util.h new file mode 100644 index 00000000000..be1b3c9b21f --- /dev/null +++ b/lib/avb/libavb/avb_util.h @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_UTIL_H_ +#define AVB_UTIL_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define AVB_STRINGIFY(x) #x +#define AVB_TO_STRING(x) AVB_STRINGIFY(x) + +#ifdef AVB_ENABLE_DEBUG +/* Aborts the program if |expr| is false. + * + * This has no effect unless AVB_ENABLE_DEBUG is defined. + */ +#define avb_assert(expr) \ + do { \ + if (!(expr)) { \ + avb_fatal("assert fail: " #expr "\n"); \ + } \ + } while (0) +#else +#define avb_assert(expr) +#endif + +/* Aborts the program if reached. + * + * This has no effect unless AVB_ENABLE_DEBUG is defined. + */ +#ifdef AVB_ENABLE_DEBUG +#define avb_assert_not_reached() \ + do { \ + avb_fatal("assert_not_reached()\n"); \ + } while (0) +#else +#define avb_assert_not_reached() +#endif + +/* Aborts the program if |addr| is not word-aligned. + * + * This has no effect unless AVB_ENABLE_DEBUG is defined. + */ +#define avb_assert_aligned(addr) \ + avb_assert((((uintptr_t)addr) & (AVB_ALIGNMENT_SIZE - 1)) == 0) + +#ifdef AVB_ENABLE_DEBUG +/* Print functions, used for diagnostics. + * + * These have no effect unless AVB_ENABLE_DEBUG is defined. + */ +#define avb_debug(message) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": DEBUG: ", \ + message, \ + NULL); \ + } while (0) +#define avb_debugv(message, ...) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": DEBUG: ", \ + message, \ + ##__VA_ARGS__); \ + } while (0) +#else +#define avb_debug(message) +#define avb_debugv(message, ...) +#endif + +/* Prints out a message. This is typically used if a runtime-error + * occurs. + */ +#define avb_error(message) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": ERROR: ", \ + message, \ + NULL); \ + } while (0) +#define avb_errorv(message, ...) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": ERROR: ", \ + message, \ + ##__VA_ARGS__); \ + } while (0) + +/* Prints out a message and calls avb_abort(). + */ +#define avb_fatal(message) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": FATAL: ", \ + message, \ + NULL); \ + avb_abort(); \ + } while (0) +#define avb_fatalv(message, ...) \ + do { \ + avb_printv(avb_basename(__FILE__), \ + ":", \ + AVB_TO_STRING(__LINE__), \ + ": FATAL: ", \ + message, \ + ##__VA_ARGS__); \ + avb_abort(); \ + } while (0) + +/* Converts a 32-bit unsigned integer from big-endian to host byte order. */ +uint32_t avb_be32toh(uint32_t in) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Converts a 64-bit unsigned integer from big-endian to host byte order. */ +uint64_t avb_be64toh(uint64_t in) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Converts a 32-bit unsigned integer from host to big-endian byte order. */ +uint32_t avb_htobe32(uint32_t in) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Converts a 64-bit unsigned integer from host to big-endian byte order. */ +uint64_t avb_htobe64(uint64_t in) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Compare |n| bytes starting at |s1| with |s2| and return 0 if they + * match, 1 if they don't. Returns 0 if |n|==0, since no bytes + * mismatched. + * + * Time taken to perform the comparison is only dependent on |n| and + * not on the relationship of the match between |s1| and |s2|. + * + * Note that unlike avb_memcmp(), this only indicates inequality, not + * whether |s1| is less than or greater than |s2|. + */ +int avb_safe_memcmp(const void* s1, + const void* s2, + size_t n) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Adds |value_to_add| to |value| with overflow protection. + * + * Returns false if the addition overflows, true otherwise. In either + * case, |value| is always modified. + */ +bool avb_safe_add_to(uint64_t* value, + uint64_t value_to_add) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Adds |a| and |b| with overflow protection, returning the value in + * |out_result|. + * + * It's permissible to pass NULL for |out_result| if you just want to + * check that the addition would not overflow. + * + * Returns false if the addition overflows, true otherwise. + */ +bool avb_safe_add(uint64_t* out_result, + uint64_t a, + uint64_t b) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Checks if |num_bytes| data at |data| is a valid UTF-8 + * string. Returns true if valid UTF-8, false otherwise. + */ +bool avb_validate_utf8(const uint8_t* data, + size_t num_bytes) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Concatenates |str1| (of |str1_len| bytes) and |str2| (of |str2_len| + * bytes) and puts the result in |buf| which holds |buf_size| + * bytes. The result is also guaranteed to be NUL terminated. Fail if + * there is not enough room in |buf| for the resulting string plus + * terminating NUL byte. + * + * Returns true if the operation succeeds, false otherwise. + */ +bool avb_str_concat(char* buf, + size_t buf_size, + const char* str1, + size_t str1_len, + const char* str2, + size_t str2_len); + +/* Like avb_malloc_() but prints a error using avb_error() if memory + * allocation fails. + */ +void* avb_malloc(size_t size) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Like avb_malloc() but sets the memory with zeroes. */ +void* avb_calloc(size_t size) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Duplicates a NUL-terminated string. Returns NULL on OOM. */ +char* avb_strdup(const char* str) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Duplicates a NULL-terminated array of NUL-terminated strings by + * concatenating them. The returned string will be + * NUL-terminated. Returns NULL on OOM. + */ +char* avb_strdupv(const char* str, + ...) AVB_ATTR_WARN_UNUSED_RESULT AVB_ATTR_SENTINEL; + +/* Finds the first occurrence of |needle| in the string |haystack| + * where both strings are NUL-terminated strings. The terminating NUL + * bytes are not compared. + * + * Returns NULL if not found, otherwise points into |haystack| for the + * first occurrence of |needle|. + */ +const char* avb_strstr(const char* haystack, + const char* needle) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Finds the first occurrence of |str| in the NULL-terminated string + * array |strings|. Each element in |strings| must be + * NUL-terminated. The string given by |str| need not be + * NUL-terminated but its size must be given in |str_size|. + * + * Returns NULL if not found, otherwise points into |strings| for the + * first occurrence of |str|. + */ +const char* avb_strv_find_str(const char* const* strings, + const char* str, + size_t str_size); + +/* Replaces all occurrences of |search| with |replace| in |str|. + * + * Returns a newly allocated string or NULL if out of memory. + */ +char* avb_replace(const char* str, + const char* search, + const char* replace) AVB_ATTR_WARN_UNUSED_RESULT; + +/* Calculates the CRC-32 for data in |buf| of size |buf_size|. */ +uint32_t avb_crc32(const uint8_t* buf, size_t buf_size); + +/* Returns the basename of |str|. This is defined as the last path + * component, assuming the normal POSIX separator '/'. If there are no + * separators, returns |str|. + */ +const char* avb_basename(const char* str); + +/* Converts any ascii lowercase characters in |str| to uppercase in-place. + * |str| must be NUL-terminated and valid UTF-8. + */ +void avb_uppercase(char* str); + +/* Converts |data_len| bytes of |data| to hex and returns the result. Returns + * NULL on OOM. Caller must free the returned string with avb_free. + */ +char* avb_bin2hex(const uint8_t* data, size_t data_len); + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_UTIL_H_ */ diff --git a/lib/avb/libavb/avb_vbmeta_image.c b/lib/avb/libavb/avb_vbmeta_image.c new file mode 100644 index 00000000000..21bbf9295d5 --- /dev/null +++ b/lib/avb/libavb/avb_vbmeta_image.c @@ -0,0 +1,308 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_vbmeta_image.h" +#include "avb_crypto.h" +#include "avb_rsa.h" +#include "avb_sha.h" +#include "avb_util.h" +#include "avb_version.h" + +AvbVBMetaVerifyResult avb_vbmeta_image_verify( + const uint8_t* data, + size_t length, + const uint8_t** out_public_key_data, + size_t* out_public_key_length) { + AvbVBMetaVerifyResult ret; + AvbVBMetaImageHeader h; + uint8_t* computed_hash; + const AvbAlgorithmData* algorithm; + AvbSHA256Ctx sha256_ctx; + AvbSHA512Ctx sha512_ctx; + const uint8_t* header_block; + const uint8_t* authentication_block; + const uint8_t* auxiliary_block; + int verification_result; + + ret = AVB_VBMETA_VERIFY_RESULT_INVALID_VBMETA_HEADER; + + if (out_public_key_data != NULL) { + *out_public_key_data = NULL; + } + if (out_public_key_length != NULL) { + *out_public_key_length = 0; + } + + /* Ensure magic is correct. */ + if (avb_safe_memcmp(data, AVB_MAGIC, AVB_MAGIC_LEN) != 0) { + avb_error("Magic is incorrect.\n"); + goto out; + } + + /* Before we byteswap, ensure length is long enough. */ + if (length < sizeof(AvbVBMetaImageHeader)) { + avb_error("Length is smaller than header.\n"); + goto out; + } + avb_vbmeta_image_header_to_host_byte_order((const AvbVBMetaImageHeader*)data, + &h); + + /* Ensure we don't attempt to access any fields if we do not meet + * the specified minimum version of libavb. + */ + if ((h.required_libavb_version_major != AVB_VERSION_MAJOR) || + (h.required_libavb_version_minor > AVB_VERSION_MINOR)) { + avb_error("Mismatch between image version and libavb version.\n"); + ret = AVB_VBMETA_VERIFY_RESULT_UNSUPPORTED_VERSION; + goto out; + } + + /* Ensure |release_string| ends with a NUL byte. */ + if (h.release_string[AVB_RELEASE_STRING_SIZE - 1] != '\0') { + avb_error("Release string does not end with a NUL byte.\n"); + goto out; + } + + /* Ensure inner block sizes are multiple of 64. */ + if ((h.authentication_data_block_size & 0x3f) != 0 || + (h.auxiliary_data_block_size & 0x3f) != 0) { + avb_error("Block size is not a multiple of 64.\n"); + goto out; + } + + /* Ensure block sizes all add up to at most |length|. */ + uint64_t block_total = sizeof(AvbVBMetaImageHeader); + if (!avb_safe_add_to(&block_total, h.authentication_data_block_size) || + !avb_safe_add_to(&block_total, h.auxiliary_data_block_size)) { + avb_error("Overflow while computing size of boot image.\n"); + goto out; + } + if (block_total > length) { + avb_error("Block sizes add up to more than given length.\n"); + goto out; + } + + uintptr_t data_ptr = (uintptr_t)data; + /* Ensure passed in memory doesn't wrap. */ + if (!avb_safe_add(NULL, (uint64_t)data_ptr, length)) { + avb_error("Boot image location and length mismatch.\n"); + goto out; + } + + /* Ensure hash and signature are entirely in the Authentication data block. */ + uint64_t hash_end; + if (!avb_safe_add(&hash_end, h.hash_offset, h.hash_size) || + hash_end > h.authentication_data_block_size) { + avb_error("Hash is not entirely in its block.\n"); + goto out; + } + uint64_t signature_end; + if (!avb_safe_add(&signature_end, h.signature_offset, h.signature_size) || + signature_end > h.authentication_data_block_size) { + avb_error("Signature is not entirely in its block.\n"); + goto out; + } + + /* Ensure public key is entirely in the Auxiliary data block. */ + uint64_t pubkey_end; + if (!avb_safe_add(&pubkey_end, h.public_key_offset, h.public_key_size) || + pubkey_end > h.auxiliary_data_block_size) { + avb_error("Public key is not entirely in its block.\n"); + goto out; + } + + /* Ensure public key metadata (if set) is entirely in the Auxiliary + * data block. */ + if (h.public_key_metadata_size > 0) { + uint64_t pubkey_md_end; + if (!avb_safe_add(&pubkey_md_end, + h.public_key_metadata_offset, + h.public_key_metadata_size) || + pubkey_md_end > h.auxiliary_data_block_size) { + avb_error("Public key metadata is not entirely in its block.\n"); + goto out; + } + } + + /* Bail early if there's no hash or signature. */ + if (h.algorithm_type == AVB_ALGORITHM_TYPE_NONE) { + ret = AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED; + goto out; + } + + /* Ensure algorithm field is supported. */ + algorithm = avb_get_algorithm_data(h.algorithm_type); + if (!algorithm) { + avb_error("Invalid or unknown algorithm.\n"); + goto out; + } + + /* Bail if the embedded hash size doesn't match the chosen algorithm. */ + if (h.hash_size != algorithm->hash_len) { + avb_error("Embedded hash has wrong size.\n"); + goto out; + } + + /* No overflow checks needed from here-on after since all block + * sizes and offsets have been verified above. + */ + + header_block = data; + authentication_block = header_block + sizeof(AvbVBMetaImageHeader); + auxiliary_block = authentication_block + h.authentication_data_block_size; + + switch (h.algorithm_type) { + /* Explicit fall-through: */ + case AVB_ALGORITHM_TYPE_SHA256_RSA2048: + case AVB_ALGORITHM_TYPE_SHA256_RSA4096: + case AVB_ALGORITHM_TYPE_SHA256_RSA8192: + avb_sha256_init(&sha256_ctx); + avb_sha256_update( + &sha256_ctx, header_block, sizeof(AvbVBMetaImageHeader)); + avb_sha256_update( + &sha256_ctx, auxiliary_block, h.auxiliary_data_block_size); + computed_hash = avb_sha256_final(&sha256_ctx); + break; + /* Explicit fall-through: */ + case AVB_ALGORITHM_TYPE_SHA512_RSA2048: + case AVB_ALGORITHM_TYPE_SHA512_RSA4096: + case AVB_ALGORITHM_TYPE_SHA512_RSA8192: + avb_sha512_init(&sha512_ctx); + avb_sha512_update( + &sha512_ctx, header_block, sizeof(AvbVBMetaImageHeader)); + avb_sha512_update( + &sha512_ctx, auxiliary_block, h.auxiliary_data_block_size); + computed_hash = avb_sha512_final(&sha512_ctx); + break; + default: + avb_error("Unknown algorithm.\n"); + goto out; + } + + if (avb_safe_memcmp(authentication_block + h.hash_offset, + computed_hash, + h.hash_size) != 0) { + avb_error("Hash does not match!\n"); + ret = AVB_VBMETA_VERIFY_RESULT_HASH_MISMATCH; + goto out; + } + + verification_result = + avb_rsa_verify(auxiliary_block + h.public_key_offset, + h.public_key_size, + authentication_block + h.signature_offset, + h.signature_size, + authentication_block + h.hash_offset, + h.hash_size, + algorithm->padding, + algorithm->padding_len); + + if (verification_result == 0) { + ret = AVB_VBMETA_VERIFY_RESULT_SIGNATURE_MISMATCH; + goto out; + } + + if (h.public_key_size > 0) { + if (out_public_key_data != NULL) { + *out_public_key_data = auxiliary_block + h.public_key_offset; + } + if (out_public_key_length != NULL) { + *out_public_key_length = h.public_key_size; + } + } + + ret = AVB_VBMETA_VERIFY_RESULT_OK; + +out: + return ret; +} + +void avb_vbmeta_image_header_to_host_byte_order(const AvbVBMetaImageHeader* src, + AvbVBMetaImageHeader* dest) { + avb_memcpy(dest, src, sizeof(AvbVBMetaImageHeader)); + + dest->required_libavb_version_major = + avb_be32toh(dest->required_libavb_version_major); + dest->required_libavb_version_minor = + avb_be32toh(dest->required_libavb_version_minor); + + dest->authentication_data_block_size = + avb_be64toh(dest->authentication_data_block_size); + dest->auxiliary_data_block_size = + avb_be64toh(dest->auxiliary_data_block_size); + + dest->algorithm_type = avb_be32toh(dest->algorithm_type); + + dest->hash_offset = avb_be64toh(dest->hash_offset); + dest->hash_size = avb_be64toh(dest->hash_size); + + dest->signature_offset = avb_be64toh(dest->signature_offset); + dest->signature_size = avb_be64toh(dest->signature_size); + + dest->public_key_offset = avb_be64toh(dest->public_key_offset); + dest->public_key_size = avb_be64toh(dest->public_key_size); + + dest->public_key_metadata_offset = + avb_be64toh(dest->public_key_metadata_offset); + dest->public_key_metadata_size = avb_be64toh(dest->public_key_metadata_size); + + dest->descriptors_offset = avb_be64toh(dest->descriptors_offset); + dest->descriptors_size = avb_be64toh(dest->descriptors_size); + + dest->rollback_index = avb_be64toh(dest->rollback_index); + dest->flags = avb_be32toh(dest->flags); +} + +const char* avb_vbmeta_verify_result_to_string(AvbVBMetaVerifyResult result) { + const char* ret = NULL; + + switch (result) { + case AVB_VBMETA_VERIFY_RESULT_OK: + ret = "OK"; + break; + case AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED: + ret = "OK_NOT_SIGNED"; + break; + case AVB_VBMETA_VERIFY_RESULT_INVALID_VBMETA_HEADER: + ret = "INVALID_VBMETA_HEADER"; + break; + case AVB_VBMETA_VERIFY_RESULT_UNSUPPORTED_VERSION: + ret = "UNSUPPORTED_VERSION"; + break; + case AVB_VBMETA_VERIFY_RESULT_HASH_MISMATCH: + ret = "HASH_MISMATCH"; + break; + case AVB_VBMETA_VERIFY_RESULT_SIGNATURE_MISMATCH: + ret = "SIGNATURE_MISMATCH"; + break; + /* Do not add a 'default:' case here because of -Wswitch. */ + } + + if (ret == NULL) { + avb_error("Unknown AvbVBMetaVerifyResult value.\n"); + ret = "(unknown)"; + } + + return ret; +} diff --git a/lib/avb/libavb/avb_vbmeta_image.h b/lib/avb/libavb/avb_vbmeta_image.h new file mode 100644 index 00000000000..d0c9f153765 --- /dev/null +++ b/lib/avb/libavb/avb_vbmeta_image.h @@ -0,0 +1,294 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_VBMETA_IMAGE_H_ +#define AVB_VBMETA_IMAGE_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "avb_crypto.h" +#include "avb_descriptor.h" + +/* Size of the vbmeta image header. */ +#define AVB_VBMETA_IMAGE_HEADER_SIZE 256 + +/* Magic for the vbmeta image header. */ +#define AVB_MAGIC "AVB0" +#define AVB_MAGIC_LEN 4 + +/* Maximum size of the release string including the terminating NUL byte. */ +#define AVB_RELEASE_STRING_SIZE 48 + +/* Flags for the vbmeta image. + * + * AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED: If this flag is set, + * hashtree image verification will be disabled. + * + * AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED: If this flag is set, + * verification will be disabled and descriptors will not be parsed. + */ +typedef enum { + AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED = (1 << 0), + AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED = (1 << 1) +} AvbVBMetaImageFlags; + +/* Binary format for header of the vbmeta image. + * + * The vbmeta image consists of three blocks: + * + * +-----------------------------------------+ + * | Header data - fixed size | + * +-----------------------------------------+ + * | Authentication data - variable size | + * +-----------------------------------------+ + * | Auxiliary data - variable size | + * +-----------------------------------------+ + * + * The "Header data" block is described by this struct and is always + * |AVB_VBMETA_IMAGE_HEADER_SIZE| bytes long. + * + * The "Authentication data" block is |authentication_data_block_size| + * bytes long and contains the hash and signature used to authenticate + * the vbmeta image. The type of the hash and signature is defined by + * the |algorithm_type| field. + * + * The "Auxiliary data" is |auxiliary_data_block_size| bytes long and + * contains the auxiliary data including the public key used to make + * the signature and descriptors. + * + * The public key is at offset |public_key_offset| with size + * |public_key_size| in this block. The size of the public key data is + * defined by the |algorithm_type| field. The format of the public key + * data is described in the |AvbRSAPublicKeyHeader| struct. + * + * The descriptors starts at |descriptors_offset| from the beginning + * of the "Auxiliary Data" block and take up |descriptors_size| + * bytes. Each descriptor is stored as a |AvbDescriptor| with tag and + * number of bytes following. The number of descriptors can be + * determined by walking this data until |descriptors_size| is + * exhausted. + * + * The size of each of the "Authentication data" and "Auxiliary data" + * blocks must be divisible by 64. This is to ensure proper alignment. + * + * Descriptors are free-form blocks stored in a part of the vbmeta + * image subject to the same integrity checks as the rest of the + * image. See the documentation for |AvbDescriptor| for well-known + * descriptors. See avb_descriptor_foreach() for a convenience + * function to iterate over descriptors. + * + * This struct is versioned, see the |required_libavb_version_major| + * and |required_libavb_version_minor| fields. This represents the + * minimum version of libavb required to verify the header and depends + * on the features (e.g. algorithms, descriptors) used. Note that this + * may be 1.0 even if generated by an avbtool from 1.4 but where no + * features introduced after 1.0 has been used. See the "Versioning + * and compatibility" section in the README.md file for more details. + * + * All fields are stored in network byte order when serialized. To + * generate a copy with fields swapped to native byte order, use the + * function avb_vbmeta_image_header_to_host_byte_order(). + * + * Before reading and/or using any of this data, you MUST verify it + * using avb_vbmeta_image_verify() and reject it unless it's signed by + * a known good public key. + */ +typedef struct AvbVBMetaImageHeader { + /* 0: Four bytes equal to "AVB0" (AVB_MAGIC). */ + uint8_t magic[AVB_MAGIC_LEN]; + + /* 4: The major version of libavb required for this header. */ + uint32_t required_libavb_version_major; + /* 8: The minor version of libavb required for this header. */ + uint32_t required_libavb_version_minor; + + /* 12: The size of the signature block. */ + uint64_t authentication_data_block_size; + /* 20: The size of the auxiliary data block. */ + uint64_t auxiliary_data_block_size; + + /* 28: The verification algorithm used, see |AvbAlgorithmType| enum. */ + uint32_t algorithm_type; + + /* 32: Offset into the "Authentication data" block of hash data. */ + uint64_t hash_offset; + /* 40: Length of the hash data. */ + uint64_t hash_size; + + /* 48: Offset into the "Authentication data" block of signature data. */ + uint64_t signature_offset; + /* 56: Length of the signature data. */ + uint64_t signature_size; + + /* 64: Offset into the "Auxiliary data" block of public key data. */ + uint64_t public_key_offset; + /* 72: Length of the public key data. */ + uint64_t public_key_size; + + /* 80: Offset into the "Auxiliary data" block of public key metadata. */ + uint64_t public_key_metadata_offset; + /* 88: Length of the public key metadata. Must be set to zero if there + * is no public key metadata. + */ + uint64_t public_key_metadata_size; + + /* 96: Offset into the "Auxiliary data" block of descriptor data. */ + uint64_t descriptors_offset; + /* 104: Length of descriptor data. */ + uint64_t descriptors_size; + + /* 112: The rollback index which can be used to prevent rollback to + * older versions. + */ + uint64_t rollback_index; + + /* 120: Flags from the AvbVBMetaImageFlags enumeration. This must be + * set to zero if the vbmeta image is not a top-level image. + */ + uint32_t flags; + + /* 124: Reserved to ensure |release_string| start on a 16-byte + * boundary. Must be set to zeroes. + */ + uint8_t reserved0[4]; + + /* 128: The release string from avbtool, e.g. "avbtool 1.0.0" or + * "avbtool 1.0.0 xyz_board Git-234abde89". Is guaranteed to be NUL + * terminated. Applications must not make assumptions about how this + * string is formatted. + */ + uint8_t release_string[AVB_RELEASE_STRING_SIZE]; + + /* 176: Padding to ensure struct is size AVB_VBMETA_IMAGE_HEADER_SIZE + * bytes. This must be set to zeroes. + */ + uint8_t reserved[80]; +} AVB_ATTR_PACKED AvbVBMetaImageHeader; + +/* Copies |src| to |dest|, byte-swapping fields in the process. + * + * Make sure you've verified |src| using avb_vbmeta_image_verify() + * before accessing the data and/or using this function. + */ +void avb_vbmeta_image_header_to_host_byte_order(const AvbVBMetaImageHeader* src, + AvbVBMetaImageHeader* dest); + +/* Return codes used in avb_vbmeta_image_verify(). + * + * AVB_VBMETA_VERIFY_RESULT_OK is returned if the vbmeta image header + * is valid, the hash is correct and the signature is correct. Keep in + * mind that you still need to check that you know the public key used + * to sign the image, see avb_vbmeta_image_verify() for details. + * + * AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED is returned if the vbmeta + * image header is valid but there is no signature or hash. + * + * AVB_VBMETA_VERIFY_RESULT_INVALID_VBMETA_HEADER is returned if the + * header of the vbmeta image is invalid, for example, invalid magic + * or inconsistent data. + * + * AVB_VBMETA_VERIFY_RESULT_UNSUPPORTED_VERSION is returned if a) the + * vbmeta image requires a minimum version of libavb which exceeds the + * version of libavb used; or b) the vbmeta image major version + * differs from the major version of libavb in use. + * + * AVB_VBMETA_VERIFY_RESULT_HASH_MISMATCH is returned if the hash + * stored in the "Authentication data" block does not match the + * calculated hash. + * + * AVB_VBMETA_VERIFY_RESULT_SIGNATURE_MISMATCH is returned if the + * signature stored in the "Authentication data" block is invalid or + * doesn't match the public key stored in the vbmeta image. + */ +typedef enum { + AVB_VBMETA_VERIFY_RESULT_OK, + AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED, + AVB_VBMETA_VERIFY_RESULT_INVALID_VBMETA_HEADER, + AVB_VBMETA_VERIFY_RESULT_UNSUPPORTED_VERSION, + AVB_VBMETA_VERIFY_RESULT_HASH_MISMATCH, + AVB_VBMETA_VERIFY_RESULT_SIGNATURE_MISMATCH, +} AvbVBMetaVerifyResult; + +/* Get a textual representation of |result|. */ +const char* avb_vbmeta_verify_result_to_string(AvbVBMetaVerifyResult result); + +/* Checks that vbmeta image at |data| of size |length| is a valid + * vbmeta image. The complete contents of the vbmeta image must be + * passed in. It's fine if |length| is bigger than the actual image, + * typically callers of this function will load the entire contents of + * the 'vbmeta_a' or 'vbmeta_b' partition and pass in its length (for + * example, 1 MiB). + * + * See the |AvbVBMetaImageHeader| struct for information about the + * three blocks (header, authentication, auxiliary) that make up a + * vbmeta image. + * + * If the function returns |AVB_VBMETA_VERIFY_RESULT_OK| and + * |out_public_key_data| is non-NULL, it will be set to point inside + * |data| for where the serialized public key data is stored and + * |out_public_key_length|, if non-NULL, will be set to the length of + * the public key data. If there is no public key in the metadata then + * |out_public_key_data| is set to NULL. + * + * See the |AvbVBMetaVerifyResult| enum for possible return values. + * + * VERY IMPORTANT: + * + * 1. Even if |AVB_VBMETA_VERIFY_RESULT_OK| is returned, you still + * need to check that the public key embedded in the image + * matches a known key! You can use 'avbtool extract_public_key' + * to extract the key (at build time, then store it along your + * code) and compare it to what is returned in + * |out_public_key_data|. + * + * 2. You need to check the |rollback_index| field against a stored + * value in NVRAM and reject the vbmeta image if the value in + * NVRAM is bigger than |rollback_index|. You must also update + * the value stored in NVRAM to the smallest value of + * |rollback_index| field from boot images in all bootable and + * authentic slots marked as GOOD. + * + * This is a low-level function to only verify the vbmeta data - you + * are likely looking for avb_slot_verify() instead for verifying + * integrity data for a whole set of partitions. + */ +AvbVBMetaVerifyResult avb_vbmeta_image_verify( + const uint8_t* data, + size_t length, + const uint8_t** out_public_key_data, + size_t* out_public_key_length) AVB_ATTR_WARN_UNUSED_RESULT; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_VBMETA_IMAGE_H_ */ diff --git a/lib/avb/libavb/avb_version.c b/lib/avb/libavb/avb_version.c new file mode 100644 index 00000000000..31f5fa6bf18 --- /dev/null +++ b/lib/avb/libavb/avb_version.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_version.h" + +#define AVB_QUOTE(str) #str +#define AVB_EXPAND_AND_QUOTE(str) AVB_QUOTE(str) + +/* Keep in sync with get_release_string() in avbtool. */ +const char* avb_version_string(void) { + return AVB_EXPAND_AND_QUOTE(AVB_VERSION_MAJOR) "." AVB_EXPAND_AND_QUOTE( + AVB_VERSION_MINOR) "." AVB_EXPAND_AND_QUOTE(AVB_VERSION_SUB); +} diff --git a/lib/avb/libavb/avb_version.h b/lib/avb/libavb/avb_version.h new file mode 100644 index 00000000000..ce4313604e0 --- /dev/null +++ b/lib/avb/libavb/avb_version.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION) +#error "Never include this file directly, include libavb.h instead." +#endif + +#ifndef AVB_VERSION_H_ +#define AVB_VERSION_H_ + +#include "avb_sysdeps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* The version number of AVB - keep in sync with avbtool. */ +#define AVB_VERSION_MAJOR 1 +#define AVB_VERSION_MINOR 1 +#define AVB_VERSION_SUB 0 + +/* Returns a NUL-terminated string for the libavb version in use. The + * returned string usually looks like "%d.%d.%d". Applications must + * not make assumptions about the content of this string. + * + * Boot loaders should display this string in debug/diagnostics output + * to aid with debugging. + * + * This is similar to the string put in the |release_string| string + * field in the VBMeta struct by avbtool. + */ +const char* avb_version_string(void); + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_VERSION_H_ */ diff --git a/lib/avb/libavb/libavb.h b/lib/avb/libavb/libavb.h new file mode 100644 index 00000000000..d5115846533 --- /dev/null +++ b/lib/avb/libavb/libavb.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef LIBAVB_H_ +#define LIBAVB_H_ + +/* The AVB_INSIDE_LIBAVB_H preprocessor symbol is used to enforce + * library users to include only this file. All public interfaces, and + * only public interfaces, must be included here. + */ + +#define AVB_INSIDE_LIBAVB_H +#include "avb_chain_partition_descriptor.h" +#include "avb_crypto.h" +#include "avb_descriptor.h" +#include "avb_footer.h" +#include "avb_hash_descriptor.h" +#include "avb_hashtree_descriptor.h" +#include "avb_kernel_cmdline_descriptor.h" +#include "avb_ops.h" +#include "avb_property_descriptor.h" +#include "avb_slot_verify.h" +#include "avb_sysdeps.h" +#include "avb_util.h" +#include "avb_vbmeta_image.h" +#include "avb_version.h" +#undef AVB_INSIDE_LIBAVB_H + +#endif /* LIBAVB_H_ */ diff --git a/lib/avb/libavb_ab/Makefile b/lib/avb/libavb_ab/Makefile new file mode 100644 index 00000000000..f22d0ed83f8 --- /dev/null +++ b/lib/avb/libavb_ab/Makefile @@ -0,0 +1,2 @@ +ccflags-y += -DAVB_COMPILATION +obj-y += avb_ab_flow.o diff --git a/lib/avb/libavb_ab/avb_ab_flow.c b/lib/avb/libavb_ab/avb_ab_flow.c new file mode 100644 index 00000000000..6097988b198 --- /dev/null +++ b/lib/avb/libavb_ab/avb_ab_flow.c @@ -0,0 +1,540 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_ab_flow.h" + +bool avb_ab_data_verify_and_byteswap(const AvbABData* src, AvbABData* dest) { + /* Ensure magic is correct. */ + if (avb_safe_memcmp(src->magic, AVB_AB_MAGIC, AVB_AB_MAGIC_LEN) != 0) { + avb_error("Magic is incorrect.\n"); + return false; + } + + avb_memcpy(dest, src, sizeof(AvbABData)); + dest->crc32 = avb_be32toh(dest->crc32); + + /* Ensure we don't attempt to access any fields if the major version + * is not supported. + */ + if (dest->version_major > AVB_AB_MAJOR_VERSION) { + avb_error("No support for given major version.\n"); + return false; + } + + /* Bail if CRC32 doesn't match. */ + if (dest->crc32 != + avb_crc32((const uint8_t*)dest, sizeof(AvbABData) - sizeof(uint32_t))) { + avb_error("CRC32 does not match.\n"); + return false; + } + + return true; +} + +void avb_ab_data_update_crc_and_byteswap(const AvbABData* src, + AvbABData* dest) { + avb_memcpy(dest, src, sizeof(AvbABData)); + dest->crc32 = avb_htobe32( + avb_crc32((const uint8_t*)dest, sizeof(AvbABData) - sizeof(uint32_t))); +} + +void avb_ab_data_init(AvbABData* data) { + avb_memset(data, '\0', sizeof(AvbABData)); + avb_memcpy(data->magic, AVB_AB_MAGIC, AVB_AB_MAGIC_LEN); + data->version_major = AVB_AB_MAJOR_VERSION; + data->version_minor = AVB_AB_MINOR_VERSION; + data->slots[0].priority = AVB_AB_MAX_PRIORITY; + data->slots[0].tries_remaining = AVB_AB_MAX_TRIES_REMAINING; + data->slots[0].successful_boot = 0; +#ifdef CONFIG_DUAL_BOOTLOADER + data->slots[0].bootloader_verified = 0; +#endif + data->slots[1].priority = AVB_AB_MAX_PRIORITY - 1; + data->slots[1].tries_remaining = AVB_AB_MAX_TRIES_REMAINING; + data->slots[1].successful_boot = 0; +#ifdef CONFIG_DUAL_BOOTLOADER + data->slots[1].bootloader_verified = 0; +#endif +} + +/* The AvbABData struct is stored 2048 bytes into the 'misc' partition + * following the 'struct bootloader_message' field. The struct is + * compatible with the guidelines in bootable/recovery/bootloader.h - + * e.g. it is stored in the |slot_suffix| field, starts with a + * NUL-byte, and is 32 bytes long. + */ +#define AB_METADATA_MISC_PARTITION_OFFSET 2048 + +AvbIOResult avb_ab_data_read(AvbABOps* ab_ops, AvbABData* data) { + AvbOps* ops = ab_ops->ops; + AvbABData serialized; + AvbIOResult io_ret; + size_t num_bytes_read; + + io_ret = ops->read_from_partition(ops, + "misc", + AB_METADATA_MISC_PARTITION_OFFSET, + sizeof(AvbABData), + &serialized, + &num_bytes_read); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + return AVB_IO_RESULT_ERROR_OOM; + } else if (io_ret != AVB_IO_RESULT_OK || + num_bytes_read != sizeof(AvbABData)) { + avb_error("Error reading A/B metadata.\n"); + return AVB_IO_RESULT_ERROR_IO; + } + + if (!avb_ab_data_verify_and_byteswap(&serialized, data)) { + avb_error( + "Error validating A/B metadata from disk. " + "Resetting and writing new A/B metadata to disk.\n"); + avb_ab_data_init(data); + return avb_ab_data_write(ab_ops, data); + } + + return AVB_IO_RESULT_OK; +} + +AvbIOResult avb_ab_data_write(AvbABOps* ab_ops, const AvbABData* data) { + AvbOps* ops = ab_ops->ops; + AvbABData serialized; + AvbIOResult io_ret; + + avb_ab_data_update_crc_and_byteswap(data, &serialized); + io_ret = ops->write_to_partition(ops, + "misc", + AB_METADATA_MISC_PARTITION_OFFSET, + sizeof(AvbABData), + &serialized); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + return AVB_IO_RESULT_ERROR_OOM; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_error("Error writing A/B metadata.\n"); + return AVB_IO_RESULT_ERROR_IO; + } + return AVB_IO_RESULT_OK; +} + +static bool slot_is_bootable(AvbABSlotData* slot) { + return slot->priority > 0 && + (slot->successful_boot || (slot->tries_remaining > 0)); +} + +static void slot_set_unbootable(AvbABSlotData* slot) { + slot->priority = 0; + slot->tries_remaining = 0; + slot->successful_boot = 0; +} + +/* Ensure all unbootable and/or illegal states are marked as the + * canonical 'unbootable' state, e.g. priority=0, tries_remaining=0, + * and successful_boot=0. + */ +static void slot_normalize(AvbABSlotData* slot) { + if (slot->priority > 0) { + if (slot->tries_remaining == 0 && !slot->successful_boot) { + /* We've exhausted all tries -> unbootable. */ + slot_set_unbootable(slot); + } + if (slot->tries_remaining > 0 && slot->successful_boot) { + /* Illegal state - avb_ab_mark_slot_successful() will clear + * tries_remaining when setting successful_boot. + */ + slot_set_unbootable(slot); + } + } else { + slot_set_unbootable(slot); + } +} + +static const char* slot_suffixes[2] = {"_a", "_b"}; + +/* Helper function to load metadata - returns AVB_IO_RESULT_OK on + * success, error code otherwise. + */ +static AvbIOResult load_metadata(AvbABOps* ab_ops, + AvbABData* ab_data, + AvbABData* ab_data_orig) { + AvbIOResult io_ret; + + io_ret = ab_ops->read_ab_metadata(ab_ops, ab_data); + if (io_ret != AVB_IO_RESULT_OK) { + avb_error("I/O error while loading A/B metadata.\n"); + return io_ret; + } + *ab_data_orig = *ab_data; + + /* Ensure data is normalized, e.g. illegal states will be marked as + * unbootable and all unbootable states are represented with + * (priority=0, tries_remaining=0, successful_boot=0). + */ + slot_normalize(&ab_data->slots[0]); + slot_normalize(&ab_data->slots[1]); + return AVB_IO_RESULT_OK; +} + +/* Writes A/B metadata to disk only if it has changed - returns + * AVB_IO_RESULT_OK on success, error code otherwise. + */ +static AvbIOResult save_metadata_if_changed(AvbABOps* ab_ops, + AvbABData* ab_data, + AvbABData* ab_data_orig) { + if (avb_safe_memcmp(ab_data, ab_data_orig, sizeof(AvbABData)) != 0) { + avb_debug("Writing A/B metadata to disk.\n"); + return ab_ops->write_ab_metadata(ab_ops, ab_data); + } + return AVB_IO_RESULT_OK; +} + +AvbABFlowResult avb_ab_flow(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data) { + AvbOps* ops = ab_ops->ops; + AvbSlotVerifyData* slot_data[2] = {NULL, NULL}; + AvbSlotVerifyData* data = NULL; + AvbABFlowResult ret; + AvbABData ab_data, ab_data_orig; + size_t slot_index_to_boot, n; + AvbIOResult io_ret; + bool saw_and_allowed_verification_error = false; + + io_ret = load_metadata(ab_ops, &ab_data, &ab_data_orig); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + + /* Validate all bootable slots. */ + for (n = 0; n < 2; n++) { + if (slot_is_bootable(&ab_data.slots[n])) { + AvbSlotVerifyResult verify_result; + bool set_slot_unbootable = false; + + verify_result = avb_slot_verify(ops, + requested_partitions, + slot_suffixes[n], + flags, + hashtree_error_mode, + &slot_data[n]); + switch (verify_result) { + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + + case AVB_SLOT_VERIFY_RESULT_OK: + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + /* Even with AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR + * these mean game over. + */ + set_slot_unbootable = true; + break; + + /* explicit fallthrough. */ + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + if (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR) { + /* Do nothing since we allow this. */ + avb_debugv("Allowing slot ", + slot_suffixes[n], + " which verified " + "with result ", + avb_slot_verify_result_to_string(verify_result), + " because " + "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR " + "is set.\n", + NULL); + saw_and_allowed_verification_error = true; + } else { + set_slot_unbootable = true; + } + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + ret = AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT; + goto out; + /* Do not add a 'default:' case here because of -Wswitch. */ + } + + if (set_slot_unbootable) { + avb_errorv("Error verifying slot ", + slot_suffixes[n], + " with result ", + avb_slot_verify_result_to_string(verify_result), + " - setting unbootable.\n", + NULL); + slot_set_unbootable(&ab_data.slots[n]); + } + } + } + + if (slot_is_bootable(&ab_data.slots[0]) && + slot_is_bootable(&ab_data.slots[1])) { + if (ab_data.slots[1].priority > ab_data.slots[0].priority) { + slot_index_to_boot = 1; + } else { + slot_index_to_boot = 0; + } + } else if (slot_is_bootable(&ab_data.slots[0])) { + slot_index_to_boot = 0; + } else if (slot_is_bootable(&ab_data.slots[1])) { + slot_index_to_boot = 1; + } else { + /* No bootable slots! */ + avb_error("No bootable slots found.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS; + goto out; + } + + /* Update stored rollback index such that the stored rollback index + * is the largest value supporting all currently bootable slots. Do + * this for every rollback index location. + */ + for (n = 0; n < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; n++) { + uint64_t rollback_index_value = 0; + + if (slot_data[0] != NULL && slot_data[1] != NULL) { + uint64_t a_rollback_index = slot_data[0]->rollback_indexes[n]; + uint64_t b_rollback_index = slot_data[1]->rollback_indexes[n]; + rollback_index_value = + (a_rollback_index < b_rollback_index ? a_rollback_index + : b_rollback_index); + } else if (slot_data[0] != NULL) { + rollback_index_value = slot_data[0]->rollback_indexes[n]; + } else if (slot_data[1] != NULL) { + rollback_index_value = slot_data[1]->rollback_indexes[n]; + } + + if (rollback_index_value != 0) { + uint64_t current_rollback_index_value; + io_ret = ops->read_rollback_index(ops, n, ¤t_rollback_index_value); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_error("Error getting rollback index for slot.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + if (current_rollback_index_value != rollback_index_value) { + io_ret = ops->write_rollback_index(ops, n, rollback_index_value); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + avb_error("Error setting stored rollback index.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + } + } + } + + /* Finally, select this slot. */ + avb_assert(slot_data[slot_index_to_boot] != NULL); + data = slot_data[slot_index_to_boot]; + slot_data[slot_index_to_boot] = NULL; + if (saw_and_allowed_verification_error) { + avb_assert(flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR); + ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR; + } else { + ret = AVB_AB_FLOW_RESULT_OK; + } + + /* ... and decrement tries remaining, if applicable. */ + if (!ab_data.slots[slot_index_to_boot].successful_boot && + ab_data.slots[slot_index_to_boot].tries_remaining > 0) { + ab_data.slots[slot_index_to_boot].tries_remaining -= 1; + } + +out: + io_ret = save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig); + if (io_ret != AVB_IO_RESULT_OK) { + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + } else { + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + } + if (data != NULL) { + avb_slot_verify_data_free(data); + data = NULL; + } + } + + for (n = 0; n < 2; n++) { + if (slot_data[n] != NULL) { + avb_slot_verify_data_free(slot_data[n]); + } + } + + if (out_data != NULL) { + *out_data = data; + } else { + if (data != NULL) { + avb_slot_verify_data_free(data); + } + } + + return ret; +} + +AvbIOResult avb_ab_mark_slot_active(AvbABOps* ab_ops, + unsigned int slot_number) { + AvbABData ab_data, ab_data_orig; + unsigned int other_slot_number; + AvbIOResult ret; + + avb_assert(slot_number < 2); + + ret = load_metadata(ab_ops, &ab_data, &ab_data_orig); + if (ret != AVB_IO_RESULT_OK) { + goto out; + } + + /* Make requested slot top priority, unsuccessful, and with max tries. */ + ab_data.slots[slot_number].priority = AVB_AB_MAX_PRIORITY; + ab_data.slots[slot_number].tries_remaining = AVB_AB_MAX_TRIES_REMAINING; + ab_data.slots[slot_number].successful_boot = 0; +#ifdef CONFIG_DUAL_BOOTLOADER + ab_data.slots[slot_number].bootloader_verified = 0; +#endif + + /* Ensure other slot doesn't have as high a priority. */ + other_slot_number = 1 - slot_number; + if (ab_data.slots[other_slot_number].priority == AVB_AB_MAX_PRIORITY) { + ab_data.slots[other_slot_number].priority = AVB_AB_MAX_PRIORITY - 1; + } + + ret = AVB_IO_RESULT_OK; + +out: + if (ret == AVB_IO_RESULT_OK) { + ret = save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig); + } + return ret; +} + +AvbIOResult avb_ab_mark_slot_unbootable(AvbABOps* ab_ops, + unsigned int slot_number) { + AvbABData ab_data, ab_data_orig; + AvbIOResult ret; + + avb_assert(slot_number < 2); + + ret = load_metadata(ab_ops, &ab_data, &ab_data_orig); + if (ret != AVB_IO_RESULT_OK) { + goto out; + } + + slot_set_unbootable(&ab_data.slots[slot_number]); + + ret = AVB_IO_RESULT_OK; + +out: + if (ret == AVB_IO_RESULT_OK) { + ret = save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig); + } + return ret; +} + +AvbIOResult avb_ab_mark_slot_successful(AvbABOps* ab_ops, + unsigned int slot_number) { + AvbABData ab_data, ab_data_orig; + AvbIOResult ret; + + avb_assert(slot_number < 2); + + ret = load_metadata(ab_ops, &ab_data, &ab_data_orig); + if (ret != AVB_IO_RESULT_OK) { + goto out; + } + + if (!slot_is_bootable(&ab_data.slots[slot_number])) { + avb_error("Cannot mark unbootable slot as successful.\n"); + ret = AVB_IO_RESULT_OK; + goto out; + } + + ab_data.slots[slot_number].tries_remaining = 0; + ab_data.slots[slot_number].successful_boot = 1; + + ret = AVB_IO_RESULT_OK; + +out: + if (ret == AVB_IO_RESULT_OK) { + ret = save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig); + } + return ret; +} + +const char* avb_ab_flow_result_to_string(AvbABFlowResult result) { + const char* ret = NULL; + + switch (result) { + case AVB_AB_FLOW_RESULT_OK: + ret = "OK"; + break; + + case AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR: + ret = "OK_WITH_VERIFICATION_ERROR"; + break; + + case AVB_AB_FLOW_RESULT_ERROR_OOM: + ret = "ERROR_OOM"; + break; + + case AVB_AB_FLOW_RESULT_ERROR_IO: + ret = "ERROR_IO"; + break; + + case AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS: + ret = "ERROR_NO_BOOTABLE_SLOTS"; + break; + + case AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT: + ret = "ERROR_INVALID_ARGUMENT"; + break; + /* Do not add a 'default:' case here because of -Wswitch. */ + } + + if (ret == NULL) { + avb_error("Unknown AvbABFlowResult value.\n"); + ret = "(unknown)"; + } + + return ret; +} diff --git a/lib/avb/libavb_ab/avb_ab_flow.h b/lib/avb/libavb_ab/avb_ab_flow.h new file mode 100644 index 00000000000..3757ba26ac2 --- /dev/null +++ b/lib/avb/libavb_ab/avb_ab_flow.h @@ -0,0 +1,261 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_AB_H) && !defined(AVB_COMPILATION) +#error \ + "Never include this file directly, include libavb_ab/libavb_ab.h instead." +#endif + +#ifndef AVB_AB_FLOW_H_ +#define AVB_AB_FLOW_H_ + +#include "avb_ab_ops.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Magic for the A/B struct when serialized. */ +#define AVB_AB_MAGIC "\0AB0" +#define AVB_AB_MAGIC_LEN 4 + +/* Versioning for the on-disk A/B metadata - keep in sync with avbtool. */ +#define AVB_AB_MAJOR_VERSION 1 +#define AVB_AB_MINOR_VERSION 0 + +/* Size of AvbABData struct. */ +#define AVB_AB_DATA_SIZE 32 + +/* Maximum values for slot data */ +#define AVB_AB_MAX_PRIORITY 15 +#define AVB_AB_MAX_TRIES_REMAINING 7 + +/* Struct used for recording per-slot metadata. + * + * When serialized, data is stored in network byte-order. + */ +typedef struct AvbABSlotData { + /* Slot priority. Valid values range from 0 to AVB_AB_MAX_PRIORITY, + * both inclusive with 1 being the lowest and AVB_AB_MAX_PRIORITY + * being the highest. The special value 0 is used to indicate the + * slot is unbootable. + */ + uint8_t priority; + + /* Number of times left attempting to boot this slot ranging from 0 + * to AVB_AB_MAX_TRIES_REMAINING. + */ + uint8_t tries_remaining; + + /* Non-zero if this slot has booted successfully, 0 otherwise. */ + uint8_t successful_boot; + + /* Reserved for future use. */ + uint8_t bootloader_verified; +} AVB_ATTR_PACKED AvbABSlotData; + +/* Struct used for recording A/B metadata. + * + * When serialized, data is stored in network byte-order. + */ +typedef struct AvbABData { + /* Magic number used for identification - see AVB_AB_MAGIC. */ + uint8_t magic[AVB_AB_MAGIC_LEN]; + + /* Version of on-disk struct - see AVB_AB_{MAJOR,MINOR}_VERSION. */ + uint8_t version_major; + uint8_t version_minor; + + /* Padding to ensure |slots| field start eight bytes in. */ + uint8_t reserved1[2]; + + /* Per-slot metadata. */ + AvbABSlotData slots[2]; + + /* Reserved for future use. */ + uint8_t reserved2[12]; + + /* CRC32 of all 28 bytes preceding this field. */ + uint32_t crc32; +} AVB_ATTR_PACKED AvbABData; + +/* Copies |src| to |dest|, byte-swapping fields in the + * process. Returns false if the data is invalid (e.g. wrong magic, + * wrong CRC32 etc.), true otherwise. + */ +bool avb_ab_data_verify_and_byteswap(const AvbABData* src, AvbABData* dest); + +/* Copies |src| to |dest|, byte-swapping fields in the process. Also + * updates the |crc32| field in |dest|. + */ +void avb_ab_data_update_crc_and_byteswap(const AvbABData* src, AvbABData* dest); + +/* Initializes |data| such that it has two slots and both slots have + * maximum tries remaining. The CRC is not set. + */ +void avb_ab_data_init(AvbABData* data); + +/* Reads A/B metadata from the 'misc' partition using |ops|. Returned + * data is properly byteswapped. Returns AVB_IO_RESULT_OK on + * success, error code otherwise. + * + * If the data read from disk is invalid (e.g. wrong magic or CRC + * checksum failure), the metadata will be reset using + * avb_ab_data_init() and then written to disk. + */ +AvbIOResult avb_ab_data_read(AvbABOps* ab_ops, AvbABData* data); + +/* Writes A/B metadata to the 'misc' partition using |ops|. This will + * byteswap and update the CRC as needed. Returns AVB_IO_RESULT_OK on + * success, error code otherwise. + */ +AvbIOResult avb_ab_data_write(AvbABOps* ab_ops, const AvbABData* data); + +/* Return codes used in avb_ab_flow(), see that function for + * documentation of each value. + */ +typedef enum { + AVB_AB_FLOW_RESULT_OK, + AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR, + AVB_AB_FLOW_RESULT_ERROR_OOM, + AVB_AB_FLOW_RESULT_ERROR_IO, + AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS, + AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT +} AvbABFlowResult; + +/* Get a textual representation of |result|. */ +const char* avb_ab_flow_result_to_string(AvbABFlowResult result); + +/* High-level function to select a slot to boot. The following + * algorithm is used: + * + * 1. A/B metadata is loaded and validated using the + * read_ab_metadata() operation. Typically this means it's read from + * the 'misc' partition and if it's invalid then it's reset using + * avb_ab_data_init() and this reset metadata is returned. + * + * 2. All bootable slots listed in the A/B metadata are verified using + * avb_slot_verify(). If a slot is invalid or if it fails verification + * (and AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR is not set, see + * below), it will be marked as unbootable in the A/B metadata and the + * metadata will be saved to disk before returning. + * + * 3. If there are no bootable slots, the value + * AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS is returned. + * + * 4. For each bootable slot, the Stored Rollback Indexes are updated + * such that for each rollback index location, the Stored Rollback + * Index is the largest number smaller than or equal to the Rollback + * Index of each slot. + * + * 5. The bootable slot with the highest priority is selected and + * returned in |out_data|. If this slot is already marked as + * successful, the A/B metadata is not modified. However, if the slot + * is not marked as bootable its |tries_remaining| count is + * decremented and the A/B metadata is saved to disk before returning. + * In either case the value AVB_AB_FLOW_RESULT_OK is returning. + * + * The partitions to load is given in |requested_partitions| as a + * NULL-terminated array of NUL-terminated strings. Typically the + * |requested_partitions| array only contains a single item for the + * boot partition, 'boot'. + * + * If the device is unlocked (and _only_ if it's unlocked), the + * AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR flag should be set + * in the |flags| parameter. This will allow considering slots as + * verified even when avb_slot_verify() returns + * AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED, + * AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION, or + * AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX for the slot in + * question. + * + * Note that neither androidboot.slot_suffix nor androidboot.slot are + * set in the |cmdline| field in |AvbSlotVerifyData| - you will have + * to pass these yourself. + * + * If a slot was selected and it verified then AVB_AB_FLOW_RESULT_OK + * is returned. + * + * If a slot was selected but it didn't verify then + * AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR is returned. This can + * only happen when the AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR + * flag is set. + * + * If an I/O operation - such as loading/saving metadata or checking + * rollback indexes - fail, the value AVB_AB_FLOW_RESULT_ERROR_IO is + * returned. + * + * If memory allocation fails, AVB_AB_FLOW_RESULT_ERROR_OOM is + * returned. + * + * If invalid arguments are passed, + * AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT is returned. For example + * this can happen if using AVB_HASHTREE_ERROR_MODE_LOGGING without + * AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR. + * + * Reasonable behavior for handling AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS + * is to initiate device repair (which is device-dependent). + */ +AvbABFlowResult avb_ab_flow(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data); + +/* Marks the slot with the given slot number as active. Returns + * AVB_IO_RESULT_OK on success, error code otherwise. + * + * This function is typically used by the OS updater when completing + * an update. It can also used by the firmware for implementing the + * "set_active" command. + */ +AvbIOResult avb_ab_mark_slot_active(AvbABOps* ab_ops, unsigned int slot_number); + +/* Marks the slot with the given slot number as unbootable. Returns + * AVB_IO_RESULT_OK on success, error code otherwise. + * + * This function is typically used by the OS updater before writing to + * a slot. + */ +AvbIOResult avb_ab_mark_slot_unbootable(AvbABOps* ab_ops, + unsigned int slot_number); + +/* Marks the slot with the given slot number as having booted + * successfully. Returns AVB_IO_RESULT_OK on success, error code + * otherwise. + * + * Calling this on an unbootable slot is an error - AVB_IO_RESULT_OK + * will be returned yet the function will have no side-effects. + * + * This function is typically used by the OS updater after having + * confirmed that the slot works as intended. + */ +AvbIOResult avb_ab_mark_slot_successful(AvbABOps* ab_ops, + unsigned int slot_number); + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_AB_FLOW_H_ */ diff --git a/lib/avb/libavb_ab/avb_ab_ops.h b/lib/avb/libavb_ab/avb_ab_ops.h new file mode 100644 index 00000000000..8d8fde7aa94 --- /dev/null +++ b/lib/avb/libavb_ab/avb_ab_ops.h @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_AB_H) && !defined(AVB_COMPILATION) +#error \ + "Never include this file directly, include libavb_ab/libavb_ab.h instead." +#endif + +#ifndef AVB_AB_OPS_H_ +#define AVB_AB_OPS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct AvbABOps; +typedef struct AvbABOps AvbABOps; + +struct AvbABData; + +/* High-level operations/functions/methods for A/B that are platform + * dependent. + */ +struct AvbABOps { + /* Operations from libavb. */ + AvbOps* ops; + + /* Reads A/B metadata from persistent storage. Returned data is + * properly byteswapped. Returns AVB_IO_RESULT_OK on success, error + * code otherwise. + * + * If the data read is invalid (e.g. wrong magic or CRC checksum + * failure), the metadata shoule be reset using avb_ab_data_init() + * and then written to persistent storage. + * + * Implementations will typically want to use avb_ab_data_read() + * here to use the 'misc' partition for persistent storage. + */ + AvbIOResult (*read_ab_metadata)(AvbABOps* ab_ops, struct AvbABData* data); + + /* Writes A/B metadata to persistent storage. This will byteswap and + * update the CRC as needed. Returns AVB_IO_RESULT_OK on success, + * error code otherwise. + * + * Implementations will typically want to use avb_ab_data_write() + * here to use the 'misc' partition for persistent storage. + */ + AvbIOResult (*write_ab_metadata)(AvbABOps* ab_ops, + const struct AvbABData* data); +}; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_AB_OPS_H_ */ diff --git a/lib/avb/libavb_ab/libavb_ab.h b/lib/avb/libavb_ab/libavb_ab.h new file mode 100644 index 00000000000..654ff5e7719 --- /dev/null +++ b/lib/avb/libavb_ab/libavb_ab.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef LIBAVB_AB_H_ +#define LIBAVB_AB_H_ + +#include + +/* The libavb_ab/ and boot_control/ code has been marked for some time + * as experimental in anticipation of being removed in the future. It + * is now deprecated and to continue using it you must define + * AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED. It will be removed Jun + * 1 2018. + */ +#ifndef AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED +#error \ + "You must define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED to use this library." +#endif + +/* The AVB_INSIDE_LIBAVB_AB_H preprocessor symbol is used to enforce + * library users to include only this file. All public interfaces, and + * only public interfaces, must be included here. + */ + +#define AVB_INSIDE_LIBAVB_AB_H +#include "avb_ab_flow.h" +#include "avb_ab_ops.h" +#undef AVB_INSIDE_LIBAVB_AB_H + +#endif /* LIBAVB_AB_H_ */ diff --git a/lib/avb/libavb_atx/Makefile b/lib/avb/libavb_atx/Makefile new file mode 100644 index 00000000000..bdd7bccbeb0 --- /dev/null +++ b/lib/avb/libavb_atx/Makefile @@ -0,0 +1,2 @@ +ccflags-y += -DAVB_COMPILATION +obj-y += avb_atx_validate.o diff --git a/lib/avb/libavb_atx/avb_atx_ops.h b/lib/avb/libavb_atx/avb_atx_ops.h new file mode 100644 index 00000000000..53c898d623d --- /dev/null +++ b/lib/avb/libavb_atx/avb_atx_ops.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_ATX_H) && !defined(AVB_COMPILATION) +#error \ + "Never include this file directly, include libavb_atx/libavb_atx.h instead." +#endif + +#ifndef AVB_ATX_OPS_H_ +#define AVB_ATX_OPS_H_ + +#include + +#include "avb_atx_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct AvbAtxOps; +typedef struct AvbAtxOps AvbAtxOps; + +/* An extension to AvbOps required by avb_atx_validate_vbmeta_public_key(). */ +struct AvbAtxOps { + /* Operations from libavb. */ + AvbOps* ops; + + /* Reads permanent |attributes| data. There are no restrictions on where this + * data is stored. On success, returns AVB_IO_RESULT_OK and populates + * |attributes|. + */ + AvbIOResult (*read_permanent_attributes)( + AvbAtxOps* atx_ops, AvbAtxPermanentAttributes* attributes); + + /* Reads a |hash| of permanent attributes. This hash MUST be retrieved from a + * permanently read-only location (e.g. fuses) when a device is LOCKED. On + * success, returned AVB_IO_RESULT_OK and populates |hash|. + */ + AvbIOResult (*read_permanent_attributes_hash)( + AvbAtxOps* atx_ops, uint8_t hash[AVB_SHA256_DIGEST_SIZE]); + + /* Provides the key version of a key used during verification. This may be + * useful for managing the minimum key version. + */ + void (*set_key_version)(AvbAtxOps* atx_ops, + size_t rollback_index_location, + uint64_t key_version); + + /* Generates |num_bytes| random bytes and stores them in |output|, + * which must point to a buffer large enough to store the bytes. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ + AvbIOResult (*get_random)(AvbAtxOps* atx_ops, + size_t num_bytes, + uint8_t* output); +}; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_ATX_OPS_H_ */ diff --git a/lib/avb/libavb_atx/avb_atx_types.h b/lib/avb/libavb_atx/avb_atx_types.h new file mode 100644 index 00000000000..e78bbfa78c2 --- /dev/null +++ b/lib/avb/libavb_atx/avb_atx_types.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_ATX_H) && !defined(AVB_COMPILATION) +#error \ + "Never include this file directly, include libavb_atx/libavb_atx.h instead." +#endif + +#ifndef AVB_ATX_TYPES_H_ +#define AVB_ATX_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Size in bytes of an Android Things product ID. */ +#define AVB_ATX_PRODUCT_ID_SIZE 16 + +/* Size in bytes of an Android Things unlock challenge. */ +#define AVB_ATX_UNLOCK_CHALLENGE_SIZE 16 + +/* Size in bytes of a serialized public key with a 4096-bit modulus. */ +#define AVB_ATX_PUBLIC_KEY_SIZE (sizeof(AvbRSAPublicKeyHeader) + 1024) + +/* Data structure of Android Things permanent attributes. */ +typedef struct AvbAtxPermanentAttributes { + uint32_t version; + uint8_t product_root_public_key[AVB_ATX_PUBLIC_KEY_SIZE]; + uint8_t product_id[AVB_ATX_PRODUCT_ID_SIZE]; +} AVB_ATTR_PACKED AvbAtxPermanentAttributes; + +/* Data structure of signed fields in an Android Things certificate. */ +typedef struct AvbAtxCertificateSignedData { + uint32_t version; + uint8_t public_key[AVB_ATX_PUBLIC_KEY_SIZE]; + uint8_t subject[AVB_SHA256_DIGEST_SIZE]; + uint8_t usage[AVB_SHA256_DIGEST_SIZE]; + uint64_t key_version; +} AVB_ATTR_PACKED AvbAtxCertificateSignedData; + +/* Data structure of an Android Things certificate. */ +typedef struct AvbAtxCertificate { + AvbAtxCertificateSignedData signed_data; + uint8_t signature[AVB_RSA4096_NUM_BYTES]; +} AVB_ATTR_PACKED AvbAtxCertificate; + +/* Data structure of Android Things public key metadata in vbmeta. */ +typedef struct AvbAtxPublicKeyMetadata { + uint32_t version; + AvbAtxCertificate product_intermediate_key_certificate; + AvbAtxCertificate product_signing_key_certificate; +} AVB_ATTR_PACKED AvbAtxPublicKeyMetadata; + +/* Data structure of an Android Things unlock challenge. */ +typedef struct AvbAtxUnlockChallenge { + uint32_t version; + uint8_t product_id_hash[AVB_SHA256_DIGEST_SIZE]; + uint8_t challenge[AVB_ATX_UNLOCK_CHALLENGE_SIZE]; +} AVB_ATTR_PACKED AvbAtxUnlockChallenge; + +/* Data structure of an Android Things unlock credential. */ +typedef struct AvbAtxUnlockCredential { + uint32_t version; + AvbAtxCertificate product_intermediate_key_certificate; + AvbAtxCertificate product_unlock_key_certificate; + uint8_t challenge_signature[AVB_RSA4096_NUM_BYTES]; +} AVB_ATTR_PACKED AvbAtxUnlockCredential; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_ATX_TYPES_H_ */ diff --git a/lib/avb/libavb_atx/avb_atx_validate.c b/lib/avb/libavb_atx/avb_atx_validate.c new file mode 100644 index 00000000000..f3c1d968412 --- /dev/null +++ b/lib/avb/libavb_atx/avb_atx_validate.c @@ -0,0 +1,401 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_atx_validate.h" + +#include +#include +#include +#include + +/* The most recent unlock challenge generated. */ +static uint8_t last_unlock_challenge[AVB_ATX_UNLOCK_CHALLENGE_SIZE]; + +/* Computes the SHA256 |hash| of |length| bytes of |data|. */ +static void sha256(const uint8_t* data, + uint32_t length, + uint8_t hash[AVB_SHA256_DIGEST_SIZE]) { + AvbSHA256Ctx context; + avb_sha256_init(&context); + avb_sha256_update(&context, data, length); + uint8_t* tmp = avb_sha256_final(&context); + avb_memcpy(hash, tmp, AVB_SHA256_DIGEST_SIZE); +} + +/* Computes the SHA512 |hash| of |length| bytes of |data|. */ +static void sha512(const uint8_t* data, + uint32_t length, + uint8_t hash[AVB_SHA512_DIGEST_SIZE]) { + AvbSHA512Ctx context; + avb_sha512_init(&context); + avb_sha512_update(&context, data, length); + uint8_t* tmp = avb_sha512_final(&context); + avb_memcpy(hash, tmp, AVB_SHA512_DIGEST_SIZE); +} + +/* Computes the SHA256 |hash| of a NUL-terminated |str|. */ +static void sha256_str(const char* str, uint8_t hash[AVB_SHA256_DIGEST_SIZE]) { + sha256((const uint8_t*)str, avb_strlen(str), hash); +} + +/* Verifies structure and |expected_hash| of permanent |attributes|. */ +static bool verify_permanent_attributes( + const AvbAtxPermanentAttributes* attributes, + const uint8_t expected_hash[AVB_SHA256_DIGEST_SIZE]) { + uint8_t hash[AVB_SHA256_DIGEST_SIZE]; + + if (attributes->version != 1) { + avb_error("Unsupported permanent attributes version.\n"); + return false; + } + sha256((const uint8_t*)attributes, sizeof(AvbAtxPermanentAttributes), hash); + if (0 != avb_safe_memcmp(hash, expected_hash, AVB_SHA256_DIGEST_SIZE)) { + avb_error("Invalid permanent attributes.\n"); + return false; + } + return true; +} + +/* Verifies the format, key version, usage, and signature of a certificate. */ +static bool verify_certificate( + const AvbAtxCertificate* certificate, + const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE], + uint64_t minimum_key_version, + const uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE]) { + const AvbAlgorithmData* algorithm_data; + uint8_t certificate_hash[AVB_SHA512_DIGEST_SIZE]; + + if (certificate->signed_data.version != 1) { + avb_error("Unsupported certificate format.\n"); + return false; + } + algorithm_data = avb_get_algorithm_data(AVB_ALGORITHM_TYPE_SHA512_RSA4096); + sha512((const uint8_t*)&certificate->signed_data, + sizeof(AvbAtxCertificateSignedData), + certificate_hash); + if (!avb_rsa_verify(authority, + AVB_ATX_PUBLIC_KEY_SIZE, + certificate->signature, + AVB_RSA4096_NUM_BYTES, + certificate_hash, + AVB_SHA512_DIGEST_SIZE, + algorithm_data->padding, + algorithm_data->padding_len)) { + avb_error("Invalid certificate signature.\n"); + return false; + } + if (certificate->signed_data.key_version < minimum_key_version) { + avb_error("Key rollback detected.\n"); + return false; + } + if (0 != avb_safe_memcmp(certificate->signed_data.usage, + expected_usage, + AVB_SHA256_DIGEST_SIZE)) { + avb_error("Invalid certificate usage.\n"); + return false; + } + return true; +} + +/* Verifies signature and fields of a PIK certificate. */ +static bool verify_pik_certificate( + const AvbAtxCertificate* certificate, + const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE], + uint64_t minimum_version) { + uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE]; + + sha256_str("com.google.android.things.vboot.ca", expected_usage); + if (!verify_certificate( + certificate, authority, minimum_version, expected_usage)) { + avb_error("Invalid PIK certificate.\n"); + return false; + } + return true; +} + +/* Verifies signature and fields of a PSK certificate. */ +static bool verify_psk_certificate( + const AvbAtxCertificate* certificate, + const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE], + uint64_t minimum_version, + const uint8_t product_id[AVB_ATX_PRODUCT_ID_SIZE]) { + uint8_t expected_subject[AVB_SHA256_DIGEST_SIZE]; + uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE]; + + sha256_str("com.google.android.things.vboot", expected_usage); + if (!verify_certificate( + certificate, authority, minimum_version, expected_usage)) { + avb_error("Invalid PSK certificate.\n"); + return false; + } + sha256(product_id, AVB_ATX_PRODUCT_ID_SIZE, expected_subject); + if (0 != avb_safe_memcmp(certificate->signed_data.subject, + expected_subject, + AVB_SHA256_DIGEST_SIZE)) { + avb_error("PSK: Product ID mismatch.\n"); + return false; + } + return true; +} + +/* Verifies signature and fields of a PUK certificate. */ +static bool verify_puk_certificate( + const AvbAtxCertificate* certificate, + const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE], + uint64_t minimum_version, + const uint8_t product_id[AVB_ATX_PRODUCT_ID_SIZE]) { + uint8_t expected_subject[AVB_SHA256_DIGEST_SIZE]; + uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE]; + + sha256_str("com.google.android.things.vboot.unlock", expected_usage); + if (!verify_certificate( + certificate, authority, minimum_version, expected_usage)) { + avb_error("Invalid PUK certificate.\n"); + return false; + } + sha256(product_id, AVB_ATX_PRODUCT_ID_SIZE, expected_subject); + if (0 != avb_safe_memcmp(certificate->signed_data.subject, + expected_subject, + AVB_SHA256_DIGEST_SIZE)) { + avb_error("PUK: Product ID mismatch.\n"); + return false; + } + return true; +} + +AvbIOResult avb_atx_validate_vbmeta_public_key( + AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted) { + AvbIOResult result = AVB_IO_RESULT_OK; + AvbAtxPermanentAttributes permanent_attributes; + uint8_t permanent_attributes_hash[AVB_SHA256_DIGEST_SIZE]; + AvbAtxPublicKeyMetadata metadata; + uint64_t minimum_version; + + /* Be pessimistic so we can exit early without having to remember to clear. + */ + *out_is_trusted = false; + + /* Read and verify permanent attributes. */ + result = ops->atx_ops->read_permanent_attributes(ops->atx_ops, + &permanent_attributes); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read permanent attributes.\n"); + return result; + } + result = ops->atx_ops->read_permanent_attributes_hash( + ops->atx_ops, permanent_attributes_hash); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read permanent attributes hash.\n"); + return result; + } + if (!verify_permanent_attributes(&permanent_attributes, + permanent_attributes_hash)) { + return AVB_IO_RESULT_OK; + } + + /* Sanity check public key metadata. */ + if (public_key_metadata_length != sizeof(AvbAtxPublicKeyMetadata)) { + avb_error("Invalid public key metadata.\n"); + return AVB_IO_RESULT_OK; + } + avb_memcpy(&metadata, public_key_metadata, sizeof(AvbAtxPublicKeyMetadata)); + if (metadata.version != 1) { + avb_error("Unsupported public key metadata.\n"); + return AVB_IO_RESULT_OK; + } + + /* Verify the PIK certificate. */ + result = ops->read_rollback_index( + ops, AVB_ATX_PIK_VERSION_LOCATION, &minimum_version); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read PIK minimum version.\n"); + return result; + } + if (!verify_pik_certificate(&metadata.product_intermediate_key_certificate, + permanent_attributes.product_root_public_key, + minimum_version)) { + return AVB_IO_RESULT_OK; + } + + /* Verify the PSK certificate. */ + result = ops->read_rollback_index( + ops, AVB_ATX_PSK_VERSION_LOCATION, &minimum_version); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read PSK minimum version.\n"); + return result; + } + if (!verify_psk_certificate( + &metadata.product_signing_key_certificate, + metadata.product_intermediate_key_certificate.signed_data.public_key, + minimum_version, + permanent_attributes.product_id)) { + return AVB_IO_RESULT_OK; + } + + /* Verify the PSK is the same key that verified vbmeta. */ + if (public_key_length != AVB_ATX_PUBLIC_KEY_SIZE) { + avb_error("Public key length mismatch.\n"); + return AVB_IO_RESULT_OK; + } + if (0 != avb_safe_memcmp( + metadata.product_signing_key_certificate.signed_data.public_key, + public_key_data, + AVB_ATX_PUBLIC_KEY_SIZE)) { + avb_error("Public key mismatch.\n"); + return AVB_IO_RESULT_OK; + } + + /* Report the key versions used during verification. */ + ops->atx_ops->set_key_version( + ops->atx_ops, + AVB_ATX_PIK_VERSION_LOCATION, + metadata.product_intermediate_key_certificate.signed_data.key_version); + ops->atx_ops->set_key_version( + ops->atx_ops, + AVB_ATX_PSK_VERSION_LOCATION, + metadata.product_signing_key_certificate.signed_data.key_version); + + *out_is_trusted = true; + return AVB_IO_RESULT_OK; +} + +AvbIOResult avb_atx_generate_unlock_challenge( + AvbAtxOps* atx_ops, AvbAtxUnlockChallenge* out_unlock_challenge) { + AvbIOResult result = AVB_IO_RESULT_OK; + AvbAtxPermanentAttributes permanent_attributes; + + /* We need the permanent attributes to compute the product_id_hash. */ + result = atx_ops->read_permanent_attributes(atx_ops, &permanent_attributes); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read permanent attributes.\n"); + return result; + } + result = atx_ops->get_random( + atx_ops, AVB_ATX_UNLOCK_CHALLENGE_SIZE, last_unlock_challenge); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to generate random challenge.\n"); + return result; + } + out_unlock_challenge->version = 1; + sha256(permanent_attributes.product_id, + AVB_ATX_PRODUCT_ID_SIZE, + out_unlock_challenge->product_id_hash); + avb_memcpy(out_unlock_challenge->challenge, + last_unlock_challenge, + AVB_ATX_UNLOCK_CHALLENGE_SIZE); + return result; +} + +AvbIOResult avb_atx_validate_unlock_credential( + AvbAtxOps* atx_ops, + const AvbAtxUnlockCredential* unlock_credential, + bool* out_is_trusted) { + AvbIOResult result = AVB_IO_RESULT_OK; + AvbAtxPermanentAttributes permanent_attributes; + uint8_t permanent_attributes_hash[AVB_SHA256_DIGEST_SIZE]; + uint64_t minimum_version; + const AvbAlgorithmData* algorithm_data; + uint8_t challenge_hash[AVB_SHA512_DIGEST_SIZE]; + + /* Be pessimistic so we can exit early without having to remember to clear. + */ + *out_is_trusted = false; + + /* Sanity check the credential. */ + if (unlock_credential->version != 1) { + avb_error("Unsupported unlock credential format.\n"); + return AVB_IO_RESULT_OK; + } + + /* Read and verify permanent attributes. */ + result = atx_ops->read_permanent_attributes(atx_ops, &permanent_attributes); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read permanent attributes.\n"); + return result; + } + result = atx_ops->read_permanent_attributes_hash(atx_ops, + permanent_attributes_hash); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read permanent attributes hash.\n"); + return result; + } + if (!verify_permanent_attributes(&permanent_attributes, + permanent_attributes_hash)) { + return AVB_IO_RESULT_OK; + } + + /* Verify the PIK certificate. */ + result = atx_ops->ops->read_rollback_index( + atx_ops->ops, AVB_ATX_PIK_VERSION_LOCATION, &minimum_version); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read PIK minimum version.\n"); + return result; + } + if (!verify_pik_certificate( + &unlock_credential->product_intermediate_key_certificate, + permanent_attributes.product_root_public_key, + minimum_version)) { + return AVB_IO_RESULT_OK; + } + + /* Verify the PUK certificate. The minimum version is shared with the PSK. */ + result = atx_ops->ops->read_rollback_index( + atx_ops->ops, AVB_ATX_PSK_VERSION_LOCATION, &minimum_version); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read PSK minimum version.\n"); + return result; + } + if (!verify_puk_certificate( + &unlock_credential->product_unlock_key_certificate, + unlock_credential->product_intermediate_key_certificate.signed_data + .public_key, + minimum_version, + permanent_attributes.product_id)) { + return AVB_IO_RESULT_OK; + } + + /* Verify the challenge signature. */ + algorithm_data = avb_get_algorithm_data(AVB_ALGORITHM_TYPE_SHA512_RSA4096); + sha512(last_unlock_challenge, AVB_ATX_UNLOCK_CHALLENGE_SIZE, challenge_hash); + if (!avb_rsa_verify(unlock_credential->product_unlock_key_certificate + .signed_data.public_key, + AVB_ATX_PUBLIC_KEY_SIZE, + unlock_credential->challenge_signature, + AVB_RSA4096_NUM_BYTES, + challenge_hash, + AVB_SHA512_DIGEST_SIZE, + algorithm_data->padding, + algorithm_data->padding_len)) { + avb_error("Invalid unlock challenge signature.\n"); + return AVB_IO_RESULT_OK; + } + + *out_is_trusted = true; + return AVB_IO_RESULT_OK; +} diff --git a/lib/avb/libavb_atx/avb_atx_validate.h b/lib/avb/libavb_atx/avb_atx_validate.h new file mode 100644 index 00000000000..1a0690d4913 --- /dev/null +++ b/lib/avb/libavb_atx/avb_atx_validate.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_ATX_H) && !defined(AVB_COMPILATION) +#error \ + "Never include this file directly, include libavb_atx/libavb_atx.h instead." +#endif + +#ifndef AVB_ATX_VALIDATE_H_ +#define AVB_ATX_VALIDATE_H_ + +#include "avb_atx_ops.h" +#include "avb_atx_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Rollback index locations for Android Things key versions. */ +#define AVB_ATX_PIK_VERSION_LOCATION 0x1000 +#define AVB_ATX_PSK_VERSION_LOCATION 0x1001 + +/* An implementation of validate_vbmeta_public_key for Android Things. See + * libavb/avb_ops.h for details on validate_vbmeta_public_key in general. This + * implementation uses the metadata expected with Android Things vbmeta images + * to perform validation on the public key. The ATX ops must be implemented. + * That is, |ops->atx_ops| must be valid. + * + * There are a multiple values that need verification: + * - Permanent Product Attributes: A hash of these attributes is fused into + * hardware. Consistency is checked. + * - Product Root Key (PRK): This key is provided in permanent attributes and + * is the root authority for all Android Things + * products. + * - Product Intermediate Key (PIK): This key is a rotated intermediary. It is + * certified by the PRK. + * - Product Signing Key (PSK): This key is a rotated authority for a specific + * Android Things product. It is certified by a + * PIK and must match |public_key_data|. + * - Product ID: This value is provided in permanent attributes and is unique + * to a specific Android Things product. This value must match + * the subject of the PSK certificate. + */ +AvbIOResult avb_atx_validate_vbmeta_public_key( + AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted); + +/* Generates a challenge which can be used to create an unlock credential. */ +AvbIOResult avb_atx_generate_unlock_challenge( + AvbAtxOps* atx_ops, AvbAtxUnlockChallenge* out_unlock_challenge); + +/* Validates an unlock credential. The certificate validation is very similar to + * the validation of public key metadata except in place of the PSK is a Product + * Unlock Key (PUK) and the certificate usage field identifies it as such. The + * challenge signature field is verified against this PUK. + */ +AvbIOResult avb_atx_validate_unlock_credential( + AvbAtxOps* atx_ops, + const AvbAtxUnlockCredential* unlock_credential, + bool* out_is_trusted); + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_ATX_VALIDATE_H_ */ diff --git a/lib/avb/libavb_atx/libavb_atx.h b/lib/avb/libavb_atx/libavb_atx.h new file mode 100644 index 00000000000..839c0afa98c --- /dev/null +++ b/lib/avb/libavb_atx/libavb_atx.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef LIBAVB_ATX_H_ +#define LIBAVB_ATX_H_ + +#include + +/* The AVB_INSIDE_LIBAVB_ATX_H preprocessor symbol is used to enforce + * library users to include only this file. All public interfaces, and + * only public interfaces, must be included here. + */ + +#define AVB_INSIDE_LIBAVB_ATX_H +#include "avb_atx_ops.h" +#include "avb_atx_types.h" +#include "avb_atx_validate.h" +#undef AVB_INSIDE_LIBAVB_ATX_H + +#endif /* LIBAVB_ATX_H_ */ diff --git a/lib/trusty/ql-tipc/LICENSE b/lib/trusty/ql-tipc/LICENSE new file mode 100644 index 00000000000..d21621abc4b --- /dev/null +++ b/lib/trusty/ql-tipc/LICENSE @@ -0,0 +1,20 @@ +Copyright 2016, The Android Open Source Project + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be +included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/lib/trusty/ql-tipc/Makefile b/lib/trusty/ql-tipc/Makefile new file mode 100644 index 00000000000..5ee616ba932 --- /dev/null +++ b/lib/trusty/ql-tipc/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2016 The Android Open Source Project +# +# Permission is hereby granted, free of charge, to any person +# obtaining a copy of this software and associated documentation +# files (the "Software"), to deal in the Software without +# restriction, including without limitation the rights to use, copy, +# modify, merge, publish, distribute, sublicense, and/or sell copies +# of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be +# included in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# + +# Sample Makefile for U-boot + +#ccflags-y += -DTIPC_ENABLE_DEBUG + +TRUSTY_DIR = lib/trusty +#ccflags-y += -I$(TRUSTY_DIR)/ql-tipc/include +ccflags-y += -I$(TRUSTY_DIR)/interface/include + +QL_TIPC = . +obj-y += \ + $(QL_TIPC)/avb.o \ + $(QL_TIPC)/hwcrypto.o \ + $(QL_TIPC)/keymaster.o \ + $(QL_TIPC)/keymaster_serializable.o \ + $(QL_TIPC)/ipc.o \ + $(QL_TIPC)/ipc_dev.o \ + $(QL_TIPC)/libtipc.o \ + $(QL_TIPC)/rpmb_proxy.o \ + $(QL_TIPC)/util.o \ + sysdeps/sysdeps_uboot.o \ + sysdeps/storage_ops_uboot.o + +obj-$(CONFIG_ARM) += \ + $(QL_TIPC)/arch/arm/trusty_mem.o \ + $(QL_TIPC)/arch/arm/trusty_dev.o diff --git a/lib/trusty/ql-tipc/README.md b/lib/trusty/ql-tipc/README.md new file mode 100644 index 00000000000..76e37817561 --- /dev/null +++ b/lib/trusty/ql-tipc/README.md @@ -0,0 +1,30 @@ +# Queueless Trusty IPC + +ql-tipc is a portable client library that implements Trusty queueless IPC. +It is intended to enable Trusty IPC in bootloader environments. + +## Code organization + +### IPC components + +- libtipc - Functions to be called by library user +- ipc - IPC library +- ipc_dev - Helper functions for sending requests to the secure OS +- rpmb_proxy - Handles RPMB requests from secure storage service +- avb - Sends requests to the Android Verified Boot service + +### Misc + +- examples/ - Implementations of bootloader-specific code. +- arch/$ARCH/ - Architecture dependent implementation of Trusty device + (see trusty_dev.h). Implements SMCs on ARM for example. + +## Portability Notes + +The suggested approach to porting ql-tipc is to copy all header and C files +into the bootloader and integrate as needed. RPMB storage operations and +functions defined in trusty/sysdeps.h require system dependent implementations. + +If the TIPC_ENABLE_DEBUG preprocessor symbol is set, the code will include +debug information and run-time checks. Production builds should not use this. + diff --git a/lib/trusty/ql-tipc/arch/arm/sm_err.h b/lib/trusty/ql-tipc/arch/arm/sm_err.h new file mode 100644 index 00000000000..940125611c4 --- /dev/null +++ b/lib/trusty/ql-tipc/arch/arm/sm_err.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef QL_TIPC_SM_ERR_H_ +#define QL_TIPC_SM_ERR_H_ + +/* Errors from the secure monitor */ +#define SM_ERR_UNDEFINED_SMC 0xFFFFFFFF /* Unknown SMC (defined by ARM DEN 0028A(0.9.0) */ +#define SM_ERR_INVALID_PARAMETERS -2 +#define SM_ERR_INTERRUPTED -3 /* Got interrupted. Call back with restart SMC */ +#define SM_ERR_UNEXPECTED_RESTART -4 /* Got an restart SMC when we didn't expect it */ +#define SM_ERR_BUSY -5 /* Temporarily busy. Call back with original args */ +#define SM_ERR_INTERLEAVED_SMC -6 /* Got a trusted_service SMC when a restart SMC is required */ +#define SM_ERR_INTERNAL_FAILURE -7 /* Unknown error */ +#define SM_ERR_NOT_SUPPORTED -8 +#define SM_ERR_NOT_ALLOWED -9 /* SMC call not allowed */ +#define SM_ERR_END_OF_INPUT -10 +#define SM_ERR_PANIC -11 /* Secure OS crashed */ +#define SM_ERR_FIQ_INTERRUPTED -12 /* Got interrupted by FIQ. Call back with SMC_SC_RESTART_FIQ on same CPU */ +#define SM_ERR_CPU_IDLE -13 /* SMC call waiting for another CPU */ +#define SM_ERR_NOP_INTERRUPTED -14 /* Got interrupted. Call back with new SMC_SC_NOP */ +#define SM_ERR_NOP_DONE -15 /* Cpu idle after SMC_SC_NOP (not an error) */ + +#endif /* QL_TIPC_SM_ERR_H_ */ diff --git a/lib/trusty/ql-tipc/arch/arm/smcall.h b/lib/trusty/ql-tipc/arch/arm/smcall.h new file mode 100644 index 00000000000..695776c93ec --- /dev/null +++ b/lib/trusty/ql-tipc/arch/arm/smcall.h @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef QL_TIPC_SMCALL_H_ +#define QL_TIPC_SMCALL_H_ + +#define SMC_NUM_ENTITIES 64 +#define SMC_NUM_ARGS 4 +#define SMC_NUM_PARAMS (SMC_NUM_ARGS - 1) + +#define SMC_IS_FASTCALL(smc_nr) ((smc_nr) & 0x80000000) +#define SMC_IS_SMC64(smc_nr) ((smc_nr) & 0x40000000) +#define SMC_ENTITY(smc_nr) (((smc_nr) & 0x3F000000) >> 24) +#define SMC_FUNCTION(smc_nr) ((smc_nr) & 0x0000FFFF) + +#define SMC_NR(entity, fn, fastcall, smc64) ((((fastcall) & 0x1) << 31) | \ + (((smc64) & 0x1) << 30) | \ + (((entity) & 0x3F) << 24) | \ + ((fn) & 0xFFFF) \ + ) + +#define SMC_FASTCALL_NR(entity, fn) SMC_NR((entity), (fn), 1, 0) +#define SMC_STDCALL_NR(entity, fn) SMC_NR((entity), (fn), 0, 0) +#define SMC_FASTCALL64_NR(entity, fn) SMC_NR((entity), (fn), 1, 1) +#define SMC_STDCALL64_NR(entity, fn) SMC_NR((entity), (fn), 0, 1) + +#define SMC_ENTITY_ARCH 0 /* ARM Architecture calls */ +#define SMC_ENTITY_CPU 1 /* CPU Service calls */ +#define SMC_ENTITY_SIP 2 /* SIP Service calls */ +#define SMC_ENTITY_OEM 3 /* OEM Service calls */ +#define SMC_ENTITY_STD 4 /* Standard Service calls */ +#define SMC_ENTITY_RESERVED 5 /* Reserved for future use */ +#define SMC_ENTITY_TRUSTED_APP 48 /* Trusted Application calls */ +#define SMC_ENTITY_TRUSTED_OS 50 /* Trusted OS calls */ +#define SMC_ENTITY_LOGGING 51 /* Used for secure -> nonsecure logging */ +#define SMC_ENTITY_SECURE_MONITOR 60 /* Trusted OS calls internal to secure monitor */ + +/* FC = Fast call, SC = Standard call */ +#define SMC_SC_RESTART_LAST SMC_STDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0) +#define SMC_SC_LOCKED_NOP SMC_STDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 1) + +/** + * SMC_SC_RESTART_FIQ - Re-enter trusty after it was interrupted by an fiq + * + * No arguments, no return value. + * + * Re-enter trusty after returning to ns to process an fiq. Must be called iff + * trusty returns SM_ERR_FIQ_INTERRUPTED. + * + * Enable by selecting api version TRUSTY_API_VERSION_RESTART_FIQ (1) or later. + */ +#define SMC_SC_RESTART_FIQ SMC_STDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 2) + +/** + * SMC_SC_NOP - Enter trusty to run pending work. + * + * No arguments. + * + * Returns SM_ERR_NOP_INTERRUPTED or SM_ERR_NOP_DONE. + * If SM_ERR_NOP_INTERRUPTED is returned, the call must be repeated. + * + * Enable by selecting api version TRUSTY_API_VERSION_SMP (2) or later. + */ +#define SMC_SC_NOP SMC_STDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 3) + +/* + * Return from secure os to non-secure os with return value in r1 + */ +#define SMC_SC_NS_RETURN SMC_STDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0) + +#define SMC_FC_RESERVED SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0) +#define SMC_FC_FIQ_EXIT SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 1) +#define SMC_FC_REQUEST_FIQ SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 2) +#define SMC_FC_GET_NEXT_IRQ SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 3) +#define SMC_FC_FIQ_ENTER SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 4) + +#define SMC_FC64_SET_FIQ_HANDLER SMC_FASTCALL64_NR(SMC_ENTITY_SECURE_MONITOR, 5) +#define SMC_FC64_GET_FIQ_REGS SMC_FASTCALL64_NR (SMC_ENTITY_SECURE_MONITOR, 6) + +#define SMC_FC_CPU_SUSPEND SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 7) +#define SMC_FC_CPU_RESUME SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 8) + +#define SMC_FC_AARCH_SWITCH SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 9) +#define SMC_FC_GET_VERSION_STR SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 10) + +/** + * SMC_FC_API_VERSION - Find and select supported API version. + * + * @r1: Version supported by client. + * + * Returns version supported by trusty. + * + * If multiple versions are supported, the client should start by calling + * SMC_FC_API_VERSION with the largest version it supports. Trusty will then + * return a version it supports. If the client does not support the version + * returned by trusty and the version returned is less than the version + * requested, repeat the call with the largest supported version less than the + * last returned version. + * + * This call must be made before any calls that are affected by the api version. + */ +#define TRUSTY_API_VERSION_RESTART_FIQ (1) +#define TRUSTY_API_VERSION_SMP (2) +#define TRUSTY_API_VERSION_SMP_NOP (3) +#define TRUSTY_API_VERSION_CURRENT (3) +#define SMC_FC_API_VERSION SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 11) + +/* TRUSTED_OS entity calls */ +#define SMC_SC_VIRTIO_GET_DESCR SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 20) +#define SMC_SC_VIRTIO_START SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 21) +#define SMC_SC_VIRTIO_STOP SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 22) + +#define SMC_SC_VDEV_RESET SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 23) +#define SMC_SC_VDEV_KICK_VQ SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 24) +#define SMC_NC_VDEV_KICK_VQ SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 25) + +/* Queueless Trusty IPC Interface */ +#define SMC_SC_TRUSTY_IPC_CREATE_QL_DEV SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 30) +#define SMC_SC_TRUSTY_IPC_SHUTDOWN_QL_DEV SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 31) +#define SMC_SC_TRUSTY_IPC_HANDLE_QL_DEV_CMD SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 32) + +#endif /* QL_TIPC_SMCALL_H_ */ diff --git a/lib/trusty/ql-tipc/arch/arm/trusty_dev.c b/lib/trusty/ql-tipc/arch/arm/trusty_dev.c new file mode 100644 index 00000000000..bd9a5fbfb6c --- /dev/null +++ b/lib/trusty/ql-tipc/arch/arm/trusty_dev.c @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include + +#include "sm_err.h" +#include "smcall.h" + +struct trusty_dev; + +#define LOCAL_LOG 0 + +#ifndef __asmeq +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" +#endif + +#ifdef NS_ARCH_ARM64 +#define SMC_ARG0 "x0" +#define SMC_ARG1 "x1" +#define SMC_ARG2 "x2" +#define SMC_ARG3 "x3" +#define SMC_ARCH_EXTENSION "" +#define SMC_REGISTERS_TRASHED "x4","x5","x6","x7","x8","x9","x10","x11", \ + "x12","x13","x14","x15","x16","x17" +#else +#define SMC_ARG0 "r0" +#define SMC_ARG1 "r1" +#define SMC_ARG2 "r2" +#define SMC_ARG3 "r3" +#define SMC_ARCH_EXTENSION ".arch_extension sec\n" +#define SMC_REGISTERS_TRASHED "ip" +#endif + +/* + * Execute SMC call into trusty + */ +static unsigned long smc(unsigned long r0, + unsigned long r1, + unsigned long r2, + unsigned long r3) +{ + register unsigned long _r0 __asm__(SMC_ARG0) = r0; + register unsigned long _r1 __asm__(SMC_ARG1) = r1; + register unsigned long _r2 __asm__(SMC_ARG2) = r2; + register unsigned long _r3 __asm__(SMC_ARG3) = r3; + + __asm__ volatile( + __asmeq("%0", SMC_ARG0) + __asmeq("%1", SMC_ARG1) + __asmeq("%2", SMC_ARG2) + __asmeq("%3", SMC_ARG3) + __asmeq("%4", SMC_ARG0) + __asmeq("%5", SMC_ARG1) + __asmeq("%6", SMC_ARG2) + __asmeq("%7", SMC_ARG3) + SMC_ARCH_EXTENSION + "smc #0" /* switch to secure world */ + : "=r" (_r0), "=r" (_r1), "=r" (_r2), "=r" (_r3) + : "r" (_r0), "r" (_r1), "r" (_r2), "r" (_r3) + : SMC_REGISTERS_TRASHED); + return _r0; +} + +static int32_t trusty_fast_call32(struct trusty_dev *dev, uint32_t smcnr, + uint32_t a0, uint32_t a1, uint32_t a2) +{ + trusty_assert(dev); + trusty_assert(SMC_IS_FASTCALL(smcnr)); + + return smc(smcnr, a0, a1, a2); +} + +static unsigned long trusty_std_call_inner(struct trusty_dev *dev, + unsigned long smcnr, + unsigned long a0, + unsigned long a1, + unsigned long a2) +{ + unsigned long ret; + int retry = 5; + + trusty_debug("%s(0x%lx 0x%lx 0x%lx 0x%lx)\n", __func__, smcnr, a0, a1, a2); + + while (true) { + ret = smc(smcnr, a0, a1, a2); + while ((int32_t)ret == SM_ERR_FIQ_INTERRUPTED) + ret = smc(SMC_SC_RESTART_FIQ, 0, 0, 0); + if ((int)ret != SM_ERR_BUSY || !retry) + break; + + trusty_debug("%s(0x%lx 0x%lx 0x%lx 0x%lx) returned busy, retry\n", + __func__, smcnr, a0, a1, a2); + + retry--; + } + + return ret; +} + +static unsigned long trusty_std_call_helper(struct trusty_dev *dev, + unsigned long smcnr, + unsigned long a0, + unsigned long a1, + unsigned long a2) +{ + unsigned long ret; + unsigned long irq_state; + + while (true) { + trusty_local_irq_disable(&irq_state); + ret = trusty_std_call_inner(dev, smcnr, a0, a1, a2); + trusty_local_irq_restore(&irq_state); + + if ((int)ret != SM_ERR_BUSY) + break; + + trusty_idle(dev); + } + + return ret; +} + +static int32_t trusty_std_call32(struct trusty_dev *dev, uint32_t smcnr, + uint32_t a0, uint32_t a1, uint32_t a2) +{ + int ret; + + trusty_assert(dev); + trusty_assert(!SMC_IS_FASTCALL(smcnr)); + + if (smcnr != SMC_SC_NOP) { + trusty_lock(dev); + } + + trusty_debug("%s(0x%x 0x%x 0x%x 0x%x) started\n", __func__, + smcnr, a0, a1, a2); + + ret = trusty_std_call_helper(dev, smcnr, a0, a1, a2); + while (ret == SM_ERR_INTERRUPTED || ret == SM_ERR_CPU_IDLE) { + trusty_debug("%s(0x%x 0x%x 0x%x 0x%x) interrupted\n", __func__, + smcnr, a0, a1, a2); + if (ret == SM_ERR_CPU_IDLE) { + trusty_idle(dev); + } + ret = trusty_std_call_helper(dev, SMC_SC_RESTART_LAST, 0, 0, 0); + } + + trusty_debug("%s(0x%x 0x%x 0x%x 0x%x) returned 0x%x\n", + __func__, smcnr, a0, a1, a2, ret); + + if (smcnr != SMC_SC_NOP) { + trusty_unlock(dev); + } + + return ret; +} + +static int trusty_call32_mem_buf(struct trusty_dev *dev, uint32_t smcnr, + struct ns_mem_page_info *page, uint32_t size) +{ + trusty_assert(dev); + trusty_assert(page); + + if (SMC_IS_FASTCALL(smcnr)) { + return trusty_fast_call32(dev, smcnr, + (uint32_t)page->attr, + (uint32_t)(page->attr >> 32), size); + } else { + return trusty_std_call32(dev, smcnr, + (uint32_t)page->attr, + (uint32_t)(page->attr >> 32), size); + } +} + +int trusty_dev_init_ipc(struct trusty_dev *dev, + struct ns_mem_page_info *buf, uint32_t buf_size) +{ + return trusty_call32_mem_buf(dev, SMC_SC_TRUSTY_IPC_CREATE_QL_DEV, + buf, buf_size); +} + +int trusty_dev_exec_ipc(struct trusty_dev *dev, + struct ns_mem_page_info *buf, uint32_t buf_size) +{ + return trusty_call32_mem_buf(dev, SMC_SC_TRUSTY_IPC_HANDLE_QL_DEV_CMD, + buf, buf_size); +} + +int trusty_dev_shutdown_ipc(struct trusty_dev *dev, + struct ns_mem_page_info *buf, uint32_t buf_size) +{ + return trusty_call32_mem_buf(dev, SMC_SC_TRUSTY_IPC_SHUTDOWN_QL_DEV, + buf, buf_size); +} + + +static int trusty_init_api_version(struct trusty_dev *dev) +{ + uint32_t api_version; + + api_version = trusty_fast_call32(dev, SMC_FC_API_VERSION, + TRUSTY_API_VERSION_CURRENT, 0, 0); + if (api_version == SM_ERR_UNDEFINED_SMC) + api_version = 0; + + if (api_version > TRUSTY_API_VERSION_CURRENT) { + trusty_error("unsupported trusty api version %u > %u\n", + api_version, TRUSTY_API_VERSION_CURRENT); + return -1; + } + + trusty_info("selected trusty api version: %u (requested %u)\n", + api_version, TRUSTY_API_VERSION_CURRENT); + + dev->api_version = api_version; + + return 0; +} + +int trusty_dev_init(struct trusty_dev *dev, void *priv_data) +{ + trusty_assert(dev); + + dev->priv_data = priv_data; + return trusty_init_api_version(dev); +} + +int trusty_dev_shutdown(struct trusty_dev *dev) +{ + trusty_assert(dev); + + dev->priv_data = NULL; + return 0; +} + diff --git a/lib/trusty/ql-tipc/arch/arm/trusty_mem.c b/lib/trusty/ql-tipc/arch/arm/trusty_mem.c new file mode 100644 index 00000000000..56d8348d3ce --- /dev/null +++ b/lib/trusty/ql-tipc/arch/arm/trusty_mem.c @@ -0,0 +1,284 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include + +/* 48-bit physical address bits 47:12 */ + +#define NS_PTE_PHYSADDR_SHIFT 12 +#define NS_PTE_PHYSADDR(pte) ((pte) & 0xFFFFFFFFF000ULL) + +/* Access permissions bits 7:6 + * EL0 EL1 + * 00 None RW + * 01 RW RW + * 10 None RO + * 11 RO RO + */ +#define NS_PTE_AP_SHIFT 6 +#define NS_PTE_AP_MASK (0x3 << NS_PTE_AP_SHIFT) + +/* Memory type and cache attributes bits 55:48 */ +#define NS_PTE_MAIR_SHIFT 48 +#define NS_PTE_MAIR_MASK (0x00FFULL << NS_PTE_MAIR_SHIFT) + +#define NS_PTE_MAIR_INNER_SHIFT 48 +#define NS_PTE_MAIR_INNER_MASK (0x000FULL << NS_PTE_MAIR_INNER_SHIFT) + +#define NS_PTE_MAIR_OUTER_SHIFT 52 +#define NS_PTE_MAIR_OUTER_MASK (0x000FULL << NS_PTE_MAIR_OUTER_SHIFT) + +/* Normal memory */ +#define NS_MAIR_NORMAL_CACHED_WB_RWA 0xFF /* inner and outer write back read/write allocate */ +#define NS_MAIR_NORMAL_CACHED_WT_RA 0xAA /* inner and outer write through read allocate */ +#define NS_MAIR_NORMAL_CACHED_WB_RA 0xEE /* inner and outer write back, read allocate */ +#define NS_MAIR_NORMAL_UNCACHED 0x44 /* uncached */ + +/* Device memory */ +#define NS_MAIR_DEVICE_STRONGLY_ORDERED 0x00 /* nGnRnE (strongly ordered) */ +#define NS_MAIR_DEVICE 0x04 /* nGnRE (device) */ +#define NS_MAIR_DEVICE_GRE 0x0C /* GRE */ + +/* shareable attributes bits 9:8 */ +#define NS_PTE_SHAREABLE_SHIFT 8 + +#define NS_NON_SHAREABLE 0x0 +#define NS_OUTER_SHAREABLE 0x2 +#define NS_INNER_SHAREABLE 0x3 + +typedef uintptr_t addr_t; +typedef uintptr_t vaddr_t; +typedef uintptr_t paddr_t; + +#if NS_ARCH_ARM64 + +#define PAR_F (0x1 << 0) + +/* + * ARM64 + */ + +/* Note: this will crash if called from user space */ +static void arm64_write_ATS1ExW(uint64_t vaddr) +{ + uint64_t _current_el; + + __asm__ volatile("mrs %0, CurrentEL" : "=r" (_current_el)); + + _current_el = (_current_el >> 2) & 0x3; + switch (_current_el) { + case 0x1: + __asm__ volatile("at S1E1W, %0" :: "r" (vaddr)); + break; + case 0x2: + __asm__ volatile("at S1E2W, %0" :: "r" (vaddr)); + break; + case 0x3: + default: + trusty_fatal("Unsupported execution state: EL%u\n", _current_el ); + break; + } + + __asm__ volatile("isb" ::: "memory"); +} + +static uint64_t arm64_read_par64(void) +{ + uint64_t _val; + __asm__ volatile("mrs %0, par_el1" : "=r" (_val)); + return _val; +} + + +static uint64_t va2par(vaddr_t va) +{ + uint64_t par; + unsigned long irq_state; + + trusty_local_irq_disable(&irq_state); + arm64_write_ATS1ExW(va); + par = arm64_read_par64(); + trusty_local_irq_restore(&irq_state); + + return par; +} + +static uint64_t par2attr(uint64_t par) +{ + uint64_t attr; + + /* set phys address */ + attr = NS_PTE_PHYSADDR(par); + + /* cache attributes */ + attr |= ((par >> 56) & 0xFF) << NS_PTE_MAIR_SHIFT; + + /* shareable attributes */ + attr |= ((par >> 7) & 0x03) << NS_PTE_SHAREABLE_SHIFT; + + /* the memory is writable and accessible so leave AP field 0 */ + attr |= 0x0 << NS_PTE_AP_SHIFT; + + return attr; +} + +#else + +#define PAR_F (0x1 << 0) +#define PAR_SS (0x1 << 1) +#define PAR_SH (0x1 << 7) +#define PAR_NOS (0x1 << 10) +#define PAR_LPAE (0x1 << 11) + +/* + * ARM32 + */ + +/* Note: this will crash if called from user space */ +static void arm_write_ATS1xW(uint64_t vaddr) +{ + uint32_t _cpsr; + + __asm__ volatile("mrs %0, cpsr" : "=r"(_cpsr)); + + if ((_cpsr & 0xF) == 0xa) + __asm__ volatile("mcr p15, 4, %0, c7, c8, 1" : : "r"(vaddr)); + else + __asm__ volatile("mcr p15, 0, %0, c7, c8, 1" : : "r"(vaddr)); +} + +static uint64_t arm_read_par64(void) +{ + uint32_t lower, higher; + + __asm__ volatile( + "mrc p15, 0, %0, c7, c4, 0 \n" + "tst %0, #(1 << 11) @ LPAE / long desc format\n" + "moveq %1, #0 \n" + "mrrcne p15, 0, %0, %1, c7 \n" + :"=r"(lower), "=r"(higher) : : + ); + + return ((uint64_t)higher << 32) | lower; +} + + +static uint8_t ish_to_mair[8] = { + 0x04, /* 0b000 Non cacheble */ + 0x00, /* 0b001 Strongly ordered */ + 0xF0, /* 0b010 reserved */ + 0x04, /* 0b011 device */ + 0xF0, /* 0b100 reserved */ + 0x0F, /* 0b101 write back - write allocate */ + 0x0A, /* 0b110 write through */ + 0x0E, /* 0b111 write back - no write allocate */ +}; + +static uint8_t osh_to_mair[4] = { + 0x00, /* 0b00 Non-cacheable */ + 0x0F, /* 0b01 Write-back, Write-allocate */ + 0x0A, /* 0b10 Write-through, no Write-allocate */ + 0x0E, /* 0b11 Write-back, no Write-allocate */ +}; + +static uint64_t par2attr(uint64_t par) +{ + uint64_t attr; + + if (par & PAR_LPAE) { + /* set phys address */ + attr = NS_PTE_PHYSADDR(par); + + /* cache attributes */ + attr |= ((par >> 56) & 0xFF) << NS_PTE_MAIR_SHIFT; + + /* shareable attributes */ + attr |= ((par >> 7) & 0x03) << NS_PTE_SHAREABLE_SHIFT; + + } else { + + /* set phys address */ + trusty_assert((par & PAR_SS) == 0); /* super section not supported */ + attr = NS_PTE_PHYSADDR(par); + + /* cache attributes */ + uint64_t inner = ((uint64_t)ish_to_mair[(par >> 4) & 0x7]) << NS_PTE_MAIR_INNER_SHIFT; + uint64_t outer = ((uint64_t)osh_to_mair[(par >> 2) & 0x3]) << NS_PTE_MAIR_OUTER_SHIFT; + uint64_t cache_attributes = (outer << 4) | inner; + + /* Trusty does not support any kind of device memory, so we will force + * cache attributes to be NORMAL UNCACHED on the Trusty side. + */ + if (cache_attributes == NS_MAIR_DEVICE_STRONGLY_ORDERED) { + attr |= ((uint64_t)NS_MAIR_NORMAL_UNCACHED << NS_PTE_MAIR_SHIFT); + } else { + attr |= inner; + attr |= outer; + } + + /* shareable attributes */ + if (par & PAR_SH) { + /* how to handle NOS bit ? */ + attr |= ((uint64_t)NS_INNER_SHAREABLE) << NS_PTE_SHAREABLE_SHIFT; + } else { + attr |= ((uint64_t)NS_NON_SHAREABLE) << NS_PTE_SHAREABLE_SHIFT; + } + } + + /* the memory is writable and accessible so leave AP field 0 */ + attr |= 0x0 << NS_PTE_AP_SHIFT; + + return attr; +} + +static uint64_t va2par(vaddr_t va) +{ + uint64_t par; + unsigned long irq_state; + + trusty_local_irq_disable(&irq_state); + arm_write_ATS1xW(va); + par = arm_read_par64(); + trusty_local_irq_restore(&irq_state); + + return par; +} + +#endif /* ARM64 */ + + +int trusty_encode_page_info(struct ns_mem_page_info *inf, void *va) +{ + uint64_t par = va2par((vaddr_t)va); + + if (par & PAR_F) { + return -1; + } + + inf->attr = par2attr(par); + + return 0; +} + diff --git a/lib/trusty/ql-tipc/avb.c b/lib/trusty/ql-tipc/avb.c new file mode 100644 index 00000000000..95b26fd2f89 --- /dev/null +++ b/lib/trusty/ql-tipc/avb.c @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include + +#define LOCAL_LOG 0 + +static bool initialized; +static int avb_tipc_version = 1; +static struct trusty_ipc_chan avb_chan; + +static int avb_send_request(struct avb_message *msg, void *req, size_t req_len) +{ + struct trusty_ipc_iovec req_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = req, .len = req_len }, + }; + + return trusty_ipc_send(&avb_chan, req_iovs, req ? 2 : 1, true); +} + +static int avb_read_response(struct avb_message *msg, uint32_t cmd, void *resp, + size_t resp_len) +{ + int rc; + struct trusty_ipc_iovec resp_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = resp, .len = resp_len }, + }; + + rc = trusty_ipc_recv(&avb_chan, resp_iovs, resp ? 2 : 1, true); + if (rc < 0) { + trusty_error("failed (%d) to recv response\n", rc); + return rc; + } + if (msg->cmd != (cmd | AVB_RESP_BIT)) { + trusty_error("malformed response\n"); + return TRUSTY_ERR_GENERIC; + } + /* return payload size */ + return rc - sizeof(*msg); +} + +/* + * Convenience function to send a request to the AVB service and read the + * response. + * + * @cmd: the command + * @req: the request buffer + * @req_size: size of the request buffer + * @resp: the response buffer + * @resp_size_p: pointer to the size of the response buffer. changed to the + actual size of the response read from the secure side + */ +static int avb_do_tipc(uint32_t cmd, void *req, uint32_t req_size, void *resp, + uint32_t *resp_size_p) +{ + int rc; + struct avb_message msg = { .cmd = cmd }; + + if (!initialized && cmd != AVB_GET_VERSION) { + trusty_error("%s: AVB TIPC client not initialized\n", __func__); + return TRUSTY_ERR_GENERIC; + } + + rc = avb_send_request(&msg, req, req_size); + if (rc < 0) { + trusty_error("%s: failed (%d) to send AVB request\n", __func__, rc); + return rc; + } + + uint32_t resp_size = resp_size_p ? *resp_size_p : 0; + rc = avb_read_response(&msg, cmd, resp, resp_size); + if (rc < 0) { + trusty_error("%s: failed (%d) to read AVB response\n", __func__, rc); + return rc; + } + /* change response size to actual response size */ + if (resp_size_p && rc != *resp_size_p) { + *resp_size_p = rc; + } + if (msg.result != AVB_ERROR_NONE) { + trusty_error("%s: AVB service returned error (%d)\n", __func__, + msg.result); + return TRUSTY_ERR_GENERIC; + } + return TRUSTY_ERR_NONE; +} + +static int avb_get_version(uint32_t *version) +{ + int rc; + struct avb_get_version_resp resp; + uint32_t resp_size = sizeof(resp); + + rc = avb_do_tipc(AVB_GET_VERSION, NULL, 0, &resp, &resp_size); + + *version = resp.version; + return rc; +} + + +int avb_tipc_init(struct trusty_ipc_dev *dev) +{ + int rc; + uint32_t version = 0; + + trusty_assert(dev); + trusty_assert(!initialized); + + trusty_ipc_chan_init(&avb_chan, dev); + trusty_debug("Connecting to AVB service\n"); + + /* connect to AVB service and wait for connect to complete */ + rc = trusty_ipc_connect(&avb_chan, AVB_PORT, true); + if (rc < 0) { + trusty_error("failed (%d) to connect to '%s'\n", rc, AVB_PORT); + return rc; + } + + /* check for version mismatch */ + rc = avb_get_version(&version); + if (rc != 0) { + trusty_error("Error getting version"); + return TRUSTY_ERR_GENERIC; + } + if (version != avb_tipc_version) { + trusty_error("AVB TIPC version mismatch. Expected %u, received %u\n", + avb_tipc_version, version); + return TRUSTY_ERR_GENERIC; + } + + /* mark as initialized */ + initialized = true; + + return TRUSTY_ERR_NONE; +} + +void avb_tipc_shutdown(struct trusty_ipc_dev *dev) +{ + if (!initialized) + return; /* nothing to do */ + + /* close channel */ + trusty_ipc_close(&avb_chan); + + initialized = false; +} + +int trusty_read_rollback_index(uint32_t slot, uint64_t *value) +{ + int rc; + struct avb_rollback_req req = { .slot = slot, .value = 0 }; + struct avb_rollback_resp resp; + uint32_t resp_size = sizeof(resp); + + rc = avb_do_tipc(READ_ROLLBACK_INDEX, &req, sizeof(req), &resp, + &resp_size); + + *value = resp.value; + return rc; +} + +int trusty_write_rollback_index(uint32_t slot, uint64_t value) +{ + int rc; + struct avb_rollback_req req = { .slot = slot, .value = value }; + struct avb_rollback_resp resp; + uint32_t resp_size = sizeof(resp); + + rc = avb_do_tipc(WRITE_ROLLBACK_INDEX, &req, sizeof(req), &resp, + &resp_size); + return rc; +} + +int trusty_read_permanent_attributes(uint8_t *attributes, uint32_t size) +{ + uint8_t resp_buf[AVB_MAX_BUFFER_LENGTH]; + uint32_t resp_size = AVB_MAX_BUFFER_LENGTH; + int rc = avb_do_tipc(READ_PERMANENT_ATTRIBUTES, NULL, 0, resp_buf, + &resp_size); + if (rc != 0) { + return rc; + } + /* ensure caller passed size matches size returned by Trusty */ + if (size != resp_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + trusty_memcpy(attributes, resp_buf, resp_size); + return rc; +} + +int trusty_write_permanent_attributes(uint8_t *attributes, uint32_t size) +{ + return avb_do_tipc(WRITE_PERMANENT_ATTRIBUTES, attributes, size, NULL, + NULL); +} + +int trusty_read_vbmeta_public_key(uint8_t *publickey, uint32_t size) +{ + uint8_t resp_buf[AVB_MAX_BUFFER_LENGTH]; + uint32_t resp_size = AVB_MAX_BUFFER_LENGTH; + int rc = avb_do_tipc(READ_VBMETA_PUBLIC_KEY, NULL, 0, resp_buf, + &resp_size); + if (rc != 0) { + return rc; + } + /* ensure caller passed size matches size returned by Trusty */ + if (size < resp_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + trusty_memcpy(publickey, resp_buf, resp_size); + return rc; +} + +int trusty_write_vbmeta_public_key(uint8_t *publickey, uint32_t size) +{ + return avb_do_tipc(WRITE_VBMETA_PUBLIC_KEY, publickey, size, NULL, + NULL); +} + +int trusty_read_lock_state(uint8_t *lock_state) +{ + uint32_t resp_size = sizeof(*lock_state); + return avb_do_tipc(READ_LOCK_STATE, NULL, 0, lock_state, + &resp_size); +} + +int trusty_write_lock_state(uint8_t lock_state) +{ + return avb_do_tipc(WRITE_LOCK_STATE, &lock_state, sizeof(lock_state), NULL, + NULL); +} + +int trusty_lock_boot_state(void) +{ + return avb_do_tipc(LOCK_BOOT_STATE, NULL, 0, NULL, NULL); +} diff --git a/lib/trusty/ql-tipc/hwcrypto.c b/lib/trusty/ql-tipc/hwcrypto.c new file mode 100644 index 00000000000..ccaf18b4279 --- /dev/null +++ b/lib/trusty/ql-tipc/hwcrypto.c @@ -0,0 +1,242 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * Copyright NXP 2018 + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include +#include "common.h" + +#define LOCAL_LOG 0 +#define CAAM_KB_HEADER_LEN 48 + +static bool initialized; +static struct trusty_ipc_chan hwcrypto_chan; + +static int hwcrypto_send_request(struct hwcrypto_message *msg, void *req, size_t req_len) +{ + struct trusty_ipc_iovec req_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = req, .len = req_len }, + }; + + return trusty_ipc_send(&hwcrypto_chan, req_iovs, req ? 2 : 1, true); +} + +static int hwcrypto_read_response(struct hwcrypto_message *msg, uint32_t cmd, void *resp, + size_t resp_len) +{ + int rc; + struct trusty_ipc_iovec resp_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = resp, .len = resp_len }, + }; + + rc = trusty_ipc_recv(&hwcrypto_chan, resp_iovs, resp ? 2 : 1, true); + if (rc < 0) { + trusty_error("failed (%d) to recv response\n", rc); + return rc; + } + if (msg->cmd != (cmd | HWCRYPTO_RESP_BIT)) { + trusty_error("malformed response\n"); + return TRUSTY_ERR_GENERIC; + } + /* return payload size */ + return rc - sizeof(*msg); +} + +/* + * Convenience function to send a request to the hwcrypto service and read the + * response. + * + * @cmd: the command + * @req: the request buffer + * @req_size: size of the request buffer + * @resp: the response buffer + * @resp_size_p: pointer to the size of the response buffer. changed to the + actual size of the response read from the secure side + * @handle_rpmb: true if the request is expected to invoke RPMB callbacks + */ +static int hwcrypto_do_tipc(uint32_t cmd, void *req, uint32_t req_size, void *resp, + uint32_t *resp_size_p, bool handle_rpmb) +{ + int rc; + struct hwcrypto_message msg = { .cmd = cmd }; + + if (!initialized) { + trusty_error("%s: HWCRYPTO TIPC client not initialized\n", __func__); + return TRUSTY_ERR_GENERIC; + } + + rc = hwcrypto_send_request(&msg, req, req_size); + if (rc < 0) { + trusty_error("%s: failed (%d) to send hwcrypto request\n", __func__, rc); + return rc; + } + + if (handle_rpmb) { + /* handle any incoming RPMB requests */ + rc = rpmb_storage_proxy_poll(); + if (rc < 0) { + trusty_error("%s: failed (%d) to get RPMB requests\n", __func__, + rc); + return rc; + } + } + + uint32_t resp_size = resp_size_p ? *resp_size_p : 0; + rc = hwcrypto_read_response(&msg, cmd, resp, resp_size); + if (rc < 0) { + trusty_error("%s: failed (%d) to read HWCRYPTO response\n", __func__, rc); + return rc; + } + /* change response size to actual response size */ + if (resp_size_p && rc != *resp_size_p) { + *resp_size_p = rc; + } + if (msg.result != HWCRYPTO_ERROR_NONE) { + trusty_error("%s: HWCRYPTO service returned error (%d)\n", __func__, + msg.result); + return TRUSTY_ERR_GENERIC; + } + return TRUSTY_ERR_NONE; +} + +int hwcrypto_tipc_init(struct trusty_ipc_dev *dev) +{ + int rc; + + trusty_assert(dev); + trusty_assert(!initialized); + + trusty_ipc_chan_init(&hwcrypto_chan, dev); + trusty_debug("Connecting to hwcrypto service\n"); + + /* connect to hwcrypto service and wait for connect to complete */ + rc = trusty_ipc_connect(&hwcrypto_chan, HWCRYPTO_PORT, true); + if (rc < 0) { + trusty_error("failed (%d) to connect to '%s'\n", rc, HWCRYPTO_PORT); + return rc; + } + + /* mark as initialized */ + initialized = true; + + return TRUSTY_ERR_NONE; +} + +void hwcrypto_tipc_shutdown(struct trusty_ipc_dev *dev) +{ + if (!initialized) + return; /* nothing to do */ + + /* close channel */ + trusty_ipc_close(&hwcrypto_chan); + + initialized = false; +} + +int hwcrypto_hash(uint32_t in_addr, uint32_t in_len, uint32_t out_addr, + uint32_t out_len, enum hwcrypto_hash_algo algo) +{ + hwcrypto_hash_msg req; + unsigned long start, end; + + /* check the address */ + if (in_addr == 0 || out_addr == 0) + return TRUSTY_ERR_INVALID_ARGS; + /* fill the request buffer */ + req.in_addr = in_addr; + req.out_addr = out_addr; + req.in_len = in_len; + req.out_len = out_len; + req.algo = algo; + + /* flush dcache for input buffer */ + start = (unsigned long)in_addr & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)in_addr + in_len, ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); + + /* invalidate dcache for output buffer */ + start = (unsigned long)out_addr & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)out_addr + out_len, ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); + + int rc = hwcrypto_do_tipc(HWCRYPTO_HASH, (void*)&req, + sizeof(req), NULL, 0, false); + return rc; +} + +int hwcrypto_gen_blob(uint32_t plain_pa, + uint32_t plain_size, uint32_t blob_pa) +{ + hwcrypto_blob_msg req; + unsigned long start, end; + + /* check the address */ + if (plain_pa == 0 || blob_pa == 0) + return TRUSTY_ERR_INVALID_ARGS; + /* fill the request buffer */ + req.plain_pa = plain_pa; + req.plain_size = plain_size; + req.blob_pa = blob_pa; + + /* flush dcache for input buffer */ + start = (unsigned long)plain_pa & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)plain_pa + plain_size, ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); + + /* invalidate dcache for output buffer */ + start = (unsigned long)blob_pa & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)blob_pa + plain_size + + CAAM_KB_HEADER_LEN, ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); + + int rc = hwcrypto_do_tipc(HWCRYPTO_ENCAP_BLOB, (void*)&req, + sizeof(req), NULL, 0, false); + return rc; +} + +int hwcrypto_gen_rng(uint32_t buf, uint32_t len) +{ + hwcrypto_rng_msg req; + unsigned long start, end; + + /* check the address */ + if (buf == 0) + return TRUSTY_ERR_INVALID_ARGS; + /* fill the request buffer */ + req.buf = buf; + req.len = len; + + /* invalidate dcache for output buffer */ + start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)buf + len, ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); + + int rc = hwcrypto_do_tipc(HWCRYPTO_GEN_RNG, (void*)&req, + sizeof(req), NULL, 0, false); + return rc; +} diff --git a/lib/trusty/ql-tipc/ipc.c b/lib/trusty/ql-tipc/ipc.c new file mode 100644 index 00000000000..f488984d764 --- /dev/null +++ b/lib/trusty/ql-tipc/ipc.c @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include + +#define LOCAL_LOG 0 + +static int sync_ipc_on_connect_complete(struct trusty_ipc_chan *chan) +{ + trusty_assert(chan); + + chan->complete = 1; + return TRUSTY_EVENT_HANDLED; +} + +static int sync_ipc_on_message(struct trusty_ipc_chan *chan) +{ + trusty_assert(chan); + + chan->complete = 1; + return TRUSTY_EVENT_HANDLED; +} + +static int sync_ipc_on_disconnect(struct trusty_ipc_chan *chan) +{ + trusty_assert(chan); + + chan->complete = TRUSTY_ERR_CHANNEL_CLOSED; + return TRUSTY_EVENT_HANDLED; +} + +static int wait_for_complete(struct trusty_ipc_chan *chan) +{ + int rc; + + chan->complete = 0; + for (;;) { + rc = trusty_ipc_poll_for_event(chan->dev); + if (rc < 0) + return rc; + + if (chan->complete) + break; + + if (rc == TRUSTY_EVENT_NONE) + trusty_ipc_dev_idle(chan->dev); + } + + return chan->complete; +} + +static int wait_for_connect(struct trusty_ipc_chan *chan) +{ + trusty_debug("%s: chan %x: waiting for connect\n", __func__, + (int)chan->handle); + return wait_for_complete(chan); +} + +static int wait_for_send(struct trusty_ipc_chan *chan) +{ + trusty_debug("%s: chan %d: waiting for send\n", __func__, chan->handle); + return wait_for_complete(chan); +} + +static int wait_for_reply(struct trusty_ipc_chan *chan) +{ + trusty_debug("%s: chan %d: waiting for reply\n", __func__, chan->handle); + return wait_for_complete(chan); +} + +static struct trusty_ipc_ops sync_ipc_ops = { + .on_connect_complete = sync_ipc_on_connect_complete, + .on_message = sync_ipc_on_message, + .on_disconnect = sync_ipc_on_disconnect, +}; + +void trusty_ipc_chan_init(struct trusty_ipc_chan *chan, + struct trusty_ipc_dev *dev) +{ + trusty_assert(chan); + trusty_assert(dev); + + trusty_memset(chan, 0, sizeof(*chan)); + + chan->handle = INVALID_IPC_HANDLE; + chan->dev = dev; + chan->ops = &sync_ipc_ops; + chan->ops_ctx = chan; +} + +int trusty_ipc_connect(struct trusty_ipc_chan *chan, const char *port, + bool wait) +{ + int rc; + + trusty_assert(chan); + trusty_assert(chan->dev); + trusty_assert(chan->handle == INVALID_IPC_HANDLE); + trusty_assert(port); + + rc = trusty_ipc_dev_connect(chan->dev, port, (uint64_t)(uintptr_t)chan); + if (rc < 0) { + trusty_error("%s: init connection failed (%d)\n", __func__, rc); + return rc; + } + chan->handle = (handle_t)rc; + trusty_debug("chan->handle: %x\n", (int)chan->handle); + + /* got valid channel */ + if (wait) { + rc = wait_for_connect(chan); + if (rc < 0) { + trusty_error("%s: wait for connect failed (%d)\n", __func__, rc); + trusty_ipc_close(chan); + } + } + + return rc; +} + +int trusty_ipc_close(struct trusty_ipc_chan *chan) +{ + int rc; + + trusty_assert(chan); + + rc = trusty_ipc_dev_close(chan->dev, chan->handle); + chan->handle = INVALID_IPC_HANDLE; + + return rc; +} + +int trusty_ipc_send(struct trusty_ipc_chan *chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt, + bool wait) +{ + int rc; + + trusty_assert(chan); + trusty_assert(chan->dev); + trusty_assert(chan->handle); + +Again: + rc = trusty_ipc_dev_send(chan->dev, chan->handle, iovs, iovs_cnt); + if (rc == TRUSTY_ERR_SEND_BLOCKED) { + if (wait) { + rc = wait_for_send(chan); + if (rc < 0) { + trusty_error("%s: wait to send failed (%d)\n", __func__, rc); + return rc; + } + goto Again; + } + } + return rc; +} + +int trusty_ipc_recv(struct trusty_ipc_chan *chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt, + bool wait) +{ + int rc; + trusty_assert(chan); + trusty_assert(chan->dev); + trusty_assert(chan->handle); + + if (wait) { + rc = wait_for_reply(chan); + if (rc < 0) { + trusty_error("%s: wait to reply failed (%d)\n", __func__, rc); + return rc; + } + } + + rc = trusty_ipc_dev_recv(chan->dev, chan->handle, iovs, iovs_cnt); + if (rc < 0) + trusty_error("%s: ipc recv failed (%d)\n", __func__, rc); + + return rc; +} + +int trusty_ipc_poll_for_event(struct trusty_ipc_dev *ipc_dev) +{ + int rc; + struct trusty_ipc_event evt; + struct trusty_ipc_chan *chan; + + trusty_assert(dev); + + rc = trusty_ipc_dev_get_event(ipc_dev, 0, &evt); + if (rc) { + trusty_error("%s: get event failed (%d)\n", __func__, rc); + return rc; + } + + /* check if we have an event */ + if (!evt.event) { + trusty_debug("%s: no event\n", __func__); + return TRUSTY_EVENT_NONE; + } + + chan = (struct trusty_ipc_chan *)(uintptr_t)evt.cookie; + trusty_assert(chan && chan->ops); + + /* check if we have raw event handler */ + if (chan->ops->on_raw_event) { + /* invoke it first */ + rc = chan->ops->on_raw_event(chan, &evt); + if (rc < 0) { + trusty_error("%s: chan %d: raw event cb returned (%d)\n", __func__, + chan->handle, rc); + return rc; + } + if (rc > 0) + return rc; /* handled */ + } + + if (evt.event & IPC_HANDLE_POLL_ERROR) { + /* something is very wrong */ + trusty_error("%s: chan %d: chan in error state\n", __func__, + chan->handle); + return TRUSTY_ERR_GENERIC; + } + + /* send unblocked should be handled first as it is edge truggered event */ + if (evt.event & IPC_HANDLE_POLL_SEND_UNBLOCKED) { + if (chan->ops->on_send_unblocked) { + rc = chan->ops->on_send_unblocked(chan); + if (rc < 0) { + trusty_error("%s: chan %d: send unblocked cb returned (%d)\n", + __func__, chan->handle, rc); + return rc; + } + if (rc > 0) + return rc; /* handled */ + } + } + + /* check for connection complete */ + if (evt.event & IPC_HANDLE_POLL_READY) { + if (chan->ops->on_connect_complete) { + rc = chan->ops->on_connect_complete(chan); + if (rc < 0) { + trusty_error("%s: chan %d: ready cb returned (%d)\n", __func__, + chan->handle, rc); + return rc; + } + if (rc > 0) + return rc; /* handled */ + } + } + + /* check for incomming messages */ + if (evt.event & IPC_HANDLE_POLL_MSG) { + if (chan->ops->on_message) { + rc = chan->ops->on_message(chan); + if (rc < 0) { + trusty_error("%s: chan %d: msg cb returned (%d)\n", __func__, + chan->handle, rc); + return rc; + } + if (rc > 0) + return rc; + } + } + + /* check for hangups */ + if (evt.event & IPC_HANDLE_POLL_HUP) { + if (chan->ops->on_disconnect) { + rc = chan->ops->on_disconnect(chan); + if (rc < 0) { + trusty_error("%s: chan %d: hup cb returned (%d)\n", __func__, + chan->handle, rc); + return rc; + } + if (rc > 0) + return rc; + } + } + + return TRUSTY_ERR_NONE; +} diff --git a/lib/trusty/ql-tipc/ipc_dev.c b/lib/trusty/ql-tipc/ipc_dev.c new file mode 100644 index 00000000000..720acf22be0 --- /dev/null +++ b/lib/trusty/ql-tipc/ipc_dev.c @@ -0,0 +1,458 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include + +#define NS_PTE_PHYSADDR(pte) ((pte) & 0xFFFFFFFFF000ULL) + +#define QL_TIPC_DEV_RESP 0x8000 +#define QL_TIPC_DEV_CONNECT 0x1 +#define QL_TIPC_DEV_GET_EVENT 0x2 +#define QL_TIPC_DEV_SEND 0x3 +#define QL_TIPC_DEV_RECV 0x4 +#define QL_TIPC_DEV_DISCONNECT 0x5 + +#define LOCAL_LOG 0 + +struct trusty_ipc_cmd_hdr { + uint16_t opcode; + uint16_t flags; + uint32_t status; + uint32_t handle; + uint32_t payload_len; + uint8_t payload[0]; +}; + +struct trusty_ipc_wait_req { + uint64_t reserved; +}; + +struct trusty_ipc_connect_req { + uint64_t cookie; + uint64_t reserved; + uint8_t name[0]; +}; + +static size_t iovec_size(const struct trusty_ipc_iovec *iovs, size_t iovs_cnt) +{ + size_t i; + size_t cb = 0; + + trusty_assert(iovs); + + for (i = 0; i < iovs_cnt; i++) { + cb += iovs[i].len; + } + + return cb; +} + +static size_t iovec_to_buf(void *buf, size_t buf_len, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt) +{ + size_t i; + size_t buf_pos = 0; + + trusty_assert(iovs); + + for (i = 0; i < iovs_cnt; i++) { + size_t to_copy = (size_t)iovs[i].len; + + if (!to_copy) + continue; + + if (to_copy > buf_len) + to_copy = buf_len; + + trusty_memcpy((uint8_t *)buf + buf_pos, iovs[i].base, to_copy); + + buf_pos += to_copy; + buf_len -= to_copy; + + if (buf_len == 0) + break; + } + + return buf_pos; +} + +static size_t buf_to_iovec(const struct trusty_ipc_iovec *iovs, size_t iovs_cnt, + const void *buf, size_t buf_len) +{ + size_t i; + size_t copied = 0; + const uint8_t *buf_ptr = buf; + + trusty_assert(buf_ptr); + trusty_assert(iovs); + + if (iovs_cnt == 0 || buf_len == 0) + return 0; + + for (i = 0; i < iovs_cnt; i++) { + size_t to_copy = buf_len; + + if (to_copy > iovs[i].len) + to_copy = iovs[i].len; + + if (!to_copy) + continue; + + trusty_memcpy(iovs[i].base, buf_ptr, to_copy); + + copied += to_copy; + buf_ptr += to_copy; + buf_len -= to_copy; + + if (buf_len == 0) + break; + } + + return copied; +} + +static int check_response(struct trusty_ipc_dev *dev, + volatile struct trusty_ipc_cmd_hdr *hdr, uint16_t cmd) +{ + if (hdr->opcode != (cmd | QL_TIPC_DEV_RESP)) { + /* malformed response */ + trusty_error("%s: malformed response cmd: 0x%x\n", + __func__, hdr->opcode); + return TRUSTY_ERR_SECOS_ERR; + } + + if (hdr->status) { + /* secure OS responded with error: TODO need error code */ + trusty_error("%s: cmd 0x%x: status = %d\n", + __func__, hdr->opcode, hdr->status); + return TRUSTY_ERR_SECOS_ERR; + } + + return TRUSTY_ERR_NONE; +} + +int trusty_ipc_dev_create(struct trusty_ipc_dev **idev, + struct trusty_dev *tdev, + size_t shared_buf_size) +{ + int rc; + struct trusty_ipc_dev *dev; + + trusty_assert(idev); + trusty_assert(!(shared_buf_size % PAGE_SIZE)); + trusty_debug("%s: Create new Trusty IPC device (%zu)\n", __func__, + shared_buf_size); + + /* allocate device context */ + dev = trusty_calloc(1, sizeof(*dev)); + if (!dev) { + trusty_error("%s: failed to allocate Trusty IPC device\n", __func__); + return TRUSTY_ERR_NO_MEMORY; + } + dev->tdev = tdev; + + /* allocate shared buffer */ + dev->buf_size = shared_buf_size; + dev->buf_vaddr = trusty_alloc_pages(shared_buf_size / PAGE_SIZE); + if (!dev->buf_vaddr) { + trusty_error("%s: failed to allocate shared memory\n", __func__); + rc = TRUSTY_ERR_NO_MEMORY; + goto err_alloc_pages; + } + + /* Get memory attributes */ + rc = trusty_encode_page_info(&dev->buf_ns, dev->buf_vaddr); + if (rc != 0) { + trusty_error("%s: failed to get shared memory attributes\n", __func__); + rc = TRUSTY_ERR_GENERIC; + goto err_page_info; + } + /* call secure OS to register shared buffer */ + rc = trusty_dev_init_ipc(dev->tdev, &dev->buf_ns, dev->buf_size); + if (rc != 0) { + trusty_error("%s: failed (%d) to create Trusty IPC device\n", + __func__, rc); + rc = TRUSTY_ERR_SECOS_ERR; + goto err_create_sec_dev; + } + + trusty_debug("%s: new Trusty IPC device (%p)\n", __func__, dev); + + *idev = dev; + return TRUSTY_ERR_NONE; + +err_page_info: +err_create_sec_dev: + trusty_free_pages(dev->buf_vaddr, dev->buf_size / PAGE_SIZE); +err_alloc_pages: + trusty_free(dev); + return rc; +} + +void trusty_ipc_dev_shutdown(struct trusty_ipc_dev *dev) +{ + int rc; + trusty_assert(dev); + + trusty_debug("%s: shutting down Trusty IPC device (%p)\n", __func__, dev); + + /* shutdown Trusty IPC device */ + rc = trusty_dev_shutdown_ipc(dev->tdev, &dev->buf_ns, dev->buf_size); + trusty_assert(!rc); + if (rc != 0) { + trusty_error("%s: failed (%d) to shutdown Trusty IPC device\n", + __func__, rc); + } + trusty_free_pages(dev->buf_vaddr, dev->buf_size / PAGE_SIZE); + trusty_free(dev); +} + +int trusty_ipc_dev_connect(struct trusty_ipc_dev *dev, const char *port, + uint64_t cookie) +{ + int rc; + size_t port_len; + volatile struct trusty_ipc_cmd_hdr *cmd; + struct trusty_ipc_connect_req *req; + + trusty_assert(dev); + trusty_assert(port); + + trusty_debug("%s: connecting to '%s'\n", __func__, port); + + /* check port name length */ + port_len = trusty_strlen(port) + 1; + if (port_len > (dev->buf_size - sizeof(*cmd) + sizeof(*req))) { + /* it would not fit into buffer */ + trusty_error("%s: port name is too long (%zu)\n", __func__, port_len); + return TRUSTY_ERR_INVALID_ARGS; + } + + /* prepare command */ + cmd = dev->buf_vaddr; + trusty_memset((void *)cmd, 0, sizeof(*cmd)); + cmd->opcode = QL_TIPC_DEV_CONNECT; + + /* prepare payload */ + req = (struct trusty_ipc_connect_req *)cmd->payload; + trusty_memset((void *)req, 0, sizeof(*req)); + req->cookie = cookie; + trusty_strcpy((char *)req->name, port); + cmd->payload_len = sizeof(*req) + port_len; + + /* call secure os */ + rc = trusty_dev_exec_ipc(dev->tdev, + &dev->buf_ns, sizeof(*cmd) + cmd->payload_len); + if (rc) { + /* secure OS returned an error */ + trusty_error("%s: secure OS returned (%d)\n", __func__, rc); + return TRUSTY_ERR_SECOS_ERR; + } + + rc = check_response(dev, cmd, QL_TIPC_DEV_CONNECT); + if (rc) { + trusty_error("%s: connect cmd failed (%d)\n", __func__, rc); + return rc; + } + + /* success */ + return cmd->handle; +} + +int trusty_ipc_dev_close(struct trusty_ipc_dev *dev, handle_t handle) +{ + int rc; + volatile struct trusty_ipc_cmd_hdr *cmd; + + trusty_assert(dev); + + trusty_debug("%s: chan %d: closing\n", __func__, handle); + + /* prepare command */ + cmd = dev->buf_vaddr; + trusty_memset((void *)cmd, 0, sizeof(*cmd)); + cmd->opcode = QL_TIPC_DEV_DISCONNECT; + cmd->handle = handle; + /* no payload */ + + /* call into secure os */ + rc = trusty_dev_exec_ipc(dev->tdev, + &dev->buf_ns, sizeof(*cmd) + cmd->payload_len); + if (rc) { + trusty_error("%s: secure OS returned (%d)\n", __func__, rc); + return TRUSTY_ERR_SECOS_ERR; + } + + rc = check_response(dev, cmd, QL_TIPC_DEV_DISCONNECT); + if (rc) { + trusty_error("%s: disconnect cmd failed (%d)\n", __func__, rc); + return rc; + } + + trusty_debug("%s: chan %d: closed\n", __func__, handle); + + return TRUSTY_ERR_NONE; +} + +int trusty_ipc_dev_get_event(struct trusty_ipc_dev *dev, handle_t chan, + struct trusty_ipc_event *event) +{ + int rc; + volatile struct trusty_ipc_cmd_hdr *cmd; + + trusty_assert(dev); + trusty_assert(event); + + /* prepare command */ + cmd = dev->buf_vaddr; + trusty_memset((void *)cmd, 0, sizeof(*cmd)); + cmd->opcode = QL_TIPC_DEV_GET_EVENT; + cmd->handle = chan; + + /* prepare payload */ + trusty_memset((void *)cmd->payload, 0, sizeof(struct trusty_ipc_wait_req)); + cmd->payload_len = sizeof(struct trusty_ipc_wait_req); + + /* call into secure os */ + rc = trusty_dev_exec_ipc(dev->tdev, + &dev->buf_ns, sizeof(*cmd) + cmd->payload_len); + if (rc) { + trusty_error("%s: secure OS returned (%d)\n", __func__, rc); + return TRUSTY_ERR_SECOS_ERR; + } + + rc = check_response(dev, cmd, QL_TIPC_DEV_GET_EVENT); + if (rc) { + trusty_error("%s: get event cmd failed (%d)\n", __func__, rc); + return rc; + } + + if ((size_t)cmd->payload_len < sizeof(*event)) { + trusty_error("%s: invalid response length (%zd)\n", + __func__, (size_t)cmd->payload_len); + return TRUSTY_ERR_SECOS_ERR; + } + + /* copy out event */ + trusty_memcpy(event, (const void *)cmd->payload, sizeof(*event)); + return TRUSTY_ERR_NONE; +} + +int trusty_ipc_dev_send(struct trusty_ipc_dev *dev, handle_t chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt) +{ + int rc; + size_t msg_size; + volatile struct trusty_ipc_cmd_hdr *cmd; + + trusty_assert(dev); + /* calc message length */ + msg_size = iovec_size(iovs, iovs_cnt); + if (msg_size > dev->buf_size - sizeof(*cmd)) { + /* msg is too big to fit provided buffer */ + trusty_error("%s: chan %d: msg is too long (%zu)\n", __func__, + chan, msg_size); + return TRUSTY_ERR_MSG_TOO_BIG; + } + + /* prepare command */ + cmd = dev->buf_vaddr; + trusty_memset((void *)cmd, 0, sizeof(*cmd)); + cmd->opcode = QL_TIPC_DEV_SEND; + cmd->handle = chan; + + /* copy in message data */ + cmd->payload_len = (uint32_t)msg_size; + msg_size = iovec_to_buf(dev->buf_vaddr + sizeof(*cmd), dev->buf_size - sizeof(*cmd), + iovs, iovs_cnt); + trusty_assert(msg_size == (size_t)cmd->payload_len); + + /* call into secure os */ + rc = trusty_dev_exec_ipc(dev->tdev, + &dev->buf_ns, sizeof(*cmd) + cmd->payload_len); + if (rc < 0) { + trusty_error("%s: secure OS returned (%d)\n", __func__, rc); + return TRUSTY_ERR_SECOS_ERR; + } + + rc = check_response(dev, cmd, QL_TIPC_DEV_SEND); + if (rc) { + trusty_error("%s: send msg failed (%d)\n", __func__, rc); + } + + return rc; +} + + +int trusty_ipc_dev_recv(struct trusty_ipc_dev *dev, handle_t chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt) +{ + int rc; + size_t copied; + volatile struct trusty_ipc_cmd_hdr *cmd; + + trusty_assert(dev); + + /* prepare command */ + cmd = dev->buf_vaddr; + trusty_memset((void *)cmd, 0, sizeof(*cmd)); + cmd->opcode = QL_TIPC_DEV_RECV; + cmd->handle = chan; + /* no payload */ + + /* call into secure os */ + rc = trusty_dev_exec_ipc(dev->tdev, + &dev->buf_ns, sizeof(*cmd) + cmd->payload_len); + if (rc < 0) { + trusty_error("%s: secure OS returned (%d)\n", __func__, rc); + return TRUSTY_ERR_SECOS_ERR; + } + + rc = check_response(dev, cmd, QL_TIPC_DEV_RECV); + if (rc) { + trusty_error("%s: recv cmd failed (%d)\n", __func__, rc); + return rc; + } + + /* copy data out to proper destination */ + copied = buf_to_iovec(iovs, iovs_cnt, + (const void *)cmd->payload, cmd->payload_len); + if (copied != (size_t)cmd->payload_len) { + /* msg is too big to fit provided buffer */ + trusty_error("%s: chan %d: buffer too small (%zu vs. %zu)\n", + __func__, chan, copied, (size_t)cmd->payload_len); + return TRUSTY_ERR_MSG_TOO_BIG; + } + + return (int)copied; +} + +void trusty_ipc_dev_idle(struct trusty_ipc_dev *dev) +{ + trusty_idle(dev->tdev); +} + diff --git a/lib/trusty/ql-tipc/keymaster.c b/lib/trusty/ql-tipc/keymaster.c new file mode 100644 index 00000000000..eaa43e38744 --- /dev/null +++ b/lib/trusty/ql-tipc/keymaster.c @@ -0,0 +1,482 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#define LOCAL_LOG 0 + +static struct trusty_ipc_chan km_chan; +static bool initialized = false; +static int trusty_km_version = 2; +static const size_t kMaxCaRequestSize = 10000; +static const size_t kMaxSendSize = 4000; +static const size_t kUuidSize = 32; + +#ifndef MIN +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#ifndef NELEMS +#define NELEMS(x) (sizeof(x) / sizeof((x)[0])) +#endif + +static int km_send_request(uint32_t cmd, const void *req, size_t req_len) +{ + struct keymaster_message header = { .cmd = cmd }; + int num_iovecs = req ? 2 : 1; + + struct trusty_ipc_iovec req_iovs[2] = { + { .base = &header, .len = sizeof(header) }, + { .base = (void*)req, .len = req_len }, + }; + + return trusty_ipc_send(&km_chan, req_iovs, num_iovecs, true); +} + +/* Checks that the command opcode in |header| matches |ex-ected_cmd|. Checks + * that |tipc_result| is a valid response size. Returns negative on error. + */ +static int check_response_error(uint32_t expected_cmd, + struct keymaster_message header, + int32_t tipc_result) +{ + if (tipc_result < 0) { + trusty_error("failed (%d) to recv response\n", tipc_result); + return tipc_result; + } + if ((size_t) tipc_result < sizeof(struct keymaster_message)) { + trusty_error("invalid response size (%d)\n", tipc_result); + return TRUSTY_ERR_GENERIC; + } + if ((header.cmd & ~(KEYMASTER_STOP_BIT)) != + (expected_cmd | KEYMASTER_RESP_BIT)) { + trusty_error("malformed response\n"); + return TRUSTY_ERR_GENERIC; + } + return tipc_result; +} + +/* Reads the raw response to |resp| up to a maximum size of |resp_len|. Format + * of each message frame read from the secure side: + * + * command header : 4 bytes + * opaque bytes : MAX(KEYMASTER_MAX_BUFFER_LENGTH, x) bytes + * + * The individual message frames from the secure side are reassembled + * into |resp|, stripping each frame's command header. Returns the number + * of bytes written to |resp| on success, negative on error. + */ +static int km_read_raw_response(uint32_t cmd, void *resp, size_t resp_len) +{ + struct keymaster_message header = { .cmd = cmd }; + int rc = TRUSTY_ERR_GENERIC; + size_t max_resp_len = resp_len; + struct trusty_ipc_iovec resp_iovs[2] = { + { .base = &header, .len = sizeof(header) }, + { .base = resp, .len = MIN(KEYMASTER_MAX_BUFFER_LENGTH, max_resp_len) } + }; + + if (!resp) { + return TRUSTY_ERR_GENERIC; + } + resp_len = 0; + while (true) { + resp_iovs[1].base = (uint8_t*)resp + resp_len; + resp_iovs[1].len = MIN(KEYMASTER_MAX_BUFFER_LENGTH, + (int)max_resp_len - (int)resp_len); + + rc = trusty_ipc_recv(&km_chan, resp_iovs, NELEMS(resp_iovs), true); + rc = check_response_error(cmd, header, rc); + if (rc < 0) { + return rc; + } + resp_len += ((size_t)rc - sizeof(struct keymaster_message)); + if (header.cmd & KEYMASTER_STOP_BIT || resp_len >= max_resp_len) { + break; + } + } + + return resp_len; +} + +/* Reads a Keymaster Response message with a sized buffer. The format + * of the response is as follows: + * + * command header : 4 bytes + * error : 4 bytes + * data length : 4 bytes + * data : |data length| bytes + * + * On success, |error|, |resp_data|, and |resp_data_len| are filled + * successfully. Returns a trusty_err. + */ +static int km_read_data_response(uint32_t cmd, int32_t *error, + uint8_t* resp_data, uint32_t* resp_data_len) +{ + struct keymaster_message header = { .cmd = cmd }; + int rc = TRUSTY_ERR_GENERIC; + size_t max_resp_len = *resp_data_len; + uint32_t resp_data_bytes = 0; + /* On the first read, recv the keymaster_message header, error code, + * response data length, and response data. On subsequent iterations, + * only recv the keymaster_message header and response data. + */ + struct trusty_ipc_iovec resp_iovs[4] = { + { .base = &header, .len = sizeof(header) }, + { .base = error, .len = sizeof(int32_t) }, + { .base = resp_data_len, .len = sizeof(uint32_t) }, + { .base = resp_data, .len = MIN(KEYMASTER_MAX_BUFFER_LENGTH, max_resp_len) } + }; + + rc = trusty_ipc_recv(&km_chan, resp_iovs, NELEMS(resp_iovs), true); + rc = check_response_error(cmd, header, rc); + if (rc < 0) { + return rc; + } + /* resp_data_bytes does not include the error or response data length */ + resp_data_bytes += ((size_t)rc - sizeof(struct keymaster_message) - + 2 * sizeof(uint32_t)); + if (header.cmd & KEYMASTER_STOP_BIT) { + return TRUSTY_ERR_NONE; + } + + /* Read the remaining response data */ + uint8_t* resp_data_start = resp_data + resp_data_bytes; + size_t resp_data_remaining = *resp_data_len - resp_data_bytes; + rc = km_read_raw_response(cmd, resp_data_start, resp_data_remaining); + if (rc < 0) { + return rc; + } + resp_data_bytes += rc; + if (*resp_data_len != resp_data_bytes) { + return TRUSTY_ERR_GENERIC; + } + return TRUSTY_ERR_NONE; +} + +/** + * Convenience method to send a request to the secure side, handle rpmb + * operations, and receive the response. If |resp_data| is not NULL, the + * caller expects an additional data buffer to be returned from the secure + * side. + */ +static int km_do_tipc(uint32_t cmd, void* req, uint32_t req_len, + void* resp_data, uint32_t* resp_data_len) +{ + int rc = TRUSTY_ERR_GENERIC; + struct km_no_response resp_header; + + rc = km_send_request(cmd, req, req_len); + if (rc < 0) { + trusty_error("%s: failed (%d) to send km request\n", __func__, rc); + return rc; + } + + if (!resp_data) { + rc = km_read_raw_response(cmd, &resp_header, sizeof(resp_header)); + } else { + rc = km_read_data_response(cmd, &resp_header.error, resp_data, + resp_data_len); + } + + if (rc < 0) { + trusty_error("%s: failed (%d) to read km response\n", __func__, rc); + return rc; + } + if (resp_header.error != KM_ERROR_OK) { + trusty_error("%s: keymaster returned error (%d)\n", __func__, + resp_header.error); + return TRUSTY_ERR_GENERIC; + } + return TRUSTY_ERR_NONE; +} + +static int32_t MessageVersion(uint8_t major_ver, uint8_t minor_ver, + uint8_t subminor_ver) { + int32_t message_version = -1; + switch (major_ver) { + case 0: + message_version = 0; + break; + case 1: + switch (minor_ver) { + case 0: + message_version = 1; + break; + case 1: + message_version = 2; + break; + } + break; + case 2: + message_version = 3; + break; + } + return message_version; +} + +static int km_get_version(int32_t *version) +{ + int rc = TRUSTY_ERR_GENERIC; + struct km_get_version_resp resp; + + rc = km_send_request(KM_GET_VERSION, NULL, 0); + if (rc < 0) { + trusty_error("failed to send km version request", rc); + return rc; + } + + rc = km_read_raw_response(KM_GET_VERSION, &resp, sizeof(resp)); + if (rc < 0) { + trusty_error("%s: failed (%d) to read km response\n", __func__, rc); + return rc; + } + + *version = MessageVersion(resp.major_ver, resp.minor_ver, + resp.subminor_ver); + return TRUSTY_ERR_NONE; +} + +int km_tipc_init(struct trusty_ipc_dev *dev) +{ + int rc = TRUSTY_ERR_GENERIC; + + trusty_assert(dev); + + trusty_ipc_chan_init(&km_chan, dev); + trusty_debug("Connecting to Keymaster service\n"); + + /* connect to km service and wait for connect to complete */ + rc = trusty_ipc_connect(&km_chan, KEYMASTER_PORT, true); + if (rc < 0) { + trusty_error("failed (%d) to connect to '%s'\n", rc, KEYMASTER_PORT); + return rc; + } + + int32_t version = -1; + rc = km_get_version(&version); + if (rc < 0) { + trusty_error("failed (%d) to get keymaster version\n", rc); + return rc; + } + if (version < trusty_km_version) { + trusty_error("keymaster version mismatch. Expected %d, received %d\n", + trusty_km_version, version); + return TRUSTY_ERR_GENERIC; + } + + /* mark as initialized */ + initialized = true; + + return TRUSTY_ERR_NONE; +} + +void km_tipc_shutdown(struct trusty_ipc_dev *dev) +{ + if (!initialized) + return; + /* close channel */ + trusty_ipc_close(&km_chan); + + initialized = false; +} + +int trusty_set_boot_params(uint32_t os_version, uint32_t os_patchlevel, + keymaster_verified_boot_t verified_boot_state, + bool device_locked, + const uint8_t *verified_boot_key_hash, + uint32_t verified_boot_key_hash_size, + const uint8_t *verified_boot_hash, + uint32_t verified_boot_hash_size) +{ + if (!initialized) { + trusty_error("Keymaster TIPC client not initialized!\n"); + return -1; + } + struct km_boot_params params = { + .os_version = os_version, + .os_patchlevel = os_patchlevel, + .device_locked = (uint32_t)device_locked, + .verified_boot_state = (uint32_t)verified_boot_state, + .verified_boot_key_hash_size = verified_boot_key_hash_size, + .verified_boot_key_hash = verified_boot_key_hash, + .verified_boot_hash_size = verified_boot_hash_size, + .verified_boot_hash = verified_boot_hash + }; + uint8_t *req = NULL; + uint32_t req_size = 0; + int rc = km_boot_params_serialize(¶ms, &req, &req_size); + + if (rc < 0) { + trusty_error("failed (%d) to serialize request\n", rc); + goto end; + } + rc = km_do_tipc(KM_SET_BOOT_PARAMS, req, req_size, NULL, NULL); + +end: + if (req) { + trusty_free(req); + } + return rc; +} + +static int trusty_send_attestation_data(uint32_t cmd, const uint8_t *data, + uint32_t data_size, + keymaster_algorithm_t algorithm) +{ + struct km_attestation_data attestation_data = { + .algorithm = (uint32_t)algorithm, + .data_size = data_size, + .data = data, + }; + uint8_t *req = NULL; + uint32_t req_size = 0; + int rc = km_attestation_data_serialize(&attestation_data, &req, &req_size); + + if (rc < 0) { + trusty_error("failed (%d) to serialize request\n", rc); + goto end; + } + rc = km_do_tipc(cmd, req, req_size, NULL, NULL); + +end: + if (req) { + trusty_free(req); + } + return rc; +} + +static int trusty_send_raw_buffer(uint32_t cmd, const uint8_t *req_data, + uint32_t req_data_size, uint8_t *resp_data, + uint32_t *resp_data_size) +{ + struct km_raw_buffer buf = { + .data_size = req_data_size, + .data = req_data, + }; + uint8_t *req = NULL; + uint32_t req_size = 0; + int rc = km_raw_buffer_serialize(&buf, &req, &req_size); + if (rc < 0) { + trusty_error("failed (%d) to serialize request\n", rc); + goto end; + } + rc = km_do_tipc(cmd, req, req_size, resp_data, resp_data_size); + +end: + if (req) { + trusty_free(req); + } + return rc; +} + +int trusty_set_attestation_key(const uint8_t *key, uint32_t key_size, + keymaster_algorithm_t algorithm) +{ + return trusty_send_attestation_data(KM_SET_ATTESTATION_KEY, key, key_size, + algorithm); +} + +int trusty_append_attestation_cert_chain(const uint8_t *cert, + uint32_t cert_size, + keymaster_algorithm_t algorithm) +{ + return trusty_send_attestation_data(KM_APPEND_ATTESTATION_CERT_CHAIN, + cert, cert_size, algorithm); +} + +int trusty_atap_get_ca_request(const uint8_t *operation_start, + uint32_t operation_start_size, + uint8_t **ca_request_p, + uint32_t *ca_request_size_p) +{ + *ca_request_p = trusty_calloc(1, kMaxCaRequestSize); + if (!*ca_request_p) { + return TRUSTY_ERR_NO_MEMORY; + } + *ca_request_size_p = kMaxCaRequestSize; + int rc = trusty_send_raw_buffer(KM_ATAP_GET_CA_REQUEST, operation_start, + operation_start_size, *ca_request_p, + ca_request_size_p); + if (rc != TRUSTY_ERR_NONE) { + trusty_free(*ca_request_p); + } + return rc; +} + +int trusty_atap_set_ca_response(const uint8_t *ca_response, + uint32_t ca_response_size) +{ + struct km_set_ca_response_begin_req begin_req; + int rc = TRUSTY_ERR_GENERIC; + uint32_t bytes_sent = 0, send_size = 0; + + /* Tell the Trusty Keymaster TA the size of CA Response message */ + begin_req.ca_response_size = ca_response_size; + rc = km_do_tipc(KM_ATAP_SET_CA_RESPONSE_BEGIN, &begin_req, + sizeof(begin_req), NULL, NULL); + if (rc != TRUSTY_ERR_NONE) { + return rc; + } + + /* Send the CA Response message in chunks */ + while (bytes_sent < ca_response_size) { + send_size = MIN(kMaxSendSize, ca_response_size - bytes_sent); + rc = trusty_send_raw_buffer(KM_ATAP_SET_CA_RESPONSE_UPDATE, + ca_response + bytes_sent, send_size, + NULL, NULL); + if (rc != TRUSTY_ERR_NONE) { + return rc; + } + bytes_sent += send_size; + } + + /* Tell Trusty Keymaster to parse the CA Response message */ + return km_do_tipc(KM_ATAP_SET_CA_RESPONSE_FINISH, NULL, 0, NULL, NULL); +} + + +int trusty_atap_read_uuid_str(char **uuid_p) +{ + *uuid_p = (char*) trusty_calloc(1, kUuidSize); + + uint32_t response_size = kUuidSize; + int rc = km_do_tipc(KM_ATAP_READ_UUID, NULL, 0, *uuid_p, + &response_size); + if (rc < 0) { + trusty_error("failed to read uuid: %d\n", rc); + trusty_free(*uuid_p); + return rc; + } + if (response_size != kUuidSize) { + trusty_error("keymaster returned wrong uuid size: %d\n", response_size); + trusty_free(*uuid_p); + rc = TRUSTY_ERR_GENERIC; + } + return rc; +} diff --git a/lib/trusty/ql-tipc/keymaster_serializable.c b/lib/trusty/ql-tipc/keymaster_serializable.c new file mode 100644 index 00000000000..65bcca05452 --- /dev/null +++ b/lib/trusty/ql-tipc/keymaster_serializable.c @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include + +uint8_t *append_to_buf(uint8_t *buf, const void *data, size_t data_len) +{ + if (data && data_len) { + trusty_memcpy(buf, data, data_len); + } + return buf + data_len; +} + +uint8_t *append_uint32_to_buf(uint8_t *buf, uint32_t val) +{ + return append_to_buf(buf, &val, sizeof(val)); +} + +uint8_t *append_sized_buf_to_buf(uint8_t *buf, const uint8_t *data, + uint32_t data_len) +{ + buf = append_uint32_to_buf(buf, data_len); + return append_to_buf(buf, data, data_len); +} + +int km_boot_params_serialize(const struct km_boot_params *params, uint8_t** out, + uint32_t *out_size) +{ + uint8_t *tmp; + + if (!out || !params || !out_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + *out_size = (sizeof(params->os_version) + sizeof(params->os_patchlevel) + + sizeof(params->device_locked) + + sizeof(params->verified_boot_state) + + sizeof(params->verified_boot_key_hash_size) + + sizeof(params->verified_boot_hash_size) + + params->verified_boot_key_hash_size + + params->verified_boot_hash_size); + *out = trusty_calloc(*out_size, 1); + if (!*out) { + return TRUSTY_ERR_NO_MEMORY; + } + + tmp = append_uint32_to_buf(*out, params->os_version); + tmp = append_uint32_to_buf(tmp, params->os_patchlevel); + tmp = append_uint32_to_buf(tmp, params->device_locked); + tmp = append_uint32_to_buf(tmp, params->verified_boot_state); + tmp = append_sized_buf_to_buf(tmp, params->verified_boot_key_hash, + params->verified_boot_key_hash_size); + tmp = append_sized_buf_to_buf(tmp, params->verified_boot_hash, + params->verified_boot_hash_size); + + return TRUSTY_ERR_NONE; +} + +int km_attestation_data_serialize(const struct km_attestation_data *data, + uint8_t** out, uint32_t *out_size) +{ + uint8_t *tmp; + + if (!out || !data || !out_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + *out_size = (sizeof(data->algorithm) + sizeof(data->data_size) + + data->data_size); + *out = trusty_calloc(*out_size, 1); + if (!*out) { + return TRUSTY_ERR_NO_MEMORY; + } + + tmp = append_uint32_to_buf(*out, data->algorithm); + tmp = append_sized_buf_to_buf(tmp, data->data, data->data_size); + + return TRUSTY_ERR_NONE; +} + +int km_raw_buffer_serialize(const struct km_raw_buffer *buf, uint8_t** out, + uint32_t *out_size) +{ + if (!out || !buf || !out_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + *out_size = sizeof(buf->data_size) + buf->data_size; + *out = trusty_calloc(*out_size, 1); + if (!*out) { + return TRUSTY_ERR_NO_MEMORY; + } + append_sized_buf_to_buf(*out, buf->data, buf->data_size); + + return TRUSTY_ERR_NONE; +} diff --git a/lib/trusty/ql-tipc/libtipc.c b/lib/trusty/ql-tipc/libtipc.c new file mode 100644 index 00000000000..30d4bbf854e --- /dev/null +++ b/lib/trusty/ql-tipc/libtipc.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * Copyright NXP 2018 + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOCAL_LOG 0 + +typedef uintptr_t vaddr_t; + +static struct trusty_ipc_dev *_ipc_dev; +static struct trusty_dev _tdev; /* There should only be one trusty device */ +static void *rpmb_ctx; +#ifndef CONFIG_AVB_ATX +bool rpmbkey_is_set(void); +#endif + +void rpmb_storage_put_ctx(void *dev); +void trusty_ipc_shutdown(void) +{ + (void)rpmb_storage_proxy_shutdown(_ipc_dev); + (void)rpmb_storage_put_ctx(rpmb_ctx); + + (void)avb_tipc_shutdown(_ipc_dev); + (void)km_tipc_shutdown(_ipc_dev); + +#ifndef CONFIG_AVB_ATX + (void)hwcrypto_tipc_shutdown(_ipc_dev); +#endif + + /* shutdown Trusty IPC device */ + (void)trusty_ipc_dev_shutdown(_ipc_dev); + + /* shutdown Trusty device */ + (void)trusty_dev_shutdown(&_tdev); +} + +int trusty_ipc_init(void) +{ + int rc; + /* init Trusty device */ + trusty_info("Initializing Trusty device\n"); + rc = trusty_dev_init(&_tdev, NULL); + if (rc != 0) { + trusty_error("Initializing Trusty device failed (%d)\n", rc); + return rc; + } + + /* create Trusty IPC device */ + trusty_info("Initializing Trusty IPC device\n"); + rc = trusty_ipc_dev_create(&_ipc_dev, &_tdev, PAGE_SIZE); + if (rc != 0) { + trusty_error("Initializing Trusty IPC device failed (%d)\n", rc); + return rc; + } + + /* get storage rpmb */ + rpmb_ctx = rpmb_storage_get_ctx(); + + /* start secure storage proxy service */ + trusty_info("Initializing RPMB storage proxy service\n"); + rc = rpmb_storage_proxy_init(_ipc_dev, rpmb_ctx); + if (rc != 0) { + trusty_error("Initlializing RPMB storage proxy service failed (%d)\n", + rc); +#ifndef CONFIG_AVB_ATX + /* check if rpmb key has been fused. */ + if(rpmbkey_is_set()) { + /* Go to hang if the key has been destroyed. */ + trusty_error("RPMB key was destroyed!\n"); + hang(); + } +#else + return rc; +#endif + } else { + /* secure storage service init ok, use trusty backed keystore */ + env_set("keystore", "trusty"); + + trusty_info("Initializing Trusty AVB client\n"); + rc = avb_tipc_init(_ipc_dev); + if (rc != 0) { + trusty_error("Initlializing Trusty AVB client failed (%d)\n", rc); + return rc; + } + + trusty_info("Initializing Trusty Keymaster client\n"); + rc = km_tipc_init(_ipc_dev); + if (rc != 0) { + trusty_error("Initlializing Trusty Keymaster client failed (%d)\n", rc); + return rc; + } + } + +#ifndef CONFIG_AVB_ATX + trusty_info("Initializing Trusty Hardware Crypto client\n"); + rc = hwcrypto_tipc_init(_ipc_dev); + if (rc != 0) { + trusty_error("Initlializing Trusty Keymaster client failed (%d)\n", rc); + return rc; + } +#endif + + return TRUSTY_ERR_NONE; +} diff --git a/lib/trusty/ql-tipc/rpmb_proxy.c b/lib/trusty/ql-tipc/rpmb_proxy.c new file mode 100644 index 00000000000..2d5ca94f49d --- /dev/null +++ b/lib/trusty/ql-tipc/rpmb_proxy.c @@ -0,0 +1,332 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include + +#define LOCAL_LOG 0 + +static bool initialized; +/* Address of rpmb device */ +static void *proxy_rpmb; +struct trusty_ipc_chan proxy_chan; + +struct storage_msg req_msg; +static uint8_t req_buf[4096]; +static uint8_t read_buf[4096]; + +/* + * Read RPMB request from storage service. Writes message to @msg + * and @req. + * + * @chan: proxy ipc channel + * @msg: address of storage message header + * @req: address of storage message request + * @req_len: length of req in bytes + */ +static int proxy_read_request(struct trusty_ipc_chan *chan, + struct storage_msg *msg, void *req, + size_t req_len) +{ + int rc; + + struct trusty_ipc_iovec req_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = req, .len = req_len }, + }; + rc = trusty_ipc_recv(chan, req_iovs, 2, false); + if (rc < 0) { + /* recv message failed */ + trusty_error("%s: failed (%d) to recv request\n", __func__, rc); + return rc; + } + + if ((size_t)rc < sizeof(*msg)) { + /* malformed message */ + trusty_error("%s: malformed request (%zu)\n", __func__, (size_t)rc); + return TRUSTY_ERR_GENERIC; + } + + return rc - sizeof(*msg); /* return payload size */ +} + +/* + * Send RPMB response to storage service + * + * @chan: proxy ipc channel + * @msg: address of storage message header + * @resp: address of storage message response + * @resp_len: length of resp in bytes + */ +static int proxy_send_response(struct trusty_ipc_chan *chan, + struct storage_msg *msg, void *resp, + size_t resp_len) +{ + struct trusty_ipc_iovec resp_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = resp, .len = resp_len } + }; + + msg->cmd |= STORAGE_RESP_BIT; + return trusty_ipc_send(chan, resp_iovs, resp ? 2 : 1, false); +} + +/* + * Executes the RPMB request at @r, sends response to storage service. + * + * @chan: proxy ipc channel + * @msg: address of storage message header + * @r: address of storage message request + * @req_len: length of resp in bytes + */ +static int proxy_handle_rpmb(struct trusty_ipc_chan *chan, + struct storage_msg *msg, const void *r, + size_t req_len) +{ + int rc; + size_t exp_len; + const void *write_data = NULL; + const void *rel_write_data = NULL; + const struct storage_rpmb_send_req *req = r; + + if (req_len < sizeof(req)) { + msg->result = STORAGE_ERR_NOT_VALID; + goto err_response; + } + + exp_len = sizeof(*req) + req->reliable_write_size + req->write_size; + if (req_len != exp_len) { + trusty_error( + "%s: malformed rpmb request: invalid length (%zu != %zu)\n", + __func__, req_len, exp_len); + msg->result = STORAGE_ERR_NOT_VALID; + goto err_response; + } + + if (req->reliable_write_size) { + if ((req->reliable_write_size % MMC_BLOCK_SIZE) != 0) { + trusty_error("%s: invalid reliable write size %u\n", __func__, + req->reliable_write_size); + msg->result = STORAGE_ERR_NOT_VALID; + goto err_response; + } + rel_write_data = req->payload; + } + + if (req->write_size) { + if ((req->write_size % MMC_BLOCK_SIZE) != 0) { + trusty_error("%: invalid write size %u\n", __func__, + req->write_size); + msg->result = STORAGE_ERR_NOT_VALID; + goto err_response; + } + write_data = req->payload + req->reliable_write_size; + } + + if (req->read_size) { + if (req->read_size % MMC_BLOCK_SIZE != 0 || + req->read_size > sizeof(read_buf)) { + trusty_error("%s: invalid read size %u\n", __func__, + req->read_size); + msg->result = STORAGE_ERR_NOT_VALID; + goto err_response; + } + } + + /* execute rpmb command */ + rc = rpmb_storage_send(proxy_rpmb, + rel_write_data, req->reliable_write_size, + write_data, req->write_size, + read_buf, req->read_size); + if (rc) { + trusty_error("%s: rpmb_storage_send failed: %d\n", __func__, rc); + msg->result = STORAGE_ERR_GENERIC; + goto err_response; + } + + if (msg->flags & STORAGE_MSG_FLAG_POST_COMMIT) { + /* + * Nothing todo for post msg commit request as MMC_IOC_MULTI_CMD + * is fully synchronous in this implementation. + */ + } + + msg->result = STORAGE_NO_ERROR; + return proxy_send_response(chan, msg, read_buf, req->read_size); + +err_response: + return proxy_send_response(chan, msg, NULL, 0); +} + +/* + * Handles storage request. + * + * @chan: proxy ipc channel + * @msg: address of storage message header + * @req: address of storage message request + * @req_len: length of resp in bytes + */ +static int proxy_handle_req(struct trusty_ipc_chan *chan, + struct storage_msg *msg, const void *req, + size_t req_len) +{ + int rc; + + if (msg->flags & STORAGE_MSG_FLAG_PRE_COMMIT) { + /* nothing to do */ + } + + switch (msg->cmd) { + case STORAGE_RPMB_SEND: + rc = proxy_handle_rpmb(chan, msg, req, req_len); + break; + + case STORAGE_FILE_DELETE: + case STORAGE_FILE_OPEN: + case STORAGE_FILE_CLOSE: + case STORAGE_FILE_WRITE: + case STORAGE_FILE_READ: + case STORAGE_FILE_GET_SIZE: + case STORAGE_FILE_SET_SIZE: + /* Bulk filesystem is not supported */ + msg->result = STORAGE_ERR_UNIMPLEMENTED; + rc = proxy_send_response(chan, msg, NULL, 0); + break; + + default: + msg->result = STORAGE_ERR_UNIMPLEMENTED; + rc = proxy_send_response(chan, msg, NULL, 0); + } + + return rc; +} + +/* + * Invalidates @chan on hangup event + * + * @chan: proxy ipc channel + */ +static int proxy_on_disconnect(struct trusty_ipc_chan *chan) +{ + trusty_assert(chan); + + trusty_debug("%s: closed by peer\n", __func__); + chan->handle = INVALID_IPC_HANDLE; + return TRUSTY_EVENT_HANDLED; +} + +/* + * Handles received storage message on message event + * + * @chan: proxy ipc channel + */ +static int proxy_on_message(struct trusty_ipc_chan *chan) +{ + int rc; + + trusty_assert(chan); + + /* read request */ + rc = proxy_read_request(chan, &req_msg, req_buf, sizeof(req_buf)); + if (rc < 0) { + trusty_error("%s: failed (%d) to read request\n", __func__, rc); + trusty_ipc_close(chan); + return rc; + } + + /* handle it and send reply */ + rc = proxy_handle_req(chan, &req_msg, req_buf, rc); + if (rc < 0) { + trusty_error("%s: failed (%d) to handle request\n", __func__, rc); + trusty_ipc_close(chan); + return rc; + } + + return TRUSTY_EVENT_HANDLED; +} + +static struct trusty_ipc_ops proxy_ops = { + .on_message = proxy_on_message, + .on_disconnect = proxy_on_disconnect, +}; + +/* + * Initialize RPMB storage proxy + */ +int rpmb_storage_proxy_init(struct trusty_ipc_dev *dev, void *rpmb_dev) +{ + int rc; + + trusty_assert(dev); + trusty_assert(!initialized); + + /* attach rpmb device */ + proxy_rpmb = rpmb_dev; + + /* init ipc channel */ + trusty_ipc_chan_init(&proxy_chan, dev); + + /* connect to proxy service and wait for connect to complete */ + rc = trusty_ipc_connect(&proxy_chan, STORAGE_DISK_PROXY_PORT, true); + if (rc < 0) { + trusty_error("%s: failed (%d) to connect to '%s'\n", __func__, rc, + STORAGE_DISK_PROXY_PORT); + return rc; + } + + /* override default ops */ + proxy_chan.ops = &proxy_ops; + + do { + /* Check for RPMB events */ + rc = trusty_ipc_poll_for_event(proxy_chan.dev); + if (rc < 0) { + trusty_error("%s: failed (%d) to get rpmb event\n", __func__, rc); + return rc; + } + + if (proxy_chan.handle == INVALID_IPC_HANDLE) { + trusty_error("%s: unexpected proxy channel close\n", __func__); + return TRUSTY_ERR_CHANNEL_CLOSED; + } + } + while (rc != TRUSTY_EVENT_NONE); + + /* mark as initialized */ + initialized = true; + + return TRUSTY_ERR_NONE; +} + +void rpmb_storage_proxy_shutdown(struct trusty_ipc_dev *dev) +{ + trusty_assert(initialized); + + /* close channel */ + trusty_ipc_close(&proxy_chan); + + initialized = false; +} diff --git a/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c b/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c new file mode 100644 index 00000000000..934286cb696 --- /dev/null +++ b/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include + +#include +#include +#include + +void *rpmb_storage_get_ctx(void) +{ + /* Unused for U-boot */ + return NULL; +} + +void rpmb_storage_put_ctx(void *dev) +{ +} + +int rpmb_storage_send(void *rpmb_dev, const void *rel_write_data, + size_t rel_write_size, const void *write_data, + size_t write_size, void *read_buf, size_t read_size) +{ + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_rel_write_data, rel_write_size); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_write_data, write_size); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_read_data, read_size); + int ret = TRUSTY_ERR_NONE; + struct mmc *mmc = find_mmc_device(mmc_get_env_dev()); + if (!mmc) { + trusty_error("failed to get mmc device.\n"); + return -1; + } + struct blk_desc *desc = mmc_get_blk_desc(mmc); + if (!desc) { + trusty_error("failed to get mmc desc.\n"); + return -1; + } + char original_part = desc->hwpart; + + /* Switch to RPMB partition */ + if (desc->hwpart != MMC_PART_RPMB) { + ret = mmc_switch_part(mmc, MMC_PART_RPMB); + if (ret) { + trusty_error("failed to switch to RPMB partition\n"); + ret = TRUSTY_ERR_GENERIC; + goto end; + } + desc->hwpart = MMC_PART_RPMB; + } + + if (rel_write_size) { + if (rel_write_size % MMC_BLOCK_SIZE) { + trusty_error( + "rel_write_size is not a multiple of MMC_BLOCK_SIZE: %d\n", + rel_write_size); + ret = TRUSTY_ERR_INVALID_ARGS; + goto end; + } + trusty_memcpy(rpmb_rel_write_data, rel_write_data, rel_write_size); + ret = mmc_rpmb_request(mmc, + (const struct s_rpmb *)rpmb_rel_write_data, + rel_write_size / MMC_BLOCK_SIZE, true); + if (ret) { + trusty_error("failed to execute rpmb reliable write\n"); + goto end; + } + } + if (write_size) { + if (write_size % MMC_BLOCK_SIZE) { + trusty_error("write_size is not a multiple of MMC_BLOCK_SIZE: %d\n", + write_size); + ret = TRUSTY_ERR_INVALID_ARGS; + goto end; + } + trusty_memcpy(rpmb_write_data, write_data, write_size); + ret = mmc_rpmb_request(mmc, (const struct s_rpmb *)rpmb_write_data, + write_size / MMC_BLOCK_SIZE, false); + if (ret) { + trusty_error("failed to execute rpmb write\n"); + goto end; + } + } + if (read_size) { + if (read_size % MMC_BLOCK_SIZE) { + trusty_error("read_size is not a multiple of MMC_BLOCK_SIZE: %d\n", + read_size); + ret = TRUSTY_ERR_INVALID_ARGS; + goto end; + } + ret = mmc_rpmb_response(mmc, (struct s_rpmb *)rpmb_read_data, + read_size / MMC_BLOCK_SIZE, 0); + trusty_memcpy((void *)read_buf, rpmb_read_data, read_size); + if (ret < 0) { + trusty_error("failed to execute rpmb read\n"); + } + } + +end: + /* Return to original partition */ + if (desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) { + trusty_error("failed to switch back to original partition\n"); + return TRUSTY_ERR_GENERIC; + } + desc->hwpart = original_part; + } + return ret; +} diff --git a/lib/trusty/ql-tipc/sysdeps/sysdeps_uboot.c b/lib/trusty/ql-tipc/sysdeps/sysdeps_uboot.c new file mode 100644 index 00000000000..b42cd20d4f7 --- /dev/null +++ b/lib/trusty/ql-tipc/sysdeps/sysdeps_uboot.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include + +#include +#include +#include + +extern int trusty_encode_page_info(struct ns_mem_page_info *page_info, + void *vaddr); + +void trusty_lock(struct trusty_dev *dev) +{ +} +void trusty_unlock(struct trusty_dev *dev) +{ +} + +void trusty_local_irq_disable(unsigned long *state) +{ + disable_interrupts(); +} + +void trusty_local_irq_restore(unsigned long *state) +{ + enable_interrupts(); +} + +void trusty_idle(struct trusty_dev *dev) +{ + wfi(); +} + +void trusty_abort(void) +{ + do_reset(NULL, 0, 0, NULL); + __builtin_unreachable(); +} + +void trusty_printf(const char *format, ...) +{ + va_list ap; + + va_start(ap, format); + vprintf(format, ap); + va_end(ap); +} + +void *trusty_memcpy(void *dest, const void *src, size_t n) +{ + return memcpy(dest, src, n); +} + +void *trusty_memset(void *dest, const int c, size_t n) +{ + return memset(dest, c, n); +} + +char *trusty_strcpy(char *dest, const char *src) +{ + return strcpy(dest, src); +} + +size_t trusty_strlen(const char *str) +{ + return strlen(str); +} + +void *trusty_calloc(size_t n, size_t size) +{ + return calloc(n, size); +} + +void trusty_free(void *addr) +{ + if (addr) + free(addr); +} + +void *trusty_alloc_pages(unsigned count) +{ + return memalign(PAGE_SIZE, count * PAGE_SIZE); +} + +void trusty_free_pages(void *va, unsigned count) +{ + if (va) + free(va); +} diff --git a/lib/trusty/ql-tipc/util.c b/lib/trusty/ql-tipc/util.c new file mode 100644 index 00000000000..89ea855ba29 --- /dev/null +++ b/lib/trusty/ql-tipc/util.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include + +const char* trusty_basename(const char* str) { + int64_t n; + size_t len; + + len = trusty_strlen(str); + if (len >= 2) { + for (n = len - 2; n >= 0; n--) { + if (str[n] == '/') { + return str + n + 1; + } + } + } + return str; +} diff --git a/net/eth-uclass.c b/net/eth-uclass.c index d30b04ba862..bdb012b377d 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -3,6 +3,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Joe Hershberger, National Instruments * + * Copyright 2017 NXP + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -40,8 +42,12 @@ static int eth_errno; static struct eth_uclass_priv *eth_get_uclass_priv(void) { struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_ETH, &uc); + if (ret) + return NULL; - uclass_get(UCLASS_ETH, &uc); assert(uc); return uc->priv; } @@ -102,6 +108,7 @@ struct udevice *eth_get_dev_by_name(const char *devname) struct udevice *it; struct uclass *uc; int len = strlen("eth"); + int ret; /* Must be longer than 3 to be an alias */ if (!strncmp(devname, "eth", len) && strlen(devname) > len) { @@ -109,7 +116,10 @@ struct udevice *eth_get_dev_by_name(const char *devname) seq = simple_strtoul(startp, &endp, 10); } - uclass_get(UCLASS_ETH, &uc); + ret = uclass_get(UCLASS_ETH, &uc); + if (ret) + return NULL; + uclass_foreach_dev(it, uc) { /* * We need the seq to be valid, so try to probe it. diff --git a/net/net.c b/net/net.c index 4259c9e321d..12951102c12 100644 --- a/net/net.c +++ b/net/net.c @@ -215,8 +215,11 @@ static int on_bootfile(const char *name, const char *value, enum env_op op, switch (op) { case env_op_create: case env_op_overwrite: - copy_filename(net_boot_file_name, value, - sizeof(net_boot_file_name)); + if (value == NULL) + return -1; + else + copy_filename(net_boot_file_name, value, + sizeof(net_boot_file_name)); break; default: break; diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 2993ade41e2..a85a62f8b5a 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -81,6 +81,7 @@ endif libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/ libs-y += drivers/ libs-$(CONFIG_SPL_USB_GADGET_SUPPORT) += drivers/usb/dwc3/ +libs-$(CONFIG_SPL_USB_GADGET_SUPPORT) += drivers/usb/cdns3/ libs-y += dts/ libs-y += fs/ libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl index b3994110dc7..955e2a16f0c 100644 --- a/scripts/Makefile.uncmd_spl +++ b/scripts/Makefile.uncmd_spl @@ -12,6 +12,7 @@ CONFIG_DM_GPIO= CONFIG_DM_I2C= CONFIG_DM_SPI= CONFIG_DM_SPI_FLASH= +CONFIG_DM_USB= endif endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 3606585c05c..9f22d59e579 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -31,6 +31,10 @@ CONFIG_AM335X_USB1_MODE CONFIG_AM437X_USB2PHY2_HOST CONFIG_ANDES_PCU CONFIG_ANDES_PCU_BASE +CONFIG_ANDROID_AB_SUPPORT +CONFIG_ANDROID_AUTO_SUPPORT +CONFIG_ANDROID_SUPPORT +CONFIG_ANDROID_THINGS_SUPPORT CONFIG_APER_0_BASE CONFIG_APER_1_BASE CONFIG_APER_SIZE @@ -106,6 +110,10 @@ CONFIG_ATMEL_NAND_HW_PMECC CONFIG_ATMEL_SPI0 CONFIG_AT_TRANS CONFIG_AUTO_ZRELADDR +CONFIG_AVB_FUSE +CONFIG_AVB_FUSE_BANK_END +CONFIG_AVB_FUSE_BANK_SIZEW +CONFIG_AVB_FUSE_BANK_START CONFIG_BACKSIDE_L2_CACHE CONFIG_BAT_PAIR CONFIG_BAT_RW @@ -493,6 +501,7 @@ CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE CONFIG_EMMC_BOOT CONFIG_EMU CONFIG_ENABLE_36BIT_PHYS +CONFIG_ENABLE_LOCKSTATUS_SUPPORT CONFIG_ENABLE_MMU CONFIG_ENABLE_MUST_CHECK CONFIG_ENABLE_WARN_DEPRECATED @@ -603,6 +612,7 @@ CONFIG_EXYNOS_TMU CONFIG_FACTORYSET CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE CONFIG_FASTBOOT_FLASH_NAND_TRIMFFS +CONFIG_FASTBOOT_LOCK CONFIG_FAST_FLASH_BIT CONFIG_FB_ADDR CONFIG_FB_BACKLIGHT @@ -676,6 +686,7 @@ CONFIG_FSL_ESDHC_PIN_MUX CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK CONFIG_FSL_FIXED_MMC_LOCATION CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +CONFIG_FSL_HSIO CONFIG_FSL_I2C_CUSTOM_DFSR CONFIG_FSL_I2C_CUSTOM_FDR CONFIG_FSL_IIM @@ -715,6 +726,7 @@ CONFIG_FSL_VIA CONFIG_FSMC_NAND_BASE CONFIG_FSMTDBLK CONFIG_FSNOTIFY +CONFIG_FSPI_QUAD_SUPPORT CONFIG_FS_POSIX_ACL CONFIG_FTAHBC020S CONFIG_FTAHBC020S_BASE @@ -957,6 +969,7 @@ CONFIG_HUSH_INIT_VAR CONFIG_HVBOOT CONFIG_HWCONFIG CONFIG_HW_ENV_SETTINGS +CONFIG_HX8363 CONFIG_I2C CONFIG_I2C_CHIPADDRESS CONFIG_I2C_CMD_TREE @@ -993,6 +1006,7 @@ CONFIG_IMX6_PWM_PER_CLK CONFIG_IMX_HDMI CONFIG_IMX_NAND CONFIG_IMX_OTP +CONFIG_IMX_PCIEB CONFIG_IMX_VIDEO_SKIP CONFIG_IMX_WATCHDOG CONFIG_INETSPACE_V2 @@ -1268,6 +1282,7 @@ CONFIG_MENUKEY CONFIG_MENUPROMPT CONFIG_MENU_SHOW CONFIG_MFG_ENV_SETTINGS +CONFIG_MFG_ENV_SETTINGS_DEFAULT CONFIG_MII CONFIG_MIIM_ADDRESS CONFIG_MII_DEFAULT_TSEC @@ -1382,6 +1397,10 @@ CONFIG_MX6SX_SABRESD_REVA CONFIG_MX6UL_14X14_EVK_EMMC_REWORK CONFIG_MXC_EPDC CONFIG_MXC_GPT_HCLK +CONFIG_MXC_KEYMAPPING +CONFIG_MXC_KPD +CONFIG_MXC_KPD_COLMAX +CONFIG_MXC_KPD_ROWMAX CONFIG_MXC_MCI_REGS_BASE CONFIG_MXC_NAND_HWECC CONFIG_MXC_NAND_IP_REGS_BASE @@ -1495,6 +1514,7 @@ CONFIG_PCIE2 CONFIG_PCIE3 CONFIG_PCIE4 CONFIG_PCIE_IMX +CONFIG_PCIE_IMX8X CONFIG_PCIE_IMX_PERST_GPIO CONFIG_PCIE_IMX_POWER_GPIO CONFIG_PCISLAVE @@ -1600,6 +1620,7 @@ CONFIG_POWER_FSL_MC13892 CONFIG_POWER_FSL_MC34704 CONFIG_POWER_HI6553 CONFIG_POWER_I2C +CONFIG_POWER_KEY CONFIG_POWER_LTC3676 CONFIG_POWER_LTC3676_I2C_ADDR CONFIG_POWER_MAX77696 @@ -1701,6 +1722,8 @@ CONFIG_REV3 CONFIG_REVISION_TAG CONFIG_RFSPART CONFIG_RIO +CONFIG_RM67191 +CONFIG_RM68200 CONFIG_RMII CONFIG_RMOBILE_BOARD_STRING CONFIG_RMSTP0_ENA @@ -1856,6 +1879,7 @@ CONFIG_SIMU CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY +CONFIG_SKIP_RESOURCE_CHECING CONFIG_SKIP_TRUNOFF_WATCHDOG CONFIG_SLIC CONFIG_SLTTMR @@ -2078,6 +2102,7 @@ CONFIG_SXNI855T CONFIG_SYSFLAGS_ADDR CONFIG_SYSFS CONFIG_SYSMGR_ISWGRP_HANDOFF +CONFIG_SYSTEM_RAMDISK_SUPPORT CONFIG_SYS_33MHZ CONFIG_SYS_64BIT CONFIG_SYS_64BIT_LBA @@ -2139,6 +2164,7 @@ CONFIG_SYS_ATMEL_TOTALSECT CONFIG_SYS_AUTOLOAD CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION CONFIG_SYS_AUXCORE_BOOTDATA +CONFIG_SYS_AUXCORE_FASTUP CONFIG_SYS_BARGSIZE CONFIG_SYS_BAUDRATE_TABLE CONFIG_SYS_BCSR @@ -2893,6 +2919,8 @@ CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET CONFIG_SYS_FSL_FMAN_ADDR +CONFIG_SYS_FSL_FSPI_AHB +CONFIG_SYS_FSL_FSPI_BE CONFIG_SYS_FSL_GUTS_ADDR CONFIG_SYS_FSL_I2C CONFIG_SYS_FSL_I2C2_OFFSET @@ -4352,6 +4380,7 @@ CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SPL_LEN CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_SPL_MALLOC_START +CONFIG_SYS_SPL_PTE_RAM_BASE CONFIG_SYS_SPR CONFIG_SYS_SRAM_BASE CONFIG_SYS_SRAM_SIZE @@ -4788,8 +4817,10 @@ CONFIG_VIDEO_BMP_GZIP CONFIG_VIDEO_BMP_LOGO CONFIG_VIDEO_BMP_RLE8 CONFIG_VIDEO_CORALP +CONFIG_VIDEO_CSI CONFIG_VIDEO_DA8XX CONFIG_VIDEO_FONT_4X6 +CONFIG_VIDEO_GIS CONFIG_VIDEO_LCD_I2C_BUS CONFIG_VIDEO_LOGO CONFIG_VIDEO_MB862xx @@ -4798,12 +4829,15 @@ CONFIG_VIDEO_MX3 CONFIG_VIDEO_MXS CONFIG_VIDEO_MXS_MODE_SYSTEM CONFIG_VIDEO_OMAP3 +CONFIG_VIDEO_PXP CONFIG_VIDEO_STD_TIMINGS +CONFIG_VIDEO_VADC CONFIG_VIDEO_VCXK CONFIG_VID_FLS_ENV CONFIG_VM86 CONFIG_VME8349 CONFIG_VOIPAC_LCD +CONFIG_VOL_DOWN_KEY CONFIG_VOL_MONITOR_INA220 CONFIG_VOL_MONITOR_IR36021_READ CONFIG_VOL_MONITOR_IR36021_SET diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index 920ccbf016d..0d11bfdb2f9 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -419,3 +419,46 @@ static int dm_test_first_next_ok_device(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_first_next_ok_device, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static const struct udevice_id fdt_dummy_ids[] = { + { .compatible = "denx,u-boot-fdt-dummy", }, + { } +}; + +UCLASS_DRIVER(fdt_dummy) = { + .name = "fdt_dummy", + .id = UCLASS_TEST_DUMMY, + .flags = DM_UC_FLAG_SEQ_ALIAS, +}; + +U_BOOT_DRIVER(fdt_dummy_drv) = { + .name = "fdt_dummy_drv", + .of_match = fdt_dummy_ids, + .id = UCLASS_TEST_DUMMY, +}; + +static int dm_test_fdt_translation(struct unit_test_state *uts) +{ + struct udevice *dev; + + /* Some simple translations */ + ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev)); + ut_asserteq_str("dev@0,0", dev->name); + ut_asserteq(0x8000, dev_read_addr(dev)); + + ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 1, true, &dev)); + ut_asserteq_str("dev@1,100", dev->name); + ut_asserteq(0x9000, dev_read_addr(dev)); + + ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 2, true, &dev)); + ut_asserteq_str("dev@2,200", dev->name); + ut_asserteq(0xA000, dev_read_addr(dev)); + + /* No translation for busses with #size-cells == 0 */ + ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 3, true, &dev)); + ut_asserteq_str("dev@42", dev->name); + ut_asserteq(0x42, dev_read_addr(dev)); + + return 0; +} +DM_TEST(dm_test_fdt_translation, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/tools/logos/freescale.bmp b/tools/logos/freescale.bmp index 1589e8073d1..43e0591c8ea 100644 Binary files a/tools/logos/freescale.bmp and b/tools/logos/freescale.bmp differ