Support for Vector Instructions

[JishinMaster]

I have not been able to use the vector instructions with the already built image.
It worked with the bl808_linux kernel and Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.6.1 cross-compiler with options : "riscv64-unknown-linux-gnu-gcc -mcpu=c906 -mtune=c906v -march=rv64gcv0p7 -mabi=lp64d"

"cat /proc/cpuinfo" shows only rv64imafdc and not the "v" instruction.
Executing code compiled with the previous command line turns to "illegal instruction".
The cross-compiler included in the SDK is not able to compile with such compiler options (but can compile with a simpler -march=rv64gcv which should be wrong). It also gives "illegal instruction".

The included command ldd also gives "llegal instruction" (for instance ldd /bin/ls) :

[ 1409.978085] ld-linux-riscv6[169]: unhandled signal 4 code 0x1 at 0x0000003f94f9a3b4 in ld-linux-riscv64v0p7_xthead-lp64d.so.1[3f94f85000+1c000]
[ 1409.978951] CPU: 0 PID: 169 Comm: ld-linux-riscv6 Not tainted 6.2.0 #1
[ 1409.979364] Hardware name: Pine64 Ox64 (DT)
[ 1409.979626] epc : 0000003f94f9a3b4 ra : 0000003f94f8bd82 sp : 0000003fd6ffa260
[ 1409.980070] gp : 0000002add502de8 tp : 0000003fa808b7b0 t0 : 0000000000000000
[ 1409.980512] t1 : 0000003f94f85aec t2 : 0000000000000000 s0 : 0000003fd6ffaf05
[ 1409.980955] s1 : 0000000000000000 a0 : 0000003f94fa41e0 a1 : 0000003fd6ffaf05
[ 1409.981470] a2 : 0000000000000008 a3 : 0000003f94fa41e0 a4 : 0000000000000001
[ 1409.981918] a5 : 0000003f94fa41e0 a6 : fefefefefefefeff a7 : 0000003f94f85b70
[ 1409.982361] s2 : 0000000000000000 s3 : 0000003f94fa3058 s4 : 0000000020000000
[ 1409.982803] s5 : 0000003f94fa22d0 s6 : 0000000000000000 s7 : 0000000000000000
[ 1409.983244] s8 : 0000000000000000 s9 : 0000003f94fa22d0 s10: 0000000000000000
[ 1409.983686] s11: 0000003fd6ffaf05 t3 : 0000003f94f970f0 t4 : 0000000000000000
[ 1409.984128] t5 : 0000000000000000 t6 : 0000000000000001
[ 1409.984455] status: 0000000200004020 badaddr: 00000000002672d7 cause: 0000000000000002
Illegal instruction
ldd: $exited with unknown exit code (132)

[gamelaster]

Please, can you describe more what you tried to do? Thanks

[Pavlos1]

OP was trying to run Linux programs that contained RISCV vector instructions. This did not work since the buildroot config disables vector support:

$ grep RVV .config
# BR2_RISCV_ISA_RVV is not set

And indeed we can see that Linux does not report supporting vector instructions in /proc/cpuinfo:

# cat /proc/cpuinfo
processor       : 0
hart            : 0
isa             : rv64imafdc
mmu             : sv39
uarch           : thead,c906
mvendorid       : 0x5b7
marchid         : 0x0
mimpid          : 0x0

By contrast, when running bouffalolab/bl808_linux:

# cat /proc/cpuinfo
processor       : 0
hart            : 0
isa             : rv64imafdcvsu
mmu             : sv39
model name      : T-HEAD C910
freq            : 1.2GHz
icache          : 64kB
dcache          : 64kB
l2cache         : 2MB
tlb             : 1024 4-ways
cache line      : 64Bytes
address sizes   : 40 bits physical, 39 bits virtual
vector version  : 0.7.1

Test File

I have attached a test file (bcd2asc inside bcd2asc.zip) which can be run on the board to demonstrate the issue. In line with OP's observations, this file does run successfully on a board running bouffalolab/bl808_linux, but generates an Illegal instruction trap on the OpenBouffalo image:

# ./bcd2asc 
[   47.945592] bcd2asc[144]: unhandled signal 4 code 0x1 at 0x00000000000105de in bcd2asc[10000+5e000]
[   47.946228] CPU: 0 PID: 144 Comm: bcd2asc Not tainted 6.2.0-rc6 #1
[   47.946718] Hardware name: Pine64 Ox64 (DT)
[   47.946991] epc : 00000000000105de ra : 000000000001065e sp : 0000003ff2228b10
[   47.947441]  gp : 00000000000720c8 tp : 00000000000747a0 t0 : 0000003f9cfb01a0
[   47.947889]  t1 : 2f2f2f2f2f2f2f2f t2 : ffffffffffffffff s0 : 0000003ff2228bb0
[   47.948338]  s1 : 0000000000010c5a a0 : 0000003ff2228b10 a1 : 000000000004c8e0
[   47.948785]  a2 : 0000000000000040 a3 : 0000000000000079 a4 : 0000003ff2228b10
[   47.949233]  a5 : 000000000004d000 a6 : 0000000000000010 a7 : 0000003ff2228b58
[   47.949681]  s2 : 0000000000010378 s3 : 0000000000000000 s4 : 0000000000010378
[   47.950129]  s5 : 00000000ffffffff s6 : 000000000000003a s7 : 0000000000000000
[   47.950577]  s8 : 0000000000000000 s9 : 0000002aea8b9f90 s10: 0000002aea8b6670
[   47.951074]  s11: 0000000000000001 t3 : ffffffffffffffff t4 : 000000000006f538
[   47.951524]  t5 : 0000000000000000 t6 : 0000000000075290
[   47.951859] status: 0000000200004020 badaddr: 00000000003872d7 cause: 0000000000000002
Illegal instruction

Generating the test file

The following instructions document how to generate the test file (bcd2asc) for yourself. They're a bit hacky but it's only meant to be a proof-of-concept. First:

git clone https://github.com/gsauthof/riscv
cd riscv

Patch the Makefile to work with the Xuantie toolchain:

diff --git a/makefile b/makefile
index 0a8edd3..f1bb6c2 100644
--- a/makefile
+++ b/makefile
@@ -1,10 +1,12 @@
 
 
-ASFLAGS = -march=rv64gcv
+ASFLAGS = -march=rv64gcv0p7 -mabi=lp64d
+CFLAGS0 = $(ASFLAGS) -mcpu=c906 -mtune=c906v -static
+LDFLAGS = -static
 
-AS = riscv64-unknown-elf-as
-CC = riscv64-unknown-elf-gcc
-LD = riscv64-unknown-elf-ld
+AS = riscv64-unknown-linux-gnu-as
+CC = riscv64-unknown-linux-gnu-gcc
+LD = riscv64-unknown-linux-gnu-ld
 
 CFLAGSW_GCC = -Wall -Wextra -Wno-missing-field-initializers \
     -Wno-parentheses -Wno-missing-braces \

Compile:

make bcd2asc

Optionally strip the file (otherwise it won't fit into the bouffalolab/bl808_linux squashfs):

riscv64-unknown-linux-gnu-strip bcd2asc

[JishinMaster]

That is indeed what I intended to do! I have seen that the bl808 linux kernel does include vector 0.7 patches for the board. The mainline linux includes vector version 1.0 support with compiler check and assembly. It seems that the 0.7 support should be backported. Le mer. 15 nov. 2023, 16:10, Pavel Zakopaylo ***@***.***> a écrit :

…

OP was trying to run Linux programs that contained RISCV vector instructions. This did not work since the buildroot config disables vector support: $ grep RVV .config # BR2_RISCV_ISA_RVV is not set And indeed we can see that Linux does not report supporting vector instructions in /proc/cpuinfo: # cat /proc/cpuinfo processor : 0 hart : 0 isa : rv64imafdc mmu : sv39 uarch : thead,c906 mvendorid : 0x5b7 marchid : 0x0 mimpid : 0x0 By contrast, when running bouffalolab/bl808_linux <https://github.com/bouffalolab/bl808_linux>: # cat /proc/cpuinfo processor : 0 hart : 0 isa : rv64imafdcvsu mmu : sv39 model name : T-HEAD C910 freq : 1.2GHz icache : 64kB dcache : 64kB l2cache : 2MB tlb : 1024 4-ways cache line : 64Bytes address sizes : 40 bits physical, 39 bits virtual vector version : 0.7.1 Test File I have attached a test file (bcd2asc inside bcd2asc.zip <https://github.com/openbouffalo/buildroot_bouffalo/files/13366150/bcd2asc.zip>) which can be run on the board to demonstrate the issue. In line with OP's observations, this file does run successfully on a board running bouffalolab/bl808_linux <https://github.com/bouffalolab/bl808_linux>, but generates an Illegal instruction trap on the OpenBouffalo image: # ./bcd2asc [ 47.945592] bcd2asc[144]: unhandled signal 4 code 0x1 at 0x00000000000105de in bcd2asc[10000+5e000] [ 47.946228] CPU: 0 PID: 144 Comm: bcd2asc Not tainted 6.2.0-rc6 #1 [ 47.946718] Hardware name: Pine64 Ox64 (DT) [ 47.946991] epc : 00000000000105de ra : 000000000001065e sp : 0000003ff2228b10 [ 47.947441] gp : 00000000000720c8 tp : 00000000000747a0 t0 : 0000003f9cfb01a0 [ 47.947889] t1 : 2f2f2f2f2f2f2f2f t2 : ffffffffffffffff s0 : 0000003ff2228bb0 [ 47.948338] s1 : 0000000000010c5a a0 : 0000003ff2228b10 a1 : 000000000004c8e0 [ 47.948785] a2 : 0000000000000040 a3 : 0000000000000079 a4 : 0000003ff2228b10 [ 47.949233] a5 : 000000000004d000 a6 : 0000000000000010 a7 : 0000003ff2228b58 [ 47.949681] s2 : 0000000000010378 s3 : 0000000000000000 s4 : 0000000000010378 [ 47.950129] s5 : 00000000ffffffff s6 : 000000000000003a s7 : 0000000000000000 [ 47.950577] s8 : 0000000000000000 s9 : 0000002aea8b9f90 s10: 0000002aea8b6670 [ 47.951074] s11: 0000000000000001 t3 : ffffffffffffffff t4 : 000000000006f538 [ 47.951524] t5 : 0000000000000000 t6 : 0000000000075290 [ 47.951859] status: 0000000200004020 badaddr: 00000000003872d7 cause: 0000000000000002 Illegal instruction Generating the test file The following instructions document how to generate the test file (bcd2asc) for yourself. They're a bit hacky but it's only meant to be a proof-of-concept. First: git clone https://github.com/gsauthof/riscvcd riscv Patch the Makefile to work with the Xuantie toolchain: diff --git a/makefile b/makefile index 0a8edd3..f1bb6c2 100644--- a/makefile+++ b/makefile@@ -1,10 +1,12 @@ -ASFLAGS = -march=rv64gcv+ASFLAGS = -march=rv64gcv0p7 -mabi=lp64d+CFLAGS0 = $(ASFLAGS) -mcpu=c906 -mtune=c906v -static+LDFLAGS = -static -AS = riscv64-unknown-elf-as-CC = riscv64-unknown-elf-gcc-LD = riscv64-unknown-elf-ld+AS = riscv64-unknown-linux-gnu-as+CC = riscv64-unknown-linux-gnu-gcc+LD = riscv64-unknown-linux-gnu-ld CFLAGSW_GCC = -Wall -Wextra -Wno-missing-field-initializers \ -Wno-parentheses -Wno-missing-braces \ Compile: make bcd2asc Optionally strip the file (otherwise it won't fit into the bouffalolab/bl808_linux <https://github.com/bouffalolab/bl808_linux> squashfs): riscv64-unknown-linux-gnu-strip bcd2asc — Reply to this email directly, view it on GitHub <#62 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AGF75H67F4OARTC5N4IIPXDYETLNHAVCNFSM6AAAAAAYBF6GQGVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTQMJSG4YTKNJUGE> . You are receiving this because you authored the thread.Message ID: ***@***.***>