From 32592bbb89c65f2d9e86424dcc5994e90dd2410a Mon Sep 17 00:00:00 2001 From: cbiffle Date: Fri, 13 Dec 2024 22:40:14 +0000 Subject: [PATCH] =?UTF-8?q?Deploying=20to=20gh-pages=20from=20@=20oxidecom?= =?UTF-8?q?puter/hubris@a443ac5be723aed7170a23de424c7b4fd0757790=20?= =?UTF-8?q?=F0=9F=9A=80?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- reference/index.html | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/reference/index.html b/reference/index.html index 669e6c4c1..fcbadb8a9 100644 --- a/reference/index.html +++ b/reference/index.html @@ -3496,7 +3496,17 @@
Arguments

0: notification bitmask corresponding to the interrupt

  • -

    1: desired state (0 = disabled, 1 = enabled)

    +

    1: desired state

    +
    +
      +
    • +

      bit 0: 0 = disabled, 1 = enabled

      +
      • +
    • +

      bit 1: 0 = leave pending, 1 = clear pending

      +
      • +
    +
    • @@ -3548,6 +3558,14 @@
    Notes
    +
    +

    The concept of a "pending" interrupt is inherently specific to a particular +architecture and interrupt controller. On an architecture without a concept of +pending interrupts, bit 1 has no effect. However, on architectures with +level-triggered interrupts from peripherals and a concept of "pending" +interrupts, clearing the pending status when re-enabling may be important for +avoiding a duplicate notification.

    +
    @@ -5714,7 +5732,7 @@

    References