diff --git a/drv/grapefruit-seq-server/gfruit_top_map.html b/drv/grapefruit-seq-server/gfruit_top_map.html index f5d3ee364..8395f05b2 100644 --- a/drv/grapefruit-seq-server/gfruit_top_map.html +++ b/drv/grapefruit-seq-server/gfruit_top_map.html @@ -453,7 +453,59 @@

top_level_map

-  spi_nor_SPICR +  base_passthru +   +
+ 0x10 +
+ + +  Enable SPI Passthru + + + + +  31..24 + RSVD + + + + +  23..16 + RSVD + + + + +  15..8 + RSVD + + + + +  7..0 + RSVD + spi_pass + + + + Name + Bit(s) + Access + Reset + Description + + + + spi_pass + 0 + rw + 0x0 + Set to make SPI Nor passthru active vs eSPI spi-nor access + + + +  spi_nor_SPICR  
0x100 @@ -462,34 +514,34 @@

top_level_map

 SPI Control Register - +  31..24 sp5_owns_flash RSVD - +  23..16 RSVD - +  15..8 rx_fifo_reset RSVD - +  7..0 tx_fifo_reset RSVD - + Name Bit(s) @@ -497,7 +549,7 @@

top_level_map

Reset Description - + sp5_owns_flash 31 @@ -508,7 +560,7 @@

top_level_map

flash offset in - + rx_fifo_reset 15 @@ -517,7 +569,7 @@

top_level_map

Set to one to reset RX FIFO. Cleared by hardware after reset. - + tx_fifo_reset 7 @@ -527,7 +579,7 @@

top_level_map

-  spi_nor_SPISR +  spi_nor_SPISR  
0x104 @@ -536,14 +588,14 @@

top_level_map

 SPI Status Register - +  31..24 RSVD tx_used_wds - +  23..16 @@ -551,14 +603,14 @@

top_level_map

tx_empty RSVD - +  15..8 RSVD rx_used_wds - +  7..0 @@ -567,7 +619,7 @@

top_level_map

RSVD busy - + Name Bit(s) @@ -575,7 +627,7 @@

top_level_map

Reset Description - + tx_used_wds 30..24 @@ -585,7 +637,7 @@

top_level_map

max of 256 bytes, so 64 words - + tx_full 23 @@ -594,7 +646,7 @@

top_level_map

Set to one to 1 when TX FIFO is full - + tx_empty 22 @@ -603,7 +655,7 @@

top_level_map

Set to one to 1 when TX FIFO is empty - + rx_used_wds 14..8 @@ -613,7 +665,7 @@

top_level_map

max of 256 bytes, so 64 words - + rx_full 7 @@ -622,7 +674,7 @@

top_level_map

Set to one to 1 when RX FIFO is full - + rx_empty 6 @@ -631,7 +683,7 @@

top_level_map

Set to one to 1 when RX FIFO is empty - + busy 0 @@ -642,7 +694,7 @@

top_level_map

-  spi_nor_Addr +  spi_nor_Addr  
0x108 @@ -651,31 +703,31 @@

top_level_map

 Target Address Register - +  31..24 addr - +  23..16 addr - +  15..8 addr - +  7..0 addr - + Name Bit(s) @@ -683,7 +735,7 @@

top_level_map

Reset Description - + addr 31..0 @@ -693,7 +745,7 @@

top_level_map

-  spi_nor_DummyCycles +  spi_nor_DummyCycles  
0x10c @@ -702,31 +754,31 @@

top_level_map

 Dummy Cycles Register - +  31..24 RSVD - +  23..16 RSVD - +  15..8 RSVD - +  7..0 count - + Name Bit(s) @@ -734,7 +786,7 @@

top_level_map

Reset Description - + count 7..0 @@ -744,7 +796,7 @@

top_level_map

-  spi_nor_DataBytes +  spi_nor_DataBytes  
0x110 @@ -753,32 +805,32 @@

top_level_map

 Data Byte Count Register - +  31..24 RSVD - +  23..16 RSVD - +  15..8 RSVD count - +  7..0 count - + Name Bit(s) @@ -786,7 +838,7 @@

top_level_map

Reset Description - + count 8..0 @@ -797,7 +849,7 @@

top_level_map

-  spi_nor_Instr +  spi_nor_Instr  
0x114 @@ -806,31 +858,31 @@

top_level_map

 SPI Instruction Register - +  31..24 RSVD - +  23..16 RSVD - +  15..8 RSVD - +  7..0 opcode - + Name Bit(s) @@ -838,7 +890,7 @@

top_level_map

Reset Description - + opcode 7..0 @@ -849,7 +901,7 @@

top_level_map

-  spi_nor_tx_fifo_wdata +  spi_nor_tx_fifo_wdata  
0x118 @@ -858,31 +910,31 @@

top_level_map

 TX FIFO Write Data Register - +  31..24 fifo_data - +  23..16 fifo_data - +  15..8 fifo_data - +  7..0 fifo_data - + Name Bit(s) @@ -890,7 +942,7 @@

top_level_map

Reset Description - + fifo_data 31..0 @@ -900,7 +952,7 @@

top_level_map

-  spi_nor_rx_fifo_rdata +  spi_nor_rx_fifo_rdata  
0x11c @@ -909,31 +961,31 @@

top_level_map

 RX FIFO Read Data Register - +  31..24 fifo_data - +  23..16 fifo_data - +  15..8 fifo_data - +  7..0 fifo_data - + Name Bit(s) @@ -941,7 +993,7 @@

top_level_map

Reset Description - + fifo_data 31..0 @@ -951,7 +1003,7 @@

top_level_map

-  spi_nor_SP5FlashOffset +  spi_nor_SP5FlashOffset  
0x120 @@ -960,31 +1012,31 @@

top_level_map

 SP5 Flash offset address - +  31..24 offset - +  23..16 offset - +  15..8 offset - +  7..0 offset - + Name Bit(s) @@ -992,17 +1044,17 @@

top_level_map

Reset Description - + offset 31..0 rw 0x0 - Address added to raw eSPI transactions to generate physical flash address + *Signed* Address added (subtracted for -ve) to raw eSPI transactions to generate physical flash address -  espi_flags +  espi_flags  
0x200 @@ -1011,32 +1063,32 @@

top_level_map

 Flags Register - +  31..24 RSVD - +  23..16 RSVD - +  15..8 RSVD - +  7..0 RSVD alert - + Name Bit(s) @@ -1044,7 +1096,7 @@

top_level_map

Reset Description - + alert 0 @@ -1054,7 +1106,7 @@

top_level_map

-  espi_control +  espi_control  
0x204 @@ -1063,25 +1115,25 @@

top_level_map

 Control Register - +  31..24 RSVD - +  23..16 RSVD - +  15..8 RSVD - +  7..0 @@ -1091,7 +1143,7 @@

top_level_map

resp_fifo_reset dbg_mode_en - + Name Bit(s) @@ -1099,7 +1151,7 @@

top_level_map

Reset Description - + cmd_fifo_reset 3 @@ -1108,7 +1160,7 @@

top_level_map

Set to one to reset the command FIFO. Cleared by hardware after reset. - + cmd_size_fifo_reset 2 @@ -1117,7 +1169,7 @@

top_level_map

Set to one to reset the command size FIFO. Cleared by hardware after reset. - + resp_fifo_reset 1 @@ -1126,7 +1178,7 @@

top_level_map

Set to one to reset response FIFO. Cleared by hardware after reset. - + dbg_mode_en 0 @@ -1136,7 +1188,7 @@

top_level_map

-  espi_status +  espi_status  
0x208 @@ -1145,32 +1197,32 @@

top_level_map

 Status Register - +  31..24 RSVD - +  23..16 RSVD - +  15..8 RSVD - +  7..0 RSVD busy - + Name Bit(s) @@ -1178,7 +1230,7 @@

top_level_map

Reset Description - + busy 0 @@ -1189,7 +1241,7 @@

top_level_map

-  espi_fifo_status +  espi_fifo_status  
0x20c @@ -1198,31 +1250,31 @@

top_level_map

 Fifo Status Register - +  31..24 cmd_used_wds - +  23..16 cmd_used_wds - +  15..8 resp_used_wds - +  7..0 resp_used_wds - + Name Bit(s) @@ -1230,7 +1282,7 @@

top_level_map

Reset Description - + cmd_used_wds 31..16 @@ -1240,7 +1292,7 @@

top_level_map

1024 words so 4kB - + resp_used_wds 15..0 @@ -1251,7 +1303,7 @@

top_level_map

-  espi_cmd_fifo_wdata +  espi_cmd_fifo_wdata  
0x210 @@ -1260,31 +1312,31 @@

top_level_map

 Command FIFO Write Data Register - +  31..24 fifo_data - +  23..16 fifo_data - +  15..8 fifo_data - +  7..0 fifo_data - + Name Bit(s) @@ -1292,7 +1344,7 @@

top_level_map

Reset Description - + fifo_data 31..0 @@ -1302,7 +1354,7 @@

top_level_map

-  espi_resp_fifo_rdata +  espi_resp_fifo_rdata  
0x214 @@ -1311,31 +1363,31 @@

top_level_map

 Response FIFO Read Data Register - +  31..24 fifo_data - +  23..16 fifo_data - +  15..8 fifo_data - +  7..0 fifo_data - + Name Bit(s) @@ -1343,7 +1395,7 @@

top_level_map

Reset Description - + fifo_data 31..0 @@ -1353,7 +1405,7 @@

top_level_map

-  espi_cmd_size_fifo_wdata +  espi_cmd_size_fifo_wdata  
0x218 @@ -1362,31 +1414,31 @@

top_level_map

 Command FIFO Byte Count FIFO - +  31..24 RSVD - +  23..16 RSVD - +  15..8 RSVD - +  7..0 fifo_data - + Name Bit(s) @@ -1394,7 +1446,7 @@

top_level_map

Reset Description - + fifo_data 7..0 @@ -1406,7 +1458,7 @@

top_level_map

-  sgpio_OUT0 +  sgpio_OUT0  
0x300 @@ -1415,19 +1467,19 @@

top_level_map

 CH0 Outputs - +  31..24 RSVD - +  23..16 RSVD - +  15..8 @@ -1439,7 +1491,7 @@

top_level_map

a4 v7 - +  7..0 @@ -1452,7 +1504,7 @@

top_level_map

h3 h0 - + Name Bit(s) @@ -1460,7 +1512,7 @@

top_level_map

Reset Description - + hbt 15 @@ -1469,7 +1521,7 @@

top_level_map

HAWAII_HEARTBEAT - + stb_rdy 14 @@ -1478,7 +1530,7 @@

top_level_map

MB_SCM_HPM_STBY_RDY - + unused 13..12 @@ -1487,7 +1539,7 @@

top_level_map

UNUSED_OUTS - + y3 11 @@ -1496,7 +1548,7 @@

top_level_map

HPM_BMC_GPIOY3-?? - + a5 10 @@ -1505,7 +1557,7 @@

top_level_map

HPM_BMC_GPIOA5-MGMT_SMBUS_DATA - + a4 9 @@ -1514,7 +1566,7 @@

top_level_map

HPM_BMC_GPIOA4-MGMT_SMBUS_CLK - + v7 8 @@ -1523,7 +1575,7 @@

top_level_map

HPM_BMC_GPIOV7-GPIO_OUTPUT_9 - + v6 7 @@ -1532,7 +1584,7 @@

top_level_map

HPM_BMC_GPIOV6-GPIO_OUTPUT_8 - + v5 6 @@ -1541,7 +1593,7 @@

top_level_map

HPM_BMC_GPIOV5-GPIO_OUTPUT_7 - + v3 5 @@ -1550,7 +1602,7 @@

top_level_map

HPM_BMC_GPIOV3-GPIO_OUTPUT_6 - + n7 4 @@ -1559,7 +1611,7 @@

top_level_map

HPM_BMC_GPION7-BMC_READY - + l5 3 @@ -1568,7 +1620,7 @@

top_level_map

HPM_BMC_GPIOL5-?? - + l4 2 @@ -1577,7 +1629,7 @@

top_level_map

HPM_BMC_GPIOL4-?? - + h3 1 @@ -1586,7 +1638,7 @@

top_level_map

HPM_BMC_GPIOH3-?? - + h0 0 @@ -1596,7 +1648,7 @@

top_level_map

-  sgpio_IN0 +  sgpio_IN0  
0x304 @@ -1605,19 +1657,19 @@

top_level_map

 CH0 Inputs - +  31..24 RSVD - +  23..16 RSVD - +  15..8 @@ -1630,7 +1682,7 @@

top_level_map

n5 n4 - +  7..0 @@ -1643,7 +1695,7 @@

top_level_map

b5 b4 - + Name Bit(s) @@ -1651,7 +1703,7 @@

top_level_map

Reset Description - + g7 15 @@ -1660,7 +1712,7 @@

top_level_map

HPM_BMC_GPIOG7-BMC_SCM_FPGA_UART_RX - + p6 14 @@ -1669,7 +1721,7 @@

top_level_map

HPM_BMC_GPIOP6-MGMT_SYS_MON_PWR_GOOD - + p4 13 @@ -1678,7 +1730,7 @@

top_level_map

HPM_BMC_GPIOP4-MGMT_SYS_MON_NMI_BTN_L - + p2 12 @@ -1687,7 +1739,7 @@

top_level_map

HPM_BMC_GPIOP2-MGMT_SYS_MON_PWR_BTN_L - + p0 11 @@ -1696,7 +1748,7 @@

top_level_map

HPM_BMC_GPIOP0-MGMT_SYS_MON_RST_BTN_L - + n6 10 @@ -1705,7 +1757,7 @@

top_level_map

HPM_BMC_GPION6-DEBUG_INPUT1 - + n5 9 @@ -1714,7 +1766,7 @@

top_level_map

HPM_BMC_GPION5-MGMT_AC_LOSS_L - + n4 8 @@ -1723,7 +1775,7 @@

top_level_map

HPM_BMC_GPION4-MGMT_SYS_MON_ATX_PWR_OK - + n3 7 @@ -1732,7 +1784,7 @@

top_level_map

HPM_BMC_GPION3-MGMT_SYS_MON_P1_THERMTRIP_L - + n2 6 @@ -1741,7 +1793,7 @@

top_level_map

HPM_BMC_GPION2-MGMT_SYS_MON_P0_THERMTRIP_L - + n1 5 @@ -1750,7 +1802,7 @@

top_level_map

HPM_BMC_GPION1-MGMT_SYS_MON_P1_PROCHOT_L - + n0 4 @@ -1759,7 +1811,7 @@

top_level_map

HPM_BMC_GPION0-MGMT_SYS_MON_P0_PROCHOT_L - + i6 3 @@ -1768,7 +1820,7 @@

top_level_map

HPM_BMC_GPIOI6-MGMT_SYS_MON_RESET_L - + b7 2 @@ -1777,7 +1829,7 @@

top_level_map

HPM_BMC_GPIOB7-P1_PRESENT_L - + b5 1 @@ -1786,7 +1838,7 @@

top_level_map

HPM_BMC_GPIOB5-P0_PRESENT_L - + b4 0 @@ -1796,7 +1848,7 @@

top_level_map

-  sgpio_OUT1 +  sgpio_OUT1  
0x308 @@ -1805,19 +1857,19 @@

top_level_map

 CH1 Outputs - +  31..24 RSVD - +  23..16 RSVD - +  15..8 @@ -1830,7 +1882,7 @@

top_level_map

o4 o3 - +  7..0 @@ -1843,7 +1895,7 @@

top_level_map

h2 h1 - + Name Bit(s) @@ -1851,7 +1903,7 @@

top_level_map

Reset Description - + g6 14 @@ -1860,7 +1912,7 @@

top_level_map

HPM_BMC_GPIOG6-BMC_SCM_FPGA_UART_TX - + p5 13 @@ -1869,7 +1921,7 @@

top_level_map

HPM_BMC_GPIOP5-MGMT_ASSERT_NMI_BTN_L - + p3 12 @@ -1878,7 +1930,7 @@

top_level_map

HPM_BMC_GPIOP3-MGMT_ASSERT_PWR_BTN_L - + p1 11 @@ -1887,7 +1939,7 @@

top_level_map

HPM_BMC_GPIOP1-MGMT_ASSERT_RST_BTN_L - + o5 10 @@ -1896,7 +1948,7 @@

top_level_map

HPM_BMC_GPIOO5-JTAG_TRST_N - + o4 9 @@ -1905,7 +1957,7 @@

top_level_map

HPM_BMC_GPIOO4-GPIO_OUTPUT_5 - + o3 8 @@ -1914,7 +1966,7 @@

top_level_map

HPM_BMC_GPIOO3-GPIO_OUTPUT_4 - + o2 7 @@ -1923,7 +1975,7 @@

top_level_map

HPM_BMC_GPIOO2-GPIO_OUTPUT_3 - + o1 6 @@ -1932,7 +1984,7 @@

top_level_map

HPM_BMC_GPIOO1-GPIO_OUTPUT_2 - + o0 5 @@ -1941,7 +1993,7 @@

top_level_map

HHPM_BMC_GPIOO0-GPIO_OUTPUT_1 - + m2 4 @@ -1950,7 +2002,7 @@

top_level_map

HPM_BMC_GPIOM2-MGMT_ASSERT_CLR_CMOS - + m1 3 @@ -1959,7 +2011,7 @@

top_level_map

HPM_BMC_GPIOM1-MGMT_ASSERT_P1_PROCHOT - + m0 2 @@ -1968,7 +2020,7 @@

top_level_map

HPM_BMC_GPIOM0-MGMT_ASSERT_P0_PROCHOT - + h2 1 @@ -1977,7 +2029,7 @@

top_level_map

HPM_BMC_GPIOH2-MGMT_SOC_RESET_L - + h1 0 @@ -1987,7 +2039,7 @@

top_level_map

-  sgpio_IN1 +  sgpio_IN1  
0x30c @@ -1996,19 +2048,19 @@

top_level_map

 CH1 Inputs - +  31..24 RSVD - +  23..16 RSVD - +  15..8 @@ -2018,7 +2070,7 @@

top_level_map

uu s7 - +  7..0 @@ -2031,7 +2083,7 @@

top_level_map

m4 m3 - + Name Bit(s) @@ -2039,7 +2091,7 @@

top_level_map

Reset Description - + uu1 15 @@ -2048,7 +2100,7 @@

top_level_map

MGMT_SMBUS_ALERT_L - + i7 14 @@ -2057,7 +2109,7 @@

top_level_map

HPM_BMC_GPIOI7-?? - + espi_sel 13 @@ -2066,7 +2118,7 @@

top_level_map

ESPI_BOOT_SEL - + uu 12..9 @@ -2075,7 +2127,7 @@

top_level_map

I2C_BMC_MB_ALERT_s - + s7 8 @@ -2084,7 +2136,7 @@

top_level_map

HPM_BMC_GPIOS7-GPIO_INPUT_6 - + s6 7 @@ -2093,7 +2145,7 @@

top_level_map

HPM_BMC_GPIOS6-GPIO_INPUT_5 - + s5 6 @@ -2102,7 +2154,7 @@

top_level_map

HPM_BMC_GPIOS5-GPIO_INPUT_4 - + s4 5 @@ -2111,7 +2163,7 @@

top_level_map

HPM_BMC_GPIOS4-GPIO_INPUT_3 - + q4 4 @@ -2120,7 +2172,7 @@

top_level_map

HPM_BMC_GPIOQ4-GPIO_INPUT_2 - + q3 3 @@ -2129,7 +2181,7 @@

top_level_map

HPM_BMC_GPIOQ3-GPIO_INPUT_1 - + m5 2 @@ -2138,7 +2190,7 @@

top_level_map

HPM_BMC_GPIOM5-?? - + m4 1 @@ -2147,7 +2199,7 @@

top_level_map

HPM_BMC_GPIOM4-?? - + m3 0 diff --git a/drv/grapefruit-seq-server/grapefruit.bz2 b/drv/grapefruit-seq-server/grapefruit.bz2 index bba6118c8..a22e3697c 100644 Binary files a/drv/grapefruit-seq-server/grapefruit.bz2 and b/drv/grapefruit-seq-server/grapefruit.bz2 differ diff --git a/drv/grapefruit-seq-server/grapefruit_reg_map.json b/drv/grapefruit-seq-server/grapefruit_reg_map.json index b79539033..eced22fc2 100644 --- a/drv/grapefruit-seq-server/grapefruit_reg_map.json +++ b/drv/grapefruit-seq-server/grapefruit_reg_map.json @@ -82,6 +82,26 @@ "desc": "Scribble Register for read-write use" } ] + }, + { + "type": "reg", + "inst_name": "passthru", + "addr_offset": 16, + "regwidth": 32, + "min_accesswidth": 32, + "children": [ + { + "type": "field", + "inst_name": "spi_pass", + "lsb": 0, + "msb": 0, + "reset": 0, + "sw_access": "rw", + "se_onread": null, + "se_onwrite": null, + "desc": "Set to make SPI Nor passthru active vs eSPI spi-nor access" + } + ] } ] } \ No newline at end of file diff --git a/drv/grapefruit-seq-server/spi_nor_reg_map.json b/drv/grapefruit-seq-server/spi_nor_reg_map.json index 6c704b53b..43c43ba23 100644 --- a/drv/grapefruit-seq-server/spi_nor_reg_map.json +++ b/drv/grapefruit-seq-server/spi_nor_reg_map.json @@ -267,7 +267,7 @@ "sw_access": "rw", "se_onread": null, "se_onwrite": null, - "desc": "Address added to raw eSPI transactions to generate physical flash address" + "desc": "*Signed* Address added (subtracted for -ve) to raw eSPI transactions to generate physical flash address" } ] }