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vivado.log
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#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Thu Jun 18 09:43:54 2020
# Process ID: 8178
# Current directory: /home/pabitra/workspace/project_zcu102
# Command line: vivado
# Log file: /home/pabitra/workspace/project_zcu102/vivado.log
# Journal file: /home/pabitra/workspace/project_zcu102/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/pabitra/workspace/project_zcu102/project_zcu102.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
open_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 6531.668 ; gain = 157.941 ; free physical = 25906 ; free virtual = 30580
update_compile_order -fileset sources_1
ERROR: [Vivado 12-4452] The hardware handoff file (.sysdef) does not exist. It may not have been generated due to:
1. A bitstream might not have been generated. Generate Bitstream and export again, or do not request a bitstream to be included in export.
2. There are no block design hardware handoff files. Check the vivado log messages for more details.
ERROR: [Vivado 12-4452] The hardware handoff file (.sysdef) does not exist. It may not have been generated due to:
1. A bitstream might not have been generated. Generate Bitstream and export again, or do not request a bitstream to be included in export.
2. There are no block design hardware handoff files. Check the vivado log messages for more details.
open_bd_design {/home/pabitra/workspace/project_zcu102/project_zcu102.srcs/sources_1/bd/design_1/design_1.bd}
Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.3 - zynq_ultra_ps_e_0
Successfully read diagram <design_1> from BD file </home/pabitra/workspace/project_zcu102/project_zcu102.srcs/sources_1/bd/design_1/design_1.bd>
set_property location {1 310 -223} [get_bd_cells zynq_ultra_ps_e_0]
generate_target all [get_files /home/pabitra/workspace/project_zcu102/project_zcu102.srcs/sources_1/bd/design_1/design_1.bd]
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'design_1' - hence not re-generating.
export_ip_user_files -of_objects [get_files /home/pabitra/workspace/project_zcu102/project_zcu102.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] /home/pabitra/workspace/project_zcu102/project_zcu102.srcs/sources_1/bd/design_1/design_1.bd]
export_simulation -of_objects [get_files /home/pabitra/workspace/project_zcu102/project_zcu102.srcs/sources_1/bd/design_1/design_1.bd] -directory /home/pabitra/workspace/project_zcu102/project_zcu102.ip_user_files/sim_scripts -ip_user_files_dir /home/pabitra/workspace/project_zcu102/project_zcu102.ip_user_files -ipstatic_source_dir /home/pabitra/workspace/project_zcu102/project_zcu102.ip_user_files/ipstatic -lib_map_path [list {modelsim=/home/pabitra/workspace/project_zcu102/project_zcu102.cache/compile_simlib/modelsim} {questa=/home/pabitra/workspace/project_zcu102/project_zcu102.cache/compile_simlib/questa} {ies=/home/pabitra/workspace/project_zcu102/project_zcu102.cache/compile_simlib/ies} {xcelium=/home/pabitra/workspace/project_zcu102/project_zcu102.cache/compile_simlib/xcelium} {vcs=/home/pabitra/workspace/project_zcu102/project_zcu102.cache/compile_simlib/vcs} {riviera=/home/pabitra/workspace/project_zcu102/project_zcu102.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet
make_wrapper -files [get_files /home/pabitra/workspace/project_zcu102/project_zcu102.srcs/sources_1/bd/design_1/design_1.bd] -top
open_bd_design {/home/pabitra/workspace/project_zcu102/project_zcu102.srcs/sources_1/bd/design_1/design_1.bd}
save_bd_design
Wrote : </home/pabitra/workspace/project_zcu102/project_zcu102.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
launch_runs impl_1 -to_step write_bitstream -jobs 8
[Thu Jun 18 09:45:38 2020] Launched synth_1...
Run output will be captured here: /home/pabitra/workspace/project_zcu102/project_zcu102.runs/synth_1/runme.log
[Thu Jun 18 09:45:38 2020] Launched impl_1...
Run output will be captured here: /home/pabitra/workspace/project_zcu102/project_zcu102.runs/impl_1/runme.log
open_bd_design {/home/pabitra/workspace/project_zcu102/project_zcu102.srcs/sources_1/bd/design_1/design_1.bd}
ERROR: [Vivado 12-4452] The hardware handoff file (.sysdef) does not exist. It may not have been generated due to:
1. A bitstream might not have been generated. Generate Bitstream and export again, or do not request a bitstream to be included in export.
2. There are no block design hardware handoff files. Check the vivado log messages for more details.
set_property location {1 268 -218} [get_bd_cells zynq_ultra_ps_e_0]
INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
WARNING: [IP_Flow 19-474] Invalid Parameter 'Component_Name'