From 593549ef090ebafda69d2ece87f513a4212f8e36 Mon Sep 17 00:00:00 2001 From: Patrick Magauran Date: Sat, 28 Nov 2020 11:01:29 -0500 Subject: [PATCH] Fix some issues preventing GVT-D. Update target.txt to use GCC5 --- i915_display.c | 6 +++--- i915_dp.c | 53 ++++++++++++++++++++++++++++++++------------------ target.txt | 2 +- 3 files changed, 38 insertions(+), 23 deletions(-) diff --git a/i915_display.c b/i915_display.c index edc28d3..22b216d 100644 --- a/i915_display.c +++ b/i915_display.c @@ -14,11 +14,11 @@ static EFI_STATUS ReadEDID(EDID *result) status = ReadEDIDHDMI(result, controller); break; case eDP: - status = ReadEDIDHDMI(result, controller); + status = ReadEDIDDP(result, controller); break; case DPSST: - status = ReadEDIDHDMI(result, controller); + status = ReadEDIDDP(result, controller); break; default: @@ -436,7 +436,7 @@ EFI_STATUS setDisplayGraphicsMode(UINT32 ModeNumber) CHECK_STATUS_ERROR(status); - // intel_hdmi_prepare(encoder, pipe_config); + // intel_hdmi_prepare(encoder, pipe_config);set // hdmi_reg=DDI_BUF_CTL(port) // it's Type C diff --git a/i915_dp.c b/i915_dp.c index d78d41d..50eff3a 100644 --- a/i915_dp.c +++ b/i915_dp.c @@ -2186,7 +2186,7 @@ EFI_STATUS _TrainDisplayPort(struct intel_dp* intel_dp) { SetupClockeDP(intel_dp->controller); /* Schedule a Hotplug Uevent to userspace to start modeset */ - _TrainDisplayPort(intel_dp); + return _TrainDisplayPort(intel_dp); } return EFI_ABORTED; } @@ -2318,10 +2318,15 @@ static void compute_m_n(unsigned int m, unsigned int n, * specified fixed N value for asynchronous clock mode, * which the devices expect also in synchronous clock mode. */ + DebugPrint(EFI_D_ERROR, "i915: progressed to dpline %d\n", + __LINE__); if (constant_n) *ret_n = 0x8000; else *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); + + DebugPrint(EFI_D_ERROR, "i915: progressed to dpline %d\n", + __LINE__); DebugPrint(EFI_D_ERROR, "m: %u, n: %u, ret_n: %u\n", m, n, *ret_n); *ret_m = div_UINT64(mul_UINT32_UINT32(m, *ret_n), n); intel_reduce_m_n_ratio(ret_m, ret_n); @@ -2345,15 +2350,22 @@ intel_link_compute_m_n(UINT16 bits_per_pixel, int nlanes, /* if (fec_enable) data_clock = intel_dp_mode_to_fec_clock(data_clock); */ + DebugPrint(EFI_D_ERROR, "i915: progressed to dpline %d\n", + __LINE__); m_n->tu = 64; + DebugPrint(EFI_D_ERROR, "i915: progressed to dpline %d\n", + __LINE__); compute_m_n(data_clock, link_clock * nlanes * 8, - &m_n->gmch_m, &m_n->gmch_n, + &(m_n->gmch_m), &(m_n->gmch_n), constant_n); - + DebugPrint(EFI_D_ERROR, "i915: progressed to dpline %d\n", + __LINE__); compute_m_n(pixel_clock, link_clock, &m_n->link_m, &m_n->link_n, constant_n); + DebugPrint(EFI_D_ERROR, "i915: progressed to dpline %d\n", + __LINE__); } EFI_STATUS SetupTranscoderAndPipeDP(i915_CONTROLLER* controller) @@ -2407,18 +2419,18 @@ EFI_STATUS SetupTranscoderAndPipeDP(i915_CONTROLLER* controller) ((vertical_syncEnd - 1) << 16)); controller->write32(PIPEASRC, ((horizontal_active - 1) << 16) | (vertical_active - 1)); - struct intel_link_m_n *m_n = {0}; + struct intel_link_m_n m_n = {0}; intel_link_compute_m_n(24, controller->OutputPath.LaneCount, controller->edid.detailTimings[DETAIL_TIME_SELCTION - ].pixelClock * 10,controller->OutputPath.LinkRate, m_n, FALSE, FALSE); + ].pixelClock * 10,controller->OutputPath.LinkRate, &m_n, FALSE, FALSE); controller->write32( PIPEA_DATA_M1, - TU_SIZE(m_n->tu) | m_n->gmch_m); + TU_SIZE(m_n.tu) | m_n.gmch_m); controller->write32( PIPEA_DATA_N1, - m_n->gmch_n); + m_n.gmch_n); controller->write32( PIPEA_LINK_M1, - m_n->link_m); + m_n.link_m); controller->write32( PIPEA_LINK_N1, - m_n->link_n); + m_n.link_n); DebugPrint(EFI_D_ERROR, "i915: HTOTAL_A (%x) = %08x\n", HTOTAL_A, controller->read32(HTOTAL_A)); DebugPrint(EFI_D_ERROR, "i915: HBLANK_A (%x) = %08x\n", HBLANK_A, controller->read32(HBLANK_A)); DebugPrint(EFI_D_ERROR, "i915: HSYNC_A (%x) = %08x\n", HSYNC_A, controller->read32(HSYNC_A)); @@ -2487,22 +2499,25 @@ EFI_STATUS SetupTranscoderAndPipeEDP(i915_CONTROLLER* controller) controller->write32(0x6f034, 0x00800000); controller->write32(0x6f040, 0x00048a37); controller->write32(0x6f044, 0x00080000); */ - struct intel_link_m_n *m_n= {0}; + struct intel_link_m_n m_n = {0}; + //struct intel_link_m_n *m_n= &m_n intel_link_compute_m_n(24, controller->OutputPath.LaneCount, controller->edid.detailTimings[DETAIL_TIME_SELCTION - ].pixelClock * 10,controller->OutputPath.LinkRate, m_n, FALSE, FALSE); - DebugPrint(EFI_D_ERROR, "i915: PIPEEDP_DATA_M1 (%x) = %08x\n", PIPEEDP_DATA_M1, TU_SIZE(m_n->tu) | m_n->gmch_m); - DebugPrint(EFI_D_ERROR, "i915: PIPEEDP_DATA_N1 (%x) = %08x\n", PIPEEDP_DATA_N1, m_n->gmch_n); - DebugPrint(EFI_D_ERROR, "i915: PIPEEDP_LINK_M1 (%x) = %08x\n", PIPEEDP_LINK_M1, m_n->link_m); - DebugPrint(EFI_D_ERROR, "i915: PIPEEDP_LINK_N1 (%x) = %08x\n", PIPEEDP_LINK_N1, m_n->link_n); + ].pixelClock * 10,controller->OutputPath.LinkRate, &m_n, FALSE, FALSE); + DebugPrint(EFI_D_ERROR, "i915: progressed to dpline %d\n", + __LINE__); + DebugPrint(EFI_D_ERROR, "i915: PIPEEDP_DATA_M1 (%x) = %08x\n", PIPEEDP_DATA_M1, TU_SIZE(m_n.tu) | m_n.gmch_m); + DebugPrint(EFI_D_ERROR, "i915: PIPEEDP_DATA_N1 (%x) = %08x\n", PIPEEDP_DATA_N1, m_n.gmch_n); + DebugPrint(EFI_D_ERROR, "i915: PIPEEDP_LINK_M1 (%x) = %08x\n", PIPEEDP_LINK_M1, m_n.link_m); + DebugPrint(EFI_D_ERROR, "i915: PIPEEDP_LINK_N1 (%x) = %08x\n", PIPEEDP_LINK_N1, m_n.link_n); controller->write32( PIPEEDP_DATA_M1, - TU_SIZE(m_n->tu) | m_n->gmch_m); + TU_SIZE(m_n.tu) | m_n.gmch_m); controller->write32( PIPEEDP_DATA_N1, - m_n->gmch_n); + m_n.gmch_n); controller->write32( PIPEEDP_LINK_M1, - m_n->link_m); + m_n.link_m); controller->write32( PIPEEDP_LINK_N1, - m_n->link_n); + m_n.link_n); DebugPrint(EFI_D_ERROR, "i915: HTOTAL_EDP (%x) = %08x\n", HTOTAL_EDP, controller->read32(HTOTAL_EDP)); DebugPrint(EFI_D_ERROR, "i915: HBLANK_EDP (%x) = %08x\n", HBLANK_EDP, controller->read32(HBLANK_EDP)); DebugPrint(EFI_D_ERROR, "i915: HSYNC_EDP (%x) = %08x\n", HSYNC_EDP, controller->read32(HSYNC_EDP)); diff --git a/target.txt b/target.txt index 19f7212..bbc6228 100644 --- a/target.txt +++ b/target.txt @@ -51,7 +51,7 @@ TOOL_CHAIN_CONF = Conf/tools_def.txt # TAGNAME List Optional Specify the name(s) of the tools_def.txt TagName to use. # If not specified, all applicable TagName tools will be # used for the build. The list uses space character separation. -TOOL_CHAIN_TAG = CLANGPDB +TOOL_CHAIN_TAG = GCC5 # MAX_CONCURRENT_THREAD_NUMBER NUMBER Optional The number of concurrent threads. If not specified or set # to zero, tool automatically detect number of processor