diff --git a/SoapyHifiBerry.vcxproj b/SoapyHifiBerry.vcxproj index b45a8fc..b9617cb 100644 --- a/SoapyHifiBerry.vcxproj +++ b/SoapyHifiBerry.vcxproj @@ -89,6 +89,7 @@ + @@ -101,6 +102,7 @@ + diff --git a/SoapyHifiBerry.vcxproj.filters b/SoapyHifiBerry.vcxproj.filters index ed9d1cc..bb363c3 100644 --- a/SoapyHifiBerry.vcxproj.filters +++ b/SoapyHifiBerry.vcxproj.filters @@ -49,6 +49,9 @@ Source files + + Source files + @@ -81,6 +84,9 @@ Header files + + Header files + diff --git a/TCA9548.cpp b/TCA9548.cpp new file mode 100644 index 0000000..6d7dd57 --- /dev/null +++ b/TCA9548.cpp @@ -0,0 +1,145 @@ +#include "TCA9548.h" + +// +// FILE: TCA9548.cpp +// AUTHOR: Rob Tillaart +// VERSION: 0.1.0 +// DATE: 2021-03-16 +// PURPOSE: Library for TCA9548 I2C multiplexer +// +// HISTORY: +// 0.1.0 2021-03-16 initial version + +#include "TCA9548.h" +#include +#include +#include +#include +#include +#include +#include +extern "C" { +#include +} +#include + +TCA9548::TCA9548(const char *i2c_device_filepath, const uint8_t deviceAddress) + : _address(deviceAddress), i2c_file(0), i2c_filepath(i2c_device_filepath) +{ + _mask = 0x00; + _resetPin = -1; + _forced = false; +} + +bool TCA9548::begin(uint8_t mask) +{ + //Open i2c device + int file; + if ((file = open(i2c_filepath.data(), O_RDWR)) < 0) + { + return false; + } + i2c_file = file; + + //Set address + if (ioctl(file, I2C_SLAVE_FORCE, _address) < 0) + { + return false; + } + + if (!isConnected()) + return false; + setChannelMask(mask); + return true; +} + +int TCA9548::i2c_read() +{ + uint8_t reg_val = 0; + + int result = write(i2c_file, &_address, 1); + if (result < 0) + { + return result; + } + + uint8_t data; + result = read(i2c_file, &data, 1); + if (result < 0) + { + return result; + } + else + { + reg_val = data; + } + + return reg_val; +} + +int TCA9548::i2c_write(uint8_t data) +{ + uint8_t buff[2]; + buff[0] = _address; + buff[1] = data; + int result = write(i2c_file, buff, 2); + if (result < 0) + { + return result; + } + return 0; +} + +bool TCA9548::isConnected() +{ + int retval = i2c_read(); + return (retval >= 0); +} + +void TCA9548::enableChannel(uint8_t channel) +{ + if (isEnabled(channel)) + return; + setChannelMask(_mask | (0x01 << channel)); +} + +void TCA9548::disableChannel(uint8_t channel) +{ + if (!isEnabled(channel)) + return; + setChannelMask(_mask & ~(0x01 << channel)); +} + +void TCA9548::selectChannel(uint8_t channel) +{ + setChannelMask(0x01 << channel); +} + +bool TCA9548::isEnabled(uint8_t channel) +{ + if (channel > 7) + return false; + return (_mask & (0x01 << channel)); +} + +void TCA9548::setChannelMask(uint8_t mask) +{ + if ((_mask == mask) && (!_forced)) + return; + _mask = mask; + i2c_write(mask); +} + +uint8_t TCA9548::getChannelMask() +{ + return _mask; +} + +int TCA9548::getError() +{ + int e = _error; + _error = 0; + return e; +} + +// -- END OF FILE -- diff --git a/TCA9548.h b/TCA9548.h new file mode 100644 index 0000000..2c5aa26 --- /dev/null +++ b/TCA9548.h @@ -0,0 +1,58 @@ +#pragma once +#include +#include +#include + +// +// FILE: TCA9548.h +// AUTHOR: Rob Tillaart +// VERSION: 0.1.0 +// DATE: 2021-03-16 +// PURPOSE: Library for TCA9548 I2C multiplexer +// +// URL: https://github.com/RobTillaart/TCA9548 +// +// Adapted for rpi PA0PHH + +#define TCA9548_LIB_VERSION (F("0.1.0")) + +class TCA9548 +{ + public: + // address = 0x70 .. 0x77 + TCA9548(const char *i2c_device_filepath, const uint8_t deviceAddress = 0x70); + bool begin(uint8_t mask = 0x00); // default no channels enabled + bool isConnected(); // find multiplexer on I2C bus + + // channel = 0.. 7 + void enableChannel(uint8_t channel); + void disableChannel(uint8_t channel); + void selectChannel(uint8_t channel); // enable only this channel + bool isEnabled(uint8_t channel); + + // mask = 0x00 .. 0xFF - every bit is a channel. + void setChannelMask(uint8_t mask); + uint8_t getChannelMask(); + + // set forced write + void setForced(bool forced) { _forced = forced; }; + bool getForced() { return _forced; }; + + // TODO improve errorhandling ? + int getError(); + + private: + uint8_t _mask = 0x00; // caching mask + uint8_t _resetPin = -1; + int _error = 0; + uint8_t _address; + bool _forced; + + int i2c_file; + std::string i2c_filepath; + + int i2c_read(); + int i2c_write(uint8_t data); +}; + +// -- END OF FILE -- diff --git a/si5351.cpp b/si5351.cpp index 4f0cf1e..fbe9ee0 100644 --- a/si5351.cpp +++ b/si5351.cpp @@ -40,8 +40,10 @@ extern "C" { /* Public functions */ /********************/ -Si5351::Si5351(const char* i2c_device_filepath, uint8_t i2c_addr): - i2c_bus_addr(i2c_addr),i2c_file(0),i2c_filepath(i2c_device_filepath) +Si5351::Si5351(const char *i2c_device_filepath, uint8_t i2c_addr) + : i2c_bus_addr(i2c_addr), i2c_file(0), i2c_filepath(i2c_device_filepath) + + { xtal_freq[0] = SI5351_XTAL_FREQ; diff --git a/si5351.h b/si5351.h index 0a4b57a..048c901 100644 --- a/si5351.h +++ b/si5351.h @@ -33,158 +33,157 @@ #include /* Define definitions */ -#define SI5351_BUS_BASE_ADDR 0x60 -#define SI5351_XTAL_FREQ 25000000 -#define SI5351_PLL_FIXED 80000000000ULL -#define SI5351_FREQ_MULT 100ULL -#define SI5351_DEFAULT_CLK 1000000000ULL - -#define SI5351_PLL_VCO_MIN 600000000 -#define SI5351_PLL_VCO_MAX 900000000 -#define SI5351_MULTISYNTH_MIN_FREQ 500000 -#define SI5351_MULTISYNTH_DIVBY4_FREQ 150000000 -#define SI5351_MULTISYNTH_MAX_FREQ 225000000 -#define SI5351_MULTISYNTH_SHARE_MAX 100000000 -#define SI5351_MULTISYNTH_SHARE_MIN 1024000 -#define SI5351_MULTISYNTH67_MAX_FREQ SI5351_MULTISYNTH_DIVBY4_FREQ -#define SI5351_CLKOUT_MIN_FREQ 4000 -#define SI5351_CLKOUT_MAX_FREQ SI5351_MULTISYNTH_MAX_FREQ -#define SI5351_CLKOUT67_MS_MIN SI5351_PLL_VCO_MIN / SI5351_MULTISYNTH67_A_MAX -#define SI5351_CLKOUT67_MIN_FREQ SI5351_CLKOUT67_MS_MIN / 128 -#define SI5351_CLKOUT67_MAX_FREQ SI5351_MULTISYNTH67_MAX_FREQ - -#define SI5351_PLL_A_MIN 15 -#define SI5351_PLL_A_MAX 90 -#define SI5351_PLL_B_MAX (SI5351_PLL_C_MAX-1) -#define SI5351_PLL_C_MAX 1048575 -#define SI5351_MULTISYNTH_A_MIN 6 -#define SI5351_MULTISYNTH_A_MAX 1800 -#define SI5351_MULTISYNTH67_A_MAX 254 -#define SI5351_MULTISYNTH_B_MAX (SI5351_MULTISYNTH_C_MAX-1) -#define SI5351_MULTISYNTH_C_MAX 1048575 -#define SI5351_MULTISYNTH_P1_MAX ((1<<18)-1) -#define SI5351_MULTISYNTH_P2_MAX ((1<<20)-1) -#define SI5351_MULTISYNTH_P3_MAX ((1<<20)-1) -#define SI5351_VCXO_PULL_MIN 30 -#define SI5351_VCXO_PULL_MAX 240 -#define SI5351_VCXO_MARGIN 103 - -#define SI5351_DEVICE_STATUS 0 -#define SI5351_INTERRUPT_STATUS 1 -#define SI5351_INTERRUPT_MASK 2 -#define SI5351_STATUS_SYS_INIT (1<<7) -#define SI5351_STATUS_LOL_B (1<<6) -#define SI5351_STATUS_LOL_A (1<<5) -#define SI5351_STATUS_LOS (1<<4) -#define SI5351_OUTPUT_ENABLE_CTRL 3 -#define SI5351_OEB_PIN_ENABLE_CTRL 9 -#define SI5351_PLL_INPUT_SOURCE 15 -#define SI5351_CLKIN_DIV_MASK (3<<6) -#define SI5351_CLKIN_DIV_1 (0<<6) -#define SI5351_CLKIN_DIV_2 (1<<6) -#define SI5351_CLKIN_DIV_4 (2<<6) -#define SI5351_CLKIN_DIV_8 (3<<6) -#define SI5351_PLLB_SOURCE (1<<3) -#define SI5351_PLLA_SOURCE (1<<2) - -#define SI5351_CLK0_CTRL 16 -#define SI5351_CLK1_CTRL 17 -#define SI5351_CLK2_CTRL 18 -#define SI5351_CLK3_CTRL 19 -#define SI5351_CLK4_CTRL 20 -#define SI5351_CLK5_CTRL 21 -#define SI5351_CLK6_CTRL 22 -#define SI5351_CLK7_CTRL 23 -#define SI5351_CLK_POWERDOWN (1<<7) -#define SI5351_CLK_INTEGER_MODE (1<<6) -#define SI5351_CLK_PLL_SELECT (1<<5) -#define SI5351_CLK_INVERT (1<<4) -#define SI5351_CLK_INPUT_MASK (3<<2) -#define SI5351_CLK_INPUT_XTAL (0<<2) -#define SI5351_CLK_INPUT_CLKIN (1<<2) -#define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2) -#define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2) -#define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0) -#define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0) -#define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0) -#define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0) -#define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0) - -#define SI5351_CLK3_0_DISABLE_STATE 24 -#define SI5351_CLK7_4_DISABLE_STATE 25 -#define SI5351_CLK_DISABLE_STATE_MASK 3 -#define SI5351_CLK_DISABLE_STATE_LOW 0 -#define SI5351_CLK_DISABLE_STATE_HIGH 1 -#define SI5351_CLK_DISABLE_STATE_FLOAT 2 -#define SI5351_CLK_DISABLE_STATE_NEVER 3 - -#define SI5351_PARAMETERS_LENGTH 8 -#define SI5351_PLLA_PARAMETERS 26 -#define SI5351_PLLB_PARAMETERS 34 -#define SI5351_CLK0_PARAMETERS 42 -#define SI5351_CLK1_PARAMETERS 50 -#define SI5351_CLK2_PARAMETERS 58 -#define SI5351_CLK3_PARAMETERS 66 -#define SI5351_CLK4_PARAMETERS 74 -#define SI5351_CLK5_PARAMETERS 82 -#define SI5351_CLK6_PARAMETERS 90 -#define SI5351_CLK7_PARAMETERS 91 -#define SI5351_CLK6_7_OUTPUT_DIVIDER 92 -#define SI5351_OUTPUT_CLK_DIV_MASK (7 << 4) -#define SI5351_OUTPUT_CLK6_DIV_MASK (7 << 0) -#define SI5351_OUTPUT_CLK_DIV_SHIFT 4 -#define SI5351_OUTPUT_CLK_DIV6_SHIFT 0 -#define SI5351_OUTPUT_CLK_DIV_1 0 -#define SI5351_OUTPUT_CLK_DIV_2 1 -#define SI5351_OUTPUT_CLK_DIV_4 2 -#define SI5351_OUTPUT_CLK_DIV_8 3 -#define SI5351_OUTPUT_CLK_DIV_16 4 -#define SI5351_OUTPUT_CLK_DIV_32 5 -#define SI5351_OUTPUT_CLK_DIV_64 6 -#define SI5351_OUTPUT_CLK_DIV_128 7 -#define SI5351_OUTPUT_CLK_DIVBY4 (3<<2) - -#define SI5351_SSC_PARAM0 149 -#define SI5351_SSC_PARAM1 150 -#define SI5351_SSC_PARAM2 151 -#define SI5351_SSC_PARAM3 152 -#define SI5351_SSC_PARAM4 153 -#define SI5351_SSC_PARAM5 154 -#define SI5351_SSC_PARAM6 155 -#define SI5351_SSC_PARAM7 156 -#define SI5351_SSC_PARAM8 157 -#define SI5351_SSC_PARAM9 158 -#define SI5351_SSC_PARAM10 159 -#define SI5351_SSC_PARAM11 160 -#define SI5351_SSC_PARAM12 161 - -#define SI5351_VXCO_PARAMETERS_LOW 162 -#define SI5351_VXCO_PARAMETERS_MID 163 -#define SI5351_VXCO_PARAMETERS_HIGH 164 - -#define SI5351_CLK0_PHASE_OFFSET 165 -#define SI5351_CLK1_PHASE_OFFSET 166 -#define SI5351_CLK2_PHASE_OFFSET 167 -#define SI5351_CLK3_PHASE_OFFSET 168 -#define SI5351_CLK4_PHASE_OFFSET 169 -#define SI5351_CLK5_PHASE_OFFSET 170 - -#define SI5351_PLL_RESET 177 -#define SI5351_PLL_RESET_B (1<<7) -#define SI5351_PLL_RESET_A (1<<5) - -#define SI5351_CRYSTAL_LOAD 183 -#define SI5351_CRYSTAL_LOAD_MASK (3<<6) -#define SI5351_CRYSTAL_LOAD_0PF (0<<6) -#define SI5351_CRYSTAL_LOAD_6PF (1<<6) -#define SI5351_CRYSTAL_LOAD_8PF (2<<6) -#define SI5351_CRYSTAL_LOAD_10PF (3<<6) - -#define SI5351_FANOUT_ENABLE 187 -#define SI5351_CLKIN_ENABLE (1<<7) -#define SI5351_XTAL_ENABLE (1<<6) -#define SI5351_MULTISYNTH_ENABLE (1<<4) - +#define SI5351_BUS_BASE_ADDR 0x60 +#define SI5351_XTAL_FREQ 25000000 +#define SI5351_PLL_FIXED 80000000000ULL +#define SI5351_FREQ_MULT 100ULL +#define SI5351_DEFAULT_CLK 1000000000ULL + +#define SI5351_PLL_VCO_MIN 600000000 +#define SI5351_PLL_VCO_MAX 900000000 +#define SI5351_MULTISYNTH_MIN_FREQ 500000 +#define SI5351_MULTISYNTH_DIVBY4_FREQ 150000000 +#define SI5351_MULTISYNTH_MAX_FREQ 225000000 +#define SI5351_MULTISYNTH_SHARE_MAX 100000000 +#define SI5351_MULTISYNTH_SHARE_MIN 1024000 +#define SI5351_MULTISYNTH67_MAX_FREQ SI5351_MULTISYNTH_DIVBY4_FREQ +#define SI5351_CLKOUT_MIN_FREQ 4000 +#define SI5351_CLKOUT_MAX_FREQ SI5351_MULTISYNTH_MAX_FREQ +#define SI5351_CLKOUT67_MS_MIN SI5351_PLL_VCO_MIN / SI5351_MULTISYNTH67_A_MAX +#define SI5351_CLKOUT67_MIN_FREQ SI5351_CLKOUT67_MS_MIN / 128 +#define SI5351_CLKOUT67_MAX_FREQ SI5351_MULTISYNTH67_MAX_FREQ + +#define SI5351_PLL_A_MIN 15 +#define SI5351_PLL_A_MAX 90 +#define SI5351_PLL_B_MAX (SI5351_PLL_C_MAX - 1) +#define SI5351_PLL_C_MAX 1048575 +#define SI5351_MULTISYNTH_A_MIN 6 +#define SI5351_MULTISYNTH_A_MAX 1800 +#define SI5351_MULTISYNTH67_A_MAX 254 +#define SI5351_MULTISYNTH_B_MAX (SI5351_MULTISYNTH_C_MAX - 1) +#define SI5351_MULTISYNTH_C_MAX 1048575 +#define SI5351_MULTISYNTH_P1_MAX ((1 << 18) - 1) +#define SI5351_MULTISYNTH_P2_MAX ((1 << 20) - 1) +#define SI5351_MULTISYNTH_P3_MAX ((1 << 20) - 1) +#define SI5351_VCXO_PULL_MIN 30 +#define SI5351_VCXO_PULL_MAX 240 +#define SI5351_VCXO_MARGIN 103 + +#define SI5351_DEVICE_STATUS 0 +#define SI5351_INTERRUPT_STATUS 1 +#define SI5351_INTERRUPT_MASK 2 +#define SI5351_STATUS_SYS_INIT (1 << 7) +#define SI5351_STATUS_LOL_B (1 << 6) +#define SI5351_STATUS_LOL_A (1 << 5) +#define SI5351_STATUS_LOS (1 << 4) +#define SI5351_OUTPUT_ENABLE_CTRL 3 +#define SI5351_OEB_PIN_ENABLE_CTRL 9 +#define SI5351_PLL_INPUT_SOURCE 15 +#define SI5351_CLKIN_DIV_MASK (3 << 6) +#define SI5351_CLKIN_DIV_1 (0 << 6) +#define SI5351_CLKIN_DIV_2 (1 << 6) +#define SI5351_CLKIN_DIV_4 (2 << 6) +#define SI5351_CLKIN_DIV_8 (3 << 6) +#define SI5351_PLLB_SOURCE (1 << 3) +#define SI5351_PLLA_SOURCE (1 << 2) + +#define SI5351_CLK0_CTRL 16 +#define SI5351_CLK1_CTRL 17 +#define SI5351_CLK2_CTRL 18 +#define SI5351_CLK3_CTRL 19 +#define SI5351_CLK4_CTRL 20 +#define SI5351_CLK5_CTRL 21 +#define SI5351_CLK6_CTRL 22 +#define SI5351_CLK7_CTRL 23 +#define SI5351_CLK_POWERDOWN (1 << 7) +#define SI5351_CLK_INTEGER_MODE (1 << 6) +#define SI5351_CLK_PLL_SELECT (1 << 5) +#define SI5351_CLK_INVERT (1 << 4) +#define SI5351_CLK_INPUT_MASK (3 << 2) +#define SI5351_CLK_INPUT_XTAL (0 << 2) +#define SI5351_CLK_INPUT_CLKIN (1 << 2) +#define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2 << 2) +#define SI5351_CLK_INPUT_MULTISYNTH_N (3 << 2) +#define SI5351_CLK_DRIVE_STRENGTH_MASK (3 << 0) +#define SI5351_CLK_DRIVE_STRENGTH_2MA (0 << 0) +#define SI5351_CLK_DRIVE_STRENGTH_4MA (1 << 0) +#define SI5351_CLK_DRIVE_STRENGTH_6MA (2 << 0) +#define SI5351_CLK_DRIVE_STRENGTH_8MA (3 << 0) + +#define SI5351_CLK3_0_DISABLE_STATE 24 +#define SI5351_CLK7_4_DISABLE_STATE 25 +#define SI5351_CLK_DISABLE_STATE_MASK 3 +#define SI5351_CLK_DISABLE_STATE_LOW 0 +#define SI5351_CLK_DISABLE_STATE_HIGH 1 +#define SI5351_CLK_DISABLE_STATE_FLOAT 2 +#define SI5351_CLK_DISABLE_STATE_NEVER 3 + +#define SI5351_PARAMETERS_LENGTH 8 +#define SI5351_PLLA_PARAMETERS 26 +#define SI5351_PLLB_PARAMETERS 34 +#define SI5351_CLK0_PARAMETERS 42 +#define SI5351_CLK1_PARAMETERS 50 +#define SI5351_CLK2_PARAMETERS 58 +#define SI5351_CLK3_PARAMETERS 66 +#define SI5351_CLK4_PARAMETERS 74 +#define SI5351_CLK5_PARAMETERS 82 +#define SI5351_CLK6_PARAMETERS 90 +#define SI5351_CLK7_PARAMETERS 91 +#define SI5351_CLK6_7_OUTPUT_DIVIDER 92 +#define SI5351_OUTPUT_CLK_DIV_MASK (7 << 4) +#define SI5351_OUTPUT_CLK6_DIV_MASK (7 << 0) +#define SI5351_OUTPUT_CLK_DIV_SHIFT 4 +#define SI5351_OUTPUT_CLK_DIV6_SHIFT 0 +#define SI5351_OUTPUT_CLK_DIV_1 0 +#define SI5351_OUTPUT_CLK_DIV_2 1 +#define SI5351_OUTPUT_CLK_DIV_4 2 +#define SI5351_OUTPUT_CLK_DIV_8 3 +#define SI5351_OUTPUT_CLK_DIV_16 4 +#define SI5351_OUTPUT_CLK_DIV_32 5 +#define SI5351_OUTPUT_CLK_DIV_64 6 +#define SI5351_OUTPUT_CLK_DIV_128 7 +#define SI5351_OUTPUT_CLK_DIVBY4 (3 << 2) + +#define SI5351_SSC_PARAM0 149 +#define SI5351_SSC_PARAM1 150 +#define SI5351_SSC_PARAM2 151 +#define SI5351_SSC_PARAM3 152 +#define SI5351_SSC_PARAM4 153 +#define SI5351_SSC_PARAM5 154 +#define SI5351_SSC_PARAM6 155 +#define SI5351_SSC_PARAM7 156 +#define SI5351_SSC_PARAM8 157 +#define SI5351_SSC_PARAM9 158 +#define SI5351_SSC_PARAM10 159 +#define SI5351_SSC_PARAM11 160 +#define SI5351_SSC_PARAM12 161 + +#define SI5351_VXCO_PARAMETERS_LOW 162 +#define SI5351_VXCO_PARAMETERS_MID 163 +#define SI5351_VXCO_PARAMETERS_HIGH 164 + +#define SI5351_CLK0_PHASE_OFFSET 165 +#define SI5351_CLK1_PHASE_OFFSET 166 +#define SI5351_CLK2_PHASE_OFFSET 167 +#define SI5351_CLK3_PHASE_OFFSET 168 +#define SI5351_CLK4_PHASE_OFFSET 169 +#define SI5351_CLK5_PHASE_OFFSET 170 + +#define SI5351_PLL_RESET 177 +#define SI5351_PLL_RESET_B (1 << 7) +#define SI5351_PLL_RESET_A (1 << 5) + +#define SI5351_CRYSTAL_LOAD 183 +#define SI5351_CRYSTAL_LOAD_MASK (3 << 6) +#define SI5351_CRYSTAL_LOAD_0PF (0 << 6) +#define SI5351_CRYSTAL_LOAD_6PF (1 << 6) +#define SI5351_CRYSTAL_LOAD_8PF (2 << 6) +#define SI5351_CRYSTAL_LOAD_10PF (3 << 6) + +#define SI5351_FANOUT_ENABLE 187 +#define SI5351_CLKIN_ENABLE (1 << 7) +#define SI5351_XTAL_ENABLE (1 << 6) +#define SI5351_MULTISYNTH_ENABLE (1 << 4) /* Macro definitions */ @@ -207,13 +206,13 @@ * beware of side effects! */ -# define do_div(n,base) ({ \ - uint64_t __base = (base); \ - uint64_t __rem; \ - __rem = ((uint64_t)(n)) % __base; \ - (n) = ((uint64_t)(n)) / __base; \ - __rem; \ - }) +#define do_div(n, base) ({ \ + uint64_t __base = (base); \ + uint64_t __rem; \ + __rem = ((uint64_t)(n)) % __base; \ + (n) = ((uint64_t)(n)) / __base; \ + __rem; \ +}) /* Enum definitions */ @@ -233,20 +232,60 @@ enum si5351_variant { }; */ -enum si5351_clock {SI5351_CLK0, SI5351_CLK1, SI5351_CLK2, SI5351_CLK3, - SI5351_CLK4, SI5351_CLK5, SI5351_CLK6, SI5351_CLK7}; +enum si5351_clock +{ + SI5351_CLK0, + SI5351_CLK1, + SI5351_CLK2, + SI5351_CLK3, + SI5351_CLK4, + SI5351_CLK5, + SI5351_CLK6, + SI5351_CLK7 +}; -enum si5351_pll {SI5351_PLLA, SI5351_PLLB}; +enum si5351_pll +{ + SI5351_PLLA, + SI5351_PLLB +}; -enum si5351_drive {SI5351_DRIVE_2MA, SI5351_DRIVE_4MA, SI5351_DRIVE_6MA, SI5351_DRIVE_8MA}; +enum si5351_drive +{ + SI5351_DRIVE_2MA, + SI5351_DRIVE_4MA, + SI5351_DRIVE_6MA, + SI5351_DRIVE_8MA +}; -enum si5351_clock_source {SI5351_CLK_SRC_XTAL, SI5351_CLK_SRC_CLKIN, SI5351_CLK_SRC_MS0, SI5351_CLK_SRC_MS}; +enum si5351_clock_source +{ + SI5351_CLK_SRC_XTAL, + SI5351_CLK_SRC_CLKIN, + SI5351_CLK_SRC_MS0, + SI5351_CLK_SRC_MS +}; -enum si5351_clock_disable {SI5351_CLK_DISABLE_LOW, SI5351_CLK_DISABLE_HIGH, SI5351_CLK_DISABLE_HI_Z, SI5351_CLK_DISABLE_NEVER}; +enum si5351_clock_disable +{ + SI5351_CLK_DISABLE_LOW, + SI5351_CLK_DISABLE_HIGH, + SI5351_CLK_DISABLE_HI_Z, + SI5351_CLK_DISABLE_NEVER +}; -enum si5351_clock_fanout {SI5351_FANOUT_CLKIN, SI5351_FANOUT_XO, SI5351_FANOUT_MS}; +enum si5351_clock_fanout +{ + SI5351_FANOUT_CLKIN, + SI5351_FANOUT_XO, + SI5351_FANOUT_MS +}; -enum si5351_pll_input {SI5351_PLL_INPUT_XO, SI5351_PLL_INPUT_CLKIN}; +enum si5351_pll_input +{ + SI5351_PLL_INPUT_XO, + SI5351_PLL_INPUT_CLKIN +}; /* Struct definitions */ @@ -276,9 +315,9 @@ struct Si5351IntStatus class Si5351 { -public: - Si5351(const char *i2c_device_filepath, uint8_t i2c_addr = SI5351_BUS_BASE_ADDR); - ~Si5351(); + public: + Si5351(const char *i2c_device_filepath, uint8_t i2c_addr = SI5351_BUS_BASE_ADDR); + ~Si5351(); bool init(uint8_t, uint32_t, int32_t); void reset(void); uint8_t set_freq(uint64_t, enum si5351_clock); @@ -301,22 +340,21 @@ class Si5351 void set_clock_fanout(enum si5351_clock_fanout, uint8_t); void set_pll_input(enum si5351_pll, enum si5351_pll_input); void set_vcxo(uint64_t, uint8_t); - void set_ref_freq(uint32_t, enum si5351_pll_input); + void set_ref_freq(uint32_t, enum si5351_pll_input); uint8_t si5351_write_bulk(uint8_t, uint8_t, uint8_t *); uint8_t si5351_write(uint8_t, uint8_t); uint8_t si5351_read(uint8_t); - struct Si5351Status dev_status = {.SYS_INIT = 0, .LOL_B = 0, .LOL_A = 0, - .LOS = 0, .REVID = 0}; - struct Si5351IntStatus dev_int_status = {.SYS_INIT_STKY = 0, .LOL_B_STKY = 0, - .LOL_A_STKY = 0, .LOS_STKY = 0}; + struct Si5351Status dev_status = {.SYS_INIT = 0, .LOL_B = 0, .LOL_A = 0, .LOS = 0, .REVID = 0}; + struct Si5351IntStatus dev_int_status = {.SYS_INIT_STKY = 0, .LOL_B_STKY = 0, .LOL_A_STKY = 0, .LOS_STKY = 0}; enum si5351_pll pll_assignment[8]; uint64_t clk_freq[8]; uint64_t plla_freq; uint64_t pllb_freq; - enum si5351_pll_input plla_ref_osc; - enum si5351_pll_input pllb_ref_osc; + enum si5351_pll_input plla_ref_osc; + enum si5351_pll_input pllb_ref_osc; uint32_t xtal_freq[2]; -private: + + private: uint64_t pll_calc(enum si5351_pll, uint64_t, struct Si5351RegSet *, int32_t, uint8_t); uint64_t multisynth_calc(uint64_t, uint64_t, struct Si5351RegSet *); uint64_t multisynth67_calc(uint64_t, uint64_t, struct Si5351RegSet *); @@ -327,12 +365,12 @@ class Si5351 uint8_t select_r_div_ms67(uint64_t *); int32_t ref_correction[2]; - uint8_t clkin_div; - uint8_t i2c_bus_addr; - bool clk_first_set[8]; + uint8_t clkin_div; + uint8_t i2c_bus_addr; + bool clk_first_set[8]; - int i2c_file; - std::string i2c_filepath; + int i2c_file; + std::string i2c_filepath; }; #endif /* SI5351_H_ */