From 4fec4b64856e9b87bb79dc9e5a42de641597f7d2 Mon Sep 17 00:00:00 2001 From: Chloe Date: Wed, 1 Nov 2023 01:28:23 +0000 Subject: [PATCH] =?UTF-8?q?Deploying=20to=20gh-pages=20from=20=20@=200281b?= =?UTF-8?q?c48854cd7f0330c9e4157436335b1e453eb=20=F0=9F=9A=80?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- 2024/cfp.html | 46 +++++++++++++++++++++----------------------- 2024/contact.html | 2 +- 2024/index.html | 10 +++++----- 2024/organizers.html | 11 +++-------- 2024/program.html | 2 +- 2024/reg.html | 2 +- 2024/submission.html | 2 +- index.html | 2 +- 8 files changed, 35 insertions(+), 42 deletions(-) diff --git a/2024/cfp.html b/2024/cfp.html index 5d014b6..78aee62 100644 --- a/2024/cfp.html +++ b/2024/cfp.html @@ -25,7 +25,7 @@

To be held in conjunction with
38th IEEE International Parallel and Distributed Processing Symposium -
San Fransisco, California, USA (May 27, 2024) +
San Fransisco, California, USA
@@ -54,32 +54,30 @@

Workshop Scope and Goals

-

The current computing landscape has gone through an ever-increasing rate of change and innovation. This change has been driven by the relentless need to improve the energy-efficient, memory, and compute throughput at all levels of the architectural hierarchy. Although the amount of data that must be organized by today's systems posed new challenges to the architecture, which can no longer be solved with classical, homogeneous design. Improvements in all those areas have led Heterogeneous systems to become the norm rather than the exception.

+

The current computing landscape has witnessed a rapid and ongoing surge of change and innovation. This change has been driven by the relentless need to improve the energy-efficiency, memory, and computational throughput across all levels of the architectural hierarchy. The mounting volume of data that today's systems need to organize poses new challenges to the architecture, which can no longer be solved with classical, homogeneous designs. Advancements in all these areas have led Heterogeneous systems to become the norm rather than the exception.

-

Heterogeneous computing leverages a diverse set of computing (CPU, GPU, FPGA, TPU, DPU, etc.) and Memory (HBM, Persistent Memory, Coherent PCI protocols, etc.), hierarchical systems and units to accelerate the execution of a diverse set of applications. Emerging and existing areas such as AI, BigData, Cloud Computing, Edge-Computing, Real-time systems, High-Performance Computing, and others have seen a real benefit due to Heterogenous computer architectures. In addition, a new wave of accelerators based on dataflow architecture instead of the traditional von Neumann is sure to bring additional challenges and opportunities.

+

Heterogeneous computing leverages a diverse set of computing (CPU, GPU, FPGA, TPU, DPU, etc.) and Memory (HBM, Persistent Memory, Coherent PCI protocols, etc.), hierarchical systems, and units to accelerate the execution of a diverse set of applications. Emerging and existing areas such as AI, BigData, Cloud Computing, Edge-Computing, Real-time systems, High-Performance Computing, and others have seen a real benefit due to Heterogeneous computer architectures. In addition, a new wave of accelerators based on dataflow architecture instead of the traditional von Neumann is sure to bring additional challenges and opportunities.

-

These new heterogeneous architectures often also require the development of new applications and programming models, to satisfy these new architectures and to fully utilize these capacities. This workshop focuses on understanding the implications of heterogeneous designs at all levels of the computing system stack, such as hardware, compiler optimizations, porting of applications, and developing programming environments for current and emerging systems in all the above-mentioned areas. It seeks to ground heterogeneous system design research through studies of application kernels and/or whole applications, as well as shed light on new tools, libraries and runtime systems that improve the performance and productivity of applications on heterogeneous systems.

+

These new heterogeneous architectures often also require the development of new applications and programming models, to satisfy these new architectures and to fully utilize their capabilities. This workshop focuses on understanding the implications of heterogeneous designs at all levels of the computing system stack, such as hardware, compiler optimizations, porting of applications, and developing programming environments for current and emerging systems in all the above-mentioned areas. It seeks to ground heterogeneous system design research through studies of application kernels and/or whole applications, as well as shed light on new tools, libraries, and runtime systems that improve the performance and productivity of applications on heterogeneous systems.

+ +

The goal of this workshop is to bring together researchers and practitioners who are at the forefront of Heterogeneous computing to learn the opportunities and challenges in future Heterogeneous system design trends and thus help influence the next trends in this area.

-

The goal of this workshop is to bring together researchers and practitioners who are at the forefront of Heterogeneous computing to learn the opportunities and challenges in future Heterogeneous system design trends and thus help influence the next trends in this area.

Topics of interest include (but are not limited to):

    -
  • Applications for hybrid/heterogenous systems;
    • -
  • Strategies for programming heterogeneous systems using high-level models such as OpenMP, OpenACC, SYCL, OneAPI, Kokkos, Raja, and low-level models such as OpenCL, CUDA;
    • -
  • Methods and tools to tackle challenges from heterogeneity in AI/ML/DL, BigData, Cloud Computing, Edge-Computing, Real-time Systems, and High-Performance Computing;
    • -
  • Strategies for application behavior characterization and performance optimization for accelerators;
    • -
  • Techniques for optimizing kernels for execution on GPGPU, FPGA, TPU, DPU and new emerging heterogeneous platforms;
    • -
  • Models of application performance on heterogeneous and accelerated HPC systems;
    • -
  • Compiler Optimizations and tuning heterogeneous systems including parallelization, loop transformation, locality optimizations, Vectorization;
    • -
  • Implications of workload characterization in heterogeneous and accelerated architecture design;
    • -
  • Benchmarking and performance evaluation for heterogeneous systems at all level of the system stack;
    • -
  • Tools and techniques to address both performance and correctness to assist application development for accelerators and heterogeneous processors;
    • -
  • System software techniques to abstract application domain-specific functionalities for accelerators;
    • -
  • Innovative use of heterogeneous computing in AI for science or optimizations for AI;
    • -
  • Design and use of domain-specific functionalities on accelerators;
    • -
  • Hybrid neuromorphic computing systems;
    • -
  • In-memory architectures;
    • -
  • Dataflow architectures;
    • +
  • Applications for GPU-based systems, and hybrid/heterogeneous systems
    • +
  • Techniques for optimizing kernels for execution on GPUs, FPGAs, TPUs, DPUs, and new emerging heterogeneous platforms
    • +
  • Strategies for programming heterogeneous systems using high-level models such as OpenMP, OpenACC, SYCL, OneAPI, Kokkos, Raja, and low-level models such as OpenCL, CUDA
    • +
  • Methods and tools to tackle challenges from heterogeneity in AI/ML/DL, Big Data, Cloud Computing, Edge-Computing, Real-time Systems, and High-Performance Computing
    • +
  • Strategies for application behavior characterization and performance optimization for accelerators
    • +
  • Models of application performance on heterogeneous and accelerated HPC systems
    • +
  • Compiler Optimizations and tuning heterogeneous systems including parallelization, loop transformation, locality optimizations, vectorization
    • +
  • Implications of workload characterization in heterogeneous and accelerated architecture design
    • +
  • Benchmarking and performance evaluation for heterogeneous systems at all levels of the system stack
    • +
  • Tools and techniques to address both performance and correctness to assist application development for accelerators and heterogeneous processors
    • +
  • System software techniques to abstract application domain-specific functionalities for accelerators
    • +
  • Innovative use of heterogeneous computing in AI for science or optimizations for AI
    • +
  • Design and use of domain-specific functionalities on accelerators

Paper Tracks:

@@ -96,9 +94,9 @@

Workshop Scope and Goals

Important Dates (AoE)

-

Paper Submission: TBD

-

Paper Notification: TBD

-

Camera-ready Deadline: TBD

+

Paper Submission: January 26, 2024

+

Paper Notification: March 1, 2024

+

Camera-ready Deadline: TBD

diff --git a/2024/contact.html b/2024/contact.html index ac2e648..49d9b05 100644 --- a/2024/contact.html +++ b/2024/contact.html @@ -25,7 +25,7 @@

To be held in conjunction with
38th IEEE International Parallel and Distributed Processing Symposium -
San Fransisco, California, USA (May 27, 2024) +
San Fransisco, California, USA
diff --git a/2024/index.html b/2024/index.html index 1ed7875..31c0836 100644 --- a/2024/index.html +++ b/2024/index.html @@ -25,7 +25,7 @@

To be held in conjunction with
38th IEEE International Parallel and Distributed Processing Symposium -
San Fransisco, California, USA (May 27, 2024) +
San Fransisco, California, USA
@@ -65,9 +65,9 @@

DESCRIPTION OF THE WORKSHOP

Important Dates (AoE)

-

Paper Submission: TBD

-

Paper Notification: TBD

-

Camera-ready Deadline: TBD

+

Paper Submission: January 26, 2024

+

Paper Notification: March 1, 2024

+

Camera-ready Deadline: TBD


@@ -80,7 +80,7 @@

Journal Special Issue

Previous Workshops

-

AsHES 2023 Virtual

+

AsHES 2023 in St.Petersburg, Florida, USA

AsHES 2022 Virtual

AsHES 2021 Virtual

AsHES 2020 in New Orleans, USA

diff --git a/2024/organizers.html b/2024/organizers.html index 2eece0d..a6f722f 100644 --- a/2024/organizers.html +++ b/2024/organizers.html @@ -25,7 +25,7 @@

To be held in conjunction with
38th IEEE International Parallel and Distributed Processing Symposium -
San Fransisco, California, USA (May 27, 2024) +
San Fransisco, California, USA
@@ -79,15 +79,10 @@

General Chair

Program Co-Chairs

Nikela Papadopoulou, Chalmers University of Technology, Sweden

-

Carl Pearson, Sandia National Labs, USA

+

Carl Pearson, Sandia National Laboratories, USA

-

Web Chair

-
-

Shumpei Shiina, The University of Tokyo, Japan

-
- -

Publicity Chair

+

Web & Publicity Chair

Chloe Alverti, UIUC, USA

diff --git a/2024/program.html b/2024/program.html index a887106..0757322 100644 --- a/2024/program.html +++ b/2024/program.html @@ -25,7 +25,7 @@

To be held in conjunction with
38th IEEE International Parallel and Distributed Processing Symposium -
San Fransisco, California, USA (May 27, 2024) +
San Fransisco, California, USA