[pull] master from Azure:master #1936
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Why I did it Adding platform support for centec v682-48y8c and v682-48x8c. V682-48y8c switch has 48 SFP+ (1G/10G/25G) ports, 8 QSFP28 (40G/100G) ports on CENTEC TsingMa.MX. V682-48y8c is different from V682-48y8c_d in that: transceiver is managed by cpu smbus rather than TsingMa.MX i2c bus. port led is managed by mcu inside TsingMa.MX. fan, psu, sensors, leds are managed by cpu smbus other than the cpu board vendor's close sourse driver. V682-48x8c switch has 48 SFP+ (1G/10G) ports, 8 QSFP28 (40G/100G) ports on CENTEC TsingMa.MX. CPU used in v682-48y8c and v682-48x8c is Intel(R) Xeon(R) CPU D-1527. How I did it Modify related code in platform and device directory. Upgrade centec sai to v1.9. upgrade python to python3 and kernel version to 5.0 for V682-48y8c_d. How to verify it Build centec amd64 sonic image, verify platform functions (port, sfp, led etc) on centec v682-48y8c and v682-48x8c board. Co-authored-by: shil <[email protected]>
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