-
Notifications
You must be signed in to change notification settings - Fork 5
/
Copy pathSample_Data_generate.log
46 lines (32 loc) · 1.42 KB
/
Sample_Data_generate.log
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Starting process: module
Starting process:
SCUBA, Version Diamond (64-bit) 3.11.0.396.4
Thu Aug 22 09:12:16 2019
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
BEGIN SCUBA Module Synthesis
Issued command : C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n Sample_Data -lang verilog -synth lse -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 8192 -width 8 -rwidth 8 -no_enable -pe 200 -pf 8000
Circuit name : Sample_Data
Module type : ebfifo
Module Version : 5.8
Ports :
Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
Outputs : Q[7:0], Empty, Full, AlmostEmpty, AlmostFull
I/O buffer : not inserted
EDIF output : Sample_Data.edn
Verilog output : Sample_Data.v
Verilog template : Sample_Data_tmpl.v
Verilog testbench: tb_Sample_Data_tmpl.v
Verilog purpose : for synthesis and simulation
Bus notation : big endian
Report output : Sample_Data.srp
Estimated Resource Usage:
EBR : 8
END SCUBA Module Synthesis
File: Sample_Data.lpc created.
End process: completed successfully.
Total Warnings: 0
Total Errors: 0