Sample_Data_tmpl.v

/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.0.396.4 */
/* Module Version: 5.8 */
/* Thu Aug 22 09:12:16 2019 */

/* parameterized module instance */
Sample_Data __ (.Data( ), .WrClock( ), .RdClock( ), .WrEn( ), .RdEn( ), 
    .Reset( ), .RPReset( ), .Q( ), .Empty( ), .Full( ), .AlmostEmpty( ), 
    .AlmostFull( ));