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ram_pll_generate.log
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Starting process: Module
Starting process:
SCUBA, Version Diamond (64-bit) 3.11.0.396.4
Sun Jul 14 13:26:29 2019
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
BEGIN SCUBA Module Synthesis
Issued command : C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n ram_pll -lang verilog -synth lse -arch xo2c00 -type pll -fin 125 -fclkop 165 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
Circuit name : ram_pll
Module type : pll
Module Version : 5.7
Ports :
Inputs : CLKI
Outputs : CLKOP
I/O buffer : not inserted
EDIF output : ram_pll.edn
Verilog output : ram_pll.v
Verilog template : ram_pll_tmpl.v
Verilog purpose : for synthesis and simulation
Bus notation : big endian
Report output : ram_pll.srp
Estimated Resource Usage:
END SCUBA Module Synthesis
File: ram_pll.lpc created.
End process: completed successfully.
Total Warnings: 0
Total Errors: 0