diff --git a/qucs/components/subcircuit.cpp b/qucs/components/subcircuit.cpp index a8207c1ed..ca9beae95 100644 --- a/qucs/components/subcircuit.cpp +++ b/qucs/components/subcircuit.cpp @@ -16,27 +16,24 @@ ***************************************************************************/ #include "subcircuit.h" -#include "schematic.h" +#include "extsimkernels/spicecompat.h" #include "main.h" #include "misc.h" -#include "extsimkernels/spicecompat.h" +#include "schematic.h" -#include #include #include +#include - - -Subcircuit::Subcircuit() -{ - Type = isComponent; // both analog and digital +Subcircuit::Subcircuit() { + Type = isComponent; // both analog and digital Description = QObject::tr("subcircuit"); Props.append(new Property("File", "", false, - QObject::tr("name of qucs schematic file"))); + QObject::tr("name of qucs schematic file"))); Model = "Sub"; - Name = "SUB"; + Name = "SUB"; SpiceModel = "X"; // Do NOT call createSymbol() here. But create port to let it rotate. @@ -44,8 +41,7 @@ Subcircuit::Subcircuit() } // --------------------------------------------------------------------- -Component* Subcircuit::newOne() -{ +Component *Subcircuit::newOne() { Subcircuit *p = new Subcircuit(); p->Props.front()->Value = Props.front()->Value; p->recreate(0); @@ -53,14 +49,13 @@ Component* Subcircuit::newOne() } // ------------------------------------------------------- -Element* Subcircuit::info(QString& Name, char* &BitmapFile, bool getNewOne) -{ +Element *Subcircuit::info(QString &Name, char *&BitmapFile, bool getNewOne) { Name = QObject::tr("Subcircuit"); - BitmapFile = (char *) "subcircuit"; + BitmapFile = (char *)"subcircuit"; - if(getNewOne) { + if (getNewOne) { Subcircuit *p = new Subcircuit(); - p->recreate(0); // createSymbol() is NOT called in constructor !!! + p->recreate(0); // createSymbol() is NOT called in constructor !!! return p; } return 0; @@ -69,75 +64,77 @@ Element* Subcircuit::info(QString& Name, char* &BitmapFile, bool getNewOne) // --------------------------------------------------------------------- // Makes the schematic symbol subcircuit with the correct number // of ports. -void Subcircuit::createSymbol() -{ +void Subcircuit::createSymbol() { int No; QString FileName(Props.front()->Value); FileName = getSubcircuitFile(); tx = INT_MIN; ty = INT_MIN; - if(loadSymbol(FileName) > 0) { // try to load subcircuit symbol - if(tx == INT_MIN) tx = x1+4; - if(ty == INT_MIN) ty = y2+4; + if (loadSymbol(FileName) > 0) { // try to load subcircuit symbol + if (tx == INT_MIN) + tx = x1 + 4; + if (ty == INT_MIN) + ty = y2 + 4; // remove unused ports QMutableListIterator ip(Ports); Port *pp; while (ip.hasNext()) { pp = ip.next(); - if(!pp->avail) { - pp = ip.peekNext(); - ip.remove(); + if (!pp->avail) { + pp = ip.peekNext(); + ip.remove(); } } - } - else { + } else { No = Schematic::testFile(FileName); - if(No < 0) No = 0; + if (No < 0) + No = 0; Ports.clear(); - remakeSymbol(No); // no symbol was found -> create standard symbol + remakeSymbol(No); // no symbol was found -> create standard symbol } } // --------------------------------------------------------------------- -void Subcircuit::remakeSymbol(int No) -{ - int h = 30*((No-1)/2) + 15; - Lines.append(new qucs::Line(-15, -h, 15, -h,QPen(Qt::darkBlue,2))); - Lines.append(new qucs::Line( 15, -h, 15, h,QPen(Qt::darkBlue,2))); - Lines.append(new qucs::Line(-15, h, 15, h,QPen(Qt::darkBlue,2))); - Lines.append(new qucs::Line(-15, -h,-15, h,QPen(Qt::darkBlue,2))); - Texts.append(new Text(-10, -6,"sub")); - - int i=0, y = 15-h; - while(i QucsVersion) {// wrong version number ? - if (!QucsSettings.IgnoreFutureVersion) { - return -4; - } + if (SymbolVersion > QucsVersion) { // wrong version number ? + if (!QucsSettings.IgnoreFutureVersion) { + return -4; + } } // read content ************************* - while(!stream.atEnd()) { + while (!stream.atEnd()) { Line = stream.readLine(); - if(Line == "") break; + if (Line == "") + break; } x1 = y1 = INT_MAX; x2 = y2 = INT_MIN; - int z=0, Result; - while(!stream.atEnd()) { + int z = 0, Result; + while (!stream.atEnd()) { Line = stream.readLine(); - if(Line == "") { - x1 -= 4; // enlarge component boundings a little + if (Line == "") { + x1 -= 4; // enlarge component boundings a little x2 += 4; y1 -= 4; y2 += 4; - return z; // return number of ports + return z; // return number of ports } Line = Line.trimmed(); - if(Line.at(0) != '<') return -5; - if(Line.at(Line.length()-1) != '>') return -6; - Line = Line.mid(1, Line.length()-2); // cut off start and end character + if (Line.at(0) != '<') + return -5; + if (Line.at(Line.length() - 1) != '>') + return -6; + Line = Line.mid(1, Line.length() - 2); // cut off start and end character Result = analyseLine(Line, 1); - if(Result < 0) return -7; // line format error + if (Result < 0) + return -7; // line format error z += Result; } - return -8; // field not closed + return -8; // field not closed } // ------------------------------------------------------- -QString Subcircuit::netlist() -{ - QString s = Model+":"+Name; +QString Subcircuit::netlist() { + QString s = Model + ":" + Name; // output all node names for (Port *p1 : Ports) - s += " "+p1->Connection->Name; // node names + s += " " + p1->Connection->Name; // node names // type for subcircuit - QString f = misc::properFileName(Props.first()->Value); - s += " Type=\""+misc::properName(f)+"\""; + QString f = misc::properFileName(Props.at(0)->Value); + s += " Type=\"" + misc::properName(f) + "\""; // output all user defined properties - for(Property *pp : Props) - s += " "+pp->Name+"=\""+pp->Value+"\""; + for (qsizetype i = 1; i < Props.size(); i++) + s += " " + Props.at(i)->Name + "=\"" + Props.at(i)->Value + "\""; return s + '\n'; } -QString Subcircuit::spice_netlist(bool) -{ - QString s; - QString f = misc::properFileName(Props.first()->Value); - s += spicecompat::check_refdes(Name,SpiceModel); - for (Port *p1 : Ports) { - QString nam = p1->Connection->Name; - if (nam=="gnd") nam = "0"; - s += " "+nam; // node names - } - s += " " + misc::properName(f); - for(Property *pp : Props) { - s += QString(" %1=%2").arg(pp->Name).arg(spicecompat::normalize_value(pp->Value)); - } - s += "\n"; - return s; +QString Subcircuit::spice_netlist(bool) { + QString s; + QString f = misc::properFileName(Props.at(0)->Value); + s += spicecompat::check_refdes(Name, SpiceModel); + for (Port *p1 : Ports) { + QString nam = p1->Connection->Name; + if (nam == "gnd") + nam = "0"; + s += " " + nam; // node names + } + s += " " + misc::properName(f); + for (qsizetype i = 1; i < Props.size(); i++) { + s += QString(" %1=%2").arg( + Props.at(i)->Name, spicecompat::normalize_value(Props.at(i)->Value)); + } + s += "\n"; + return s; } // ------------------------------------------------------- -QString Subcircuit::vhdlCode(int) -{ - QString f = misc::properFileName(Props.first()->Value); +QString Subcircuit::vhdlCode(int) { + QString f = misc::properFileName(Props.at(0)->Value); QString s = " " + Name + ": entity Sub_" + misc::properName(f); // output all user defined properties if (Props.at(1) != nullptr) { s += " generic map ("; s += Props.at(1)->Value; - for(int i = 2; i < Props.size(); i++){ + for (qsizetype i = 2; i < Props.size(); i++) { s += ", " + Props.at(i)->Value; } s += ")"; @@ -257,11 +257,11 @@ QString Subcircuit::vhdlCode(int) s += " port map ("; QListIterator iport(Ports); Port *pp = iport.next(); - if(pp) + if (pp) s += pp->Connection->Name; while (iport.hasNext()) { pp = iport.next(); - s += ", "+pp->Connection->Name; // node names + s += ", " + pp->Connection->Name; // node names } s += ");\n"; @@ -269,29 +269,28 @@ QString Subcircuit::vhdlCode(int) } // ------------------------------------------------------- -QString Subcircuit::verilogCode(int) -{ - QString f = misc::properFileName(Props.first()->Value); +QString Subcircuit::verilogCode(int) { + QString f = misc::properFileName(Props.at(0)->Value); QString s = " Sub_" + misc::properName(f); // output all user defined properties if (Props.at(1) != nullptr) { s += " #("; s += misc::Verilog_Param(Props.at(1)->Value); - for(int i = 2; i < Props.size(); i++) + for (qsizetype i = 2; i < Props.size(); i++) s += ", " + misc::Verilog_Param(Props.at(i)->Value); s += ")"; } // output all node names - s += " " + Name + " ("; + s += " " + Name + " ("; QListIterator iport(Ports); Port *pp = iport.next(); - if(pp) + if (pp) s += pp->Connection->Name; while (iport.hasNext()) { pp = iport.next(); - s += ", "+pp->Connection->Name; // node names + s += ", " + pp->Connection->Name; // node names } s += ");\n"; @@ -299,7 +298,6 @@ QString Subcircuit::verilogCode(int) } // ------------------------------------------------------- -QString Subcircuit::getSubcircuitFile() -{ - return misc::properAbsFileName(Props.front()->Value, containingSchematic); +QString Subcircuit::getSubcircuitFile() { + return misc::properAbsFileName(Props.at(0)->Value, containingSchematic); }