Why are verilog-a modules not loaded when a file that uses them is opened?

[medwatt]

I have a bunch of verilog-a modules in a schematic file. Everything is fine. I restart qucs-a and open the schematic again and get the message that the symbols for the verilog-a modules are not found. I have to manually load them again. Why is this step necessary?

[ra3xdh]

The concept of the Verilog-A modules loading was proposed around 2014 by Guilherme Torri, the former developer of Qucs. I am again only maintaining this code. I cannot say why the developer decided don't load the modules automatically on project open. I would completely rewrite this susbsystem without JSON files and manual compile/load. I have a concept of the Verilog-A device that will act like the existing SPICE file device. But this task has a low priority because of low demand on compact modeling features among average Qucs-S users.

[ra3xdh]

Probably automatic load/unload verilog-a modules could be added on project open. Need more investigations on this. But I am more inclined to rewrite this subsystem and deprecate the JSON files approach in the future.

[pramkyjosep]

CAN GIVE FOR XILINX CODES FOR BASIC GATES