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XSPICE Digital_AUX Library preliminary work #1193
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I suspect that some devices used in subcircuits contain pure digital model (Verilog/VHDL). There is no way to supress it inclusion in the library if such model is found. |
I can't find any Library in Qucs, QucsStudio or Qucs-S that used "Verilog/VHDL". Seems like a lot of work for little return. QucsStudio does have "Compiled Models" but not many use that feature. Any idea if this will hinder adding Spice Library device with parameter passing to Create Library? |
I cannot remember such libraries too. I am not sure if this feature (VHDL/Verilog support in libraries) was ever used after it was introduced. |
Any idea if this will hinder adding Spice Library device with parameter passing to Create Library? |
Since you make Libraries by hand, any hints how to make a Library of this project? |
I'll take a look as soon as I can, but I've no clue at this moment |
Mike Brinson made Xanalogue.lib. Some of the subcircuits in this project should have similar structure. Issue #944 adds more context. |
Goals: I made a simplified test project with XSPICE ADC & DAC Bridges, digital Clock and Analog Clock. I made two subcircuits each of the ADC & DAC Bridges using "Spice library" and "Spice netlist". Subcircuits made using Spice library support parameter passing and subcircuits made using Spice netlist do not. Unfortunately the Qucs Create Library utility supports making a Library from subcircuits made using Spice netlist but doesn't support making one from subcircuits made using Spice library. I decided to make two Libraries "Digital_slib.lib" and "Digital_snet.lib" to see what the syntax differences looked like. As expected the devices in "Digital_snet.lib" "function" but don't support parameter passing. The devices in "Digital_slib.lib" don't work. In the case of subcircuits made with "digital" devices, Qucs Create Library inserts unrelated Verilog/VHDL sections into the Library cluttering it with spurious entries. |
Probably I will implement a way to pass parameters to SPICE file device. This task could be done before the release. Otherwise its need to wait #944 in the next release cycle.
The Verilog/VHDL section should not affect the analog simulation. |
When comparing "Digital_snet.lib" to "Xanalogue.lib" there are numerous extra entries that don't seem to do anything like "ModelIncludes "ADC_bridge.cir.lst" and "ModelIncludes "DAC_bridge.cir.lst" which are temp files never used again. Digital_snet.lib also has more "subcircuit" and "parameter" entries than Xanalogue.lib even though both are for simple XSPICE devices. |
LST files are for Qucsator. These directives has no effect in SPICE simulation. |
LST files are never used after the Library is made. They also don't exist on anyone's PC other than the original Author. I delete them all the time. |
@tomhajjar The PR #1197 allows parameter passing for SPICE file component. You may proceed with the library design. |
One nice thing about Spice library is you can copy-paste parameter info from the Spice file into the parameter field. |
First cut at Digital_AUX.lib. I deleted a number of sources and pull-up/downs I deemed redundant. One minor issue is sometimes a Digital simulation doesn't need a "ground" so instead of adding a resistor to ground I "grounded ground". Without it simulation failed. |
null |
Is this library ready for upload in the repository? |
Yes. Also the goal is to also have all the files used to make the Libraries be available in the Discussion section. It should help with expansion of the Libraries and spawn new ones. Having had to "reverse engineer" many of the original "Qucs" Libraries wasn't fun... |
Library uploaded by #1200 |
I started preliminary work on the Digital_AUX.lib to determine what will be in the Library.
As an experiment I made the Library knowing it would be missing most of the Spice models to see what it would look like. Since multiple Qucs-S Libraries like Xanalogue.lib also have Parameter-Passing and were made by hand I figured I might be able to add the missing info. I was surprised to see the following Verilog sections since they don't exist in any Qucs Library I have seen.
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