diff --git a/README.md b/README.md
index 88783457..7c877047 100644
--- a/README.md
+++ b/README.md
@@ -31,23 +31,30 @@ Use CMake to build Qucs-S. Install all necessary dependencies: GCC, Qt, Flex, Bi
 
 ### Dependencies
 
-#### Ubuntu
+Qucs-S requires Qt6 libraries including QtCharts, CMake, flex, bison, gperf, and dos2unix as compile time
+dependencies. Install these packages using the package manager of your distribution before compiling Qucs-S.
+Ngspice is not required at compile time, but it is required as runtime dependency to run the simulation.
+
+Here are some examples for the popular Linux distributions.
+
+#### Ubuntu or Debian
 
 ~~~
-sudo apt-get install ngspice build-essential git cmake qtbase5-dev qttools5-dev libqt5svg5-dev libqt5charts5-dev flex bison gperf dos2unix
+sudo apt-get install ngspice build-essential git cmake flex bison gperf dos2unix
+sudo apt-get install qt6-base-dev qt6-tools-dev qt6-tools-dev-tools libglx-dev linguist-qt6 
+sudo apt-get install qt6-l10n-tools libqt6svg6-dev libgl1-mesa-dev qt6-charts-dev libqt6opengl6-dev
 ~~~
 
-#### OpenSUSE Tumbleweed
+#### Fedora
 
 ~~~
-sudo zypper install ngspice git cmake libqt5-qtbase-devel libqt5-qttools-devel libqt5-qtsvg-devel libqt5-qtcharts-devel flex bison gperf dos2unix
+sudo dnf install gcc-c++ cmake git flex bison gperf dos2unix ngspice
+sudo dnf install qt6-qtbase-devel cmake qt6-qtsvg-devel qt6-qttools-devel qt6-qtcharts-devel 
 ~~~
 
 ### Compiling
 
-#### Qt5
-
-Then clone this git repository and execute in the top directory:
+After installing the dependecies, clone this git repository and execute in the top directory:
 
 ~~~
 git submodule init
@@ -59,19 +66,16 @@ make
 make install
 ~~~
 
-Where `/your_install_prefix/` is desired installation directory. Substitute any
-desire path (for example `$HOME/qucs-s`) here. You may omit this option and
-installation steps. Default installation directory will be `/usr/local` if
+Since the v25.1.0 the Qucs-S will be configured with Qt6 by default. Substutute the  `/your_install_prefix/` 
+as desired installation directory. Substitute any desire path (for example `$HOME/qucs-s`) here. 
+You may omit this option and installation steps. Default installation directory will be `/usr/local` if
 `CMAKE_INSTALL_PREFIX` is not defined.
 
-#### Qt6
+### Qt5/Qt6 support
 
-Since v1.0.1 Qucs-S supports build with Qt6. Set the `WITH_QT6` flag to tell CMake use the Qt6. 
-For example use the following command sequence for Ubuntu-22.04
+Qt5 support has been dropped since v25.1.0. Only Qt6 libraries are supported. Set the `WITH_QT6=ON` 
+cmake flag if compiling the Qucs-S versions before v25.1.0
 
-~~~
-cmake .. -DWITH_QT6=ON -DCMAKE_INSTALL_PREFIX=/your_install_prefix/
-~~~ 
 
 ### Running
 
diff --git a/library/CMakeLists.txt b/library/CMakeLists.txt
index 591ed7d6..457fef24 100644
--- a/library/CMakeLists.txt
+++ b/library/CMakeLists.txt
@@ -9,7 +9,7 @@ Crystal.lib
 Diodes.lib
 DiodesSchottky.lib
 Diodes_Extended.lib
-Digital_CD4000.lib
+Digital_CD.lib
 Digital_HC.lib
 Digital_LV.lib
 GeDiodes.lib
diff --git a/library/Digital_CD4000.lib b/library/Digital_CD.lib
similarity index 59%
rename from library/Digital_CD4000.lib
rename to library/Digital_CD.lib
index 31d54503..d91e7d25 100644
--- a/library/Digital_CD4000.lib
+++ b/library/Digital_CD.lib
@@ -1,11 +1,72 @@
-<Qucs Library 24.4.1 "Digital_CD4000">
+<Qucs Library 24.4.99 "Digital_CD">
+
+<Component CD4001>
+  <Description>
+2-Input NOR Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_CD_CD4001 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="CD4001_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "CD4001.cir.lst">
+  <Spice>
+* -------------------------------- CD4001B-------------------------------
+*
+*  Quad 2-Input NOR Gate
+*
+*  The CMOS Logic Data Book, 1991, Motorola Pages 6-5 to 6-14
+*  jds    6/6/94
+*  This part is shown in the data book as MC14001B
+*
+.SUBCKT CD4001B IN1A IN2A OUTA
++  optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
++  params: MNTYMXDLY=0 IO_LEVEL=0
+*
+Uf0 nor(2) VDD VSS
++   IN1A IN2A OUTA
++   DLY_MOD IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_MOD ugate (TPLHMN=-1 TPLHTY=125ns TPLHMX=250ns
++                     TPHLMN=-1 TPHLTY=125ns TPHLMX=250ns)
+
+.ENDS CD4001B
+*
+
+.SUBCKT Digital_CD_CD4001  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 CD4001B
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #000080 2 1>
+    <Line -10 20 -5 0 #000080 2 1>
+    <Line -10 -20 -5 0 #000080 2 1>
+  </Symbol>
+</Component>
 
 <Component CD4011>
   <Description>
-Quad 2-Input CMOS NAND
+2-Input NAND Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
   </Description>
   <Model>
-.Def:Digital_CD4000_CD4011 _net0 _net2 _net1
+.Def:Digital_CD_CD4011 _net0 _net2 _net1
 Sub:X1 _net0 _net2 _net1 gnd Type="CD4011_cir"
 .Def:End
   </Model>
@@ -33,7 +94,7 @@ Uf0 nand(2) VDD VSS
 .ENDS CD4011B
 *
 
-.SUBCKT Digital_CD4000_CD4011  gnd _net0 _net2 _net1 
+.SUBCKT Digital_CD_CD4011  gnd _net0 _net2 _net1 
 X1 _net0 _net2 _net1 CD4011B
 .ENDS
   </Spice>
@@ -51,12 +112,77 @@ X1 _net0 _net2 _net1 CD4011B
   </Symbol>
 </Component>
 
+<Component CD4012>
+  <Description>
+4-Input NAND Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_CD_CD4012 _net0 _net1 _net2 _net3 _net4
+Sub:X1 _net0 _net1 _net2 _net3 _net4 gnd Type="CD4012_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "CD4012.cir.lst">
+  <Spice>
+* ------------------------------ CD4012B------------------------
+*
+*  Dual 4-Input NAND Gate
+*
+*  The CMOS Logic Data Book, 1991, Motorola Pages 6-5 to 6-14
+*  jds    6/6/94
+*  This part is shown in the data book as MC14012B
+*
+.SUBCKT CD4012B IN1A IN2A IN3A IN4A OUTA
++  optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
++  params: MNTYMXDLY=0 IO_LEVEL=0
+*
+Uf0 nand(4) VDD VSS
++   IN1A IN2A IN3A IN4A OUTA
++   DLY_MOD IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_MOD ugate (TPLHMN=-1 TPLHTY=160ns TPLHMX=300ns
++                     TPHLMN=-1 TPHLTY=160ns TPHLMX=300ns)
+
+.ENDS CD4012B
+*
+
+.SUBCKT Digital_CD_CD4012  gnd _net0 _net1 _net2 _net3 _net4 
+X1 _net0 _net1 _net2 _net3 _net4 CD4012B
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line -30 -30 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <Line -30 30 20 0 #000080 2 1>
+    <Line -10 40 0 -80 #000080 2 1>
+    <Ellipse 20 -4 8 8 #000080 1 1 #000080 1 1>
+    <EArc -20 -20 40 40 4320 2880 #000080 2 1>
+    <Line 0 20 -10 0 #000080 2 1>
+    <.PortSym -30 -30 1 0 P1>
+    <.PortSym -30 -10 2 0 P2>
+    <.PortSym -30 10 3 0 P3>
+    <.PortSym -30 30 4 0 P4>
+    <.PortSym 40 0 5 180 P5>
+    <.ID 20 14 Y>
+    <Line 28 0 12 0 #000080 2 1>
+    <Line 0 -20 -10 0 #000080 2 1>
+  </Symbol>
+</Component>
+
 <Component CD4013>
   <Description>
-Two D-type CMOS Flip-flops
+D-Type Positive Edge Triggered Flip-Flop With Preset And Clear
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
   </Description>
   <Model>
-.Def:Digital_CD4000_CD4013 _net0 _net1 _net2 _net3 _net4 _net5
+.Def:Digital_CD_CD4013 _net0 _net1 _net2 _net3 _net4 _net5
 Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 gnd Type="CD4013_cir"
 .Def:End
   </Model>
@@ -120,7 +246,7 @@ U4 CONSTRAINT(3) VDD VSS
 .ENDS CD4013B
 *
 
-.SUBCKT Digital_CD4000_CD4013  gnd _net0 _net1 _net2 _net3 _net4 _net5 
+.SUBCKT Digital_CD_CD4013  gnd _net0 _net1 _net2 _net3 _net4 _net5 
 X1 _net0 _net1 _net2 _net3 _net4 _net5 CD4013B
 .ENDS
   </Spice>
@@ -152,10 +278,14 @@ X1 _net0 _net1 _net2 _net3 _net4 _net5 CD4013B
 
 <Component CD4017>
   <Description>
-Decade counter with 10 decoded outputs
+5-stage Johnson Decade Counter
+with 10 Decoded Outputs
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
   </Description>
   <Model>
-.Def:Digital_CD4000_CD4017 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12
+.Def:Digital_CD_CD4017 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12
 Sub:X1 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 gnd Type="CD4017_cir"
 .Def:End
   </Model>
@@ -256,7 +386,7 @@ Ucnstr CONSTRAINT(3) VDD VSS
 .ENDS CD4017B
 *
 
-.SUBCKT Digital_CD4000_CD4017  gnd _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 
+.SUBCKT Digital_CD_CD4017  gnd _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 
 X1 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 CD4017B
 .ENDS
   </Spice>
@@ -312,10 +442,13 @@ X1 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _ne
 
 <Component CD4022>
   <Description>
-Octal counter with 8 decoded outputs
+Octal Counter with 8 Decoded Outputs
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
   </Description>
   <Model>
-.Def:Digital_CD4000_CD4022 _net11 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10
+.Def:Digital_CD_CD4022 _net11 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10
 Sub:X1 _net11 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 gnd Type="CD4022_cir"
 .Def:End
   </Model>
@@ -402,7 +535,7 @@ U4 CONSTRAINT(3) VDD VSS
 
 .ENDS CD4022B
 
-.SUBCKT Digital_CD4000_CD4022  gnd _net11 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 
+.SUBCKT Digital_CD_CD4022  gnd _net11 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 
 X1 _net11 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 CD4022B
 .ENDS
   </Spice>
@@ -452,10 +585,13 @@ X1 _net11 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 CD4
 
 <Component CD4040>
   <Description>
-
+12-Stage Binary Ripple Counter
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
   </Description>
   <Model>
-.Def:Digital_CD4000_CD4040 _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11
+.Def:Digital_CD_CD4040 _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11
 Sub:X1 _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 gnd Type="CD4040_cir"
 .Def:End
   </Model>
@@ -643,7 +779,7 @@ Ucnstr CONSTRAINT(2) VDD VSS
 .ENDS CD4040B
 *
 
-.SUBCKT Digital_CD4000_CD4040  gnd _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 
+.SUBCKT Digital_CD_CD4040  gnd _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 
 X1 _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 CD4040B
 .ENDS
   </Spice>
@@ -696,3 +832,364 @@ X1 _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _ne
   </Symbol>
 </Component>
 
+<Component CD4069>
+  <Description>
+Inverting Buffer
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:Digital_CD_CD4069 _net0 _net1
+Sub:X1 _net0 _net1 gnd Type="CD4069_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "CD4069.cir.lst">
+  <Spice>
+* ---------------------------- CD4069UB --------------------------
+*
+*  Hex Inverting Buffer
+*
+*  The CMOS Logic Data Book, 1988, National Semiconductor Pages 5-180 to 5-183
+*  jds    6/8/94
+*
+.SUBCKT CD4069UB A ABAR
++  optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
++  params: MNTYMXDLY=0 IO_LEVEL=0
+
+uf0 inv VDD VSS
++   A ABAR
++   DLY_MOD IO_4000UB MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_MOD ugate (TPLHMN=-1 TPLHTY=50ns TPLHMX=90ns
++                     TPHLMN=-1 TPHLTY=50ns TPHLMX=90ns)
+
+.ENDS CD4069UB
+*
+
+.SUBCKT Digital_CD_CD4069  gnd _net0 _net1 
+X1 _net0 _net1 CD4069UB
+.ENDS
+  </Spice>
+  <Symbol>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line -10 20 0 -40 #000080 2 1>
+    <Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <.ID 10 14 Y>
+    <.PortSym 30 0 2 180 P2>
+    <Line -30 0 20 0 #000080 2 1>
+    <.PortSym -30 0 1 0 P1>
+  </Symbol>
+</Component>
+
+<Component CD4070>
+  <Description>
+2-Input XOR Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:Digital_CD_CD4070 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="CD4070_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "CD4070.cir.lst">
+  <Spice>
+* -------------------------------- CD4070B -------------------------------
+*
+*  Quad 2-Input XOR Gate
+*
+*  The CMOS Logic Data Book, 1988, National Semiconductor Pages 5-184 to 5-187
+*  jds    6/8/94
+*
+.SUBCKT CD4070B IN1A IN2A OUTA
++  optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
++  params: MNTYMXDLY=0 IO_LEVEL=0
+
+uf0 xor VDD VSS
++   IN1A IN2A OUTA
++   DLY_MOD IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_MOD ugate (TPLHMN=-1 TPLHTY=110ns TPLHMX=185ns
++                     TPHLMN=-1 TPHLTY=110ns TPHLMX=185ns)
+
+.ENDS CD4070B
+*
+
+.SUBCKT Digital_CD_CD4070  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 CD4070B
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #000080 2 1>
+    <EArc -15 -20 10 40 4320 2880 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component CD4071>
+  <Description>
+2-Input OR Gate
+  XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:Digital_CD_CD4071 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="CD4071_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "CD4071.cir.lst">
+  <Spice>
+* --------------------------- CD4071B------------------------
+*
+*  Quad 2-Input OR Gate
+*
+*  The CMOS Logic Data Book, 1991, Motorola Pages 6-5 to 6-14
+*  jds    6/6/94
+*  This part is shown in the data book as MC14071B
+*
+.SUBCKT CD4071B IN1A IN2A OUTA
++  optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
++  params: MNTYMXDLY=0 IO_LEVEL=0
+*
+Uf0 or(2) VDD VSS
++   IN1A IN2A OUTA
++   DLY_MOD IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_MOD ugate (TPLHMN=-1 TPLHTY=160ns TPLHMX=300ns
++                     TPHLMN=-1 TPHLTY=160ns TPHLMX=300ns)
+
+.ENDS CD4071B
+*
+
+.SUBCKT Digital_CD_CD4071  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 CD4071B
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #000080 2 1>
+    <Line -10 20 -5 0 #000080 2 1>
+    <Line -10 -20 -5 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component CD4081>
+  <Description>
+2-Input AND Gate
+  XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:Digital_CD_CD4081 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="CD4081_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "CD4081.cir.lst">
+  <Spice>
+* ------------------------------ CD4081B-------------------------
+*
+*  Quad 2-Input AND Gate
+*
+*  The CMOS Logic Data Book, 1991, Motorola Pages 6-5 to 6-14
+*  jds    6/6/94
+*  This part is shown in the data book as MC14081B
+*
+.SUBCKT CD4081B IN1A IN2A OUTA
++  optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
++  params: MNTYMXDLY=0 IO_LEVEL=0
+*
+Uf0 and(2) VDD VSS
++   IN1A IN2A OUTA
++   DLY_MOD IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_MOD ugate (TPLHMN=-1 TPLHTY=160ns TPLHMX=300ns
++                     TPHLMN=-1 TPHLTY=160ns TPHLMX=300ns)
+
+.ENDS CD4081B
+*
+
+.SUBCKT Digital_CD_CD4081  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 CD4081B
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line -10 20 0 -40 #000080 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component CD4094>
+  <Description>
+8 Bit Static Shift Register/Latch
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:Digital_CD_CD4094 _net7 _net8 _net9 _net10 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net11 _net12 _net13
+Sub:X1 _net7 _net8 _net9 _net10 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net11 _net12 _net13 gnd Type="CD4094_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "CD4094.cir.lst">
+  <Spice>
+*-------------------------------------------------------------CD4094B-----
+
+* 8 Bit Static Shift Register/Latch with Tri-State Outputs
+* National CMOS Logic Databook
+* jat 9/7/95
+
+.SUBCKT CD4094B STROBE DATA CLOCK OUTEN Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 QS QSPRIME
++ OPTIONAL:  VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
++ PARAMS:  MNTYMXDLY=0 IO_LEVEL=0
+
+U1 LOGICEXP(1,1) VDD VSS
++ CLOCK CLOCKBAR
++ D0_GATE IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ LOGIC:
++   CLOCKBAR = {~CLOCK}
+
+U2 DFF(8) VDD VSS
++ $D_HI $D_HI CLOCK
++ DATA Q1I Q2I Q3I Q4I Q5I Q6I Q7I
++ Q1I Q2I Q3I Q4I Q5I Q6I Q7I QSO
++ $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC
++ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U3 DFF(1) VDD VSS
++ $D_HI $D_HI CLOCKBAR
++ QSO QSPRIMEO $D_NC
++ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U4 DLTCH(8) VDD VSS
++ $D_HI $D_HI STROBE
++ Q1I Q2I Q3I Q4I Q5I Q6I Q7I QSO
++ Q1O Q2O Q3O Q4O Q5O Q6O Q7O Q8O 
++ $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC
++ D0_GFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U5 PINDLY(10,1,2) VDD VSS
++ Q1O Q2O Q3O Q4O Q5O Q6O Q7O Q8O QSO QSPRIMEO
++ OUTEN
++ STROBE CLOCK
++ Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 QS QSPRIME
++ IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ BOOLEAN:
++   UNLATCH = {CHANGED_LH(STROBE,0)}
++   EDGE = {CHANGED_LH(CLOCK,0)}
++ TRISTATE:
++   ENABLE HI = OUTEN
++      Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 = {
++         CASE(
++            TRN_Z$ | TRN_$Z, DELAY(-1,140NS,280NS),
++            UNLATCH & (TRN_LH | TRN_HL), DELAY(-1,290NS,580NS),
++            EDGE & (TRN_LH | TRN_HL), DELAY(-1,420NS,840NS),
++            DELAY(-1,421NS,841NS))}
++ PINDLY:
++   QS = {
++      CASE(
++         (TRN_LH | TRN_HL), DELAY(-1,300NS,600NS),
++          DELAY(-1,301NS,601NS))}
++ PINDLY:
++   QSPRIME= {
++      CASE(
++         (TRN_LH | TRN_HL), DELAY(-1,230NS,460NS),
++          DELAY(-1,231NS,461NS))}
+
+U6 CONSTRAINT(3) VDD VSS
++ CLOCK DATA STROBE
++ IO_4000B IO_LEVEL={IO_LEVEL}
++ SETUP_HOLD:
++   CLOCK LH = CLOCK
++   DATA(1) = DATA
++   SETUPTIME = 40NS
++ WIDTH:
++  NODE = CLOCK
++  MIN_HI = 100NS
++  MIN_LO = 100NS
++ WIDTH:
++  NODE = STROBE
++  MIN_HI = 100NS
++ FREQ: 
++  NODE = CLOCK
++  MAXFREQ = 3MEG
+
+.ENDS CD4094B
+
+.SUBCKT Digital_CD_CD4094  gnd _net7 _net8 _net9 _net10 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net11 _net12 _net13 
+X1 _net7 _net8 _net9 _net10 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net11 _net12 _net13 CD4094B
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Text 4 9 12 #000080 0 "QB">
+    <Text 4 -11 12 #000080 0 "QA">
+    <Text 4 29 12 #000080 0 "QC">
+    <Rectangle -30 -20 60 230 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Text 4 109 12 #000080 0 "QG">
+    <Text 4 129 12 #000080 0 "QH">
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 140 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <.PortSym 50 0 5 180 QA>
+    <.PortSym 50 20 6 180 QB>
+    <.PortSym 50 40 7 180 QC>
+    <.PortSym 50 60 8 180 QD>
+    <.PortSym 50 80 9 180 QE>
+    <.PortSym 50 100 10 180 QF>
+    <.PortSym 50 120 11 180 QG>
+    <.PortSym 50 140 12 180 QH>
+    <.ID -10 214 Y>
+    <Text 4 159 12 #000080 0 "QS">
+    <Line 30 170 20 0 #000080 2 1>
+    <Line 30 190 20 0 #000080 2 1>
+    <.PortSym 50 170 13 180 QS>
+    <.PortSym 50 190 14 180 QSP>
+    <.PortSym -50 0 4 0 OE>
+    <Line -50 0 20 0 #000080 2 1>
+    <Text -28 -10 12 #000080 0 "OE">
+    <Text -3 179 12 #000080 0 "QSP">
+    <Text 3 69 12 #000080 0 "QE">
+    <Text 3 50 12 #000080 0 "QD">
+    <Text 3 89 12 #000080 0 "QF">
+    <Line -50 60 20 0 #000080 2 1>
+    <Text -28 50 12 #000080 0 "D">
+    <.PortSym -50 100 3 0 CLK>
+    <Line -50 100 20 0 #000080 2 1>
+    <Line -15 100 -15 -10 #000080 2 1>
+    <Line -30 110 15 -10 #000080 2 1>
+    <.PortSym -50 60 2 0 D>
+    <Line -50 20 20 0 #000080 2 1>
+    <.PortSym -50 20 1 0 STB>
+    <Text -28 10 12 #000080 0 "STB">
+  </Symbol>
+</Component>
\ No newline at end of file
diff --git a/library/Digital_HC.lib b/library/Digital_HC.lib
index a14571e6..9c2b5cfc 100644
--- a/library/Digital_HC.lib
+++ b/library/Digital_HC.lib
@@ -2,8 +2,8 @@
 
 <Component 74HC00>
   <Description>
-2-Input Nand Gate
-
+2-Input NAND Gate
+XSPICE Based Model
 Requirements:
 .spiceinit: set ngbehavior=psa
 .PARAM: vcc=5
@@ -15,7 +15,7 @@ Sub:X1 _net0 _net1 _net2 gnd Type="n74HC00_cir"
   </Model>
   <ModelIncludes "74HC00.cir.lst">
   <Spice>
-* ----------------------------------------------------------- 74HC00 ------
+* ---------------------------------- 74HC00 -------------------------------
 *  Quad 2-Input Nand Gates
 *
 *  The High-Speed CMOS Logic Data Book, 1989, TI Pages 2-3 to 2-5
@@ -39,7 +39,7 @@ X1 _net0 _net1 _net2 74HC00
   </Spice>
   <Symbol>
     <EArc -30 -20 40 40 4320 2880 #000080 2 1>
-    <Line -10 20 0 -40 #000000 2 1>
+    <Line -10 20 0 -40 #000080 2 1>
     <Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
     <Line 10 0 20 0 #000080 2 1>
     <Line -30 -10 20 0 #000080 2 1>
@@ -53,8 +53,8 @@ X1 _net0 _net1 _net2 74HC00
 
 <Component 74HC02>
   <Description>
-2-Input Nor Gate
-
+2-Input NOR Gate
+XSPICE Based Model
 Requirements:
 .spiceinit: set ngbehavior=psa
 .PARAM: vcc=5
@@ -66,7 +66,7 @@ Sub:X1 _net0 _net2 _net1 gnd Type="n74HC02_cir"
   </Model>
   <ModelIncludes "74HC02.cir.lst">
   <Spice>
-* ----------------------------------------------------------- 74HC02 ------
+* ----------------------------------- 74HC02 ------------------------------
 *  Quad 2-Input Nor Gates
 *
 *  The High-Speed CMOS Logic Data Book, 1989, TI Pages 2-13 to 2-15
@@ -99,15 +99,15 @@ X1 _net0 _net2 _net1 74HC02
     <Line -30 -10 20 0 #000080 2 1>
     <Line -30 10 20 0 #000080 2 1>
     <EArc -20 -20 10 40 4320 2880 #000080 2 1>
-    <Line -10 20 -5 0 #000000 2 1>
-    <Line -10 -20 -5 0 #000000 2 1>
+    <Line -10 20 -5 0 #000080 2 1>
+    <Line -10 -20 -5 0 #000080 2 1>
   </Symbol>
 </Component>
 
 <Component 74HC04>
   <Description>
 Inverter
-
+XSPICE Based Model
 Requirements:
 .spiceinit: set ngbehavior=psa
 .PARAM: vcc=5
@@ -119,7 +119,7 @@ Sub:X1 _net0 _net1 gnd Type="n74HC04_cir"
   </Model>
   <ModelIncludes "74HC04.cir.lst">
   <Spice>
-* ----------------------------------------------------------- 74HC04 ------
+* ------------------------------- 74HC04 -------------------------
 *  Hex Inverters
 *
 *  The High-Speed CMOS Logic Data Book, 1989, TI Pages 2-23 to 2-25
@@ -143,7 +143,7 @@ X1 _net0 _net1 74HC04
   </Spice>
   <Symbol>
     <EArc -30 -20 40 40 4320 2880 #000080 2 1>
-    <Line -10 20 0 -40 #000000 2 1>
+    <Line -10 20 0 -40 #000080 2 1>
     <Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
     <Line 10 0 20 0 #000080 2 1>
     <.ID 10 14 Y>
@@ -155,8 +155,8 @@ X1 _net0 _net1 74HC04
 
 <Component 74HC08>
   <Description>
-2-Input And Gate
-
+2-Input AND Gate
+XSPICE Based Model
 Requirements:
 .spiceinit: set ngbehavior=psa
 .PARAM: vcc=5
@@ -168,7 +168,7 @@ Sub:X1 _net0 _net2 _net1 gnd Type="n74HC08_cir"
   </Model>
   <ModelIncludes "74HC08.cir.lst">
   <Spice>
-* ----------------------------------------------------------- 74HC08 ------
+* ---------------------------------- 74HC08 -----------------------
 *  Quad 2-Input And Gates   
 *
 *  The High-Speed CMOS Logic Data Book, 1989, TI Pages 2-37 to 2-39
@@ -196,7 +196,7 @@ X1 _net0 _net2 _net1 74HC08
     <.PortSym 30 0 3 180 P3>
     <.ID 10 14 Y>
     <EArc -30 -20 40 40 4320 2880 #000080 2 1>
-    <Line -10 20 0 -40 #000000 2 1>
+    <Line -10 20 0 -40 #000080 2 1>
     <Line 10 0 20 0 #000080 2 1>
     <Line -30 -10 20 0 #000080 2 1>
     <Line -30 10 20 0 #000080 2 1>
@@ -205,8 +205,8 @@ X1 _net0 _net2 _net1 74HC08
 
 <Component 74HC32>
   <Description>
-2-Input Or Gate
-
+2-Input OR Gate
+XSPICE Based Model
 Requirements:
 .spiceinit: set ngbehavior=psa
 .PARAM: vcc=5
@@ -218,7 +218,7 @@ Sub:X1 _net0 _net2 _net1 gnd Type="n74HC32_cir"
   </Model>
   <ModelIncludes "74HC32.cir.lst">
   <Spice>
-* ----------------------------------------------------------- 74HC32 ------
+* ---------------------------------- 74HC32 ------------------------
 *  Quad 2-Input Or Gates
 *
 *  The High-Speed CMOS Logic Data Book, 1989, TI Pages 2-77 to 2-79
@@ -250,15 +250,15 @@ X1 _net0 _net2 _net1 74HC32
     <Line -30 -10 20 0 #000080 2 1>
     <Line -30 10 20 0 #000080 2 1>
     <EArc -20 -20 10 40 4320 2880 #000080 2 1>
-    <Line -10 20 -5 0 #000000 2 1>
-    <Line -10 -20 -5 0 #000000 2 1>
+    <Line -10 20 -5 0 #000080 2 1>
+    <Line -10 -20 -5 0 #000080 2 1>
   </Symbol>
 </Component>
 
 <Component 74HC74>
   <Description>
 D-Type Positive Edge Triggered Flip-Flop With Preset And Clear
-
+XSPICE Based Model
 Requirements:
 .spiceinit: set ngbehavior=psa
 .PARAM: vcc=5
@@ -270,7 +270,7 @@ Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 gnd Type="n74HC74_cir"
   </Model>
   <ModelIncludes "74HC74.cir.lst">
   <Spice>
-* ----------------------------------------------------------- 74HC74 ------
+* --------------------------------- 74HC74 -------------------------
 *  Dual D-Type Positive Edge Triggered Flip-Flops With  Preset And Clear
 *
 *  The High-Speed CMOS Logic Data Book, 1989, TI Pages 2-101 to 2-103
@@ -326,8 +326,8 @@ X1 _net0 _net1 _net2 _net3 _net4 _net5 74HC74
 
 <Component 74HC86>
   <Description>
-2-Input Exclusive-Or Gate
-
+2-Input Exclusive-OR Gate
+XSPICE Based Model
 Requirements:
 .spiceinit: set ngbehavior=psa
 .PARAM: vcc=5
@@ -339,7 +339,7 @@ Sub:X1 _net0 _net2 _net1 gnd Type="n74HC86_cir"
   </Model>
   <ModelIncludes "74HC86.cir.lst">
   <Spice>
-* ----------------------------------------------------------- 74HC86 ------
+* --------------------------------- 74HC86 ------------------------
 *  Quad 2-Input Exclusive-Or Gates
 *
 *  The High-Speed CMOS Logic Data Book, 1989, TI Pages 2-129 to 2-131
@@ -377,8 +377,8 @@ X1 _net0 _net2 _net1 74HC86
 
 <Component 74HC132>
   <Description>
-2-Input Nand Gate
-
+2-Input NAND Gate
+XSPICE Based Model
 Requirements:
 .spiceinit: set ngbehavior=psa
 .PARAM: vcc=5
@@ -390,7 +390,7 @@ Sub:X1 _net0 _net2 _net1 gnd Type="n74HC132_cir"
   </Model>
   <ModelIncludes "74HC132.cir.lst">
   <Spice>
-* ----------------------------------------------------------- 74HC132 ------
+* ---------------------------------- 74HC132 ----------------------------
 *  Quad 2-Input Nand Schmitt Triggers
 *
 *  The High-Speed CMOS Logic Data Book, 1989, TI Pages 2-159 to 2-161
@@ -416,7 +416,7 @@ X1 _net0 _net2 _net1 74HC132
     <.PortSym -30 10 2 0 P2>
     <.PortSym 30 0 3 180 P3>
     <EArc -30 -20 40 40 4320 2880 #000080 2 1>
-    <Line -10 20 0 -40 #000000 2 1>
+    <Line -10 20 0 -40 #000080 2 1>
     <Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
     <Line 10 0 20 0 #000080 2 1>
     <Line -30 -10 20 0 #000080 2 1>
@@ -430,3 +430,971 @@ X1 _net0 _net2 _net1 74HC132
   </Symbol>
 </Component>
 
+<Component 74HC164>
+  <Description>
+8-Bit Parallel-Out Serial Shift Register
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_HC_74HC164 _net0 _net1 _net3 _net2 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11
+Sub:X1 _net0 _net1 _net3 _net2 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 gnd Type="n74HC164_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74HC164.cir.lst">
+  <Spice>
+* ------------------------------- 74HC164 ----------------------------------
+*  8-Bit Parallel-Out Serial Shift Register
+*
+*  The High Speed CMOS Logic Data Book, 1989, TI Pages 2-231 to 2-234
+*  jds    3/28/94
+*
+.SUBCKT 74HC164B A B CLRBAR CLK QA QB QC QD QE QF QG QH
++  optional: DPWR=$G_DPWR DGND=$G_DGND
++  params: MNTYMXDLY=0 IO_LEVEL=0
+
+U74HC164 LOGICEXP (3,3) DPWR DGND
++        CLK A B
++        r0 s0 clkbar
++        D0_GATE IO_HC IO_LEVEL={IO_LEVEL}
++
++    LOGIC:
++      r0 = { (~(A & B)) }
++      s0 = { (~r0) }
++      clkbar = { (~CLK) }
+
+
+uf0  JKff(8)  DPWR DGND
++    $D_HI CLRBAR clkbar
++    s0 QA_O QB_O QC_O QD_O QE_O QF_O QG_O
++    r0 qabar qbbar qcbar qdbar qebar qfbar qgbar
++    QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O
++    qabar qbbar qcbar qdbar qebar qfbar qgbar qhbar
++    D0_EFF IO_HC
+
+Udly PINDLY (8,0,4) DPWR DGND
++    QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O
++    CLRBAR CLK A B
++    QA QB QC QD QE QF QG QH
++    IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++
++    BOOLEAN:
++       DATA=  { ( CHANGED(A,0) | CHANGED(B,0) ) }
++       CLOCK= { CHANGED(CLK,0) }
++       CLEAR= { CHANGED(CLRBAR,0) }
++
++    PINDLY:
++       QA QB QC QD QE QF QG QH  = {
++                   CASE(
++                       CLEAR & TRN_HL, DELAY(-1,28ns,41ns),
++                       CLOCK & TRN_LH, DELAY(-1,23ns,35ns),
++                       CLOCK & TRN_HL, DELAY(-1,23ns,35ns),
++                       DELAY(-1,29ns,42ns)
++                       )
++                     }
+
+Ucnstr CONSTRAINT(4) DPWR DGND
++          CLRBAR CLK  A B
++          IO_HC
++
++      FREQ:
++         NODE = CLK
++         MAXFREQ = 31MEG
++      WIDTH:
++         NODE = CLK
++         MIN_LO = 16ns
++         MIN_HI = 16ns
++      WIDTH:
++         NODE = CLRBAR
++         MIN_LO = 20ns
++      SETUP_HOLD:
++        CLOCK LH = CLK
++        DATA(2) = A B
++        SETUPTIME = 20ns
++        HOLDTIME = 5ns
++        WHEN = { CLRBAR != '0 }
++      SETUP_HOLD:
++        DATA(1) = CLRBAR
++        CLOCK LH = CLK
++        SETUPTIME = 20ns
+
+.ENDS 74HC164B
+*
+
+.SUBCKT Digital_HC_74HC164  gnd _net0 _net1 _net3 _net2 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 
+X1 _net0 _net1 _net3 _net2 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 74HC164B
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Text 4 9 12 #000080 0 "QB">
+    <Text 4 -11 12 #000080 0 "QA">
+    <Text 4 29 12 #000080 0 "QC">
+    <Text 4 49 12 #000080 0 "QD">
+    <Text 4 69 12 #000080 0 "QE">
+    <Line -50 0 20 0 #000080 2 1>
+    <Text -28 -10 12 #000080 0 "A">
+    <Rectangle -30 -20 60 180 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Text 4 89 12 #000080 0 "QF">
+    <Text 4 109 12 #000080 0 "QG">
+    <Text 4 129 12 #000080 0 "QH">
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 140 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <Line -50 20 20 0 #000080 2 1>
+    <Line -50 60 20 0 #000080 2 1>
+    <Text -28 10 12 #000080 0 "B">
+    <Text -28 50 12 #000080 0 "CLR">
+    <Ellipse -31 56 -8 8 #000080 1 1 #000080 1 1>
+    <Line -50 140 20 0 #000080 2 1>
+    <Line -15 140 -15 -10 #000080 2 1>
+    <Line -30 150 15 -10 #000080 2 1>
+    <.PortSym -50 60 3 0 CLRBAR>
+    <.ID -10 164 Y>
+    <.PortSym -50 0 1 0 A>
+    <.PortSym -50 20 2 0 B>
+    <.PortSym -50 140 4 0 CLK>
+    <.PortSym 50 0 5 180 QA>
+    <.PortSym 50 20 6 180 QB>
+    <.PortSym 50 40 7 180 QC>
+    <.PortSym 50 60 8 180 QD>
+    <.PortSym 50 80 9 180 QE>
+    <.PortSym 50 100 10 180 QF>
+    <.PortSym 50 120 11 180 QG>
+    <.PortSym 50 140 12 180 QH>
+  </Symbol>
+</Component>
+
+<Component 74HC4017>
+  <Description>
+5-stage Johnson Decade Counter
+with 10 Decoded Outputs
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:Digital_HC_74HC4017 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13
+Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 gnd Type="n74HC4017_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74HC4017.cir.lst">
+  <Spice>
+*-----------------------------74HC4017-----------------------------
+
+* Decade Counters/Dividers
+* TI High-Speed CMOS Logic Data Book, 1989, pages 2-625 to 2-629
+* jat 12/29/95
+
+.SUBCKT 74HC4017B CLKENBAR CLK CLR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 CO
++ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
++ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 LOGICEXP(13,14) DPWR DGND
++ CLK CLKENBAR CLR Q1 Q2 Q3 Q4 Q5 Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR
++ CLOCK CLRBAR D3 Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O Y8O Y9O COO
++ D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ LOGIC:
++   CLOCK = {CLK & (~CLKENBAR)}
++   CLRBAR ={~CLR}
++   D3 = {Q2 & (Q1 | Q3)}
++   Y0O = {Q1BAR & Q5BAR}
++   Y1O = {Q1 & Q2BAR}
++   Y2O = {Q2 & Q3BAR}
++   Y3O = {Q3 & Q4BAR}
++   Y4O = {Q4 & Q5BAR}
++   Y5O = {Q1 & Q5}
++   Y6O = {Q2 & Q1BAR}
++   Y7O = {Q3 & Q2BAR}
++   Y8O = {Q4 & Q3BAR}
++   Y9O = {Q5 & Q4BAR}
++   COO = {Q5BAR}
+
+U2 DFF(5) DPWR DGND
++ $D_HI CLRBAR CLOCK
++ Q5BAR Q1 D3 Q3 Q4
++ Q1 Q2 Q3 Q4 Q5
++ Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U3 PINDLY(11,0,3) DPWR DGND
++ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O Y8O Y9O COO
++ CLR CLKENBAR CLK
++ Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 CO
++ IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ BOOLEAN:
++  CLEAR = {CHANGED(CLR,0)}
++  ENAB = {CHANGED(CLKENBAR,0)}
++  EDGE = {CHANGED_LH(CLK,0)}
++ PINDLY:
++  Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9  = {
++    CASE(
++        CLEAR & (TRN_LH | TRN_HL), DELAY(-1,23NS,46NS),
++        ENAB & (TRN_LH | TRN_HL), DELAY(-1,25NS,50NS),
++        EDGE & (TRN_LH | TRN_HL), DELAY(-1,23NS,46NS),
++        DELAY(-1,26NS,51NS))}
++ PINDLY:
++    CO = {
++      CASE(
++        CLEAR & TRN_LH, DELAY(-1,23NS,46NS),
++        ENAB & (TRN_LH | TRN_HL), DELAY(-1,25NS,50NS),
++        EDGE & (TRN_LH | TRN_HL), DELAY(-1,23NS,46NS),
++        DELAY(-1,26NS,51NS))}
+
+U4 CONSTRAINT(3) DPWR DGND
++ CLK CLKENBAR CLR
++ IO_HC IO_LEVEL={IO_LEVEL}
++ FREQ:
++  NODE = CLK
++  MAXFREQ = 31MEG
++ FREQ:
++  NODE = CLKENBAR
++  MAXFREQ = 31MEG
++ WIDTH:
++  NODE = CLK
++  MIN_LO = 16NS
++  MIN_HI = 16NS
++ WIDTH:
++  NODE = CLKENBAR
++  MIN_LO = 16NS
++  MIN_HI = 16NS
++ WIDTH:
++  NODE = CLR
++  MIN_HI = 16NS
++ SETUP_HOLD:
++  CLOCK LH = CLK
++  DATA(1) = CLKENBAR
++  SETUPTIME_LO = 10NS
++  HOLDTIME_LO = 5NS
++ SETUP_HOLD:
++  CLOCK HL = CLKENBAR
++  DATA(1) = CLK
++  SETUPTIME_HI = 10NS
++  HOLDTIME_HI = 5NS
++ SETUP_HOLD:
++  CLOCK LH = CLK
++  DATA(1) = CLR
++  SETUPTIME_LO = 10NS
++ SETUP_HOLD:
++  CLOCK HL = CLKENBAR
++  DATA(1) = CLR
++  SETUPTIME_LO = 10NS
+
+.ENDS 74HC4017
+
+.SUBCKT Digital_HC_74HC4017  gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 
+X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 74HC4017B
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Text 4 -11 12 #000080 0 "Q0">
+    <Text 4 29 12 #000080 0 "Q2">
+    <Text 4 49 12 #000080 0 "Q3">
+    <Text 4 69 12 #000080 0 "Q4">
+    <Rectangle -30 -20 60 250 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Text 4 109 12 #000080 0 "Q6">
+    <Text 4 129 12 #000080 0 "Q7">
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 140 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <Line 30 160 20 0 #000080 2 1>
+    <Line 30 180 20 0 #000080 2 1>
+    <Text 4 169 12 #000080 0 "Q9">
+    <Line -50 0 20 0 #000080 2 1>
+    <Line -15 0 -15 -10 #000080 2 1>
+    <Line -30 10 15 -10 #000080 2 1>
+    <Line -50 60 20 0 #000080 2 1>
+    <Text -28 50 12 #000080 0 "CLR">
+    <Text 4 9 12 #000080 0 "Q1">
+    <Text 4 89 12 #000080 0 "Q5">
+    <Text 4 149 12 #000080 0 "Q8">
+    <.ID -10 234 Y>
+    <.PortSym -50 60 3 0 CLR>
+    <Text -28 10 12 #000080 0 "ENB">
+    <Line 30 210 20 0 #000080 2 1>
+    <Text -16 199 12 #000080 0 "COUT">
+    <Line -50 20 20 0 #000080 2 1>
+    <Ellipse -31 16 -8 8 #000080 1 1 #000080 1 1>
+    <.PortSym 50 210 14 180 CO>
+    <.PortSym -50 20 1 0 CLKENB>
+    <.PortSym -50 0 2 0 CLK>
+    <.PortSym 50 20 5 180 Y1>
+    <.PortSym 50 40 6 180 Y2>
+    <.PortSym 50 60 7 180 Y3>
+    <.PortSym 50 80 8 180 Y4>
+    <.PortSym 50 100 9 180 Y5>
+    <.PortSym 50 120 10 180 Y6>
+    <.PortSym 50 140 11 180 Y7>
+    <.PortSym 50 160 12 180 Y8>
+    <.PortSym 50 180 13 180 Y9>
+    <.PortSym 50 0 4 180 Y0>
+  </Symbol>
+</Component>
+
+<Component 74HC4020>
+  <Description>
+14-Stage Binary Ripple Counter
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:Digital_HC_74HC4020 _net1 _net2 _net0 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13
+Sub:X1 _net1 _net2 _net0 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 gnd Type="n74HC4020_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74HC4020.cir.lst">
+  <Spice>
+* ---------------------------- 74HC4020 -------------------------------------
+*  Asynchronous 14-Bit Binary Counters
+*
+*  The High Speed CMOS Logic Data Book, 1989, TI Pages 2-631 to 2-634
+*  bss    6/28/94
+*
+.SUBCKT 74HC402B CLK CLR QA QD QE QF QG QH QI QJ QK QL QM QN 
++     optional:  DPWR=$G_DPWR DGND=$G_DGND
++     params:  MNTYMXDLY=0 IO_LEVEL=0
+
+U1 inv DPWR DGND
++     CLR RESETBAR
++     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U2 JKFF(1) DPWR DGND
++     $D_HI RESETBAR CLK $D_HI $D_HI QA_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U3 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QA_O $D_HI $D_HI QB_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U4 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QB_O $D_HI $D_HI QC_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U5 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QC_O $D_HI $D_HI QD_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U6 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QD_O $D_HI $D_HI QE_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U7 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QE_O $D_HI $D_HI QF_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U8 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QF_O $D_HI $D_HI QG_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U9 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QG_O $D_HI $D_HI QH_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U10 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QH_O $D_HI $D_HI QI_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U11 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QI_O $D_HI $D_HI QJ_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U12 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QJ_O $D_HI $D_HI QK_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U13 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QK_O $D_HI $D_HI QL_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U14 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QL_O $D_HI $D_HI QM_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U15 JKFF(1) DPWR DGND
++     $D_HI RESETBAR QM_O $D_HI $D_HI QN_O $D_NC
++     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U16DLY PINDLY(12,0,2) DPWR DGND
++     QA_O QD_O QE_O QF_O QG_O QH_O QI_O QJ_O QK_O QL_O QM_O QN_O
++     CLR CLK
++     QA QD QE QF QG QH QI QJ QK QL QM QN
++     IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++
++  BOOLEAN:
++     CLOCK = {CHANGED_HL(CLK,0)}
++     CLEAR = {CHANGED_LH(CLR,0)}
++
++  PINDLY:
++     QA = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,16ns,30ns),
++         CLOCK & TRN_HL, DELAY(-1,16ns,30ns),
++         DELAY(-1,18ns,31ns))}
++
++     QD = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,40ns,75ns),
++         CLOCK & TRN_HL, DELAY(-1,40ns,75ns),
++         DELAY(-1,41ns,76ns))}
++
++     QE = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,48ns,90ns),
++         CLOCK & TRN_HL, DELAY(-1,48ns,90ns),
++         DELAY(-1,49ns,91ns))}
++
++     QF = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,56ns,105ns),
++         CLOCK & TRN_HL, DELAY(-1,56ns,105ns),
++         DELAY(-1,57ns,106ns))}
++
++     QG = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,64ns,120ns),
++         CLOCK & TRN_HL, DELAY(-1,64ns,120ns),
++         DELAY(-1,65ns,121ns))}
++
++     QH = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,72ns,135ns),
++         CLOCK & TRN_HL, DELAY(-1,72ns,135ns),
++         DELAY(-1,73ns,136ns))}
++
++     QI = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,80ns,150ns),
++         CLOCK & TRN_HL, DELAY(-1,80ns,150ns),
++         DELAY(-1,81ns,151ns))}
++
++     QJ = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,88ns,165ns),
++         CLOCK & TRN_HL, DELAY(-1,88ns,165ns),
++         DELAY(-1,89ns,166ns))}
++
++     QK = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,96ns,180ns),
++         CLOCK & TRN_HL, DELAY(-1,96ns,180ns),
++         DELAY(-1,97ns,181ns))}
++
++     QL = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,104ns,195ns),
++         CLOCK & TRN_HL, DELAY(-1,104ns,195ns),
++         DELAY(-1,105ns,196ns))}
++
++     QM = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,112ns,210ns),
++         CLOCK & TRN_HL, DELAY(-1,112ns,210ns),
++         DELAY(-1,113ns,211ns))}
++
++     QN = {
++       CASE(
++         CLEAR & TRN_HL, DELAY(-1,17ns,28ns),
++         CLOCK & TRN_LH, DELAY(-1,120ns,225ns),
++         CLOCK & TRN_HL, DELAY(-1,120ns,225ns),
++         DELAY(-1,121ns,226ns))}
+
+U17CON CONSTRAINT(2) DPWR DGND
++     CLK CLR
++     IO_HC IO_LEVEL={IO_LEVEL}
++
++  WIDTH:
++     NODE=CLR
++     MIN_HI=18ns
++
++  WIDTH:
++     NODE=CLK
++     MIN_HI=23ns
++     MIN_LO=23ns
++
++	SETUP_HOLD:
++		CLOCK HL=CLK
++		DATA(1)=CLR
++		SETUPTIME_LO=15ns
+
+.ENDS 74HC4020B
+*
+
+.SUBCKT Digital_HC_74HC4020  gnd _net1 _net2 _net0 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 
+X1 _net1 _net2 _net0 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 74HC402B
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Text 4 9 12 #000080 0 "QD">
+    <Text 4 -11 12 #000080 0 "QA">
+    <Text 4 29 12 #000080 0 "QE">
+    <Text 4 49 12 #000080 0 "QF">
+    <Text 4 69 12 #000080 0 "QG">
+    <Rectangle -30 -20 60 260 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Text 4 89 12 #000080 0 "QH">
+    <Text 4 129 12 #000080 0 "QJ">
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 140 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <Line 30 160 20 0 #000080 2 1>
+    <Line 30 180 20 0 #000080 2 1>
+    <Line 30 200 20 0 #000080 2 1>
+    <Line 30 220 20 0 #000080 2 1>
+    <.PortSym 50 0 3 180 QA>
+    <.PortSym 50 40 5 180 QE>
+    <.PortSym 50 60 6 180 QF>
+    <.PortSym 50 80 7 180 QG>
+    <.PortSym 50 100 8 180 QH>
+    <.PortSym 50 120 9 180 QI>
+    <.PortSym 50 140 10 180 QJ>
+    <.PortSym 50 160 11 180 QK>
+    <.PortSym 50 180 12 180 QL>
+    <Text 4 149 12 #000080 0 "QK">
+    <Text 4 209 12 #000080 0 "QN">
+    <.ID -10 244 Y>
+    <.PortSym 50 200 13 180 QM>
+    <.PortSym 50 220 14 180 QN>
+    <Line -50 0 20 0 #000080 2 1>
+    <Line -15 0 -15 -10 #000080 2 1>
+    <Line -30 10 15 -10 #000080 2 1>
+    <Line -50 60 20 0 #000080 2 1>
+    <Text -28 50 12 #000080 0 "CLR">
+    <.PortSym 50 20 4 180 QD>
+    <.PortSym -50 60 2 0 CLR>
+    <.PortSym -50 0 1 0 CLK>
+    <Text 4 109 12 #000080 0 "QI">
+    <Text 4 169 12 #000080 0 "QL">
+    <Text 4 189 12 #000080 0 "QM">
+  </Symbol>
+</Component>
+
+<Component 74HC4024>
+  <Description>
+7-Stage Binary Ripple Counter
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:Digital_HC_74HC4024 _net7 _net8 _net0 _net1 _net2 _net3 _net4 _net5 _net6
+Sub:X1 _net7 _net8 _net0 _net1 _net2 _net3 _net4 _net5 _net6 gnd Type="n74HC4024_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74HC4024.cir.lst">
+  <Spice>
+*-----------------------------74HC4024-----------------------------------
+
+* The 74HC4024 Asynchronous 7-Bit Binary Counter
+* TI High Speed CMOS Logic Data Book, 1989, pages 2-635 to 2-638
+* jat 8/9/95
+
+.SUBCKT 74HC4024B CLK CLR QA QB QC QD QE QF QG
++ OPTIONAL:  DPWR=$G_DPWR DGND=$G_DGND
++ PARAMS:  MNTYMXDLY=0 IO_LEVEL=0
+
+U1 LOGICEXP(2,2) DPWR DGND
++ CLR CLK
++ CLOCKA CLRBAR
++ D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ LOGIC:
++  CLOCKA = {CLK & (~CLR)}
++  CLRBAR = {~CLR}
+
+U2 JKFF(1) DPWR DGND 
++ $D_HI CLRBAR CLOCKA 
++ $D_HI $D_HI Q_A $D_NC 
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U3 JKFF(1) DPWR DGND
++ $D_HI CLRBAR Q_A
++ $D_HI $D_HI Q_B $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U4 JKFF(1) DPWR DGND
++ $D_HI CLRBAR Q_B
++ $D_HI $D_HI Q_C $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ 
+U5 JKFF(1) DPWR DGND
++ $D_HI CLRBAR Q_C
++ $D_HI $D_HI Q_D $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U6 JKFF(1) DPWR DGND
++ $D_HI CLRBAR Q_D
++ $D_HI $D_HI Q_E $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U7 JKFF(1) DPWR DGND
++ $D_HI CLRBAR Q_E
++ $D_HI $D_HI Q_F $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U8 JKFF(1) DPWR DGND
++ $D_HI CLRBAR Q_F
++ $D_HI $D_HI Q_G $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U9 PINDLY(7,0,2) DPWR DGND
++ Q_A Q_B Q_C Q_D Q_E Q_F Q_G
++ CLR CLOCKA
++ QA QB QC QD QE QF QG
++ IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ BOOLEAN:
++          CLEAR = {CHANGED_LH(CLR,0)}
++          ACLK = {CHANGED_HL(CLOCKA,0)}
++ PINDLY:
++          QA = {
++            CASE(
++               CLEAR & TRN_HL, DELAY(-1,17NS,26NS),
++               ACLK & (TRN_LH | TRN_HL), DELAY(-1,16NS,24NS),
++               DELAY(-1,18NS,27NS))}
++          QB = {
++            CASE(
++               CLEAR & TRN_HL, DELAY(-1,17NS,26NS),
++               ACLK & (TRN_LH | TRN_HL), DELAY(-1,24NS,39NS),
++               DELAY(-1,25NS,40NS))}
++          QC = {
++            CASE(
++               CLEAR & TRN_HL, DELAY(-1,17NS,26NS),
++               ACLK & (TRN_LH | TRN_HL), DELAY(-1,32NS,54NS),
++               DELAY(-1,33NS,55NS))}
++          QD = {
++            CASE(
++               CLEAR & TRN_HL, DELAY(-1,17NS,26NS),
++               ACLK & (TRN_LH | TRN_HL), DELAY(-1,40NS,69NS),
++               DELAY(-1,41NS,70NS))}
++          QE = {
++            CASE(
++               CLEAR & TRN_HL, DELAY(-1,17NS,26NS),
++               ACLK & (TRN_LH | TRN_HL), DELAY(-1,48NS,84NS),
++               DELAY(-1,49NS,85NS))}
++          QF = {
++            CASE(
++               CLEAR & TRN_HL, DELAY(-1,17NS,26NS),
++               ACLK & (TRN_LH | TRN_HL), DELAY(-1,56NS,99NS),
++               DELAY(-1,57NS,100NS))}
++          QG = {
++            CASE(
++               CLEAR & TRN_HL, DELAY(-1,17NS,26NS),
++               ACLK & (TRN_LH | TRN_HL), DELAY(-1,64NS,114NS),
++               DELAY(-1,65NS,115NS))}
+
+U10 CONSTRAINT(2) DPWR DGND
++ CLK CLR
++ IO_HC IO_LEVEL={IO_LEVEL}
++ SETUP_HOLD:
++             CLOCK HL = CLK
++             DATA(1) = CLR
++             SETUPTIME_LO = 20NS
++ WIDTH:
++             NODE = CLK
++             MIN_HI = 23NS
++             MIN_LO = 23NS
++ WIDTH:
++             NODE = CLR
++             MIN_HI = 20NS
++ FREQ:
++             NODE = CLK
++             MAXFREQ = 22MEG
+
+.ENDS 74HC4024B
+
+.SUBCKT Digital_HC_74HC4024  gnd _net7 _net8 _net0 _net1 _net2 _net3 _net4 _net5 _net6 
+X1 _net7 _net8 _net0 _net1 _net2 _net3 _net4 _net5 _net6 74HC4024B
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Text 4 9 12 #000080 0 "QB">
+    <Text 4 -11 12 #000080 0 "QA">
+    <Text 4 29 12 #000080 0 "QC">
+    <Text 4 49 12 #000080 0 "QD">
+    <Text 4 69 12 #000080 0 "QE">
+    <Rectangle -30 -20 60 160 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Text 4 89 12 #000080 0 "QF">
+    <Text 4 109 12 #000080 0 "QG">
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <.PortSym 50 0 3 180 QA>
+    <.PortSym 50 20 4 180 QB>
+    <.PortSym 50 40 5 180 QC>
+    <.PortSym 50 60 6 180 QD>
+    <.PortSym 50 80 7 180 QE>
+    <.PortSym 50 100 8 180 QF>
+    <.PortSym 50 120 9 180 QG>
+    <Line -50 0 20 0 #000080 2 1>
+    <Line -15 0 -15 -10 #000080 2 1>
+    <Line -30 10 15 -10 #000080 2 1>
+    <Line -50 60 20 0 #000080 2 1>
+    <Text -28 50 12 #000080 0 "CLR">
+    <.PortSym -50 60 2 0 CLR>
+    <.PortSym -50 0 1 0 CLK>
+    <.ID -10 144 Y>
+  </Symbol>
+</Component>
+
+<Component 74HC4040>
+  <Description>
+12-Stage Binary Ripple Counter
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:Digital_HC_74HC4040 _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11
+Sub:X1 _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 gnd Type="n74HC4040_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74HC4040.cir.lst">
+  <Spice>
+*---------------------------------------------------------74HC4040-------
+
+* The 74HC4040 Asynchronous 12 Bit Binary Counter
+* TI High Speed CMOS Logic Data Book, 1989, pages 2-639 to 2-642
+* jat 8/10/95
+
+.SUBCKT 74HC4040B CLR CLK QA QB QC QD QE QF QG QH QI QJ QK QL
++ OPTIONAL:  DPWR=$G_DPWR DGND=$G_DGND
++ PARAMS:  MNTYMXDLY=0 IO_LEVEL=0
+
+U1 LOGICEXP(1,1) DPWR DGND
++ CLR
++ RESETBAR
++ D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ LOGIC:
++        RESETBAR = {~CLR}
+
+U2 JKFF(1) DPWR DGND
++ $D_HI RESETBAR CLK
++ $D_HI $D_HI Q_A $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U3 JKFF(1) DPWR DGND
++ $D_HI RESETBAR Q_A
++ $D_HI $D_HI Q_B $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U4 JKFF(1) DPWR DGND
++ $D_HI RESETBAR Q_B
++ $D_HI $D_HI Q_C $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U5 JKFF(1) DPWR DGND
++ $D_HI RESETBAR Q_C
++ $D_HI $D_HI Q_D $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U6 JKFF(1) DPWR DGND
++ $D_HI RESETBAR Q_D
++ $D_HI $D_HI Q_E $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U7 JKFF(1) DPWR DGND
++ $D_HI RESETBAR Q_E
++ $D_HI $D_HI Q_F $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U8 JKFF(1) DPWR DGND
++ $D_HI RESETBAR Q_F
++ $D_HI $D_HI Q_G $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U9 JKFF(1) DPWR DGND
++ $D_HI RESETBAR Q_G
++ $D_HI $D_HI Q_H $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U10 JKFF(1) DPWR DGND
++ $D_HI RESETBAR Q_H
++ $D_HI $D_HI Q_I $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U11 JKFF(1) DPWR DGND
++ $D_HI RESETBAR Q_I
++ $D_HI $D_HI Q_J $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U12 JKFF(1) DPWR DGND
++ $D_HI RESETBAR Q_J
++ $D_HI $D_HI Q_K $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U13 JKFF(1) DPWR DGND
++ $D_HI RESETBAR Q_K
++ $D_HI $D_HI Q_L $D_NC
++ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U14 PINDLY(12,0,2) DPWR DGND
++ Q_A Q_B Q_C Q_D Q_E Q_F Q_G Q_H Q_I Q_J Q_K Q_L
++ CLR CLK
++ QA QB QC QD QE QF QG QH QI QJ QK QL
++ IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ BOOLEAN:
++          CLEAR = {CHANGED_LH(CLR,0)}
++          ACLK = {CHANGED_HL(CLK,0)}
++ PINDLY:
++          QA = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,16NS,30NS),
++              DELAY(-1,17NS,31NS))}
++          QB = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,24NS,45NS),
++              DELAY(-1,25NS,46NS))}
++          QC = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,32NS,60NS),
++              DELAY(-1,33NS,61NS))}
++          QD = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,40NS,75NS),
++              DELAY(-1,41NS,76NS))}
++          QE = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,48NS,90NS),
++              DELAY(-1,49NS,91NS))}
++          QF = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,56NS,105NS),
++              DELAY(-1,57NS,106NS))}
++          QG = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,64NS,120NS),
++              DELAY(-1,65NS,121NS))}
++          QH = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,72NS,135NS),
++              DELAY(-1,73NS,136NS))}
++          QI = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,80NS,150NS),
++              DELAY(-1,81NS,151NS))}
++          QJ = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,88NS,165NS),
++              DELAY(-1,89NS,166NS))}
++          QK = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,96NS,180NS),
++              DELAY(-1,97NS,181NS))}
++          QL = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,17NS,28NS),
++              ACLK & (TRN_LH | TRN_HL), DELAY(-1,104NS,195NS),
++              DELAY(-1,105NS,196NS))}
+
+U15 CONSTRAINT(2) DPWR DGND
++ CLK CLR
++ IO_HC IO_LEVEL={IO_LEVEL}
++ SETUP_HOLD:
++             CLOCK HL = CLK
++             DATA(1) = CLR
++             SETUPTIME_LO = 15NS
++ WIDTH:
++             NODE = CLK
++             MIN_HI = 23NS
++             MIN_LO = 23NS
++ WIDTH:
++             NODE = CLR
++             MIN_HI = 18NS
++ FREQ:
++             NODE = CLK
++             MAXFREQ = 22MEG
+
+.ENDS 74HC4040B
+
+.SUBCKT Digital_HC_74HC4040  gnd _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 
+X1 _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 74HC4040B
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Text 4 9 12 #000080 0 "QB">
+    <Text 4 -11 12 #000080 0 "QA">
+    <Text 4 29 12 #000080 0 "QC">
+    <Text 4 49 12 #000080 0 "QD">
+    <Text 4 69 12 #000080 0 "QE">
+    <Rectangle -30 -20 60 260 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Text 4 89 12 #000080 0 "QF">
+    <Text 4 109 12 #000080 0 "QG">
+    <Text 4 129 12 #000080 0 "QH">
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 140 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <Line 30 160 20 0 #000080 2 1>
+    <Line 30 180 20 0 #000080 2 1>
+    <Line 30 200 20 0 #000080 2 1>
+    <Line 30 220 20 0 #000080 2 1>
+    <.PortSym 50 0 3 180 QA>
+    <.PortSym 50 20 4 180 QB>
+    <.PortSym 50 40 5 180 QC>
+    <.PortSym 50 60 6 180 QD>
+    <.PortSym 50 80 7 180 QE>
+    <.PortSym 50 100 8 180 QF>
+    <.PortSym 50 120 9 180 QG>
+    <.PortSym 50 140 10 180 QH>
+    <.PortSym 50 160 11 180 QI>
+    <.PortSym 50 180 12 180 QJ>
+    <Text 4 149 12 #000080 0 "QI">
+    <Text 4 169 12 #000080 0 "QJ">
+    <Text 4 189 12 #000080 0 "QK">
+    <Text 4 209 12 #000080 0 "QL">
+    <.ID -10 244 Y>
+    <.PortSym 50 200 13 180 QK>
+    <.PortSym 50 220 14 180 QL>
+    <Line -50 0 20 0 #000080 2 1>
+    <Line -15 0 -15 -10 #000080 2 1>
+    <Line -30 10 15 -10 #000080 2 1>
+    <Line -50 60 20 0 #000080 2 1>
+    <Text -28 50 12 #000080 0 "CLR">
+    <.PortSym -50 0 2 0 CLK>
+    <.PortSym -50 60 1 0 CLR>
+  </Symbol>
+</Component>
\ No newline at end of file
diff --git a/library/Digital_LV.lib b/library/Digital_LV.lib
index 329c7395..5e1ad39e 100644
--- a/library/Digital_LV.lib
+++ b/library/Digital_LV.lib
@@ -1,9 +1,9 @@
-<Qucs Library 24.3.99 "Digital_LV">
+<Qucs Library 24.4.99 "Digital_LV">
 
 <Component 74LV00>
   <Description>
-2-Input Nand Gate
-
+2-Input NAND Gate
+XSPICE Based Model
 Requirements:
 .spiceinit: set ngbehavior=psa
 .PARAM: vcc=5
@@ -43,7 +43,6 @@ X1 _net0 _net1 _net2 74LV00A
   </Spice>
   <Symbol>
     <EArc -30 -20 40 40 4320 2880 #000080 2 1>
-    <Line -10 20 0 -40 #000000 2 1>
     <Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
     <Line 10 0 20 0 #000080 2 1>
     <Line -30 -10 20 0 #000080 2 1>
@@ -52,13 +51,280 @@ X1 _net0 _net1 _net2 74LV00A
     <.PortSym -30 10 2 0 P2>
     <.PortSym 30 0 3 180 P3>
     <.ID 10 14 Y>
+    <Line -10 20 0 -40 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component 74LV02>
+  <Description>
+2-Input NOR Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV02 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="n74LV02_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV02.cir.lst">
+  <Spice>
+* ---------------------------------- 74LV02A ---------------------
+*  Quad 2-Input Nor Gates
+*
+*  TI PDF File
+*  bss    2/18/03
+*
+.SUBCKT 74LV02A  1A 1B 1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 nor(2) DPWR_3V DGND_3V
++     1A 1B 1Y
++     DLY_LV02 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV02 ugate (tplhTY=7.6ns tplhMX=11.4ns tphlTY=7.6ns tphlMX=11.4ns)
+
+.ENDS  74LV02A
+*
+
+.SUBCKT Digital_LV_74LV02  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 74LV02A
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #000080 2 1>
+    <Line -10 20 -5 0 #000080 2 1>
+    <Line -10 -20 -5 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component 74LV04>
+  <Description>
+Inverter
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV04 _net0 _net1
+Sub:X1 _net0 _net1 gnd Type="n74LV04_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV04.cir.lst">
+  <Spice>
+* -------------------------- 74LV04A --------------------------------
+*  Hex Inverters
+*
+*  TI PDF File
+*  bss    1/2/03
+*
+.SUBCKT 74LV04A  1A  1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 inv DPWR_3V DGND_3V
++     1A 1Y
++     DLY_LV04 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV04 ugate (tplhTY=7.3ns tplhMX=10.6ns tphlTY=7.3ns tphlMX=10.6ns)
+
+.ENDS  74LV04A
+*
+
+.SUBCKT Digital_LV_74LV04  gnd _net0 _net1 
+X1 _net0 _net1 74LV04A
+.ENDS
+  </Spice>
+  <Symbol>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line -10 20 0 -40 #000080 2 1>
+    <Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <.ID 10 14 Y>
+    <.PortSym 30 0 2 180 P2>
+    <Line -30 0 20 0 #000080 2 1>
+    <.PortSym -30 0 1 0 P1>
+  </Symbol>
+</Component>
+
+<Component 74LV08>
+  <Description>
+2-Input AND Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV08 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="n74LV08_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV08.cir.lst">
+  <Spice>
+* ---------------------------- 74LV08A ------------------------------
+*  Quad 2-Input AND Gate
+*
+*  TI PDF File
+*  bss    2/21/03
+*
+.SUBCKT 74LV08A  1A 1B 1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 and(2) DPWR_3V DGND_3V
++     1A 1B 1Y
++     DLY_LV08 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV08 ugate (tplhTY=7.5ns tplhMX=12.3ns tphlTY=7.5ns tphlMX=12.3ns)
+
+.ENDS  74LV08A
+*
+
+.SUBCKT Digital_LV_74LV08  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 74LV08A
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line -10 20 0 -40 #000080 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component 74LV20>
+  <Description>
+4-Input NAND Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV20 _net0 _net1 _net2 _net3 _net4
+Sub:X1 _net0 _net1 _net2 _net3 _net4 gnd Type="n74LV20_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV20.cir.lst">
+  <Spice>
+* ----------------------------- 74LV20A -------------------------
+*  Dual 4-Input Nand Gate 
+*
+*  TI PDF File
+*  bss    2/24/03
+*
+.SUBCKT 74LV20A  1A 1B 1C 1D 1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 nand(4) DPWR_3V DGND_3V
++     1A 1B 1C 1D 1Y
++     DLY_LV20 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV20 ugate (tplhTY=6.5ns tplhMX=10.1ns tphlTY=6.5ns tphlMX=10.1ns)
+
+.ENDS  74LV20A
+*
+
+.SUBCKT Digital_LV_74LV20  gnd _net0 _net1 _net2 _net3 _net4 
+X1 _net0 _net1 _net2 _net3 _net4 74LV20A
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line -30 -30 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <Line -30 30 20 0 #000080 2 1>
+    <Line -10 40 0 -80 #000080 2 1>
+    <Ellipse 20 -4 8 8 #000080 1 1 #000080 1 1>
+    <EArc -20 -20 40 40 4320 2880 #000080 2 1>
+    <Line 0 20 -10 0 #000080 2 1>
+    <.PortSym -30 -30 1 0 P1>
+    <.PortSym -30 -10 2 0 P2>
+    <.PortSym -30 10 3 0 P3>
+    <.PortSym -30 30 4 0 P4>
+    <.PortSym 40 0 5 180 P5>
+    <.ID 20 14 Y>
+    <Line 28 0 12 0 #000080 2 1>
+    <Line 0 -20 -10 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component 74LV32>
+  <Description>
+2-Input OR Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV32 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="n74LV32_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV32.cir.lst">
+  <Spice>
+* -------------------------- 74LV32A ----------------------------
+*  Quad 2-Input Or Gate
+*
+*  TI PDF File
+*  bss    2/24/03
+*
+.SUBCKT 74LV32A  1A 1B 1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 or(2) DPWR_3V DGND_3V
++     1A 1B 1Y
++     DLY_LV32 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV32 ugate (tplhTY=6.9ns tplhMX=11.4ns tphlTY=6.9ns tphlMX=11.4ns)
+
+.ENDS  74LV32A
+*
+
+.SUBCKT Digital_LV_74LV32  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 74LV32A
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #000080 2 1>
+    <Line -10 20 -5 0 #000080 2 1>
+    <Line -10 -20 -5 0 #000080 2 1>
   </Symbol>
 </Component>
 
 <Component 74LV74>
   <Description>
 D-Type Positive Edge Triggered Flip-Flop With Preset And Clear
-
+XSPICE Based Model
 Requirements:
 .spiceinit: set ngbehavior=psa
 .PARAM: vcc=5
@@ -73,7 +339,7 @@ Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 gnd Type="n74LV74_cir"
 * The timing parameters for all of these models were taken from the specifications for a 
 * 3.3V power supply and a 50pF capacitive load.
 *
-* ----------------------------------------------------------- 74LV74A ------
+* -------------------------------------- 74LV74A ---------------------------
 *  Dual Positive Edge Triggered D-Type Flip-Flop
 *
 *  TI PDF File
@@ -127,3 +393,544 @@ X1 _net0 _net1 _net2 _net3 _net4 _net5 74LV74A
   </Symbol>
 </Component>
 
+<Component 74LV86>
+  <Description>
+2-Input Exclusive-OR Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV86 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="n74LV86_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV86.cir.lst">
+  <Spice>
+* ----------------------------------------------------------- 74LV86A ------
+*  Quad 2-Input Exclusive-Or Gate
+*
+*  TI PDF File
+*  bss    2/24/03
+*
+.SUBCKT 74LV86  1A 1B 1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 xor DPWR_3V DGND_3V
++     1A 1B 1Y
++     DLY_LV86 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV86 ugate (tplhTY=7.4ns tplhMX=14.5ns tphlTY=7.4ns tphlMX=14.5ns)
+
+.ENDS  74LV86
+*
+
+.SUBCKT Digital_LV_74LV86  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 74LV86
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #000080 2 1>
+    <EArc -15 -20 10 40 4320 2880 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component 74LV138>
+  <Description>
+3-Line To 8-Line Decoder/Demultiplexer
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV138 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13
+Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 gnd Type="n74LV138_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV138.cir.lst">
+  <Spice>
+*-----------------------------------------------------------74LV138A-----
+* 3-Line To 8-Line Decoder/Demultiplexer
+*
+*  TI PDF File
+*  bss    2/25/03
+
+.SUBCKT 74LV138A A B C G1 G2ABAR G2BBAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 LOGICEXP(6,8) DPWR_3V DGND_3V
++ A B C G1 G2ABAR G2BBAR
++ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
++ D0_GATE IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ LOGIC:
++   ENAB = {G1 & ~G2ABAR & ~G2BBAR}
++   Y0O = {~(~A & ~B & ~C & ENAB)}
++   Y1O = {~(A & ~B & ~C & ENAB)}
++   Y2O = {~(~A & B & ~C & ENAB)}
++   Y3O = {~(A & B & ~C & ENAB)}
++   Y4O = {~(~A & ~B & C & ENAB)}
++   Y5O = {~(A & ~B & C & ENAB)}
++   Y6O = {~(~A & B & C & ENAB)}
++   Y7O = {~(A & B & C & ENAB)}
+
+U2 PINDLY(8,0,6) DPWR_3V DGND_3V
++ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
++ A B C G1 G2ABAR G2BBAR
++ Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
++ IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ BOOLEAN:
++     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
++     ENBAR = {CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0)}
++     EN = {CHANGED(G1,0)}
++  PINDLY:
++     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
++       CASE(
++          EN & TRN_LH, DELAY(-1,10.6ns,16.3ns),
++          EN & TRN_HL, DELAY(-1,10.6ns,16.3ns),
++          ENBAR & TRN_LH, DELAY(-1,10ns,14.9ns),
++          ENBAR & TRN_HL, DELAY(-1,10ns,14.9ns),
++          IN & TRN_LH, DELAY(-1,10.3ns,15.8ns),
++          IN & TRN_HL, DELAY(-1,10.3ns,15.8ns),
++          DELAY(-1,11ns,17ns))}
+
+.ENDS 74LV138A
+*
+
+.SUBCKT Digital_LV_74LV138  gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 
+X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 74LV138A
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Rectangle -30 -20 60 180 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 140 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <Line -50 0 20 0 #000080 2 1>
+    <.PortSym 50 0 7 180 Y0>
+    <.PortSym 50 20 8 180 Y1>
+    <.PortSym 50 40 9 180 Y2>
+    <.PortSym 50 60 10 180 Y3>
+    <.PortSym 50 80 11 180 Y4>
+    <.PortSym 50 100 12 180 Y5>
+    <.PortSym 50 120 13 180 Y6>
+    <.PortSym 50 140 14 180 Y7>
+    <Line -50 20 20 0 #000080 2 1>
+    <Line -50 40 20 0 #000080 2 1>
+    <.PortSym -50 20 2 0 B>
+    <.PortSym -50 0 1 0 A>
+    <.PortSym -50 40 3 0 C>
+    <Line -50 80 20 0 #000080 2 1>
+    <Line -50 100 20 0 #000080 2 1>
+    <Ellipse -31 96 -8 8 #000080 1 1 #000080 1 1>
+    <Line -50 120 20 0 #000080 2 1>
+    <Ellipse -31 116 -8 8 #000080 1 1 #000080 1 1>
+    <.PortSym -50 80 4 0 G1>
+    <.PortSym -50 100 5 0 G2AB>
+    <.PortSym -50 120 6 0 G2BB>
+    <Text -25 -11 12 #000080 0 "A">
+    <Text 6 29 12 #000080 0 "Y2">
+    <Text 6 49 12 #000080 0 "Y3">
+    <Text 6 129 12 #000080 0 "Y7">
+    <Text 6 9 12 #000080 0 "Y1">
+    <Text 6 89 12 #000080 0 "Y5">
+    <Text 6 -11 12 #000080 0 "Y0">
+    <Text 6 69 12 #000080 0 "Y4">
+    <Text 6 109 12 #000080 0 "Y6">
+    <Text -25 9 12 #000080 0 "B">
+    <Text -25 69 12 #000080 0 "G1">
+    <Text -25 89 12 #000080 0 "G2">
+    <Text -25 109 12 #000080 0 "G3">
+    <.ID -10 164 Y>
+    <Text -25 29 12 #000080 0 "C">
+  </Symbol>
+</Component>
+
+<Component 74LV164>
+  <Description>
+8-Bit Parallel-Out Serial Shift Register
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV164 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11
+Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 gnd Type="n74LV164_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV164.cir.lst">
+  <Spice>
+* ----------------------------------------------------------- 74LV164 ------
+*  8-Bit Parallel-Out Serial Shift Register
+*
+*  TI PDF File
+*  bss    2/26/03
+*
+.SUBCKT 74LV164 A B CLRBAR CLK QA QB QC QD QE QF QG QH
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U74164 LOGICEXP (3,3) DPWR_3V DGND_3V
++        CLK A B
++        r0 s0 clkbar
++        D0_GATE IO_LV-A IO_LEVEL={IO_LEVEL}
++
++    LOGIC:
++      r0 = { (~(A & B)) }
++      s0 = { (~r0) }
++      clkbar = { (~CLK) }
+
+uf0  JKff(8)  DPWR_3V DGND_3V
++    $D_HI CLRBAR clkbar
++    s0 QA_O QB_O QC_O QD_O QE_O QF_O QG_O
++    r0 qabar qbbar qcbar qdbar qebar qfbar qgbar
++    QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O
++    qabar qbbar qcbar qdbar qebar qfbar qgbar qhbar
++    D0_EFF IO_LV-A
+
+Udly PINDLY (8,0,2) DPWR_3V DGND_3V
++    QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O
++    CLRBAR CLK
++    QA QB QC QD QE QF QG QH
++    IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++
++    BOOLEAN:
++       CLOCK= { CHANGED(CLK,0) }
++       CLEAR= { CHANGED_HL(CLRBAR,0) }
++
++    PINDLY:
++       QA QB QC QD QE QF QG QH  = {
++                   CASE(
++                       CLEAR & TRN_HL, DELAY(-1,7.9ns,16.3ns),
++                       CLOCK, DELAY(-1,8.3ns,16.3ns),
++                       DELAY(-1,9ns,17ns)
++                       )
++                     }
+
+Ucnstr CONSTRAINT(4) DPWR_3V DGND_3V
++          CLRBAR CLK A B
++          IO_LV-A
++
++      FREQ:
++        NODE = CLK
++        MAXFREQ = 120MEG
++      WIDTH:
++        NODE = CLK
++        MIN_HI = 5ns
++			MIN_LO = 5ns
++      WIDTH:
++        NODE = CLRBAR
++        MIN_LO = 5ns
++      SETUP_HOLD:
++        CLOCK LH = CLK
++        DATA(2) = A B
++        SETUPTIME = 5ns
++        WHEN = { CLRBAR != '0 }
++      SETUP_HOLD:
++        DATA(1) = CLRBAR
++        CLOCK LH = CLK
++        SETUPTIME_HI = 2.5ns
+
+.ENDS 74LV164
+*
+
+.SUBCKT Digital_LV_74LV164  gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 
+X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 74LV164
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Text 4 9 12 #000080 0 "QB">
+    <Text 4 -11 12 #000080 0 "QA">
+    <Text 4 29 12 #000080 0 "QC">
+    <Text 4 49 12 #000080 0 "QD">
+    <Text 4 69 12 #000080 0 "QE">
+    <Line -50 0 20 0 #000080 2 1>
+    <Text -28 -10 12 #000080 0 "A">
+    <Rectangle -30 -20 60 180 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Text 4 89 12 #000080 0 "QF">
+    <Text 4 109 12 #000080 0 "QG">
+    <Text 4 129 12 #000080 0 "QH">
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 140 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <Line -50 20 20 0 #000080 2 1>
+    <Line -50 60 20 0 #000080 2 1>
+    <Text -28 10 12 #000080 0 "B">
+    <Text -28 50 12 #000080 0 "CLR">
+    <Ellipse -31 56 -8 8 #000080 1 1 #000080 1 1>
+    <Line -50 140 20 0 #000080 2 1>
+    <Line -15 140 -15 -10 #000080 2 1>
+    <Line -30 150 15 -10 #000080 2 1>
+    <.PortSym -50 60 3 0 CLRBAR>
+    <.ID -10 164 Y>
+    <.PortSym -50 0 1 0 A>
+    <.PortSym -50 20 2 0 B>
+    <.PortSym -50 140 4 0 CLK>
+    <.PortSym 50 0 5 180 QA>
+    <.PortSym 50 20 6 180 QB>
+    <.PortSym 50 40 7 180 QC>
+    <.PortSym 50 60 8 180 QD>
+    <.PortSym 50 80 9 180 QE>
+    <.PortSym 50 100 10 180 QF>
+    <.PortSym 50 120 11 180 QG>
+    <.PortSym 50 140 12 180 QH>
+  </Symbol>
+</Component>
+
+<Component 74LV4040>
+  <Description>
+12-Stage Binary Ripple Counter
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV4040 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13
+Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 gnd Type="n74LV4040_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV4040.cir.lst">
+  <Spice>
+*
+*---------------------74LV4040A-----------------------
+* 12-Bit Asynchronous Binary Counter
+*
+*  TI PDF File
+*  bss    2/28/03
+
+.SUBCKT 74LV4040 CLR CLK QA QB QC QD QE QF QG QH QI QJ QK QL
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 LOGICEXP(1,1) DPWR_3V DGND_3V
++ CLR
++ RESETBAR
++ D0_GATE IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ LOGIC:
++        RESETBAR = {~CLR}
+
+U2 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR CLK
++ $D_HI $D_HI Q_A $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U3 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_A
++ $D_HI $D_HI Q_B $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U4 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_B
++ $D_HI $D_HI Q_C $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U5 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_C
++ $D_HI $D_HI Q_D $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U6 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_D
++ $D_HI $D_HI Q_E $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U7 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_E
++ $D_HI $D_HI Q_F $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U8 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_F
++ $D_HI $D_HI Q_G $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U9 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_G
++ $D_HI $D_HI Q_H $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U10 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_H
++ $D_HI $D_HI Q_I $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U11 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_I
++ $D_HI $D_HI Q_J $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U12 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_J
++ $D_HI $D_HI Q_K $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U13 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_K
++ $D_HI $D_HI Q_L $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U14 PINDLY(12,0,2) DPWR_3V DGND_3V
++ Q_A Q_B Q_C Q_D Q_E Q_F Q_G Q_H Q_I Q_J Q_K Q_L
++ CLR CLK
++ QA QB QC QD QE QF QG QH QI QJ QK QL
++ IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ BOOLEAN:
++          CLEAR = {CHANGED_LH(CLR,0)}
++          ACLK = {CHANGED_HL(CLK,0)}
++ PINDLY:
++          QA = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,7.5ns,15.4ns),
++              DELAY(-1,10ns,17ns))}
++          QB = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,8.7ns,19.8ns),
++              DELAY(-1,10ns,20ns))}
++          QC = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,9.9ns,24.2ns),
++              DELAY(-1,10ns,25ns))}
++          QD = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,11.1ns,28.6ns),
++              DELAY(-1,12ns,29ns))}
++          QE = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,12.3ns,33ns),
++              DELAY(-1,13ns,34ns))}
++          QF = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,13.5ns,37.4ns),
++              DELAY(-1,14ns,38ns))}
++          QG = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,14.7ns,41.8ns),
++              DELAY(-1,15ns,42ns))}
++          QH = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,15.9ns,46.2ns),
++              DELAY(-1,16ns,47ns))}
++          QI = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,17.1ns,50.6ns),
++              DELAY(-1,18ns,51ns))}
++          QJ = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,18.3ns,55ns),
++              DELAY(-1,19ns,56ns))}
++          QK = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,19.5ns,59.4ns),
++              DELAY(-1,20ns,60ns))}
++          QL = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,20.7ns,63.8ns),
++              DELAY(-1,21ns,64ns))}
+
+U15 CONSTRAINT(2) DPWR_3V DGND_3V
++ CLK CLR
++ IO_LV-A IO_LEVEL={IO_LEVEL}
++ SETUP_HOLD:
++             CLOCK HL = CLK
++             DATA(1) = CLR
++             SETUPTIME_LO = 5NS
++ WIDTH:
++             NODE = CLK
++             MIN_HI = 5NS
++             MIN_LO = 5NS
++ WIDTH:
++             NODE = CLR
++             MIN_HI = 5NS
++ FREQ:
++             NODE = CLK
++             MAXFREQ = 130MEG
+
+.ENDS 74LV4040
+*
+
+.SUBCKT Digital_LV_74LV4040  gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 
+X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 74LV4040
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Text 4 9 12 #000080 0 "QB">
+    <Text 4 -11 12 #000080 0 "QA">
+    <Text 4 29 12 #000080 0 "QC">
+    <Text 4 49 12 #000080 0 "QD">
+    <Text 4 69 12 #000080 0 "QE">
+    <Rectangle -30 -20 60 260 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Text 4 89 12 #000080 0 "QF">
+    <Text 4 109 12 #000080 0 "QG">
+    <Text 4 129 12 #000080 0 "QH">
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 140 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <Line 30 160 20 0 #000080 2 1>
+    <Line 30 180 20 0 #000080 2 1>
+    <Line 30 200 20 0 #000080 2 1>
+    <Line 30 220 20 0 #000080 2 1>
+    <.PortSym 50 0 3 180 QA>
+    <.PortSym 50 20 4 180 QB>
+    <.PortSym 50 40 5 180 QC>
+    <.PortSym 50 60 6 180 QD>
+    <.PortSym 50 80 7 180 QE>
+    <.PortSym 50 100 8 180 QF>
+    <.PortSym 50 120 9 180 QG>
+    <.PortSym 50 140 10 180 QH>
+    <.PortSym 50 160 11 180 QI>
+    <.PortSym 50 180 12 180 QJ>
+    <Text 4 149 12 #000080 0 "QI">
+    <Text 4 169 12 #000080 0 "QJ">
+    <Text 4 189 12 #000080 0 "QK">
+    <Text 4 209 12 #000080 0 "QL">
+    <.ID -10 244 Y>
+    <.PortSym 50 200 13 180 QK>
+    <.PortSym 50 220 14 180 QL>
+    <.PortSym -50 0 2 0 CLK>
+    <Line -50 0 20 0 #000080 2 1>
+    <Line -15 0 -15 -10 #000080 2 1>
+    <Line -30 10 15 -10 #000080 2 1>
+    <Line -50 60 20 0 #000080 2 1>
+    <Text -28 50 12 #000080 0 "CLR">
+    <.PortSym -50 60 1 0 CLR>
+  </Symbol>
+</Component>
\ No newline at end of file
diff --git a/library/qucs.blacklist b/library/qucs.blacklist
index 21323617..d52727af 100644
--- a/library/qucs.blacklist
+++ b/library/qucs.blacklist
@@ -1,6 +1,6 @@
 SpiceOpamp.lib
 Cores.lib
-Digital_CD4000.lib
+Digital_CD.lib
 Digital_HC.lib
 Digital_LV.lib
 Transformers.lib
diff --git a/library/xyce.blacklist b/library/xyce.blacklist
index e6a40756..536dfbeb 100644
--- a/library/xyce.blacklist
+++ b/library/xyce.blacklist
@@ -1,6 +1,6 @@
 Substrates.lib
 Xanalogue.lib
 PWM_Controller.lib
-Digital_CD4000.lib
+Digital_CD.lib
 Digital_HC.lib
 Digital_LV.lib