Make SRAMs directly emit FIRRTL memories (chipsalliance#3955)

rameloni · Apr 2, 2024 · feab7a7 · feab7a7
1 parent 6406c41
commit feab7a7
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Showing 12 changed files with 387 additions and 90 deletions.
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala
@@ -373,14 +373,14 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
   private[chisel3] final def isSynthesizable: Boolean = _binding.map {
     case ChildBinding(parent) => parent.isSynthesizable
     case _: TopBinding => true
-    case (_: SampleElementBinding[_] | _: MemTypeBinding[_]) => false
+    case (_: SampleElementBinding[_] | _: MemTypeBinding[_] | _: FirrtlMemTypeBinding) => false
   }.getOrElse(false)
 
   private[chisel3] def topBindingOpt: Option[TopBinding] = _binding.flatMap {
     case ChildBinding(parent) => parent.topBindingOpt
     case bindingVal: TopBinding => Some(bindingVal)
     case SampleElementBinding(parent) => parent.topBindingOpt
-    case _: MemTypeBinding[_] => None
+    case (_: MemTypeBinding[_] | _: FirrtlMemTypeBinding) => None
   }
 
   private[chisel3] def topBinding: TopBinding = topBindingOpt.get

diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
@@ -160,7 +160,9 @@ abstract class RawModule extends BaseModule {
           // probes have their refs set eagerly
           case _ => // don't name literals
         }
-      } // else, don't name unbound types
+      }
+    case m: SramTarget =>
+      id.forceName(default = "MEM", _namespace)
   }
 
   private[chisel3] override def generateComponent(): Option[Component] = {

diff --git a/core/src/main/scala/chisel3/SramTarget.scala b/core/src/main/scala/chisel3/SramTarget.scala
@@ -0,0 +1,9 @@
+package chisel3
+
+import chisel3.internal.NamedComponent
+
+/** Provides an underlying target-able class for SRAM.
+  */
+private[chisel3] final class SramTarget extends NamedComponent {
+  _parent.foreach(_.addId(this))
+}
diff --git a/core/src/main/scala/chisel3/experimental/Analog.scala b/core/src/main/scala/chisel3/experimental/Analog.scala
@@ -53,7 +53,8 @@ final class Analog private (private[chisel3] val width: Width) extends Element {
       case ChildBinding(parent) => parent.topBinding
       // See https://github.com/freechipsproject/chisel3/pull/946
       case SampleElementBinding(parent) => parent.topBinding
-      case a: MemTypeBinding[_] => a
+      case a: MemTypeBinding[_]    => a
+      case a: FirrtlMemTypeBinding => a
     }
 
     targetTopBinding match {

diff --git a/core/src/main/scala/chisel3/internal/Binding.scala b/core/src/main/scala/chisel3/internal/Binding.scala
@@ -95,6 +95,9 @@ private[chisel3] case class OpBinding(enclosure: RawModule, visibility: Option[W
 private[chisel3] case class MemoryPortBinding(enclosure: RawModule, visibility: Option[WhenContext])
     extends ConstrainedBinding
     with ConditionalDeclarable
+private[chisel3] case class SramPortBinding(enclosure: RawModule, visibility: Option[WhenContext])
+    extends ConstrainedBinding
+    with ConditionalDeclarable
 private[chisel3] case class RegBinding(enclosure: RawModule, visibility: Option[WhenContext])
     extends ConstrainedBinding
     with ConditionalDeclarable
@@ -119,6 +122,12 @@ private[chisel3] case class SampleElementBinding[T <: Data](parent: Vec[T]) exte
 private[chisel3] case class MemTypeBinding[T <: Data](parent: MemBase[T]) extends Binding {
   def location: Option[BaseModule] = parent._parent
 }
+
+/** Special binding for Firrtl memory (SRAM) types */
+private[chisel3] case class FirrtlMemTypeBinding(parent: SramTarget) extends Binding {
+  def location: Option[BaseModule] = parent._parent
+}
+
 // A DontCare element has a specific Binding, somewhat like a literal.
 // It is a source (RHS). It may only be connected/applied to sinks.
 private[chisel3] case class DontCareBinding() extends UnconstrainedBinding

diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -148,6 +148,20 @@ private[chisel3] object Converter {
       Some(firrtl.CDefMemory(convert(info), e.name, extractType(t, info, typeAliases), size, false))
     case e @ DefSeqMemory(info, id, t, size, ruw) =>
       Some(firrtl.CDefMemory(convert(info), e.name, extractType(t, info, typeAliases), size, true, ruw))
+    case e @ FirrtlMemory(info, id, t, size, readPortNames, writePortNames, readwritePortNames) =>
+      Some(
+        fir.DefMemory(
+          convert(info),
+          e.name,
+          extractType(t, info, typeAliases),
+          size,
+          1,
+          1,
+          readPortNames,
+          writePortNames,
+          readwritePortNames
+        )
+      )
     case e: DefMemPort[_] =>
       val info = e.sourceInfo
       Some(

diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -219,7 +219,7 @@ private[chisel3] object ir {
       // NOTE: mod eq ctx.id only occurs in Target and Named-related APIs
       if (mod eq ctx.id) localName else name
   }
-  case class Slot(imm: Node, name: String) extends Arg {
+  case class Slot(imm: Arg, name: String) extends Arg {
     override def contextualName(ctx: Component): String = {
       val immName = imm.contextualName(ctx)
       if (immName.isEmpty) name else s"$immName.$name"
@@ -288,6 +288,16 @@ private[chisel3] object ir {
     readUnderWrite: fir.ReadUnderWrite.Value)
       extends Definition
 
+  case class FirrtlMemory(
+    sourceInfo:         SourceInfo,
+    id:                 HasId,
+    t:                  Data,
+    size:               BigInt,
+    readPortNames:      Seq[String],
+    writePortNames:     Seq[String],
+    readwritePortNames: Seq[String])
+      extends Definition
+
   case class DefMemPort[T <: Data](
     sourceInfo: SourceInfo,
     id:         T,
@@ -310,7 +320,7 @@ private[chisel3] object ir {
   case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command
   case class AltBegin(sourceInfo: SourceInfo) extends Command
   case class OtherwiseEnd(sourceInfo: SourceInfo, firrtlDepth: Int) extends Command
-  case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
+  case class Connect(sourceInfo: SourceInfo, loc: Arg, exp: Arg) extends Command
   case class PropAssign(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
   case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command
   case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command

diff --git a/panamaconverter/src/PanamaCIRCTConverter.scala b/panamaconverter/src/PanamaCIRCTConverter.scala
@@ -986,7 +986,7 @@ class PanamaCIRCTConverter(val circt: PanamaCIRCT, fos: Option[FirtoolOptions],
   }
 
   def visitConnect(connect: Connect): Unit = {
-    val dest = util.referTo(connect.loc.id, connect.sourceInfo)
+    val dest = util.referTo(connect.loc, connect.sourceInfo)
     var src = util.referTo(connect.exp, connect.sourceInfo)
     util.emitConnect(dest, src, util.convert(connect.sourceInfo))
   }

diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala
@@ -474,9 +474,9 @@ object Select {
   // Given a loc, return all subcomponents of id that could be assigned to in connect
   private def getEffected(a: Arg): Seq[Data] = a match {
     case Node(id: Data) => DataMirror.collectAllMembers(id)
-    case Slot(imm, name) => Seq(imm.id.asInstanceOf[Record].elements(name))
-    case Index(imm, _)   => getEffected(imm)
-    case _               => throw new InternalErrorException("Match error: a=$a")
+    case Slot(imm: Node, name) => Seq(imm.id.asInstanceOf[Record].elements(name))
+    case Index(imm, _) => getEffected(imm)
+    case _             => throw new InternalErrorException("Match error: a=$a")
   }
 
   // Given an arg, return the corresponding id. Don't use on a loc of a connect.