diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 96235f8d94da4f..bbdb531f494b73 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -2450,13 +2450,28 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
 	return plane;
 }
 
-#define VC4_NUM_OVERLAY_PLANES	48
+#define VC4_NUM_OVERLAY_PLANES	16
+#define VC4_NUM_TXP_OVERLAY_PLANES 32
 
 int vc4_plane_create_additional_planes(struct drm_device *drm)
 {
 	struct drm_plane *cursor_plane;
 	struct drm_crtc *crtc;
 	unsigned int i;
+	struct drm_crtc *txp_crtc;
+	uint32_t non_txp_crtc_mask;
+
+	drm_for_each_crtc(crtc, drm) {
+		struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+
+		if (vc4_crtc->feeds_txp) {
+			txp_crtc = crtc;
+			break;
+		}
+	}
+
+	non_txp_crtc_mask = GENMASK(drm->mode_config.num_crtc - 1, 0) -
+					drm_crtc_mask(txp_crtc);
 
 	/* Set up some arbitrary number of planes.  We're not limited
 	 * by a set number of physical registers, just the space in
@@ -2470,7 +2485,22 @@ int vc4_plane_create_additional_planes(struct drm_device *drm)
 	for (i = 0; i < VC4_NUM_OVERLAY_PLANES; i++) {
 		struct drm_plane *plane =
 			vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY,
-				       GENMASK(drm->mode_config.num_crtc - 1, 0));
+				       non_txp_crtc_mask);
+
+		if (IS_ERR(plane))
+			continue;
+
+		/* Create zpos property. Max of all the overlays + 1 primary +
+		 * 1 cursor plane on a crtc.
+		 */
+		drm_plane_create_zpos_property(plane, i + 1, 1,
+					       VC4_NUM_OVERLAY_PLANES + 1);
+	}
+
+	for (i = 0; i < VC4_NUM_TXP_OVERLAY_PLANES; i++) {
+		struct drm_plane *plane =
+			vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY,
+				       drm_crtc_mask(txp_crtc));
 
 		if (IS_ERR(plane))
 			continue;