RPi5 6.9+ NVME boot regression #6321
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@pelwell any ideas on the cause for this regression starting your Linux 6.9+ branches? Or suggestions how to debug this? |
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Based on the call stack and the register content, it's failing ungracefully initialising one of RP1s clocks because another clock of that name already exists. This should never happen. The list of RP1 clock names is:
Note that the RP1 clock driver has not changed between rpi-6.6.y and rpi-6.11.y, so there is no immediately obvious reason why it has started failing for you. By the way, I recommend getting some kind of serial cable (e.g. our Debug Probe) as a better way to debug boot failures. |
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@pelwell Thank you for taking a look.
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Yes, in the past I was able to run kernels 6.9 and newer without issues, albeit while booting from sdcard and without initramfs. Today I also validated, that by placing the 6.11-rc7 kernel and initramfs on the sdcard's boot partition and specifying it in the sdcard's config.txt via the kernel and initramfs options as well adjusting the To summarize, the same initramfs boots correctly when placed on sdcard, but fails with above issue if placed on nvme. For Linux <6.9, the initramfs works fine even when placed on the nvme. Please let me know if I can help provide further information for debugging this. |
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Pull request #6363 adds some kernel logging to the RP1 clock driver, and hopefully stops it crashing when registration fails. After about 40 minutes you should be able to run |
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Thank you, @pelwell. I've applied the patch from #6363 locally and rebuilt the kernel. Your PR is to rpi-6.6.y, which does not exhibit the problem in the first place and thus I doubt that rpi-update would get the right kernel. Do you publish builds for all branches? Below is the debug output when booting from nvme. The boot indeed succeeds with your patch, though the fan speed controller seems broken (and fan remains at full speed after boot). Booting with the previously mentioned sdcard workaround does not exhibit fan speed issues. I'm not sure what the clksrc clocks are and whether they are expected to show up in the devicetree on the booted system, but |
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Your problem is caused by the fact that your build commands don't update the Device Tree ( Between the image that you started with and 6.9, this happened: 9a108c8 Mixing and matching DTBs and kernels is not a supported use case - it might work, but there's a distinctly non-zero chance that it won't, as you've discovered. I'll merge the patch that makes the failed clock registration non-fatal, but I've found that although the boot continues, the resulting system has some odd behaviour (UART is erratic, etc.) |
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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I've pushed the patch - d290bef - which I think resolves this issue. |
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <[email protected]> drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers General-purpose clocks are routed (via a pad) to a large variety of peripheral aux muxes, and themselves gather a large variety of source clocks. Entries without a corresponding name string should not be selected - they bring out internal test/debug clocks which may be intermittent or very high frequency. As the GPCLK inputs to peripheral muxes come from a pad, differentiate the source name from the divider output name. This allows the possibility of specifying an off-chip clock source to drive the internal peripheral clock. Signed-off-by: Jonathan Bell <[email protected]> drivers: clk: rp1: constrain clock divider outputs to design maximums Overclocking peripherals is generally a bad thing to do - so reject any attempt to set a clock output higher than it should be. Signed-off-by: Jonathan Bell <[email protected]> clk: rp1: Reserve pll_audio* for clk_i2s Prevent all clocks except clk_i2s from using the audio PLLs as sources, so that clk_i2s may be allowed to change them as needed. Signed-off-by: Phil Elwell <[email protected]> clk: rp1: Allow clk_i2s to change the audio PLLs Add dedicated code allowing the audio PLLs to be changed, enabling perfect I2S clock generation. The slowest legal pll_audio_core and pll_audio will be selected that leads to the required clk_i2s rate. Signed-off-by: Phil Elwell <[email protected]> clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]> clk: clk-rp1: Don't crash on duplicate clocks When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
popcornmix
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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Thank you, @pelwell. I've confirmed that the current rpi-6.11.y branch, which includes your commit, boots up successfully in my setting, printing the "wrong dtbs?" error in dmesg while preserving the "fanspeed stuck at high" issue. Adjusting tryboot.txt config to add After confirming successful tryboot, I've used the following to update the main kernel: I must have accidentally had compatible dtbs on the sdcard before.. Thank you for looking into this and adding the dmesg message. It will hopefully make debugging for others easier in the future. |
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RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <[email protected]> drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers General-purpose clocks are routed (via a pad) to a large variety of peripheral aux muxes, and themselves gather a large variety of source clocks. Entries without a corresponding name string should not be selected - they bring out internal test/debug clocks which may be intermittent or very high frequency. As the GPCLK inputs to peripheral muxes come from a pad, differentiate the source name from the divider output name. This allows the possibility of specifying an off-chip clock source to drive the internal peripheral clock. Signed-off-by: Jonathan Bell <[email protected]> drivers: clk: rp1: constrain clock divider outputs to design maximums Overclocking peripherals is generally a bad thing to do - so reject any attempt to set a clock output higher than it should be. Signed-off-by: Jonathan Bell <[email protected]> clk: rp1: Reserve pll_audio* for clk_i2s Prevent all clocks except clk_i2s from using the audio PLLs as sources, so that clk_i2s may be allowed to change them as needed. Signed-off-by: Phil Elwell <[email protected]> clk: rp1: Allow clk_i2s to change the audio PLLs Add dedicated code allowing the audio PLLs to be changed, enabling perfect I2S clock generation. The slowest legal pll_audio_core and pll_audio will be selected that leads to the required clk_i2s rate. Signed-off-by: Phil Elwell <[email protected]> clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]> clk: clk-rp1: Don't crash on duplicate clocks When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
popcornmix
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RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <[email protected]> drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers General-purpose clocks are routed (via a pad) to a large variety of peripheral aux muxes, and themselves gather a large variety of source clocks. Entries without a corresponding name string should not be selected - they bring out internal test/debug clocks which may be intermittent or very high frequency. As the GPCLK inputs to peripheral muxes come from a pad, differentiate the source name from the divider output name. This allows the possibility of specifying an off-chip clock source to drive the internal peripheral clock. Signed-off-by: Jonathan Bell <[email protected]> drivers: clk: rp1: constrain clock divider outputs to design maximums Overclocking peripherals is generally a bad thing to do - so reject any attempt to set a clock output higher than it should be. Signed-off-by: Jonathan Bell <[email protected]> clk: rp1: Reserve pll_audio* for clk_i2s Prevent all clocks except clk_i2s from using the audio PLLs as sources, so that clk_i2s may be allowed to change them as needed. Signed-off-by: Phil Elwell <[email protected]> clk: rp1: Allow clk_i2s to change the audio PLLs Add dedicated code allowing the audio PLLs to be changed, enabling perfect I2S clock generation. The slowest legal pll_audio_core and pll_audio will be selected that leads to the required clk_i2s rate. Signed-off-by: Phil Elwell <[email protected]> clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]> clk: clk-rp1: Don't crash on duplicate clocks When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <[email protected]> drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers General-purpose clocks are routed (via a pad) to a large variety of peripheral aux muxes, and themselves gather a large variety of source clocks. Entries without a corresponding name string should not be selected - they bring out internal test/debug clocks which may be intermittent or very high frequency. As the GPCLK inputs to peripheral muxes come from a pad, differentiate the source name from the divider output name. This allows the possibility of specifying an off-chip clock source to drive the internal peripheral clock. Signed-off-by: Jonathan Bell <[email protected]> drivers: clk: rp1: constrain clock divider outputs to design maximums Overclocking peripherals is generally a bad thing to do - so reject any attempt to set a clock output higher than it should be. Signed-off-by: Jonathan Bell <[email protected]> clk: rp1: Reserve pll_audio* for clk_i2s Prevent all clocks except clk_i2s from using the audio PLLs as sources, so that clk_i2s may be allowed to change them as needed. Signed-off-by: Phil Elwell <[email protected]> clk: rp1: Allow clk_i2s to change the audio PLLs Add dedicated code allowing the audio PLLs to be changed, enabling perfect I2S clock generation. The slowest legal pll_audio_core and pll_audio will be selected that leads to the required clk_i2s rate. Signed-off-by: Phil Elwell <[email protected]> clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]> clk: clk-rp1: Don't crash on duplicate clocks When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <[email protected]> drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers General-purpose clocks are routed (via a pad) to a large variety of peripheral aux muxes, and themselves gather a large variety of source clocks. Entries without a corresponding name string should not be selected - they bring out internal test/debug clocks which may be intermittent or very high frequency. As the GPCLK inputs to peripheral muxes come from a pad, differentiate the source name from the divider output name. This allows the possibility of specifying an off-chip clock source to drive the internal peripheral clock. Signed-off-by: Jonathan Bell <[email protected]> drivers: clk: rp1: constrain clock divider outputs to design maximums Overclocking peripherals is generally a bad thing to do - so reject any attempt to set a clock output higher than it should be. Signed-off-by: Jonathan Bell <[email protected]> clk: rp1: Reserve pll_audio* for clk_i2s Prevent all clocks except clk_i2s from using the audio PLLs as sources, so that clk_i2s may be allowed to change them as needed. Signed-off-by: Phil Elwell <[email protected]> clk: rp1: Allow clk_i2s to change the audio PLLs Add dedicated code allowing the audio PLLs to be changed, enabling perfect I2S clock generation. The slowest legal pll_audio_core and pll_audio will be selected that leads to the required clk_i2s rate. Signed-off-by: Phil Elwell <[email protected]> clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]> clk: clk-rp1: Don't crash on duplicate clocks When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <[email protected]> drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers General-purpose clocks are routed (via a pad) to a large variety of peripheral aux muxes, and themselves gather a large variety of source clocks. Entries without a corresponding name string should not be selected - they bring out internal test/debug clocks which may be intermittent or very high frequency. As the GPCLK inputs to peripheral muxes come from a pad, differentiate the source name from the divider output name. This allows the possibility of specifying an off-chip clock source to drive the internal peripheral clock. Signed-off-by: Jonathan Bell <[email protected]> drivers: clk: rp1: constrain clock divider outputs to design maximums Overclocking peripherals is generally a bad thing to do - so reject any attempt to set a clock output higher than it should be. Signed-off-by: Jonathan Bell <[email protected]> clk: rp1: Reserve pll_audio* for clk_i2s Prevent all clocks except clk_i2s from using the audio PLLs as sources, so that clk_i2s may be allowed to change them as needed. Signed-off-by: Phil Elwell <[email protected]> clk: rp1: Allow clk_i2s to change the audio PLLs Add dedicated code allowing the audio PLLs to be changed, enabling perfect I2S clock generation. The slowest legal pll_audio_core and pll_audio will be selected that leads to the required clk_i2s rate. Signed-off-by: Phil Elwell <[email protected]> clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]> clk: clk-rp1: Don't crash on duplicate clocks When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <[email protected]> drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers General-purpose clocks are routed (via a pad) to a large variety of peripheral aux muxes, and themselves gather a large variety of source clocks. Entries without a corresponding name string should not be selected - they bring out internal test/debug clocks which may be intermittent or very high frequency. As the GPCLK inputs to peripheral muxes come from a pad, differentiate the source name from the divider output name. This allows the possibility of specifying an off-chip clock source to drive the internal peripheral clock. Signed-off-by: Jonathan Bell <[email protected]> drivers: clk: rp1: constrain clock divider outputs to design maximums Overclocking peripherals is generally a bad thing to do - so reject any attempt to set a clock output higher than it should be. Signed-off-by: Jonathan Bell <[email protected]> clk: rp1: Reserve pll_audio* for clk_i2s Prevent all clocks except clk_i2s from using the audio PLLs as sources, so that clk_i2s may be allowed to change them as needed. Signed-off-by: Phil Elwell <[email protected]> clk: rp1: Allow clk_i2s to change the audio PLLs Add dedicated code allowing the audio PLLs to be changed, enabling perfect I2S clock generation. The slowest legal pll_audio_core and pll_audio will be selected that leads to the required clk_i2s rate. Signed-off-by: Phil Elwell <[email protected]> clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]> clk: clk-rp1: Don't crash on duplicate clocks When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <[email protected]> drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers General-purpose clocks are routed (via a pad) to a large variety of peripheral aux muxes, and themselves gather a large variety of source clocks. Entries without a corresponding name string should not be selected - they bring out internal test/debug clocks which may be intermittent or very high frequency. As the GPCLK inputs to peripheral muxes come from a pad, differentiate the source name from the divider output name. This allows the possibility of specifying an off-chip clock source to drive the internal peripheral clock. Signed-off-by: Jonathan Bell <[email protected]> drivers: clk: rp1: constrain clock divider outputs to design maximums Overclocking peripherals is generally a bad thing to do - so reject any attempt to set a clock output higher than it should be. Signed-off-by: Jonathan Bell <[email protected]> clk: rp1: Reserve pll_audio* for clk_i2s Prevent all clocks except clk_i2s from using the audio PLLs as sources, so that clk_i2s may be allowed to change them as needed. Signed-off-by: Phil Elwell <[email protected]> clk: rp1: Allow clk_i2s to change the audio PLLs Add dedicated code allowing the audio PLLs to be changed, enabling perfect I2S clock generation. The slowest legal pll_audio_core and pll_audio will be selected that leads to the required clk_i2s rate. Signed-off-by: Phil Elwell <[email protected]> clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]> clk: clk-rp1: Don't crash on duplicate clocks When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <[email protected]> drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers General-purpose clocks are routed (via a pad) to a large variety of peripheral aux muxes, and themselves gather a large variety of source clocks. Entries without a corresponding name string should not be selected - they bring out internal test/debug clocks which may be intermittent or very high frequency. As the GPCLK inputs to peripheral muxes come from a pad, differentiate the source name from the divider output name. This allows the possibility of specifying an off-chip clock source to drive the internal peripheral clock. Signed-off-by: Jonathan Bell <[email protected]> drivers: clk: rp1: constrain clock divider outputs to design maximums Overclocking peripherals is generally a bad thing to do - so reject any attempt to set a clock output higher than it should be. Signed-off-by: Jonathan Bell <[email protected]> clk: rp1: Reserve pll_audio* for clk_i2s Prevent all clocks except clk_i2s from using the audio PLLs as sources, so that clk_i2s may be allowed to change them as needed. Signed-off-by: Phil Elwell <[email protected]> clk: rp1: Allow clk_i2s to change the audio PLLs Add dedicated code allowing the audio PLLs to be changed, enabling perfect I2S clock generation. The slowest legal pll_audio_core and pll_audio will be selected that leads to the required clk_i2s rate. Signed-off-by: Phil Elwell <[email protected]> clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]> clk: clk-rp1: Don't crash on duplicate clocks When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <[email protected]> drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers General-purpose clocks are routed (via a pad) to a large variety of peripheral aux muxes, and themselves gather a large variety of source clocks. Entries without a corresponding name string should not be selected - they bring out internal test/debug clocks which may be intermittent or very high frequency. As the GPCLK inputs to peripheral muxes come from a pad, differentiate the source name from the divider output name. This allows the possibility of specifying an off-chip clock source to drive the internal peripheral clock. Signed-off-by: Jonathan Bell <[email protected]> drivers: clk: rp1: constrain clock divider outputs to design maximums Overclocking peripherals is generally a bad thing to do - so reject any attempt to set a clock output higher than it should be. Signed-off-by: Jonathan Bell <[email protected]> clk: rp1: Reserve pll_audio* for clk_i2s Prevent all clocks except clk_i2s from using the audio PLLs as sources, so that clk_i2s may be allowed to change them as needed. Signed-off-by: Phil Elwell <[email protected]> clk: rp1: Allow clk_i2s to change the audio PLLs Add dedicated code allowing the audio PLLs to be changed, enabling perfect I2S clock generation. The slowest legal pll_audio_core and pll_audio will be selected that leads to the required clk_i2s rate. Signed-off-by: Phil Elwell <[email protected]> clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]> clk: clk-rp1: Don't crash on duplicate clocks When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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Nov 25, 2024
RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <[email protected]> drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers General-purpose clocks are routed (via a pad) to a large variety of peripheral aux muxes, and themselves gather a large variety of source clocks. Entries without a corresponding name string should not be selected - they bring out internal test/debug clocks which may be intermittent or very high frequency. As the GPCLK inputs to peripheral muxes come from a pad, differentiate the source name from the divider output name. This allows the possibility of specifying an off-chip clock source to drive the internal peripheral clock. Signed-off-by: Jonathan Bell <[email protected]> drivers: clk: rp1: constrain clock divider outputs to design maximums Overclocking peripherals is generally a bad thing to do - so reject any attempt to set a clock output higher than it should be. Signed-off-by: Jonathan Bell <[email protected]> clk: rp1: Reserve pll_audio* for clk_i2s Prevent all clocks except clk_i2s from using the audio PLLs as sources, so that clk_i2s may be allowed to change them as needed. Signed-off-by: Phil Elwell <[email protected]> clk: rp1: Allow clk_i2s to change the audio PLLs Add dedicated code allowing the audio PLLs to be changed, enabling perfect I2S clock generation. The slowest legal pll_audio_core and pll_audio will be selected that leads to the required clk_i2s rate. Signed-off-by: Phil Elwell <[email protected]> clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]> clk: clk-rp1: Don't crash on duplicate clocks When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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Nov 25, 2024
When using DTBs that don't match the kernel version, it's possible for clock registration to fail. Handle that failure, in the hope that the system can continue to boot, with a suitable error message. Link: #6321 Signed-off-by: Phil Elwell <[email protected]>
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Describe the bug
Linux 6.9 c64bb7e, 6.10 084962e and 6.11 (based on local rebase of rpi-6.11.y branch on 6.11-rc4), RPi5 with X1001 and NVME SSD initramfs fails to boot with attached stacktrace. The issue does not occur with 6.7 (777eaee) and 6.8 (ea34d5a) as built by me according to the same procedure.
Steps to reproduce the behaviour
Build / install procedure on RPi OS 64 bit.
with tryboot setup as
Device (s)
Raspberry Pi 5
System
cat /etc/rpi-issue
Raspberry Pi reference 2024-07-04
Generated using pi-gen, https://github.com/RPi-Distro/pi-gen, 48efb5fc5485fafdc9de8ad481eb5c09e1182656, stage2
sudo vcgencmd version
2024/07/30 15:25:46
Copyright (c) 2012 Broadcom
version 790da7ef (release) (embedded)
uname -a
Linux raspberrypi 6.8.12-v8+ #1 SMP PREEMPT Wed Aug 21 20:43:18 UTC 2024 aarch64 GNU/Linux
Logs
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Additional context
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