FPGA implementation

[ws200106]

Hello author, thank you very much for being able to open source your project, can you provide systemverilog code for FPGA implementation?

[ridgerchu]

Hi there,
Thank you for your interest in our open-source project and for your request regarding SystemVerilog code for FPGA implementation.
At the moment, we are still in the process of optimizing our FPGA implementation to ensure the best possible performance and reliability. We understand the importance of providing FPGA support and are actively working on it.
Once we have completed the optimization and thoroughly tested the FPGA implementation, we will make it available to the community!

[RCoeurjoly]

Thank you for your dedication to optimizing the FPGA implementation. I understand the importance of ensuring performance and reliability. However, if possible, would you consider sharing the current version of the SystemVerilog code? Access to the work-in-progress could be incredibly beneficial for users like myself who are eager to learn from your approach and contribute to the project's development. Any level of access would be greatly appreciated, even if it's not the final version!

[jainhitesh9998]

Hi @ridgerchu ,
out of curiosity, what fpga toolkits are planned to be supported?
if you could list them.

Also are there any plans to make it work on intel arria 10 series of fpga. we have a bunch of them used for some other purpose, would love to benchmark and contribute in that aspect if it will be supported

[sifferman]

Hello. I am managing the hardware implementation. Once we finish our optimizations and reorganizations, we will make the code available. We have several researchers at UCSC working on it, so it will be completed within the next couple months.

We are designing the RTL to be functional across as many targets as possible. Our design and testbenches will hopefully work on open-source and commercial flows.

As for the FPGA implementation itself, as was mentioned in the paper preprint, we are currently using the Intel D5005 with a Stratix 10 GX through DevCloud.