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top.syr
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top.syr
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Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
--> Reading design: top.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "top.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "top"
Output Format : NGC
Target Device : xc3s1200e-5-fg320
---- Source Options
Top Module Name : top
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
---- Other Options
Cores Search Directories : {"ipcore_dir" }
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "ipcore_dir/frameBuffer.v" in library work
Compiling verilog file "vga.v" in library work
Module <frameBuffer> compiled
Compiling verilog file "top.v" in library work
Module <vga> compiled
Module <top> compiled
No errors in compilation
Analysis of file <"top.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <top> in library <work>.
Analyzing hierarchy for module <vga> in library <work>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <top>.
Module <top> is correct for synthesis.
Analyzing module <vga> in library <work>.
WARNING:Xst:2211 - "ipcore_dir/frameBuffer.v" line 136: Instantiating black box module <frameBuffer>.
Module <vga> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <vga>.
Related source file is "vga.v".
WARNING:Xst:1780 - Signal <btur> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Using one-hot encoding for signal <tur>.
Found 2-bit register for signal <outBlue>.
Found 1-bit register for signal <HS>.
Found 3-bit register for signal <outGreen>.
Found 3-bit register for signal <outRed>.
Found 1-bit register for signal <VS>.
Found 10-bit up counter for signal <Hcnt>.
Found 10-bit up counter for signal <Vcnt>.
Found 15-bit updown accumulator for signal <addra>.
Found 10-bit comparator greater for signal <addra$cmp_gt0000> created at line 99.
Found 10-bit comparator greater for signal <addra$cmp_gt0001> created at line 99.
Found 10-bit comparator less for signal <addra$cmp_lt0000> created at line 99.
Found 10-bit comparator less for signal <addra$cmp_lt0001> created at line 99.
Found 1-bit register for signal <ck25MHz>.
Found T flip-flop for signal <cycle<0>>.
Found 2-bit register for signal <tur>.
Found 10-bit comparator greatequal for signal <tur$cmp_ge0000> created at line 90.
Found 10-bit comparator greatequal for signal <tur$cmp_ge0001> created at line 90.
Summary:
inferred 2 Counter(s).
inferred 1 Accumulator(s).
inferred 1 T-type flip-flop(s).
inferred 13 D-type flip-flop(s).
inferred 6 Comparator(s).
Unit <vga> synthesized.
Synthesizing Unit <top>.
Related source file is "top.v".
Unit <top> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 2
10-bit up counter : 2
# Accumulators : 1
15-bit updown accumulator : 1
# Registers : 7
1-bit register : 3
2-bit register : 2
3-bit register : 2
# Toggle Registers : 1
T flip-flop : 1
# Comparators : 6
10-bit comparator greatequal : 2
10-bit comparator greater : 2
10-bit comparator less : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Reading core <ipcore_dir/frameBuffer.ngc>.
Loading core <frameBuffer> for timing and area information for instance <inst_parrot>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Counters : 2
10-bit up counter : 2
# Accumulators : 1
15-bit updown accumulator : 1
# Registers : 14
Flip-Flops : 14
# Comparators : 6
10-bit comparator greatequal : 2
10-bit comparator greater : 2
10-bit comparator less : 2
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <top> ...
Optimizing unit <vga> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 49
Flip-Flops : 49
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : top.ngr
Top Level Output File Name : top
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 11
Cell Usage :
# BELS : 166
# GND : 2
# INV : 5
# LUT1 : 19
# LUT2 : 15
# LUT2_D : 1
# LUT2_L : 2
# LUT3 : 8
# LUT3_D : 3
# LUT3_L : 1
# LUT4 : 32
# LUT4_D : 3
# LUT4_L : 4
# MUXCY : 32
# MUXF5 : 2
# VCC : 2
# XORCY : 35
# FlipFlops/Latches : 52
# FD : 2
# FDE : 5
# FDR : 19
# FDRE : 26
# RAMS : 10
# RAMB16_S1_S1 : 8
# RAMB16_S4_S4 : 2
# Clock Buffers : 2
# BUFG : 1
# BUFGP : 1
# IO Buffers : 10
# OBUF : 10
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s1200efg320-5
Number of Slices: 50 out of 8672 0%
Number of Slice Flip Flops: 52 out of 17344 0%
Number of 4 input LUTs: 93 out of 17344 0%
Number of IOs: 11
Number of bonded IOBs: 11 out of 250 4%
Number of BRAMs: 10 out of 28 35%
Number of GCLKs: 2 out of 24 8%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-------+
vgainst/ck25MHz1 | BUFG | 61 |
mclk | BUFGP | 1 |
vgainst/inst_parrot/N1 | NONE(vgainst/inst_parrot/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp1x1.ram)| 10 |
-----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 6.713ns (Maximum Frequency: 148.970MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 4.063ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'vgainst/ck25MHz1'
Clock period: 6.713ns (frequency: 148.970MHz)
Total number of paths / destination ports: 4095 / 269
-------------------------------------------------------------------------
Delay: 6.713ns (Levels of Logic = 4)
Source: vgainst/Hcnt_5 (FF)
Destination: vgainst/addra_14 (FF)
Source Clock: vgainst/ck25MHz1 rising
Destination Clock: vgainst/ck25MHz1 rising
Data Path: vgainst/Hcnt_5 to vgainst/addra_14
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 8 0.514 0.712 vgainst/Hcnt_5 (vgainst/Hcnt_5)
LUT3:I1->O 2 0.612 0.449 vgainst/addra_cmp_eq00022 (vgainst/addra_cmp_eq00022)
LUT4:I1->O 16 0.612 0.882 vgainst/addra_not0002112 (vgainst/addra_mux0000<14>_inv)
LUT4:I3->O 1 0.612 0.360 vgainst/addra_not000210 (vgainst/addra_not000210)
LUT4:I3->O 15 0.612 0.864 vgainst/addra_not000242 (vgainst/addra_not0002)
FDRE:CE 0.483 vgainst/addra_0
----------------------------------------
Total 6.713ns (3.445ns logic, 3.268ns route)
(51.3% logic, 48.7% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'mclk'
Clock period: 1.689ns (frequency: 592.084MHz)
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 1.689ns (Levels of Logic = 0)
Source: vgainst/ck25MHz (FF)
Destination: vgainst/ck25MHz (FF)
Source Clock: mclk rising
Destination Clock: mclk rising
Data Path: vgainst/ck25MHz to vgainst/ck25MHz
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 2 0.514 0.380 vgainst/ck25MHz (vgainst/ck25MHz1)
FDR:R 0.795 vgainst/ck25MHz
----------------------------------------
Total 1.689ns (1.309ns logic, 0.380ns route)
(77.5% logic, 22.5% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'vgainst/ck25MHz1'
Total number of paths / destination ports: 10 / 10
-------------------------------------------------------------------------
Offset: 4.063ns (Levels of Logic = 1)
Source: vgainst/HS (FF)
Destination: HS (PAD)
Source Clock: vgainst/ck25MHz1 rising
Data Path: vgainst/HS to HS
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.514 0.380 vgainst/HS (vgainst/HS)
OBUF:I->O 3.169 HS_OBUF (HS)
----------------------------------------
Total 4.063ns (3.683ns logic, 0.380ns route)
(90.6% logic, 9.4% route)
=========================================================================
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.09 secs
-->
Total memory usage is 205112 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos : 1 ( 0 filtered)