trap instruction page fault error and mode shifting from M-mode to U-mode in spike debug mode

[kommarisurendra]

while executing the assembly code with using csr instructions in spike debug mode the M-mode is shifting to low level modes(U or S)..
and also it showing " exception trap_instruction_page_fault " at parcicular pc address..

core 0: exception trap_instruction_page_fault, epc 0x00000000000100b0
core 0: tval 0x00000000000100b0

and also while executing csr instructions it is also showing like this-
core 0: 0x00000000000100b8 (0x30529073) csrw mtvec, t0
core 0: exception trap_illegal_instruction, epc 0x00000000000100b8
core 0: tval 0x0000000030529073