diff --git a/README.md b/README.md new file mode 100644 index 0000000..5503637 --- /dev/null +++ b/README.md @@ -0,0 +1,127 @@ +This is the repo of the generator tool riscv_disasm_from_sail, a tool that ingests the https://github.com/riscv/sail-riscv executable model of the RISCV instruction set and generates most of a disassembler for the architecture. + +# What is Sail ? + +Sail is a Domain Specific Language, a specialized programming language made for a narrow, singular purpose and not designed for general development of arbitrary programs (although it might end up, nonetheless, suitable for general development anyway). SQL and regular expressions are often-cited examples of DSLs. + +Sail’s specialized domain is describing Instruction Set Architectures in an executable form. + +# Why Sail ? + +Describing ISAs like RISCV and x86 (among others) in machine-readable executable formats has many rationales: + +1- ISAs are increasingly too complex for natural language. Even just describing the sequential semantics of an instruction - how it intreprets its addressing mode(s), how it fetches operands, how it computes a result, what registers/memory and/or any other architectural state it modifies or clobbers or saves or restores - can get unmanagebly tedious and confusing in natural language. + +Add to that the fact that ISAs often specify addtional semantics on top of simple sequential execution of instruction streams: traps, faults, interrupts, privilege levels, ABI conventions, memory models, etc…, and it becomes obvious that describing an ISA is itself a computationally complex task that requires a suitable formal language. + +2- Formal models enable automatic generation of ISA artifacts from a single source of truth. It’s clear, for instance, that assemblers and disassemblers are related, they “contain the same information”, in a certain sense. It follows that it’s wasteful and error-prone to write them by hand: it constitutes a duplication of information. + +A well-defined executable model of the ISA could in principle contain the core information needed to generate both. An assembler-generator would ingest this model and generate an assembler, and a disassembler-generator would ingest the same model and generate a disassembler. This is commonly called the [Model-Driven Engineering](https://en.wikipedia.org/wiki/Model-driven_engineering) development methodology. Sail enables the application of MDE to the development of ISA artifacts. + +# Why is Sail a new language? + +The fact that Sail is an entirely new language and not a library, a framework or an internal DSL in an existing one deserves an explanation. Being a new language enables Sail to optimize its syntax and semantics for its domain, at the cost of larger development effort for the Sail compiler team. + +For instance, the following are 2 features that Sail provides specifically to syntax-sugar ISA development: + + 1- Dependent typing: Sail can track values on the type level, such that it's possible to define the number 2 as a type, and derive a new type (e.g. 4) from it using type-level arithmetics. Dependent typing is an advanced feature not present in the vast majority of mainstream languages, even functional ones. Sail uses this advanced type system to ensure additional type safety and consistency checking for architectural parameters (e.g. register file width) at compile time. + +2- Bidirectional mappings: Sail mappings are functions that can be run in both direction. Their type signature is a hint of their nature: while functions are typed A→ B, meaning they derive values of type B from values of type A, mappings are typed A↔B, meaning they can go “back and forth” from values of any type to values of the other. Mappings can be a very concise way of specifying bidirectional computations, such as describing how to obtain a structured object representing an instruction from the binary encoding of the instruction, how to parse the binary form of the instruction, and at the same time also how to serialize the structured object back to its binary encoding. + +# How to run + +The `end2end-smoke-test` workflow file in the CI directory (.github) setups the generator’s environment from scratch on a new machine. It should be viewed as the authoritative guide on how to run the generator on a new machine, even if it gets out of sync of this README. (In such case, please update the README to reflect the file.) + +The steps are reproduced below with explanations: + +## 1- Download and install Ocaml toolchain + +Ocaml has an installation guide [here](https://ocaml.org/install#linux_mac_bsd), but in a nutshell, the following commands are enough on most *nix systems (any Linux, MacOS, any BSD): + +```bash +sudo apt-get install bubblewrap +bash -c "sh <(curl -fsSL [https://opam.ocaml.org/install.sh](https://opam.ocaml.org/install.sh))" +opam init +opam install dune +``` + +And this is indeed what the workflow file does, with the exception that it pipes values + +to serve as interactive inputs to the first 2 commands because can’t require user inputs. + +- The `bubblewrap` package is a low-level interface for creating and managing sandboxed environments, `opam` requires it by default on Linux systems to run arbitrary code safely +- The second command downloads Ocaml and installs it, +- The third command initializes `opam`, Ocaml’s package downloader/installer and toolchain manager (manages the installation of different Ocaml compilers on the same machine), and +- The fourth downloads and installs `dune`, Ocaml’s package manager. + +> P.S. It would be correct to say that exactly one out of {`opam`, `dune`} is actually needed, but alas, that’s a problem for the Ocaml language community to sort out, not this tool. +> + +The following are optional development dependencies that aren’t strictly needed for running the generator, but might be useful if you want to modify the generator: + +```bash +opam install ocaml-lsp-server odoc ocamlformat utop +``` + +## 2- Install generator dependencies + +The generator tool itself has almost no dependencies except Libsail, the Sail compiler exposed as a library. It also requires installing Sail itself as a shell command because the Sail standard library must be downloaded, and requires the system-level command line tool `z3`, the popular SMT solver from Microsoft Research, exposed as a cmd tool. + +In commands: + +```bash +git clone https://github.com/moste00/riscv_disasm_from_sail.git +cd riscv_disasm_from_sail && source ~/.bash_profile +export OPAMCONFIRMLEVEL=yes +opam update + +opam install sail=0.18 +sudo apt-get install z3 +opam install . --deps-only +``` + +It’s very important to fix the exact Sail version, as above, because Sail is in heavy development and every version breaks its predecessor’s APIs. The version is determined by what the maintainers of the `sail-riscv` model choose. + +## 3- Fetch the sail-riscv model + +Because Sail is a large language and this tool is *not* a general purpose Sail→C compiler, only a subset of Sail’s features is actually supported. More generally, the tool also makes some specific assumptions about its input code, for example that the logic to stringify instructions is a mapping (and not, e.g., a function). Taken together, those 2 facts imply that the input sail-riscv model could break the tool if it violates those assumptions or uses more Sail features than what the tool supports. + +Therefore, `riscv_disasm_from_sail` versions its input. In `sail.hash.txt`, there is a git sha hash that states the latest sail-riscv version that the tool ran successfully on. It’s generally preferable for this version to not lag the sail-riscv model latest commit on master by too much (~1 month worth of commits are the limits), and it’s a bug in `riscv_disasm_from_sail` if it crashes on the latest master commit. + +To get the input model, run the following in the parent directory of the tool: + +```bash +git clone https://github.com/riscv/sail-riscv.git +cd sail-riscv +git reset --hard $(cat sail.hash.txt) +``` + +## 4- Run the generator on the input + +Finally, run the following command from the generator’s directory to obtain the generated C code: + +```bash +source ~/.bash_profile && dune exec --profile release -- riscv_disasm_from_sail -f sail.filepaths.txt +``` + +## 5- Or just copy riscv_disasm + +The outputs of the generator for the model version specified by sail.hash.txt is also kept in this repo, this is a quality-of-life feature for 2 reasons: + +1- If a commit to `riscv_disasm_from_sail` changed the generated code, the diff to the generated code is accompanied by the diff to the generator’s logic as an explanation + +2- Users can simply copy the generated code instead of going through steps 1..4 above + +As a downside, if the generated C code is used elsewhere, such as in a RISCV module in https://github.com/capstone-engine/capstone disassembler framework (the primary purpose and raison d'être of this tool), this means that the handwritten code in riscv_disasm (all the files not having “.gen” in their names) MUST NOT be modified in that site of use, only here in this repo. + +# Updating the input model version + +To update the version of sail-riscv, you have to update sail.filepaths.txt and sail.hash.txt. To update the first, run : + +```bash +tools/riscv-ls.sh +``` + +This will (ab)use the makefile in the sail-riscv repo to print an ordered list of all files that comprise the model. This is also the procedure to follow if the sail-riscv directory is not the direct filetree-sibling of the riscv_disasm_from_sail directory, as the paths in the committed sail.filepaths.txt assume this relationship, but you can override those paths by running the above command and giving it any valid path to the sail-riscv model directory. + +Updating the hash must be done manually as of yet, query the sail-riscv repo version (e.g. using git log) and paste the version in sail.hash.txt. \ No newline at end of file diff --git a/bin/main.ml b/bin/main.ml index 064c6c6..5979b4a 100644 --- a/bin/main.ml +++ b/bin/main.ml @@ -46,23 +46,7 @@ let anon_arg_handler a = let () = Arg.parse arg_spec anon_arg_handler usage_msg -let read_filepaths name = - let names = ref [] in - let file_chnl = open_in name in - try - while true do - names := input_line file_chnl :: !names - done; - [""] (*UNREACHABLE, just to guide type checker*) - with - | End_of_file -> - close_in file_chnl; - List.rev !names - | e -> - close_in_noerr file_chnl; - raise e - -let filepaths = read_filepaths !paths_filename +let filepaths = Utils.read_file !paths_filename let initial_typeenv = Type_check.initial_env @@ -94,6 +78,14 @@ let asm = Gen_assembler.gen_asm ast analysis let asm_str, tables_str = Stringify.stringify_assembler asm typdefwalker +let gen_instr_types_conf = + Gen_instr_types.read_config "sail.instr_types_excluded_enums.txt" + +let instr_types = Gen_instr_types.gen_instr_types analysis gen_instr_types_conf + +let instr_types_str, instr_types_mapping_str = + Stringify.stringify_instr_types instr_types typdefwalker + let () = write_c_file Constants.ast_type_filename ctypedefs_str let () = write_c_file Constants.decode_logic_filename proc_dec_str @@ -111,3 +103,11 @@ let () = let () = write_c_file Constants.ast2str_tables_filename tables_str ~additional_includes:["\"" ^ Constants.ast_type_filename ^ "\""] + +let () = + write_c_file Constants.instr_types_filename instr_types_str + ~additional_includes:["\"" ^ Constants.ast_type_filename ^ "\""] + +let () = + write_c_file Constants.instr_types_mapping_filename instr_types_mapping_str + ~additional_includes:["\"" ^ Constants.instr_types_filename ^ "\""] diff --git a/lib/constants.ml b/lib/constants.ml index 826c3c2..3a6bfef 100644 --- a/lib/constants.ml +++ b/lib/constants.ml @@ -25,3 +25,7 @@ let ast_assembly_mapping = "assembly" let assembler_filename = "riscv_ast2str.gen.inc" let ast2str_tables_filename = "riscv_ast2str_tbls.gen.inc" + +let instr_types_filename = "riscv_insn.gen.inc" + +let instr_types_mapping_filename = "riscv_insn_mapping.gen.inc" diff --git a/lib/gen_instr_types.ml b/lib/gen_instr_types.ml new file mode 100644 index 0000000..c24798a --- /dev/null +++ b/lib/gen_instr_types.ml @@ -0,0 +1,36 @@ +open Utils +open Sail_analysis +open Hashset + +type config = { exclude_enums : string set } + +type instr_types = (string, int * string list) Hashtbl.t + +let read_config path = + let c = { exclude_enums = Hashtbl.create 10 } in + List.iter (fun e -> set_add c.exclude_enums e) (Utils.read_file path); + c + +let add_instr_types conf case_names_to_instr_types analysis case_name + enum_typenames = + let do_add name types = Hashtbl.add case_names_to_instr_types name types in + let applicable_enums = + List.filter + (fun (_, name) -> not (set_contains conf.exclude_enums name)) + enum_typenames + in + match applicable_enums with + | [] -> do_add case_name (-1, [case_name]) + | [(i, enum_typename)] -> + do_add case_name (i, get_all_members_of_enum analysis enum_typename) + | _ -> failwith "FAIL" + +let gen_instr_types analysis conf = + let case_names_to_enum_typenames = get_all_cases_with_enum_members analysis in + let instr_types = + Hashtbl.create (Hashtbl.length case_names_to_enum_typenames) + in + Hashtbl.iter + (add_instr_types conf instr_types analysis) + case_names_to_enum_typenames; + instr_types diff --git a/lib/sail_analysis.ml b/lib/sail_analysis.ml index 057918f..4b5aeaf 100644 --- a/lib/sail_analysis.ml +++ b/lib/sail_analysis.ml @@ -376,6 +376,12 @@ let get_case_arg_size ana case_name arg_idx = let is_member_of_enum ana maybe_member = Type_check.is_enum_member maybe_member ana.sail_env.e +let get_all_members_of_enum ana enum_typename = + let member_ids = Bindings.find (mk_id enum_typename) ana.sail_env.enums in + let members = ref [] in + IdSet.iter (fun i -> members := id_to_str i :: !members) member_ids; + !members + let get_bv2str_mapping ana map_name = let bv2str_mappings = ana.mapping_ctx.to_string_mappings_registery.bv2string_mappings @@ -399,3 +405,27 @@ let get_struct2str_mapping ana map_name = ana.mapping_ctx.to_string_mappings_registery.struct2string_mappings in Option.map snd (Hashtbl.find_opt struct2str_mappings map_name) + +let get_all_cases_with_enum_members ana = + let cases_type_sigs = ana.type_ctx.union_cases_type_signatures in + let cases_with_enum_members = + Hashtbl.create (Hashtbl.length cases_type_sigs) + in + Hashtbl.iter + (fun case_name typesig -> + let enum_types = + List.mapi + (fun i typ -> + match typ with + | Named_type name when Bindings.mem (mk_id name) ana.sail_env.enums + -> + Some (i, name) + | _ -> None + ) + typesig + in + let enum_types = List.filter_map (fun a -> a) enum_types in + Hashtbl.add cases_with_enum_members case_name enum_types + ) + cases_type_sigs; + cases_with_enum_members diff --git a/lib/sail_analysis.mli b/lib/sail_analysis.mli index 5a75911..2aa4539 100644 --- a/lib/sail_analysis.mli +++ b/lib/sail_analysis.mli @@ -20,6 +20,8 @@ val get_case_arg_size : sail_analysis_result -> string -> int -> int option val is_member_of_enum : sail_analysis_result -> id -> bool +val get_all_members_of_enum : sail_analysis_result -> string -> string list + val get_bv2str_mapping : sail_analysis_result -> string -> bv2str_table option val get_enum2str_mapping : @@ -30,3 +32,6 @@ val get_bool2str_mapping : val get_struct2str_mapping : sail_analysis_result -> string -> struct2str_table option + +val get_all_cases_with_enum_members : + sail_analysis_result -> (string, (int * string) list) Hashtbl.t diff --git a/lib/stringify.ml b/lib/stringify.ml index 5e68f6b..62567c9 100644 --- a/lib/stringify.ml +++ b/lib/stringify.ml @@ -321,7 +321,39 @@ let stringfy_tostr_logic ({ walker; _ } as str_state) i tostr = ^ ") {" ^ true_assignments ^ "}" ^ "else {" ^ false_asssignments ^ "} ", "" ) - | Struct2str (_, _, _) -> ("/* TODO */", "") + | Struct2str (_, arg_idx, tbl) -> + let struct_arg = + ast_c_parameter ^ "->" ^ Option.get (get_member_path walker arg_idx) + in + let cases = ref [] in + Hashtbl.iter + (fun kv_pairs string -> + let cond = + List.map + (fun (key, valu) -> + "(" ^ struct_arg ^ "." ^ key ^ " == " + ^ ( match valu with + | Bv_const s -> s + | Bool_const b -> if b then "1" else "0" + | Binding s -> s + | Enum_lit e -> add_prefix_unless_exists identifier_prefix e + ) + ^ ")" + ) + kv_pairs + in + let cond = String.concat " && " cond in + let case = + "if (" ^ cond ^ ") { s" ^ string_of_int i ^ " = \"" ^ string + ^ "\"; s" ^ string_of_int i ^ "_len = " + ^ string_of_int (String.length string) + ^ ";} else " + in + cases := case :: !cases + ) + tbl; + + (String.concat "" !cases ^ ";", "") | Intrinsic_tostr_logic (name, args) -> let sep = if List.length args != 0 then "," else "" in let args = List.map (stringify_intrinsic_logic_arg walker) args in @@ -338,7 +370,8 @@ let stringify_subcase_body ({ walker; _ } as str_state) body = let i = string_of_int i in match tostr with | Intrinsic_tostr_logic _ -> - "char s" ^ i ^ "_buffer[RISCV_TEMP_BUFFER_MAX_LEN] = {0}; char *s" ^ i + "char s" ^ i + ^ "_buffer[RISCV_TEMP_BUFFER_MAX_LEN] = {0}; char *s" ^ i ^ " = s" ^ i ^ "_buffer; size_t s" ^ i ^ "_len = 0;" | _ -> "char *s" ^ i ^ " = \"\" ; size_t s" ^ i ^ "_len = 0;" ) @@ -412,3 +445,81 @@ let stringify_assembler asm walker = ( prologue ^ concat_defs ^ procedure_start ^ procedure_body ^ procedure_end, tables ) + +let stringify_instr_types instr_types typedef_walker = + let enum_def = Buffer.create 10000 in + let mapping = Buffer.create 10000 in + let mapping_table = Buffer.create 10000 in + + let put = Buffer.add_string enum_def in + let apnd = Buffer.add_string mapping in + let prnt = Buffer.add_string mapping_table in + + put "enum "; + put (String.lowercase_ascii identifier_prefix); + put "insn { "; + + prnt " = {"; + + apnd "uint16_t get_insn_type("; + apnd ("struct " ^ ast_sail_def_name ^ " *" ^ ast_c_parameter); + apnd ") { switch ("; + apnd (ast_c_parameter ^ "->" ^ ast_sail_def_name ^ generated_ast_enum_suffix); + apnd ") {"; + + let max_num_instr_types = ref 0 in + Hashtbl.iter + (fun case_name (i, types) -> + set_walker_case typedef_walker case_name; + let case_name = add_prefix_unless_exists identifier_prefix case_name in + put "\n//--------------------- "; + put case_name; + put "--------------------- \n"; + + List.iter + (fun typename -> + put "RISCV_INSN_"; + put (strip_prefix_if_exists identifier_prefix typename); + put "," + ) + types; + let len = List.length types in + if len > !max_num_instr_types then max_num_instr_types := len; + + prnt ("[" ^ case_name ^ "] = {"); + prnt + (String.concat "," + (List.map (add_prefix_unless_exists identifier_prefix) types) + ); + prnt "},"; + + if i != -1 then ( + apnd "case "; + apnd case_name; + apnd ": return to_insn["; + apnd case_name; + apnd "]["; + apnd (ast_c_parameter ^ "->"); + apnd (Option.get (get_member_path typedef_walker i)); + apnd "];" + ) + ) + instr_types; + (* Close the enum definition *) + put "};"; + (* Close the function definition *) + apnd "default: return to_insn["; + apnd (ast_c_parameter ^ "->" ^ ast_sail_def_name ^ generated_ast_enum_suffix); + apnd "][0];}}"; + (* Close the table definition *) + prnt "};"; + let table_decl = + "static const uint16_t to_insn[" + ^ string_of_int (Hashtbl.length instr_types) + ^ "][" + ^ string_of_int !max_num_instr_types + ^ "]" + in + ( Buffer.contents enum_def, + table_decl ^ Buffer.contents mapping_table ^ Buffer.contents mapping + ) diff --git a/lib/utils.ml b/lib/utils.ml index 81b4ea3..7f04095 100644 --- a/lib/utils.ml +++ b/lib/utils.ml @@ -53,6 +53,14 @@ let str_starts_with prefix str = let add_prefix_unless_exists prefix str = if str_starts_with prefix str then str else prefix ^ str +let strip_prefix_if_exists prefix str = + if not (str_starts_with prefix str) then str + else ( + let plen = String.length prefix in + let len = String.length str in + String.sub str plen (len - plen) + ) + let get_some_or_failwith opt msg = match opt with Some thing -> thing | None -> failwith msg @@ -61,3 +69,19 @@ let assert_empty_or_length1_or_failwith listt msg = let get_sole_element_or_none listt = if List.length listt = 1 then Some (List.nth listt 0) else None + +let read_file name = + let names = ref [] in + let file_chnl = open_in name in + try + while true do + names := input_line file_chnl :: !names + done; + [""] (*UNREACHABLE, just to guide type checker*) + with + | End_of_file -> + close_in file_chnl; + List.rev !names + | e -> + close_in_noerr file_chnl; + raise e diff --git a/riscv_disasm/riscv_ast2str.gen.inc b/riscv_disasm/riscv_ast2str.gen.inc index 41404b6..87d5ab8 100644 --- a/riscv_disasm/riscv_ast2str.gen.inc +++ b/riscv_disasm/riscv_ast2str.gen.inc @@ -1466,7 +1466,29 @@ void ast2str(struct ast *tree, char *buff, riscv_conf *conf) { char *s5 = s5_buffer; size_t s5_len = 0; char *s6 = ""; - size_t s6_len = 0; /* TODO */ + size_t s6_len = 0; + if ((tree->ast_node.mul.mul_op.high == 1) && + (tree->ast_node.mul.mul_op.signed_rs1 == 1) && + (tree->ast_node.mul.mul_op.signed_rs2 == 1)) { + s0 = "mulh"; + s0_len = 4; + } else if ((tree->ast_node.mul.mul_op.high == 1) && + (tree->ast_node.mul.mul_op.signed_rs1 == 0) && + (tree->ast_node.mul.mul_op.signed_rs2 == 0)) { + s0 = "mulhu"; + s0_len = 5; + } else if ((tree->ast_node.mul.mul_op.high == 1) && + (tree->ast_node.mul.mul_op.signed_rs1 == 1) && + (tree->ast_node.mul.mul_op.signed_rs2 == 0)) { + s0 = "mulhsu"; + s0_len = 6; + } else if ((tree->ast_node.mul.mul_op.high == 0) && + (tree->ast_node.mul.mul_op.signed_rs1 == 1) && + (tree->ast_node.mul.mul_op.signed_rs2 == 1)) { + s0 = "mul"; + s0_len = 3; + } else + ; spc(&s1, &s1_len, conf); reg_name(tree->ast_node.mul.rd, &s2, &s2_len); sep(&s3, &s3_len, conf); diff --git a/riscv_disasm/riscv_insn.gen.inc b/riscv_disasm/riscv_insn.gen.inc new file mode 100644 index 0000000..20bd82b --- /dev/null +++ b/riscv_disasm/riscv_insn.gen.inc @@ -0,0 +1,977 @@ +#ifndef __Riscv_insn_gen_inc__ +#define __Riscv_insn_gen_inc__ +#include + +#include + +#include "riscv_ast.gen.inc" +#include + +enum riscv_insn { + //--------------------- RISCV_REV8--------------------- + RISCV_INSN_REV8, + //--------------------- RISCV_WXTYPE--------------------- + RISCV_INSN_WX_VSUBU, + RISCV_INSN_WX_VSUB, + RISCV_INSN_WX_VADDU, + RISCV_INSN_WX_VADD, + //--------------------- RISCV_C_SRLI_HINT--------------------- + RISCV_INSN_C_SRLI_HINT, + //--------------------- RISCV_AES64DS--------------------- + RISCV_INSN_AES64DS, + //--------------------- RISCV_VMSBF_M--------------------- + RISCV_INSN_VMSBF_M, + //--------------------- RISCV_RTYPE--------------------- + RISCV_INSN_XOR, + RISCV_INSN_SUB, + RISCV_INSN_SRL, + RISCV_INSN_SRA, + RISCV_INSN_SLTU, + RISCV_INSN_SLT, + RISCV_INSN_SLL, + RISCV_INSN_OR, + RISCV_INSN_AND, + RISCV_INSN_ADD, + //--------------------- RISCV_VFMERGE--------------------- + RISCV_INSN_VFMERGE, + //--------------------- RISCV_RIVVTYPE--------------------- + RISCV_INSN_IVV_VWREDSUMU, + RISCV_INSN_IVV_VWREDSUM, + //--------------------- RISCV_C_ZEXT_W--------------------- + RISCV_INSN_C_ZEXT_W, + //--------------------- RISCV_SFENCE_INVAL_IR--------------------- + RISCV_INSN_SFENCE_INVAL_IR, + //--------------------- RISCV_XPERM4--------------------- + RISCV_INSN_XPERM4, + //--------------------- RISCV_C_AND--------------------- + RISCV_INSN_C_AND, + //--------------------- RISCV_AES32DSI--------------------- + RISCV_INSN_AES32DSI, + //--------------------- RISCV_RORI--------------------- + RISCV_INSN_RORI, + //--------------------- RISCV_JALR--------------------- + RISCV_INSN_JALR, + //--------------------- RISCV_VMSIF_M--------------------- + RISCV_INSN_VMSIF_M, + //--------------------- RISCV_VLSSEGTYPE--------------------- + RISCV_INSN_VLSSEGTYPE, + //--------------------- RISCV_SHA512SIG1H--------------------- + RISCV_INSN_SHA512SIG1H, + //--------------------- RISCV_FLTQ_S--------------------- + RISCV_INSN_FLTQ_S, + //--------------------- RISCV_VXSG--------------------- + RISCV_INSN_VX_VSLIDEUP, + RISCV_INSN_VX_VSLIDEDOWN, + RISCV_INSN_VX_VRGATHER, + //--------------------- RISCV_VXCMPTYPE--------------------- + RISCV_INSN_VXCMP_VMSNE, + RISCV_INSN_VXCMP_VMSLTU, + RISCV_INSN_VXCMP_VMSLT, + RISCV_INSN_VXCMP_VMSLEU, + RISCV_INSN_VXCMP_VMSLE, + RISCV_INSN_VXCMP_VMSGTU, + RISCV_INSN_VXCMP_VMSGT, + RISCV_INSN_VXCMP_VMSEQ, + //--------------------- RISCV_C_LHU--------------------- + RISCV_INSN_C_LHU, + //--------------------- RISCV_JAL--------------------- + RISCV_INSN_JAL, + //--------------------- RISCV_ECALL--------------------- + RISCV_INSN_ECALL, + //--------------------- RISCV_C_FSWSP--------------------- + RISCV_INSN_C_FSWSP, + //--------------------- RISCV_VMVXS--------------------- + RISCV_INSN_VMVXS, + //--------------------- RISCV_C_FLD--------------------- + RISCV_INSN_C_FLD, + //--------------------- RISCV_SHIFTIWOP--------------------- + RISCV_INSN_SRLIW, + RISCV_INSN_SRAIW, + RISCV_INSN_SLLIW, + //--------------------- RISCV_UNZIP--------------------- + RISCV_INSN_UNZIP, + //--------------------- RISCV_ZICBOM--------------------- + RISCV_INSN_CBO_INVAL, + RISCV_INSN_CBO_FLUSH, + RISCV_INSN_CBO_CLEAN, + //--------------------- RISCV_SHA512SIG1--------------------- + RISCV_INSN_SHA512SIG1, + //--------------------- RISCV_NITYPE--------------------- + RISCV_INSN_NI_VNCLIPU, + RISCV_INSN_NI_VNCLIP, + //--------------------- RISCV_WFI--------------------- + RISCV_INSN_WFI, + //--------------------- RISCV_VVMTYPE--------------------- + RISCV_INSN_VVM_VMSBC, + RISCV_INSN_VVM_VMADC, + //--------------------- RISCV_MVXMATYPE--------------------- + RISCV_INSN_MVX_VNMSUB, + RISCV_INSN_MVX_VNMSAC, + RISCV_INSN_MVX_VMADD, + RISCV_INSN_MVX_VMACC, + //--------------------- RISCV_FLI_D--------------------- + RISCV_INSN_FLI_D, + //--------------------- RISCV_C_ADDI_HINT--------------------- + RISCV_INSN_C_ADDI_HINT, + //--------------------- RISCV_MASKTYPEX--------------------- + RISCV_INSN_MASKTYPEX, + //--------------------- RISCV_FROUNDNX_D--------------------- + RISCV_INSN_FROUNDNX_D, + //--------------------- RISCV_FROUND_D--------------------- + RISCV_INSN_FROUND_D, + //--------------------- RISCV_VSETIVLI--------------------- + RISCV_INSN_VSETIVLI, + //--------------------- RISCV_FMAXM_D--------------------- + RISCV_INSN_FMAXM_D, + //--------------------- RISCV_C_SD--------------------- + RISCV_INSN_C_SD, + //--------------------- RISCV_F_BIN_TYPE_H--------------------- + RISCV_INSN_FSGNJ_H, + RISCV_INSN_FSGNJX_H, + RISCV_INSN_FSGNJN_H, + RISCV_INSN_FMIN_H, + RISCV_INSN_FMAX_H, + RISCV_INSN_FLT_H, + RISCV_INSN_FLE_H, + RISCV_INSN_FEQ_H, + //--------------------- RISCV_ZBKB_PACKW--------------------- + RISCV_INSN_ZBKB_PACKW, + //--------------------- RISCV_FVVMTYPE--------------------- + RISCV_INSN_FVVM_VMFNE, + RISCV_INSN_FVVM_VMFLT, + RISCV_INSN_FVVM_VMFLE, + RISCV_INSN_FVVM_VMFEQ, + //--------------------- RISCV_VMVSX--------------------- + RISCV_INSN_VMVSX, + //--------------------- RISCV_F_UN_RM_TYPE_D--------------------- + RISCV_INSN_FSQRT_D, + RISCV_INSN_FCVT_W_D, + RISCV_INSN_FCVT_WU_D, + RISCV_INSN_FCVT_S_D, + RISCV_INSN_FCVT_L_D, + RISCV_INSN_FCVT_LU_D, + RISCV_INSN_FCVT_D_WU, + RISCV_INSN_FCVT_D_W, + RISCV_INSN_FCVT_D_S, + RISCV_INSN_FCVT_D_LU, + RISCV_INSN_FCVT_D_L, + //--------------------- RISCV_ORCB--------------------- + RISCV_INSN_ORCB, + //--------------------- RISCV_C_MUL--------------------- + RISCV_INSN_C_MUL, + //--------------------- RISCV_SM3P1--------------------- + RISCV_INSN_SM3P1, + //--------------------- RISCV_CLMUL--------------------- + RISCV_INSN_CLMUL, + //--------------------- RISCV_FLEQ_S--------------------- + RISCV_INSN_FLEQ_S, + //--------------------- RISCV_WVXTYPE--------------------- + RISCV_INSN_WVX_VWMULU, + RISCV_INSN_WVX_VWMULSU, + RISCV_INSN_WVX_VWMUL, + RISCV_INSN_WVX_VSUBU, + RISCV_INSN_WVX_VSUB, + RISCV_INSN_WVX_VADDU, + RISCV_INSN_WVX_VADD, + //--------------------- RISCV_FMAXM_S--------------------- + RISCV_INSN_FMAXM_S, + //--------------------- RISCV_C_ILLEGAL--------------------- + RISCV_INSN_C_ILLEGAL, + //--------------------- RISCV_NXSTYPE--------------------- + RISCV_INSN_NXS_VNSRL, + RISCV_INSN_NXS_VNSRA, + //--------------------- RISCV_VSOXSEGTYPE--------------------- + RISCV_INSN_VSOXSEGTYPE, + //--------------------- RISCV_C_NOP--------------------- + RISCV_INSN_C_NOP, + //--------------------- RISCV_VXMCTYPE--------------------- + RISCV_INSN_VXMC_VMSBC, + RISCV_INSN_VXMC_VMADC, + //--------------------- RISCV_MMTYPE--------------------- + RISCV_INSN_MM_VMXOR, + RISCV_INSN_MM_VMXNOR, + RISCV_INSN_MM_VMORN, + RISCV_INSN_MM_VMOR, + RISCV_INSN_MM_VMNOR, + RISCV_INSN_MM_VMNAND, + RISCV_INSN_MM_VMANDN, + RISCV_INSN_MM_VMAND, + //--------------------- RISCV_F_UN_TYPE_S--------------------- + RISCV_INSN_FMV_X_W, + RISCV_INSN_FMV_W_X, + RISCV_INSN_FCLASS_S, + //--------------------- RISCV_NVTYPE--------------------- + RISCV_INSN_NV_VNCLIPU, + RISCV_INSN_NV_VNCLIP, + //--------------------- RISCV_AES64KS2--------------------- + RISCV_INSN_AES64KS2, + //--------------------- RISCV_AES32ESMI--------------------- + RISCV_INSN_AES32ESMI, + //--------------------- RISCV_F_MADD_TYPE_H--------------------- + RISCV_INSN_FNMSUB_H, + RISCV_INSN_FNMADD_H, + RISCV_INSN_FMSUB_H, + RISCV_INSN_FMADD_H, + //--------------------- RISCV_FROUNDNX_H--------------------- + RISCV_INSN_FROUNDNX_H, + //--------------------- RISCV_MOVETYPEI--------------------- + RISCV_INSN_MOVETYPEI, + //--------------------- RISCV_FLTQ_H--------------------- + RISCV_INSN_FLTQ_H, + //--------------------- RISCV_C_LW--------------------- + RISCV_INSN_C_LW, + //--------------------- RISCV_C_LWSP--------------------- + RISCV_INSN_C_LWSP, + //--------------------- RISCV_C_ADDI16SP--------------------- + RISCV_INSN_C_ADDI16SP, + //--------------------- RISCV_SHA512SIG0L--------------------- + RISCV_INSN_SHA512SIG0L, + //--------------------- RISCV_SM3P0--------------------- + RISCV_INSN_SM3P0, + //--------------------- RISCV_SM4ED--------------------- + RISCV_INSN_SM4ED, + //--------------------- RISCV_FMINM_D--------------------- + RISCV_INSN_FMINM_D, + //--------------------- RISCV_AES64IM--------------------- + RISCV_INSN_AES64IM, + //--------------------- RISCV_VLRETYPE--------------------- + RISCV_INSN_VLRETYPE, + //--------------------- RISCV_VFMVFS--------------------- + RISCV_INSN_VFMVFS, + //--------------------- RISCV_CTZ--------------------- + RISCV_INSN_CTZ, + //--------------------- RISCV_FMVH_X_D--------------------- + RISCV_INSN_FMVH_X_D, + //--------------------- RISCV_SLLIUW--------------------- + RISCV_INSN_SLLIUW, + //--------------------- RISCV_FMINM_S--------------------- + RISCV_INSN_FMINM_S, + //--------------------- RISCV_ZBA_RTYPEUW--------------------- + RISCV_INSN_SH3ADDUW, + RISCV_INSN_SH2ADDUW, + RISCV_INSN_SH1ADDUW, + RISCV_INSN_ADDUW, + //--------------------- RISCV_F_BIN_RM_TYPE_D--------------------- + RISCV_INSN_FSUB_D, + RISCV_INSN_FMUL_D, + RISCV_INSN_FDIV_D, + RISCV_INSN_FADD_D, + //--------------------- RISCV_C_ADD_HINT--------------------- + RISCV_INSN_C_ADD_HINT, + //--------------------- RISCV_F_MADD_TYPE_S--------------------- + RISCV_INSN_FNMSUB_S, + RISCV_INSN_FNMADD_S, + RISCV_INSN_FMSUB_S, + RISCV_INSN_FMADD_S, + //--------------------- RISCV_ZIP--------------------- + RISCV_INSN_ZIP, + //--------------------- RISCV_SHA512SUM1--------------------- + RISCV_INSN_SHA512SUM1, + //--------------------- RISCV_C_LDSP--------------------- + RISCV_INSN_C_LDSP, + //--------------------- RISCV_F_UN_RM_TYPE_H--------------------- + RISCV_INSN_FSQRT_H, + RISCV_INSN_FCVT_W_H, + RISCV_INSN_FCVT_WU_H, + RISCV_INSN_FCVT_S_H, + RISCV_INSN_FCVT_L_H, + RISCV_INSN_FCVT_LU_H, + RISCV_INSN_FCVT_H_WU, + RISCV_INSN_FCVT_H_W, + RISCV_INSN_FCVT_H_S, + RISCV_INSN_FCVT_H_LU, + RISCV_INSN_FCVT_H_L, + RISCV_INSN_FCVT_H_D, + RISCV_INSN_FCVT_D_H, + //--------------------- RISCV_CPOP--------------------- + RISCV_INSN_CPOP, + //--------------------- RISCV_FWFTYPE--------------------- + RISCV_INSN_FWF_VSUB, + RISCV_INSN_FWF_VADD, + //--------------------- RISCV_FWVTYPE--------------------- + RISCV_INSN_FWV_VSUB, + RISCV_INSN_FWV_VADD, + //--------------------- RISCV_ZBB_RTYPE--------------------- + RISCV_INSN_XNOR, + RISCV_INSN_ROR, + RISCV_INSN_ROL, + RISCV_INSN_ORN, + RISCV_INSN_MINU, + RISCV_INSN_MIN, + RISCV_INSN_MAXU, + RISCV_INSN_MAX, + RISCV_INSN_ANDN, + //--------------------- RISCV_SM4KS--------------------- + RISCV_INSN_SM4KS, + //--------------------- RISCV_RORIW--------------------- + RISCV_INSN_RORIW, + //--------------------- RISCV_NXTYPE--------------------- + RISCV_INSN_NX_VNCLIPU, + RISCV_INSN_NX_VNCLIP, + //--------------------- RISCV_C_ADDIW--------------------- + RISCV_INSN_C_ADDIW, + //--------------------- RISCV_C_LD--------------------- + RISCV_INSN_C_LD, + //--------------------- RISCV_CTZW--------------------- + RISCV_INSN_CTZW, + //--------------------- RISCV_XPERM8--------------------- + RISCV_INSN_XPERM8, + //--------------------- RISCV_ITYPE--------------------- + RISCV_INSN_XORI, + RISCV_INSN_SLTIU, + RISCV_INSN_SLTI, + RISCV_INSN_ORI, + RISCV_INSN_ANDI, + RISCV_INSN_ADDI, + //--------------------- RISCV_VID_V--------------------- + RISCV_INSN_VID_V, + //--------------------- RISCV_FENCE--------------------- + RISCV_INSN_FENCE, + //--------------------- RISCV_C_FLWSP--------------------- + RISCV_INSN_C_FLWSP, + //--------------------- RISCV_STORE--------------------- + RISCV_INSN_STORE, + //--------------------- RISCV_F_BIN_TYPE_S--------------------- + RISCV_INSN_FSGNJ_S, + RISCV_INSN_FSGNJX_S, + RISCV_INSN_FSGNJN_S, + RISCV_INSN_FMIN_S, + RISCV_INSN_FMAX_S, + RISCV_INSN_FLT_S, + RISCV_INSN_FLE_S, + RISCV_INSN_FEQ_S, + //--------------------- RISCV_VSSEGTYPE--------------------- + RISCV_INSN_VSSEGTYPE, + //--------------------- RISCV_F_BIN_TYPE_D--------------------- + RISCV_INSN_FSGNJ_D, + RISCV_INSN_FSGNJX_D, + RISCV_INSN_FSGNJN_D, + RISCV_INSN_FMIN_D, + RISCV_INSN_FMAX_D, + RISCV_INSN_FLT_D, + RISCV_INSN_FLE_D, + RISCV_INSN_FEQ_D, + //--------------------- RISCV_ZICOND_RTYPE--------------------- + RISCV_INSN_CZERO_NEZ, + RISCV_INSN_CZERO_EQZ, + //--------------------- RISCV_C_FSDSP--------------------- + RISCV_INSN_C_FSDSP, + //--------------------- RISCV_SRET--------------------- + RISCV_INSN_SRET, + //--------------------- RISCV_STORE_FP--------------------- + RISCV_INSN_STORE_FP, + //--------------------- RISCV_C_JALR--------------------- + RISCV_INSN_C_JALR, + //--------------------- RISCV_FENCE_TSO--------------------- + RISCV_INSN_FENCE_TSO, + //--------------------- RISCV_SHA512SIG0--------------------- + RISCV_INSN_SHA512SIG0, + //--------------------- RISCV_FLI_S--------------------- + RISCV_INSN_FLI_S, + //--------------------- RISCV_C_SB--------------------- + RISCV_INSN_C_SB, + //--------------------- RISCV_ZBB_RTYPEW--------------------- + RISCV_INSN_RORW, + RISCV_INSN_ROLW, + //--------------------- RISCV_C_FLDSP--------------------- + RISCV_INSN_C_FLDSP, + //--------------------- RISCV_C_MV_HINT--------------------- + RISCV_INSN_C_MV_HINT, + //--------------------- RISCV_FCVTMOD_W_D--------------------- + RISCV_INSN_FCVTMOD_W_D, + //--------------------- RISCV_RFVVTYPE--------------------- + RISCV_INSN_FVV_VFWREDUSUM, + RISCV_INSN_FVV_VFWREDOSUM, + RISCV_INSN_FVV_VFREDUSUM, + RISCV_INSN_FVV_VFREDOSUM, + RISCV_INSN_FVV_VFREDMIN, + RISCV_INSN_FVV_VFREDMAX, + //--------------------- RISCV_SHA512SIG0H--------------------- + RISCV_INSN_SHA512SIG0H, + //--------------------- RISCV_AMO--------------------- + RISCV_INSN_AMOXOR, + RISCV_INSN_AMOSWAP, + RISCV_INSN_AMOOR, + RISCV_INSN_AMOMINU, + RISCV_INSN_AMOMIN, + RISCV_INSN_AMOMAXU, + RISCV_INSN_AMOMAX, + RISCV_INSN_AMOAND, + RISCV_INSN_AMOADD, + //--------------------- RISCV_LOAD_FP--------------------- + RISCV_INSN_LOAD_FP, + //--------------------- RISCV_VVMSTYPE--------------------- + RISCV_INSN_VVMS_VSBC, + RISCV_INSN_VVMS_VADC, + //--------------------- RISCV_FVVMATYPE--------------------- + RISCV_INSN_FVV_VNMSUB, + RISCV_INSN_FVV_VNMSAC, + RISCV_INSN_FVV_VNMADD, + RISCV_INSN_FVV_VNMACC, + RISCV_INSN_FVV_VMSUB, + RISCV_INSN_FVV_VMSAC, + RISCV_INSN_FVV_VMADD, + RISCV_INSN_FVV_VMACC, + //--------------------- RISCV_VEXT2TYPE--------------------- + RISCV_INSN_VEXT2_ZVF2, + RISCV_INSN_VEXT2_SVF2, + //--------------------- RISCV_EBREAK--------------------- + RISCV_INSN_EBREAK, + //--------------------- RISCV_C_LUI--------------------- + RISCV_INSN_C_LUI, + //--------------------- RISCV_F_MADD_TYPE_D--------------------- + RISCV_INSN_FNMSUB_D, + RISCV_INSN_FNMADD_D, + RISCV_INSN_FMSUB_D, + RISCV_INSN_FMADD_D, + //--------------------- RISCV_C_ZEXT_H--------------------- + RISCV_INSN_C_ZEXT_H, + //--------------------- RISCV_SHA512SIG1L--------------------- + RISCV_INSN_SHA512SIG1L, + //--------------------- RISCV_VLSEGTYPE--------------------- + RISCV_INSN_VLSEGTYPE, + //--------------------- RISCV_SHA256SIG0--------------------- + RISCV_INSN_SHA256SIG0, + //--------------------- RISCV_F_UN_TYPE_H--------------------- + RISCV_INSN_FMV_X_H, + RISCV_INSN_FMV_H_X, + RISCV_INSN_FCLASS_H, + //--------------------- RISCV_C_ADDI4SPN--------------------- + RISCV_INSN_C_ADDI4SPN, + //--------------------- RISCV_VVTYPE--------------------- + RISCV_INSN_VV_VXOR, + RISCV_INSN_VV_VSUB, + RISCV_INSN_VV_VSSUBU, + RISCV_INSN_VV_VSSUB, + RISCV_INSN_VV_VSSRL, + RISCV_INSN_VV_VSSRA, + RISCV_INSN_VV_VSRL, + RISCV_INSN_VV_VSRA, + RISCV_INSN_VV_VSMUL, + RISCV_INSN_VV_VSLL, + RISCV_INSN_VV_VSADDU, + RISCV_INSN_VV_VSADD, + RISCV_INSN_VV_VRGATHEREI16, + RISCV_INSN_VV_VRGATHER, + RISCV_INSN_VV_VOR, + RISCV_INSN_VV_VMINU, + RISCV_INSN_VV_VMIN, + RISCV_INSN_VV_VMAXU, + RISCV_INSN_VV_VMAX, + RISCV_INSN_VV_VAND, + RISCV_INSN_VV_VADD, + //--------------------- RISCV_FLEQ_H--------------------- + RISCV_INSN_FLEQ_H, + //--------------------- RISCV_VICMPTYPE--------------------- + RISCV_INSN_VICMP_VMSNE, + RISCV_INSN_VICMP_VMSLEU, + RISCV_INSN_VICMP_VMSLE, + RISCV_INSN_VICMP_VMSGTU, + RISCV_INSN_VICMP_VMSGT, + RISCV_INSN_VICMP_VMSEQ, + //--------------------- RISCV_C_FLW--------------------- + RISCV_INSN_C_FLW, + //--------------------- RISCV_C_SWSP--------------------- + RISCV_INSN_C_SWSP, + //--------------------- RISCV_FLTQ_D--------------------- + RISCV_INSN_FLTQ_D, + //--------------------- RISCV_AES64ES--------------------- + RISCV_INSN_AES64ES, + //--------------------- RISCV_C_SRAI_HINT--------------------- + RISCV_INSN_C_SRAI_HINT, + //--------------------- RISCV_DIV--------------------- + RISCV_INSN_DIV, + //--------------------- RISCV_F_UN_TYPE_D--------------------- + RISCV_INSN_FMV_X_D, + RISCV_INSN_FMV_D_X, + RISCV_INSN_FCLASS_D, + //--------------------- RISCV_C_LH--------------------- + RISCV_INSN_C_LH, + //--------------------- RISCV_C_NOP_HINT--------------------- + RISCV_INSN_C_NOP_HINT, + //--------------------- RISCV_VFIRST_M--------------------- + RISCV_INSN_VFIRST_M, + //--------------------- RISCV_MVVMATYPE--------------------- + RISCV_INSN_MVV_VNMSUB, + RISCV_INSN_MVV_VNMSAC, + RISCV_INSN_MVV_VMADD, + RISCV_INSN_MVV_VMACC, + //--------------------- RISCV_FENCEI_RESERVED--------------------- + RISCV_INSN_FENCEI_RESERVED, + //--------------------- RISCV_C_ADDI--------------------- + RISCV_INSN_C_ADDI, + //--------------------- RISCV_VLOXSEGTYPE--------------------- + RISCV_INSN_VLOXSEGTYPE, + //--------------------- RISCV_MUL--------------------- + RISCV_INSN_MUL, + //--------------------- RISCV_VMSOF_M--------------------- + RISCV_INSN_VMSOF_M, + //--------------------- RISCV_FLEQ_D--------------------- + RISCV_INSN_FLEQ_D, + //--------------------- RISCV_VSSSEGTYPE--------------------- + RISCV_INSN_VSSSEGTYPE, + //--------------------- RISCV_VXTYPE--------------------- + RISCV_INSN_VX_VXOR, + RISCV_INSN_VX_VSUB, + RISCV_INSN_VX_VSSUBU, + RISCV_INSN_VX_VSSUB, + RISCV_INSN_VX_VSSRL, + RISCV_INSN_VX_VSSRA, + RISCV_INSN_VX_VSRL, + RISCV_INSN_VX_VSRA, + RISCV_INSN_VX_VSMUL, + RISCV_INSN_VX_VSLL, + RISCV_INSN_VX_VSADDU, + RISCV_INSN_VX_VSADD, + RISCV_INSN_VX_VRSUB, + RISCV_INSN_VX_VOR, + RISCV_INSN_VX_VMINU, + RISCV_INSN_VX_VMIN, + RISCV_INSN_VX_VMAXU, + RISCV_INSN_VX_VMAX, + RISCV_INSN_VX_VAND, + RISCV_INSN_VX_VADD, + //--------------------- RISCV_BTYPE--------------------- + RISCV_INSN_BNE, + RISCV_INSN_BLTU, + RISCV_INSN_BLT, + RISCV_INSN_BGEU, + RISCV_INSN_BGE, + RISCV_INSN_BEQ, + //--------------------- RISCV_LOAD--------------------- + RISCV_INSN_LOAD, + //--------------------- RISCV_VIOTA_M--------------------- + RISCV_INSN_VIOTA_M, + //--------------------- RISCV_CLMULR--------------------- + RISCV_INSN_CLMULR, + //--------------------- RISCV_VXMSTYPE--------------------- + RISCV_INSN_VXMS_VSBC, + RISCV_INSN_VXMS_VADC, + //--------------------- RISCV_CLZ--------------------- + RISCV_INSN_CLZ, + //--------------------- RISCV_UTYPE--------------------- + RISCV_INSN_LUI, + RISCV_INSN_AUIPC, + //--------------------- RISCV_CLMULH--------------------- + RISCV_INSN_CLMULH, + //--------------------- RISCV_FLI_H--------------------- + RISCV_INSN_FLI_H, + //--------------------- RISCV_F_BIN_RM_TYPE_H--------------------- + RISCV_INSN_FSUB_H, + RISCV_INSN_FMUL_H, + RISCV_INSN_FDIV_H, + RISCV_INSN_FADD_H, + //--------------------- RISCV_VSETVLI--------------------- + RISCV_INSN_VSETVLI, + //--------------------- RISCV_C_SEXT_B--------------------- + RISCV_INSN_C_SEXT_B, + //--------------------- RISCV_VLUXSEGTYPE--------------------- + RISCV_INSN_VLUXSEGTYPE, + //--------------------- RISCV_SHA512SUM1R--------------------- + RISCV_INSN_SHA512SUM1R, + //--------------------- RISCV_VITYPE--------------------- + RISCV_INSN_VI_VXOR, + RISCV_INSN_VI_VSSRL, + RISCV_INSN_VI_VSSRA, + RISCV_INSN_VI_VSRL, + RISCV_INSN_VI_VSRA, + RISCV_INSN_VI_VSLL, + RISCV_INSN_VI_VSADDU, + RISCV_INSN_VI_VSADD, + RISCV_INSN_VI_VRSUB, + RISCV_INSN_VI_VOR, + RISCV_INSN_VI_VAND, + RISCV_INSN_VI_VADD, + //--------------------- RISCV_STORECON--------------------- + RISCV_INSN_STORECON, + //--------------------- RISCV_VMVRTYPE--------------------- + RISCV_INSN_VMVRTYPE, + //--------------------- RISCV_ZBKB_RTYPE--------------------- + RISCV_INSN_PACKH, + RISCV_INSN_PACK, + //--------------------- RISCV_VISG--------------------- + RISCV_INSN_VI_VSLIDEUP, + RISCV_INSN_VI_VSLIDEDOWN, + RISCV_INSN_VI_VRGATHER, + //--------------------- RISCV_C_ADD--------------------- + RISCV_INSN_C_ADD, + //--------------------- RISCV_FVFTYPE--------------------- + RISCV_INSN_VF_VSUB, + RISCV_INSN_VF_VSLIDE1UP, + RISCV_INSN_VF_VSLIDE1DOWN, + RISCV_INSN_VF_VSGNJX, + RISCV_INSN_VF_VSGNJN, + RISCV_INSN_VF_VSGNJ, + RISCV_INSN_VF_VRSUB, + RISCV_INSN_VF_VRDIV, + RISCV_INSN_VF_VMUL, + RISCV_INSN_VF_VMIN, + RISCV_INSN_VF_VMAX, + RISCV_INSN_VF_VDIV, + RISCV_INSN_VF_VADD, + //--------------------- RISCV_FENCE_RESERVED--------------------- + RISCV_INSN_FENCE_RESERVED, + //--------------------- RISCV_MASKTYPEI--------------------- + RISCV_INSN_MASKTYPEI, + //--------------------- RISCV_FVVTYPE--------------------- + RISCV_INSN_FVV_VSUB, + RISCV_INSN_FVV_VSGNJX, + RISCV_INSN_FVV_VSGNJN, + RISCV_INSN_FVV_VSGNJ, + RISCV_INSN_FVV_VMUL, + RISCV_INSN_FVV_VMIN, + RISCV_INSN_FVV_VMAX, + RISCV_INSN_FVV_VDIV, + RISCV_INSN_FVV_VADD, + //--------------------- RISCV_CPOPW--------------------- + RISCV_INSN_CPOPW, + //--------------------- RISCV_C_LI_HINT--------------------- + RISCV_INSN_C_LI_HINT, + //--------------------- RISCV_SHA256SUM1--------------------- + RISCV_INSN_SHA256SUM1, + //--------------------- RISCV_VSUXSEGTYPE--------------------- + RISCV_INSN_VSUXSEGTYPE, + //--------------------- RISCV_VIMCTYPE--------------------- + RISCV_INSN_VIMC_VMADC, + //--------------------- RISCV_VIMSTYPE--------------------- + RISCV_INSN_VIMS_VADC, + //--------------------- RISCV_MASKTYPEV--------------------- + RISCV_INSN_MASKTYPEV, + //--------------------- RISCV_FVFMTYPE--------------------- + RISCV_INSN_VFM_VMFNE, + RISCV_INSN_VFM_VMFLT, + RISCV_INSN_VFM_VMFLE, + RISCV_INSN_VFM_VMFGT, + RISCV_INSN_VFM_VMFGE, + RISCV_INSN_VFM_VMFEQ, + //--------------------- RISCV_ADDIW--------------------- + RISCV_INSN_ADDIW, + //--------------------- RISCV_MRET--------------------- + RISCV_INSN_MRET, + //--------------------- RISCV_VLSEGFFTYPE--------------------- + RISCV_INSN_VLSEGFFTYPE, + //--------------------- RISCV_C_ANDI--------------------- + RISCV_INSN_C_ANDI, + //--------------------- RISCV_WVTYPE--------------------- + RISCV_INSN_WV_VSUBU, + RISCV_INSN_WV_VSUB, + RISCV_INSN_WV_VADDU, + RISCV_INSN_WV_VADD, + //--------------------- RISCV_C_SDSP--------------------- + RISCV_INSN_C_SDSP, + //--------------------- RISCV_C_SUBW--------------------- + RISCV_INSN_C_SUBW, + //--------------------- RISCV_VEXT4TYPE--------------------- + RISCV_INSN_VEXT4_ZVF4, + RISCV_INSN_VEXT4_SVF4, + //--------------------- RISCV_VSETVL--------------------- + RISCV_INSN_VSETVL, + //--------------------- RISCV_C_SH--------------------- + RISCV_INSN_C_SH, + //--------------------- RISCV_MVVCOMPRESS--------------------- + RISCV_INSN_MVVCOMPRESS, + //--------------------- RISCV_FWVVTYPE--------------------- + RISCV_INSN_FWVV_VSUB, + RISCV_INSN_FWVV_VMUL, + RISCV_INSN_FWVV_VADD, + //--------------------- RISCV_VMTYPE--------------------- + RISCV_INSN_VSM, + RISCV_INSN_VLM, + //--------------------- RISCV_FROUND_H--------------------- + RISCV_INSN_FROUND_H, + //--------------------- RISCV_C_JAL--------------------- + RISCV_INSN_C_JAL, + //--------------------- RISCV_SFENCE_VMA--------------------- + RISCV_INSN_SFENCE_VMA, + //--------------------- RISCV_NVSTYPE--------------------- + RISCV_INSN_NVS_VNSRL, + RISCV_INSN_NVS_VNSRA, + //--------------------- RISCV_FROUND_S--------------------- + RISCV_INSN_FROUND_S, + //--------------------- RISCV_NISTYPE--------------------- + RISCV_INSN_NIS_VNSRL, + RISCV_INSN_NIS_VNSRA, + //--------------------- RISCV_C_SLLI--------------------- + RISCV_INSN_C_SLLI, + //--------------------- RISCV_VXMTYPE--------------------- + RISCV_INSN_VXM_VMSBC, + RISCV_INSN_VXM_VMADC, + //--------------------- RISCV_FENCEI--------------------- + RISCV_INSN_FENCEI, + //--------------------- RISCV_VFMVSF--------------------- + RISCV_INSN_VFMVSF, + //--------------------- RISCV_VEXT8TYPE--------------------- + RISCV_INSN_VEXT8_ZVF8, + RISCV_INSN_VEXT8_SVF8, + //--------------------- RISCV_C_OR--------------------- + RISCV_INSN_C_OR, + //--------------------- RISCV_FWVFMATYPE--------------------- + RISCV_INSN_FWVF_VNMSAC, + RISCV_INSN_FWVF_VNMACC, + RISCV_INSN_FWVF_VMSAC, + RISCV_INSN_FWVF_VMACC, + //--------------------- RISCV_SHIFTIOP--------------------- + RISCV_INSN_SRLI, + RISCV_INSN_SRAI, + RISCV_INSN_SLLI, + //--------------------- RISCV_DIVW--------------------- + RISCV_INSN_DIVW, + //--------------------- RISCV_C_ZEXT_B--------------------- + RISCV_INSN_C_ZEXT_B, + //--------------------- RISCV_C_MV--------------------- + RISCV_INSN_C_MV, + //--------------------- RISCV_VIMTYPE--------------------- + RISCV_INSN_VIM_VMADC, + //--------------------- RISCV_LOADRES--------------------- + RISCV_INSN_LOADRES, + //--------------------- RISCV_C_J--------------------- + RISCV_INSN_C_J, + //--------------------- RISCV_AES32ESI--------------------- + RISCV_INSN_AES32ESI, + //--------------------- RISCV_C_BEQZ--------------------- + RISCV_INSN_C_BEQZ, + //--------------------- RISCV_SHA512SUM0--------------------- + RISCV_INSN_SHA512SUM0, + //--------------------- RISCV_SHA512SUM0R--------------------- + RISCV_INSN_SHA512SUM0R, + //--------------------- RISCV_REMW--------------------- + RISCV_INSN_REMW, + //--------------------- RISCV_VFMV--------------------- + RISCV_INSN_VFMV, + //--------------------- RISCV_C_SEXT_H--------------------- + RISCV_INSN_C_SEXT_H, + //--------------------- RISCV_WMVXTYPE--------------------- + RISCV_INSN_WMVX_VWMACCUS, + RISCV_INSN_WMVX_VWMACCU, + RISCV_INSN_WMVX_VWMACCSU, + RISCV_INSN_WMVX_VWMACC, + //--------------------- RISCV_C_FSW--------------------- + RISCV_INSN_C_FSW, + //--------------------- RISCV_C_SW--------------------- + RISCV_INSN_C_SW, + //--------------------- RISCV_ZBS_RTYPE--------------------- + RISCV_INSN_BSET, + RISCV_INSN_BINV, + RISCV_INSN_BEXT, + RISCV_INSN_BCLR, + //--------------------- RISCV_C_SUB--------------------- + RISCV_INSN_C_SUB, + //--------------------- RISCV_VFUNARY0--------------------- + RISCV_INSN_FV_CVT_X_F, + RISCV_INSN_FV_CVT_XU_F, + RISCV_INSN_FV_CVT_RTZ_X_F, + RISCV_INSN_FV_CVT_RTZ_XU_F, + RISCV_INSN_FV_CVT_F_XU, + RISCV_INSN_FV_CVT_F_X, + //--------------------- RISCV_FROUNDNX_S--------------------- + RISCV_INSN_FROUNDNX_S, + //--------------------- RISCV_ZICBOZ--------------------- + RISCV_INSN_ZICBOZ, + //--------------------- RISCV_SFENCE_W_INVAL--------------------- + RISCV_INSN_SFENCE_W_INVAL, + //--------------------- RISCV_C_JR--------------------- + RISCV_INSN_C_JR, + //--------------------- RISCV_C_NOT--------------------- + RISCV_INSN_C_NOT, + //--------------------- RISCV_ZBB_EXTOP--------------------- + RISCV_INSN_ZEXTH, + RISCV_INSN_SEXTH, + RISCV_INSN_SEXTB, + //--------------------- RISCV_MVVTYPE--------------------- + RISCV_INSN_MVV_VREMU, + RISCV_INSN_MVV_VREM, + RISCV_INSN_MVV_VMULHU, + RISCV_INSN_MVV_VMULHSU, + RISCV_INSN_MVV_VMULH, + RISCV_INSN_MVV_VMUL, + RISCV_INSN_MVV_VDIVU, + RISCV_INSN_MVV_VDIV, + RISCV_INSN_MVV_VASUBU, + RISCV_INSN_MVV_VASUB, + RISCV_INSN_MVV_VAADDU, + RISCV_INSN_MVV_VAADD, + //--------------------- RISCV_FVFMATYPE--------------------- + RISCV_INSN_VF_VNMSUB, + RISCV_INSN_VF_VNMSAC, + RISCV_INSN_VF_VNMADD, + RISCV_INSN_VF_VNMACC, + RISCV_INSN_VF_VMSUB, + RISCV_INSN_VF_VMSAC, + RISCV_INSN_VF_VMADD, + RISCV_INSN_VF_VMACC, + //--------------------- RISCV_FMAXM_H--------------------- + RISCV_INSN_FMAXM_H, + //--------------------- RISCV_SHA256SUM0--------------------- + RISCV_INSN_SHA256SUM0, + //--------------------- RISCV_ZBS_IOP--------------------- + RISCV_INSN_BSETI, + RISCV_INSN_BINVI, + RISCV_INSN_BEXTI, + RISCV_INSN_BCLRI, + //--------------------- RISCV_C_XOR--------------------- + RISCV_INSN_C_XOR, + //--------------------- RISCV_FMINM_H--------------------- + RISCV_INSN_FMINM_H, + //--------------------- RISCV_C_LUI_HINT--------------------- + RISCV_INSN_C_LUI_HINT, + //--------------------- RISCV_VVMCTYPE--------------------- + RISCV_INSN_VVMC_VMSBC, + RISCV_INSN_VVMC_VMADC, + //--------------------- RISCV_F_BIN_RM_TYPE_S--------------------- + RISCV_INSN_FSUB_S, + RISCV_INSN_FMUL_S, + RISCV_INSN_FDIV_S, + RISCV_INSN_FADD_S, + //--------------------- RISCV_SINVAL_VMA--------------------- + RISCV_INSN_SINVAL_VMA, + //--------------------- RISCV_MOVETYPEX--------------------- + RISCV_INSN_MOVETYPEX, + //--------------------- RISCV_C_BNEZ--------------------- + RISCV_INSN_C_BNEZ, + //--------------------- RISCV_FWVVMATYPE--------------------- + RISCV_INSN_FWVV_VNMSAC, + RISCV_INSN_FWVV_VNMACC, + RISCV_INSN_FWVV_VMSAC, + RISCV_INSN_FWVV_VMACC, + //--------------------- RISCV_AES64KS1I--------------------- + RISCV_INSN_AES64KS1I, + //--------------------- RISCV_RMVVTYPE--------------------- + RISCV_INSN_MVV_VREDXOR, + RISCV_INSN_MVV_VREDSUM, + RISCV_INSN_MVV_VREDOR, + RISCV_INSN_MVV_VREDMINU, + RISCV_INSN_MVV_VREDMIN, + RISCV_INSN_MVV_VREDMAXU, + RISCV_INSN_MVV_VREDMAX, + RISCV_INSN_MVV_VREDAND, + //--------------------- RISCV_CLZW--------------------- + RISCV_INSN_CLZW, + //--------------------- RISCV_REM--------------------- + RISCV_INSN_REM, + //--------------------- RISCV_C_EBREAK--------------------- + RISCV_INSN_C_EBREAK, + //--------------------- RISCV_AES64ESM--------------------- + RISCV_INSN_AES64ESM, + //--------------------- RISCV_VFNUNARY0--------------------- + RISCV_INSN_FNV_CVT_X_F, + RISCV_INSN_FNV_CVT_XU_F, + RISCV_INSN_FNV_CVT_RTZ_X_F, + RISCV_INSN_FNV_CVT_RTZ_XU_F, + RISCV_INSN_FNV_CVT_ROD_F_F, + RISCV_INSN_FNV_CVT_F_XU, + RISCV_INSN_FNV_CVT_F_X, + RISCV_INSN_FNV_CVT_F_F, + //--------------------- RISCV_VFWUNARY0--------------------- + RISCV_INSN_FWV_CVT_X_F, + RISCV_INSN_FWV_CVT_XU_F, + RISCV_INSN_FWV_CVT_RTZ_X_F, + RISCV_INSN_FWV_CVT_RTZ_XU_F, + RISCV_INSN_FWV_CVT_F_XU, + RISCV_INSN_FWV_CVT_F_X, + RISCV_INSN_FWV_CVT_F_F, + //--------------------- RISCV_MOVETYPEV--------------------- + RISCV_INSN_MOVETYPEV, + //--------------------- RISCV_VFUNARY1--------------------- + RISCV_INSN_FVV_VSQRT, + RISCV_INSN_FVV_VRSQRT7, + RISCV_INSN_FVV_VREC7, + RISCV_INSN_FVV_VCLASS, + //--------------------- RISCV_FWVFTYPE--------------------- + RISCV_INSN_FWVF_VSUB, + RISCV_INSN_FWVF_VMUL, + RISCV_INSN_FWVF_VADD, + //--------------------- RISCV_ZBA_RTYPE--------------------- + RISCV_INSN_SH3ADD, + RISCV_INSN_SH2ADD, + RISCV_INSN_SH1ADD, + //--------------------- RISCV_C_SRLI--------------------- + RISCV_INSN_C_SRLI, + //--------------------- RISCV_VSRETYPE--------------------- + RISCV_INSN_VSRETYPE, + //--------------------- RISCV_C_SLLI_HINT--------------------- + RISCV_INSN_C_SLLI_HINT, + //--------------------- RISCV_WVVTYPE--------------------- + RISCV_INSN_WVV_VWMULU, + RISCV_INSN_WVV_VWMULSU, + RISCV_INSN_WVV_VWMUL, + RISCV_INSN_WVV_VSUBU, + RISCV_INSN_WVV_VSUB, + RISCV_INSN_WVV_VADDU, + RISCV_INSN_WVV_VADD, + //--------------------- RISCV_AES64DSM--------------------- + RISCV_INSN_AES64DSM, + //--------------------- RISCV_URET--------------------- + RISCV_INSN_URET, + //--------------------- RISCV_C_LI--------------------- + RISCV_INSN_C_LI, + //--------------------- RISCV_CSR--------------------- + RISCV_INSN_CSRRW, + RISCV_INSN_CSRRS, + RISCV_INSN_CSRRC, + //--------------------- RISCV_C_SRAI--------------------- + RISCV_INSN_C_SRAI, + //--------------------- RISCV_FMVP_D_X--------------------- + RISCV_INSN_FMVP_D_X, + //--------------------- RISCV_C_LBU--------------------- + RISCV_INSN_C_LBU, + //--------------------- RISCV_F_UN_RM_TYPE_S--------------------- + RISCV_INSN_FSQRT_S, + RISCV_INSN_FCVT_W_S, + RISCV_INSN_FCVT_WU_S, + RISCV_INSN_FCVT_S_WU, + RISCV_INSN_FCVT_S_W, + RISCV_INSN_FCVT_S_LU, + RISCV_INSN_FCVT_S_L, + RISCV_INSN_FCVT_L_S, + RISCV_INSN_FCVT_LU_S, + //--------------------- RISCV_RTYPEW--------------------- + RISCV_INSN_SUBW, + RISCV_INSN_SRLW, + RISCV_INSN_SRAW, + RISCV_INSN_SLLW, + RISCV_INSN_ADDW, + //--------------------- RISCV_WMVVTYPE--------------------- + RISCV_INSN_WMVV_VWMACCU, + RISCV_INSN_WMVV_VWMACCSU, + RISCV_INSN_WMVV_VWMACC, + //--------------------- RISCV_MULW--------------------- + RISCV_INSN_MULW, + //--------------------- RISCV_VVCMPTYPE--------------------- + RISCV_INSN_VVCMP_VMSNE, + RISCV_INSN_VVCMP_VMSLTU, + RISCV_INSN_VVCMP_VMSLT, + RISCV_INSN_VVCMP_VMSLEU, + RISCV_INSN_VVCMP_VMSLE, + RISCV_INSN_VVCMP_VMSEQ, + //--------------------- RISCV_ILLEGAL--------------------- + RISCV_INSN_ILLEGAL, + //--------------------- RISCV_BREV8--------------------- + RISCV_INSN_BREV8, + //--------------------- RISCV_AES32DSMI--------------------- + RISCV_INSN_AES32DSMI, + //--------------------- RISCV_C_FSD--------------------- + RISCV_INSN_C_FSD, + //--------------------- RISCV_C_ADDW--------------------- + RISCV_INSN_C_ADDW, + //--------------------- RISCV_VCPOP_M--------------------- + RISCV_INSN_VCPOP_M, + //--------------------- RISCV_SHA256SIG1--------------------- + RISCV_INSN_SHA256SIG1, + //--------------------- RISCV_MVXTYPE--------------------- + RISCV_INSN_MVX_VSLIDE1UP, + RISCV_INSN_MVX_VSLIDE1DOWN, + RISCV_INSN_MVX_VREMU, + RISCV_INSN_MVX_VREM, + RISCV_INSN_MVX_VMULHU, + RISCV_INSN_MVX_VMULHSU, + RISCV_INSN_MVX_VMULH, + RISCV_INSN_MVX_VMUL, + RISCV_INSN_MVX_VDIVU, + RISCV_INSN_MVX_VDIV, + RISCV_INSN_MVX_VASUBU, + RISCV_INSN_MVX_VASUB, + RISCV_INSN_MVX_VAADDU, + RISCV_INSN_MVX_VAADD, +}; + +#endif diff --git a/riscv_disasm/riscv_insn_mapping.gen.inc b/riscv_disasm/riscv_insn_mapping.gen.inc new file mode 100644 index 0000000..aeb40be --- /dev/null +++ b/riscv_disasm/riscv_insn_mapping.gen.inc @@ -0,0 +1,599 @@ +#ifndef __Riscv_insn_mapping_gen_inc__ +#define __Riscv_insn_mapping_gen_inc__ +#include + +#include + +#include "riscv_insn.gen.inc" +#include + +static const uint16_t to_insn[295][21] = { + [RISCV_REV8] = {RISCV_REV8}, + [RISCV_WXTYPE] = {RISCV_WX_VSUBU, RISCV_WX_VSUB, RISCV_WX_VADDU, + RISCV_WX_VADD}, + [RISCV_C_SRLI_HINT] = {RISCV_C_SRLI_HINT}, + [RISCV_AES64DS] = {RISCV_AES64DS}, + [RISCV_VMSBF_M] = {RISCV_VMSBF_M}, + [RISCV_RTYPE] = {RISCV_XOR, RISCV_SUB, RISCV_SRL, RISCV_SRA, RISCV_SLTU, + RISCV_SLT, RISCV_SLL, RISCV_OR, RISCV_AND, RISCV_ADD}, + [RISCV_VFMERGE] = {RISCV_VFMERGE}, + [RISCV_RIVVTYPE] = {RISCV_IVV_VWREDSUMU, RISCV_IVV_VWREDSUM}, + [RISCV_C_ZEXT_W] = {RISCV_C_ZEXT_W}, + [RISCV_SFENCE_INVAL_IR] = {RISCV_SFENCE_INVAL_IR}, + [RISCV_XPERM4] = {RISCV_XPERM4}, + [RISCV_C_AND] = {RISCV_C_AND}, + [RISCV_AES32DSI] = {RISCV_AES32DSI}, + [RISCV_RORI] = {RISCV_RORI}, + [RISCV_JALR] = {RISCV_JALR}, + [RISCV_VMSIF_M] = {RISCV_VMSIF_M}, + [RISCV_VLSSEGTYPE] = {RISCV_VLSSEGTYPE}, + [RISCV_SHA512SIG1H] = {RISCV_SHA512SIG1H}, + [RISCV_FLTQ_S] = {RISCV_FLTQ_S}, + [RISCV_VXSG] = {RISCV_VX_VSLIDEUP, RISCV_VX_VSLIDEDOWN, RISCV_VX_VRGATHER}, + [RISCV_VXCMPTYPE] = {RISCV_VXCMP_VMSNE, RISCV_VXCMP_VMSLTU, + RISCV_VXCMP_VMSLT, RISCV_VXCMP_VMSLEU, + RISCV_VXCMP_VMSLE, RISCV_VXCMP_VMSGTU, + RISCV_VXCMP_VMSGT, RISCV_VXCMP_VMSEQ}, + [RISCV_C_LHU] = {RISCV_C_LHU}, + [RISCV_JAL] = {RISCV_JAL}, + [RISCV_ECALL] = {RISCV_ECALL}, + [RISCV_C_FSWSP] = {RISCV_C_FSWSP}, + [RISCV_VMVXS] = {RISCV_VMVXS}, + [RISCV_C_FLD] = {RISCV_C_FLD}, + [RISCV_SHIFTIWOP] = {RISCV_SRLIW, RISCV_SRAIW, RISCV_SLLIW}, + [RISCV_UNZIP] = {RISCV_UNZIP}, + [RISCV_ZICBOM] = {RISCV_CBO_INVAL, RISCV_CBO_FLUSH, RISCV_CBO_CLEAN}, + [RISCV_SHA512SIG1] = {RISCV_SHA512SIG1}, + [RISCV_NITYPE] = {RISCV_NI_VNCLIPU, RISCV_NI_VNCLIP}, + [RISCV_WFI] = {RISCV_WFI}, + [RISCV_VVMTYPE] = {RISCV_VVM_VMSBC, RISCV_VVM_VMADC}, + [RISCV_MVXMATYPE] = {RISCV_MVX_VNMSUB, RISCV_MVX_VNMSAC, RISCV_MVX_VMADD, + RISCV_MVX_VMACC}, + [RISCV_FLI_D] = {RISCV_FLI_D}, + [RISCV_C_ADDI_HINT] = {RISCV_C_ADDI_HINT}, + [RISCV_MASKTYPEX] = {RISCV_MASKTYPEX}, + [RISCV_FROUNDNX_D] = {RISCV_FROUNDNX_D}, + [RISCV_FROUND_D] = {RISCV_FROUND_D}, + [RISCV_VSETIVLI] = {RISCV_VSETIVLI}, + [RISCV_FMAXM_D] = {RISCV_FMAXM_D}, + [RISCV_C_SD] = {RISCV_C_SD}, + [RISCV_F_BIN_TYPE_H] = {RISCV_FSGNJ_H, RISCV_FSGNJX_H, RISCV_FSGNJN_H, + RISCV_FMIN_H, RISCV_FMAX_H, RISCV_FLT_H, + RISCV_FLE_H, RISCV_FEQ_H}, + [RISCV_ZBKB_PACKW] = {RISCV_ZBKB_PACKW}, + [RISCV_FVVMTYPE] = {RISCV_FVVM_VMFNE, RISCV_FVVM_VMFLT, RISCV_FVVM_VMFLE, + RISCV_FVVM_VMFEQ}, + [RISCV_VMVSX] = {RISCV_VMVSX}, + [RISCV_F_UN_RM_TYPE_D] = {RISCV_FSQRT_D, RISCV_FCVT_W_D, RISCV_FCVT_WU_D, + RISCV_FCVT_S_D, RISCV_FCVT_L_D, RISCV_FCVT_LU_D, + RISCV_FCVT_D_WU, RISCV_FCVT_D_W, RISCV_FCVT_D_S, + RISCV_FCVT_D_LU, RISCV_FCVT_D_L}, + [RISCV_ORCB] = {RISCV_ORCB}, + [RISCV_C_MUL] = {RISCV_C_MUL}, + [RISCV_SM3P1] = {RISCV_SM3P1}, + [RISCV_CLMUL] = {RISCV_CLMUL}, + [RISCV_FLEQ_S] = {RISCV_FLEQ_S}, + [RISCV_WVXTYPE] = {RISCV_WVX_VWMULU, RISCV_WVX_VWMULSU, RISCV_WVX_VWMUL, + RISCV_WVX_VSUBU, RISCV_WVX_VSUB, RISCV_WVX_VADDU, + RISCV_WVX_VADD}, + [RISCV_FMAXM_S] = {RISCV_FMAXM_S}, + [RISCV_C_ILLEGAL] = {RISCV_C_ILLEGAL}, + [RISCV_NXSTYPE] = {RISCV_NXS_VNSRL, RISCV_NXS_VNSRA}, + [RISCV_VSOXSEGTYPE] = {RISCV_VSOXSEGTYPE}, + [RISCV_C_NOP] = {RISCV_C_NOP}, + [RISCV_VXMCTYPE] = {RISCV_VXMC_VMSBC, RISCV_VXMC_VMADC}, + [RISCV_MMTYPE] = {RISCV_MM_VMXOR, RISCV_MM_VMXNOR, RISCV_MM_VMORN, + RISCV_MM_VMOR, RISCV_MM_VMNOR, RISCV_MM_VMNAND, + RISCV_MM_VMANDN, RISCV_MM_VMAND}, + [RISCV_F_UN_TYPE_S] = {RISCV_FMV_X_W, RISCV_FMV_W_X, RISCV_FCLASS_S}, + [RISCV_NVTYPE] = {RISCV_NV_VNCLIPU, RISCV_NV_VNCLIP}, + [RISCV_AES64KS2] = {RISCV_AES64KS2}, + [RISCV_AES32ESMI] = {RISCV_AES32ESMI}, + [RISCV_F_MADD_TYPE_H] = {RISCV_FNMSUB_H, RISCV_FNMADD_H, RISCV_FMSUB_H, + RISCV_FMADD_H}, + [RISCV_FROUNDNX_H] = {RISCV_FROUNDNX_H}, + [RISCV_MOVETYPEI] = {RISCV_MOVETYPEI}, + [RISCV_FLTQ_H] = {RISCV_FLTQ_H}, + [RISCV_C_LW] = {RISCV_C_LW}, + [RISCV_C_LWSP] = {RISCV_C_LWSP}, + [RISCV_C_ADDI16SP] = {RISCV_C_ADDI16SP}, + [RISCV_SHA512SIG0L] = {RISCV_SHA512SIG0L}, + [RISCV_SM3P0] = {RISCV_SM3P0}, + [RISCV_SM4ED] = {RISCV_SM4ED}, + [RISCV_FMINM_D] = {RISCV_FMINM_D}, + [RISCV_AES64IM] = {RISCV_AES64IM}, + [RISCV_VLRETYPE] = {RISCV_VLRETYPE}, + [RISCV_VFMVFS] = {RISCV_VFMVFS}, + [RISCV_CTZ] = {RISCV_CTZ}, + [RISCV_FMVH_X_D] = {RISCV_FMVH_X_D}, + [RISCV_SLLIUW] = {RISCV_SLLIUW}, + [RISCV_FMINM_S] = {RISCV_FMINM_S}, + [RISCV_ZBA_RTYPEUW] = {RISCV_SH3ADDUW, RISCV_SH2ADDUW, RISCV_SH1ADDUW, + RISCV_ADDUW}, + [RISCV_F_BIN_RM_TYPE_D] = {RISCV_FSUB_D, RISCV_FMUL_D, RISCV_FDIV_D, + RISCV_FADD_D}, + [RISCV_C_ADD_HINT] = {RISCV_C_ADD_HINT}, + [RISCV_F_MADD_TYPE_S] = {RISCV_FNMSUB_S, RISCV_FNMADD_S, RISCV_FMSUB_S, + RISCV_FMADD_S}, + [RISCV_ZIP] = {RISCV_ZIP}, + [RISCV_SHA512SUM1] = {RISCV_SHA512SUM1}, + [RISCV_C_LDSP] = {RISCV_C_LDSP}, + [RISCV_F_UN_RM_TYPE_H] = {RISCV_FSQRT_H, RISCV_FCVT_W_H, RISCV_FCVT_WU_H, + RISCV_FCVT_S_H, RISCV_FCVT_L_H, RISCV_FCVT_LU_H, + RISCV_FCVT_H_WU, RISCV_FCVT_H_W, RISCV_FCVT_H_S, + RISCV_FCVT_H_LU, RISCV_FCVT_H_L, RISCV_FCVT_H_D, + RISCV_FCVT_D_H}, + [RISCV_CPOP] = {RISCV_CPOP}, + [RISCV_FWFTYPE] = {RISCV_FWF_VSUB, RISCV_FWF_VADD}, + [RISCV_FWVTYPE] = {RISCV_FWV_VSUB, RISCV_FWV_VADD}, + [RISCV_ZBB_RTYPE] = {RISCV_XNOR, RISCV_ROR, RISCV_ROL, RISCV_ORN, + RISCV_MINU, RISCV_MIN, RISCV_MAXU, RISCV_MAX, + RISCV_ANDN}, + [RISCV_SM4KS] = {RISCV_SM4KS}, + [RISCV_RORIW] = {RISCV_RORIW}, + [RISCV_NXTYPE] = {RISCV_NX_VNCLIPU, RISCV_NX_VNCLIP}, + [RISCV_C_ADDIW] = {RISCV_C_ADDIW}, + [RISCV_C_LD] = {RISCV_C_LD}, + [RISCV_CTZW] = {RISCV_CTZW}, + [RISCV_XPERM8] = {RISCV_XPERM8}, + [RISCV_ITYPE] = {RISCV_XORI, RISCV_SLTIU, RISCV_SLTI, RISCV_ORI, RISCV_ANDI, + RISCV_ADDI}, + [RISCV_VID_V] = {RISCV_VID_V}, + [RISCV_FENCE] = {RISCV_FENCE}, + [RISCV_C_FLWSP] = {RISCV_C_FLWSP}, + [RISCV_STORE] = {RISCV_STORE}, + [RISCV_F_BIN_TYPE_S] = {RISCV_FSGNJ_S, RISCV_FSGNJX_S, RISCV_FSGNJN_S, + RISCV_FMIN_S, RISCV_FMAX_S, RISCV_FLT_S, + RISCV_FLE_S, RISCV_FEQ_S}, + [RISCV_VSSEGTYPE] = {RISCV_VSSEGTYPE}, + [RISCV_F_BIN_TYPE_D] = {RISCV_FSGNJ_D, RISCV_FSGNJX_D, RISCV_FSGNJN_D, + RISCV_FMIN_D, RISCV_FMAX_D, RISCV_FLT_D, + RISCV_FLE_D, RISCV_FEQ_D}, + [RISCV_ZICOND_RTYPE] = {RISCV_CZERO_NEZ, RISCV_CZERO_EQZ}, + [RISCV_C_FSDSP] = {RISCV_C_FSDSP}, + [RISCV_SRET] = {RISCV_SRET}, + [RISCV_STORE_FP] = {RISCV_STORE_FP}, + [RISCV_C_JALR] = {RISCV_C_JALR}, + [RISCV_FENCE_TSO] = {RISCV_FENCE_TSO}, + [RISCV_SHA512SIG0] = {RISCV_SHA512SIG0}, + [RISCV_FLI_S] = {RISCV_FLI_S}, + [RISCV_C_SB] = {RISCV_C_SB}, + [RISCV_ZBB_RTYPEW] = {RISCV_RORW, RISCV_ROLW}, + [RISCV_C_FLDSP] = {RISCV_C_FLDSP}, + [RISCV_C_MV_HINT] = {RISCV_C_MV_HINT}, + [RISCV_FCVTMOD_W_D] = {RISCV_FCVTMOD_W_D}, + [RISCV_RFVVTYPE] = {RISCV_FVV_VFWREDUSUM, RISCV_FVV_VFWREDOSUM, + RISCV_FVV_VFREDUSUM, RISCV_FVV_VFREDOSUM, + RISCV_FVV_VFREDMIN, RISCV_FVV_VFREDMAX}, + [RISCV_SHA512SIG0H] = {RISCV_SHA512SIG0H}, + [RISCV_AMO] = {RISCV_AMOXOR, RISCV_AMOSWAP, RISCV_AMOOR, RISCV_AMOMINU, + RISCV_AMOMIN, RISCV_AMOMAXU, RISCV_AMOMAX, RISCV_AMOAND, + RISCV_AMOADD}, + [RISCV_LOAD_FP] = {RISCV_LOAD_FP}, + [RISCV_VVMSTYPE] = {RISCV_VVMS_VSBC, RISCV_VVMS_VADC}, + [RISCV_FVVMATYPE] = {RISCV_FVV_VNMSUB, RISCV_FVV_VNMSAC, RISCV_FVV_VNMADD, + RISCV_FVV_VNMACC, RISCV_FVV_VMSUB, RISCV_FVV_VMSAC, + RISCV_FVV_VMADD, RISCV_FVV_VMACC}, + [RISCV_VEXT2TYPE] = {RISCV_VEXT2_ZVF2, RISCV_VEXT2_SVF2}, + [RISCV_EBREAK] = {RISCV_EBREAK}, + [RISCV_C_LUI] = {RISCV_C_LUI}, + [RISCV_F_MADD_TYPE_D] = {RISCV_FNMSUB_D, RISCV_FNMADD_D, RISCV_FMSUB_D, + RISCV_FMADD_D}, + [RISCV_C_ZEXT_H] = {RISCV_C_ZEXT_H}, + [RISCV_SHA512SIG1L] = {RISCV_SHA512SIG1L}, + [RISCV_VLSEGTYPE] = {RISCV_VLSEGTYPE}, + [RISCV_SHA256SIG0] = {RISCV_SHA256SIG0}, + [RISCV_F_UN_TYPE_H] = {RISCV_FMV_X_H, RISCV_FMV_H_X, RISCV_FCLASS_H}, + [RISCV_C_ADDI4SPN] = {RISCV_C_ADDI4SPN}, + [RISCV_VVTYPE] = {RISCV_VV_VXOR, RISCV_VV_VSUB, RISCV_VV_VSSUBU, + RISCV_VV_VSSUB, RISCV_VV_VSSRL, RISCV_VV_VSSRA, + RISCV_VV_VSRL, RISCV_VV_VSRA, RISCV_VV_VSMUL, + RISCV_VV_VSLL, RISCV_VV_VSADDU, RISCV_VV_VSADD, + RISCV_VV_VRGATHEREI16, RISCV_VV_VRGATHER, RISCV_VV_VOR, + RISCV_VV_VMINU, RISCV_VV_VMIN, RISCV_VV_VMAXU, + RISCV_VV_VMAX, RISCV_VV_VAND, RISCV_VV_VADD}, + [RISCV_FLEQ_H] = {RISCV_FLEQ_H}, + [RISCV_VICMPTYPE] = {RISCV_VICMP_VMSNE, RISCV_VICMP_VMSLEU, + RISCV_VICMP_VMSLE, RISCV_VICMP_VMSGTU, + RISCV_VICMP_VMSGT, RISCV_VICMP_VMSEQ}, + [RISCV_C_FLW] = {RISCV_C_FLW}, + [RISCV_C_SWSP] = {RISCV_C_SWSP}, + [RISCV_FLTQ_D] = {RISCV_FLTQ_D}, + [RISCV_AES64ES] = {RISCV_AES64ES}, + [RISCV_C_SRAI_HINT] = {RISCV_C_SRAI_HINT}, + [RISCV_DIV] = {RISCV_DIV}, + [RISCV_F_UN_TYPE_D] = {RISCV_FMV_X_D, RISCV_FMV_D_X, RISCV_FCLASS_D}, + [RISCV_C_LH] = {RISCV_C_LH}, + [RISCV_C_NOP_HINT] = {RISCV_C_NOP_HINT}, + [RISCV_VFIRST_M] = {RISCV_VFIRST_M}, + [RISCV_MVVMATYPE] = {RISCV_MVV_VNMSUB, RISCV_MVV_VNMSAC, RISCV_MVV_VMADD, + RISCV_MVV_VMACC}, + [RISCV_FENCEI_RESERVED] = {RISCV_FENCEI_RESERVED}, + [RISCV_C_ADDI] = {RISCV_C_ADDI}, + [RISCV_VLOXSEGTYPE] = {RISCV_VLOXSEGTYPE}, + [RISCV_MUL] = {RISCV_MUL}, + [RISCV_VMSOF_M] = {RISCV_VMSOF_M}, + [RISCV_FLEQ_D] = {RISCV_FLEQ_D}, + [RISCV_VSSSEGTYPE] = {RISCV_VSSSEGTYPE}, + [RISCV_VXTYPE] = {RISCV_VX_VXOR, RISCV_VX_VSUB, RISCV_VX_VSSUBU, + RISCV_VX_VSSUB, RISCV_VX_VSSRL, RISCV_VX_VSSRA, + RISCV_VX_VSRL, RISCV_VX_VSRA, RISCV_VX_VSMUL, + RISCV_VX_VSLL, RISCV_VX_VSADDU, RISCV_VX_VSADD, + RISCV_VX_VRSUB, RISCV_VX_VOR, RISCV_VX_VMINU, + RISCV_VX_VMIN, RISCV_VX_VMAXU, RISCV_VX_VMAX, + RISCV_VX_VAND, RISCV_VX_VADD}, + [RISCV_BTYPE] = {RISCV_BNE, RISCV_BLTU, RISCV_BLT, RISCV_BGEU, RISCV_BGE, + RISCV_BEQ}, + [RISCV_LOAD] = {RISCV_LOAD}, + [RISCV_VIOTA_M] = {RISCV_VIOTA_M}, + [RISCV_CLMULR] = {RISCV_CLMULR}, + [RISCV_VXMSTYPE] = {RISCV_VXMS_VSBC, RISCV_VXMS_VADC}, + [RISCV_CLZ] = {RISCV_CLZ}, + [RISCV_UTYPE] = {RISCV_LUI, RISCV_AUIPC}, + [RISCV_CLMULH] = {RISCV_CLMULH}, + [RISCV_FLI_H] = {RISCV_FLI_H}, + [RISCV_F_BIN_RM_TYPE_H] = {RISCV_FSUB_H, RISCV_FMUL_H, RISCV_FDIV_H, + RISCV_FADD_H}, + [RISCV_VSETVLI] = {RISCV_VSETVLI}, + [RISCV_C_SEXT_B] = {RISCV_C_SEXT_B}, + [RISCV_VLUXSEGTYPE] = {RISCV_VLUXSEGTYPE}, + [RISCV_SHA512SUM1R] = {RISCV_SHA512SUM1R}, + [RISCV_VITYPE] = {RISCV_VI_VXOR, RISCV_VI_VSSRL, RISCV_VI_VSSRA, + RISCV_VI_VSRL, RISCV_VI_VSRA, RISCV_VI_VSLL, + RISCV_VI_VSADDU, RISCV_VI_VSADD, RISCV_VI_VRSUB, + RISCV_VI_VOR, RISCV_VI_VAND, RISCV_VI_VADD}, + [RISCV_STORECON] = {RISCV_STORECON}, + [RISCV_VMVRTYPE] = {RISCV_VMVRTYPE}, + [RISCV_ZBKB_RTYPE] = {RISCV_PACKH, RISCV_PACK}, + [RISCV_VISG] = {RISCV_VI_VSLIDEUP, RISCV_VI_VSLIDEDOWN, RISCV_VI_VRGATHER}, + [RISCV_C_ADD] = {RISCV_C_ADD}, + [RISCV_FVFTYPE] = {RISCV_VF_VSUB, RISCV_VF_VSLIDE1UP, RISCV_VF_VSLIDE1DOWN, + RISCV_VF_VSGNJX, RISCV_VF_VSGNJN, RISCV_VF_VSGNJ, + RISCV_VF_VRSUB, RISCV_VF_VRDIV, RISCV_VF_VMUL, + RISCV_VF_VMIN, RISCV_VF_VMAX, RISCV_VF_VDIV, + RISCV_VF_VADD}, + [RISCV_FENCE_RESERVED] = {RISCV_FENCE_RESERVED}, + [RISCV_MASKTYPEI] = {RISCV_MASKTYPEI}, + [RISCV_FVVTYPE] = {RISCV_FVV_VSUB, RISCV_FVV_VSGNJX, RISCV_FVV_VSGNJN, + RISCV_FVV_VSGNJ, RISCV_FVV_VMUL, RISCV_FVV_VMIN, + RISCV_FVV_VMAX, RISCV_FVV_VDIV, RISCV_FVV_VADD}, + [RISCV_CPOPW] = {RISCV_CPOPW}, + [RISCV_C_LI_HINT] = {RISCV_C_LI_HINT}, + [RISCV_SHA256SUM1] = {RISCV_SHA256SUM1}, + [RISCV_VSUXSEGTYPE] = {RISCV_VSUXSEGTYPE}, + [RISCV_VIMCTYPE] = {RISCV_VIMC_VMADC}, + [RISCV_VIMSTYPE] = {RISCV_VIMS_VADC}, + [RISCV_MASKTYPEV] = {RISCV_MASKTYPEV}, + [RISCV_FVFMTYPE] = {RISCV_VFM_VMFNE, RISCV_VFM_VMFLT, RISCV_VFM_VMFLE, + RISCV_VFM_VMFGT, RISCV_VFM_VMFGE, RISCV_VFM_VMFEQ}, + [RISCV_ADDIW] = {RISCV_ADDIW}, + [RISCV_MRET] = {RISCV_MRET}, + [RISCV_VLSEGFFTYPE] = {RISCV_VLSEGFFTYPE}, + [RISCV_C_ANDI] = {RISCV_C_ANDI}, + [RISCV_WVTYPE] = {RISCV_WV_VSUBU, RISCV_WV_VSUB, RISCV_WV_VADDU, + RISCV_WV_VADD}, + [RISCV_C_SDSP] = {RISCV_C_SDSP}, + [RISCV_C_SUBW] = {RISCV_C_SUBW}, + [RISCV_VEXT4TYPE] = {RISCV_VEXT4_ZVF4, RISCV_VEXT4_SVF4}, + [RISCV_VSETVL] = {RISCV_VSETVL}, + [RISCV_C_SH] = {RISCV_C_SH}, + [RISCV_MVVCOMPRESS] = {RISCV_MVVCOMPRESS}, + [RISCV_FWVVTYPE] = {RISCV_FWVV_VSUB, RISCV_FWVV_VMUL, RISCV_FWVV_VADD}, + [RISCV_VMTYPE] = {RISCV_VSM, RISCV_VLM}, + [RISCV_FROUND_H] = {RISCV_FROUND_H}, + [RISCV_C_JAL] = {RISCV_C_JAL}, + [RISCV_SFENCE_VMA] = {RISCV_SFENCE_VMA}, + [RISCV_NVSTYPE] = {RISCV_NVS_VNSRL, RISCV_NVS_VNSRA}, + [RISCV_FROUND_S] = {RISCV_FROUND_S}, + [RISCV_NISTYPE] = {RISCV_NIS_VNSRL, RISCV_NIS_VNSRA}, + [RISCV_C_SLLI] = {RISCV_C_SLLI}, + [RISCV_VXMTYPE] = {RISCV_VXM_VMSBC, RISCV_VXM_VMADC}, + [RISCV_FENCEI] = {RISCV_FENCEI}, + [RISCV_VFMVSF] = {RISCV_VFMVSF}, + [RISCV_VEXT8TYPE] = {RISCV_VEXT8_ZVF8, RISCV_VEXT8_SVF8}, + [RISCV_C_OR] = {RISCV_C_OR}, + [RISCV_FWVFMATYPE] = {RISCV_FWVF_VNMSAC, RISCV_FWVF_VNMACC, + RISCV_FWVF_VMSAC, RISCV_FWVF_VMACC}, + [RISCV_SHIFTIOP] = {RISCV_SRLI, RISCV_SRAI, RISCV_SLLI}, + [RISCV_DIVW] = {RISCV_DIVW}, + [RISCV_C_ZEXT_B] = {RISCV_C_ZEXT_B}, + [RISCV_C_MV] = {RISCV_C_MV}, + [RISCV_VIMTYPE] = {RISCV_VIM_VMADC}, + [RISCV_LOADRES] = {RISCV_LOADRES}, + [RISCV_C_J] = {RISCV_C_J}, + [RISCV_AES32ESI] = {RISCV_AES32ESI}, + [RISCV_C_BEQZ] = {RISCV_C_BEQZ}, + [RISCV_SHA512SUM0] = {RISCV_SHA512SUM0}, + [RISCV_SHA512SUM0R] = {RISCV_SHA512SUM0R}, + [RISCV_REMW] = {RISCV_REMW}, + [RISCV_VFMV] = {RISCV_VFMV}, + [RISCV_C_SEXT_H] = {RISCV_C_SEXT_H}, + [RISCV_WMVXTYPE] = {RISCV_WMVX_VWMACCUS, RISCV_WMVX_VWMACCU, + RISCV_WMVX_VWMACCSU, RISCV_WMVX_VWMACC}, + [RISCV_C_FSW] = {RISCV_C_FSW}, + [RISCV_C_SW] = {RISCV_C_SW}, + [RISCV_ZBS_RTYPE] = {RISCV_BSET, RISCV_BINV, RISCV_BEXT, RISCV_BCLR}, + [RISCV_C_SUB] = {RISCV_C_SUB}, + [RISCV_VFUNARY0] = {RISCV_FV_CVT_X_F, RISCV_FV_CVT_XU_F, + RISCV_FV_CVT_RTZ_X_F, RISCV_FV_CVT_RTZ_XU_F, + RISCV_FV_CVT_F_XU, RISCV_FV_CVT_F_X}, + [RISCV_FROUNDNX_S] = {RISCV_FROUNDNX_S}, + [RISCV_ZICBOZ] = {RISCV_ZICBOZ}, + [RISCV_SFENCE_W_INVAL] = {RISCV_SFENCE_W_INVAL}, + [RISCV_C_JR] = {RISCV_C_JR}, + [RISCV_C_NOT] = {RISCV_C_NOT}, + [RISCV_ZBB_EXTOP] = {RISCV_ZEXTH, RISCV_SEXTH, RISCV_SEXTB}, + [RISCV_MVVTYPE] = {RISCV_MVV_VREMU, RISCV_MVV_VREM, RISCV_MVV_VMULHU, + RISCV_MVV_VMULHSU, RISCV_MVV_VMULH, RISCV_MVV_VMUL, + RISCV_MVV_VDIVU, RISCV_MVV_VDIV, RISCV_MVV_VASUBU, + RISCV_MVV_VASUB, RISCV_MVV_VAADDU, RISCV_MVV_VAADD}, + [RISCV_FVFMATYPE] = {RISCV_VF_VNMSUB, RISCV_VF_VNMSAC, RISCV_VF_VNMADD, + RISCV_VF_VNMACC, RISCV_VF_VMSUB, RISCV_VF_VMSAC, + RISCV_VF_VMADD, RISCV_VF_VMACC}, + [RISCV_FMAXM_H] = {RISCV_FMAXM_H}, + [RISCV_SHA256SUM0] = {RISCV_SHA256SUM0}, + [RISCV_ZBS_IOP] = {RISCV_BSETI, RISCV_BINVI, RISCV_BEXTI, RISCV_BCLRI}, + [RISCV_C_XOR] = {RISCV_C_XOR}, + [RISCV_FMINM_H] = {RISCV_FMINM_H}, + [RISCV_C_LUI_HINT] = {RISCV_C_LUI_HINT}, + [RISCV_VVMCTYPE] = {RISCV_VVMC_VMSBC, RISCV_VVMC_VMADC}, + [RISCV_F_BIN_RM_TYPE_S] = {RISCV_FSUB_S, RISCV_FMUL_S, RISCV_FDIV_S, + RISCV_FADD_S}, + [RISCV_SINVAL_VMA] = {RISCV_SINVAL_VMA}, + [RISCV_MOVETYPEX] = {RISCV_MOVETYPEX}, + [RISCV_C_BNEZ] = {RISCV_C_BNEZ}, + [RISCV_FWVVMATYPE] = {RISCV_FWVV_VNMSAC, RISCV_FWVV_VNMACC, + RISCV_FWVV_VMSAC, RISCV_FWVV_VMACC}, + [RISCV_AES64KS1I] = {RISCV_AES64KS1I}, + [RISCV_RMVVTYPE] = {RISCV_MVV_VREDXOR, RISCV_MVV_VREDSUM, RISCV_MVV_VREDOR, + RISCV_MVV_VREDMINU, RISCV_MVV_VREDMIN, + RISCV_MVV_VREDMAXU, RISCV_MVV_VREDMAX, + RISCV_MVV_VREDAND}, + [RISCV_CLZW] = {RISCV_CLZW}, + [RISCV_REM] = {RISCV_REM}, + [RISCV_C_EBREAK] = {RISCV_C_EBREAK}, + [RISCV_AES64ESM] = {RISCV_AES64ESM}, + [RISCV_VFNUNARY0] = {RISCV_FNV_CVT_X_F, RISCV_FNV_CVT_XU_F, + RISCV_FNV_CVT_RTZ_X_F, RISCV_FNV_CVT_RTZ_XU_F, + RISCV_FNV_CVT_ROD_F_F, RISCV_FNV_CVT_F_XU, + RISCV_FNV_CVT_F_X, RISCV_FNV_CVT_F_F}, + [RISCV_VFWUNARY0] = {RISCV_FWV_CVT_X_F, RISCV_FWV_CVT_XU_F, + RISCV_FWV_CVT_RTZ_X_F, RISCV_FWV_CVT_RTZ_XU_F, + RISCV_FWV_CVT_F_XU, RISCV_FWV_CVT_F_X, + RISCV_FWV_CVT_F_F}, + [RISCV_MOVETYPEV] = {RISCV_MOVETYPEV}, + [RISCV_VFUNARY1] = {RISCV_FVV_VSQRT, RISCV_FVV_VRSQRT7, RISCV_FVV_VREC7, + RISCV_FVV_VCLASS}, + [RISCV_FWVFTYPE] = {RISCV_FWVF_VSUB, RISCV_FWVF_VMUL, RISCV_FWVF_VADD}, + [RISCV_ZBA_RTYPE] = {RISCV_SH3ADD, RISCV_SH2ADD, RISCV_SH1ADD}, + [RISCV_C_SRLI] = {RISCV_C_SRLI}, + [RISCV_VSRETYPE] = {RISCV_VSRETYPE}, + [RISCV_C_SLLI_HINT] = {RISCV_C_SLLI_HINT}, + [RISCV_WVVTYPE] = {RISCV_WVV_VWMULU, RISCV_WVV_VWMULSU, RISCV_WVV_VWMUL, + RISCV_WVV_VSUBU, RISCV_WVV_VSUB, RISCV_WVV_VADDU, + RISCV_WVV_VADD}, + [RISCV_AES64DSM] = {RISCV_AES64DSM}, + [RISCV_URET] = {RISCV_URET}, + [RISCV_C_LI] = {RISCV_C_LI}, + [RISCV_CSR] = {RISCV_CSRRW, RISCV_CSRRS, RISCV_CSRRC}, + [RISCV_C_SRAI] = {RISCV_C_SRAI}, + [RISCV_FMVP_D_X] = {RISCV_FMVP_D_X}, + [RISCV_C_LBU] = {RISCV_C_LBU}, + [RISCV_F_UN_RM_TYPE_S] = {RISCV_FSQRT_S, RISCV_FCVT_W_S, RISCV_FCVT_WU_S, + RISCV_FCVT_S_WU, RISCV_FCVT_S_W, RISCV_FCVT_S_LU, + RISCV_FCVT_S_L, RISCV_FCVT_L_S, RISCV_FCVT_LU_S}, + [RISCV_RTYPEW] = {RISCV_SUBW, RISCV_SRLW, RISCV_SRAW, RISCV_SLLW, + RISCV_ADDW}, + [RISCV_WMVVTYPE] = {RISCV_WMVV_VWMACCU, RISCV_WMVV_VWMACCSU, + RISCV_WMVV_VWMACC}, + [RISCV_MULW] = {RISCV_MULW}, + [RISCV_VVCMPTYPE] = {RISCV_VVCMP_VMSNE, RISCV_VVCMP_VMSLTU, + RISCV_VVCMP_VMSLT, RISCV_VVCMP_VMSLEU, + RISCV_VVCMP_VMSLE, RISCV_VVCMP_VMSEQ}, + [RISCV_ILLEGAL] = {RISCV_ILLEGAL}, + [RISCV_BREV8] = {RISCV_BREV8}, + [RISCV_AES32DSMI] = {RISCV_AES32DSMI}, + [RISCV_C_FSD] = {RISCV_C_FSD}, + [RISCV_C_ADDW] = {RISCV_C_ADDW}, + [RISCV_VCPOP_M] = {RISCV_VCPOP_M}, + [RISCV_SHA256SIG1] = {RISCV_SHA256SIG1}, + [RISCV_MVXTYPE] = {RISCV_MVX_VSLIDE1UP, RISCV_MVX_VSLIDE1DOWN, + RISCV_MVX_VREMU, RISCV_MVX_VREM, RISCV_MVX_VMULHU, + RISCV_MVX_VMULHSU, RISCV_MVX_VMULH, RISCV_MVX_VMUL, + RISCV_MVX_VDIVU, RISCV_MVX_VDIV, RISCV_MVX_VASUBU, + RISCV_MVX_VASUB, RISCV_MVX_VAADDU, RISCV_MVX_VAADD}, +}; +uint16_t get_insn_type(struct ast *tree) { + switch (tree->ast_node_type) { + case RISCV_WXTYPE: + return to_insn[RISCV_WXTYPE][tree->ast_node.wxtype.funct6]; + case RISCV_RTYPE: + return to_insn[RISCV_RTYPE][tree->ast_node.rtype.op]; + case RISCV_RIVVTYPE: + return to_insn[RISCV_RIVVTYPE][tree->ast_node.rivvtype.funct6]; + case RISCV_VXSG: + return to_insn[RISCV_VXSG][tree->ast_node.vxsg.funct6]; + case RISCV_VXCMPTYPE: + return to_insn[RISCV_VXCMPTYPE][tree->ast_node.vxcmptype.funct6]; + case RISCV_SHIFTIWOP: + return to_insn[RISCV_SHIFTIWOP][tree->ast_node.shiftiwop.op]; + case RISCV_ZICBOM: + return to_insn[RISCV_ZICBOM][tree->ast_node.riscv_zicbom.cbop]; + case RISCV_NITYPE: + return to_insn[RISCV_NITYPE][tree->ast_node.nitype.funct6]; + case RISCV_VVMTYPE: + return to_insn[RISCV_VVMTYPE][tree->ast_node.vvmtype.funct6]; + case RISCV_MVXMATYPE: + return to_insn[RISCV_MVXMATYPE][tree->ast_node.mvxmatype.funct6]; + case RISCV_F_BIN_TYPE_H: + return to_insn[RISCV_F_BIN_TYPE_H][tree->ast_node.f_bin_type_h.fle_h]; + case RISCV_FVVMTYPE: + return to_insn[RISCV_FVVMTYPE][tree->ast_node.fvvmtype.funct6]; + case RISCV_F_UN_RM_TYPE_D: + return to_insn[RISCV_F_UN_RM_TYPE_D] + [tree->ast_node.f_un_rm_type_d.fcvt_d_lu]; + case RISCV_WVXTYPE: + return to_insn[RISCV_WVXTYPE][tree->ast_node.wvxtype.funct6]; + case RISCV_NXSTYPE: + return to_insn[RISCV_NXSTYPE][tree->ast_node.nxstype.funct6]; + case RISCV_VXMCTYPE: + return to_insn[RISCV_VXMCTYPE][tree->ast_node.vxmctype.funct6]; + case RISCV_MMTYPE: + return to_insn[RISCV_MMTYPE][tree->ast_node.mmtype.funct6]; + case RISCV_F_UN_TYPE_S: + return to_insn[RISCV_F_UN_TYPE_S][tree->ast_node.f_un_type_s.fmv_w_x]; + case RISCV_NVTYPE: + return to_insn[RISCV_NVTYPE][tree->ast_node.nvtype.funct6]; + case RISCV_F_MADD_TYPE_H: + return to_insn[RISCV_F_MADD_TYPE_H][tree->ast_node.f_madd_type_h.op]; + case RISCV_ZBA_RTYPEUW: + return to_insn[RISCV_ZBA_RTYPEUW][tree->ast_node.zba_rtypeuw.op]; + case RISCV_F_BIN_RM_TYPE_D: + return to_insn[RISCV_F_BIN_RM_TYPE_D][tree->ast_node.f_bin_rm_type_d.op]; + case RISCV_F_MADD_TYPE_S: + return to_insn[RISCV_F_MADD_TYPE_S][tree->ast_node.f_madd_type_s.op]; + case RISCV_F_UN_RM_TYPE_H: + return to_insn[RISCV_F_UN_RM_TYPE_H] + [tree->ast_node.f_un_rm_type_h.fcvt_h_lu]; + case RISCV_FWFTYPE: + return to_insn[RISCV_FWFTYPE][tree->ast_node.fwftype.funct6]; + case RISCV_FWVTYPE: + return to_insn[RISCV_FWVTYPE][tree->ast_node.fwvtype.funct6]; + case RISCV_ZBB_RTYPE: + return to_insn[RISCV_ZBB_RTYPE][tree->ast_node.zbb_rtype.op]; + case RISCV_NXTYPE: + return to_insn[RISCV_NXTYPE][tree->ast_node.nxtype.funct6]; + case RISCV_ITYPE: + return to_insn[RISCV_ITYPE][tree->ast_node.itype.op]; + case RISCV_F_BIN_TYPE_S: + return to_insn[RISCV_F_BIN_TYPE_S][tree->ast_node.f_bin_type_s.fle_s]; + case RISCV_F_BIN_TYPE_D: + return to_insn[RISCV_F_BIN_TYPE_D][tree->ast_node.f_bin_type_d.fle_d]; + case RISCV_ZICOND_RTYPE: + return to_insn[RISCV_ZICOND_RTYPE] + [tree->ast_node.zicond_rtype.riscv_czero_nez]; + case RISCV_ZBB_RTYPEW: + return to_insn[RISCV_ZBB_RTYPEW][tree->ast_node.zbb_rtypew.op]; + case RISCV_RFVVTYPE: + return to_insn[RISCV_RFVVTYPE][tree->ast_node.rfvvtype.funct6]; + case RISCV_AMO: + return to_insn[RISCV_AMO][tree->ast_node.amo.op]; + case RISCV_VVMSTYPE: + return to_insn[RISCV_VVMSTYPE][tree->ast_node.vvmstype.funct6]; + case RISCV_FVVMATYPE: + return to_insn[RISCV_FVVMATYPE][tree->ast_node.fvvmatype.funct6]; + case RISCV_VEXT2TYPE: + return to_insn[RISCV_VEXT2TYPE][tree->ast_node.vext2type.funct6]; + case RISCV_F_MADD_TYPE_D: + return to_insn[RISCV_F_MADD_TYPE_D][tree->ast_node.f_madd_type_d.op]; + case RISCV_F_UN_TYPE_H: + return to_insn[RISCV_F_UN_TYPE_H][tree->ast_node.f_un_type_h.fmv_h_x]; + case RISCV_VVTYPE: + return to_insn[RISCV_VVTYPE][tree->ast_node.vvtype.funct6]; + case RISCV_VICMPTYPE: + return to_insn[RISCV_VICMPTYPE][tree->ast_node.vicmptype.funct6]; + case RISCV_F_UN_TYPE_D: + return to_insn[RISCV_F_UN_TYPE_D][tree->ast_node.f_un_type_d.fmv_d_x]; + case RISCV_MVVMATYPE: + return to_insn[RISCV_MVVMATYPE][tree->ast_node.mvvmatype.funct6]; + case RISCV_VXTYPE: + return to_insn[RISCV_VXTYPE][tree->ast_node.vxtype.funct6]; + case RISCV_BTYPE: + return to_insn[RISCV_BTYPE][tree->ast_node.btype.op]; + case RISCV_VXMSTYPE: + return to_insn[RISCV_VXMSTYPE][tree->ast_node.vxmstype.funct6]; + case RISCV_UTYPE: + return to_insn[RISCV_UTYPE][tree->ast_node.utype.op]; + case RISCV_F_BIN_RM_TYPE_H: + return to_insn[RISCV_F_BIN_RM_TYPE_H][tree->ast_node.f_bin_rm_type_h.op]; + case RISCV_VITYPE: + return to_insn[RISCV_VITYPE][tree->ast_node.vitype.funct6]; + case RISCV_ZBKB_RTYPE: + return to_insn[RISCV_ZBKB_RTYPE][tree->ast_node.zbkb_rtype.op]; + case RISCV_VISG: + return to_insn[RISCV_VISG][tree->ast_node.visg.funct6]; + case RISCV_FVFTYPE: + return to_insn[RISCV_FVFTYPE][tree->ast_node.fvftype.funct6]; + case RISCV_FVVTYPE: + return to_insn[RISCV_FVVTYPE][tree->ast_node.fvvtype.funct6]; + case RISCV_VIMCTYPE: + return to_insn[RISCV_VIMCTYPE][tree->ast_node.vimctype.funct6]; + case RISCV_VIMSTYPE: + return to_insn[RISCV_VIMSTYPE][tree->ast_node.vimstype.funct6]; + case RISCV_FVFMTYPE: + return to_insn[RISCV_FVFMTYPE][tree->ast_node.fvfmtype.funct6]; + case RISCV_WVTYPE: + return to_insn[RISCV_WVTYPE][tree->ast_node.wvtype.funct6]; + case RISCV_VEXT4TYPE: + return to_insn[RISCV_VEXT4TYPE][tree->ast_node.vext4type.funct6]; + case RISCV_FWVVTYPE: + return to_insn[RISCV_FWVVTYPE][tree->ast_node.fwvvtype.funct6]; + case RISCV_VMTYPE: + return to_insn[RISCV_VMTYPE][tree->ast_node.vmtype.op]; + case RISCV_NVSTYPE: + return to_insn[RISCV_NVSTYPE][tree->ast_node.nvstype.funct6]; + case RISCV_NISTYPE: + return to_insn[RISCV_NISTYPE][tree->ast_node.nistype.funct6]; + case RISCV_VXMTYPE: + return to_insn[RISCV_VXMTYPE][tree->ast_node.vxmtype.funct6]; + case RISCV_VEXT8TYPE: + return to_insn[RISCV_VEXT8TYPE][tree->ast_node.vext8type.funct6]; + case RISCV_FWVFMATYPE: + return to_insn[RISCV_FWVFMATYPE][tree->ast_node.fwvfmatype.funct6]; + case RISCV_SHIFTIOP: + return to_insn[RISCV_SHIFTIOP][tree->ast_node.shiftiop.op]; + case RISCV_VIMTYPE: + return to_insn[RISCV_VIMTYPE][tree->ast_node.vimtype.funct6]; + case RISCV_WMVXTYPE: + return to_insn[RISCV_WMVXTYPE][tree->ast_node.wmvxtype.funct6]; + case RISCV_ZBS_RTYPE: + return to_insn[RISCV_ZBS_RTYPE][tree->ast_node.zbs_rtype.op]; + case RISCV_VFUNARY0: + return to_insn[RISCV_VFUNARY0][tree->ast_node.vfunary0.vfunary0]; + case RISCV_ZBB_EXTOP: + return to_insn[RISCV_ZBB_EXTOP][tree->ast_node.zbb_extop.op]; + case RISCV_MVVTYPE: + return to_insn[RISCV_MVVTYPE][tree->ast_node.mvvtype.funct6]; + case RISCV_FVFMATYPE: + return to_insn[RISCV_FVFMATYPE][tree->ast_node.fvfmatype.funct6]; + case RISCV_ZBS_IOP: + return to_insn[RISCV_ZBS_IOP][tree->ast_node.zbs_iop.op]; + case RISCV_VVMCTYPE: + return to_insn[RISCV_VVMCTYPE][tree->ast_node.vvmctype.funct6]; + case RISCV_F_BIN_RM_TYPE_S: + return to_insn[RISCV_F_BIN_RM_TYPE_S][tree->ast_node.f_bin_rm_type_s.op]; + case RISCV_FWVVMATYPE: + return to_insn[RISCV_FWVVMATYPE][tree->ast_node.fwvvmatype.funct6]; + case RISCV_RMVVTYPE: + return to_insn[RISCV_RMVVTYPE][tree->ast_node.rmvvtype.funct6]; + case RISCV_VFNUNARY0: + return to_insn[RISCV_VFNUNARY0][tree->ast_node.vfnunary0.vfnunary0]; + case RISCV_VFWUNARY0: + return to_insn[RISCV_VFWUNARY0][tree->ast_node.vfwunary0.vfwunary0]; + case RISCV_VFUNARY1: + return to_insn[RISCV_VFUNARY1][tree->ast_node.vfunary1.vfunary1]; + case RISCV_FWVFTYPE: + return to_insn[RISCV_FWVFTYPE][tree->ast_node.fwvftype.funct6]; + case RISCV_ZBA_RTYPE: + return to_insn[RISCV_ZBA_RTYPE][tree->ast_node.zba_rtype.op]; + case RISCV_WVVTYPE: + return to_insn[RISCV_WVVTYPE][tree->ast_node.wvvtype.funct6]; + case RISCV_CSR: + return to_insn[RISCV_CSR][tree->ast_node.csr.op]; + case RISCV_F_UN_RM_TYPE_S: + return to_insn[RISCV_F_UN_RM_TYPE_S] + [tree->ast_node.f_un_rm_type_s.fcvt_s_lu]; + case RISCV_RTYPEW: + return to_insn[RISCV_RTYPEW][tree->ast_node.rtypew.op]; + case RISCV_WMVVTYPE: + return to_insn[RISCV_WMVVTYPE][tree->ast_node.wmvvtype.funct6]; + case RISCV_VVCMPTYPE: + return to_insn[RISCV_VVCMPTYPE][tree->ast_node.vvcmptype.funct6]; + case RISCV_MVXTYPE: + return to_insn[RISCV_MVXTYPE][tree->ast_node.mvxtype.funct6]; + default: + return to_insn[tree->ast_node_type][0]; + } +} + +#endif diff --git a/sail.instr_types_excluded_enums.txt b/sail.instr_types_excluded_enums.txt new file mode 100644 index 0000000..fd76f2e --- /dev/null +++ b/sail.instr_types_excluded_enums.txt @@ -0,0 +1,3 @@ +rounding_mode +vlewidth +word_width \ No newline at end of file