From 30f7a361e71990ed545e6b22ebc9d4a396dd9656 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Tue, 21 Nov 2023 20:10:57 -0500 Subject: [PATCH] Update generated files. --- librz/analysis/arch/hexagon/hexagon_il.c | 39 ++++- librz/analysis/arch/hexagon/hexagon_il.h | 4 +- .../arch/hexagon/hexagon_il_getter_table.h | 4 +- .../arch/hexagon/il_ops/hexagon_il_A2_ops.c | 48 +++--- .../arch/hexagon/il_ops/hexagon_il_A4_ops.c | 8 +- .../arch/hexagon/il_ops/hexagon_il_A5_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_A6_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_A7_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_C2_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_C4_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_F2_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_G4_ops.c | 4 +- .../hexagon/il_ops/hexagon_il_IMPORTED_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_J2_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_J4_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_L2_ops.c | 32 ++-- .../arch/hexagon/il_ops/hexagon_il_L4_ops.c | 22 +-- .../arch/hexagon/il_ops/hexagon_il_L6_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_M2_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_M4_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_M5_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_M6_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_M7_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_R6_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_S2_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_S4_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_S5_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_S6_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_SA1_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_SL1_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_SL2_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_SS1_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_SS2_ops.c | 4 +- .../il_ops/hexagon_il_UNDOCUMENTED_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_V6_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_Y2_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_Y4_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_Y5_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_Y6_ops.c | 4 +- .../arch/hexagon/il_ops/hexagon_il_dep_ops.c | 4 +- .../hexagon/il_ops/hexagon_il_invalid_ops.c | 4 +- .../hexagon/il_ops/hexagon_il_non_insn_ops.c | 4 +- .../analysis/hexagon_dwarf_reg_num_table.inc | 2 +- librz/analysis/p/analysis_hexagon.c | 4 +- librz/asm/arch/hexagon/hexagon.c | 144 +++++++++--------- librz/asm/arch/hexagon/hexagon.h | 4 +- librz/asm/arch/hexagon/hexagon_arch.c | 4 +- librz/asm/arch/hexagon/hexagon_arch.h | 4 +- librz/asm/arch/hexagon/hexagon_disas.c | 12 +- librz/asm/arch/hexagon/hexagon_insn.h | 4 +- librz/asm/arch/hexagon/hexagon_reg_tables.h | 4 +- librz/asm/p/asm_hexagon.c | 4 +- test/db/asm/hexagon | 2 +- 53 files changed, 259 insertions(+), 226 deletions(-) diff --git a/librz/analysis/arch/hexagon/hexagon_il.c b/librz/analysis/arch/hexagon/hexagon_il.c index 48bd5799a11..fa4265c87be 100644 --- a/librz/analysis/arch/hexagon/hexagon_il.c +++ b/librz/analysis/arch/hexagon/hexagon_il.c @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -268,7 +268,7 @@ static bool set_pkt_il_ops(RZ_INOUT HexPkt *p) { } return true; not_impl: - RZ_LOG_WARN("Hexagon instruction %" PFMT32d " not implemented.\n", pos->bin.insn->identifier); + RZ_LOG_INFO("Hexagon instruction %" PFMT32d " not implemented.\n", pos->bin.insn->identifier); return false; } @@ -329,6 +329,9 @@ RZ_IPI RzILOpEffect *hex_get_il_op(const ut32 addr, const bool get_pkt_op) { if (!hic) { return EMPTY(); } + if (hic->identifier == HEX_INS_INVALID_DECODE) { + return NULL; + } if (state->just_init || might_has_jumped) { // Assume that the instruction at the address the VM was initialized is the first instruction. // Also make it valid if a jump let to this packet. @@ -359,7 +362,7 @@ RZ_IPI RzILOpEffect *hex_get_il_op(const ut32 addr, const bool get_pkt_op) { rz_vector_push(p->il_ops, op); if (!set_pkt_il_ops(p)) { - RZ_LOG_WARN("IL ops at 0x%" PFMT32x " contain not implemented instructions.\n", addr); + RZ_LOG_INFO("IL ops at 0x%" PFMT32x " contain not implemented instructions.\n", addr); return NULL; } @@ -564,17 +567,26 @@ RZ_IPI RZ_OWN RzILOpEffect *hex_write_reg(RZ_BORROW HexInsnPktBundle *bundle, co case HEX_REG_CLASS_DOUBLE_REGS: case HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS: high_name = hex_get_reg_in_class(HEX_REG_CLASS_INT_REGS, reg_num + 1, false, true, true); + if (!high_name) { + return NULL; + } high_val = SHIFTR0(DUP(val), U8(HEX_GPR_WIDTH)); // fallthrough case HEX_REG_CLASS_INT_REGS: case HEX_REG_CLASS_INT_REGS_LOW8: case HEX_REG_CLASS_GENERAL_SUB_REGS: low_name = hex_get_reg_in_class(HEX_REG_CLASS_INT_REGS, reg_num, false, true, true); + if (!low_name) { + return NULL; + } low_val = CAST(HEX_GPR_WIDTH, IL_FALSE, val); break; case HEX_REG_CLASS_CTR_REGS64: if (hex_ctr_immut_masks[reg_num + 1] != HEX_IMMUTABLE_REG) { high_name = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, reg_num + 1, false, true, true); + if (!high_name) { + return NULL; + } high_val = SHIFTR0(DUP(val), U8(HEX_GPR_WIDTH)); if (hex_ctr_immut_masks[reg_num + 1] != 0) { high_val = get_masked_reg_val(VARG(high_name), CAST(HEX_GPR_WIDTH, IL_FALSE, high_val), hex_ctr_immut_masks[reg_num + 1]); @@ -585,6 +597,9 @@ RZ_IPI RZ_OWN RzILOpEffect *hex_write_reg(RZ_BORROW HexInsnPktBundle *bundle, co case HEX_REG_CLASS_CTR_REGS: if (hex_ctr_immut_masks[reg_num] != HEX_IMMUTABLE_REG) { low_name = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, reg_num, false, true, true); + if (!low_name) { + return NULL; + } low_val = CAST(HEX_GPR_WIDTH, IL_FALSE, val); if (hex_ctr_immut_masks[reg_num] != 0) { low_val = get_masked_reg_val(VARG(low_name), low_val, hex_ctr_immut_masks[reg_num]); @@ -606,6 +621,9 @@ RZ_IPI RZ_OWN RzILOpEffect *hex_write_reg(RZ_BORROW HexInsnPktBundle *bundle, co break; case HEX_REG_CLASS_PRED_REGS: low_name = hex_get_reg_in_class(HEX_REG_CLASS_PRED_REGS, reg_num, false, true, true); + if (!low_name) { + return NULL; + } if (other_slot_wrote_to_pred(bundle, reg_num)) { // If the register was written before by another slot, the values get ANDed. low_val = LOGAND(VARG(low_name), val); @@ -705,6 +723,9 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b tmp_reg = true; } high_name = hex_get_reg_in_class(HEX_REG_CLASS_INT_REGS, reg_num + 1, false, tmp_reg, true); + if (!high_name) { + return NULL; + } high_val = SHIFTL0(CAST(HEX_GPR64_WIDTH, IL_FALSE, VARG(high_name)), U8(HEX_GPR_WIDTH)); val_width = HEX_GPR64_WIDTH; // fallthrough @@ -716,6 +737,9 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b tmp_reg = true; } low_name = hex_get_reg_in_class(HEX_REG_CLASS_INT_REGS, reg_num, false, tmp_reg, true); + if (!low_name) { + return NULL; + } low_val = VARG(low_name); break; case HEX_REG_CLASS_CTR_REGS64: @@ -724,6 +748,9 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b tmp_reg = true; } high_name = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, reg_num + 1, false, tmp_reg, true); + if (!high_name) { + return NULL; + } if (reg_num + 1 == 9) { // C9 = PC. Does not exist in VM as var high_val = SHIFTL0(CAST(HEX_GPR64_WIDTH, IL_FALSE, U32(pkt->pkt_addr)), U8(HEX_GPR_WIDTH)); @@ -753,6 +780,9 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b break; } low_name = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, reg_num, false, tmp_reg, true); + if (!low_name) { + return NULL; + } if (reg_num == 9) { low_val = U32(pkt->pkt_addr); } else { @@ -765,6 +795,9 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b tmp_reg = true; } low_name = hex_get_reg_in_class(HEX_REG_CLASS_PRED_REGS, reg_num, false, tmp_reg, true); + if (!low_name) { + return NULL; + } return VARG(low_name); } if (read_cond_faulty(low_val, high_val, val_width)) { diff --git a/librz/analysis/arch/hexagon/hexagon_il.h b/librz/analysis/arch/hexagon/hexagon_il.h index 12ca88c61b7..aa5b37cd20d 100644 --- a/librz/analysis/arch/hexagon/hexagon_il.h +++ b/librz/analysis/arch/hexagon/hexagon_il.h @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/hexagon_il_getter_table.h b/librz/analysis/arch/hexagon/hexagon_il_getter_table.h index faea2980066..59b4fef5156 100644 --- a/librz/analysis/arch/hexagon/hexagon_il_getter_table.h +++ b/librz/analysis/arch/hexagon/hexagon_il_getter_table.h @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A2_ops.c index 6c3bb504b75..0475e71e4dd 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A2_ops.c @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -756,7 +756,7 @@ RzILOpEffect *hex_il_op_a2_addpsat(HexInsnPktBundle *bundle) { RzILOpPure *op_AND_17 = LOGAND(VARL("__xor"), VARL("__mask")); RzILOpEffect *branch_44 = BRANCH(NON_ZERO(op_AND_17), seq_then_42, seq_else_43); - RzILOpEffect *instruction_sequence = SEQN(6, op_ASSIGN_3, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_44); + RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_3, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_44, EMPTY()); return instruction_sequence; } @@ -6279,45 +6279,45 @@ RzILOpEffect *hex_il_op_a2_vcmpwgt(HexInsnPktBundle *bundle) { RzILOpEffect *seq_44 = SEQN(2, op_ASSIGN_2, for_43); // j = 0x4; - RzILOpEffect *op_ASSIGN_46 = SETL("j", SN(32, 4)); + RzILOpEffect *op_ASSIGN_47 = SETL("j", SN(32, 4)); // HYB(++j); - RzILOpEffect *op_INC_49 = SETL("j", INC(VARL("j"), 32)); + RzILOpEffect *op_INC_50 = SETL("j", INC(VARL("j"), 32)); // h_tmp71 = HYB(++j); - RzILOpEffect *op_ASSIGN_hybrid_tmp_51 = SETL("h_tmp71", VARL("j")); + RzILOpEffect *op_ASSIGN_hybrid_tmp_52 = SETL("h_tmp71", VARL("j")); // seq(h_tmp71 = HYB(++j); HYB(++j)); - RzILOpEffect *seq_52 = SEQN(2, op_ASSIGN_hybrid_tmp_51, op_INC_49); + RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_hybrid_tmp_52, op_INC_50); // Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) | (((((st64) ((st32) ((Rss >> 0x20) & 0xffffffff))) > ((st64) ((st32) ((Rtt >> 0x20) & 0xffffffff)))) ? 0x1 : 0x0) << j))); - RzILOpPure *op_LSHIFT_54 = SHIFTL0(UN(64, 1), VARL("j")); - RzILOpPure *op_NOT_55 = LOGNOT(op_LSHIFT_54); - RzILOpPure *op_AND_58 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_55); - RzILOpPure *op_RSHIFT_62 = SHIFTRA(DUP(Rss), SN(32, 0x20)); - RzILOpPure *op_AND_64 = LOGAND(op_RSHIFT_62, SN(64, 0xffffffff)); - RzILOpPure *op_RSHIFT_70 = SHIFTRA(DUP(Rtt), SN(32, 0x20)); - RzILOpPure *op_AND_72 = LOGAND(op_RSHIFT_70, SN(64, 0xffffffff)); - RzILOpPure *op_GT_75 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_64), DUP(op_AND_64))), CAST(32, MSB(DUP(op_AND_64)), DUP(op_AND_64))), CAST(64, MSB(CAST(32, MSB(op_AND_72), DUP(op_AND_72))), CAST(32, MSB(DUP(op_AND_72)), DUP(op_AND_72)))); - RzILOpPure *ite_cast_ut64_76 = ITE(op_GT_75, UN(64, 1), UN(64, 0)); - RzILOpPure *op_LSHIFT_77 = SHIFTL0(ite_cast_ut64_76, VARL("j")); - RzILOpPure *op_OR_78 = LOGOR(op_AND_58, op_LSHIFT_77); - RzILOpEffect *op_ASSIGN_80 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_78)); + RzILOpPure *op_LSHIFT_55 = SHIFTL0(UN(64, 1), VARL("j")); + RzILOpPure *op_NOT_56 = LOGNOT(op_LSHIFT_55); + RzILOpPure *op_AND_59 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_56); + RzILOpPure *op_RSHIFT_63 = SHIFTRA(DUP(Rss), SN(32, 0x20)); + RzILOpPure *op_AND_65 = LOGAND(op_RSHIFT_63, SN(64, 0xffffffff)); + RzILOpPure *op_RSHIFT_71 = SHIFTRA(DUP(Rtt), SN(32, 0x20)); + RzILOpPure *op_AND_73 = LOGAND(op_RSHIFT_71, SN(64, 0xffffffff)); + RzILOpPure *op_GT_76 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_65), DUP(op_AND_65))), CAST(32, MSB(DUP(op_AND_65)), DUP(op_AND_65))), CAST(64, MSB(CAST(32, MSB(op_AND_73), DUP(op_AND_73))), CAST(32, MSB(DUP(op_AND_73)), DUP(op_AND_73)))); + RzILOpPure *ite_cast_ut64_77 = ITE(op_GT_76, UN(64, 1), UN(64, 0)); + RzILOpPure *op_LSHIFT_78 = SHIFTL0(ite_cast_ut64_77, VARL("j")); + RzILOpPure *op_OR_79 = LOGOR(op_AND_59, op_LSHIFT_78); + RzILOpEffect *op_ASSIGN_81 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_79)); // seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) ...; - RzILOpEffect *seq_82 = SEQN(2, op_ASSIGN_80, EMPTY()); + RzILOpEffect *seq_83 = SEQN(2, op_ASSIGN_81, EMPTY()); // seq(seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ...; - RzILOpEffect *seq_83 = SEQN(2, seq_82, seq_52); + RzILOpEffect *seq_84 = SEQN(2, seq_83, seq_53); // while ((j <= 0x7)) { seq(seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ... }; - RzILOpPure *op_LE_48 = SLE(VARL("j"), SN(32, 7)); - RzILOpEffect *for_84 = REPEAT(op_LE_48, seq_83); + RzILOpPure *op_LE_49 = SLE(VARL("j"), SN(32, 7)); + RzILOpEffect *for_85 = REPEAT(op_LE_49, seq_84); // seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp71; Pd = ((st8) ( ...; - RzILOpEffect *seq_85 = SEQN(2, op_ASSIGN_46, for_84); + RzILOpEffect *seq_86 = SEQN(2, op_ASSIGN_47, for_85); - RzILOpEffect *instruction_sequence = SEQN(2, seq_44, seq_85); + RzILOpEffect *instruction_sequence = SEQN(4, seq_44, EMPTY(), seq_86, EMPTY()); return instruction_sequence; } diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A4_ops.c index dcc756418ce..b8bc45b75f0 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A4_ops.c @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -2511,7 +2511,7 @@ RzILOpEffect *hex_il_op_a4_vcmpweqi(HexInsnPktBundle *bundle) { // seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp134; Pd = ((st8) ...; RzILOpEffect *seq_73 = SEQN(2, op_ASSIGN_41, for_72); - RzILOpEffect *instruction_sequence = SEQN(5, imm_assign_25, seq_38, EMPTY(), seq_73, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(4, imm_assign_25, seq_38, EMPTY(), seq_73); return instruction_sequence; } @@ -2603,7 +2603,7 @@ RzILOpEffect *hex_il_op_a4_vcmpwgti(HexInsnPktBundle *bundle) { // seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp136; Pd = ((st8) ...; RzILOpEffect *seq_73 = SEQN(2, op_ASSIGN_41, for_72); - RzILOpEffect *instruction_sequence = SEQN(4, imm_assign_25, seq_38, EMPTY(), seq_73); + RzILOpEffect *instruction_sequence = SEQN(5, imm_assign_25, seq_38, EMPTY(), seq_73, EMPTY()); return instruction_sequence; } @@ -2695,7 +2695,7 @@ RzILOpEffect *hex_il_op_a4_vcmpwgtui(HexInsnPktBundle *bundle) { // seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp138; Pd = ((st8) ...; RzILOpEffect *seq_72 = SEQN(2, op_ASSIGN_40, for_71); - RzILOpEffect *instruction_sequence = SEQN(4, imm_assign_25, seq_38, seq_72, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(3, imm_assign_25, seq_38, seq_72); return instruction_sequence; } diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A5_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A5_ops.c index b4cc5cea93f..bf78fbac178 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A5_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A5_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A6_ops.c index c02f3e9eb8d..0713853b1fb 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A6_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A7_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A7_ops.c index c51f611b603..b173f086bde 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A7_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A7_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_C2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_C2_ops.c index 53623523259..a3b7c06588e 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_C2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_C2_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_C4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_C4_ops.c index fbfcfa6b419..49c14d3c214 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_C4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_C4_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_F2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_F2_ops.c index f2949b32f8d..261ae413cae 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_F2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_F2_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_G4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_G4_ops.c index a77c73e1776..44d1283fc36 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_G4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_G4_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_IMPORTED_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_IMPORTED_ops.c index f307cc383ac..a7c5b9fdf4d 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_IMPORTED_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_IMPORTED_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_J2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_J2_ops.c index ca52c9e779e..2142281521e 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_J2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_J2_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_J4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_J4_ops.c index e109e242c4e..f8a1ab8d3d1 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_J4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_J4_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L2_ops.c index 586ddc8853d..08028ea2c44 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L2_ops.c @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -169,7 +169,7 @@ RzILOpEffect *hex_il_op_l2_loadalignb_pci(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_25 = LOGOR(op_RSHIFT_22, op_LSHIFT_24); RzILOpEffect *op_ASSIGN_27 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_25)); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, op_ASSIGN_27); + RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, op_ASSIGN_27, EMPTY()); return instruction_sequence; } @@ -215,7 +215,7 @@ RzILOpEffect *hex_il_op_l2_loadalignb_pcr(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_43 = LOGOR(op_RSHIFT_40, op_LSHIFT_42); RzILOpEffect *op_ASSIGN_45 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_43)); - RzILOpEffect *instruction_sequence = SEQN(7, seq_30, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_36, op_ASSIGN_45, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(6, seq_30, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_36, op_ASSIGN_45); return instruction_sequence; } @@ -252,7 +252,7 @@ RzILOpEffect *hex_il_op_l2_loadalignb_pi(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_21 = LOGOR(op_RSHIFT_18, op_LSHIFT_20); RzILOpEffect *op_ASSIGN_23 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_21)); - RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, op_ASSIGN_23, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, op_ASSIGN_23); return instruction_sequence; } @@ -287,7 +287,7 @@ RzILOpEffect *hex_il_op_l2_loadalignb_pr(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_20 = LOGOR(op_RSHIFT_17, op_LSHIFT_19); RzILOpEffect *op_ASSIGN_22 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_20)); - RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, op_ASSIGN_22, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(6, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, op_ASSIGN_22); return instruction_sequence; } @@ -495,7 +495,7 @@ RzILOpEffect *hex_il_op_l2_loadalignh_pi(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_21 = LOGOR(op_RSHIFT_18, op_LSHIFT_20); RzILOpEffect *op_ASSIGN_23 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_21)); - RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, op_ASSIGN_23, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, op_ASSIGN_23); return instruction_sequence; } @@ -530,7 +530,7 @@ RzILOpEffect *hex_il_op_l2_loadalignh_pr(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_20 = LOGOR(op_RSHIFT_17, op_LSHIFT_19); RzILOpEffect *op_ASSIGN_22 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_20)); - RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, op_ASSIGN_22, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(6, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, op_ASSIGN_22); return instruction_sequence; } @@ -1118,7 +1118,7 @@ RzILOpEffect *hex_il_op_l2_loadbsw4_pbr(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp181; Rdd = ((st64) ...; RzILOpEffect *seq_55 = SEQN(2, op_ASSIGN_19, for_54); - RzILOpEffect *instruction_sequence = SEQN(6, seq_8, op_ASSIGN_11, EMPTY(), op_ASSIGN_17, seq_55, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(5, seq_8, op_ASSIGN_11, EMPTY(), op_ASSIGN_17, seq_55); return instruction_sequence; } @@ -1195,7 +1195,7 @@ RzILOpEffect *hex_il_op_l2_loadbsw4_pci(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp183; Rdd = ((st64) ...; RzILOpEffect *seq_56 = SEQN(2, op_ASSIGN_20, for_55); - RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_56, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_56); return instruction_sequence; } @@ -1344,7 +1344,7 @@ RzILOpEffect *hex_il_op_l2_loadbsw4_pi(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp186; Rdd = ((st64) ...; RzILOpEffect *seq_52 = SEQN(2, op_ASSIGN_16, for_51); - RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, seq_52, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, seq_52); return instruction_sequence; } @@ -1412,7 +1412,7 @@ RzILOpEffect *hex_il_op_l2_loadbsw4_pr(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp187; Rdd = ((st64) ...; RzILOpEffect *seq_51 = SEQN(2, op_ASSIGN_15, for_50); - RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, seq_51, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(6, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, seq_51); return instruction_sequence; } @@ -1636,7 +1636,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw2_pci(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp192; Rd = ((st32) ...; RzILOpEffect *seq_57 = SEQN(2, op_ASSIGN_20, for_56); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_57); + RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_57, EMPTY()); return instruction_sequence; } @@ -1715,7 +1715,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw2_pcr(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp194; Rd = ((st32) ...; RzILOpEffect *seq_75 = SEQN(2, op_ASSIGN_38, for_74); - RzILOpEffect *instruction_sequence = SEQN(6, seq_30, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_36, seq_75); + RzILOpEffect *instruction_sequence = SEQN(7, seq_30, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_36, seq_75, EMPTY()); return instruction_sequence; } @@ -1920,7 +1920,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw4_io(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp197; Rdd = ((st64) ...; RzILOpEffect *seq_50 = SEQN(2, op_ASSIGN_14, for_49); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, op_ASSIGN_6, EMPTY(), op_ASSIGN_12, seq_50, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(5, imm_assign_0, op_ASSIGN_6, EMPTY(), op_ASSIGN_12, seq_50); return instruction_sequence; } @@ -2000,7 +2000,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw4_pbr(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp199; Rdd = ((st64) ...; RzILOpEffect *seq_55 = SEQN(2, op_ASSIGN_19, for_54); - RzILOpEffect *instruction_sequence = SEQN(5, seq_8, op_ASSIGN_11, EMPTY(), op_ASSIGN_17, seq_55); + RzILOpEffect *instruction_sequence = SEQN(6, seq_8, op_ASSIGN_11, EMPTY(), op_ASSIGN_17, seq_55, EMPTY()); return instruction_sequence; } @@ -2077,7 +2077,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw4_pci(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp201; Rdd = ((st64) ...; RzILOpEffect *seq_56 = SEQN(2, op_ASSIGN_20, for_55); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_56); + RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_56, EMPTY()); return instruction_sequence; } diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L4_ops.c index f8cdfdcd620..1a79f449fe4 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L4_ops.c @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -706,9 +706,9 @@ RzILOpEffect *hex_il_op_l4_loadalignb_ap(HexInsnPktBundle *bundle) { RzILOpEffect *op_ASSIGN_18 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_16)); // Re = ((st32) U); - RzILOpEffect *op_ASSIGN_21 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); + RzILOpEffect *op_ASSIGN_22 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, op_ASSIGN_18, op_ASSIGN_21); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, op_ASSIGN_18, EMPTY(), op_ASSIGN_22); return instruction_sequence; } @@ -747,7 +747,7 @@ RzILOpEffect *hex_il_op_l4_loadalignb_ur(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_22 = LOGOR(op_RSHIFT_19, op_LSHIFT_21); RzILOpEffect *op_ASSIGN_24 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_22)); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, op_ASSIGN_24, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, op_ASSIGN_24); return instruction_sequence; } @@ -887,9 +887,9 @@ RzILOpEffect *hex_il_op_l4_loadbsw2_ap(HexInsnPktBundle *bundle) { RzILOpEffect *seq_48 = SEQN(2, op_ASSIGN_11, for_47); // Re = ((st32) U); - RzILOpEffect *op_ASSIGN_51 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); + RzILOpEffect *op_ASSIGN_52 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, seq_48, op_ASSIGN_51); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, seq_48, EMPTY(), op_ASSIGN_52); return instruction_sequence; } @@ -961,7 +961,7 @@ RzILOpEffect *hex_il_op_l4_loadbsw2_ur(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp225; Rd = ((st32) ...; RzILOpEffect *seq_54 = SEQN(2, op_ASSIGN_17, for_53); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, seq_54); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, seq_54, EMPTY()); return instruction_sequence; } @@ -1027,9 +1027,9 @@ RzILOpEffect *hex_il_op_l4_loadbsw4_ap(HexInsnPktBundle *bundle) { RzILOpEffect *seq_47 = SEQN(2, op_ASSIGN_11, for_46); // Re = ((st32) U); - RzILOpEffect *op_ASSIGN_50 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); + RzILOpEffect *op_ASSIGN_51 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, seq_47, op_ASSIGN_50); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, seq_47, EMPTY(), op_ASSIGN_51); return instruction_sequence; } @@ -1101,7 +1101,7 @@ RzILOpEffect *hex_il_op_l4_loadbsw4_ur(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp227; Rdd = ((st64) ...; RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_17, for_52); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, seq_53, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, seq_53); return instruction_sequence; } @@ -1241,7 +1241,7 @@ RzILOpEffect *hex_il_op_l4_loadbzw2_ur(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp229; Rd = ((st32) ...; RzILOpEffect *seq_54 = SEQN(2, op_ASSIGN_17, for_53); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, seq_54); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, seq_54, EMPTY()); return instruction_sequence; } diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L6_ops.c index c4ca2d32486..28bc379a31d 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L6_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M2_ops.c index 31df93c966c..08af3e6ab69 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M2_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M4_ops.c index bf3fc2b5855..89941d1da2a 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M4_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M5_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M5_ops.c index 151b1bfa53b..22b24a5d3d1 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M5_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M5_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M6_ops.c index 68595581f19..ad31d0f609b 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M6_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M7_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M7_ops.c index 0f0a149c801..a44bdf1f8c9 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M7_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M7_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_R6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_R6_ops.c index 7398c53de8f..3c30b36a6e3 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_R6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_R6_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S2_ops.c index 312f6647a58..4409b476b1f 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S2_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S4_ops.c index a946ef2620f..6a590c3aafc 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S4_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S5_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S5_ops.c index 4f1a272db16..2d801b5b26b 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S5_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S5_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S6_ops.c index 541205cc1bc..7d6b7fe7b9c 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S6_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SA1_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SA1_ops.c index 240aee2a3eb..4f4f0ed90dc 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SA1_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SA1_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL1_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL1_ops.c index 491c0bf559f..fb3903a60c0 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL1_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL1_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL2_ops.c index 8ae27e4b5c4..5e06c46c9ef 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL2_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS1_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS1_ops.c index 64370195b82..3ac377f4a6a 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS1_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS1_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS2_ops.c index d1a4fbbc821..4a78e8dc6f2 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS2_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_UNDOCUMENTED_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_UNDOCUMENTED_ops.c index 221cecc3016..261274fee69 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_UNDOCUMENTED_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_UNDOCUMENTED_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_V6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_V6_ops.c index d94e47bc265..03509d66c51 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_V6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_V6_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y2_ops.c index b16773a2fd5..b346601e91e 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y2_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y4_ops.c index 25889174f45..0f8241b201c 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y4_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y5_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y5_ops.c index 1abb6202005..ca0e3950f55 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y5_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y5_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y6_ops.c index 6fcaa8098e0..a078da0c6e9 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y6_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_dep_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_dep_ops.c index b209b2fc51b..38aca4f81d3 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_dep_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_dep_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_invalid_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_invalid_ops.c index 5523f3eaa1a..9f3e6e8719c 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_invalid_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_invalid_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_non_insn_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_non_insn_ops.c index d455fe1a4b6..6a17be46467 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_non_insn_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_non_insn_ops.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/hexagon_dwarf_reg_num_table.inc b/librz/analysis/hexagon_dwarf_reg_num_table.inc index a833bf997b4..04e0b4dea6d 100644 --- a/librz/analysis/hexagon_dwarf_reg_num_table.inc +++ b/librz/analysis/hexagon_dwarf_reg_num_table.inc @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/p/analysis_hexagon.c b/librz/analysis/p/analysis_hexagon.c index 0756cfa0c1a..35e7ea62a09 100644 --- a/librz/analysis/p/analysis_hexagon.c +++ b/librz/analysis/p/analysis_hexagon.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/asm/arch/hexagon/hexagon.c b/librz/asm/arch/hexagon/hexagon.c index 24d57956f9f..0bcacc819ca 100644 --- a/librz/asm/arch/hexagon/hexagon.c +++ b/librz/asm/arch/hexagon/hexagon.c @@ -3,13 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 -// SPDX-FileCopyrightText: 2021 Rot127 -// SPDX-License-Identifier: LGPL-3.0-only - -// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c -// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -57,8 +51,8 @@ RZ_API ut32 hex_resolve_reg_enum_id(HexRegClass class, ut32 reg_num) { const char *hex_get_ctr_regs(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_ctrregs_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_ctr_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_ctr_regs", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_ctrregs_lt_v69[reg_num]; @@ -68,16 +62,16 @@ const char *hex_get_ctr_regs(int reg_num, bool get_alias, bool get_new, bool reg name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_ctr_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_ctr_regs", reg_num); + return NULL; } return name; } const char *hex_get_ctr_regs64(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_ctrregs64_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_ctr_regs64", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_ctr_regs64", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_ctrregs64_lt_v69[reg_num]; @@ -87,16 +81,16 @@ const char *hex_get_ctr_regs64(int reg_num, bool get_alias, bool get_new, bool r name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_ctr_regs64", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_ctr_regs64", reg_num); + return NULL; } return name; } const char *hex_get_double_regs(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_doubleregs_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_double_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_double_regs", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_doubleregs_lt_v69[reg_num]; @@ -106,8 +100,8 @@ const char *hex_get_double_regs(int reg_num, bool get_alias, bool get_new, bool name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_double_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_double_regs", reg_num); + return NULL; } return name; } @@ -115,8 +109,8 @@ const char *hex_get_double_regs(int reg_num, bool get_alias, bool get_new, bool const char *hex_get_general_double_low8_regs(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { reg_num = hex_resolve_reg_enum_id(HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS, reg_num); if (reg_num >= ARRAY_LEN(hexagon_generaldoublelow8regs_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_general_double_low8_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_general_double_low8_regs", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_generaldoublelow8regs_lt_v69[reg_num]; @@ -126,8 +120,8 @@ const char *hex_get_general_double_low8_regs(int reg_num, bool get_alias, bool g name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_general_double_low8_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_general_double_low8_regs", reg_num); + return NULL; } return name; } @@ -135,8 +129,8 @@ const char *hex_get_general_double_low8_regs(int reg_num, bool get_alias, bool g const char *hex_get_general_sub_regs(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { reg_num = hex_resolve_reg_enum_id(HEX_REG_CLASS_GENERAL_SUB_REGS, reg_num); if (reg_num >= ARRAY_LEN(hexagon_generalsubregs_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_general_sub_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_general_sub_regs", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_generalsubregs_lt_v69[reg_num]; @@ -146,16 +140,16 @@ const char *hex_get_general_sub_regs(int reg_num, bool get_alias, bool get_new, name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_general_sub_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_general_sub_regs", reg_num); + return NULL; } return name; } const char *hex_get_guest_regs(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_guestregs_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_guest_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_guest_regs", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_guestregs_lt_v69[reg_num]; @@ -165,16 +159,16 @@ const char *hex_get_guest_regs(int reg_num, bool get_alias, bool get_new, bool r name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_guest_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_guest_regs", reg_num); + return NULL; } return name; } const char *hex_get_guest_regs64(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_guestregs64_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_guest_regs64", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_guest_regs64", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_guestregs64_lt_v69[reg_num]; @@ -184,16 +178,16 @@ const char *hex_get_guest_regs64(int reg_num, bool get_alias, bool get_new, bool name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_guest_regs64", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_guest_regs64", reg_num); + return NULL; } return name; } const char *hex_get_hvx_qr(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_hvxqr_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_hvx_qr", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_hvx_qr", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_hvxqr_lt_v69[reg_num]; @@ -203,16 +197,16 @@ const char *hex_get_hvx_qr(int reg_num, bool get_alias, bool get_new, bool reg_n name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_hvx_qr", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_hvx_qr", reg_num); + return NULL; } return name; } const char *hex_get_hvx_vqr(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_hvxvqr_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_hvx_vqr", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_hvx_vqr", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_hvxvqr_lt_v69[reg_num]; @@ -222,16 +216,16 @@ const char *hex_get_hvx_vqr(int reg_num, bool get_alias, bool get_new, bool reg_ name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_hvx_vqr", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_hvx_vqr", reg_num); + return NULL; } return name; } const char *hex_get_hvx_vr(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_hvxvr_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_hvx_vr", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_hvx_vr", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_hvxvr_lt_v69[reg_num]; @@ -241,16 +235,16 @@ const char *hex_get_hvx_vr(int reg_num, bool get_alias, bool get_new, bool reg_n name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_hvx_vr", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_hvx_vr", reg_num); + return NULL; } return name; } const char *hex_get_hvx_wr(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_hvxwr_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_hvx_wr", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_hvx_wr", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_hvxwr_lt_v69[reg_num]; @@ -260,16 +254,16 @@ const char *hex_get_hvx_wr(int reg_num, bool get_alias, bool get_new, bool reg_n name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_hvx_wr", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_hvx_wr", reg_num); + return NULL; } return name; } const char *hex_get_int_regs(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_intregs_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_int_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_int_regs", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_intregs_lt_v69[reg_num]; @@ -279,16 +273,16 @@ const char *hex_get_int_regs(int reg_num, bool get_alias, bool get_new, bool reg name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_int_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_int_regs", reg_num); + return NULL; } return name; } const char *hex_get_int_regs_low8(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_intregslow8_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_int_regs_low8", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_int_regs_low8", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_intregslow8_lt_v69[reg_num]; @@ -298,8 +292,8 @@ const char *hex_get_int_regs_low8(int reg_num, bool get_alias, bool get_new, boo name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_int_regs_low8", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_int_regs_low8", reg_num); + return NULL; } return name; } @@ -307,8 +301,8 @@ const char *hex_get_int_regs_low8(int reg_num, bool get_alias, bool get_new, boo const char *hex_get_mod_regs(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { reg_num = hex_resolve_reg_enum_id(HEX_REG_CLASS_MOD_REGS, reg_num); if (reg_num >= ARRAY_LEN(hexagon_modregs_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_mod_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_mod_regs", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_modregs_lt_v69[reg_num]; @@ -318,16 +312,16 @@ const char *hex_get_mod_regs(int reg_num, bool get_alias, bool get_new, bool reg name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_mod_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_mod_regs", reg_num); + return NULL; } return name; } const char *hex_get_pred_regs(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_predregs_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_pred_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_pred_regs", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_predregs_lt_v69[reg_num]; @@ -337,16 +331,16 @@ const char *hex_get_pred_regs(int reg_num, bool get_alias, bool get_new, bool re name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_pred_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_pred_regs", reg_num); + return NULL; } return name; } const char *hex_get_sys_regs(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_sysregs_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_sys_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_sys_regs", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_sysregs_lt_v69[reg_num]; @@ -356,16 +350,16 @@ const char *hex_get_sys_regs(int reg_num, bool get_alias, bool get_new, bool reg name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_sys_regs", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_sys_regs", reg_num); + return NULL; } return name; } const char *hex_get_sys_regs64(int reg_num, bool get_alias, bool get_new, bool reg_num_is_enum) { if (reg_num >= ARRAY_LEN(hexagon_sysregs64_lt_v69)) { - RZ_LOG_WARN("%s: Index out of range during register name lookup: i = %d\n", "hex_get_sys_regs64", reg_num); - return ""; + RZ_LOG_INFO("%s: Index out of range during register name lookup: i = %d\n", "hex_get_sys_regs64", reg_num); + return NULL; } const char *name; const HexRegNames rn = hexagon_sysregs64_lt_v69[reg_num]; @@ -375,8 +369,8 @@ const char *hex_get_sys_regs64(int reg_num, bool get_alias, bool get_new, bool r name = get_new ? rn.name_tmp : rn.name; } if (!name) { - RZ_LOG_WARN("%s: No register name present at index: %d\n", "hex_get_sys_regs64", reg_num); - return ""; + RZ_LOG_INFO("%s: No register name present at index: %d\n", "hex_get_sys_regs64", reg_num); + return NULL; } return name; } diff --git a/librz/asm/arch/hexagon/hexagon.h b/librz/asm/arch/hexagon/hexagon.h index 7ee2e7cc0b4..9389af482e1 100644 --- a/librz/asm/arch/hexagon/hexagon.h +++ b/librz/asm/arch/hexagon/hexagon.h @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/asm/arch/hexagon/hexagon_arch.c b/librz/asm/arch/hexagon/hexagon_arch.c index 08bf31fa90e..5fbc5ff370d 100644 --- a/librz/asm/arch/hexagon/hexagon_arch.c +++ b/librz/asm/arch/hexagon/hexagon_arch.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/asm/arch/hexagon/hexagon_arch.h b/librz/asm/arch/hexagon/hexagon_arch.h index 697009c96ad..f70da5a5ac9 100644 --- a/librz/asm/arch/hexagon/hexagon_arch.h +++ b/librz/asm/arch/hexagon/hexagon_arch.h @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/asm/arch/hexagon/hexagon_disas.c b/librz/asm/arch/hexagon/hexagon_disas.c index 3caa5ea8ce2..7da160d9f33 100644 --- a/librz/asm/arch/hexagon/hexagon_disas.c +++ b/librz/asm/arch/hexagon/hexagon_disas.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -34139,7 +34139,13 @@ static void hex_disasm_with_templates(const HexInsnTemplate *tpl, HexState *stat if (op->info & HEX_OP_TEMPLATE_FLAG_REG_N_REG) { regidx = resolve_n_register(hi->ops[i].op.reg, hic->addr, pkt); } - rz_strbuf_append(&sb, hex_get_reg_in_class(op->reg_cls, regidx, print_reg_alias, false, false)); + const char *reg_name = hex_get_reg_in_class(op->reg_cls, regidx, print_reg_alias, false, false); + if (!reg_name) { + rz_strbuf_append(&sb, ""); + hi->identifier = HEX_INS_INVALID_DECODE; + } else { + rz_strbuf_append(&sb, reg_name); + } break; default: rz_warn_if_reached(); diff --git a/librz/asm/arch/hexagon/hexagon_insn.h b/librz/asm/arch/hexagon/hexagon_insn.h index 813b856980a..83300fddf36 100644 --- a/librz/asm/arch/hexagon/hexagon_insn.h +++ b/librz/asm/arch/hexagon/hexagon_insn.h @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/asm/arch/hexagon/hexagon_reg_tables.h b/librz/asm/arch/hexagon/hexagon_reg_tables.h index dfa52255a15..72d86a0aa03 100644 --- a/librz/asm/arch/hexagon/hexagon_reg_tables.h +++ b/librz/asm/arch/hexagon/hexagon_reg_tables.h @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/asm/p/asm_hexagon.c b/librz/asm/p/asm_hexagon.c index 4f000453342..aaa5a2591fe 100644 --- a/librz/asm/p/asm_hexagon.c +++ b/librz/asm/p/asm_hexagon.c @@ -3,13 +3,13 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-21 15:00:15-05:00 +// Date of code generation: 2023-11-21 20:07:05-05:00 // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 19:58:03-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/test/db/asm/hexagon b/test/db/asm/hexagon index 8f727aeee00..f85ee0b5aac 100644 --- a/test/db/asm/hexagon +++ b/test/db/asm/hexagon @@ -108,4 +108,4 @@ d "? l2invidx(R22)" 00c056a6 0x0 d "? l2fetch(R19,R1:0)" 00c093a6 0x0 d "? l2cleanidx(R20)" 00c034a6 0x0 d "? R12 = ctlbw(R7:6,R6)" 0cc6c66c 0x0 -d "? l2fetch(R24,R13)" 00cd18a6 0x0 +d "? l2fetch(R24,R13)" 00cd18a6 0x0 \ No newline at end of file