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@Rot127
Rot127 committed Nov 21, 2023
1 parent 162d5ff commit 662e4d5
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14 changes: 9 additions & 5 deletions librz/analysis/arch/hexagon/hexagon_il.c
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Expand Up @@ -3,7 +3,7 @@

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-17 15:27:57-05:00
// Date of code generation: 2023-11-21 15:00:15-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
Expand Down Expand Up @@ -643,13 +643,17 @@ static inline bool read_cond_faulty(RzILOpPure *low_val, RzILOpPure *high_val, u
}

/**
* \brief Checks for rw registers (e.g. Rx) if read and writes overlap.
* \brief Checks for rw registers (e.g. Rx) if reads and writes overlap.
*
* \returns true If the register is a "x" register and the read and write flag was set.
* \returns false Otherwise.
* \param pkt The packet of the current instruction.
* \param op The operand to check.
* \param reg_num The number of the register to check.
*
* \return true If the register is a "x" register and it was read and written before.
* \return false Otherwise.
*/
static bool x_reg_rw_overlap(const HexPkt *pkt, const HexOp *op, ut32 reg_num) {
switch(op->class) {
switch (op->class) {
default:
rz_warn_if_reached();
RZ_LOG_WARN("Checking rw overlap of class %d not implemented yet.", op->class);
Expand Down
6 changes: 6 additions & 0 deletions librz/analysis/arch/hexagon/hexagon_il.h
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@@ -1,6 +1,12 @@
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-21 15:00:15-05:00
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-17 15:27:57-05:00
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6 changes: 6 additions & 0 deletions librz/analysis/arch/hexagon/hexagon_il_getter_table.h
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@@ -1,6 +1,12 @@
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-21 15:00:15-05:00
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-17 15:27:57-05:00
Expand Down
100 changes: 50 additions & 50 deletions librz/analysis/arch/hexagon/il_ops/hexagon_il_A2_ops.c
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Expand Up @@ -3,7 +3,7 @@

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-17 15:27:57-05:00
// Date of code generation: 2023-11-21 15:00:15-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
Expand Down Expand Up @@ -756,7 +756,7 @@ RzILOpEffect *hex_il_op_a2_addpsat(HexInsnPktBundle *bundle) {
RzILOpPure *op_AND_17 = LOGAND(VARL("__xor"), VARL("__mask"));
RzILOpEffect *branch_44 = BRANCH(NON_ZERO(op_AND_17), seq_then_42, seq_else_43);

RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_3, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_44, EMPTY());
RzILOpEffect *instruction_sequence = SEQN(6, op_ASSIGN_3, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_44);
return instruction_sequence;
}

Expand Down Expand Up @@ -2328,11 +2328,11 @@ RzILOpEffect *hex_il_op_a2_roundsat(HexInsnPktBundle *bundle) {
RzILOpEffect *branch_43 = BRANCH(NON_ZERO(op_AND_17), seq_then_41, seq_else_42);

// Rd = ((st32) ((st64) ((st32) ((tmp >> 0x20) & 0xffffffff))));
RzILOpPure *op_RSHIFT_48 = SHIFTRA(VARL("tmp"), SN(32, 0x20));
RzILOpPure *op_AND_50 = LOGAND(op_RSHIFT_48, SN(64, 0xffffffff));
RzILOpEffect *op_ASSIGN_54 = WRITE_REG(bundle, Rd_op, CAST(32, MSB(CAST(64, MSB(CAST(32, MSB(op_AND_50), DUP(op_AND_50))), CAST(32, MSB(DUP(op_AND_50)), DUP(op_AND_50)))), CAST(64, MSB(CAST(32, MSB(DUP(op_AND_50)), DUP(op_AND_50))), CAST(32, MSB(DUP(op_AND_50)), DUP(op_AND_50)))));
RzILOpPure *op_RSHIFT_49 = SHIFTRA(VARL("tmp"), SN(32, 0x20));
RzILOpPure *op_AND_51 = LOGAND(op_RSHIFT_49, SN(64, 0xffffffff));
RzILOpEffect *op_ASSIGN_55 = WRITE_REG(bundle, Rd_op, CAST(32, MSB(CAST(64, MSB(CAST(32, MSB(op_AND_51), DUP(op_AND_51))), CAST(32, MSB(DUP(op_AND_51)), DUP(op_AND_51)))), CAST(64, MSB(CAST(32, MSB(DUP(op_AND_51)), DUP(op_AND_51))), CAST(32, MSB(DUP(op_AND_51)), DUP(op_AND_51)))));

RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_4, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_43, op_ASSIGN_54);
RzILOpEffect *instruction_sequence = SEQN(8, op_ASSIGN_4, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_43, EMPTY(), op_ASSIGN_55);
return instruction_sequence;
}

Expand Down Expand Up @@ -6185,45 +6185,45 @@ RzILOpEffect *hex_il_op_a2_vcmpweq(HexInsnPktBundle *bundle) {
RzILOpEffect *seq_44 = SEQN(2, op_ASSIGN_2, for_43);

// j = 0x4;
RzILOpEffect *op_ASSIGN_46 = SETL("j", SN(32, 4));
RzILOpEffect *op_ASSIGN_47 = SETL("j", SN(32, 4));

// HYB(++j);
RzILOpEffect *op_INC_49 = SETL("j", INC(VARL("j"), 32));
RzILOpEffect *op_INC_50 = SETL("j", INC(VARL("j"), 32));

// h_tmp69 = HYB(++j);
RzILOpEffect *op_ASSIGN_hybrid_tmp_51 = SETL("h_tmp69", VARL("j"));
RzILOpEffect *op_ASSIGN_hybrid_tmp_52 = SETL("h_tmp69", VARL("j"));

// seq(h_tmp69 = HYB(++j); HYB(++j));
RzILOpEffect *seq_52 = SEQN(2, op_ASSIGN_hybrid_tmp_51, op_INC_49);
RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_hybrid_tmp_52, op_INC_50);

// Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) | (((((st64) ((st32) ((Rss >> 0x20) & 0xffffffff))) == ((st64) ((st32) ((Rtt >> 0x20) & 0xffffffff)))) ? 0x1 : 0x0) << j)));
RzILOpPure *op_LSHIFT_54 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_55 = LOGNOT(op_LSHIFT_54);
RzILOpPure *op_AND_58 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_55);
RzILOpPure *op_RSHIFT_62 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_64 = LOGAND(op_RSHIFT_62, SN(64, 0xffffffff));
RzILOpPure *op_RSHIFT_70 = SHIFTRA(DUP(Rtt), SN(32, 0x20));
RzILOpPure *op_AND_72 = LOGAND(op_RSHIFT_70, SN(64, 0xffffffff));
RzILOpPure *op_EQ_75 = EQ(CAST(64, MSB(CAST(32, MSB(op_AND_64), DUP(op_AND_64))), CAST(32, MSB(DUP(op_AND_64)), DUP(op_AND_64))), CAST(64, MSB(CAST(32, MSB(op_AND_72), DUP(op_AND_72))), CAST(32, MSB(DUP(op_AND_72)), DUP(op_AND_72))));
RzILOpPure *ite_cast_ut64_76 = ITE(op_EQ_75, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_77 = SHIFTL0(ite_cast_ut64_76, VARL("j"));
RzILOpPure *op_OR_78 = LOGOR(op_AND_58, op_LSHIFT_77);
RzILOpEffect *op_ASSIGN_80 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_78));
RzILOpPure *op_LSHIFT_55 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_56 = LOGNOT(op_LSHIFT_55);
RzILOpPure *op_AND_59 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_56);
RzILOpPure *op_RSHIFT_63 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_65 = LOGAND(op_RSHIFT_63, SN(64, 0xffffffff));
RzILOpPure *op_RSHIFT_71 = SHIFTRA(DUP(Rtt), SN(32, 0x20));
RzILOpPure *op_AND_73 = LOGAND(op_RSHIFT_71, SN(64, 0xffffffff));
RzILOpPure *op_EQ_76 = EQ(CAST(64, MSB(CAST(32, MSB(op_AND_65), DUP(op_AND_65))), CAST(32, MSB(DUP(op_AND_65)), DUP(op_AND_65))), CAST(64, MSB(CAST(32, MSB(op_AND_73), DUP(op_AND_73))), CAST(32, MSB(DUP(op_AND_73)), DUP(op_AND_73))));
RzILOpPure *ite_cast_ut64_77 = ITE(op_EQ_76, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_78 = SHIFTL0(ite_cast_ut64_77, VARL("j"));
RzILOpPure *op_OR_79 = LOGOR(op_AND_59, op_LSHIFT_78);
RzILOpEffect *op_ASSIGN_81 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_79));

// seq(h_tmp69; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) ...;
RzILOpEffect *seq_82 = SEQN(2, op_ASSIGN_80, EMPTY());
RzILOpEffect *seq_83 = SEQN(2, op_ASSIGN_81, EMPTY());

// seq(seq(h_tmp69; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ...;
RzILOpEffect *seq_83 = SEQN(2, seq_82, seq_52);
RzILOpEffect *seq_84 = SEQN(2, seq_83, seq_53);

// while ((j <= 0x7)) { seq(seq(h_tmp69; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ... };
RzILOpPure *op_LE_48 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_84 = REPEAT(op_LE_48, seq_83);
RzILOpPure *op_LE_49 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_85 = REPEAT(op_LE_49, seq_84);

// seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp69; Pd = ((st8) ( ...;
RzILOpEffect *seq_85 = SEQN(2, op_ASSIGN_46, for_84);
RzILOpEffect *seq_86 = SEQN(2, op_ASSIGN_47, for_85);

RzILOpEffect *instruction_sequence = SEQN(3, seq_44, seq_85, EMPTY());
RzILOpEffect *instruction_sequence = SEQN(3, seq_44, EMPTY(), seq_86);
return instruction_sequence;
}

Expand Down Expand Up @@ -6279,45 +6279,45 @@ RzILOpEffect *hex_il_op_a2_vcmpwgt(HexInsnPktBundle *bundle) {
RzILOpEffect *seq_44 = SEQN(2, op_ASSIGN_2, for_43);

// j = 0x4;
RzILOpEffect *op_ASSIGN_47 = SETL("j", SN(32, 4));
RzILOpEffect *op_ASSIGN_46 = SETL("j", SN(32, 4));

// HYB(++j);
RzILOpEffect *op_INC_50 = SETL("j", INC(VARL("j"), 32));
RzILOpEffect *op_INC_49 = SETL("j", INC(VARL("j"), 32));

// h_tmp71 = HYB(++j);
RzILOpEffect *op_ASSIGN_hybrid_tmp_52 = SETL("h_tmp71", VARL("j"));
RzILOpEffect *op_ASSIGN_hybrid_tmp_51 = SETL("h_tmp71", VARL("j"));

// seq(h_tmp71 = HYB(++j); HYB(++j));
RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_hybrid_tmp_52, op_INC_50);
RzILOpEffect *seq_52 = SEQN(2, op_ASSIGN_hybrid_tmp_51, op_INC_49);

// Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) | (((((st64) ((st32) ((Rss >> 0x20) & 0xffffffff))) > ((st64) ((st32) ((Rtt >> 0x20) & 0xffffffff)))) ? 0x1 : 0x0) << j)));
RzILOpPure *op_LSHIFT_55 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_56 = LOGNOT(op_LSHIFT_55);
RzILOpPure *op_AND_59 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_56);
RzILOpPure *op_RSHIFT_63 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_65 = LOGAND(op_RSHIFT_63, SN(64, 0xffffffff));
RzILOpPure *op_RSHIFT_71 = SHIFTRA(DUP(Rtt), SN(32, 0x20));
RzILOpPure *op_AND_73 = LOGAND(op_RSHIFT_71, SN(64, 0xffffffff));
RzILOpPure *op_GT_76 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_65), DUP(op_AND_65))), CAST(32, MSB(DUP(op_AND_65)), DUP(op_AND_65))), CAST(64, MSB(CAST(32, MSB(op_AND_73), DUP(op_AND_73))), CAST(32, MSB(DUP(op_AND_73)), DUP(op_AND_73))));
RzILOpPure *ite_cast_ut64_77 = ITE(op_GT_76, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_78 = SHIFTL0(ite_cast_ut64_77, VARL("j"));
RzILOpPure *op_OR_79 = LOGOR(op_AND_59, op_LSHIFT_78);
RzILOpEffect *op_ASSIGN_81 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_79));
RzILOpPure *op_LSHIFT_54 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_55 = LOGNOT(op_LSHIFT_54);
RzILOpPure *op_AND_58 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_55);
RzILOpPure *op_RSHIFT_62 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_64 = LOGAND(op_RSHIFT_62, SN(64, 0xffffffff));
RzILOpPure *op_RSHIFT_70 = SHIFTRA(DUP(Rtt), SN(32, 0x20));
RzILOpPure *op_AND_72 = LOGAND(op_RSHIFT_70, SN(64, 0xffffffff));
RzILOpPure *op_GT_75 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_64), DUP(op_AND_64))), CAST(32, MSB(DUP(op_AND_64)), DUP(op_AND_64))), CAST(64, MSB(CAST(32, MSB(op_AND_72), DUP(op_AND_72))), CAST(32, MSB(DUP(op_AND_72)), DUP(op_AND_72))));
RzILOpPure *ite_cast_ut64_76 = ITE(op_GT_75, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_77 = SHIFTL0(ite_cast_ut64_76, VARL("j"));
RzILOpPure *op_OR_78 = LOGOR(op_AND_58, op_LSHIFT_77);
RzILOpEffect *op_ASSIGN_80 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_78));

// seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) ...;
RzILOpEffect *seq_83 = SEQN(2, op_ASSIGN_81, EMPTY());
RzILOpEffect *seq_82 = SEQN(2, op_ASSIGN_80, EMPTY());

// seq(seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ...;
RzILOpEffect *seq_84 = SEQN(2, seq_83, seq_53);
RzILOpEffect *seq_83 = SEQN(2, seq_82, seq_52);

// while ((j <= 0x7)) { seq(seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ... };
RzILOpPure *op_LE_49 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_85 = REPEAT(op_LE_49, seq_84);
RzILOpPure *op_LE_48 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_84 = REPEAT(op_LE_48, seq_83);

// seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp71; Pd = ((st8) ( ...;
RzILOpEffect *seq_86 = SEQN(2, op_ASSIGN_47, for_85);
RzILOpEffect *seq_85 = SEQN(2, op_ASSIGN_46, for_84);

RzILOpEffect *instruction_sequence = SEQN(3, seq_44, EMPTY(), seq_86);
RzILOpEffect *instruction_sequence = SEQN(2, seq_44, seq_85);
return instruction_sequence;
}

Expand Down
44 changes: 22 additions & 22 deletions librz/analysis/arch/hexagon/il_ops/hexagon_il_A4_ops.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-17 15:27:57-05:00
// Date of code generation: 2023-11-21 15:00:15-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
Expand Down Expand Up @@ -2475,43 +2475,43 @@ RzILOpEffect *hex_il_op_a4_vcmpweqi(HexInsnPktBundle *bundle) {
RzILOpEffect *seq_38 = SEQN(2, op_ASSIGN_2, for_37);

// j = 0x4;
RzILOpEffect *op_ASSIGN_40 = SETL("j", SN(32, 4));
RzILOpEffect *op_ASSIGN_41 = SETL("j", SN(32, 4));

// HYB(++j);
RzILOpEffect *op_INC_43 = SETL("j", INC(VARL("j"), 32));
RzILOpEffect *op_INC_44 = SETL("j", INC(VARL("j"), 32));

// h_tmp134 = HYB(++j);
RzILOpEffect *op_ASSIGN_hybrid_tmp_45 = SETL("h_tmp134", VARL("j"));
RzILOpEffect *op_ASSIGN_hybrid_tmp_46 = SETL("h_tmp134", VARL("j"));

// seq(h_tmp134 = HYB(++j); HYB(++j));
RzILOpEffect *seq_46 = SEQN(2, op_ASSIGN_hybrid_tmp_45, op_INC_43);
RzILOpEffect *seq_47 = SEQN(2, op_ASSIGN_hybrid_tmp_46, op_INC_44);

// Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) | (((((st64) ((st32) ((Rss >> 0x20) & 0xffffffff))) == ((st64) s)) ? 0x1 : 0x0) << j)));
RzILOpPure *op_LSHIFT_48 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_49 = LOGNOT(op_LSHIFT_48);
RzILOpPure *op_AND_52 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_49);
RzILOpPure *op_RSHIFT_56 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_58 = LOGAND(op_RSHIFT_56, SN(64, 0xffffffff));
RzILOpPure *op_EQ_62 = EQ(CAST(64, MSB(CAST(32, MSB(op_AND_58), DUP(op_AND_58))), CAST(32, MSB(DUP(op_AND_58)), DUP(op_AND_58))), CAST(64, MSB(VARL("s")), VARL("s")));
RzILOpPure *ite_cast_ut64_63 = ITE(op_EQ_62, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_64 = SHIFTL0(ite_cast_ut64_63, VARL("j"));
RzILOpPure *op_OR_65 = LOGOR(op_AND_52, op_LSHIFT_64);
RzILOpEffect *op_ASSIGN_67 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_65));
RzILOpPure *op_LSHIFT_49 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_50 = LOGNOT(op_LSHIFT_49);
RzILOpPure *op_AND_53 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_50);
RzILOpPure *op_RSHIFT_57 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_59 = LOGAND(op_RSHIFT_57, SN(64, 0xffffffff));
RzILOpPure *op_EQ_63 = EQ(CAST(64, MSB(CAST(32, MSB(op_AND_59), DUP(op_AND_59))), CAST(32, MSB(DUP(op_AND_59)), DUP(op_AND_59))), CAST(64, MSB(VARL("s")), VARL("s")));
RzILOpPure *ite_cast_ut64_64 = ITE(op_EQ_63, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_65 = SHIFTL0(ite_cast_ut64_64, VARL("j"));
RzILOpPure *op_OR_66 = LOGOR(op_AND_53, op_LSHIFT_65);
RzILOpEffect *op_ASSIGN_68 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_66));

// seq(h_tmp134; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j)) ...;
RzILOpEffect *seq_69 = SEQN(2, op_ASSIGN_67, EMPTY());
RzILOpEffect *seq_70 = SEQN(2, op_ASSIGN_68, EMPTY());

// seq(seq(h_tmp134; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ...;
RzILOpEffect *seq_70 = SEQN(2, seq_69, seq_46);
RzILOpEffect *seq_71 = SEQN(2, seq_70, seq_47);

// while ((j <= 0x7)) { seq(seq(h_tmp134; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ... };
RzILOpPure *op_LE_42 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_71 = REPEAT(op_LE_42, seq_70);
RzILOpPure *op_LE_43 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_72 = REPEAT(op_LE_43, seq_71);

// seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp134; Pd = ((st8) ...;
RzILOpEffect *seq_72 = SEQN(2, op_ASSIGN_40, for_71);
RzILOpEffect *seq_73 = SEQN(2, op_ASSIGN_41, for_72);

RzILOpEffect *instruction_sequence = SEQN(4, imm_assign_25, seq_38, seq_72, EMPTY());
RzILOpEffect *instruction_sequence = SEQN(5, imm_assign_25, seq_38, EMPTY(), seq_73, EMPTY());
return instruction_sequence;
}

Expand Down Expand Up @@ -2695,7 +2695,7 @@ RzILOpEffect *hex_il_op_a4_vcmpwgtui(HexInsnPktBundle *bundle) {
// seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp138; Pd = ((st8) ...;
RzILOpEffect *seq_72 = SEQN(2, op_ASSIGN_40, for_71);

RzILOpEffect *instruction_sequence = SEQN(3, imm_assign_25, seq_38, seq_72);
RzILOpEffect *instruction_sequence = SEQN(4, imm_assign_25, seq_38, seq_72, EMPTY());
return instruction_sequence;
}

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6 changes: 6 additions & 0 deletions librz/analysis/arch/hexagon/il_ops/hexagon_il_A5_ops.c
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@@ -1,6 +1,12 @@
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-21 15:00:15-05:00
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-17 15:27:57-05:00
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6 changes: 6 additions & 0 deletions librz/analysis/arch/hexagon/il_ops/hexagon_il_A6_ops.c
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@@ -1,6 +1,12 @@
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-21 15:00:15-05:00
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-17 15:27:57-05:00
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6 changes: 6 additions & 0 deletions librz/analysis/arch/hexagon/il_ops/hexagon_il_A7_ops.c
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@@ -1,6 +1,12 @@
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-21 15:00:15-05:00
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-17 15:27:57-05:00
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6 changes: 6 additions & 0 deletions librz/analysis/arch/hexagon/il_ops/hexagon_il_C2_ops.c
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@@ -1,6 +1,12 @@
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-21 15:00:15-05:00
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-17 15:27:57-05:00
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6 changes: 6 additions & 0 deletions librz/analysis/arch/hexagon/il_ops/hexagon_il_C4_ops.c
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Original file line number Diff line number Diff line change
@@ -1,6 +1,12 @@
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-21 15:00:15-05:00
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2023-11-17 15:27:57-05:00
Expand Down
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