From 8f04ca800ca13c2df6623ec88bc7c99f762af0ec Mon Sep 17 00:00:00 2001 From: billow Date: Fri, 2 Jun 2023 09:45:00 +0800 Subject: [PATCH] Update capstone and tests --- subprojects/capstone-next.wrap | 2 +- test/db/analysis/golang | 4 +- test/db/analysis/tricore | 766 ++++++++++++++++++++++++++++++--- test/db/analysis/vars | 144 ++++--- test/db/analysis/x86_64 | 4 + test/db/asm/x86_16 | 2 +- test/db/asm/x86_32 | 2 +- test/db/asm/x86_64 | 12 +- test/db/cmd/cmd_a8 | 2 +- test/db/cmd/cmd_a_capital_o | 2 +- test/db/cmd/cmd_ao | 2 +- test/db/cmd/cmd_list | 8 +- test/db/formats/mach0/imports | 1 + test/db/rzil/ppc32 | 1 + test/db/tools/rz | 1 + 15 files changed, 827 insertions(+), 126 deletions(-) diff --git a/subprojects/capstone-next.wrap b/subprojects/capstone-next.wrap index b06aa21d221..05deade5095 100644 --- a/subprojects/capstone-next.wrap +++ b/subprojects/capstone-next.wrap @@ -1,5 +1,5 @@ [wrap-git] url = https://github.com/capstone-engine/capstone.git -revision = 7729902a56fafd971bebba7776f594172027a8bf +revision = 53e68142050957e278d1a7f31b6ab52cbe9bed26 directory = capstone-next patch_directory = capstone-next diff --git a/test/db/analysis/golang b/test/db/analysis/golang index 5b8b9a347dd..d70edf2789b 100644 --- a/test/db/analysis/golang +++ b/test/db/analysis/golang @@ -131,7 +131,7 @@ EXPECT=< ; load effective address - 0x80000028 7b00000d movh d0, 53248 ; move high - 0x8000002c 1b008200 addi d0, d0, 2080 ; add immediate - 0x80000030 cd80e20f mtcr #0xfe28, d0 ; move to core register - 0x80000034 0d00c004 isync ; synchronize instructions - 0x80000038 7b000008 movh d0, 32768 ; move high - 0x8000003c 1b003000 addi d0, d0, 768 ; add immediate - 0x80000040 cd40e20f mtcr #0xfe24, d0 ; move to core register - 0x80000044 0d00c004 isync ; synchronize instructions - 0x80000048 4d40e00f mfcr d0, #0xfe04 ; move from core register - 0x8000004c 8ff04701 or d0, d0, 127 ; bitwise or - 0x80000050 8f00c801 andn d0, d0, 128 - 0x80000054 cd40e00f mtcr #0xfe04, d0 ; move to core register - 0x80000058 0d00c004 isync ; synchronize instructions - 0x8000005c 4d40e00f mfcr d0, #0xfe04 ; move from core register - 0x80000060 8f005001 or d0, d0, 256 ; bitwise or - 0x80000064 cd40e00f mtcr #0xfe04, d0 ; move to core register - 0x80000068 0d00c004 isync ; synchronize instructions + 0x80000014 85f12000 ld.w d1, #0xf0000020 ; load word + ,=< 0x80000018 6f010400 jz.t d1, #0, #0x80000020 ; jump if zero bit + ,==< 0x8000001c 5d006800 jl #0x800000ec ; jump and link + || 0x80000020 910000ad movh.a sp, #0xd000 ; move high to address + || 0x80000024 d9aa6000 lea sp, [sp]#0x420 ; load effective address + || 0x80000028 7b00000d movh d0, #0xd000 ; move high + || 0x8000002c 1b008200 addi d0, d0, #0x820 ; add immediate + || 0x80000030 cd80e20f mtcr #-0x1d8, d0 ; move to core register + || 0x80000034 0d00c004 isync ; synchronize instructions + || 0x80000038 7b000008 movh d0, #0x8000 ; move high + || 0x8000003c 1b003000 addi d0, d0, #0x300 ; add immediate + || 0x80000040 cd40e20f mtcr #-0x1dc, d0 ; move to core register + || 0x80000044 0d00c004 isync ; synchronize instructions + || 0x80000048 4d40e00f mfcr d0, #0xfe04 ; move from core register + || 0x8000004c 8ff04701 or d0, d0, #0x7f ; bitwise or + || 0x80000050 8f00c801 andn d0, d0, #0x80 + || 0x80000054 cd40e00f mtcr #-0x1fc, d0 ; move to core register + || 0x80000058 0d00c004 isync ; synchronize instructions + || 0x8000005c 4d40e00f mfcr d0, #0xfe04 ; move from core register + || 0x80000060 8f005001 or d0, d0, #0x100 ; bitwise or + || 0x80000064 cd40e00f mtcr #-0x1fc, d0 ; move to core register + || 0x80000068 0d00c004 isync ; synchronize instructions EOF RUN @@ -192,3 +192,673 @@ BTV = 0x00000000 pc = 0x00000000 EOF RUN + +NAME=tricore analysis elf +FILE=bins/tricore/ASCLIN_UART_1_KIT_TC397_TFT_stripped.elf +CMDS=< 424 fcn.800842f0 +0x80084158 7 408 -> 144 fcn.80084158 +0x80083efe 1 430 fcn.80083efe +0x80084d56 1 60 fcn.80084d56 +0x800830d8 39 3622 -> 3614 fcn.800830d8 +0x8008453e 7 300 fcn.8008453e +0x800844d6 1 104 fcn.800844d6 +0x800858fe 28 900 fcn.800858fe +0x8008807a 1 116 fcn.8008807a +0x80087dce 8 366 fcn.80087dce +0x800880ee 1 62 fcn.800880ee +0x80087f3c 8 318 fcn.80087f3c +0x80084e6a 1 46 fcn.80084e6a +0x80084d92 7 216 -> 212 fcn.80084d92 +0x800868b8 6 156 -> 64 fcn.800868b8 +0x80082d14 1 206 fcn.80082d14 +0x80082de2 1 84 fcn.80082de2 +0x8008466a 1 64 fcn.8008466a +0x80087c68 4 202 fcn.80087c68 +0x8008812c 5 200 fcn.8008812c +0x80084c90 6 120 fcn.80084c90 +0x800848c2 9 974 -> 694 fcn.800848c2 +0x80086210 3 226 fcn.80086210 +0x800862f2 1 158 fcn.800862f2 +0x80085668 1 212 fcn.80085668 +0x80085600 3 104 fcn.80085600 +0x8008a19c 2 16 fcn.8008a19c +0x80084828 1 38 fcn.80084828 +0x80084766 3 104 -> 38 fcn.80084766 +0x8008484e 1 36 fcn.8008484e +0x80084800 1 40 fcn.80084800 +0x80084d08 4 78 fcn.80084d08 +0x80084872 4 80 fcn.80084872 +0x80085e8c 28 900 fcn.80085e8c +0x800840ac 8 172 -> 134 fcn.800840ac +0x800864ea 4 174 -> 78 fcn.800864ea +0x800846aa 6 188 -> 70 fcn.800846aa +0x800847ce 1 50 fcn.800847ce +0x800895ae 2 1526 -> 80 fcn.800895ae +0x80089c20 7 122 -> 74 fcn.80089c20 +0x800897f4 3 420 -> 66 fcn.800897f4 +0x80089ba4 5 1078 -> 124 fcn.80089ba4 +0x80089dc2 13 172 -> 146 fcn.80089dc2 +0x8008573c 3 242 fcn.8008573c +0x800854bc 3 162 fcn.800854bc +0x8008582e 6 208 fcn.8008582e +0x80085c82 3 256 fcn.80085c82 +0x8008555e 3 162 fcn.8008555e +0x80085d82 6 266 fcn.80085d82 +0x8008977c 1 56 fcn.8008977c +0x8008957e 2 44 fcn.8008957e +0x80089ab0 3 64 fcn.80089ab0 +0x80089e6e 4 38 fcn.80089e6e +0x800897b4 1 64 fcn.800897b4 +0x80089b38 3 42 fcn.80089b38 +0x80089af0 3 72 -> 30 fcn.80089af0 +0x80089cb0 3 274 -> 54 fcn.80089cb0 +0x80089998 6 280 -> 94 fcn.80089998 +0x800867e0 5 216 -> 176 fcn.800867e0 +0x80086598 5 216 -> 176 fcn.80086598 +0x80086670 8 368 -> 328 fcn.80086670 +0x80087bb2 2 182 fcn.80087bb2 +0x80086390 5 346 -> 306 fcn.80086390 +0x80087d32 4 156 fcn.80087d32 +0x800881f4 5 154 fcn.800881f4 +0x8008828e 3 136 fcn.8008828e +0x80088316 3 136 fcn.80088316 +0x8008839e 3 148 fcn.8008839e +0x80088432 3 148 fcn.80088432 +0x80089fda 1 12 fcn.80089fda +0x8008a280 5 282 -> 44 fcn.8008a280 +0x8008a39c 2 38 fcn.8008a39c +0x8008a06c 3 58 fcn.8008a06c +0x8008a112 15 138 -> 124 fcn.8008a112 +0x800884c6 3 136 fcn.800884c6 +0x8008854e 3 148 fcn.8008854e +0x80086954 121 4702 -> 4162 fcn.80086954 +0x8008876e 3 124 fcn.8008876e +0x800885e2 1 146 fcn.800885e2 +0x80088706 1 52 fcn.80088706 +0x800888de 25 422 fcn.800888de +0x8008873a 1 52 fcn.8008873a +0x80088674 1 146 fcn.80088674 +0x800887ea 5 244 -> 212 fcn.800887ea +0x80089bfa 2 24 fcn.80089bfa +0x80089be0 2 14 fcn.80089be0 +0x800895e0 6 44 fcn.800895e0 +0x8008a3da 2 22 fcn.8008a3da +0x8008a73c 2 38 fcn.8008a73c +0x8008a3f0 14 156 -> 134 fcn.8008a3f0 +0x8008a48c 3 26 fcn.8008a48c +0x8008a3c2 3 16 fcn.8008a3c2 +0x8008a60a 4 52 fcn.8008a60a +0x8008a72c 4 16 -> 10 fcn.8008a72c +0x8008a4aa 4 170 -> 62 fcn.8008a4aa +0x8008a554 3 30 fcn.8008a554 +0x8008a686 3 56 fcn.8008a686 +0x80089fe6 3 134 fcn.80089fe6 +0x8008a6be 5 78 -> 74 fcn.8008a6be +0x8008a70c 2 24 -> 18 fcn.8008a70c +0x8008a790 1 10 fcn.8008a790 +0x8008a77a 3 38 -> 20 fcn.8008a77a +0x8008a572 4 38 fcn.8008a572 +0x8008a724 1 6 fcn.8008a724 +0x8008a78c 1 4 fcn.8008a78c + ;-- section..start_tc0: + ;-- segment.LOAD6: +/ entry0(); +| 0x80080020 movh.a a15, #0x8009 ; [18] -r-x section size 12 named .start_tc0 +| 0x80080024 lea a15, [a15]#-0x757c +\ 0x80080028 ji a15 + ; CALL XREF from section..text @ +0xc +/ fcn.800842f0(int32_t arg5); +| ; arg int32_t arg5 @ a4 +| 0x800842f0 mov.aa a14, sp +| 0x800842f2 sub.a sp, #0x68 +| 0x800842f4 st.a [a14]#-0x64, a4 ; arg5 +| 0x800842f8 mfcr d15, #0xfe2c +| 0x800842fc st.w [a14]#-8, d15 +| 0x80084300 ld.w d15, [a14]#-8 +| 0x80084304 st.w [a14]#-0x38, d15 +| 0x80084308 ld.w d15, [a14]#-0x38 +| 0x8008430c sh d15, d15, #-0xf +| 0x80084310 and d15, #1 +| 0x80084312 and d15, #0xff +| 0x80084314 st.b [a14]#-9, d15 +| 0x80084318 disable +| 0x8008431c nop +| 0x8008431e ld.bu d15, [a14]#-9 +| 0x80084322 st.b [a14]#-0xa, d15 +| 0x80084326 movh d15, #0xf000 +| 0x8008432a addi d15, d15, #0x1000 +| 0x8008432e st.w [a14]#-0x10, d15 +| 0x80084332 ld.w d15, [a14]#-0x10 +| 0x80084336 mov.a a15, d15 +| 0x80084338 ld.w d15, [a15]#0x10 +| 0x8008433a mul.u e2, d15, #1 +| 0x8008433e st.d [a14]#-0x18, e2 +| 0x80084342 ld.w d15, [a14]#-0x10 +| 0x80084346 mov.a a15, d15 +| 0x80084348 ld.w d15, [a15]#0x2c +| 0x8008434a mul.u e2, d15, #1 +| 0x8008434e mov d5, d2 +| 0x80084350 mov d4, #0 +| 0x80084352 ld.w d15, [a14]#-0x18 +| 0x80084356 or d15, d4 +| 0x80084358 st.w [a14]#-0x18, d15 +| 0x8008435c ld.w d15, [a14]#-0x14 +| 0x80084360 or d15, d5 +| 0x80084362 st.w [a14]#-0x14, d15 +| 0x80084366 ld.d e2, [a14]#-0x18 +| 0x8008436a mov d15, d2 +| 0x8008436c st.w [a14]#-0x20, d15 +| 0x80084370 mov d15, #-1 +| 0x80084372 sh d15, #-1 +| 0x80084374 and d15, d3 +| 0x80084376 st.w [a14]#-0x1c, d15 +| 0x8008437a ld.b d15, [a14]#-0xa +| 0x8008437e st.b [a14]#-0x21, d15 +| 0x80084382 ld.bu d15, [a14]#-0x21 +| ,=< 0x80084386 jz d15, #0x8008438c +| | 0x80084388 enable +| `-> 0x8008438c ld.d e2, [a14]#-0x20 +| 0x80084390 ld.w d15, [a14]#-0x64 +| 0x80084394 mov.a a15, d15 +| 0x80084396 st.d [a15]#0x18, e2 +| 0x8008439a ld.w d15, [a14]#-0x64 +| 0x8008439e mov.a a15, d15 +| 0x800843a0 ld.w d15, [a15]#0x14 +| 0x800843a2 add d2, d15, #1 +| 0x800843a4 ld.w d15, [a14]#-0x64 +| 0x800843a8 mov d3, d2 +| 0x800843aa mov.a a15, d15 +| 0x800843ac st.w [a15]#0x14, d3 ; 20 +| 0x800843ae ld.w d15, [a14]#-0x64 +| 0x800843b2 mov.a a15, d15 +| 0x800843b4 ld.w d15, [a15]#4 +| 0x800843b6 st.w [a14]#-0x28, d15 +| 0x800843ba ld.w d15, [a14]#-0x28 +| 0x800843be st.w [a14]#-0x2c, d15 +| 0x800843c2 ld.w d15, [a14]#-0x2c +| 0x800843c6 mov.a a15, d15 +| 0x800843c8 ld.h d15, [a15]#4 +| 0x800843ca eq d15, d15, #0 +| 0x800843cc and d15, #0xff +| ,=< 0x800843ce jnz d15, #0x800844ca +| | 0x800843d0 ld.w d15, [a14]#-0x64 +| | 0x800843d4 mov.a a15, d15 +| | 0x800843d6 ld.w d15, [a15]#0x10 +| ,==< 0x800843d8 jz d15, #0x800843e0 +| ,===< 0x800843da jeq d15, #1, #0x8008448a +| ,====< 0x800843de j #0x800844d4 +| ||`--> 0x800843e0 mov d15, #0 +| || | 0x800843e2 st.h [a14]#-4, d15 +| || | 0x800843e6 mov d15, #0 +| || | 0x800843e8 st.h [a14]#-2, d15 +| || | 0x800843ec mov d15, #0 +| || | 0x800843ee st.b [a14]#-0x49, d15 +| || | 0x800843f2 ld.w d15, [a14]#-0x64 +| || | 0x800843f6 mov.a a15, d15 +| || | 0x800843f8 ld.w d15, [a15]#4 +| || | 0x800843fa st.w [a14]#-0x30, d15 +| || | 0x800843fe ld.w d15, [a14]#-0x30 +| || | 0x80084402 mov.a a15, d15 +| || | 0x80084404 ld.h d15, [a15]#4 +| || | 0x80084406 st.h [a14]#-4, d15 +| || | 0x8008440a ld.w d15, [a14]#-0x64 +| || | 0x8008440e mov.a a15, d15 +| || | 0x80084410 ld.w d15, [a15]#0 +| || | 0x80084412 st.w [a14]#-0x34, d15 +| || | 0x80084416 ld.w d15, [a14]#-0x34 +| || | 0x8008441a mov.a a15, d15 +| || | 0x8008441c ld.w d15, [a15]#0xc +| || | 0x8008441e sh d15, d15, #-0x10 +| || | 0x80084422 and d15, #0x1f +| || | 0x80084424 and d15, #0xff +| || | 0x80084426 st.b [a14]#-0x49, d15 +| || | 0x8008442a ld.bu d15, [a14]#-0x49 +| || | 0x8008442e extr.u d15, d15, #0, #0x10 +| || | 0x80084432 rsub d15, d15, #0x10 +| || | 0x80084436 st.h [a14]#-2, d15 +| || | 0x8008443a ld.hu d15, [a14]#-2 +| || | 0x8008443e ld.hu d2, [a14]#-4 +| ||,==< 0x80084442 jge.u d2, d15, #0x8008444e +| |||| 0x80084446 ld.h d15, [a14]#-4 +| |||| 0x8008444a st.h [a14]#-2, d15 +| |||| 0x8008444e ld.w d15, [a14]#-0x64 +| |||| 0x80084452 mov.a a15, d15 +| |||| 0x80084454 ld.w d3, [a15]#4 +| |||| 0x80084456 ld.h d15, [a14]#-2 +| |||| 0x8008445a mov.d d4, a14 +| |||| 0x8008445c addi d2, d4, #-0x48 +| |||| 0x80084460 mov.a a4, d3 +| |||| 0x80084462 mov.a a5, d2 +| |||| 0x80084464 mov d4, d15 +| |||| 0x80084466 mov e6, #0 +| |||| 0x80084468 call #0x800858fe ; fcn.800858fe +| |||| 0x8008446c ld.w d15, [a14]#-0x64 +| |||| 0x80084470 mov.a a15, d15 +| |||| 0x80084472 ld.w d3, [a15]#0 +| |||| 0x80084474 ld.hu d15, [a14]#-2 +| |||| 0x80084478 mov.d d4, a14 +| |||| 0x8008447a addi d2, d4, #-0x48 +| |||| 0x8008447e mov.a a4, d3 +| |||| 0x80084480 mov.a a5, d2 +| |||| 0x80084482 mov d4, d15 +| |||| 0x80084484 call #0x80084d08 ; fcn.80084d08 +| ||,==< 0x80084488 j #0x800844c8 +.. +| | |||| ; CODE XREF from fcn.800842f0 @ 0x80084488 +| |,`--> 0x800844c8 j #0x800844d4 +| ||||`-> 0x800844ca ld.w d15, [a14]#-0x64 +| |||| 0x800844ce mov d2, #0 +| |||| 0x800844d0 mov.a a15, d15 +| |||| 0x800844d2 st.b [a15]#0xc, d2 ; 12 +| |||| ; CODE XREFS from fcn.800842f0 @ 0x800843de, 0x800844c8 +\ ``---> 0x800844d4 ret +EOF +RUN + +NAME=tricore analysis elf2 +FILE=bins/tricore/Blinky_LED_1_KIT_TC367_TFT.elf +CMDS=< 32 fcn.80000744 +0x80000456 2 98 fcn.80000456 +0x80000e46 1 14 fcn.80000e46 +0x80000ce4 1 10 fcn.80000ce4 +0x80000d60 1 16 fcn.80000d60 +0x80000cee 1 10 fcn.80000cee +0x80000dfe 1 10 fcn.80000dfe +0x80000cf8 2 20 fcn.80000cf8 +0x80000d22 2 22 fcn.80000d22 +0x80000d4e 1 10 fcn.80000d4e +0x80000d58 1 8 fcn.80000d58 +0x80000d70 1 10 fcn.80000d70 +0x80000e62 1 14 fcn.80000e62 +0x80000d0c 1 14 fcn.80000d0c +0x80000d44 2 10 fcn.80000d44 +0x80000096 1 10 fcn.80000096 +0x800000c8 1 14 fcn.800000c8 +0x8000008c 1 10 fcn.8000008c +0x8000007e 1 14 fcn.8000007e +0x8000030a 1 16 fcn.8000030a +0x800005b6 1 16 fcn.800005b6 +0x8000056e 6 56 -> 54 fcn.8000056e +0x800005d6 3 20 -> 12 fcn.800005d6 +0x80000556 3 24 -> 16 fcn.80000556 +0x800011a6 3 28 fcn.800011a6 +0x80000542 1 10 fcn.80000542 +0x80000518 1 16 fcn.80000518 +0x800004b8 1 22 fcn.800004b8 +0x800006bc 1 30 fcn.800006bc +0x80000528 1 16 fcn.80000528 +0x800004f4 1 10 fcn.800004f4 +0x800004fe 1 10 fcn.800004fe +0x80000538 1 10 fcn.80000538 +0x800005ea 5 40 -> 32 fcn.800005ea +0x80000612 1 10 fcn.80000612 +0x8000054c 2 10 fcn.8000054c +0x80000c98 2 74 fcn.80000c98 +0x8000061c 6 160 -> 158 fcn.8000061c +0x80000e54 1 14 fcn.80000e54 +0x80000e08 3 34 fcn.80000e08 +0x80000d38 1 12 fcn.80000d38 +0x80000df0 1 14 fcn.80000df0 +0x80000e70 3 34 loc.80000e70 +0x80000508 1 16 fcn.80000508 +0x800005c6 1 8 fcn.800005c6 +0x800004ce 1 18 fcn.800004ce +0x800004e0 1 10 fcn.800004e0 +0x800005a6 1 16 fcn.800005a6 +0x800004ea 1 10 fcn.800004ea +0x800005ce 1 8 fcn.800005ce +0x80000d1a 1 8 fcn.80000d1a +0x80000db4 1 8 fcn.80000db4 +0x80000ddc 2 20 fcn.80000ddc +0x80000d7a 3 58 fcn.80000d7a +0x80000dbc 3 32 fcn.80000dbc +0x80001008 2 34 fcn.80001008 +0x8000104e 1 18 fcn.8000104e +0x8000103c 1 10 fcn.8000103c +0x8000102a 2 18 fcn.8000102a +0x80000fc2 1 16 fcn.80000fc2 +0x80001046 1 8 fcn.80001046 +0x80000fee 1 26 fcn.80000fee +0x80001064 1 14 fcn.80001064 +0x80001072 1 14 fcn.80001072 +0x80000fe0 1 14 fcn.80000fe0 +0x80000fd2 1 14 fcn.80000fd2 +0x8000132c 1 68 fcn.8000132c +0x800012fe 1 46 fcn.800012fe +0x800000b0 1 8 fcn.800000b0 +0x80001080 1 28 fcn.80001080 +0x80001162 1 6 fcn.80001162 +0x8000109c 1 26 fcn.8000109c +0x80001168 1 6 fcn.80001168 +0x80001060 1 4 fcn.80001060 +0x800011d2 1 12 loc.800011d2 +0x800011de 10 90 fcn.800011de +0x800010d4 1 28 fcn.800010d4 +0x800010b6 1 30 fcn.800010b6 +0x800000b8 1 14 fcn.800000b8 +0x800000a0 1 16 fcn.800000a0 +0x80000790 48 1288 -> 1020 fcn.80000790 +0x8000116e 2 56 fcn.8000116e +0x80000e2a 1 16 fcn.80000e2a +0x80000e3a 1 12 fcn.80000e3a +0x80000286 1 14 fcn.80000286 +0x80000294 5 118 -> 102 fcn.80000294 +0x80000060 1 30 fcn.80000060 +0x80000020 1 64 fcn.80000020 +0x80000200 11 134 fcn.80000200 +0x8030010c 1 16 fcn.8030010c +0x800010f0 6 114 -> 112 fcn.800010f0 + ; CODE XREF from fcn.80000020 @ 0x8000005c + ;-- section..text.Bsp.waitTime: + ;-- segment.LOAD13: +|- (loc) fcn.80000200(); +| 0x80000200 fcall #0x8000008c ; fcn.8000008c ; [77] -r-x section size 134 named .text.Bsp.waitTime +| 0x80000204 ne d15, d4, d0 +| 0x80000208 or.ne d15, d5, d1 +| ,=< 0x8000020c jnz d15, #0x80000218 +| | 0x8000020e fcall #0x80000096 ; fcn.80000096 +| | 0x80000212 ld.d e2, [a15]#0 +| ,==< 0x80000216 j #0x80000244 +| |`-> 0x80000218 mfcr d15, #0xfe2c +| | 0x8000021c extr.u d15, d15, #0xf, #1 +| | 0x80000220 ne d15, d15, #0 +| | 0x80000224 disable +| | 0x80000228 nop +| | 0x8000022a fcall #0x8000007e ; fcn.8000007e +| | 0x8000022e ld.d e2, [a15]#0 +| | 0x80000232 and d0, d2 +| | 0x80000234 and d1, d3 +| |,=< 0x80000236 jz d15, #0x8000023c +| || 0x80000238 enable +| |`-> 0x8000023c addx d2, d0, d4 +| | 0x80000240 addc d3, d1, d5 +| | ; CODE XREF from fcn.80000200 @ 0x80000216 +| `.-> 0x80000244 fcall #0x8000008c ; fcn.8000008c +| : 0x80000248 ne d15, d2, d0 +| : 0x8000024c or.ne d15, d3, d1 +| ,==< 0x80000250 jz d15, #0x80000282 +| |: 0x80000252 mfcr d15, #0xfe2c +| |: 0x80000256 extr.u d15, d15, #0xf, #1 +| |: 0x8000025a ne d15, d15, #0 +| |: 0x8000025e disable +| |: 0x80000262 nop +| |: 0x80000264 fcall #0x8000007e ; fcn.8000007e +| |: 0x80000268 ld.d e4, [a15]#0 +| |: 0x8000026c and d0, d4 +| |: 0x8000026e and d1, d5 +| ,===< 0x80000270 jz d15, #0x80000276 +| ||: 0x80000272 enable +| `---> 0x80000276 ge.u d15, d0, d2 +| |: 0x8000027a and.eq d15, d1, d3 +| |: 0x8000027e or.lt d15, d3, d1 +| ``=< 0x80000282 jz d15, #0x80000244 +\ 0x80000284 ret +EOF +RUN + +NAME=tricore analysis graph +FILE=bins/elf/float_ex1/float_ex1_tricore_gcc +CMDS=< 0x800004f2 mov d15, #0 +| |,=< 0x800004f4 j #0x8000054c +| `--> 0x800004f6 mov d4, #0x14 +| | 0x800004fa call #0x80000afc +| | 0x800004fe mov.aa a15, a2 +| | 0x80000500 mov.d d15, a15 +| | 0x80000502 ld.a a15, [a14]#-0x18 +| | 0x80000506 st.w [a15]#0, d15 +| | 0x80000508 ld.a a15, [a14]#-0x18 +| | 0x8000050c ld.a a15, [a15]#0 +| | 0x8000050e ld.w d15, [a14]#-4 +| | 0x80000512 st.w [a15]#0, d15 +| | 0x80000514 ld.a a15, [a14]#-0x18 +| | 0x80000518 nop +| | 0x8000051a ld.w d15, [a15]#0 +| | 0x8000051c mov.a a15, d15 +| | 0x8000051e add.a a15, #4 +| | 0x80000520 mov d4, #5 +| | 0x80000522 ld.a a5, [a14]#-8 +| | 0x80000526 mov.aa a4, a15 +| | 0x80000528 call #0x800011e0 +| | 0x8000052c ld.a a15, [a14]#-0x18 +| | 0x80000530 ld.a a15, [a15]#0 +| | 0x80000532 ld.d e4, [a14]#-0x10 +| | 0x80000536 call #0x80000728 +| | 0x8000053a mov d15, d2 +| | 0x8000053c st.w [a15]#0xc, d15 +| | 0x8000053e ld.a a15, [a14]#-0x18 +| | 0x80000542 ld.a a15, [a15]#0 +| | 0x80000544 ld.w d15, [a14]#-0x14 +| | 0x80000548 st.w [a15]#0x10, d15 +| | 0x8000054a mov d15, #1 +| `-> 0x8000054c mov d2, d15 +\ 0x8000054e ret EOF RUN @@ -1139,11 +1152,12 @@ EXPECT=<> (var _flags) (bv 8 0x2) false)) (set pf (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x2) false)) (set af (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x2) false)) (set zf (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x1) false)) (set sf (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x1) false)) (set tf (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x1) false)) (set if (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x1) false)) (set df (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x1) false)) (set of (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x3) false)) (set nt (lsb (var _flags))) (set sp (+ (var sp) (bv 16 0x2)))) diff --git a/test/db/asm/x86_32 b/test/db/asm/x86_32 index b383c9046a7..93e71810924 100644 --- a/test/db/asm/x86_32 +++ b/test/db/asm/x86_32 @@ -242,7 +242,7 @@ d "lodsd eax, dword [si]" 67ad 0x0 (seq (set eax (loadw 0 32 (+ (+ (cast 32 fals d "loop 3" 66e200 0x0 (seq (set ecx (- (var ecx) (bv 32 0x1))) (branch (! (is_zero (var ecx))) (jmp (bv 32 0x6)) nop)) d "loope 3" 66e100 0x0 (seq (set ecx (- (var ecx) (bv 32 0x1))) (branch (&& (! (is_zero (var ecx))) (var zf)) (jmp (bv 32 0x6)) nop)) d "loopne 3" 66e000 0x0 (seq (set ecx (- (var ecx) (bv 32 0x1))) (branch (&& (! (is_zero (var ecx))) (! (var zf))) (jmp (bv 32 0x6)) nop)) -d "lsl eax, dword [eax]" 0f0300 +dB "lsl eax, dword [eax]" 0f0300 d "ltr ax" 0f00d8 d "ltr word [eax]" 0f0018 d "lzcnt eax, dword [eax]" f30fbd00 diff --git a/test/db/asm/x86_64 b/test/db/asm/x86_64 index 642ebc08b9e..21be1bfa8c1 100644 --- a/test/db/asm/x86_64 +++ b/test/db/asm/x86_64 @@ -1004,12 +1004,12 @@ a "bswap r15d" 410fcf ad "endbr64" f30f1efa d "enter 8, 0" c8080000 0x0 (seq (set _alloc_sz (cast 16 false (bv 64 0x8))) (set _nest_lvl (mod (cast 8 false (bv 64 0x0)) (bv 8 0x20))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (var rbp))) (set rsp (var final)) (set _frame_tmp (var rsp)) (branch (is_zero (var _nest_lvl)) nop (seq (branch (! (ule (var _nest_lvl) (bv 8 0x1))) (seq (set _itr (bv 8 0x1)) (repeat (&& (ule (var _itr) (var _nest_lvl)) (! (== (var _itr) (var _nest_lvl)))) (seq (set rbp (- (var rbp) (bv 64 0x8))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (loadw 0 64 (var rbp)))) (set rsp (var final)) (set _itr (+ (var _itr) (bv 8 0x1)))))) nop) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (var _frame_tmp))) (set rsp (var final)))) (set rsp (- (var rsp) (cast 64 false (var _alloc_sz)))) (set rbp (var _frame_tmp))) d "enter 8, 0" 66c8080000 0x0 (seq (set _alloc_sz (cast 16 false (bv 32 0x8))) (set _nest_lvl (mod (cast 8 false (bv 32 0x0)) (bv 8 0x20))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (cast 32 false (var rbp)))) (set rsp (var final)) (set _frame_tmp (var rsp)) (branch (is_zero (var _nest_lvl)) nop (seq (branch (! (ule (var _nest_lvl) (bv 8 0x1))) (seq (set _itr (bv 8 0x1)) (repeat (&& (ule (var _itr) (var _nest_lvl)) (! (== (var _itr) (var _nest_lvl)))) (seq (set rbp (- (var rbp) (bv 64 0x4))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (loadw 0 32 (var rbp)))) (set rsp (var final)) (set _itr (+ (var _itr) (bv 8 0x1)))))) nop) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (var _frame_tmp))) (set rsp (var final)))) (set rsp (- (var rsp) (cast 64 false (var _alloc_sz)))) (set rbp (cast 64 false (var _frame_tmp)))) -ad "xchg eax, r8d" 4190 0x0 (seq (set _temp (cast 32 false (var rax))) (set rax (cast 64 false (cast 32 false (var r8)))) (set r8 (cast 64 false (var _temp)))) -a "xchg r8d, eax" 4190 0x0 (seq (set _temp (cast 32 false (var rax))) (set rax (cast 64 false (cast 32 false (var r8)))) (set r8 (cast 64 false (var _temp)))) -ad "xchg rax, rdx" 4892 0x0 (seq (set _temp (var rax)) (set rax (var rdx)) (set rdx (var _temp))) -a "xchg rdx, rax" 4892 0x0 (seq (set _temp (var rax)) (set rax (var rdx)) (set rdx (var _temp))) -ad "xchg rax, r8" 4990 0x0 (seq (set _temp (var rax)) (set rax (var r8)) (set r8 (cast 64 false (var _temp)))) -a "xchg r8, rax" 4990 0x0 (seq (set _temp (var rax)) (set rax (var r8)) (set r8 (cast 64 false (var _temp)))) +adB "xchg eax, r8d" 4190 0x0 (seq (set _temp (cast 32 false (var rax))) (set rax (cast 64 false (cast 32 false (var r8)))) (set r8 (cast 64 false (var _temp)))) +aB "xchg r8d, eax" 4190 0x0 (seq (set _temp (cast 32 false (var rax))) (set rax (cast 64 false (cast 32 false (var r8)))) (set r8 (cast 64 false (var _temp)))) +adB "xchg rax, rdx" 4892 0x0 (seq (set _temp (var rax)) (set rax (var rdx)) (set rdx (var _temp))) +aB "xchg rdx, rax" 4892 0x0 (seq (set _temp (var rax)) (set rax (var rdx)) (set rdx (var _temp))) +adB "xchg rax, r8" 4990 0x0 (seq (set _temp (var rax)) (set rax (var r8)) (set r8 (cast 64 false (var _temp)))) +aB "xchg r8, rax" 4990 0x0 (seq (set _temp (var rax)) (set rax (var r8)) (set r8 (cast 64 false (var _temp)))) ad "xchg rdx, rbx" 4887da 0x0 (seq (set _temp (var rdx)) (set rdx (var rbx)) (set rbx (var _temp))) ad "xchg rbx, rdx" 4887d3 0x0 (seq (set _temp (var rbx)) (set rbx (var rdx)) (set rdx (var _temp))) ad "xchg r8, r15" 4d87f8 0x0 (seq (set _temp (var r8)) (set r8 (cast 64 false (var r15))) (set r15 (cast 64 false (var _temp)))) diff --git a/test/db/cmd/cmd_a8 b/test/db/cmd/cmd_a8 index fde1b35af54..1ea5ccaa988 100644 --- a/test/db/cmd/cmd_a8 +++ b/test/db/cmd/cmd_a8 @@ -18,6 +18,6 @@ e asm.bits=64 a8j c745f400000000 EOF EXPECT=<>,<<,36,+,0xffffffff,&,[4],0xffffffff,&,ip,= -[{"opcode":"ldr ip, [pc, 0x24]","disasm":"ldr ip, sym.__libc_csu_fini","pseudo":"ip = sym.__libc_csu_fini","description":"load from memory to register","mnemonic":"ldr","mask":"ffffffff","esil":"2,2,8,$$,+,>>,<<,36,+,0xffffffff,&,[4],0xffffffff,&,ip,=","rzil":{"opcode":"set","dst":"r12","src":{"opcode":"loadw","mem":0,"key":{"opcode":"bitv","bits":"0x817c","len":32},"bits":32}},"sign":false,"prefix":0,"id":75,"opex":{"operands":[{"type":"reg","value":"ip"},{"type":"mem","base":"pc","scale":1,"disp":36}]},"addr":33104,"bytes":"24c09fe5","disp":36,"ptr":33148,"size":4,"type":"load","esilcost":4,"ireg":"pc","scale":1,"refptr":4,"cycles":4,"failcycles":0,"delay":0,"stackptr":0,"family":"cpu"}] +[{"opcode":"ldr ip, [pc, 0x24]","disasm":"ldr ip, sym.__libc_csu_fini","pseudo":"ip = sym.__libc_csu_fini","description":"load from memory to register","mnemonic":"ldr","mask":"ffffffff","esil":"2,2,8,$$,+,>>,<<,36,+,0xffffffff,&,[4],0xffffffff,&,ip,=","rzil":{"opcode":"set","dst":"r12","src":{"opcode":"loadw","mem":0,"key":{"opcode":"bitv","bits":"0x817c","len":32},"bits":32}},"sign":false,"prefix":0,"id":83,"opex":{"operands":[{"type":"reg","value":"ip"},{"type":"mem","base":"pc","scale":1,"disp":36}]},"addr":33104,"bytes":"24c09fe5","disp":36,"ptr":33148,"size":4,"type":"load","esilcost":4,"ireg":"pc","scale":1,"refptr":4,"cycles":4,"failcycles":0,"delay":0,"stackptr":0,"family":"cpu"}] EOF RUN \ No newline at end of file diff --git a/test/db/cmd/cmd_ao b/test/db/cmd/cmd_ao index ca877ffc6cb..ef479373391 100644 --- a/test/db/cmd/cmd_ao +++ b/test/db/cmd/cmd_ao @@ -134,10 +134,10 @@ aam 3 cmova conditional move - above/not below nor equal (cf=0 and zf=0) cmovae conditional move - above or equal/not below/not carry (cf=0) +movabs absolute data moves movapd move aligned packed double-fp values movaps move aligned packed single-fp values vmovapd move aligned packed double-precision floating-point values vmovaps move aligned packed single-precision floating-point values -movabs absolute data moves EOF RUN diff --git a/test/db/cmd/cmd_list b/test/db/cmd/cmd_list index 17440ea560a..565bc213b11 100644 --- a/test/db/cmd/cmd_list +++ b/test/db/cmd/cmd_list @@ -436,6 +436,8 @@ a___ 16 32 64 x86.nasm LGPL3 X86 nasm assembler a___ 16 32 64 x86.nz LGPL3 x86 handmade assembler _dA_ 16 xap PD XAP4 RISC (CSR) _dA_ 32 xcore BSD Capstone XCore disassembler (by pancake) +_dAe 32 64 riscv.cs BSD Capstone RISCV disassembler +_dA_ 32 tricore BSD Siemens TriCore CPU (by billow) _dA_ 16 32 arc GPL3 Argonaut RISC Core _dA_ 32 cris GPL3 Axis Communications 32-bit embedded processor (by pancake) _d__ 32 hppa GPL3 HP PA-RISC @@ -444,7 +446,6 @@ adAe 32 64 mips.gnu GPL3 MIPS CPU _dA_ 32 nios2 GPL3 NIOS II Embedded Processor _dAe 32 64 riscv GPL3 RISC-V _dA_ 32 64 sparc.gnu GPL3 Scalable Processor Architecture -_dA_ 32 tricore GPL3 Siemens TriCore CPU _dA_ 8 32 vax GPL3 VAX _dAe 32 xtensa GPL3 XTensa CPU adA_ 8 z80 GPL3 Zilog Z80 (by condret) @@ -508,6 +509,8 @@ x86.nasm x86.nz xap xcore +riscv.cs +tricore arc cris hppa @@ -516,7 +519,6 @@ mips.gnu nios2 riscv sparc.gnu -tricore vax xtensa z80 @@ -527,7 +529,7 @@ NAME=Print the asm/analysis plugins in JSON FILE== CMDS=Laj EXPECT=<