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Fix many many mem leaks.
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@Rot127
Rot127 committed Nov 29, 2023
1 parent 37c3e04 commit 8f18e32
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Showing 4 changed files with 43 additions and 40 deletions.
33 changes: 17 additions & 16 deletions librz/analysis/arch/hexagon/hexagon_il.c
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Original file line number Diff line number Diff line change
Expand Up @@ -195,6 +195,7 @@ static RZ_OWN RzILOpEffect *hex_pkt_to_il_seq(HexPkt *pkt) {
rz_return_val_if_fail(pkt && pkt->il_ops, NULL);

if (rz_vector_len(pkt->il_ops) == 1) {
rz_vector_clear(pkt->il_ops);
// We need at least the instruction op and the packet commit.
// So if there aren't at least two ops something went wrong.
RZ_LOG_WARN("Invalid il ops sequence! There should be at least two il ops per packet.\n");
Expand Down Expand Up @@ -418,40 +419,40 @@ static void log_reg_read(RZ_BORROW HexPkt *pkt, ut8 reg_num, HexRegClass reg_cla
case HEX_REG_CLASS_DOUBLE_REGS:
case HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS:
if (tmp_reg) {
pkt->il_op_stats.gpr_tmp_read |= (1 << (reg_num + 1));
pkt->il_op_stats.gpr_tmp_read |= (1ULL << (reg_num + 1));
} else {
pkt->il_op_stats.gpr_read |= (1 << (reg_num + 1));
pkt->il_op_stats.gpr_read |= (1ULL << (reg_num + 1));
}
// fallthrough
case HEX_REG_CLASS_INT_REGS:
case HEX_REG_CLASS_INT_REGS_LOW8:
case HEX_REG_CLASS_GENERAL_SUB_REGS:
if (tmp_reg) {
pkt->il_op_stats.gpr_tmp_read |= (1 << reg_num);
pkt->il_op_stats.gpr_tmp_read |= (1ULL << reg_num);
} else {
pkt->il_op_stats.gpr_read |= (1 << reg_num);
pkt->il_op_stats.gpr_read |= (1ULL << reg_num);
}
break;
case HEX_REG_CLASS_CTR_REGS64:
if (tmp_reg) {
pkt->il_op_stats.ctr_tmp_read |= (1 << (reg_num + 1));
pkt->il_op_stats.ctr_tmp_read |= (1ULL << (reg_num + 1));
} else {
pkt->il_op_stats.ctr_read |= (1 << (reg_num + 1));
pkt->il_op_stats.ctr_read |= (1ULL << (reg_num + 1));
}
// fallthrough
case HEX_REG_CLASS_MOD_REGS:
case HEX_REG_CLASS_CTR_REGS:
if (tmp_reg) {
pkt->il_op_stats.ctr_tmp_read |= (1 << reg_num);
pkt->il_op_stats.ctr_tmp_read |= (1ULL << reg_num);
} else {
pkt->il_op_stats.ctr_read |= (1 << reg_num);
pkt->il_op_stats.ctr_read |= (1ULL << reg_num);
}
break;
case HEX_REG_CLASS_PRED_REGS:
if (tmp_reg) {
pkt->il_op_stats.pred_tmp_read |= (1 << reg_num);
pkt->il_op_stats.pred_tmp_read |= (1ULL << reg_num);
} else {
pkt->il_op_stats.pred_read |= (1 << reg_num);
pkt->il_op_stats.pred_read |= (1ULL << reg_num);
}
break;
}
Expand All @@ -478,26 +479,26 @@ static void log_reg_write(RZ_BORROW HexInsnPktBundle *bundle, ut8 reg_num, HexRe
break;
case HEX_REG_CLASS_DOUBLE_REGS:
case HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS:
pkt->il_op_stats.gpr_written |= (1 << (reg_num + 1));
pkt->il_op_stats.gpr_written |= (1ULL << (reg_num + 1));
// fallthrough
case HEX_REG_CLASS_INT_REGS:
case HEX_REG_CLASS_INT_REGS_LOW8:
case HEX_REG_CLASS_GENERAL_SUB_REGS:
pkt->il_op_stats.gpr_written |= (1 << reg_num);
pkt->il_op_stats.gpr_written |= (1ULL << reg_num);
break;
case HEX_REG_CLASS_CTR_REGS64:
if (hex_ctr_immut_masks[reg_num + 1] != HEX_IMMUTABLE_REG) {
pkt->il_op_stats.ctr_written |= (1 << (reg_num + 1));
pkt->il_op_stats.ctr_written |= (1ULL << (reg_num + 1));
}
// fallthrough
case HEX_REG_CLASS_MOD_REGS:
case HEX_REG_CLASS_CTR_REGS:
if (hex_ctr_immut_masks[reg_num] != HEX_IMMUTABLE_REG) {
pkt->il_op_stats.ctr_written |= (1 << reg_num);
pkt->il_op_stats.ctr_written |= (1ULL << reg_num);
}
break;
case HEX_REG_CLASS_PRED_REGS:
pkt->il_op_stats.pred_written |= (1 << reg_num);
pkt->il_op_stats.pred_written |= (1ULL << reg_num);
if (bundle->insn) {
log_pred_write_slot(bundle, reg_num);
}
Expand Down Expand Up @@ -818,7 +819,7 @@ RZ_IPI RZ_OWN RzILOpEffect *hex_cancel_slot(RZ_BORROW HexPkt *pkt, ut8 slot) {
rz_warn_if_reached();
RZ_LOG_WARN("Slot %d does not exist!", slot);
}
pkt->il_op_stats.slot_cancelled |= (1 << slot);
pkt->il_op_stats.slot_cancelled |= (1ULL << slot);
return EMPTY();
}

Expand Down
43 changes: 23 additions & 20 deletions librz/asm/arch/hexagon/hexagon_arch.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,11 @@
#include <rz_analysis.h>
#include <rz_util.h>
#include <rz_vector.h>
#include <string.h>
#include "hexagon.h"
#include "hexagon_insn.h"
#include "rz_list.h"
#include "rz_util/rz_strbuf.h"
#include "hexagon_arch.h"

static inline bool is_last_instr(const ut8 parse_bits) {
Expand Down Expand Up @@ -234,6 +237,7 @@ static HexPkt *hex_get_stale_pkt(HexState *state) {
stale_state_pkt = &state->pkts[i];
}
}
hex_clear_pkt(stale_state_pkt);
return stale_state_pkt;
}

Expand Down Expand Up @@ -275,30 +279,23 @@ RZ_API void hex_insn_free(RZ_NULLABLE HexInsn *i) {
* \param i The instruction container to be freed.
*/
RZ_API void hex_insn_container_free(RZ_NULLABLE HexInsnContainer *c) {
if (c && c->is_duplex) {
if (c) {
// bin is a uninion. Just free all of them.
hex_insn_free(c->bin.sub[0]);
hex_insn_free(c->bin.sub[1]);
} else if (c) {
hex_insn_free(c->bin.insn);
}
free(c);
}

/**
* \brief Copies one instruction container to another.
* \brief Moves one instruction container to another.
*
* \param dest The destination insruction container.
* \param src The source instruction container.
*/
RZ_API void hex_copy_insn_container(RZ_OUT HexInsnContainer *dest, const HexInsnContainer *src) {
RZ_API void hex_move_insn_container(RZ_OUT HexInsnContainer *dest, const HexInsnContainer *src) {
rz_return_if_fail(dest && src);
memcpy(dest, src, sizeof(HexInsnContainer));
if (src->is_duplex) {
memcpy(dest->bin.sub[0], src->bin.sub[0], sizeof(HexInsn));
memcpy(dest->bin.sub[1], src->bin.sub[1], sizeof(HexInsn));
} else {
memcpy(dest->bin.insn, src->bin.insn, sizeof(HexInsn));
}
memmove(dest, src, sizeof(HexInsnContainer));
}

/**
Expand Down Expand Up @@ -695,7 +692,8 @@ static HexInsnContainer *hex_add_to_pkt(HexState *state, const HexInsnContainer
RZ_LOG_FATAL("Instruction could not be set! A packet can only hold four instructions but k=%d.", k);
}
HexInsnContainer *hic = hexagon_alloc_instr_container();
hex_copy_insn_container(hic, new_hic);
hex_move_insn_container(hic, new_hic);
rz_list_del_n(pkt->bin, k);
rz_list_insert(pkt->bin, k, hic);

if (k == 0) {
Expand Down Expand Up @@ -728,7 +726,8 @@ static HexInsnContainer *hex_to_new_pkt(HexState *state, const HexInsnContainer
hex_clear_pkt(new_pkt);

HexInsnContainer *hic = hexagon_alloc_instr_container();
hex_copy_insn_container(hic, new_hic);
hex_move_insn_container(hic, new_hic);
rz_list_del_n(new_pkt->bin, 0);
rz_list_insert(new_pkt->bin, 0, hic);

new_pkt->last_instr_present |= is_last_instr(hic->parse_bits);
Expand Down Expand Up @@ -756,7 +755,7 @@ static HexInsnContainer *hex_add_to_stale_pkt(HexState *state, const HexInsnCont
hex_clear_pkt(pkt);

HexInsnContainer *hic = hexagon_alloc_instr_container();
hex_copy_insn_container(hic, new_hic);
hex_move_insn_container(hic, new_hic);
rz_list_insert(pkt->bin, 0, hic);

pkt->last_instr_present |= is_last_instr(hic->parse_bits);
Expand Down Expand Up @@ -843,6 +842,7 @@ static void print_state_pkt(const HexState *state, st32 index, HexBufferAction a
RZ_LOG_DEBUG("╰─────┴──────────────┴─────┴──────────────────┴───┴───┴───┴───╯\n");
}
}
rz_strbuf_free(pkt_line);
#endif
}

Expand Down Expand Up @@ -924,11 +924,10 @@ static HexInsnContainer *hex_add_hic_to_state(HexState *state, const HexInsnCont
HexInsnContainer *result_hic = hex_to_new_pkt(state, new_hic, p, &state->pkts[ni]);
print_state_pkt(state, ni, HEX_BUF_NEW, result_hic);
return result_hic;
} else {
HexInsnContainer *result_hic = hex_add_to_stale_pkt(state, new_hic);
print_state_pkt(state, -1, HEX_BUF_STALE, result_hic);
return result_hic;
}
HexInsnContainer *result_hic = hex_add_to_stale_pkt(state, new_hic);
print_state_pkt(state, -1, HEX_BUF_STALE, result_hic);
return result_hic;
}

/**
Expand Down Expand Up @@ -961,7 +960,11 @@ static void setup_new_hic(HexInsnContainer *hic, const HexReversedOpcode *rz_rev

hic->asm_op.size = 4;
hic->ana_op.size = 4;

hic->bin.sub[0] = NULL;
hic->bin.sub[1] = NULL;
if (parse_bits == 0b00) {
hic->is_duplex = true;
hic->bin.sub[0] = hexagon_alloc_instr();
hic->bin.sub[1] = hexagon_alloc_instr();
} else {
Expand Down Expand Up @@ -1102,4 +1105,4 @@ RZ_API void hexagon_reverse_opcode(const RzAsm *rz_asm, HexReversedOpcode *rz_re
if (copy_result) {
copy_asm_ana_ops(state, rz_reverse, hic);
}
}
}
4 changes: 2 additions & 2 deletions librz/asm/arch/hexagon/hexagon_arch.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,8 +80,8 @@ RZ_API HexLoopAttr hex_get_loop_flag(const HexPkt *p);
RZ_API const HexOp *hex_isa_to_reg(const HexInsn *hi, const char isa_id, bool new_reg);
RZ_API ut64 hex_isa_to_imm(const HexInsn *hi, const char isa_id);
void hex_set_hic_text(RZ_INOUT HexInsnContainer *hic);
RZ_API void hex_copy_insn_container(RZ_OUT HexInsnContainer *dest, const HexInsnContainer *src);
RZ_API void hex_move_insn_container(RZ_OUT HexInsnContainer *dest, const HexInsnContainer *src);
RZ_API HexPkt *hex_get_pkt(RZ_BORROW HexState *state, const ut32 addr);
RZ_API HexInsnContainer *hex_get_hic_at_addr(HexState *state, const ut32 addr);
RZ_API const HexOp hex_nreg_to_op(const HexInsnPktBundle *bundle, const char isa_id);
#endif
#endif
3 changes: 1 addition & 2 deletions librz/asm/arch/hexagon/hexagon_disas.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34158,6 +34158,7 @@ static void hex_disasm_with_templates(const HexInsnTemplate *tpl, HexState *stat
rz_strbuf_append_n(&sb, tpl->syntax + syntax_cur, syntax_len - syntax_cur);
}
strncpy(hi->text_infix, rz_strbuf_get(&sb), sizeof(hi->text_infix) - 1);
rz_strbuf_fini(&sb);

// RzAnalysisOp contents
hic->ana_op.addr = hic->addr;
Expand Down Expand Up @@ -34294,8 +34295,6 @@ int hexagon_disasm_instruction(HexState *state, const ut32 hi_u32, RZ_INOUT HexI
}
if (hic->identifier == HEX_INS_INVALID_DECODE) {
hic->ana_op.type = RZ_ANALYSIS_OP_TYPE_ILL;
HexInsn *hi = hexagon_alloc_instr();
hic->bin.insn = hi;
snprintf(hic->bin.insn->text_infix, sizeof(hic->bin.insn->text_infix), "invalid");
}
hex_set_hic_text(hic);
Expand Down

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