diff --git a/librz/arch/isa/hexagon/hexagon.h b/librz/arch/isa/hexagon/hexagon.h
index 547f6b70fe2..35c907ed924 100644
--- a/librz/arch/isa/hexagon/hexagon.h
+++ b/librz/arch/isa/hexagon/hexagon.h
@@ -841,4 +841,4 @@ RZ_API const HexOp hex_alias_to_op(HexRegAlias alias, bool tmp_reg);
 RZ_API const char *hex_alias_to_reg_name(HexRegAlias alias, bool tmp_reg);
 RZ_API const HexOp hex_explicit_to_op(ut32 reg_num, HexRegClass reg_class, bool tmp_reg);
 
-#endif
\ No newline at end of file
+#endif
diff --git a/librz/arch/isa/hexagon/hexagon_il.c b/librz/arch/isa/hexagon/hexagon_il.c
index d138a387c48..6a98bc2d1ce 100644
--- a/librz/arch/isa/hexagon/hexagon_il.c
+++ b/librz/arch/isa/hexagon/hexagon_il.c
@@ -53,7 +53,7 @@ static HexILOp hex_endloop01_op = {
 /**
  * \brief Sends the IL op at \p start to the position \p newloc.
  *
- * Note: THis is a copy of the same function implemented by Qualcomm in QEMU.
+ * Note: This is a copy of the same function implemented by Qualcomm in QEMU.
  * See: https://gitlab.com/qemu-project/qemu/-/blob/master/target/hexagon/decode.c :: decode_send_insn_to
  *
  * \param ops The IL ops list.
@@ -61,10 +61,9 @@ static HexILOp hex_endloop01_op = {
  * \param newloc Position the op shall be moved to.
  */
 static void hex_send_insn_to_i(RzPVector /*<HexILOp *>*/ *ops, ut8 start, ut8 newloc) {
-	rz_return_if_fail(ops);
+	rz_return_if_fail(ops && newloc < rz_pvector_len(ops));
 
 	st32 direction;
-	st32 i;
 	if (start == newloc) {
 		return;
 	}
@@ -75,9 +74,11 @@ static void hex_send_insn_to_i(RzPVector /*<HexILOp *>*/ *ops, ut8 start, ut8 ne
 		/* move towards beginning */
 		direction = -1;
 	}
-	for (i = start; i != newloc; i += direction) {
-		HexILOp *tmp_op = rz_pvector_assign_at(ops, i, (HexILOp *)rz_pvector_at(ops, i + direction));
-		rz_pvector_assign_at(ops, i + direction, tmp_op);
+	for (st32 i = start; i != newloc; i += direction) {
+		HexILOp *neighbor_op = (HexILOp *)rz_pvector_at(ops, i + direction);
+		HexILOp *to_move_op = (HexILOp *)rz_pvector_at(ops, i);
+		rz_pvector_set(ops, i, neighbor_op);
+		rz_pvector_set(ops, i + direction, to_move_op);
 	}
 }
 
diff --git a/librz/arch/isa/hexagon/il_ops/hexagon_il_non_insn_ops.c b/librz/arch/isa/hexagon/il_ops/hexagon_il_non_insn_ops.c
index ed2c2fed4be..919cc790200 100644
--- a/librz/arch/isa/hexagon/il_ops/hexagon_il_non_insn_ops.c
+++ b/librz/arch/isa/hexagon/il_ops/hexagon_il_non_insn_ops.c
@@ -950,7 +950,7 @@ RZ_IPI RZ_OWN RzILOpEffect *hex_commit_packet(HexInsnPktBundle *bundle) {
 }
 
 RZ_IPI RZ_OWN RzILOpEffect *hex_il_op_jump_flag_init(HexInsnPktBundle *bundle) {
-	return SETL("jump_flag", IL_FALSE);
+	return SEQ2(SETL("jump_flag", IL_FALSE), SETL("jump_target", U32(0xffffffff)));
 }
 
 RZ_IPI RZ_OWN RzILOpEffect *hex_il_op_next_pkt_jmp(HexInsnPktBundle *bundle) {