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Sync with lated generated files.
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@Rot127
Rot127 committed Mar 21, 2024
1 parent 911bb53 commit d7070eb
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Showing 52 changed files with 297 additions and 309 deletions.
2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/hexagon.c
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/hexagon.h
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/hexagon_arch.c
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/hexagon_arch.h
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/hexagon_disas.c
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/hexagon_dwarf_reg_num_table.inc
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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6 changes: 3 additions & 3 deletions librz/arch/isa/hexagon/hexagon_il.c
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
Expand Down Expand Up @@ -408,9 +408,9 @@ RZ_IPI RzILOpEffect *hex_get_il_op(const ut32 addr, const bool get_pkt_op) {
rz_pvector_push(p->il_ops, &hex_endloop01_op);
}

rz_pvector_push(p->il_ops, &hex_pkt_commit);
// Add a jump to the next packet.
rz_pvector_push(p->il_ops, &hex_next_jump_to_next_pkt);
rz_pvector_push(p->il_ops, &hex_pkt_commit);

check_for_jumps(p, &might_has_jumped);

Expand Down Expand Up @@ -864,7 +864,7 @@ RZ_IPI void hex_reset_il_pkt_stats(HexILExecData *stats) {
rz_bv_free(stats->ctr_tmp_read);
rz_bv_free(stats->gpr_tmp_read);
rz_bv_free(stats->pred_tmp_read);
stats->slot_cancelled = rz_bv_new(32);
stats->slot_cancelled = rz_bv_new(64);
stats->ctr_written = rz_bv_new(64);
stats->gpr_written = rz_bv_new(64);
stats->pred_written = rz_bv_new(32);
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/hexagon_il.h
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/hexagon_il_getter_table.h
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/hexagon_insn.h
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/hexagon_reg_tables.h
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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90 changes: 45 additions & 45 deletions librz/arch/isa/hexagon/il_ops/hexagon_il_A2_ops.c
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Expand Up @@ -3,7 +3,7 @@

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
Expand Down Expand Up @@ -6279,45 +6279,45 @@ RzILOpEffect *hex_il_op_a2_vcmpwgt(HexInsnPktBundle *bundle) {
RzILOpEffect *seq_44 = SEQN(2, op_ASSIGN_2, for_43);

// j = 0x4;
RzILOpEffect *op_ASSIGN_47 = SETL("j", SN(32, 4));
RzILOpEffect *op_ASSIGN_46 = SETL("j", SN(32, 4));

// HYB(++j);
RzILOpEffect *op_INC_50 = SETL("j", INC(VARL("j"), 32));
RzILOpEffect *op_INC_49 = SETL("j", INC(VARL("j"), 32));

// h_tmp71 = HYB(++j);
RzILOpEffect *op_ASSIGN_hybrid_tmp_52 = SETL("h_tmp71", VARL("j"));
RzILOpEffect *op_ASSIGN_hybrid_tmp_51 = SETL("h_tmp71", VARL("j"));

// seq(h_tmp71 = HYB(++j); HYB(++j));
RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_hybrid_tmp_52, op_INC_50);
RzILOpEffect *seq_52 = SEQN(2, op_ASSIGN_hybrid_tmp_51, op_INC_49);

// Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) | (((((st64) ((st32) ((Rss >> 0x20) & 0xffffffff))) > ((st64) ((st32) ((Rtt >> 0x20) & 0xffffffff)))) ? 0x1 : 0x0) << j)));
RzILOpPure *op_LSHIFT_55 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_56 = LOGNOT(op_LSHIFT_55);
RzILOpPure *op_AND_59 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_56);
RzILOpPure *op_RSHIFT_63 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_65 = LOGAND(op_RSHIFT_63, SN(64, 0xffffffff));
RzILOpPure *op_RSHIFT_71 = SHIFTRA(DUP(Rtt), SN(32, 0x20));
RzILOpPure *op_AND_73 = LOGAND(op_RSHIFT_71, SN(64, 0xffffffff));
RzILOpPure *op_GT_76 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_65), DUP(op_AND_65))), CAST(32, MSB(DUP(op_AND_65)), DUP(op_AND_65))), CAST(64, MSB(CAST(32, MSB(op_AND_73), DUP(op_AND_73))), CAST(32, MSB(DUP(op_AND_73)), DUP(op_AND_73))));
RzILOpPure *ite_cast_ut64_77 = ITE(op_GT_76, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_78 = SHIFTL0(ite_cast_ut64_77, VARL("j"));
RzILOpPure *op_OR_79 = LOGOR(op_AND_59, op_LSHIFT_78);
RzILOpEffect *op_ASSIGN_81 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_79));
RzILOpPure *op_LSHIFT_54 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_55 = LOGNOT(op_LSHIFT_54);
RzILOpPure *op_AND_58 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_55);
RzILOpPure *op_RSHIFT_62 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_64 = LOGAND(op_RSHIFT_62, SN(64, 0xffffffff));
RzILOpPure *op_RSHIFT_70 = SHIFTRA(DUP(Rtt), SN(32, 0x20));
RzILOpPure *op_AND_72 = LOGAND(op_RSHIFT_70, SN(64, 0xffffffff));
RzILOpPure *op_GT_75 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_64), DUP(op_AND_64))), CAST(32, MSB(DUP(op_AND_64)), DUP(op_AND_64))), CAST(64, MSB(CAST(32, MSB(op_AND_72), DUP(op_AND_72))), CAST(32, MSB(DUP(op_AND_72)), DUP(op_AND_72))));
RzILOpPure *ite_cast_ut64_76 = ITE(op_GT_75, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_77 = SHIFTL0(ite_cast_ut64_76, VARL("j"));
RzILOpPure *op_OR_78 = LOGOR(op_AND_58, op_LSHIFT_77);
RzILOpEffect *op_ASSIGN_80 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_78));

// seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) ...;
RzILOpEffect *seq_83 = op_ASSIGN_81;
RzILOpEffect *seq_82 = op_ASSIGN_80;

// seq(seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ...;
RzILOpEffect *seq_84 = SEQN(2, seq_83, seq_53);
RzILOpEffect *seq_83 = SEQN(2, seq_82, seq_52);

// while ((j <= 0x7)) { seq(seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ... };
RzILOpPure *op_LE_49 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_85 = REPEAT(op_LE_49, seq_84);
RzILOpPure *op_LE_48 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_84 = REPEAT(op_LE_48, seq_83);

// seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp71; Pd = ((st8) ( ...;
RzILOpEffect *seq_86 = SEQN(2, op_ASSIGN_47, for_85);
RzILOpEffect *seq_85 = SEQN(2, op_ASSIGN_46, for_84);

RzILOpEffect *instruction_sequence = SEQN(2, seq_44, seq_86);
RzILOpEffect *instruction_sequence = SEQN(2, seq_44, seq_85);
return instruction_sequence;
}

Expand Down Expand Up @@ -6373,45 +6373,45 @@ RzILOpEffect *hex_il_op_a2_vcmpwgtu(HexInsnPktBundle *bundle) {
RzILOpEffect *seq_44 = SEQN(2, op_ASSIGN_2, for_43);

// j = 0x4;
RzILOpEffect *op_ASSIGN_46 = SETL("j", SN(32, 4));
RzILOpEffect *op_ASSIGN_47 = SETL("j", SN(32, 4));

// HYB(++j);
RzILOpEffect *op_INC_49 = SETL("j", INC(VARL("j"), 32));
RzILOpEffect *op_INC_50 = SETL("j", INC(VARL("j"), 32));

// h_tmp73 = HYB(++j);
RzILOpEffect *op_ASSIGN_hybrid_tmp_51 = SETL("h_tmp73", VARL("j"));
RzILOpEffect *op_ASSIGN_hybrid_tmp_52 = SETL("h_tmp73", VARL("j"));

// seq(h_tmp73 = HYB(++j); HYB(++j));
RzILOpEffect *seq_52 = SEQN(2, op_ASSIGN_hybrid_tmp_51, op_INC_49);
RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_hybrid_tmp_52, op_INC_50);

// Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) | (((((ut64) ((ut32) ((Rss >> 0x20) & 0xffffffff))) > ((ut64) ((ut32) ((Rtt >> 0x20) & 0xffffffff)))) ? 0x1 : 0x0) << j)));
RzILOpPure *op_LSHIFT_54 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_55 = LOGNOT(op_LSHIFT_54);
RzILOpPure *op_AND_58 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_55);
RzILOpPure *op_RSHIFT_62 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_64 = LOGAND(op_RSHIFT_62, SN(64, 0xffffffff));
RzILOpPure *op_RSHIFT_70 = SHIFTRA(DUP(Rtt), SN(32, 0x20));
RzILOpPure *op_AND_72 = LOGAND(op_RSHIFT_70, SN(64, 0xffffffff));
RzILOpPure *op_GT_75 = UGT(CAST(64, IL_FALSE, CAST(32, IL_FALSE, op_AND_64)), CAST(64, IL_FALSE, CAST(32, IL_FALSE, op_AND_72)));
RzILOpPure *ite_cast_ut64_76 = ITE(op_GT_75, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_77 = SHIFTL0(ite_cast_ut64_76, VARL("j"));
RzILOpPure *op_OR_78 = LOGOR(op_AND_58, op_LSHIFT_77);
RzILOpEffect *op_ASSIGN_80 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_78));
RzILOpPure *op_LSHIFT_55 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_56 = LOGNOT(op_LSHIFT_55);
RzILOpPure *op_AND_59 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_56);
RzILOpPure *op_RSHIFT_63 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_65 = LOGAND(op_RSHIFT_63, SN(64, 0xffffffff));
RzILOpPure *op_RSHIFT_71 = SHIFTRA(DUP(Rtt), SN(32, 0x20));
RzILOpPure *op_AND_73 = LOGAND(op_RSHIFT_71, SN(64, 0xffffffff));
RzILOpPure *op_GT_76 = UGT(CAST(64, IL_FALSE, CAST(32, IL_FALSE, op_AND_65)), CAST(64, IL_FALSE, CAST(32, IL_FALSE, op_AND_73)));
RzILOpPure *ite_cast_ut64_77 = ITE(op_GT_76, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_78 = SHIFTL0(ite_cast_ut64_77, VARL("j"));
RzILOpPure *op_OR_79 = LOGOR(op_AND_59, op_LSHIFT_78);
RzILOpEffect *op_ASSIGN_81 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_79));

// seq(h_tmp73; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) ...;
RzILOpEffect *seq_82 = op_ASSIGN_80;
RzILOpEffect *seq_83 = op_ASSIGN_81;

// seq(seq(h_tmp73; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ...;
RzILOpEffect *seq_83 = SEQN(2, seq_82, seq_52);
RzILOpEffect *seq_84 = SEQN(2, seq_83, seq_53);

// while ((j <= 0x7)) { seq(seq(h_tmp73; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ... };
RzILOpPure *op_LE_48 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_84 = REPEAT(op_LE_48, seq_83);
RzILOpPure *op_LE_49 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_85 = REPEAT(op_LE_49, seq_84);

// seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp73; Pd = ((st8) ( ...;
RzILOpEffect *seq_85 = SEQN(2, op_ASSIGN_46, for_84);
RzILOpEffect *seq_86 = SEQN(2, op_ASSIGN_47, for_85);

RzILOpEffect *instruction_sequence = SEQN(2, seq_44, seq_85);
RzILOpEffect *instruction_sequence = SEQN(2, seq_44, seq_86);
return instruction_sequence;
}

Expand Down
42 changes: 21 additions & 21 deletions librz/arch/isa/hexagon/il_ops/hexagon_il_A4_ops.c
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Expand Up @@ -3,7 +3,7 @@

// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
Expand Down Expand Up @@ -2567,43 +2567,43 @@ RzILOpEffect *hex_il_op_a4_vcmpwgti(HexInsnPktBundle *bundle) {
RzILOpEffect *seq_38 = SEQN(2, op_ASSIGN_2, for_37);

// j = 0x4;
RzILOpEffect *op_ASSIGN_41 = SETL("j", SN(32, 4));
RzILOpEffect *op_ASSIGN_40 = SETL("j", SN(32, 4));

// HYB(++j);
RzILOpEffect *op_INC_44 = SETL("j", INC(VARL("j"), 32));
RzILOpEffect *op_INC_43 = SETL("j", INC(VARL("j"), 32));

// h_tmp136 = HYB(++j);
RzILOpEffect *op_ASSIGN_hybrid_tmp_46 = SETL("h_tmp136", VARL("j"));
RzILOpEffect *op_ASSIGN_hybrid_tmp_45 = SETL("h_tmp136", VARL("j"));

// seq(h_tmp136 = HYB(++j); HYB(++j));
RzILOpEffect *seq_47 = SEQN(2, op_ASSIGN_hybrid_tmp_46, op_INC_44);
RzILOpEffect *seq_46 = SEQN(2, op_ASSIGN_hybrid_tmp_45, op_INC_43);

// Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) | (((((st64) ((st32) ((Rss >> 0x20) & 0xffffffff))) > ((st64) s)) ? 0x1 : 0x0) << j)));
RzILOpPure *op_LSHIFT_49 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_50 = LOGNOT(op_LSHIFT_49);
RzILOpPure *op_AND_53 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_50);
RzILOpPure *op_RSHIFT_57 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_59 = LOGAND(op_RSHIFT_57, SN(64, 0xffffffff));
RzILOpPure *op_GT_63 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_59), DUP(op_AND_59))), CAST(32, MSB(DUP(op_AND_59)), DUP(op_AND_59))), CAST(64, MSB(VARL("s")), VARL("s")));
RzILOpPure *ite_cast_ut64_64 = ITE(op_GT_63, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_65 = SHIFTL0(ite_cast_ut64_64, VARL("j"));
RzILOpPure *op_OR_66 = LOGOR(op_AND_53, op_LSHIFT_65);
RzILOpEffect *op_ASSIGN_68 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_66));
RzILOpPure *op_LSHIFT_48 = SHIFTL0(UN(64, 1), VARL("j"));
RzILOpPure *op_NOT_49 = LOGNOT(op_LSHIFT_48);
RzILOpPure *op_AND_52 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_49);
RzILOpPure *op_RSHIFT_56 = SHIFTRA(DUP(Rss), SN(32, 0x20));
RzILOpPure *op_AND_58 = LOGAND(op_RSHIFT_56, SN(64, 0xffffffff));
RzILOpPure *op_GT_62 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_58), DUP(op_AND_58))), CAST(32, MSB(DUP(op_AND_58)), DUP(op_AND_58))), CAST(64, MSB(VARL("s")), VARL("s")));
RzILOpPure *ite_cast_ut64_63 = ITE(op_GT_62, UN(64, 1), UN(64, 0));
RzILOpPure *op_LSHIFT_64 = SHIFTL0(ite_cast_ut64_63, VARL("j"));
RzILOpPure *op_OR_65 = LOGOR(op_AND_52, op_LSHIFT_64);
RzILOpEffect *op_ASSIGN_67 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_65));

// seq(h_tmp136; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j)) ...;
RzILOpEffect *seq_70 = op_ASSIGN_68;
RzILOpEffect *seq_69 = op_ASSIGN_67;

// seq(seq(h_tmp136; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ...;
RzILOpEffect *seq_71 = SEQN(2, seq_70, seq_47);
RzILOpEffect *seq_70 = SEQN(2, seq_69, seq_46);

// while ((j <= 0x7)) { seq(seq(h_tmp136; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ... };
RzILOpPure *op_LE_43 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_72 = REPEAT(op_LE_43, seq_71);
RzILOpPure *op_LE_42 = SLE(VARL("j"), SN(32, 7));
RzILOpEffect *for_71 = REPEAT(op_LE_42, seq_70);

// seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp136; Pd = ((st8) ...;
RzILOpEffect *seq_73 = SEQN(2, op_ASSIGN_41, for_72);
RzILOpEffect *seq_72 = SEQN(2, op_ASSIGN_40, for_71);

RzILOpEffect *instruction_sequence = SEQN(3, imm_assign_25, seq_38, seq_73);
RzILOpEffect *instruction_sequence = SEQN(3, imm_assign_25, seq_38, seq_72);
return instruction_sequence;
}

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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/il_ops/hexagon_il_A5_ops.c
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/il_ops/hexagon_il_A6_ops.c
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/il_ops/hexagon_il_A7_ops.c
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/il_ops/hexagon_il_C2_ops.c
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/il_ops/hexagon_il_C4_ops.c
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/il_ops/hexagon_il_F2_ops.c
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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2 changes: 1 addition & 1 deletion librz/arch/isa/hexagon/il_ops/hexagon_il_G4_ops.c
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
// Date of code generation: 2024-03-16 00:50:15-05:00
// Date of code generation: 2024-03-16 06:22:39-05:00
//========================================
// The following code is generated.
// Do not edit. Repository of code generator:
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