diff --git a/librz/asm/arch/hexagon/hexagon.h b/librz/asm/arch/hexagon/hexagon.h index 5c38ad7f62e..dc567256093 100644 --- a/librz/asm/arch/hexagon/hexagon.h +++ b/librz/asm/arch/hexagon/hexagon.h @@ -137,6 +137,7 @@ typedef struct { char text_infix[128]; ///< Textual disassembly of the instruction. HexOp ops[HEX_MAX_OPERANDS]; ///< The operands of the instructions. HexILInsn il_insn; ///< RZIL instruction. These are not meant for execution! Use the packet ops for that. + ut8 slot; ///< The slot the instruction is located. } HexInsn; /** diff --git a/librz/asm/arch/hexagon/hexagon_arch.c b/librz/asm/arch/hexagon/hexagon_arch.c index e44cd4db009..8709c456917 100644 --- a/librz/asm/arch/hexagon/hexagon_arch.c +++ b/librz/asm/arch/hexagon/hexagon_arch.c @@ -567,6 +567,35 @@ RZ_API HexLoopAttr hex_get_loop_flag(const HexPkt *p) { } } +/** + * \brief Sets the given packet to valid and updates the packet information of + * each instruction in it. + * + * \param state The to operate on. + * \param pkt The packet to set to valid. + */ +static void make_packet_valid(RZ_BORROW HexState *state, RZ_BORROW HexPkt *pkt) { + rz_return_if_fail(state && pkt); + pkt->is_valid = true; + HexInsnContainer *hi = NULL; + RzListIter *it = NULL; + ut8 i = 0; + ut8 slot = 0; + rz_list_foreach (pkt->bin, it, hi) { + hex_set_pkt_info(&state->rz_asm, hi, pkt, i, true); + if (hi->is_duplex) { + hi->bin.sub[0]->slot = 0; + hi->bin.sub[1]->slot = 1; + slot = 2; + } else { + hi->bin.insn->slot = slot; + ++slot; + } + ++i; + } + pkt->last_access = rz_time_now(); +} + /** * \brief Sets the packet after \p pkt to valid and updates its textual assembly. * @@ -587,15 +616,7 @@ static void make_next_packet_valid(HexState *state, const HexPkt *pkt) { if (p->is_valid) { break; } - p->is_valid = true; - HexInsnContainer *hi = NULL; - RzListIter *it = NULL; - ut8 slot = 0; - rz_list_foreach (p->bin, it, hi) { - hex_set_pkt_info(&state->rz_asm, hi, p, slot, true); - ++slot; - } - p->last_access = rz_time_now(); + make_packet_valid(state, p); break; } }