diff --git a/librz/analysis/arch/arm/arm_esil64.c b/librz/analysis/arch/arm/arm_esil64.c
index 4760b64177b..3ecdf360fc1 100644
--- a/librz/analysis/arch/arm/arm_esil64.c
+++ b/librz/analysis/arch/arm/arm_esil64.c
@@ -1040,7 +1040,11 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
 			if (REGSIZE64(0) == 4) {
 				rz_strbuf_appendf(&op->esil, "%s,0xffffffff,^,%s,&=", REG64(1), REG64(0));
 			} else {
-				rz_strbuf_appendf(&op->esil, "%s,0xffffffffffffffff,^,%s,&=", REG64(1), REG64(0));
+				if (ISREG64(1)) {
+					rz_strbuf_appendf(&op->esil, "%s,0xffffffffffffffff,^,%s,&=", REG64(1), REG64(0));
+				} else {
+					rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",0xffffffffffffffff,^,%s,&=", IMM64(1), REG64(0));
+				}
 			}
 		} else {
 			if (REGSIZE64(0) == 4) {
diff --git a/test/db/esil/arm_64 b/test/db/esil/arm_64
index ec7995a6bae..8131d6b6c10 100644
--- a/test/db/esil/arm_64
+++ b/test/db/esil/arm_64
@@ -899,3 +899,16 @@ EXPECT=<<EOF
 x0 = 0x0000000000000005
 EOF
 RUN
+
+NAME=bic	v0.4s, #0, lsl #24
+FILE=malloc://0x200
+CMDS=<<EOF
+e asm.arch=arm
+e asm.bits=64
+wx 0x0074006f # bic	v0.4s, #0, lsl #24
+pie 1
+EOF
+EXPECT=<<EOF
+0x00000000 0x0,0xffffffffffffffff,^,q0,&=
+EOF
+RUN
\ No newline at end of file